arch/sh/drivers/dma/dma-sh.c

   1 /*
   2  * arch/sh/drivers/dma/dma-sh.c
   3  *
   4  * SuperH On-chip DMAC Support
   5  *
   6  * Copyright (C) 2000 Takashi YOSHII
   7  * Copyright (C) 2003, 2004 Paul Mundt
   8  * Copyright (C) 2005 Andriy Skulysh
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <asm/dreamcast/dma.h>
  18 #include <asm/dma.h>
  19 #include <asm/io.h>
  20 #include "dma-sh.h"
  21
  22
  23
  24 #ifdef CONFIG_CPU_SH4
  25 static struct ipr_data dmae_ipr_map[] = {
  26         { DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  27 };
  28 #endif
  29 static struct ipr_data dmte_ipr_map[] = {
  30         /*
  31          * Normally we could just do DMTE0_IRQ + chan outright, though in the
  32          * case of the 7751R, the DMTE IRQs for channels > 4 start right above
  33          * the SCIF
  34          */
  35         { DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  36         { DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  37         { DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  38         { DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  39         { DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  40         { DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  41         { DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  42         { DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
  43 };
  44
  45 static inline unsigned int get_dmte_irq(unsigned int chan)
  46 {
  47         unsigned int irq = 0;
  48         if (chan < ARRAY_SIZE(dmte_ipr_map))
  49                 irq = dmte_ipr_map[chan].irq;
  50         return irq;
  51 }
  52
  53 /*
  54  * We determine the correct shift size based off of the CHCR transmit size
  55  * for the given channel. Since we know that it will take:
  56  *
  57  *      info->count >> ts_shift[transmit_size]
  58  *
  59  * iterations to complete the transfer.
  60  */
  61 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
  62 {
  63         u32 chcr = ctrl_inl(CHCR[chan->chan]);
  64
  65         return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
  66 }
  67
  68 /*
  69  * The transfer end interrupt must read the chcr register to end the
  70  * hardware interrupt active condition.
  71  * Besides that it needs to waken any waiting process, which should handle
  72  * setting up the next transfer.
  73  */
  74 static irqreturn_t dma_tei(int irq, void *dev_id)
  75 {
  76         struct dma_channel *chan = dev_id;
  77         u32 chcr;
  78
  79         chcr = ctrl_inl(CHCR[chan->chan]);
  80
  81         if (!(chcr & CHCR_TE))
  82                 return IRQ_NONE;
  83
  84         chcr &= ~(CHCR_IE | CHCR_DE);
  85         ctrl_outl(chcr, CHCR[chan->chan]);
  86
  87         wake_up(&chan->wait_queue);
  88
  89         return IRQ_HANDLED;
  90 }
  91
  92 static int sh_dmac_request_dma(struct dma_channel *chan)
  93 {
  94         if (unlikely(!chan->flags & DMA_TEI_CAPABLE))
  95                 return 0;
  96
  97         chan->name = kzalloc(32, GFP_KERNEL);
  98         if (unlikely(chan->name == NULL))
  99                 return -ENOMEM;
 100         snprintf(chan->name, 32, "DMAC Transfer End (Channel %d)",
 101                  chan->chan);
 102
 103         return request_irq(get_dmte_irq(chan->chan), dma_tei,
 104                            IRQF_DISABLED, chan->name, chan);
 105 }
 106
 107 static void sh_dmac_free_dma(struct dma_channel *chan)
 108 {
 109         free_irq(get_dmte_irq(chan->chan), chan);
 110         kfree(chan->name);
 111 }
 112
 113 static void
 114 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
 115 {
 116         if (!chcr)
 117                 chcr = RS_DUAL | CHCR_IE;
 118
 119         if (chcr & CHCR_IE) {
 120                 chcr &= ~CHCR_IE;
 121                 chan->flags |= DMA_TEI_CAPABLE;
 122         } else {
 123                 chan->flags &= ~DMA_TEI_CAPABLE;
 124         }
 125
 126         ctrl_outl(chcr, CHCR[chan->chan]);
 127
 128         chan->flags |= DMA_CONFIGURED;
 129 }
 130
 131 static void sh_dmac_enable_dma(struct dma_channel *chan)
 132 {
 133         int irq;
 134         u32 chcr;
 135
 136         chcr = ctrl_inl(CHCR[chan->chan]);
 137         chcr |= CHCR_DE;
 138
 139         if (chan->flags & DMA_TEI_CAPABLE)
 140                 chcr |= CHCR_IE;
 141
 142         ctrl_outl(chcr, CHCR[chan->chan]);
 143
 144         if (chan->flags & DMA_TEI_CAPABLE) {
 145                 irq = get_dmte_irq(chan->chan);
 146                 enable_irq(irq);
 147         }
 148 }
 149
 150 static void sh_dmac_disable_dma(struct dma_channel *chan)
 151 {
 152         int irq;
 153         u32 chcr;
 154
 155         if (chan->flags & DMA_TEI_CAPABLE) {
 156                 irq = get_dmte_irq(chan->chan);
 157                 disable_irq(irq);
 158         }
 159
 160         chcr = ctrl_inl(CHCR[chan->chan]);
 161         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 162         ctrl_outl(chcr, CHCR[chan->chan]);
 163 }
 164
 165 static int sh_dmac_xfer_dma(struct dma_channel *chan)
 166 {
 167         /*
 168          * If we haven't pre-configured the channel with special flags, use
 169          * the defaults.
 170          */
 171         if (unlikely(!(chan->flags & DMA_CONFIGURED)))
 172                 sh_dmac_configure_channel(chan, 0);
 173
 174         sh_dmac_disable_dma(chan);
 175
 176         /*
 177          * Single-address mode usage note!
 178          *
 179          * It's important that we don't accidentally write any value to SAR/DAR
 180          * (this includes 0) that hasn't been directly specified by the user if
 181          * we're in single-address mode.
 182          *
 183          * In this case, only one address can be defined, anything else will
 184          * result in a DMA address error interrupt (at least on the SH-4),
 185          * which will subsequently halt the transfer.
 186          *
 187          * Channel 2 on the Dreamcast is a special case, as this is used for
 188          * cascading to the PVR2 DMAC. In this case, we still need to write
 189          * SAR and DAR, regardless of value, in order for cascading to work.
 190          */
 191         if (chan->sar || (mach_is_dreamcast() &&
 192                           chan->chan == PVR2_CASCADE_CHAN))
 193                 ctrl_outl(chan->sar, SAR[chan->chan]);
 194         if (chan->dar || (mach_is_dreamcast() &&
 195                           chan->chan == PVR2_CASCADE_CHAN))
 196                 ctrl_outl(chan->dar, DAR[chan->chan]);
 197
 198         ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
 199
 200         sh_dmac_enable_dma(chan);
 201
 202         return 0;
 203 }
 204
 205 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 206 {
 207         if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
 208                 return 0;
 209
 210         return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
 211 }
 212
 213 #ifdef CONFIG_CPU_SUBTYPE_SH7780
 214 #define dmaor_read_reg()        ctrl_inw(DMAOR)
 215 #define dmaor_write_reg(data)   ctrl_outw(data, DMAOR)
 216 #else
 217 #define dmaor_read_reg()        ctrl_inl(DMAOR)
 218 #define dmaor_write_reg(data)   ctrl_outl(data, DMAOR)
 219 #endif
 220
 221 static inline int dmaor_reset(void)
 222 {
 223         unsigned long dmaor = dmaor_read_reg();
 224
 225         /* Try to clear the error flags first, incase they are set */
 226         dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
 227         dmaor_write_reg(dmaor);
 228
 229         dmaor |= DMAOR_INIT;
 230         dmaor_write_reg(dmaor);
 231
 232         /* See if we got an error again */
 233         if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
 234                 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
 235                 return -EINVAL;
 236         }
 237
 238         return 0;
 239 }
 240
 241 #if defined(CONFIG_CPU_SH4)
 242 static irqreturn_t dma_err(int irq, void *dummy)
 243 {
 244         dmaor_reset();
 245         disable_irq(irq);
 246
 247         return IRQ_HANDLED;
 248 }
 249 #endif
 250
 251 static struct dma_ops sh_dmac_ops = {
 252         .request        = sh_dmac_request_dma,
 253         .free           = sh_dmac_free_dma,
 254         .get_residue    = sh_dmac_get_dma_residue,
 255         .xfer           = sh_dmac_xfer_dma,
 256         .configure      = sh_dmac_configure_channel,
 257 };
 258
 259 static struct dma_info sh_dmac_info = {
 260         .name           = "sh_dmac",
 261         .nr_channels    = CONFIG_NR_ONCHIP_DMA_CHANNELS,
 262         .ops            = &sh_dmac_ops,
 263         .flags          = DMAC_CHANNELS_TEI_CAPABLE,
 264 };
 265
 266 static int __init sh_dmac_init(void)
 267 {
 268         struct dma_info *info = &sh_dmac_info;
 269         int i;
 270
 271 #ifdef CONFIG_CPU_SH4
 272         make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map));
 273         i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
 274         if (unlikely(i < 0))
 275                 return i;
 276 #endif
 277
 278         i = info->nr_channels;
 279         if (i > ARRAY_SIZE(dmte_ipr_map))
 280                 i = ARRAY_SIZE(dmte_ipr_map);
 281         make_ipr_irq(dmte_ipr_map, i);
 282
 283         /*
 284          * Initialize DMAOR, and clean up any error flags that may have
 285          * been set.
 286          */
 287         i = dmaor_reset();
 288         if (unlikely(i != 0))
 289                 return i;
 290
 291         return register_dmac(info);
 292 }
 293
 294 static void __exit sh_dmac_exit(void)
 295 {
 296 #ifdef CONFIG_CPU_SH4
 297         free_irq(DMAE_IRQ, 0);
 298 #endif
 299         unregister_dmac(&sh_dmac_info);
 300 }
 301
 302 subsys_initcall(sh_dmac_init);
 303 module_exit(sh_dmac_exit);
 304
 305 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
 306 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
 307 MODULE_LICENSE("GPL");