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1 /*
2 * PCI autoconfiguration library
4 * Author: Matt Porter <mporter@mvista.com>
6 * Copyright 2000, 2001 MontaVista Software Inc.
7 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
8 * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
17 * Modified for MIPS by Jun Sun, jsun@mvista.com
19 * . Simplify the interface between pci_auto and the rest: a single function.
20 * . Assign resources from low address to upper address.
21 * . change most int to u32.
23 * Further modified to include it as mips generic code, ppopov@mvista.com.
25 * 2001-10-26 Bradley D. LaRonde <brad@ltc.com>
26 * - Add a top_bus argument to the "early config" functions so that
27 * they can set a fake parent bus pointer to convince the underlying
28 * pci ops to use type 1 configuration for sub busses.
29 * - Set bridge base and limit registers correctly.
30 * - Align io and memory base properly before and after bridge setup.
31 * - Don't fall through to pci_setup_bars for bridge.
32 * - Reformat the debug output to look more like lspci's output.
34 * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
36 * 2003-08-05 Paul Mundt <lethal@linux-sh.org>
37 * - Don't update the BAR values on systems that already have valid addresses
38 * and don't want these updated for whatever reason, by way of a new config
39 * option check. However, we still read in the old BAR values so that they
40 * can still be reported through the debug output.
43 #include <linux/kernel.h>
44 #include <linux/init.h>
45 #include <linux/types.h>
46 #include <linux/pci.h>
48 #define DEBUG
49 #ifdef DEBUG
50 #define DBG(x...) printk(x)
51 #else
52 #define DBG(x...)
53 #endif
56 * These functions are used early on before PCI scanning is done
57 * and all of the pci_dev and pci_bus structures have been created.
59 static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
60 int top_bus, int busnr, int devfn)
62 static struct pci_dev dev;
63 static struct pci_bus bus;
65 dev.bus = &bus;
66 dev.sysdata = hose;
67 dev.devfn = devfn;
68 bus.number = busnr;
69 bus.ops = hose->pci_ops;
71 if(busnr != top_bus)
72 /* Fake a parent bus structure. */
73 bus.parent = &bus;
74 else
75 bus.parent = NULL;
77 return &dev;
80 #define EARLY_PCI_OP(rw, size, type) \
81 int early_##rw##_config_##size(struct pci_channel *hose, \
82 int top_bus, int bus, int devfn, int offset, type value) \
83 { \
84 return pci_##rw##_config_##size( \
85 fake_pci_dev(hose, top_bus, bus, devfn), \
86 offset, value); \
89 EARLY_PCI_OP(read, byte, u8 *)
90 EARLY_PCI_OP(read, word, u16 *)
91 EARLY_PCI_OP(read, dword, u32 *)
92 EARLY_PCI_OP(write, byte, u8)
93 EARLY_PCI_OP(write, word, u16)
94 EARLY_PCI_OP(write, dword, u32)
96 static struct resource *io_resource_inuse;
97 static struct resource *mem_resource_inuse;
99 static u32 pciauto_lower_iospc;
100 static u32 pciauto_upper_iospc;
102 static u32 pciauto_lower_memspc;
103 static u32 pciauto_upper_memspc;
105 static void __init
106 pciauto_setup_bars(struct pci_channel *hose,
107 int top_bus,
108 int current_bus,
109 int pci_devfn,
110 int bar_limit)
112 u32 bar_response, bar_size, bar_value;
113 u32 bar, addr_mask, bar_nr = 0;
114 u32 * upper_limit;
115 u32 * lower_limit;
116 int found_mem64 = 0;
118 for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
119 u32 bar_addr;
121 /* Read the old BAR value */
122 early_read_config_dword(hose, top_bus,
123 current_bus,
124 pci_devfn,
125 bar,
126 &bar_addr);
128 /* Tickle the BAR and get the response */
129 early_write_config_dword(hose, top_bus,
130 current_bus,
131 pci_devfn,
132 bar,
133 0xffffffff);
135 early_read_config_dword(hose, top_bus,
136 current_bus,
137 pci_devfn,
138 bar,
139 &bar_response);
142 * Write the old BAR value back out, only update the BAR
143 * if we implicitly want resources to be updated, which
144 * is done by the generic code further down. -- PFM.
146 early_write_config_dword(hose, top_bus,
147 current_bus,
148 pci_devfn,
149 bar,
150 bar_addr);
152 /* If BAR is not implemented go to the next BAR */
153 if (!bar_response)
154 continue;
157 * Workaround for a BAR that doesn't use its upper word,
158 * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
159 * bdl <brad@ltc.com>
161 if (!(bar_response & 0xffff0000))
162 bar_response |= 0xffff0000;
164 retry:
165 /* Check the BAR type and set our address mask */
166 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
167 addr_mask = PCI_BASE_ADDRESS_IO_MASK;
168 upper_limit = &pciauto_upper_iospc;
169 lower_limit = &pciauto_lower_iospc;
170 DBG(" I/O");
171 } else {
172 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
173 PCI_BASE_ADDRESS_MEM_TYPE_64)
174 found_mem64 = 1;
176 addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
177 upper_limit = &pciauto_upper_memspc;
178 lower_limit = &pciauto_lower_memspc;
179 DBG(" Mem");
183 /* Calculate requested size */
184 bar_size = ~(bar_response & addr_mask) + 1;
186 /* Allocate a base address */
187 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
189 if ((bar_value + bar_size) > *upper_limit) {
190 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
191 if (io_resource_inuse->child) {
192 io_resource_inuse =
193 io_resource_inuse->child;
194 pciauto_lower_iospc =
195 io_resource_inuse->start;
196 pciauto_upper_iospc =
197 io_resource_inuse->end + 1;
198 goto retry;
201 } else {
202 if (mem_resource_inuse->child) {
203 mem_resource_inuse =
204 mem_resource_inuse->child;
205 pciauto_lower_memspc =
206 mem_resource_inuse->start;
207 pciauto_upper_memspc =
208 mem_resource_inuse->end + 1;
209 goto retry;
212 DBG(" unavailable -- skipping, value %x size %x\n",
213 bar_value, bar_size);
214 continue;
217 #ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
218 /* Write it out and update our limit */
219 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
220 bar, bar_value);
221 #endif
223 *lower_limit = bar_value + bar_size;
226 * If we are a 64-bit decoder then increment to the
227 * upper 32 bits of the bar and force it to locate
228 * in the lower 4GB of memory.
230 if (found_mem64) {
231 bar += 4;
232 early_write_config_dword(hose, top_bus,
233 current_bus,
234 pci_devfn,
235 bar,
236 0x00000000);
239 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
241 bar_nr++;
246 static void __init
247 pciauto_prescan_setup_bridge(struct pci_channel *hose,
248 int top_bus,
249 int current_bus,
250 int pci_devfn,
251 int sub_bus)
253 /* Configure bus number registers */
254 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
255 PCI_PRIMARY_BUS, current_bus);
256 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
257 PCI_SECONDARY_BUS, sub_bus + 1);
258 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
259 PCI_SUBORDINATE_BUS, 0xff);
261 /* Align memory and I/O to 1MB and 4KB boundaries. */
262 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
263 & ~(0x100000 - 1);
264 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
265 & ~(0x1000 - 1);
267 /* Set base (lower limit) of address range behind bridge. */
268 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
269 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
270 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
271 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
272 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
273 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
275 /* We don't support prefetchable memory for now, so disable */
276 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
277 PCI_PREF_MEMORY_BASE, 0);
278 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
279 PCI_PREF_MEMORY_LIMIT, 0);
282 static void __init
283 pciauto_postscan_setup_bridge(struct pci_channel *hose,
284 int top_bus,
285 int current_bus,
286 int pci_devfn,
287 int sub_bus)
289 u32 temp;
292 * [jsun] we always bump up baselines a little, so that if there
293 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
294 * spaces.
296 pciauto_lower_memspc += 1;
297 pciauto_lower_iospc += 1;
299 /* Configure bus number registers */
300 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
301 PCI_SUBORDINATE_BUS, sub_bus);
303 /* Set upper limit of address range behind bridge. */
304 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
305 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
306 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
307 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
308 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
309 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
311 /* Align memory and I/O to 1MB and 4KB boundaries. */
312 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
313 & ~(0x100000 - 1);
314 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
315 & ~(0x1000 - 1);
317 /* Enable memory and I/O accesses, enable bus master */
318 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
319 PCI_COMMAND, &temp);
320 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
321 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
322 | PCI_COMMAND_MASTER);
325 static void __init
326 pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
327 int top_bus,
328 int current_bus,
329 int pci_devfn,
330 int sub_bus)
332 /* Configure bus number registers */
333 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
334 PCI_PRIMARY_BUS, current_bus);
335 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
336 PCI_SECONDARY_BUS, sub_bus + 1);
337 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
338 PCI_SUBORDINATE_BUS, 0xff);
340 /* Align memory and I/O to 4KB and 4 byte boundaries. */
341 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
342 & ~(0x1000 - 1);
343 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
344 & ~(0x4 - 1);
346 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
347 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
348 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
349 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
352 static void __init
353 pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
354 int top_bus,
355 int current_bus,
356 int pci_devfn,
357 int sub_bus)
359 u32 temp;
362 * [jsun] we always bump up baselines a little, so that if there
363 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
364 * spaces.
366 pciauto_lower_memspc += 1;
367 pciauto_lower_iospc += 1;
370 * Configure subordinate bus number. The PCI subsystem
371 * bus scan will renumber buses (reserving three additional
372 * for this PCI<->CardBus bridge for the case where a CardBus
373 * adapter contains a P2P or CB2CB bridge.
376 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
377 PCI_SUBORDINATE_BUS, sub_bus);
380 * Reserve an additional 4MB for mem space and 16KB for
381 * I/O space. This should cover any additional space
382 * requirement of unusual CardBus devices with
383 * additional bridges that can consume more address space.
385 * Although pcmcia-cs currently will reprogram bridge
386 * windows, the goal is to add an option to leave them
387 * alone and use the bridge window ranges as the regions
388 * that are searched for free resources upon hot-insertion
389 * of a device. This will allow a PCI<->CardBus bridge
390 * configured by this routine to happily live behind a
391 * P2P bridge in a system.
393 /* Align memory and I/O to 4KB and 4 byte boundaries. */
394 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
395 & ~(0x1000 - 1);
396 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
397 & ~(0x4 - 1);
398 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
399 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
400 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
401 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
402 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
404 /* Enable memory and I/O accesses, enable bus master */
405 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
406 PCI_COMMAND, &temp);
407 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
408 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
409 PCI_COMMAND_MASTER);
412 #define PCIAUTO_IDE_MODE_MASK 0x05
414 static int __init
415 pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
417 int sub_bus;
418 u32 pci_devfn, pci_class, cmdstat, found_multi=0;
419 unsigned short vid, did;
420 unsigned char header_type;
421 int devfn_start = 0;
422 int devfn_stop = 0xff;
424 sub_bus = current_bus;
426 if (hose->first_devfn)
427 devfn_start = hose->first_devfn;
428 if (hose->last_devfn)
429 devfn_stop = hose->last_devfn;
431 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
433 if (PCI_FUNC(pci_devfn) && !found_multi)
434 continue;
436 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
437 PCI_VENDOR_ID, &vid);
439 if (vid == 0xffff) continue;
441 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
442 PCI_HEADER_TYPE, &header_type);
444 if (!PCI_FUNC(pci_devfn))
445 found_multi = header_type & 0x80;
447 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
448 PCI_DEVICE_ID, &did);
450 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
451 PCI_CLASS_REVISION, &pci_class);
453 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
454 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
455 pci_class >> 16, vid, did);
456 if (pci_class & 0xff)
457 DBG(" (rev %.2x)", pci_class & 0xff);
458 DBG("\n");
460 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
461 DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
462 current_bus, sub_bus + 1);
463 pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
464 pci_devfn, sub_bus);
465 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
466 sub_bus + 1,
467 pciauto_lower_iospc, pciauto_lower_memspc);
468 sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
469 DBG("Back to bus %.2x\n", current_bus);
470 pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
471 pci_devfn, sub_bus);
472 continue;
473 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
474 DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n",
475 current_bus, sub_bus + 1);
476 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
477 /* Place CardBus Socket/ExCA registers */
478 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
480 pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
481 current_bus, pci_devfn, sub_bus);
483 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
484 sub_bus + 1,
485 pciauto_lower_iospc, pciauto_lower_memspc);
486 sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
487 DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
488 pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
489 current_bus, pci_devfn, sub_bus);
490 continue;
491 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
493 unsigned char prg_iface;
495 early_read_config_byte(hose, top_bus, current_bus,
496 pci_devfn, PCI_CLASS_PROG, &prg_iface);
497 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
498 DBG("Skipping legacy mode IDE controller\n");
499 continue;
504 * Found a peripheral, enable some standard
505 * settings
507 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
508 PCI_COMMAND, &cmdstat);
509 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
510 PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
511 PCI_COMMAND_MEMORY |
512 PCI_COMMAND_MASTER);
513 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
514 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
515 PCI_LATENCY_TIMER, 0x80);
516 #endif
518 /* Allocate PCI I/O and/or memory space */
519 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
521 return sub_bus;
524 int __init
525 pciauto_assign_resources(int busno, struct pci_channel *hose)
527 /* setup resource limits */
528 io_resource_inuse = hose->io_resource;
529 mem_resource_inuse = hose->mem_resource;
531 pciauto_lower_iospc = io_resource_inuse->start;
532 pciauto_upper_iospc = io_resource_inuse->end + 1;
533 pciauto_lower_memspc = mem_resource_inuse->start;
534 pciauto_upper_memspc = mem_resource_inuse->end + 1;
535 DBG("Autoconfig PCI channel 0x%p\n", hose);
536 DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
537 busno, pciauto_lower_iospc, pciauto_upper_iospc,
538 pciauto_lower_memspc, pciauto_upper_memspc);
540 return pciauto_bus_scan(hose, busno, busno);