arch/sh/kernel/cpu/sh4/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2006  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17 #include <asm/io.h>
  18
  19 int __init detect_cpu_and_cache_system(void)
  20 {
  21         unsigned long pvr, prr, cvr;
  22         unsigned long size;
  23
  24         static unsigned long sizes[16] = {
  25                 [1] = (1 << 12),
  26                 [2] = (1 << 13),
  27                 [4] = (1 << 14),
  28                 [8] = (1 << 15),
  29                 [9] = (1 << 16)
  30         };
  31
  32         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
  33         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  34         cvr = (ctrl_inl(CCN_CVR));
  35
  36         /*
  37          * Setup some sane SH-4 defaults for the icache
  38          */
  39         cpu_data->icache.way_incr       = (1 << 13);
  40         cpu_data->icache.entry_shift    = 5;
  41         cpu_data->icache.sets           = 256;
  42         cpu_data->icache.ways           = 1;
  43         cpu_data->icache.linesz         = L1_CACHE_BYTES;
  44
  45         /*
  46          * And again for the dcache ..
  47          */
  48         cpu_data->dcache.way_incr       = (1 << 14);
  49         cpu_data->dcache.entry_shift    = 5;
  50         cpu_data->dcache.sets           = 512;
  51         cpu_data->dcache.ways           = 1;
  52         cpu_data->dcache.linesz         = L1_CACHE_BYTES;
  53
  54         /*
  55          * Setup some generic flags we can probe
  56          * (L2 and DSP detection only work on SH-4A)
  57          */
  58         if (((pvr >> 16) & 0xff) == 0x10) {
  59                 if ((cvr & 0x02000000) == 0)
  60                         cpu_data->flags |= CPU_HAS_L2_CACHE;
  61                 if ((cvr & 0x10000000) == 0)
  62                         cpu_data->flags |= CPU_HAS_DSP;
  63
  64                 cpu_data->flags |= CPU_HAS_LLSC;
  65         }
  66
  67         /* FPU detection works for everyone */
  68         if ((cvr & 0x20000000) == 1)
  69                 cpu_data->flags |= CPU_HAS_FPU;
  70
  71         /* Mask off the upper chip ID */
  72         pvr &= 0xffff;
  73
  74         /*
  75          * Probe the underlying processor version/revision and
  76          * adjust cpu_data setup accordingly.
  77          */
  78         switch (pvr) {
  79         case 0x205:
  80                 cpu_data->type = CPU_SH7750;
  81                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  82                                    CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA;
  83                 break;
  84         case 0x206:
  85                 cpu_data->type = CPU_SH7750S;
  86                 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU |
  87                                    CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA;
  88                 break;
  89         case 0x1100:
  90                 cpu_data->type = CPU_SH7751;
  91                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
  92                 break;
  93         case 0x2000:
  94                 cpu_data->type = CPU_SH73180;
  95                 cpu_data->icache.ways = 4;
  96                 cpu_data->dcache.ways = 4;
  97                 cpu_data->flags |= CPU_HAS_LLSC;
  98                 break;
  99         case 0x2001:
 100         case 0x2004:
 101                 cpu_data->type = CPU_SH7770;
 102                 cpu_data->icache.ways = 4;
 103                 cpu_data->dcache.ways = 4;
 104
 105                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
 106                 break;
 107         case 0x2006:
 108         case 0x200A:
 109                 if (prr == 0x61)
 110                         cpu_data->type = CPU_SH7781;
 111                 else
 112                         cpu_data->type = CPU_SH7780;
 113
 114                 cpu_data->icache.ways = 4;
 115                 cpu_data->dcache.ways = 4;
 116
 117                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 118                                    CPU_HAS_LLSC;
 119                 break;
 120         case 0x3000:
 121         case 0x3003:
 122                 cpu_data->type = CPU_SH7343;
 123                 cpu_data->icache.ways = 4;
 124                 cpu_data->dcache.ways = 4;
 125                 cpu_data->flags |= CPU_HAS_LLSC;
 126                 break;
 127         case 0x8000:
 128                 cpu_data->type = CPU_ST40RA;
 129                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 130                 break;
 131         case 0x8100:
 132                 cpu_data->type = CPU_ST40GX1;
 133                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 134                 break;
 135         case 0x700:
 136                 cpu_data->type = CPU_SH4_501;
 137                 cpu_data->icache.ways = 2;
 138                 cpu_data->dcache.ways = 2;
 139                 cpu_data->flags |= CPU_HAS_PTEA;
 140                 break;
 141         case 0x600:
 142                 cpu_data->type = CPU_SH4_202;
 143                 cpu_data->icache.ways = 2;
 144                 cpu_data->dcache.ways = 2;
 145                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 146                 break;
 147         case 0x500 ... 0x501:
 148                 switch (prr) {
 149                 case 0x10:
 150                         cpu_data->type = CPU_SH7750R;
 151                         break;
 152                 case 0x11:
 153                         cpu_data->type = CPU_SH7751R;
 154                         break;
 155                 case 0x50 ... 0x5f:
 156                         cpu_data->type = CPU_SH7760;
 157                         break;
 158                 }
 159
 160                 cpu_data->icache.ways = 2;
 161                 cpu_data->dcache.ways = 2;
 162
 163                 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
 164
 165                 break;
 166         default:
 167                 cpu_data->type = CPU_SH_NONE;
 168                 break;
 169         }
 170
 171 #ifdef CONFIG_SH_DIRECT_MAPPED
 172         cpu_data->icache.ways = 1;
 173         cpu_data->dcache.ways = 1;
 174 #endif
 175
 176         /*
 177          * On anything that's not a direct-mapped cache, look to the CVR
 178          * for I/D-cache specifics.
 179          */
 180         if (cpu_data->icache.ways > 1) {
 181                 size = sizes[(cvr >> 20) & 0xf];
 182                 cpu_data->icache.way_incr       = (size >> 1);
 183                 cpu_data->icache.sets           = (size >> 6);
 184
 185         }
 186
 187         /* Setup the rest of the I-cache info */
 188         cpu_data->icache.entry_mask = cpu_data->icache.way_incr -
 189                                       cpu_data->icache.linesz;
 190
 191         cpu_data->icache.way_size = cpu_data->icache.sets *
 192                                     cpu_data->icache.linesz;
 193
 194         /* And the rest of the D-cache */
 195         if (cpu_data->dcache.ways > 1) {
 196                 size = sizes[(cvr >> 16) & 0xf];
 197                 cpu_data->dcache.way_incr       = (size >> 1);
 198                 cpu_data->dcache.sets           = (size >> 6);
 199         }
 200
 201         cpu_data->dcache.entry_mask = cpu_data->dcache.way_incr -
 202                                       cpu_data->dcache.linesz;
 203
 204         cpu_data->dcache.way_size = cpu_data->dcache.sets *
 205                                     cpu_data->dcache.linesz;
 206
 207         /*
 208          * Setup the L2 cache desc
 209          *
 210          * SH-4A's have an optional PIPT L2.
 211          */
 212         if (cpu_data->flags & CPU_HAS_L2_CACHE) {
 213                 /*
 214                  * Size calculation is much more sensible
 215                  * than it is for the L1.
 216                  *
 217                  * Sizes are 128KB, 258KB, 512KB, and 1MB.
 218                  */
 219                 size = (cvr & 0xf) << 17;
 220
 221                 BUG_ON(!size);
 222
 223                 cpu_data->scache.way_incr       = (1 << 16);
 224                 cpu_data->scache.entry_shift    = 5;
 225                 cpu_data->scache.ways           = 4;
 226                 cpu_data->scache.linesz         = L1_CACHE_BYTES;
 227                 cpu_data->scache.entry_mask     =
 228                         (cpu_data->scache.way_incr - cpu_data->scache.linesz);
 229                 cpu_data->scache.sets           = size /
 230                         (cpu_data->scache.linesz * cpu_data->scache.ways);
 231                 cpu_data->scache.way_size       =
 232                         (cpu_data->scache.sets * cpu_data->scache.linesz);
 233         }
 234
 235         return 0;
 236 }