arch/sh/kernel/timers/timer-tmu.c

   1 /*
   2  * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
   3  *
   4  *  Copyright (C) 2005  Paul Mundt
   5  *
   6  * TMU handling code hacked out of arch/sh/kernel/time.c
   7  *
   8  *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
   9  *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
  10  *  Copyright (C) 2002, 2003, 2004  Paul Mundt
  11  *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
  12  *
  13  * This file is subject to the terms and conditions of the GNU General Public
  14  * License.  See the file "COPYING" in the main directory of this archive
  15  * for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/seqlock.h>
  22 #include <asm/timer.h>
  23 #include <asm/rtc.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/clock.h>
  27
  28 #define TMU_TOCR_INIT   0x00
  29 #define TMU0_TCR_INIT   0x0020
  30 #define TMU_TSTR_INIT   1
  31
  32 #define TMU0_TCR_CALIB  0x0000
  33
  34 static DEFINE_SPINLOCK(tmu0_lock);
  35
  36 static unsigned long tmu_timer_get_offset(void)
  37 {
  38         int count;
  39         unsigned long flags;
  40
  41         static int count_p = 0x7fffffff;    /* for the first call after boot */
  42         static unsigned long jiffies_p = 0;
  43
  44         /*
  45          * cache volatile jiffies temporarily; we have IRQs turned off.
  46          */
  47         unsigned long jiffies_t;
  48
  49         spin_lock_irqsave(&tmu0_lock, flags);
  50         /* timer count may underflow right here */
  51         count = ctrl_inl(TMU0_TCNT);    /* read the latched count */
  52
  53         jiffies_t = jiffies;
  54
  55         /*
  56          * avoiding timer inconsistencies (they are rare, but they happen)...
  57          * there is one kind of problem that must be avoided here:
  58          *  1. the timer counter underflows
  59          */
  60
  61         if (jiffies_t == jiffies_p) {
  62                 if (count > count_p) {
  63                         /* the nutcase */
  64                         if (ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
  65                                 count -= LATCH;
  66                         } else {
  67                                 printk("%s (): hardware timer problem?\n",
  68                                        __FUNCTION__);
  69                         }
  70                 }
  71         } else
  72                 jiffies_p = jiffies_t;
  73
  74         count_p = count;
  75         spin_unlock_irqrestore(&tmu0_lock, flags);
  76
  77         count = ((LATCH-1) - count) * TICK_SIZE;
  78         count = (count + LATCH/2) / LATCH;
  79
  80         return count;
  81 }
  82
  83 static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
  84 {
  85         unsigned long timer_status;
  86
  87         /* Clear UNF bit */
  88         timer_status = ctrl_inw(TMU0_TCR);
  89         timer_status &= ~0x100;
  90         ctrl_outw(timer_status, TMU0_TCR);
  91
  92         /*
  93          * Here we are in the timer irq handler. We just have irqs locally
  94          * disabled but we don't know if the timer_bh is running on the other
  95          * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
  96          * the irq version of write_lock because as just said we have irq
  97          * locally disabled. -arca
  98          */
  99         write_seqlock(&xtime_lock);
 100         handle_timer_tick();
 101         write_sequnlock(&xtime_lock);
 102
 103         return IRQ_HANDLED;
 104 }
 105
 106 static struct irqaction tmu_irq = {
 107         .name           = "timer",
 108         .handler        = tmu_timer_interrupt,
 109         .flags          = IRQF_DISABLED,
 110         .mask           = CPU_MASK_NONE,
 111 };
 112
 113 static void tmu_clk_init(struct clk *clk)
 114 {
 115         u8 divisor = TMU0_TCR_INIT & 0x7;
 116         ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
 117         clk->rate = clk->parent->rate / (4 << (divisor << 1));
 118 }
 119
 120 static void tmu_clk_recalc(struct clk *clk)
 121 {
 122         u8 divisor = ctrl_inw(TMU0_TCR) & 0x7;
 123         clk->rate = clk->parent->rate / (4 << (divisor << 1));
 124 }
 125
 126 static struct clk_ops tmu_clk_ops = {
 127         .init           = tmu_clk_init,
 128         .recalc         = tmu_clk_recalc,
 129 };
 130
 131 static struct clk tmu0_clk = {
 132         .name           = "tmu0_clk",
 133         .ops            = &tmu_clk_ops,
 134 };
 135
 136 static int tmu_timer_start(void)
 137 {
 138         ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
 139         return 0;
 140 }
 141
 142 static int tmu_timer_stop(void)
 143 {
 144         ctrl_outb(0, TMU_TSTR);
 145         return 0;
 146 }
 147
 148 static int tmu_timer_init(void)
 149 {
 150         unsigned long interval;
 151
 152         setup_irq(TIMER_IRQ, &tmu_irq);
 153
 154         tmu0_clk.parent = clk_get("module_clk");
 155
 156         /* Start TMU0 */
 157         tmu_timer_stop();
 158 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
 159         ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
 160 #endif
 161
 162         clk_register(&tmu0_clk);
 163         clk_enable(&tmu0_clk);
 164
 165         interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
 166         printk(KERN_INFO "Interval = %ld\n", interval);
 167
 168         ctrl_outl(interval, TMU0_TCOR);
 169         ctrl_outl(interval, TMU0_TCNT);
 170
 171         tmu_timer_start();
 172
 173         return 0;
 174 }
 175
 176 struct sys_timer_ops tmu_timer_ops = {
 177         .init           = tmu_timer_init,
 178         .start          = tmu_timer_start,
 179         .stop           = tmu_timer_stop,
 180 #ifndef CONFIG_GENERIC_TIME
 181         .get_offset     = tmu_timer_get_offset,
 182 #endif
 183 };
 184
 185 struct sys_timer tmu_timer = {
 186         .name   = "tmu",
 187         .ops    = &tmu_timer_ops,
 188 };