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[hh.org.git] / arch / sh / kernel / traps.c
blob53dfa55f3156b40327e977aef77d7fef08d5351e
1 /*
2 * 'traps.c' handles hardware traps and faults after we have saved some
3 * state in 'entry.S'.
4 *
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2006 Paul Mundt
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
18 #include <linux/module.h>
19 #include <linux/kallsyms.h>
20 #include <linux/io.h>
21 #include <asm/system.h>
22 #include <asm/uaccess.h>
23
24 #ifdef CONFIG_SH_KGDB
25 #include <asm/kgdb.h>
26 #define CHK_REMOTE_DEBUG(regs) \
27 { \
28 if (kgdb_debug_hook && !user_mode(regs))\
29 (*kgdb_debug_hook)(regs); \
30 }
31 #else
32 #define CHK_REMOTE_DEBUG(regs)
33 #endif
34
35 #ifdef CONFIG_CPU_SH2
36 #define TRAP_RESERVED_INST 4
37 #define TRAP_ILLEGAL_SLOT_INST 6
38 #else
39 #define TRAP_RESERVED_INST 12
40 #define TRAP_ILLEGAL_SLOT_INST 13
41 #endif
42
43 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
44 {
45 unsigned long p;
46 int i;
47
48 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
49
50 for (p = bottom & ~31; p < top; ) {
51 printk("%04lx: ", p & 0xffff);
52
53 for (i = 0; i < 8; i++, p += 4) {
54 unsigned int val;
55
56 if (p < bottom || p >= top)
57 printk(" ");
58 else {
59 if (__get_user(val, (unsigned int __user *)p)) {
60 printk("\n");
61 return;
62 }
63 printk("%08x ", val);
64 }
65 }
66 printk("\n");
67 }
68 }
69
70 DEFINE_SPINLOCK(die_lock);
71
72 void die(const char * str, struct pt_regs * regs, long err)
73 {
74 static int die_counter;
75
76 console_verbose();
77 spin_lock_irq(&die_lock);
78 bust_spinlocks(1);
79
80 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
81
82 CHK_REMOTE_DEBUG(regs);
83 print_modules();
84 show_regs(regs);
85
86 printk("Process: %s (pid: %d, stack limit = %p)\n",
87 current->comm, current->pid, task_stack_page(current) + 1);
88
89 if (!user_mode(regs) || in_interrupt())
90 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
91 (unsigned long)task_stack_page(current));
92
93 bust_spinlocks(0);
94 spin_unlock_irq(&die_lock);
95 do_exit(SIGSEGV);
96 }
97
98 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
99 long err)
100 {
101 if (!user_mode(regs))
102 die(str, regs, err);
103 }
104
105 static int handle_unaligned_notify_count = 10;
106
107 /*
108 * try and fix up kernelspace address errors
109 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
110 * - kernel/userspace interfaces cause a jump to an appropriate handler
111 * - other kernel errors are bad
112 * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
113 */
114 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
115 {
116 if (!user_mode(regs)) {
117 const struct exception_table_entry *fixup;
118 fixup = search_exception_tables(regs->pc);
119 if (fixup) {
120 regs->pc = fixup->fixup;
121 return 0;
122 }
123 die(str, regs, err);
124 }
125 return -EFAULT;
126 }
127
128 /*
129 * handle an instruction that does an unaligned memory access by emulating the
130 * desired behaviour
131 * - note that PC _may not_ point to the faulting instruction
132 * (if that instruction is in a branch delay slot)
133 * - return 0 if emulation okay, -EFAULT on existential error
134 */
135 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs)
136 {
137 int ret, index, count;
138 unsigned long *rm, *rn;
139 unsigned char *src, *dst;
140
141 index = (instruction>>8)&15; /* 0x0F00 */
142 rn = &regs->regs[index];
143
144 index = (instruction>>4)&15; /* 0x00F0 */
145 rm = &regs->regs[index];
146
147 count = 1<<(instruction&3);
148
149 ret = -EFAULT;
150 switch (instruction>>12) {
151 case 0: /* mov.[bwl] to/from memory via r0+rn */
152 if (instruction & 8) {
153 /* from memory */
154 src = (unsigned char*) *rm;
155 src += regs->regs[0];
156 dst = (unsigned char*) rn;
157 *(unsigned long*)dst = 0;
158
159 #ifdef __LITTLE_ENDIAN__
160 if (copy_from_user(dst, src, count))
161 goto fetch_fault;
162
163 if ((count == 2) && dst[1] & 0x80) {
164 dst[2] = 0xff;
165 dst[3] = 0xff;
166 }
167 #else
168 dst += 4-count;
169
170 if (__copy_user(dst, src, count))
171 goto fetch_fault;
172
173 if ((count == 2) && dst[2] & 0x80) {
174 dst[0] = 0xff;
175 dst[1] = 0xff;
176 }
177 #endif
178 } else {
179 /* to memory */
180 src = (unsigned char*) rm;
181 #if !defined(__LITTLE_ENDIAN__)
182 src += 4-count;
183 #endif
184 dst = (unsigned char*) *rn;
185 dst += regs->regs[0];
186
187 if (copy_to_user(dst, src, count))
188 goto fetch_fault;
189 }
190 ret = 0;
191 break;
192
193 case 1: /* mov.l Rm,@(disp,Rn) */
194 src = (unsigned char*) rm;
195 dst = (unsigned char*) *rn;
196 dst += (instruction&0x000F)<<2;
197
198 if (copy_to_user(dst,src,4))
199 goto fetch_fault;
200 ret = 0;
201 break;
202
203 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
204 if (instruction & 4)
205 *rn -= count;
206 src = (unsigned char*) rm;
207 dst = (unsigned char*) *rn;
208 #if !defined(__LITTLE_ENDIAN__)
209 src += 4-count;
210 #endif
211 if (copy_to_user(dst, src, count))
212 goto fetch_fault;
213 ret = 0;
214 break;
215
216 case 5: /* mov.l @(disp,Rm),Rn */
217 src = (unsigned char*) *rm;
218 src += (instruction&0x000F)<<2;
219 dst = (unsigned char*) rn;
220 *(unsigned long*)dst = 0;
221
222 if (copy_from_user(dst,src,4))
223 goto fetch_fault;
224 ret = 0;
225 break;
226
227 case 6: /* mov.[bwl] from memory, possibly with post-increment */
228 src = (unsigned char*) *rm;
229 if (instruction & 4)
230 *rm += count;
231 dst = (unsigned char*) rn;
232 *(unsigned long*)dst = 0;
233
234 #ifdef __LITTLE_ENDIAN__
235 if (copy_from_user(dst, src, count))
236 goto fetch_fault;
237
238 if ((count == 2) && dst[1] & 0x80) {
239 dst[2] = 0xff;
240 dst[3] = 0xff;
241 }
242 #else
243 dst += 4-count;
244
245 if (copy_from_user(dst, src, count))
246 goto fetch_fault;
247
248 if ((count == 2) && dst[2] & 0x80) {
249 dst[0] = 0xff;
250 dst[1] = 0xff;
251 }
252 #endif
253 ret = 0;
254 break;
255
256 case 8:
257 switch ((instruction&0xFF00)>>8) {
258 case 0x81: /* mov.w R0,@(disp,Rn) */
259 src = (unsigned char*) &regs->regs[0];
260 #if !defined(__LITTLE_ENDIAN__)
261 src += 2;
262 #endif
263 dst = (unsigned char*) *rm; /* called Rn in the spec */
264 dst += (instruction&0x000F)<<1;
265
266 if (copy_to_user(dst, src, 2))
267 goto fetch_fault;
268 ret = 0;
269 break;
270
271 case 0x85: /* mov.w @(disp,Rm),R0 */
272 src = (unsigned char*) *rm;
273 src += (instruction&0x000F)<<1;
274 dst = (unsigned char*) &regs->regs[0];
275 *(unsigned long*)dst = 0;
276
277 #if !defined(__LITTLE_ENDIAN__)
278 dst += 2;
279 #endif
280
281 if (copy_from_user(dst, src, 2))
282 goto fetch_fault;
283
284 #ifdef __LITTLE_ENDIAN__
285 if (dst[1] & 0x80) {
286 dst[2] = 0xff;
287 dst[3] = 0xff;
288 }
289 #else
290 if (dst[2] & 0x80) {
291 dst[0] = 0xff;
292 dst[1] = 0xff;
293 }
294 #endif
295 ret = 0;
296 break;
297 }
298 break;
299 }
300 return ret;
301
302 fetch_fault:
303 /* Argh. Address not only misaligned but also non-existent.
304 * Raise an EFAULT and see if it's trapped
305 */
306 return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
307 }
308
309 /*
310 * emulate the instruction in the delay slot
311 * - fetches the instruction from PC+2
312 */
313 static inline int handle_unaligned_delayslot(struct pt_regs *regs)
314 {
315 u16 instruction;
316
317 if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) {
318 /* the instruction-fetch faulted */
319 if (user_mode(regs))
320 return -EFAULT;
321
322 /* kernel */
323 die("delay-slot-insn faulting in handle_unaligned_delayslot", regs, 0);
324 }
325
326 return handle_unaligned_ins(instruction,regs);
327 }
328
329 /*
330 * handle an instruction that does an unaligned memory access
331 * - have to be careful of branch delay-slot instructions that fault
332 * SH3:
333 * - if the branch would be taken PC points to the branch
334 * - if the branch would not be taken, PC points to delay-slot
335 * SH4:
336 * - PC always points to delayed branch
337 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
338 */
339
340 /* Macros to determine offset from current PC for branch instructions */
341 /* Explicit type coercion is used to force sign extension where needed */
342 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
343 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
344
345 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
346 {
347 u_int rm;
348 int ret, index;
349
350 index = (instruction>>8)&15; /* 0x0F00 */
351 rm = regs->regs[index];
352
353 /* shout about the first ten userspace fixups */
354 if (user_mode(regs) && handle_unaligned_notify_count>0) {
355 handle_unaligned_notify_count--;
356
357 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
358 current->comm,current->pid,(u16*)regs->pc,instruction);
359 }
360
361 ret = -EFAULT;
362 switch (instruction&0xF000) {
363 case 0x0000:
364 if (instruction==0x000B) {
365 /* rts */
366 ret = handle_unaligned_delayslot(regs);
367 if (ret==0)
368 regs->pc = regs->pr;
369 }
370 else if ((instruction&0x00FF)==0x0023) {
371 /* braf @Rm */
372 ret = handle_unaligned_delayslot(regs);
373 if (ret==0)
374 regs->pc += rm + 4;
375 }
376 else if ((instruction&0x00FF)==0x0003) {
377 /* bsrf @Rm */
378 ret = handle_unaligned_delayslot(regs);
379 if (ret==0) {
380 regs->pr = regs->pc + 4;
381 regs->pc += rm + 4;
382 }
383 }
384 else {
385 /* mov.[bwl] to/from memory via r0+rn */
386 goto simple;
387 }
388 break;
389
390 case 0x1000: /* mov.l Rm,@(disp,Rn) */
391 goto simple;
392
393 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
394 goto simple;
395
396 case 0x4000:
397 if ((instruction&0x00FF)==0x002B) {
398 /* jmp @Rm */
399 ret = handle_unaligned_delayslot(regs);
400 if (ret==0)
401 regs->pc = rm;
402 }
403 else if ((instruction&0x00FF)==0x000B) {
404 /* jsr @Rm */
405 ret = handle_unaligned_delayslot(regs);
406 if (ret==0) {
407 regs->pr = regs->pc + 4;
408 regs->pc = rm;
409 }
410 }
411 else {
412 /* mov.[bwl] to/from memory via r0+rn */
413 goto simple;
414 }
415 break;
416
417 case 0x5000: /* mov.l @(disp,Rm),Rn */
418 goto simple;
419
420 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
421 goto simple;
422
423 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
424 switch (instruction&0x0F00) {
425 case 0x0100: /* mov.w R0,@(disp,Rm) */
426 goto simple;
427 case 0x0500: /* mov.w @(disp,Rm),R0 */
428 goto simple;
429 case 0x0B00: /* bf lab - no delayslot*/
430 break;
431 case 0x0F00: /* bf/s lab */
432 ret = handle_unaligned_delayslot(regs);
433 if (ret==0) {
434 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
435 if ((regs->sr & 0x00000001) != 0)
436 regs->pc += 4; /* next after slot */
437 else
438 #endif
439 regs->pc += SH_PC_8BIT_OFFSET(instruction);
440 }
441 break;
442 case 0x0900: /* bt lab - no delayslot */
443 break;
444 case 0x0D00: /* bt/s lab */
445 ret = handle_unaligned_delayslot(regs);
446 if (ret==0) {
447 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
448 if ((regs->sr & 0x00000001) == 0)
449 regs->pc += 4; /* next after slot */
450 else
451 #endif
452 regs->pc += SH_PC_8BIT_OFFSET(instruction);
453 }
454 break;
455 }
456 break;
457
458 case 0xA000: /* bra label */
459 ret = handle_unaligned_delayslot(regs);
460 if (ret==0)
461 regs->pc += SH_PC_12BIT_OFFSET(instruction);
462 break;
463
464 case 0xB000: /* bsr label */
465 ret = handle_unaligned_delayslot(regs);
466 if (ret==0) {
467 regs->pr = regs->pc + 4;
468 regs->pc += SH_PC_12BIT_OFFSET(instruction);
469 }
470 break;
471 }
472 return ret;
473
474 /* handle non-delay-slot instruction */
475 simple:
476 ret = handle_unaligned_ins(instruction,regs);
477 if (ret==0)
478 regs->pc += 2;
479 return ret;
480 }
481
482 /*
483 * Handle various address error exceptions
484 */
485 asmlinkage void do_address_error(struct pt_regs *regs,
486 unsigned long writeaccess,
487 unsigned long address)
488 {
489 unsigned long error_code;
490 mm_segment_t oldfs;
491 u16 instruction;
492 int tmp;
493
494 asm volatile("stc r2_bank,%0": "=r" (error_code));
495
496 oldfs = get_fs();
497
498 if (user_mode(regs)) {
499 local_irq_enable();
500 current->thread.error_code = error_code;
501 current->thread.trap_no = (writeaccess) ? 8 : 7;
502
503 /* bad PC is not something we can fix */
504 if (regs->pc & 1)
505 goto uspace_segv;
506
507 set_fs(USER_DS);
508 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
509 /* Argh. Fault on the instruction itself.
510 This should never happen non-SMP
511 */
512 set_fs(oldfs);
513 goto uspace_segv;
514 }
515
516 tmp = handle_unaligned_access(instruction, regs);
517 set_fs(oldfs);
518
519 if (tmp==0)
520 return; /* sorted */
521
522 uspace_segv:
523 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned access\n", current->comm);
524 force_sig(SIGSEGV, current);
525 } else {
526 if (regs->pc & 1)
527 die("unaligned program counter", regs, error_code);
528
529 set_fs(KERNEL_DS);
530 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
531 /* Argh. Fault on the instruction itself.
532 This should never happen non-SMP
533 */
534 set_fs(oldfs);
535 die("insn faulting in do_address_error", regs, 0);
536 }
537
538 handle_unaligned_access(instruction, regs);
539 set_fs(oldfs);
540 }
541 }
542
543 #ifdef CONFIG_SH_DSP
544 /*
545 * SH-DSP support gerg@snapgear.com.
546 */
547 int is_dsp_inst(struct pt_regs *regs)
548 {
549 unsigned short inst;
550
551 /*
552 * Safe guard if DSP mode is already enabled or we're lacking
553 * the DSP altogether.
554 */
555 if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
556 return 0;
557
558 get_user(inst, ((unsigned short *) regs->pc));
559
560 inst &= 0xf000;
561
562 /* Check for any type of DSP or support instruction */
563 if ((inst == 0xf000) || (inst == 0x4000))
564 return 1;
565
566 return 0;
567 }
568 #else
569 #define is_dsp_inst(regs) (0)
570 #endif /* CONFIG_SH_DSP */
571
572 /* arch/sh/kernel/cpu/sh4/fpu.c */
573 extern int do_fpu_inst(unsigned short, struct pt_regs *);
574 extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
575 unsigned long r6, unsigned long r7, struct pt_regs regs);
576
577 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
578 unsigned long r6, unsigned long r7,
579 struct pt_regs regs)
580 {
581 unsigned long error_code;
582 struct task_struct *tsk = current;
583
584 #ifdef CONFIG_SH_FPU_EMU
585 unsigned short inst;
586 int err;
587
588 get_user(inst, (unsigned short*)regs.pc);
589
590 err = do_fpu_inst(inst, &regs);
591 if (!err) {
592 regs.pc += 2;
593 return;
594 }
595 /* not a FPU inst. */
596 #endif
597
598 #ifdef CONFIG_SH_DSP
599 /* Check if it's a DSP instruction */
600 if (is_dsp_inst(&regs)) {
601 /* Enable DSP mode, and restart instruction. */
602 regs.sr |= SR_DSP;
603 return;
604 }
605 #endif
606
607 asm volatile("stc r2_bank, %0": "=r" (error_code));
608 local_irq_enable();
609 tsk->thread.error_code = error_code;
610 tsk->thread.trap_no = TRAP_RESERVED_INST;
611 CHK_REMOTE_DEBUG(&regs);
612 force_sig(SIGILL, tsk);
613 die_if_no_fixup("reserved instruction", &regs, error_code);
614 }
615
616 #ifdef CONFIG_SH_FPU_EMU
617 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
618 {
619 /*
620 * bfs: 8fxx: PC+=d*2+4;
621 * bts: 8dxx: PC+=d*2+4;
622 * bra: axxx: PC+=D*2+4;
623 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
624 * braf:0x23: PC+=Rn*2+4;
625 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
626 * jmp: 4x2b: PC=Rn;
627 * jsr: 4x0b: PC=Rn after PR=PC+4;
628 * rts: 000b: PC=PR;
629 */
630 if ((inst & 0xfd00) == 0x8d00) {
631 regs->pc += SH_PC_8BIT_OFFSET(inst);
632 return 0;
633 }
634
635 if ((inst & 0xe000) == 0xa000) {
636 regs->pc += SH_PC_12BIT_OFFSET(inst);
637 return 0;
638 }
639
640 if ((inst & 0xf0df) == 0x0003) {
641 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
642 return 0;
643 }
644
645 if ((inst & 0xf0df) == 0x400b) {
646 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
647 return 0;
648 }
649
650 if ((inst & 0xffff) == 0x000b) {
651 regs->pc = regs->pr;
652 return 0;
653 }
654
655 return 1;
656 }
657 #endif
658
659 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
660 unsigned long r6, unsigned long r7,
661 struct pt_regs regs)
662 {
663 unsigned long error_code;
664 struct task_struct *tsk = current;
665 #ifdef CONFIG_SH_FPU_EMU
666 unsigned short inst;
667
668 get_user(inst, (unsigned short *)regs.pc + 1);
669 if (!do_fpu_inst(inst, &regs)) {
670 get_user(inst, (unsigned short *)regs.pc);
671 if (!emulate_branch(inst, &regs))
672 return;
673 /* fault in branch.*/
674 }
675 /* not a FPU inst. */
676 #endif
677
678 asm volatile("stc r2_bank, %0": "=r" (error_code));
679 local_irq_enable();
680 tsk->thread.error_code = error_code;
681 tsk->thread.trap_no = TRAP_RESERVED_INST;
682 CHK_REMOTE_DEBUG(&regs);
683 force_sig(SIGILL, tsk);
684 die_if_no_fixup("illegal slot instruction", &regs, error_code);
685 }
686
687 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
688 unsigned long r6, unsigned long r7,
689 struct pt_regs regs)
690 {
691 long ex;
692 asm volatile("stc r2_bank, %0" : "=r" (ex));
693 die_if_kernel("exception", &regs, ex);
694 }
695
696 #if defined(CONFIG_SH_STANDARD_BIOS)
697 void *gdb_vbr_vector;
698
699 static inline void __init gdb_vbr_init(void)
700 {
701 register unsigned long vbr;
702
703 /*
704 * Read the old value of the VBR register to initialise
705 * the vector through which debug and BIOS traps are
706 * delegated by the Linux trap handler.
707 */
708 asm volatile("stc vbr, %0" : "=r" (vbr));
709
710 gdb_vbr_vector = (void *)(vbr + 0x100);
711 printk("Setting GDB trap vector to 0x%08lx\n",
712 (unsigned long)gdb_vbr_vector);
713 }
714 #endif
715
716 void __init per_cpu_trap_init(void)
717 {
718 extern void *vbr_base;
719
720 #ifdef CONFIG_SH_STANDARD_BIOS
721 gdb_vbr_init();
722 #endif
723
724 /* NOTE: The VBR value should be at P1
725 (or P2, virtural "fixed" address space).
726 It's definitely should not in physical address. */
727
728 asm volatile("ldc %0, vbr"
729 : /* no output */
730 : "r" (&vbr_base)
731 : "memory");
732 }
733
734 void *set_exception_table_vec(unsigned int vec, void *handler)
735 {
736 extern void *exception_handling_table[];
737 void *old_handler;
738
739 old_handler = exception_handling_table[vec];
740 exception_handling_table[vec] = handler;
741 return old_handler;
742 }
743
744 void __init trap_init(void)
745 {
746 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
747 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
748
749 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
750 defined(CONFIG_SH_FPU_EMU)
751 /*
752 * For SH-4 lacking an FPU, treat floating point instructions as
753 * reserved. They'll be handled in the math-emu case, or faulted on
754 * otherwise.
755 */
756 set_exception_table_evt(0x800, do_reserved_inst);
757 set_exception_table_evt(0x820, do_illegal_slot_inst);
758 #elif defined(CONFIG_SH_FPU)
759 set_exception_table_evt(0x800, do_fpu_state_restore);
760 set_exception_table_evt(0x820, do_fpu_state_restore);
761 #endif
762
763 /* Setup VBR for boot cpu */
764 per_cpu_trap_init();
765 }
766
767 void show_trace(struct task_struct *tsk, unsigned long *sp,
768 struct pt_regs *regs)
769 {
770 unsigned long addr;
771
772 if (regs && user_mode(regs))
773 return;
774
775 printk("\nCall trace: ");
776 #ifdef CONFIG_KALLSYMS
777 printk("\n");
778 #endif
779
780 while (!kstack_end(sp)) {
781 addr = *sp++;
782 if (kernel_text_address(addr))
783 print_ip_sym(addr);
784 }
785
786 printk("\n");
787 }
788
789 void show_stack(struct task_struct *tsk, unsigned long *sp)
790 {
791 unsigned long stack;
792
793 if (!tsk)
794 tsk = current;
795 if (tsk == current)
796 sp = (unsigned long *)current_stack_pointer;
797 else
798 sp = (unsigned long *)tsk->thread.sp;
799
800 stack = (unsigned long)sp;
801 dump_mem("Stack: ", stack, THREAD_SIZE +
802 (unsigned long)task_stack_page(tsk));
803 show_trace(tsk, sp, NULL);
804 }
805
806 void dump_stack(void)
807 {
808 show_stack(NULL, NULL);
809 }
810 EXPORT_SYMBOL(dump_stack);
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