arch/v850/kernel/rte_nb85e_cb.c

   1 /*
   2  * arch/v850/kernel/rte_nb85e_cb.c -- Midas labs RTE-V850E/NB85E-CB board
   3  *
   4  *  Copyright (C) 2001,02,03  NEC Electronics Corporation
   5  *  Copyright (C) 2001,02,03  Miles Bader <miles@gnu.org>
   6  *
   7  * This file is subject to the terms and conditions of the GNU General
   8  * Public License.  See the file COPYING in the main directory of this
   9  * archive for more details.
  10  *
  11  * Written by Miles Bader <miles@gnu.org>
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/mm.h>
  17 #include <linux/swap.h>
  18 #include <linux/bootmem.h>
  19 #include <linux/irq.h>
  20
  21 #include <asm/atomic.h>
  22 #include <asm/page.h>
  23 #include <asm/v850e.h>
  24 #include <asm/rte_nb85e_cb.h>
  25
  26 #include "mach.h"
  27
  28 void __init mach_early_init (void)
  29 {
  30         /* Configure caching; some possible settings:
  31
  32              BHC = 0x0000, DCC = 0x0000  -- all caching disabled
  33              BHC = 0x0040, DCC = 0x0000  -- SDRAM: icache only
  34              BHC = 0x0080, DCC = 0x0C00  -- SDRAM: write-back dcache only
  35              BHC = 0x00C0, DCC = 0x0C00  -- SDRAM: icache + write-back dcache
  36              BHC = 0x00C0, DCC = 0x0800  -- SDRAM: icache + write-thru dcache
  37
  38            We can only cache SDRAM (we can't use cache SRAM because it's in
  39            the same memory region as the on-chip RAM and I/O space).
  40
  41            Unfortunately, the dcache seems to be buggy, so we only use the
  42            icache for now.  */
  43         v850e_cache_enable (0x0040 /*BHC*/, 0x0003 /*ICC*/, 0x0000 /*DCC*/);
  44
  45         rte_cb_early_init ();
  46 }
  47
  48 void __init mach_get_physical_ram (unsigned long *ram_start,
  49                                    unsigned long *ram_len)
  50 {
  51         /* We just use SDRAM here.  */
  52         *ram_start = SDRAM_ADDR;
  53         *ram_len = SDRAM_SIZE;
  54 }
  55
  56 void mach_gettimeofday (struct timespec *tv)
  57 {
  58         tv->tv_sec = 0;
  59         tv->tv_nsec = 0;
  60 }
  61
  62 /* Called before configuring an on-chip UART.  */
  63 void rte_nb85e_cb_uart_pre_configure (unsigned chan,
  64                                     unsigned cflags, unsigned baud)
  65 {
  66         /* The RTE-NB85E-CB connects some general-purpose I/O pins on the
  67            CPU to the RTS/CTS lines the UART's serial connection, as follows:
  68            P00 = CTS (in), P01 = DSR (in), P02 = RTS (out), P03 = DTR (out). */
  69
  70         TEG_PORT0_PM = 0x03;    /* P00 and P01 inputs, P02 and P03 outputs */
  71         TEG_PORT0_IO = 0x03;    /* Accept input */
  72
  73         /* Do pre-configuration for the actual UART.  */
  74         teg_uart_pre_configure (chan, cflags, baud);
  75 }
  76
  77 void __init mach_init_irqs (void)
  78 {
  79         teg_init_irqs ();
  80         rte_cb_init_irqs ();
  81 }