arch/x86_64/kernel/genapic_flat.c

   1 /*
   2  * Copyright 2004 James Cleverdon, IBM.
   3  * Subject to the GNU Public License, v.2
   4  *
   5  * Flat APIC subarch code.
   6  *
   7  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
   8  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
   9  * James Cleverdon.
  10  */
  11 #include <linux/threads.h>
  12 #include <linux/cpumask.h>
  13 #include <linux/string.h>
  14 #include <linux/kernel.h>
  15 #include <linux/ctype.h>
  16 #include <linux/init.h>
  17 #include <asm/smp.h>
  18 #include <asm/ipi.h>
  19
  20 static cpumask_t flat_target_cpus(void)
  21 {
  22         return cpu_online_map;
  23 }
  24
  25 static cpumask_t flat_vector_allocation_domain(int cpu)
  26 {
  27         /* Careful. Some cpus do not strictly honor the set of cpus
  28          * specified in the interrupt destination when using lowest
  29          * priority interrupt delivery mode.
  30          *
  31          * In particular there was a hyperthreading cpu observed to
  32          * deliver interrupts to the wrong hyperthread when only one
  33          * hyperthread was specified in the interrupt desitination.
  34          */
  35         cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
  36         return domain;
  37 }
  38
  39 /*
  40  * Set up the logical destination ID.
  41  *
  42  * Intel recommends to set DFR, LDR and TPR before enabling
  43  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  44  * document number 292116).  So here it goes...
  45  */
  46 static void flat_init_apic_ldr(void)
  47 {
  48         unsigned long val;
  49         unsigned long num, id;
  50
  51         num = smp_processor_id();
  52         id = 1UL << num;
  53         x86_cpu_to_log_apicid[num] = id;
  54         apic_write(APIC_DFR, APIC_DFR_FLAT);
  55         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  56         val |= SET_APIC_LOGICAL_ID(id);
  57         apic_write(APIC_LDR, val);
  58 }
  59
  60 static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
  61 {
  62         unsigned long mask = cpus_addr(cpumask)[0];
  63         unsigned long cfg;
  64         unsigned long flags;
  65
  66         local_irq_save(flags);
  67
  68         /*
  69          * Wait for idle.
  70          */
  71         apic_wait_icr_idle();
  72
  73         /*
  74          * prepare target chip field
  75          */
  76         cfg = __prepare_ICR2(mask);
  77         apic_write(APIC_ICR2, cfg);
  78
  79         /*
  80          * program the ICR
  81          */
  82         cfg = __prepare_ICR(0, vector, APIC_DEST_LOGICAL);
  83
  84         /*
  85          * Send the IPI. The write to APIC_ICR fires this off.
  86          */
  87         apic_write(APIC_ICR, cfg);
  88         local_irq_restore(flags);
  89 }
  90
  91 static void flat_send_IPI_allbutself(int vector)
  92 {
  93 #ifdef  CONFIG_HOTPLUG_CPU
  94         int hotplug = 1;
  95 #else
  96         int hotplug = 0;
  97 #endif
  98         if (hotplug || vector == NMI_VECTOR) {
  99                 cpumask_t allbutme = cpu_online_map;
 100
 101                 cpu_clear(smp_processor_id(), allbutme);
 102
 103                 if (!cpus_empty(allbutme))
 104                         flat_send_IPI_mask(allbutme, vector);
 105         } else if (num_online_cpus() > 1) {
 106                 __send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
 107         }
 108 }
 109
 110 static void flat_send_IPI_all(int vector)
 111 {
 112         if (vector == NMI_VECTOR)
 113                 flat_send_IPI_mask(cpu_online_map, vector);
 114         else
 115                 __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
 116 }
 117
 118 static int flat_apic_id_registered(void)
 119 {
 120         return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map);
 121 }
 122
 123 static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
 124 {
 125         return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
 126 }
 127
 128 static unsigned int phys_pkg_id(int index_msb)
 129 {
 130         return hard_smp_processor_id() >> index_msb;
 131 }
 132
 133 struct genapic apic_flat =  {
 134         .name = "flat",
 135         .int_delivery_mode = dest_LowestPrio,
 136         .int_dest_mode = (APIC_DEST_LOGICAL != 0),
 137         .target_cpus = flat_target_cpus,
 138         .vector_allocation_domain = flat_vector_allocation_domain,
 139         .apic_id_registered = flat_apic_id_registered,
 140         .init_apic_ldr = flat_init_apic_ldr,
 141         .send_IPI_all = flat_send_IPI_all,
 142         .send_IPI_allbutself = flat_send_IPI_allbutself,
 143         .send_IPI_mask = flat_send_IPI_mask,
 144         .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
 145         .phys_pkg_id = phys_pkg_id,
 146 };
 147
 148 /*
 149  * Physflat mode is used when there are more than 8 CPUs on a AMD system.
 150  * We cannot use logical delivery in this case because the mask
 151  * overflows, so use physical mode.
 152  */
 153
 154 static cpumask_t physflat_target_cpus(void)
 155 {
 156         return cpu_online_map;
 157 }
 158
 159 static cpumask_t physflat_vector_allocation_domain(int cpu)
 160 {
 161         cpumask_t domain = CPU_MASK_NONE;
 162         cpu_set(cpu, domain);
 163         return domain;
 164 }
 165
 166
 167 static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
 168 {
 169         send_IPI_mask_sequence(cpumask, vector);
 170 }
 171
 172 static void physflat_send_IPI_allbutself(int vector)
 173 {
 174         cpumask_t allbutme = cpu_online_map;
 175
 176         cpu_clear(smp_processor_id(), allbutme);
 177         physflat_send_IPI_mask(allbutme, vector);
 178 }
 179
 180 static void physflat_send_IPI_all(int vector)
 181 {
 182         physflat_send_IPI_mask(cpu_online_map, vector);
 183 }
 184
 185 static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
 186 {
 187         int cpu;
 188
 189         /*
 190          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 191          * May as well be the first.
 192          */
 193         cpu = first_cpu(cpumask);
 194         if ((unsigned)cpu < NR_CPUS)
 195                 return x86_cpu_to_apicid[cpu];
 196         else
 197                 return BAD_APICID;
 198 }
 199
 200 struct genapic apic_physflat =  {
 201         .name = "physical flat",
 202         .int_delivery_mode = dest_Fixed,
 203         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 204         .target_cpus = physflat_target_cpus,
 205         .vector_allocation_domain = physflat_vector_allocation_domain,
 206         .apic_id_registered = flat_apic_id_registered,
 207         .init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
 208         .send_IPI_all = physflat_send_IPI_all,
 209         .send_IPI_allbutself = physflat_send_IPI_allbutself,
 210         .send_IPI_mask = physflat_send_IPI_mask,
 211         .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
 212         .phys_pkg_id = phys_pkg_id,
 213 };