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[hh.org.git] / drivers / net / pcnet32.c
blob36f9d988278f76771292c45a365a41ddd4ad478e
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #ifdef CONFIG_PCNET32_NAPI
26 #define DRV_VERSION "1.33-NAPI"
27 #else
28 #define DRV_VERSION "1.33"
29 #endif
30 #define DRV_RELDATE "27.Jun.2006"
31 #define PFX DRV_NAME ": "
32
33 static const char *const version =
34 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/string.h>
39 #include <linux/errno.h>
40 #include <linux/ioport.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <linux/ethtool.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
55
56 #include <asm/dma.h>
57 #include <asm/io.h>
58 #include <asm/uaccess.h>
59 #include <asm/irq.h>
60
61 /*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64 static struct pci_device_id pcnet32_pci_tbl[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
74
75 { } /* terminate list */
76 };
77
78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
79
80 static int cards_found;
81
82 /*
83 * VLB I/O addresses
84 */
85 static unsigned int pcnet32_portlist[] __initdata =
86 { 0x300, 0x320, 0x340, 0x360, 0 };
87
88 static int pcnet32_debug = 0;
89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb; /* check for VLB cards ? */
91
92 static struct net_device *pcnet32_dev;
93
94 static int max_interrupt_work = 2;
95 static int rx_copybreak = 200;
96
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
101
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
106
107 #define PCNET32_DMA_MASK 0xffffffff
108
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112 /*
113 * table to translate option values from tulip
114 * to internal options
115 */
116 static const unsigned char options_mapping[] = {
117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
134 };
135
136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Loopback test (offline)"
138 };
139
140 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141
142 #define PCNET32_NUM_REGS 136
143
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options[MAX_UNITS];
146 static int full_duplex[MAX_UNITS];
147 static int homepna[MAX_UNITS];
148
149 /*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
159 /*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
169 #endif
170
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
173
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
176
177 #define PKT_BUF_SZ 1544
178
179 /* Offsets from base I/O address. */
180 #define PCNET32_WIO_RDP 0x10
181 #define PCNET32_WIO_RAP 0x12
182 #define PCNET32_WIO_RESET 0x14
183 #define PCNET32_WIO_BDP 0x16
184
185 #define PCNET32_DWIO_RDP 0x10
186 #define PCNET32_DWIO_RAP 0x14
187 #define PCNET32_DWIO_RESET 0x18
188 #define PCNET32_DWIO_BDP 0x1C
189
190 #define PCNET32_TOTAL_SIZE 0x20
191
192 #define CSR0 0
193 #define CSR0_INIT 0x1
194 #define CSR0_START 0x2
195 #define CSR0_STOP 0x4
196 #define CSR0_TXPOLL 0x8
197 #define CSR0_INTEN 0x40
198 #define CSR0_IDON 0x0100
199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200 #define PCNET32_INIT_LOW 1
201 #define PCNET32_INIT_HIGH 2
202 #define CSR3 3
203 #define CSR4 4
204 #define CSR5 5
205 #define CSR5_SUSPEND 0x0001
206 #define CSR15 15
207 #define PCNET32_MC_FILTER 8
208
209 #define PCNET32_79C970A 0x2621
210
211 /* The PCNET32 Rx and Tx ring descriptors. */
212 struct pcnet32_rx_head {
213 u32 base;
214 s16 buf_length; /* two`s complement of length */
215 s16 status;
216 u32 msg_length;
217 u32 reserved;
218 };
219
220 struct pcnet32_tx_head {
221 u32 base;
222 s16 length; /* two`s complement of length */
223 s16 status;
224 u32 misc;
225 u32 reserved;
226 };
227
228 /* The PCNET32 32-Bit initialization block, described in databook. */
229 struct pcnet32_init_block {
230 u16 mode;
231 u16 tlen_rlen;
232 u8 phys_addr[6];
233 u16 reserved;
234 u32 filter[2];
235 /* Receive and transmit ring base, along with extra bits. */
236 u32 rx_ring;
237 u32 tx_ring;
238 };
239
240 /* PCnet32 access functions */
241 struct pcnet32_access {
242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
249 };
250
251 /*
252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
254 */
255 struct pcnet32_private {
256 struct pcnet32_init_block init_block;
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
260 dma_addr_t dma_addr;/* DMA address of beginning of this
261 object, returned by pci_alloc_consistent */
262 struct pci_dev *pci_dev;
263 const char *name;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
283 struct net_device_stats stats;
284 char tx_full;
285 char phycount; /* number of phys found */
286 int options;
287 unsigned int shared_irq:1, /* shared irq possible */
288 dxsuflo:1, /* disable transmit stop on uflo */
289 mii:1; /* mii port available */
290 struct net_device *next;
291 struct mii_if_info mii_if;
292 struct timer_list watchdog_timer;
293 struct timer_list blink_timer;
294 u32 msg_enable; /* debug message level */
295
296 /* each bit indicates an available PHY */
297 u32 phymask;
298 unsigned short chip_version; /* which variant this is */
299 };
300
301 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
302 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
303 static int pcnet32_open(struct net_device *);
304 static int pcnet32_init_ring(struct net_device *);
305 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
306 static void pcnet32_tx_timeout(struct net_device *dev);
307 static irqreturn_t pcnet32_interrupt(int, void *);
308 static int pcnet32_close(struct net_device *);
309 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
310 static void pcnet32_load_multicast(struct net_device *dev);
311 static void pcnet32_set_multicast_list(struct net_device *);
312 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
313 static void pcnet32_watchdog(struct net_device *);
314 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
315 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
316 int val);
317 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
318 static void pcnet32_ethtool_test(struct net_device *dev,
319 struct ethtool_test *eth_test, u64 * data);
320 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
321 static int pcnet32_phys_id(struct net_device *dev, u32 data);
322 static void pcnet32_led_blink_callback(struct net_device *dev);
323 static int pcnet32_get_regs_len(struct net_device *dev);
324 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
325 void *ptr);
326 static void pcnet32_purge_tx_ring(struct net_device *dev);
327 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
328 static void pcnet32_free_ring(struct net_device *dev);
329 static void pcnet32_check_media(struct net_device *dev, int verbose);
330
331 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
332 {
333 outw(index, addr + PCNET32_WIO_RAP);
334 return inw(addr + PCNET32_WIO_RDP);
335 }
336
337 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
338 {
339 outw(index, addr + PCNET32_WIO_RAP);
340 outw(val, addr + PCNET32_WIO_RDP);
341 }
342
343 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
344 {
345 outw(index, addr + PCNET32_WIO_RAP);
346 return inw(addr + PCNET32_WIO_BDP);
347 }
348
349 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
350 {
351 outw(index, addr + PCNET32_WIO_RAP);
352 outw(val, addr + PCNET32_WIO_BDP);
353 }
354
355 static u16 pcnet32_wio_read_rap(unsigned long addr)
356 {
357 return inw(addr + PCNET32_WIO_RAP);
358 }
359
360 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
361 {
362 outw(val, addr + PCNET32_WIO_RAP);
363 }
364
365 static void pcnet32_wio_reset(unsigned long addr)
366 {
367 inw(addr + PCNET32_WIO_RESET);
368 }
369
370 static int pcnet32_wio_check(unsigned long addr)
371 {
372 outw(88, addr + PCNET32_WIO_RAP);
373 return (inw(addr + PCNET32_WIO_RAP) == 88);
374 }
375
376 static struct pcnet32_access pcnet32_wio = {
377 .read_csr = pcnet32_wio_read_csr,
378 .write_csr = pcnet32_wio_write_csr,
379 .read_bcr = pcnet32_wio_read_bcr,
380 .write_bcr = pcnet32_wio_write_bcr,
381 .read_rap = pcnet32_wio_read_rap,
382 .write_rap = pcnet32_wio_write_rap,
383 .reset = pcnet32_wio_reset
384 };
385
386 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
387 {
388 outl(index, addr + PCNET32_DWIO_RAP);
389 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
390 }
391
392 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
393 {
394 outl(index, addr + PCNET32_DWIO_RAP);
395 outl(val, addr + PCNET32_DWIO_RDP);
396 }
397
398 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
399 {
400 outl(index, addr + PCNET32_DWIO_RAP);
401 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
402 }
403
404 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
405 {
406 outl(index, addr + PCNET32_DWIO_RAP);
407 outl(val, addr + PCNET32_DWIO_BDP);
408 }
409
410 static u16 pcnet32_dwio_read_rap(unsigned long addr)
411 {
412 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
413 }
414
415 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
416 {
417 outl(val, addr + PCNET32_DWIO_RAP);
418 }
419
420 static void pcnet32_dwio_reset(unsigned long addr)
421 {
422 inl(addr + PCNET32_DWIO_RESET);
423 }
424
425 static int pcnet32_dwio_check(unsigned long addr)
426 {
427 outl(88, addr + PCNET32_DWIO_RAP);
428 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
429 }
430
431 static struct pcnet32_access pcnet32_dwio = {
432 .read_csr = pcnet32_dwio_read_csr,
433 .write_csr = pcnet32_dwio_write_csr,
434 .read_bcr = pcnet32_dwio_read_bcr,
435 .write_bcr = pcnet32_dwio_write_bcr,
436 .read_rap = pcnet32_dwio_read_rap,
437 .write_rap = pcnet32_dwio_write_rap,
438 .reset = pcnet32_dwio_reset
439 };
440
441 static void pcnet32_netif_stop(struct net_device *dev)
442 {
443 dev->trans_start = jiffies;
444 netif_poll_disable(dev);
445 netif_tx_disable(dev);
446 }
447
448 static void pcnet32_netif_start(struct net_device *dev)
449 {
450 netif_wake_queue(dev);
451 netif_poll_enable(dev);
452 }
453
454 /*
455 * Allocate space for the new sized tx ring.
456 * Free old resources
457 * Save new resources.
458 * Any failure keeps old resources.
459 * Must be called with lp->lock held.
460 */
461 static void pcnet32_realloc_tx_ring(struct net_device *dev,
462 struct pcnet32_private *lp,
463 unsigned int size)
464 {
465 dma_addr_t new_ring_dma_addr;
466 dma_addr_t *new_dma_addr_list;
467 struct pcnet32_tx_head *new_tx_ring;
468 struct sk_buff **new_skb_list;
469
470 pcnet32_purge_tx_ring(dev);
471
472 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
473 sizeof(struct pcnet32_tx_head) *
474 (1 << size),
475 &new_ring_dma_addr);
476 if (new_tx_ring == NULL) {
477 if (netif_msg_drv(lp))
478 printk("\n" KERN_ERR
479 "%s: Consistent memory allocation failed.\n",
480 dev->name);
481 return;
482 }
483 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
484
485 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
486 GFP_ATOMIC);
487 if (!new_dma_addr_list) {
488 if (netif_msg_drv(lp))
489 printk("\n" KERN_ERR
490 "%s: Memory allocation failed.\n", dev->name);
491 goto free_new_tx_ring;
492 }
493
494 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
495 GFP_ATOMIC);
496 if (!new_skb_list) {
497 if (netif_msg_drv(lp))
498 printk("\n" KERN_ERR
499 "%s: Memory allocation failed.\n", dev->name);
500 goto free_new_lists;
501 }
502
503 kfree(lp->tx_skbuff);
504 kfree(lp->tx_dma_addr);
505 pci_free_consistent(lp->pci_dev,
506 sizeof(struct pcnet32_tx_head) *
507 lp->tx_ring_size, lp->tx_ring,
508 lp->tx_ring_dma_addr);
509
510 lp->tx_ring_size = (1 << size);
511 lp->tx_mod_mask = lp->tx_ring_size - 1;
512 lp->tx_len_bits = (size << 12);
513 lp->tx_ring = new_tx_ring;
514 lp->tx_ring_dma_addr = new_ring_dma_addr;
515 lp->tx_dma_addr = new_dma_addr_list;
516 lp->tx_skbuff = new_skb_list;
517 return;
518
519 free_new_lists:
520 kfree(new_dma_addr_list);
521 free_new_tx_ring:
522 pci_free_consistent(lp->pci_dev,
523 sizeof(struct pcnet32_tx_head) *
524 (1 << size),
525 new_tx_ring,
526 new_ring_dma_addr);
527 return;
528 }
529
530 /*
531 * Allocate space for the new sized rx ring.
532 * Re-use old receive buffers.
533 * alloc extra buffers
534 * free unneeded buffers
535 * free unneeded buffers
536 * Save new resources.
537 * Any failure keeps old resources.
538 * Must be called with lp->lock held.
539 */
540 static void pcnet32_realloc_rx_ring(struct net_device *dev,
541 struct pcnet32_private *lp,
542 unsigned int size)
543 {
544 dma_addr_t new_ring_dma_addr;
545 dma_addr_t *new_dma_addr_list;
546 struct pcnet32_rx_head *new_rx_ring;
547 struct sk_buff **new_skb_list;
548 int new, overlap;
549
550 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
551 sizeof(struct pcnet32_rx_head) *
552 (1 << size),
553 &new_ring_dma_addr);
554 if (new_rx_ring == NULL) {
555 if (netif_msg_drv(lp))
556 printk("\n" KERN_ERR
557 "%s: Consistent memory allocation failed.\n",
558 dev->name);
559 return;
560 }
561 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
562
563 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
564 GFP_ATOMIC);
565 if (!new_dma_addr_list) {
566 if (netif_msg_drv(lp))
567 printk("\n" KERN_ERR
568 "%s: Memory allocation failed.\n", dev->name);
569 goto free_new_rx_ring;
570 }
571
572 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
573 GFP_ATOMIC);
574 if (!new_skb_list) {
575 if (netif_msg_drv(lp))
576 printk("\n" KERN_ERR
577 "%s: Memory allocation failed.\n", dev->name);
578 goto free_new_lists;
579 }
580
581 /* first copy the current receive buffers */
582 overlap = min(size, lp->rx_ring_size);
583 for (new = 0; new < overlap; new++) {
584 new_rx_ring[new] = lp->rx_ring[new];
585 new_dma_addr_list[new] = lp->rx_dma_addr[new];
586 new_skb_list[new] = lp->rx_skbuff[new];
587 }
588 /* now allocate any new buffers needed */
589 for (; new < size; new++ ) {
590 struct sk_buff *rx_skbuff;
591 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
592 if (!(rx_skbuff = new_skb_list[new])) {
593 /* keep the original lists and buffers */
594 if (netif_msg_drv(lp))
595 printk(KERN_ERR
596 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
597 dev->name);
598 goto free_all_new;
599 }
600 skb_reserve(rx_skbuff, 2);
601
602 new_dma_addr_list[new] =
603 pci_map_single(lp->pci_dev, rx_skbuff->data,
604 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
605 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
606 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
607 new_rx_ring[new].status = le16_to_cpu(0x8000);
608 }
609 /* and free any unneeded buffers */
610 for (; new < lp->rx_ring_size; new++) {
611 if (lp->rx_skbuff[new]) {
612 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
613 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
614 dev_kfree_skb(lp->rx_skbuff[new]);
615 }
616 }
617
618 kfree(lp->rx_skbuff);
619 kfree(lp->rx_dma_addr);
620 pci_free_consistent(lp->pci_dev,
621 sizeof(struct pcnet32_rx_head) *
622 lp->rx_ring_size, lp->rx_ring,
623 lp->rx_ring_dma_addr);
624
625 lp->rx_ring_size = (1 << size);
626 lp->rx_mod_mask = lp->rx_ring_size - 1;
627 lp->rx_len_bits = (size << 4);
628 lp->rx_ring = new_rx_ring;
629 lp->rx_ring_dma_addr = new_ring_dma_addr;
630 lp->rx_dma_addr = new_dma_addr_list;
631 lp->rx_skbuff = new_skb_list;
632 return;
633
634 free_all_new:
635 for (; --new >= lp->rx_ring_size; ) {
636 if (new_skb_list[new]) {
637 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
638 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
639 dev_kfree_skb(new_skb_list[new]);
640 }
641 }
642 kfree(new_skb_list);
643 free_new_lists:
644 kfree(new_dma_addr_list);
645 free_new_rx_ring:
646 pci_free_consistent(lp->pci_dev,
647 sizeof(struct pcnet32_rx_head) *
648 (1 << size),
649 new_rx_ring,
650 new_ring_dma_addr);
651 return;
652 }
653
654 static void pcnet32_purge_rx_ring(struct net_device *dev)
655 {
656 struct pcnet32_private *lp = dev->priv;
657 int i;
658
659 /* free all allocated skbuffs */
660 for (i = 0; i < lp->rx_ring_size; i++) {
661 lp->rx_ring[i].status = 0; /* CPU owns buffer */
662 wmb(); /* Make sure adapter sees owner change */
663 if (lp->rx_skbuff[i]) {
664 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
665 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
666 dev_kfree_skb_any(lp->rx_skbuff[i]);
667 }
668 lp->rx_skbuff[i] = NULL;
669 lp->rx_dma_addr[i] = 0;
670 }
671 }
672
673 #ifdef CONFIG_NET_POLL_CONTROLLER
674 static void pcnet32_poll_controller(struct net_device *dev)
675 {
676 disable_irq(dev->irq);
677 pcnet32_interrupt(0, dev);
678 enable_irq(dev->irq);
679 }
680 #endif
681
682 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
683 {
684 struct pcnet32_private *lp = dev->priv;
685 unsigned long flags;
686 int r = -EOPNOTSUPP;
687
688 if (lp->mii) {
689 spin_lock_irqsave(&lp->lock, flags);
690 mii_ethtool_gset(&lp->mii_if, cmd);
691 spin_unlock_irqrestore(&lp->lock, flags);
692 r = 0;
693 }
694 return r;
695 }
696
697 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
698 {
699 struct pcnet32_private *lp = dev->priv;
700 unsigned long flags;
701 int r = -EOPNOTSUPP;
702
703 if (lp->mii) {
704 spin_lock_irqsave(&lp->lock, flags);
705 r = mii_ethtool_sset(&lp->mii_if, cmd);
706 spin_unlock_irqrestore(&lp->lock, flags);
707 }
708 return r;
709 }
710
711 static void pcnet32_get_drvinfo(struct net_device *dev,
712 struct ethtool_drvinfo *info)
713 {
714 struct pcnet32_private *lp = dev->priv;
715
716 strcpy(info->driver, DRV_NAME);
717 strcpy(info->version, DRV_VERSION);
718 if (lp->pci_dev)
719 strcpy(info->bus_info, pci_name(lp->pci_dev));
720 else
721 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
722 }
723
724 static u32 pcnet32_get_link(struct net_device *dev)
725 {
726 struct pcnet32_private *lp = dev->priv;
727 unsigned long flags;
728 int r;
729
730 spin_lock_irqsave(&lp->lock, flags);
731 if (lp->mii) {
732 r = mii_link_ok(&lp->mii_if);
733 } else if (lp->chip_version >= PCNET32_79C970A) {
734 ulong ioaddr = dev->base_addr; /* card base I/O address */
735 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
736 } else { /* can not detect link on really old chips */
737 r = 1;
738 }
739 spin_unlock_irqrestore(&lp->lock, flags);
740
741 return r;
742 }
743
744 static u32 pcnet32_get_msglevel(struct net_device *dev)
745 {
746 struct pcnet32_private *lp = dev->priv;
747 return lp->msg_enable;
748 }
749
750 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
751 {
752 struct pcnet32_private *lp = dev->priv;
753 lp->msg_enable = value;
754 }
755
756 static int pcnet32_nway_reset(struct net_device *dev)
757 {
758 struct pcnet32_private *lp = dev->priv;
759 unsigned long flags;
760 int r = -EOPNOTSUPP;
761
762 if (lp->mii) {
763 spin_lock_irqsave(&lp->lock, flags);
764 r = mii_nway_restart(&lp->mii_if);
765 spin_unlock_irqrestore(&lp->lock, flags);
766 }
767 return r;
768 }
769
770 static void pcnet32_get_ringparam(struct net_device *dev,
771 struct ethtool_ringparam *ering)
772 {
773 struct pcnet32_private *lp = dev->priv;
774
775 ering->tx_max_pending = TX_MAX_RING_SIZE;
776 ering->tx_pending = lp->tx_ring_size;
777 ering->rx_max_pending = RX_MAX_RING_SIZE;
778 ering->rx_pending = lp->rx_ring_size;
779 }
780
781 static int pcnet32_set_ringparam(struct net_device *dev,
782 struct ethtool_ringparam *ering)
783 {
784 struct pcnet32_private *lp = dev->priv;
785 unsigned long flags;
786 unsigned int size;
787 ulong ioaddr = dev->base_addr;
788 int i;
789
790 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
791 return -EINVAL;
792
793 if (netif_running(dev))
794 pcnet32_netif_stop(dev);
795
796 spin_lock_irqsave(&lp->lock, flags);
797 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
798
799 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
800
801 /* set the minimum ring size to 4, to allow the loopback test to work
802 * unchanged.
803 */
804 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
805 if (size <= (1 << i))
806 break;
807 }
808 if ((1 << i) != lp->tx_ring_size)
809 pcnet32_realloc_tx_ring(dev, lp, i);
810
811 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
812 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
813 if (size <= (1 << i))
814 break;
815 }
816 if ((1 << i) != lp->rx_ring_size)
817 pcnet32_realloc_rx_ring(dev, lp, i);
818
819 dev->weight = lp->rx_ring_size / 2;
820
821 if (netif_running(dev)) {
822 pcnet32_netif_start(dev);
823 pcnet32_restart(dev, CSR0_NORMAL);
824 }
825
826 spin_unlock_irqrestore(&lp->lock, flags);
827
828 if (netif_msg_drv(lp))
829 printk(KERN_INFO
830 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
831 lp->rx_ring_size, lp->tx_ring_size);
832
833 return 0;
834 }
835
836 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
837 u8 * data)
838 {
839 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
840 }
841
842 static int pcnet32_self_test_count(struct net_device *dev)
843 {
844 return PCNET32_TEST_LEN;
845 }
846
847 static void pcnet32_ethtool_test(struct net_device *dev,
848 struct ethtool_test *test, u64 * data)
849 {
850 struct pcnet32_private *lp = dev->priv;
851 int rc;
852
853 if (test->flags == ETH_TEST_FL_OFFLINE) {
854 rc = pcnet32_loopback_test(dev, data);
855 if (rc) {
856 if (netif_msg_hw(lp))
857 printk(KERN_DEBUG "%s: Loopback test failed.\n",
858 dev->name);
859 test->flags |= ETH_TEST_FL_FAILED;
860 } else if (netif_msg_hw(lp))
861 printk(KERN_DEBUG "%s: Loopback test passed.\n",
862 dev->name);
863 } else if (netif_msg_hw(lp))
864 printk(KERN_DEBUG
865 "%s: No tests to run (specify 'Offline' on ethtool).",
866 dev->name);
867 } /* end pcnet32_ethtool_test */
868
869 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
870 {
871 struct pcnet32_private *lp = dev->priv;
872 struct pcnet32_access *a = &lp->a; /* access to registers */
873 ulong ioaddr = dev->base_addr; /* card base I/O address */
874 struct sk_buff *skb; /* sk buff */
875 int x, i; /* counters */
876 int numbuffs = 4; /* number of TX/RX buffers and descs */
877 u16 status = 0x8300; /* TX ring status */
878 u16 teststatus; /* test of ring status */
879 int rc; /* return code */
880 int size; /* size of packets */
881 unsigned char *packet; /* source packet data */
882 static const int data_len = 60; /* length of source packets */
883 unsigned long flags;
884 unsigned long ticks;
885
886 rc = 1; /* default to fail */
887
888 if (netif_running(dev))
889 #ifdef CONFIG_PCNET32_NAPI
890 pcnet32_netif_stop(dev);
891 #else
892 pcnet32_close(dev);
893 #endif
894
895 spin_lock_irqsave(&lp->lock, flags);
896 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
897
898 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
899
900 /* Reset the PCNET32 */
901 lp->a.reset(ioaddr);
902 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
903
904 /* switch pcnet32 to 32bit mode */
905 lp->a.write_bcr(ioaddr, 20, 2);
906
907 /* purge & init rings but don't actually restart */
908 pcnet32_restart(dev, 0x0000);
909
910 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
911
912 /* Initialize Transmit buffers. */
913 size = data_len + 15;
914 for (x = 0; x < numbuffs; x++) {
915 if (!(skb = dev_alloc_skb(size))) {
916 if (netif_msg_hw(lp))
917 printk(KERN_DEBUG
918 "%s: Cannot allocate skb at line: %d!\n",
919 dev->name, __LINE__);
920 goto clean_up;
921 } else {
922 packet = skb->data;
923 skb_put(skb, size); /* create space for data */
924 lp->tx_skbuff[x] = skb;
925 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
926 lp->tx_ring[x].misc = 0;
927
928 /* put DA and SA into the skb */
929 for (i = 0; i < 6; i++)
930 *packet++ = dev->dev_addr[i];
931 for (i = 0; i < 6; i++)
932 *packet++ = dev->dev_addr[i];
933 /* type */
934 *packet++ = 0x08;
935 *packet++ = 0x06;
936 /* packet number */
937 *packet++ = x;
938 /* fill packet with data */
939 for (i = 0; i < data_len; i++)
940 *packet++ = i;
941
942 lp->tx_dma_addr[x] =
943 pci_map_single(lp->pci_dev, skb->data, skb->len,
944 PCI_DMA_TODEVICE);
945 lp->tx_ring[x].base =
946 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
947 wmb(); /* Make sure owner changes after all others are visible */
948 lp->tx_ring[x].status = le16_to_cpu(status);
949 }
950 }
951
952 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
953 a->write_bcr(ioaddr, 32, x | 0x0002);
954
955 /* set int loopback in CSR15 */
956 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
957 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
958
959 teststatus = le16_to_cpu(0x8000);
960 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
961
962 /* Check status of descriptors */
963 for (x = 0; x < numbuffs; x++) {
964 ticks = 0;
965 rmb();
966 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
967 spin_unlock_irqrestore(&lp->lock, flags);
968 msleep(1);
969 spin_lock_irqsave(&lp->lock, flags);
970 rmb();
971 ticks++;
972 }
973 if (ticks == 200) {
974 if (netif_msg_hw(lp))
975 printk("%s: Desc %d failed to reset!\n",
976 dev->name, x);
977 break;
978 }
979 }
980
981 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
982 wmb();
983 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
984 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
985
986 for (x = 0; x < numbuffs; x++) {
987 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
988 skb = lp->rx_skbuff[x];
989 for (i = 0; i < size; i++) {
990 printk("%02x ", *(skb->data + i));
991 }
992 printk("\n");
993 }
994 }
995
996 x = 0;
997 rc = 0;
998 while (x < numbuffs && !rc) {
999 skb = lp->rx_skbuff[x];
1000 packet = lp->tx_skbuff[x]->data;
1001 for (i = 0; i < size; i++) {
1002 if (*(skb->data + i) != packet[i]) {
1003 if (netif_msg_hw(lp))
1004 printk(KERN_DEBUG
1005 "%s: Error in compare! %2x - %02x %02x\n",
1006 dev->name, i, *(skb->data + i),
1007 packet[i]);
1008 rc = 1;
1009 break;
1010 }
1011 }
1012 x++;
1013 }
1014
1015 clean_up:
1016 *data1 = rc;
1017 pcnet32_purge_tx_ring(dev);
1018
1019 x = a->read_csr(ioaddr, CSR15);
1020 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1021
1022 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1023 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1024
1025 #ifdef CONFIG_PCNET32_NAPI
1026 if (netif_running(dev)) {
1027 pcnet32_netif_start(dev);
1028 pcnet32_restart(dev, CSR0_NORMAL);
1029 } else {
1030 pcnet32_purge_rx_ring(dev);
1031 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1032 }
1033 spin_unlock_irqrestore(&lp->lock, flags);
1034 #else
1035 if (netif_running(dev)) {
1036 spin_unlock_irqrestore(&lp->lock, flags);
1037 pcnet32_open(dev);
1038 } else {
1039 pcnet32_purge_rx_ring(dev);
1040 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1041 spin_unlock_irqrestore(&lp->lock, flags);
1042 }
1043 #endif
1044
1045 return (rc);
1046 } /* end pcnet32_loopback_test */
1047
1048 static void pcnet32_led_blink_callback(struct net_device *dev)
1049 {
1050 struct pcnet32_private *lp = dev->priv;
1051 struct pcnet32_access *a = &lp->a;
1052 ulong ioaddr = dev->base_addr;
1053 unsigned long flags;
1054 int i;
1055
1056 spin_lock_irqsave(&lp->lock, flags);
1057 for (i = 4; i < 8; i++) {
1058 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1059 }
1060 spin_unlock_irqrestore(&lp->lock, flags);
1061
1062 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1063 }
1064
1065 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1066 {
1067 struct pcnet32_private *lp = dev->priv;
1068 struct pcnet32_access *a = &lp->a;
1069 ulong ioaddr = dev->base_addr;
1070 unsigned long flags;
1071 int i, regs[4];
1072
1073 if (!lp->blink_timer.function) {
1074 init_timer(&lp->blink_timer);
1075 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1076 lp->blink_timer.data = (unsigned long)dev;
1077 }
1078
1079 /* Save the current value of the bcrs */
1080 spin_lock_irqsave(&lp->lock, flags);
1081 for (i = 4; i < 8; i++) {
1082 regs[i - 4] = a->read_bcr(ioaddr, i);
1083 }
1084 spin_unlock_irqrestore(&lp->lock, flags);
1085
1086 mod_timer(&lp->blink_timer, jiffies);
1087 set_current_state(TASK_INTERRUPTIBLE);
1088
1089 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1090 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1091
1092 msleep_interruptible(data * 1000);
1093 del_timer_sync(&lp->blink_timer);
1094
1095 /* Restore the original value of the bcrs */
1096 spin_lock_irqsave(&lp->lock, flags);
1097 for (i = 4; i < 8; i++) {
1098 a->write_bcr(ioaddr, i, regs[i - 4]);
1099 }
1100 spin_unlock_irqrestore(&lp->lock, flags);
1101
1102 return 0;
1103 }
1104
1105 /*
1106 * lp->lock must be held.
1107 */
1108 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1109 int can_sleep)
1110 {
1111 int csr5;
1112 struct pcnet32_private *lp = dev->priv;
1113 struct pcnet32_access *a = &lp->a;
1114 ulong ioaddr = dev->base_addr;
1115 int ticks;
1116
1117 /* really old chips have to be stopped. */
1118 if (lp->chip_version < PCNET32_79C970A)
1119 return 0;
1120
1121 /* set SUSPEND (SPND) - CSR5 bit 0 */
1122 csr5 = a->read_csr(ioaddr, CSR5);
1123 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1124
1125 /* poll waiting for bit to be set */
1126 ticks = 0;
1127 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1128 spin_unlock_irqrestore(&lp->lock, *flags);
1129 if (can_sleep)
1130 msleep(1);
1131 else
1132 mdelay(1);
1133 spin_lock_irqsave(&lp->lock, *flags);
1134 ticks++;
1135 if (ticks > 200) {
1136 if (netif_msg_hw(lp))
1137 printk(KERN_DEBUG
1138 "%s: Error getting into suspend!\n",
1139 dev->name);
1140 return 0;
1141 }
1142 }
1143 return 1;
1144 }
1145
1146 /*
1147 * process one receive descriptor entry
1148 */
1149
1150 static void pcnet32_rx_entry(struct net_device *dev,
1151 struct pcnet32_private *lp,
1152 struct pcnet32_rx_head *rxp,
1153 int entry)
1154 {
1155 int status = (short)le16_to_cpu(rxp->status) >> 8;
1156 int rx_in_place = 0;
1157 struct sk_buff *skb;
1158 short pkt_len;
1159
1160 if (status != 0x03) { /* There was an error. */
1161 /*
1162 * There is a tricky error noted by John Murphy,
1163 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1164 * buffers it's possible for a jabber packet to use two
1165 * buffers, with only the last correctly noting the error.
1166 */
1167 if (status & 0x01) /* Only count a general error at the */
1168 lp->stats.rx_errors++; /* end of a packet. */
1169 if (status & 0x20)
1170 lp->stats.rx_frame_errors++;
1171 if (status & 0x10)
1172 lp->stats.rx_over_errors++;
1173 if (status & 0x08)
1174 lp->stats.rx_crc_errors++;
1175 if (status & 0x04)
1176 lp->stats.rx_fifo_errors++;
1177 return;
1178 }
1179
1180 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1181
1182 /* Discard oversize frames. */
1183 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1184 if (netif_msg_drv(lp))
1185 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1186 dev->name, pkt_len);
1187 lp->stats.rx_errors++;
1188 return;
1189 }
1190 if (pkt_len < 60) {
1191 if (netif_msg_rx_err(lp))
1192 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1193 lp->stats.rx_errors++;
1194 return;
1195 }
1196
1197 if (pkt_len > rx_copybreak) {
1198 struct sk_buff *newskb;
1199
1200 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1201 skb_reserve(newskb, 2);
1202 skb = lp->rx_skbuff[entry];
1203 pci_unmap_single(lp->pci_dev,
1204 lp->rx_dma_addr[entry],
1205 PKT_BUF_SZ - 2,
1206 PCI_DMA_FROMDEVICE);
1207 skb_put(skb, pkt_len);
1208 lp->rx_skbuff[entry] = newskb;
1209 newskb->dev = dev;
1210 lp->rx_dma_addr[entry] =
1211 pci_map_single(lp->pci_dev,
1212 newskb->data,
1213 PKT_BUF_SZ - 2,
1214 PCI_DMA_FROMDEVICE);
1215 rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
1216 rx_in_place = 1;
1217 } else
1218 skb = NULL;
1219 } else {
1220 skb = dev_alloc_skb(pkt_len + 2);
1221 }
1222
1223 if (skb == NULL) {
1224 if (netif_msg_drv(lp))
1225 printk(KERN_ERR
1226 "%s: Memory squeeze, dropping packet.\n",
1227 dev->name);
1228 lp->stats.rx_dropped++;
1229 return;
1230 }
1231 skb->dev = dev;
1232 if (!rx_in_place) {
1233 skb_reserve(skb, 2); /* 16 byte align */
1234 skb_put(skb, pkt_len); /* Make room */
1235 pci_dma_sync_single_for_cpu(lp->pci_dev,
1236 lp->rx_dma_addr[entry],
1237 PKT_BUF_SZ - 2,
1238 PCI_DMA_FROMDEVICE);
1239 eth_copy_and_sum(skb,
1240 (unsigned char *)(lp->rx_skbuff[entry]->data),
1241 pkt_len, 0);
1242 pci_dma_sync_single_for_device(lp->pci_dev,
1243 lp->rx_dma_addr[entry],
1244 PKT_BUF_SZ - 2,
1245 PCI_DMA_FROMDEVICE);
1246 }
1247 lp->stats.rx_bytes += skb->len;
1248 skb->protocol = eth_type_trans(skb, dev);
1249 #ifdef CONFIG_PCNET32_NAPI
1250 netif_receive_skb(skb);
1251 #else
1252 netif_rx(skb);
1253 #endif
1254 dev->last_rx = jiffies;
1255 lp->stats.rx_packets++;
1256 return;
1257 }
1258
1259 static int pcnet32_rx(struct net_device *dev, int quota)
1260 {
1261 struct pcnet32_private *lp = dev->priv;
1262 int entry = lp->cur_rx & lp->rx_mod_mask;
1263 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1264 int npackets = 0;
1265
1266 /* If we own the next entry, it's a new packet. Send it up. */
1267 while (quota > npackets && (short)le16_to_cpu(rxp->status) >= 0) {
1268 pcnet32_rx_entry(dev, lp, rxp, entry);
1269 npackets += 1;
1270 /*
1271 * The docs say that the buffer length isn't touched, but Andrew
1272 * Boyd of QNX reports that some revs of the 79C965 clear it.
1273 */
1274 rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1275 wmb(); /* Make sure owner changes after others are visible */
1276 rxp->status = le16_to_cpu(0x8000);
1277 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1278 rxp = &lp->rx_ring[entry];
1279 }
1280
1281 return npackets;
1282 }
1283
1284 static int pcnet32_tx(struct net_device *dev)
1285 {
1286 struct pcnet32_private *lp = dev->priv;
1287 unsigned int dirty_tx = lp->dirty_tx;
1288 int delta;
1289 int must_restart = 0;
1290
1291 while (dirty_tx != lp->cur_tx) {
1292 int entry = dirty_tx & lp->tx_mod_mask;
1293 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1294
1295 if (status < 0)
1296 break; /* It still hasn't been Txed */
1297
1298 lp->tx_ring[entry].base = 0;
1299
1300 if (status & 0x4000) {
1301 /* There was a major error, log it. */
1302 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1303 lp->stats.tx_errors++;
1304 if (netif_msg_tx_err(lp))
1305 printk(KERN_ERR
1306 "%s: Tx error status=%04x err_status=%08x\n",
1307 dev->name, status,
1308 err_status);
1309 if (err_status & 0x04000000)
1310 lp->stats.tx_aborted_errors++;
1311 if (err_status & 0x08000000)
1312 lp->stats.tx_carrier_errors++;
1313 if (err_status & 0x10000000)
1314 lp->stats.tx_window_errors++;
1315 #ifndef DO_DXSUFLO
1316 if (err_status & 0x40000000) {
1317 lp->stats.tx_fifo_errors++;
1318 /* Ackk! On FIFO errors the Tx unit is turned off! */
1319 /* Remove this verbosity later! */
1320 if (netif_msg_tx_err(lp))
1321 printk(KERN_ERR
1322 "%s: Tx FIFO error!\n",
1323 dev->name);
1324 must_restart = 1;
1325 }
1326 #else
1327 if (err_status & 0x40000000) {
1328 lp->stats.tx_fifo_errors++;
1329 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1330 /* Ackk! On FIFO errors the Tx unit is turned off! */
1331 /* Remove this verbosity later! */
1332 if (netif_msg_tx_err(lp))
1333 printk(KERN_ERR
1334 "%s: Tx FIFO error!\n",
1335 dev->name);
1336 must_restart = 1;
1337 }
1338 }
1339 #endif
1340 } else {
1341 if (status & 0x1800)
1342 lp->stats.collisions++;
1343 lp->stats.tx_packets++;
1344 }
1345
1346 /* We must free the original skb */
1347 if (lp->tx_skbuff[entry]) {
1348 pci_unmap_single(lp->pci_dev,
1349 lp->tx_dma_addr[entry],
1350 lp->tx_skbuff[entry]->
1351 len, PCI_DMA_TODEVICE);
1352 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1353 lp->tx_skbuff[entry] = NULL;
1354 lp->tx_dma_addr[entry] = 0;
1355 }
1356 dirty_tx++;
1357 }
1358
1359 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1360 if (delta > lp->tx_ring_size) {
1361 if (netif_msg_drv(lp))
1362 printk(KERN_ERR
1363 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1364 dev->name, dirty_tx, lp->cur_tx,
1365 lp->tx_full);
1366 dirty_tx += lp->tx_ring_size;
1367 delta -= lp->tx_ring_size;
1368 }
1369
1370 if (lp->tx_full &&
1371 netif_queue_stopped(dev) &&
1372 delta < lp->tx_ring_size - 2) {
1373 /* The ring is no longer full, clear tbusy. */
1374 lp->tx_full = 0;
1375 netif_wake_queue(dev);
1376 }
1377 lp->dirty_tx = dirty_tx;
1378
1379 return must_restart;
1380 }
1381
1382 #ifdef CONFIG_PCNET32_NAPI
1383 static int pcnet32_poll(struct net_device *dev, int *budget)
1384 {
1385 struct pcnet32_private *lp = dev->priv;
1386 int quota = min(dev->quota, *budget);
1387 unsigned long ioaddr = dev->base_addr;
1388 unsigned long flags;
1389 u16 val;
1390
1391 quota = pcnet32_rx(dev, quota);
1392
1393 spin_lock_irqsave(&lp->lock, flags);
1394 if (pcnet32_tx(dev)) {
1395 /* reset the chip to clear the error condition, then restart */
1396 lp->a.reset(ioaddr);
1397 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1398 pcnet32_restart(dev, CSR0_START);
1399 netif_wake_queue(dev);
1400 }
1401 spin_unlock_irqrestore(&lp->lock, flags);
1402
1403 *budget -= quota;
1404 dev->quota -= quota;
1405
1406 if (dev->quota == 0) {
1407 return 1;
1408 }
1409
1410 netif_rx_complete(dev);
1411
1412 spin_lock_irqsave(&lp->lock, flags);
1413
1414 /* clear interrupt masks */
1415 val = lp->a.read_csr(ioaddr, CSR3);
1416 val &= 0x00ff;
1417 lp->a.write_csr(ioaddr, CSR3, val);
1418
1419 /* Set interrupt enable. */
1420 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1421 mmiowb();
1422 spin_unlock_irqrestore(&lp->lock, flags);
1423
1424 return 0;
1425 }
1426 #endif
1427
1428 #define PCNET32_REGS_PER_PHY 32
1429 #define PCNET32_MAX_PHYS 32
1430 static int pcnet32_get_regs_len(struct net_device *dev)
1431 {
1432 struct pcnet32_private *lp = dev->priv;
1433 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1434
1435 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1436 }
1437
1438 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1439 void *ptr)
1440 {
1441 int i, csr0;
1442 u16 *buff = ptr;
1443 struct pcnet32_private *lp = dev->priv;
1444 struct pcnet32_access *a = &lp->a;
1445 ulong ioaddr = dev->base_addr;
1446 unsigned long flags;
1447
1448 spin_lock_irqsave(&lp->lock, flags);
1449
1450 csr0 = a->read_csr(ioaddr, CSR0);
1451 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1452 pcnet32_suspend(dev, &flags, 1);
1453
1454 /* read address PROM */
1455 for (i = 0; i < 16; i += 2)
1456 *buff++ = inw(ioaddr + i);
1457
1458 /* read control and status registers */
1459 for (i = 0; i < 90; i++) {
1460 *buff++ = a->read_csr(ioaddr, i);
1461 }
1462
1463 *buff++ = a->read_csr(ioaddr, 112);
1464 *buff++ = a->read_csr(ioaddr, 114);
1465
1466 /* read bus configuration registers */
1467 for (i = 0; i < 30; i++) {
1468 *buff++ = a->read_bcr(ioaddr, i);
1469 }
1470 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1471 for (i = 31; i < 36; i++) {
1472 *buff++ = a->read_bcr(ioaddr, i);
1473 }
1474
1475 /* read mii phy registers */
1476 if (lp->mii) {
1477 int j;
1478 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1479 if (lp->phymask & (1 << j)) {
1480 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1481 lp->a.write_bcr(ioaddr, 33,
1482 (j << 5) | i);
1483 *buff++ = lp->a.read_bcr(ioaddr, 34);
1484 }
1485 }
1486 }
1487 }
1488
1489 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1490 int csr5;
1491
1492 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1493 csr5 = a->read_csr(ioaddr, CSR5);
1494 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1495 }
1496
1497 spin_unlock_irqrestore(&lp->lock, flags);
1498 }
1499
1500 static const struct ethtool_ops pcnet32_ethtool_ops = {
1501 .get_settings = pcnet32_get_settings,
1502 .set_settings = pcnet32_set_settings,
1503 .get_drvinfo = pcnet32_get_drvinfo,
1504 .get_msglevel = pcnet32_get_msglevel,
1505 .set_msglevel = pcnet32_set_msglevel,
1506 .nway_reset = pcnet32_nway_reset,
1507 .get_link = pcnet32_get_link,
1508 .get_ringparam = pcnet32_get_ringparam,
1509 .set_ringparam = pcnet32_set_ringparam,
1510 .get_tx_csum = ethtool_op_get_tx_csum,
1511 .get_sg = ethtool_op_get_sg,
1512 .get_tso = ethtool_op_get_tso,
1513 .get_strings = pcnet32_get_strings,
1514 .self_test_count = pcnet32_self_test_count,
1515 .self_test = pcnet32_ethtool_test,
1516 .phys_id = pcnet32_phys_id,
1517 .get_regs_len = pcnet32_get_regs_len,
1518 .get_regs = pcnet32_get_regs,
1519 .get_perm_addr = ethtool_op_get_perm_addr,
1520 };
1521
1522 /* only probes for non-PCI devices, the rest are handled by
1523 * pci_register_driver via pcnet32_probe_pci */
1524
1525 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1526 {
1527 unsigned int *port, ioaddr;
1528
1529 /* search for PCnet32 VLB cards at known addresses */
1530 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1531 if (request_region
1532 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1533 /* check if there is really a pcnet chip on that ioaddr */
1534 if ((inb(ioaddr + 14) == 0x57)
1535 && (inb(ioaddr + 15) == 0x57)) {
1536 pcnet32_probe1(ioaddr, 0, NULL);
1537 } else {
1538 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1539 }
1540 }
1541 }
1542 }
1543
1544 static int __devinit
1545 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1546 {
1547 unsigned long ioaddr;
1548 int err;
1549
1550 err = pci_enable_device(pdev);
1551 if (err < 0) {
1552 if (pcnet32_debug & NETIF_MSG_PROBE)
1553 printk(KERN_ERR PFX
1554 "failed to enable device -- err=%d\n", err);
1555 return err;
1556 }
1557 pci_set_master(pdev);
1558
1559 ioaddr = pci_resource_start(pdev, 0);
1560 if (!ioaddr) {
1561 if (pcnet32_debug & NETIF_MSG_PROBE)
1562 printk(KERN_ERR PFX
1563 "card has no PCI IO resources, aborting\n");
1564 return -ENODEV;
1565 }
1566
1567 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1568 if (pcnet32_debug & NETIF_MSG_PROBE)
1569 printk(KERN_ERR PFX
1570 "architecture does not support 32bit PCI busmaster DMA\n");
1571 return -ENODEV;
1572 }
1573 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1574 NULL) {
1575 if (pcnet32_debug & NETIF_MSG_PROBE)
1576 printk(KERN_ERR PFX
1577 "io address range already allocated\n");
1578 return -EBUSY;
1579 }
1580
1581 err = pcnet32_probe1(ioaddr, 1, pdev);
1582 if (err < 0) {
1583 pci_disable_device(pdev);
1584 }
1585 return err;
1586 }
1587
1588 /* pcnet32_probe1
1589 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1590 * pdev will be NULL when called from pcnet32_probe_vlbus.
1591 */
1592 static int __devinit
1593 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1594 {
1595 struct pcnet32_private *lp;
1596 dma_addr_t lp_dma_addr;
1597 int i, media;
1598 int fdx, mii, fset, dxsuflo;
1599 int chip_version;
1600 char *chipname;
1601 struct net_device *dev;
1602 struct pcnet32_access *a = NULL;
1603 u8 promaddr[6];
1604 int ret = -ENODEV;
1605
1606 /* reset the chip */
1607 pcnet32_wio_reset(ioaddr);
1608
1609 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1610 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1611 a = &pcnet32_wio;
1612 } else {
1613 pcnet32_dwio_reset(ioaddr);
1614 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1615 && pcnet32_dwio_check(ioaddr)) {
1616 a = &pcnet32_dwio;
1617 } else
1618 goto err_release_region;
1619 }
1620
1621 chip_version =
1622 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1623 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1624 printk(KERN_INFO " PCnet chip version is %#x.\n",
1625 chip_version);
1626 if ((chip_version & 0xfff) != 0x003) {
1627 if (pcnet32_debug & NETIF_MSG_PROBE)
1628 printk(KERN_INFO PFX "Unsupported chip version.\n");
1629 goto err_release_region;
1630 }
1631
1632 /* initialize variables */
1633 fdx = mii = fset = dxsuflo = 0;
1634 chip_version = (chip_version >> 12) & 0xffff;
1635
1636 switch (chip_version) {
1637 case 0x2420:
1638 chipname = "PCnet/PCI 79C970"; /* PCI */
1639 break;
1640 case 0x2430:
1641 if (shared)
1642 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1643 else
1644 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1645 break;
1646 case 0x2621:
1647 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1648 fdx = 1;
1649 break;
1650 case 0x2623:
1651 chipname = "PCnet/FAST 79C971"; /* PCI */
1652 fdx = 1;
1653 mii = 1;
1654 fset = 1;
1655 break;
1656 case 0x2624:
1657 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1658 fdx = 1;
1659 mii = 1;
1660 fset = 1;
1661 break;
1662 case 0x2625:
1663 chipname = "PCnet/FAST III 79C973"; /* PCI */
1664 fdx = 1;
1665 mii = 1;
1666 break;
1667 case 0x2626:
1668 chipname = "PCnet/Home 79C978"; /* PCI */
1669 fdx = 1;
1670 /*
1671 * This is based on specs published at www.amd.com. This section
1672 * assumes that a card with a 79C978 wants to go into standard
1673 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1674 * and the module option homepna=1 can select this instead.
1675 */
1676 media = a->read_bcr(ioaddr, 49);
1677 media &= ~3; /* default to 10Mb ethernet */
1678 if (cards_found < MAX_UNITS && homepna[cards_found])
1679 media |= 1; /* switch to home wiring mode */
1680 if (pcnet32_debug & NETIF_MSG_PROBE)
1681 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1682 (media & 1) ? "1" : "10");
1683 a->write_bcr(ioaddr, 49, media);
1684 break;
1685 case 0x2627:
1686 chipname = "PCnet/FAST III 79C975"; /* PCI */
1687 fdx = 1;
1688 mii = 1;
1689 break;
1690 case 0x2628:
1691 chipname = "PCnet/PRO 79C976";
1692 fdx = 1;
1693 mii = 1;
1694 break;
1695 default:
1696 if (pcnet32_debug & NETIF_MSG_PROBE)
1697 printk(KERN_INFO PFX
1698 "PCnet version %#x, no PCnet32 chip.\n",
1699 chip_version);
1700 goto err_release_region;
1701 }
1702
1703 /*
1704 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1705 * starting until the packet is loaded. Strike one for reliability, lose
1706 * one for latency - although on PCI this isnt a big loss. Older chips
1707 * have FIFO's smaller than a packet, so you can't do this.
1708 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1709 */
1710
1711 if (fset) {
1712 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1713 a->write_csr(ioaddr, 80,
1714 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1715 dxsuflo = 1;
1716 }
1717
1718 dev = alloc_etherdev(0);
1719 if (!dev) {
1720 if (pcnet32_debug & NETIF_MSG_PROBE)
1721 printk(KERN_ERR PFX "Memory allocation failed.\n");
1722 ret = -ENOMEM;
1723 goto err_release_region;
1724 }
1725 SET_NETDEV_DEV(dev, &pdev->dev);
1726
1727 if (pcnet32_debug & NETIF_MSG_PROBE)
1728 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1729
1730 /* In most chips, after a chip reset, the ethernet address is read from the
1731 * station address PROM at the base address and programmed into the
1732 * "Physical Address Registers" CSR12-14.
1733 * As a precautionary measure, we read the PROM values and complain if
1734 * they disagree with the CSRs. If they miscompare, and the PROM addr
1735 * is valid, then the PROM addr is used.
1736 */
1737 for (i = 0; i < 3; i++) {
1738 unsigned int val;
1739 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1740 /* There may be endianness issues here. */
1741 dev->dev_addr[2 * i] = val & 0x0ff;
1742 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1743 }
1744
1745 /* read PROM address and compare with CSR address */
1746 for (i = 0; i < 6; i++)
1747 promaddr[i] = inb(ioaddr + i);
1748
1749 if (memcmp(promaddr, dev->dev_addr, 6)
1750 || !is_valid_ether_addr(dev->dev_addr)) {
1751 if (is_valid_ether_addr(promaddr)) {
1752 if (pcnet32_debug & NETIF_MSG_PROBE) {
1753 printk(" warning: CSR address invalid,\n");
1754 printk(KERN_INFO
1755 " using instead PROM address of");
1756 }
1757 memcpy(dev->dev_addr, promaddr, 6);
1758 }
1759 }
1760 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1761
1762 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1763 if (!is_valid_ether_addr(dev->perm_addr))
1764 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1765
1766 if (pcnet32_debug & NETIF_MSG_PROBE) {
1767 for (i = 0; i < 6; i++)
1768 printk(" %2.2x", dev->dev_addr[i]);
1769
1770 /* Version 0x2623 and 0x2624 */
1771 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1772 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1773 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1774 switch (i >> 10) {
1775 case 0:
1776 printk(" 20 bytes,");
1777 break;
1778 case 1:
1779 printk(" 64 bytes,");
1780 break;
1781 case 2:
1782 printk(" 128 bytes,");
1783 break;
1784 case 3:
1785 printk("~220 bytes,");
1786 break;
1787 }
1788 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1789 printk(" BCR18(%x):", i & 0xffff);
1790 if (i & (1 << 5))
1791 printk("BurstWrEn ");
1792 if (i & (1 << 6))
1793 printk("BurstRdEn ");
1794 if (i & (1 << 7))
1795 printk("DWordIO ");
1796 if (i & (1 << 11))
1797 printk("NoUFlow ");
1798 i = a->read_bcr(ioaddr, 25);
1799 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1800 i = a->read_bcr(ioaddr, 26);
1801 printk(" SRAM_BND=0x%04x,", i << 8);
1802 i = a->read_bcr(ioaddr, 27);
1803 if (i & (1 << 14))
1804 printk("LowLatRx");
1805 }
1806 }
1807
1808 dev->base_addr = ioaddr;
1809 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1810 if ((lp =
1811 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1812 if (pcnet32_debug & NETIF_MSG_PROBE)
1813 printk(KERN_ERR PFX
1814 "Consistent memory allocation failed.\n");
1815 ret = -ENOMEM;
1816 goto err_free_netdev;
1817 }
1818
1819 memset(lp, 0, sizeof(*lp));
1820 lp->dma_addr = lp_dma_addr;
1821 lp->pci_dev = pdev;
1822
1823 spin_lock_init(&lp->lock);
1824
1825 SET_MODULE_OWNER(dev);
1826 SET_NETDEV_DEV(dev, &pdev->dev);
1827 dev->priv = lp;
1828 lp->name = chipname;
1829 lp->shared_irq = shared;
1830 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1831 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1832 lp->tx_mod_mask = lp->tx_ring_size - 1;
1833 lp->rx_mod_mask = lp->rx_ring_size - 1;
1834 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1835 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1836 lp->mii_if.full_duplex = fdx;
1837 lp->mii_if.phy_id_mask = 0x1f;
1838 lp->mii_if.reg_num_mask = 0x1f;
1839 lp->dxsuflo = dxsuflo;
1840 lp->mii = mii;
1841 lp->chip_version = chip_version;
1842 lp->msg_enable = pcnet32_debug;
1843 if ((cards_found >= MAX_UNITS)
1844 || (options[cards_found] > sizeof(options_mapping)))
1845 lp->options = PCNET32_PORT_ASEL;
1846 else
1847 lp->options = options_mapping[options[cards_found]];
1848 lp->mii_if.dev = dev;
1849 lp->mii_if.mdio_read = mdio_read;
1850 lp->mii_if.mdio_write = mdio_write;
1851
1852 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1853 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1854 lp->options |= PCNET32_PORT_FD;
1855
1856 if (!a) {
1857 if (pcnet32_debug & NETIF_MSG_PROBE)
1858 printk(KERN_ERR PFX "No access methods\n");
1859 ret = -ENODEV;
1860 goto err_free_consistent;
1861 }
1862 lp->a = *a;
1863
1864 /* prior to register_netdev, dev->name is not yet correct */
1865 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1866 ret = -ENOMEM;
1867 goto err_free_ring;
1868 }
1869 /* detect special T1/E1 WAN card by checking for MAC address */
1870 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1871 && dev->dev_addr[2] == 0x75)
1872 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1873
1874 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1875 lp->init_block.tlen_rlen =
1876 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1877 for (i = 0; i < 6; i++)
1878 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1879 lp->init_block.filter[0] = 0x00000000;
1880 lp->init_block.filter[1] = 0x00000000;
1881 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1882 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1883
1884 /* switch pcnet32 to 32bit mode */
1885 a->write_bcr(ioaddr, 20, 2);
1886
1887 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1888 init_block)) & 0xffff);
1889 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1890 init_block)) >> 16);
1891
1892 if (pdev) { /* use the IRQ provided by PCI */
1893 dev->irq = pdev->irq;
1894 if (pcnet32_debug & NETIF_MSG_PROBE)
1895 printk(" assigned IRQ %d.\n", dev->irq);
1896 } else {
1897 unsigned long irq_mask = probe_irq_on();
1898
1899 /*
1900 * To auto-IRQ we enable the initialization-done and DMA error
1901 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1902 * boards will work.
1903 */
1904 /* Trigger an initialization just for the interrupt. */
1905 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1906 mdelay(1);
1907
1908 dev->irq = probe_irq_off(irq_mask);
1909 if (!dev->irq) {
1910 if (pcnet32_debug & NETIF_MSG_PROBE)
1911 printk(", failed to detect IRQ line.\n");
1912 ret = -ENODEV;
1913 goto err_free_ring;
1914 }
1915 if (pcnet32_debug & NETIF_MSG_PROBE)
1916 printk(", probed IRQ %d.\n", dev->irq);
1917 }
1918
1919 /* Set the mii phy_id so that we can query the link state */
1920 if (lp->mii) {
1921 /* lp->phycount and lp->phymask are set to 0 by memset above */
1922
1923 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1924 /* scan for PHYs */
1925 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1926 unsigned short id1, id2;
1927
1928 id1 = mdio_read(dev, i, MII_PHYSID1);
1929 if (id1 == 0xffff)
1930 continue;
1931 id2 = mdio_read(dev, i, MII_PHYSID2);
1932 if (id2 == 0xffff)
1933 continue;
1934 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1935 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1936 lp->phycount++;
1937 lp->phymask |= (1 << i);
1938 lp->mii_if.phy_id = i;
1939 if (pcnet32_debug & NETIF_MSG_PROBE)
1940 printk(KERN_INFO PFX
1941 "Found PHY %04x:%04x at address %d.\n",
1942 id1, id2, i);
1943 }
1944 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1945 if (lp->phycount > 1) {
1946 lp->options |= PCNET32_PORT_MII;
1947 }
1948 }
1949
1950 init_timer(&lp->watchdog_timer);
1951 lp->watchdog_timer.data = (unsigned long)dev;
1952 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1953
1954 /* The PCNET32-specific entries in the device structure. */
1955 dev->open = &pcnet32_open;
1956 dev->hard_start_xmit = &pcnet32_start_xmit;
1957 dev->stop = &pcnet32_close;
1958 dev->get_stats = &pcnet32_get_stats;
1959 dev->set_multicast_list = &pcnet32_set_multicast_list;
1960 dev->do_ioctl = &pcnet32_ioctl;
1961 dev->ethtool_ops = &pcnet32_ethtool_ops;
1962 dev->tx_timeout = pcnet32_tx_timeout;
1963 dev->watchdog_timeo = (5 * HZ);
1964 dev->weight = lp->rx_ring_size / 2;
1965 #ifdef CONFIG_PCNET32_NAPI
1966 dev->poll = pcnet32_poll;
1967 #endif
1968
1969 #ifdef CONFIG_NET_POLL_CONTROLLER
1970 dev->poll_controller = pcnet32_poll_controller;
1971 #endif
1972
1973 /* Fill in the generic fields of the device structure. */
1974 if (register_netdev(dev))
1975 goto err_free_ring;
1976
1977 if (pdev) {
1978 pci_set_drvdata(pdev, dev);
1979 } else {
1980 lp->next = pcnet32_dev;
1981 pcnet32_dev = dev;
1982 }
1983
1984 if (pcnet32_debug & NETIF_MSG_PROBE)
1985 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1986 cards_found++;
1987
1988 /* enable LED writes */
1989 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1990
1991 return 0;
1992
1993 err_free_ring:
1994 pcnet32_free_ring(dev);
1995 err_free_consistent:
1996 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1997 err_free_netdev:
1998 free_netdev(dev);
1999 err_release_region:
2000 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2001 return ret;
2002 }
2003
2004 /* if any allocation fails, caller must also call pcnet32_free_ring */
2005 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
2006 {
2007 struct pcnet32_private *lp = dev->priv;
2008
2009 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2010 sizeof(struct pcnet32_tx_head) *
2011 lp->tx_ring_size,
2012 &lp->tx_ring_dma_addr);
2013 if (lp->tx_ring == NULL) {
2014 if (netif_msg_drv(lp))
2015 printk("\n" KERN_ERR PFX
2016 "%s: Consistent memory allocation failed.\n",
2017 name);
2018 return -ENOMEM;
2019 }
2020
2021 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2022 sizeof(struct pcnet32_rx_head) *
2023 lp->rx_ring_size,
2024 &lp->rx_ring_dma_addr);
2025 if (lp->rx_ring == NULL) {
2026 if (netif_msg_drv(lp))
2027 printk("\n" KERN_ERR PFX
2028 "%s: Consistent memory allocation failed.\n",
2029 name);
2030 return -ENOMEM;
2031 }
2032
2033 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2034 GFP_ATOMIC);
2035 if (!lp->tx_dma_addr) {
2036 if (netif_msg_drv(lp))
2037 printk("\n" KERN_ERR PFX
2038 "%s: Memory allocation failed.\n", name);
2039 return -ENOMEM;
2040 }
2041
2042 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2043 GFP_ATOMIC);
2044 if (!lp->rx_dma_addr) {
2045 if (netif_msg_drv(lp))
2046 printk("\n" KERN_ERR PFX
2047 "%s: Memory allocation failed.\n", name);
2048 return -ENOMEM;
2049 }
2050
2051 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2052 GFP_ATOMIC);
2053 if (!lp->tx_skbuff) {
2054 if (netif_msg_drv(lp))
2055 printk("\n" KERN_ERR PFX
2056 "%s: Memory allocation failed.\n", name);
2057 return -ENOMEM;
2058 }
2059
2060 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2061 GFP_ATOMIC);
2062 if (!lp->rx_skbuff) {
2063 if (netif_msg_drv(lp))
2064 printk("\n" KERN_ERR PFX
2065 "%s: Memory allocation failed.\n", name);
2066 return -ENOMEM;
2067 }
2068
2069 return 0;
2070 }
2071
2072 static void pcnet32_free_ring(struct net_device *dev)
2073 {
2074 struct pcnet32_private *lp = dev->priv;
2075
2076 kfree(lp->tx_skbuff);
2077 lp->tx_skbuff = NULL;
2078
2079 kfree(lp->rx_skbuff);
2080 lp->rx_skbuff = NULL;
2081
2082 kfree(lp->tx_dma_addr);
2083 lp->tx_dma_addr = NULL;
2084
2085 kfree(lp->rx_dma_addr);
2086 lp->rx_dma_addr = NULL;
2087
2088 if (lp->tx_ring) {
2089 pci_free_consistent(lp->pci_dev,
2090 sizeof(struct pcnet32_tx_head) *
2091 lp->tx_ring_size, lp->tx_ring,
2092 lp->tx_ring_dma_addr);
2093 lp->tx_ring = NULL;
2094 }
2095
2096 if (lp->rx_ring) {
2097 pci_free_consistent(lp->pci_dev,
2098 sizeof(struct pcnet32_rx_head) *
2099 lp->rx_ring_size, lp->rx_ring,
2100 lp->rx_ring_dma_addr);
2101 lp->rx_ring = NULL;
2102 }
2103 }
2104
2105 static int pcnet32_open(struct net_device *dev)
2106 {
2107 struct pcnet32_private *lp = dev->priv;
2108 unsigned long ioaddr = dev->base_addr;
2109 u16 val;
2110 int i;
2111 int rc;
2112 unsigned long flags;
2113
2114 if (request_irq(dev->irq, &pcnet32_interrupt,
2115 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2116 (void *)dev)) {
2117 return -EAGAIN;
2118 }
2119
2120 spin_lock_irqsave(&lp->lock, flags);
2121 /* Check for a valid station address */
2122 if (!is_valid_ether_addr(dev->dev_addr)) {
2123 rc = -EINVAL;
2124 goto err_free_irq;
2125 }
2126
2127 /* Reset the PCNET32 */
2128 lp->a.reset(ioaddr);
2129
2130 /* switch pcnet32 to 32bit mode */
2131 lp->a.write_bcr(ioaddr, 20, 2);
2132
2133 if (netif_msg_ifup(lp))
2134 printk(KERN_DEBUG
2135 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2136 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2137 (u32) (lp->rx_ring_dma_addr),
2138 (u32) (lp->dma_addr +
2139 offsetof(struct pcnet32_private, init_block)));
2140
2141 /* set/reset autoselect bit */
2142 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2143 if (lp->options & PCNET32_PORT_ASEL)
2144 val |= 2;
2145 lp->a.write_bcr(ioaddr, 2, val);
2146
2147 /* handle full duplex setting */
2148 if (lp->mii_if.full_duplex) {
2149 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2150 if (lp->options & PCNET32_PORT_FD) {
2151 val |= 1;
2152 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2153 val |= 2;
2154 } else if (lp->options & PCNET32_PORT_ASEL) {
2155 /* workaround of xSeries250, turn on for 79C975 only */
2156 if (lp->chip_version == 0x2627)
2157 val |= 3;
2158 }
2159 lp->a.write_bcr(ioaddr, 9, val);
2160 }
2161
2162 /* set/reset GPSI bit in test register */
2163 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2164 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2165 val |= 0x10;
2166 lp->a.write_csr(ioaddr, 124, val);
2167
2168 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2169 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2170 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2171 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2172 if (lp->options & PCNET32_PORT_ASEL) {
2173 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2174 if (netif_msg_link(lp))
2175 printk(KERN_DEBUG
2176 "%s: Setting 100Mb-Full Duplex.\n",
2177 dev->name);
2178 }
2179 }
2180 if (lp->phycount < 2) {
2181 /*
2182 * 24 Jun 2004 according AMD, in order to change the PHY,
2183 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2184 * duplex, and/or enable auto negotiation, and clear DANAS
2185 */
2186 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2187 lp->a.write_bcr(ioaddr, 32,
2188 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2189 /* disable Auto Negotiation, set 10Mpbs, HD */
2190 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2191 if (lp->options & PCNET32_PORT_FD)
2192 val |= 0x10;
2193 if (lp->options & PCNET32_PORT_100)
2194 val |= 0x08;
2195 lp->a.write_bcr(ioaddr, 32, val);
2196 } else {
2197 if (lp->options & PCNET32_PORT_ASEL) {
2198 lp->a.write_bcr(ioaddr, 32,
2199 lp->a.read_bcr(ioaddr,
2200 32) | 0x0080);
2201 /* enable auto negotiate, setup, disable fd */
2202 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2203 val |= 0x20;
2204 lp->a.write_bcr(ioaddr, 32, val);
2205 }
2206 }
2207 } else {
2208 int first_phy = -1;
2209 u16 bmcr;
2210 u32 bcr9;
2211 struct ethtool_cmd ecmd;
2212
2213 /*
2214 * There is really no good other way to handle multiple PHYs
2215 * other than turning off all automatics
2216 */
2217 val = lp->a.read_bcr(ioaddr, 2);
2218 lp->a.write_bcr(ioaddr, 2, val & ~2);
2219 val = lp->a.read_bcr(ioaddr, 32);
2220 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2221
2222 if (!(lp->options & PCNET32_PORT_ASEL)) {
2223 /* setup ecmd */
2224 ecmd.port = PORT_MII;
2225 ecmd.transceiver = XCVR_INTERNAL;
2226 ecmd.autoneg = AUTONEG_DISABLE;
2227 ecmd.speed =
2228 lp->
2229 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2230 bcr9 = lp->a.read_bcr(ioaddr, 9);
2231
2232 if (lp->options & PCNET32_PORT_FD) {
2233 ecmd.duplex = DUPLEX_FULL;
2234 bcr9 |= (1 << 0);
2235 } else {
2236 ecmd.duplex = DUPLEX_HALF;
2237 bcr9 |= ~(1 << 0);
2238 }
2239 lp->a.write_bcr(ioaddr, 9, bcr9);
2240 }
2241
2242 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2243 if (lp->phymask & (1 << i)) {
2244 /* isolate all but the first PHY */
2245 bmcr = mdio_read(dev, i, MII_BMCR);
2246 if (first_phy == -1) {
2247 first_phy = i;
2248 mdio_write(dev, i, MII_BMCR,
2249 bmcr & ~BMCR_ISOLATE);
2250 } else {
2251 mdio_write(dev, i, MII_BMCR,
2252 bmcr | BMCR_ISOLATE);
2253 }
2254 /* use mii_ethtool_sset to setup PHY */
2255 lp->mii_if.phy_id = i;
2256 ecmd.phy_address = i;
2257 if (lp->options & PCNET32_PORT_ASEL) {
2258 mii_ethtool_gset(&lp->mii_if, &ecmd);
2259 ecmd.autoneg = AUTONEG_ENABLE;
2260 }
2261 mii_ethtool_sset(&lp->mii_if, &ecmd);
2262 }
2263 }
2264 lp->mii_if.phy_id = first_phy;
2265 if (netif_msg_link(lp))
2266 printk(KERN_INFO "%s: Using PHY number %d.\n",
2267 dev->name, first_phy);
2268 }
2269
2270 #ifdef DO_DXSUFLO
2271 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2272 val = lp->a.read_csr(ioaddr, CSR3);
2273 val |= 0x40;
2274 lp->a.write_csr(ioaddr, CSR3, val);
2275 }
2276 #endif
2277
2278 lp->init_block.mode =
2279 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2280 pcnet32_load_multicast(dev);
2281
2282 if (pcnet32_init_ring(dev)) {
2283 rc = -ENOMEM;
2284 goto err_free_ring;
2285 }
2286
2287 /* Re-initialize the PCNET32, and start it when done. */
2288 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
2289 offsetof(struct pcnet32_private,
2290 init_block)) & 0xffff);
2291 lp->a.write_csr(ioaddr, 2,
2292 (lp->dma_addr +
2293 offsetof(struct pcnet32_private, init_block)) >> 16);
2294
2295 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2296 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2297
2298 netif_start_queue(dev);
2299
2300 if (lp->chip_version >= PCNET32_79C970A) {
2301 /* Print the link status and start the watchdog */
2302 pcnet32_check_media(dev, 1);
2303 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2304 }
2305
2306 i = 0;
2307 while (i++ < 100)
2308 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2309 break;
2310 /*
2311 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2312 * reports that doing so triggers a bug in the '974.
2313 */
2314 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2315
2316 if (netif_msg_ifup(lp))
2317 printk(KERN_DEBUG
2318 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2319 dev->name, i,
2320 (u32) (lp->dma_addr +
2321 offsetof(struct pcnet32_private, init_block)),
2322 lp->a.read_csr(ioaddr, CSR0));
2323
2324 spin_unlock_irqrestore(&lp->lock, flags);
2325
2326 return 0; /* Always succeed */
2327
2328 err_free_ring:
2329 /* free any allocated skbuffs */
2330 pcnet32_purge_rx_ring(dev);
2331
2332 /*
2333 * Switch back to 16bit mode to avoid problems with dumb
2334 * DOS packet driver after a warm reboot
2335 */
2336 lp->a.write_bcr(ioaddr, 20, 4);
2337
2338 err_free_irq:
2339 spin_unlock_irqrestore(&lp->lock, flags);
2340 free_irq(dev->irq, dev);
2341 return rc;
2342 }
2343
2344 /*
2345 * The LANCE has been halted for one reason or another (busmaster memory
2346 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2347 * etc.). Modern LANCE variants always reload their ring-buffer
2348 * configuration when restarted, so we must reinitialize our ring
2349 * context before restarting. As part of this reinitialization,
2350 * find all packets still on the Tx ring and pretend that they had been
2351 * sent (in effect, drop the packets on the floor) - the higher-level
2352 * protocols will time out and retransmit. It'd be better to shuffle
2353 * these skbs to a temp list and then actually re-Tx them after
2354 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2355 */
2356
2357 static void pcnet32_purge_tx_ring(struct net_device *dev)
2358 {
2359 struct pcnet32_private *lp = dev->priv;
2360 int i;
2361
2362 for (i = 0; i < lp->tx_ring_size; i++) {
2363 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2364 wmb(); /* Make sure adapter sees owner change */
2365 if (lp->tx_skbuff[i]) {
2366 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2367 lp->tx_skbuff[i]->len,
2368 PCI_DMA_TODEVICE);
2369 dev_kfree_skb_any(lp->tx_skbuff[i]);
2370 }
2371 lp->tx_skbuff[i] = NULL;
2372 lp->tx_dma_addr[i] = 0;
2373 }
2374 }
2375
2376 /* Initialize the PCNET32 Rx and Tx rings. */
2377 static int pcnet32_init_ring(struct net_device *dev)
2378 {
2379 struct pcnet32_private *lp = dev->priv;
2380 int i;
2381
2382 lp->tx_full = 0;
2383 lp->cur_rx = lp->cur_tx = 0;
2384 lp->dirty_rx = lp->dirty_tx = 0;
2385
2386 for (i = 0; i < lp->rx_ring_size; i++) {
2387 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2388 if (rx_skbuff == NULL) {
2389 if (!
2390 (rx_skbuff = lp->rx_skbuff[i] =
2391 dev_alloc_skb(PKT_BUF_SZ))) {
2392 /* there is not much, we can do at this point */
2393 if (netif_msg_drv(lp))
2394 printk(KERN_ERR
2395 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2396 dev->name);
2397 return -1;
2398 }
2399 skb_reserve(rx_skbuff, 2);
2400 }
2401
2402 rmb();
2403 if (lp->rx_dma_addr[i] == 0)
2404 lp->rx_dma_addr[i] =
2405 pci_map_single(lp->pci_dev, rx_skbuff->data,
2406 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2407 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2408 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2409 wmb(); /* Make sure owner changes after all others are visible */
2410 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2411 }
2412 /* The Tx buffer address is filled in as needed, but we do need to clear
2413 * the upper ownership bit. */
2414 for (i = 0; i < lp->tx_ring_size; i++) {
2415 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2416 wmb(); /* Make sure adapter sees owner change */
2417 lp->tx_ring[i].base = 0;
2418 lp->tx_dma_addr[i] = 0;
2419 }
2420
2421 lp->init_block.tlen_rlen =
2422 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2423 for (i = 0; i < 6; i++)
2424 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2425 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2426 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2427 wmb(); /* Make sure all changes are visible */
2428 return 0;
2429 }
2430
2431 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2432 * then flush the pending transmit operations, re-initialize the ring,
2433 * and tell the chip to initialize.
2434 */
2435 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2436 {
2437 struct pcnet32_private *lp = dev->priv;
2438 unsigned long ioaddr = dev->base_addr;
2439 int i;
2440
2441 /* wait for stop */
2442 for (i = 0; i < 100; i++)
2443 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2444 break;
2445
2446 if (i >= 100 && netif_msg_drv(lp))
2447 printk(KERN_ERR
2448 "%s: pcnet32_restart timed out waiting for stop.\n",
2449 dev->name);
2450
2451 pcnet32_purge_tx_ring(dev);
2452 if (pcnet32_init_ring(dev))
2453 return;
2454
2455 /* ReInit Ring */
2456 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2457 i = 0;
2458 while (i++ < 1000)
2459 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2460 break;
2461
2462 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2463 }
2464
2465 static void pcnet32_tx_timeout(struct net_device *dev)
2466 {
2467 struct pcnet32_private *lp = dev->priv;
2468 unsigned long ioaddr = dev->base_addr, flags;
2469
2470 spin_lock_irqsave(&lp->lock, flags);
2471 /* Transmitter timeout, serious problems. */
2472 if (pcnet32_debug & NETIF_MSG_DRV)
2473 printk(KERN_ERR
2474 "%s: transmit timed out, status %4.4x, resetting.\n",
2475 dev->name, lp->a.read_csr(ioaddr, CSR0));
2476 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2477 lp->stats.tx_errors++;
2478 if (netif_msg_tx_err(lp)) {
2479 int i;
2480 printk(KERN_DEBUG
2481 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2482 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2483 lp->cur_rx);
2484 for (i = 0; i < lp->rx_ring_size; i++)
2485 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2486 le32_to_cpu(lp->rx_ring[i].base),
2487 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2488 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2489 le16_to_cpu(lp->rx_ring[i].status));
2490 for (i = 0; i < lp->tx_ring_size; i++)
2491 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2492 le32_to_cpu(lp->tx_ring[i].base),
2493 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2494 le32_to_cpu(lp->tx_ring[i].misc),
2495 le16_to_cpu(lp->tx_ring[i].status));
2496 printk("\n");
2497 }
2498 pcnet32_restart(dev, CSR0_NORMAL);
2499
2500 dev->trans_start = jiffies;
2501 netif_wake_queue(dev);
2502
2503 spin_unlock_irqrestore(&lp->lock, flags);
2504 }
2505
2506 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2507 {
2508 struct pcnet32_private *lp = dev->priv;
2509 unsigned long ioaddr = dev->base_addr;
2510 u16 status;
2511 int entry;
2512 unsigned long flags;
2513
2514 spin_lock_irqsave(&lp->lock, flags);
2515
2516 if (netif_msg_tx_queued(lp)) {
2517 printk(KERN_DEBUG
2518 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2519 dev->name, lp->a.read_csr(ioaddr, CSR0));
2520 }
2521
2522 /* Default status -- will not enable Successful-TxDone
2523 * interrupt when that option is available to us.
2524 */
2525 status = 0x8300;
2526
2527 /* Fill in a Tx ring entry */
2528
2529 /* Mask to ring buffer boundary. */
2530 entry = lp->cur_tx & lp->tx_mod_mask;
2531
2532 /* Caution: the write order is important here, set the status
2533 * with the "ownership" bits last. */
2534
2535 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2536
2537 lp->tx_ring[entry].misc = 0x00000000;
2538
2539 lp->tx_skbuff[entry] = skb;
2540 lp->tx_dma_addr[entry] =
2541 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2542 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2543 wmb(); /* Make sure owner changes after all others are visible */
2544 lp->tx_ring[entry].status = le16_to_cpu(status);
2545
2546 lp->cur_tx++;
2547 lp->stats.tx_bytes += skb->len;
2548
2549 /* Trigger an immediate send poll. */
2550 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2551
2552 dev->trans_start = jiffies;
2553
2554 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2555 lp->tx_full = 1;
2556 netif_stop_queue(dev);
2557 }
2558 spin_unlock_irqrestore(&lp->lock, flags);
2559 return 0;
2560 }
2561
2562 /* The PCNET32 interrupt handler. */
2563 static irqreturn_t
2564 pcnet32_interrupt(int irq, void *dev_id)
2565 {
2566 struct net_device *dev = dev_id;
2567 struct pcnet32_private *lp;
2568 unsigned long ioaddr;
2569 u16 csr0;
2570 int boguscnt = max_interrupt_work;
2571
2572 ioaddr = dev->base_addr;
2573 lp = dev->priv;
2574
2575 spin_lock(&lp->lock);
2576
2577 csr0 = lp->a.read_csr(ioaddr, CSR0);
2578 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2579 if (csr0 == 0xffff) {
2580 break; /* PCMCIA remove happened */
2581 }
2582 /* Acknowledge all of the current interrupt sources ASAP. */
2583 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2584
2585 if (netif_msg_intr(lp))
2586 printk(KERN_DEBUG
2587 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2588 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2589
2590 /* Log misc errors. */
2591 if (csr0 & 0x4000)
2592 lp->stats.tx_errors++; /* Tx babble. */
2593 if (csr0 & 0x1000) {
2594 /*
2595 * This happens when our receive ring is full. This
2596 * shouldn't be a problem as we will see normal rx
2597 * interrupts for the frames in the receive ring. But
2598 * there are some PCI chipsets (I can reproduce this
2599 * on SP3G with Intel saturn chipset) which have
2600 * sometimes problems and will fill up the receive
2601 * ring with error descriptors. In this situation we
2602 * don't get a rx interrupt, but a missed frame
2603 * interrupt sooner or later.
2604 */
2605 lp->stats.rx_errors++; /* Missed a Rx frame. */
2606 }
2607 if (csr0 & 0x0800) {
2608 if (netif_msg_drv(lp))
2609 printk(KERN_ERR
2610 "%s: Bus master arbitration failure, status %4.4x.\n",
2611 dev->name, csr0);
2612 /* unlike for the lance, there is no restart needed */
2613 }
2614 #ifdef CONFIG_PCNET32_NAPI
2615 if (netif_rx_schedule_prep(dev)) {
2616 u16 val;
2617 /* set interrupt masks */
2618 val = lp->a.read_csr(ioaddr, CSR3);
2619 val |= 0x5f00;
2620 lp->a.write_csr(ioaddr, CSR3, val);
2621 mmiowb();
2622 __netif_rx_schedule(dev);
2623 break;
2624 }
2625 #else
2626 pcnet32_rx(dev, dev->weight);
2627 if (pcnet32_tx(dev)) {
2628 /* reset the chip to clear the error condition, then restart */
2629 lp->a.reset(ioaddr);
2630 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2631 pcnet32_restart(dev, CSR0_START);
2632 netif_wake_queue(dev);
2633 }
2634 #endif
2635 csr0 = lp->a.read_csr(ioaddr, CSR0);
2636 }
2637
2638 #ifndef CONFIG_PCNET32_NAPI
2639 /* Set interrupt enable. */
2640 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2641 #endif
2642
2643 if (netif_msg_intr(lp))
2644 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2645 dev->name, lp->a.read_csr(ioaddr, CSR0));
2646
2647 spin_unlock(&lp->lock);
2648
2649 return IRQ_HANDLED;
2650 }
2651
2652 static int pcnet32_close(struct net_device *dev)
2653 {
2654 unsigned long ioaddr = dev->base_addr;
2655 struct pcnet32_private *lp = dev->priv;
2656 unsigned long flags;
2657
2658 del_timer_sync(&lp->watchdog_timer);
2659
2660 netif_stop_queue(dev);
2661
2662 spin_lock_irqsave(&lp->lock, flags);
2663
2664 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2665
2666 if (netif_msg_ifdown(lp))
2667 printk(KERN_DEBUG
2668 "%s: Shutting down ethercard, status was %2.2x.\n",
2669 dev->name, lp->a.read_csr(ioaddr, CSR0));
2670
2671 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2672 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2673
2674 /*
2675 * Switch back to 16bit mode to avoid problems with dumb
2676 * DOS packet driver after a warm reboot
2677 */
2678 lp->a.write_bcr(ioaddr, 20, 4);
2679
2680 spin_unlock_irqrestore(&lp->lock, flags);
2681
2682 free_irq(dev->irq, dev);
2683
2684 spin_lock_irqsave(&lp->lock, flags);
2685
2686 pcnet32_purge_rx_ring(dev);
2687 pcnet32_purge_tx_ring(dev);
2688
2689 spin_unlock_irqrestore(&lp->lock, flags);
2690
2691 return 0;
2692 }
2693
2694 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2695 {
2696 struct pcnet32_private *lp = dev->priv;
2697 unsigned long ioaddr = dev->base_addr;
2698 unsigned long flags;
2699
2700 spin_lock_irqsave(&lp->lock, flags);
2701 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2702 spin_unlock_irqrestore(&lp->lock, flags);
2703
2704 return &lp->stats;
2705 }
2706
2707 /* taken from the sunlance driver, which it took from the depca driver */
2708 static void pcnet32_load_multicast(struct net_device *dev)
2709 {
2710 struct pcnet32_private *lp = dev->priv;
2711 volatile struct pcnet32_init_block *ib = &lp->init_block;
2712 volatile u16 *mcast_table = (u16 *) & ib->filter;
2713 struct dev_mc_list *dmi = dev->mc_list;
2714 unsigned long ioaddr = dev->base_addr;
2715 char *addrs;
2716 int i;
2717 u32 crc;
2718
2719 /* set all multicast bits */
2720 if (dev->flags & IFF_ALLMULTI) {
2721 ib->filter[0] = 0xffffffff;
2722 ib->filter[1] = 0xffffffff;
2723 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2724 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2725 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2726 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2727 return;
2728 }
2729 /* clear the multicast filter */
2730 ib->filter[0] = 0;
2731 ib->filter[1] = 0;
2732
2733 /* Add addresses */
2734 for (i = 0; i < dev->mc_count; i++) {
2735 addrs = dmi->dmi_addr;
2736 dmi = dmi->next;
2737
2738 /* multicast address? */
2739 if (!(*addrs & 1))
2740 continue;
2741
2742 crc = ether_crc_le(6, addrs);
2743 crc = crc >> 26;
2744 mcast_table[crc >> 4] =
2745 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2746 (1 << (crc & 0xf)));
2747 }
2748 for (i = 0; i < 4; i++)
2749 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2750 le16_to_cpu(mcast_table[i]));
2751 return;
2752 }
2753
2754 /*
2755 * Set or clear the multicast filter for this adaptor.
2756 */
2757 static void pcnet32_set_multicast_list(struct net_device *dev)
2758 {
2759 unsigned long ioaddr = dev->base_addr, flags;
2760 struct pcnet32_private *lp = dev->priv;
2761 int csr15, suspended;
2762
2763 spin_lock_irqsave(&lp->lock, flags);
2764 suspended = pcnet32_suspend(dev, &flags, 0);
2765 csr15 = lp->a.read_csr(ioaddr, CSR15);
2766 if (dev->flags & IFF_PROMISC) {
2767 /* Log any net taps. */
2768 if (netif_msg_hw(lp))
2769 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2770 dev->name);
2771 lp->init_block.mode =
2772 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2773 7);
2774 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2775 } else {
2776 lp->init_block.mode =
2777 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2778 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2779 pcnet32_load_multicast(dev);
2780 }
2781
2782 if (suspended) {
2783 int csr5;
2784 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2785 csr5 = lp->a.read_csr(ioaddr, CSR5);
2786 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2787 } else {
2788 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2789 pcnet32_restart(dev, CSR0_NORMAL);
2790 netif_wake_queue(dev);
2791 }
2792
2793 spin_unlock_irqrestore(&lp->lock, flags);
2794 }
2795
2796 /* This routine assumes that the lp->lock is held */
2797 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2798 {
2799 struct pcnet32_private *lp = dev->priv;
2800 unsigned long ioaddr = dev->base_addr;
2801 u16 val_out;
2802
2803 if (!lp->mii)
2804 return 0;
2805
2806 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2807 val_out = lp->a.read_bcr(ioaddr, 34);
2808
2809 return val_out;
2810 }
2811
2812 /* This routine assumes that the lp->lock is held */
2813 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2814 {
2815 struct pcnet32_private *lp = dev->priv;
2816 unsigned long ioaddr = dev->base_addr;
2817
2818 if (!lp->mii)
2819 return;
2820
2821 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2822 lp->a.write_bcr(ioaddr, 34, val);
2823 }
2824
2825 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2826 {
2827 struct pcnet32_private *lp = dev->priv;
2828 int rc;
2829 unsigned long flags;
2830
2831 /* SIOC[GS]MIIxxx ioctls */
2832 if (lp->mii) {
2833 spin_lock_irqsave(&lp->lock, flags);
2834 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2835 spin_unlock_irqrestore(&lp->lock, flags);
2836 } else {
2837 rc = -EOPNOTSUPP;
2838 }
2839
2840 return rc;
2841 }
2842
2843 static int pcnet32_check_otherphy(struct net_device *dev)
2844 {
2845 struct pcnet32_private *lp = dev->priv;
2846 struct mii_if_info mii = lp->mii_if;
2847 u16 bmcr;
2848 int i;
2849
2850 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2851 if (i == lp->mii_if.phy_id)
2852 continue; /* skip active phy */
2853 if (lp->phymask & (1 << i)) {
2854 mii.phy_id = i;
2855 if (mii_link_ok(&mii)) {
2856 /* found PHY with active link */
2857 if (netif_msg_link(lp))
2858 printk(KERN_INFO
2859 "%s: Using PHY number %d.\n",
2860 dev->name, i);
2861
2862 /* isolate inactive phy */
2863 bmcr =
2864 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2865 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2866 bmcr | BMCR_ISOLATE);
2867
2868 /* de-isolate new phy */
2869 bmcr = mdio_read(dev, i, MII_BMCR);
2870 mdio_write(dev, i, MII_BMCR,
2871 bmcr & ~BMCR_ISOLATE);
2872
2873 /* set new phy address */
2874 lp->mii_if.phy_id = i;
2875 return 1;
2876 }
2877 }
2878 }
2879 return 0;
2880 }
2881
2882 /*
2883 * Show the status of the media. Similar to mii_check_media however it
2884 * correctly shows the link speed for all (tested) pcnet32 variants.
2885 * Devices with no mii just report link state without speed.
2886 *
2887 * Caller is assumed to hold and release the lp->lock.
2888 */
2889
2890 static void pcnet32_check_media(struct net_device *dev, int verbose)
2891 {
2892 struct pcnet32_private *lp = dev->priv;
2893 int curr_link;
2894 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2895 u32 bcr9;
2896
2897 if (lp->mii) {
2898 curr_link = mii_link_ok(&lp->mii_if);
2899 } else {
2900 ulong ioaddr = dev->base_addr; /* card base I/O address */
2901 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2902 }
2903 if (!curr_link) {
2904 if (prev_link || verbose) {
2905 netif_carrier_off(dev);
2906 if (netif_msg_link(lp))
2907 printk(KERN_INFO "%s: link down\n", dev->name);
2908 }
2909 if (lp->phycount > 1) {
2910 curr_link = pcnet32_check_otherphy(dev);
2911 prev_link = 0;
2912 }
2913 } else if (verbose || !prev_link) {
2914 netif_carrier_on(dev);
2915 if (lp->mii) {
2916 if (netif_msg_link(lp)) {
2917 struct ethtool_cmd ecmd;
2918 mii_ethtool_gset(&lp->mii_if, &ecmd);
2919 printk(KERN_INFO
2920 "%s: link up, %sMbps, %s-duplex\n",
2921 dev->name,
2922 (ecmd.speed == SPEED_100) ? "100" : "10",
2923 (ecmd.duplex ==
2924 DUPLEX_FULL) ? "full" : "half");
2925 }
2926 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2927 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2928 if (lp->mii_if.full_duplex)
2929 bcr9 |= (1 << 0);
2930 else
2931 bcr9 &= ~(1 << 0);
2932 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2933 }
2934 } else {
2935 if (netif_msg_link(lp))
2936 printk(KERN_INFO "%s: link up\n", dev->name);
2937 }
2938 }
2939 }
2940
2941 /*
2942 * Check for loss of link and link establishment.
2943 * Can not use mii_check_media because it does nothing if mode is forced.
2944 */
2945
2946 static void pcnet32_watchdog(struct net_device *dev)
2947 {
2948 struct pcnet32_private *lp = dev->priv;
2949 unsigned long flags;
2950
2951 /* Print the link status if it has changed */
2952 spin_lock_irqsave(&lp->lock, flags);
2953 pcnet32_check_media(dev, 0);
2954 spin_unlock_irqrestore(&lp->lock, flags);
2955
2956 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2957 }
2958
2959 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2960 {
2961 struct net_device *dev = pci_get_drvdata(pdev);
2962
2963 if (dev) {
2964 struct pcnet32_private *lp = dev->priv;
2965
2966 unregister_netdev(dev);
2967 pcnet32_free_ring(dev);
2968 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2969 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2970 free_netdev(dev);
2971 pci_disable_device(pdev);
2972 pci_set_drvdata(pdev, NULL);
2973 }
2974 }
2975
2976 static struct pci_driver pcnet32_driver = {
2977 .name = DRV_NAME,
2978 .probe = pcnet32_probe_pci,
2979 .remove = __devexit_p(pcnet32_remove_one),
2980 .id_table = pcnet32_pci_tbl,
2981 };
2982
2983 /* An additional parameter that may be passed in... */
2984 static int debug = -1;
2985 static int tx_start_pt = -1;
2986 static int pcnet32_have_pci;
2987
2988 module_param(debug, int, 0);
2989 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2990 module_param(max_interrupt_work, int, 0);
2991 MODULE_PARM_DESC(max_interrupt_work,
2992 DRV_NAME " maximum events handled per interrupt");
2993 module_param(rx_copybreak, int, 0);
2994 MODULE_PARM_DESC(rx_copybreak,
2995 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2996 module_param(tx_start_pt, int, 0);
2997 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2998 module_param(pcnet32vlb, int, 0);
2999 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3000 module_param_array(options, int, NULL, 0);
3001 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3002 module_param_array(full_duplex, int, NULL, 0);
3003 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3004 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3005 module_param_array(homepna, int, NULL, 0);
3006 MODULE_PARM_DESC(homepna,
3007 DRV_NAME
3008 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3009
3010 MODULE_AUTHOR("Thomas Bogendoerfer");
3011 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3012 MODULE_LICENSE("GPL");
3013
3014 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3015
3016 static int __init pcnet32_init_module(void)
3017 {
3018 printk(KERN_INFO "%s", version);
3019
3020 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3021
3022 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3023 tx_start = tx_start_pt;
3024
3025 /* find the PCI devices */
3026 if (!pci_register_driver(&pcnet32_driver))
3027 pcnet32_have_pci = 1;
3028
3029 /* should we find any remaining VLbus devices ? */
3030 if (pcnet32vlb)
3031 pcnet32_probe_vlbus(pcnet32_portlist);
3032
3033 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3034 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3035
3036 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3037 }
3038
3039 static void __exit pcnet32_cleanup_module(void)
3040 {
3041 struct net_device *next_dev;
3042
3043 while (pcnet32_dev) {
3044 struct pcnet32_private *lp = pcnet32_dev->priv;
3045 next_dev = lp->next;
3046 unregister_netdev(pcnet32_dev);
3047 pcnet32_free_ring(pcnet32_dev);
3048 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3049 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
3050 free_netdev(pcnet32_dev);
3051 pcnet32_dev = next_dev;
3052 }
3053
3054 if (pcnet32_have_pci)
3055 pci_unregister_driver(&pcnet32_driver);
3056 }
3057
3058 module_init(pcnet32_init_module);
3059 module_exit(pcnet32_cleanup_module);
3060
3061 /*
3062 * Local variables:
3063 * c-indent-level: 4
3064 * tab-width: 8
3065 * End:
3066 */
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