2 * drivers/net/phy/cicada.c
4 * Driver for Cicada PHYs
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/string.h>
19 #include <linux/errno.h>
20 #include <linux/unistd.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
37 #include <asm/uaccess.h>
39 /* Cicada Extended Control Register 1 */
40 #define MII_CIS8201_EXT_CON1 0x17
41 #define MII_CIS8201_EXTCON1_INIT 0x0000
43 /* Cicada Interrupt Mask Register */
44 #define MII_CIS8201_IMASK 0x19
45 #define MII_CIS8201_IMASK_IEN 0x8000
46 #define MII_CIS8201_IMASK_SPEED 0x4000
47 #define MII_CIS8201_IMASK_LINK 0x2000
48 #define MII_CIS8201_IMASK_DUPLEX 0x1000
49 #define MII_CIS8201_IMASK_MASK 0xf000
51 /* Cicada Interrupt Status Register */
52 #define MII_CIS8201_ISTAT 0x1a
53 #define MII_CIS8201_ISTAT_STATUS 0x8000
54 #define MII_CIS8201_ISTAT_SPEED 0x4000
55 #define MII_CIS8201_ISTAT_LINK 0x2000
56 #define MII_CIS8201_ISTAT_DUPLEX 0x1000
58 /* Cicada Auxiliary Control/Status Register */
59 #define MII_CIS8201_AUX_CONSTAT 0x1c
60 #define MII_CIS8201_AUXCONSTAT_INIT 0x0004
61 #define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
62 #define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
63 #define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
64 #define MII_CIS8201_AUXCONSTAT_100 0x0008
66 MODULE_DESCRIPTION("Cicadia PHY driver");
67 MODULE_AUTHOR("Andy Fleming");
68 MODULE_LICENSE("GPL");
70 static int cis820x_config_init(struct phy_device
*phydev
)
74 err
= phy_write(phydev
, MII_CIS8201_AUX_CONSTAT
,
75 MII_CIS8201_AUXCONSTAT_INIT
);
80 err
= phy_write(phydev
, MII_CIS8201_EXT_CON1
,
81 MII_CIS8201_EXTCON1_INIT
);
86 static int cis820x_ack_interrupt(struct phy_device
*phydev
)
88 int err
= phy_read(phydev
, MII_CIS8201_ISTAT
);
90 return (err
< 0) ? err
: 0;
93 static int cis820x_config_intr(struct phy_device
*phydev
)
97 if(phydev
->interrupts
== PHY_INTERRUPT_ENABLED
)
98 err
= phy_write(phydev
, MII_CIS8201_IMASK
,
99 MII_CIS8201_IMASK_MASK
);
101 err
= phy_write(phydev
, MII_CIS8201_IMASK
, 0);
106 /* Cicada 8201, a.k.a Vitesse VSC8201 */
107 static struct phy_driver cis8201_driver
= {
108 .phy_id
= 0x000fc410,
109 .name
= "Cicada Cis8201",
110 .phy_id_mask
= 0x000ffff0,
111 .features
= PHY_GBIT_FEATURES
,
112 .flags
= PHY_HAS_INTERRUPT
,
113 .config_init
= &cis820x_config_init
,
114 .config_aneg
= &genphy_config_aneg
,
115 .read_status
= &genphy_read_status
,
116 .ack_interrupt
= &cis820x_ack_interrupt
,
117 .config_intr
= &cis820x_config_intr
,
118 .driver
= { .owner
= THIS_MODULE
,},
122 static struct phy_driver cis8204_driver
= {
123 .phy_id
= 0x000fc440,
124 .name
= "Cicada Cis8204",
125 .phy_id_mask
= 0x000fffc0,
126 .features
= PHY_GBIT_FEATURES
,
127 .flags
= PHY_HAS_INTERRUPT
,
128 .config_init
= &cis820x_config_init
,
129 .config_aneg
= &genphy_config_aneg
,
130 .read_status
= &genphy_read_status
,
131 .ack_interrupt
= &cis820x_ack_interrupt
,
132 .config_intr
= &cis820x_config_intr
,
133 .driver
= { .owner
= THIS_MODULE
,},
136 static int __init
cicada_init(void)
140 ret
= phy_driver_register(&cis8204_driver
);
144 ret
= phy_driver_register(&cis8201_driver
);
150 phy_driver_unregister(&cis8204_driver
);
155 static void __exit
cicada_exit(void)
157 phy_driver_unregister(&cis8204_driver
);
158 phy_driver_unregister(&cis8201_driver
);
161 module_init(cicada_init
);
162 module_exit(cicada_exit
);