drivers/net/qla3xxx.h

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7 #ifndef _QLA3XXX_H_
   8 #define _QLA3XXX_H_
   9
  10 /*
  11  * IOCB Definitions...
  12  */
  13 #pragma pack(1)
  14
  15 #define OPCODE_OB_MAC_IOCB_FN0          0x01
  16 #define OPCODE_OB_MAC_IOCB_FN2          0x21
  17 #define OPCODE_OB_TCP_IOCB_FN0          0x03
  18 #define OPCODE_OB_TCP_IOCB_FN2          0x23
  19 #define OPCODE_UPDATE_NCB_IOCB_FN0      0x00
  20 #define OPCODE_UPDATE_NCB_IOCB_FN2      0x20
  21
  22 #define OPCODE_UPDATE_NCB_IOCB      0xF0
  23 #define OPCODE_IB_MAC_IOCB          0xF9
  24 #define OPCODE_IB_IP_IOCB           0xFA
  25 #define OPCODE_IB_TCP_IOCB          0xFB
  26 #define OPCODE_DUMP_PROTO_IOCB      0xFE
  27 #define OPCODE_BUFFER_ALERT_IOCB    0xFB
  28
  29 #define OPCODE_FUNC_ID_MASK                 0x30
  30 #define OUTBOUND_MAC_IOCB                   0x01        /* plus function bits */
  31 #define OUTBOUND_TCP_IOCB                   0x03        /* plus function bits */
  32 #define UPDATE_NCB_IOCB                     0x00        /* plus function bits */
  33
  34 #define FN0_MA_BITS_MASK    0x00
  35 #define FN1_MA_BITS_MASK    0x80
  36
  37 struct ob_mac_iocb_req {
  38         u8 opcode;
  39         u8 flags;
  40 #define OB_MAC_IOCB_REQ_MA  0xC0
  41 #define OB_MAC_IOCB_REQ_F   0x20
  42 #define OB_MAC_IOCB_REQ_X   0x10
  43 #define OB_MAC_IOCB_REQ_D   0x02
  44 #define OB_MAC_IOCB_REQ_I   0x01
  45         __le16 reserved0;
  46
  47         __le32 transaction_id;
  48         __le16 data_len;
  49         __le16 reserved1;
  50         __le32 reserved2;
  51         __le32 reserved3;
  52         __le32 buf_addr0_low;
  53         __le32 buf_addr0_high;
  54         __le32 buf_0_len;
  55         __le32 buf_addr1_low;
  56         __le32 buf_addr1_high;
  57         __le32 buf_1_len;
  58         __le32 buf_addr2_low;
  59         __le32 buf_addr2_high;
  60         __le32 buf_2_len;
  61         __le32 reserved4;
  62         __le32 reserved5;
  63 };
  64 /*
  65  * The following constants define control bits for buffer
  66  * length fields for all IOCB's.
  67  */
  68 #define OB_MAC_IOCB_REQ_E   0x80000000  /* Last valid buffer in list. */
  69 #define OB_MAC_IOCB_REQ_C   0x40000000  /* points to an OAL. (continuation) */
  70 #define OB_MAC_IOCB_REQ_L   0x20000000  /* Auburn local address pointer. */
  71 #define OB_MAC_IOCB_REQ_R   0x10000000  /* 32-bit address pointer. */
  72
  73 struct ob_mac_iocb_rsp {
  74         u8 opcode;
  75         u8 flags;
  76 #define OB_MAC_IOCB_RSP_P   0x08
  77 #define OB_MAC_IOCB_RSP_S   0x02
  78 #define OB_MAC_IOCB_RSP_I   0x01
  79
  80         __le16 reserved0;
  81         __le32 transaction_id;
  82         __le32 reserved1;
  83         __le32 reserved2;
  84 };
  85
  86 struct ib_mac_iocb_rsp {
  87         u8 opcode;
  88         u8 flags;
  89 #define IB_MAC_IOCB_RSP_S   0x80
  90 #define IB_MAC_IOCB_RSP_H1  0x40
  91 #define IB_MAC_IOCB_RSP_H0  0x20
  92 #define IB_MAC_IOCB_RSP_B   0x10
  93 #define IB_MAC_IOCB_RSP_M   0x08
  94 #define IB_MAC_IOCB_RSP_MA  0x07
  95
  96         __le16 length;
  97         __le32 reserved;
  98         __le32 ial_low;
  99         __le32 ial_high;
 100
 101 };
 102
 103 struct ob_ip_iocb_req {
 104         u8 opcode;
 105         __le16 flags;
 106 #define OB_IP_IOCB_REQ_O        0x100
 107 #define OB_IP_IOCB_REQ_H        0x008
 108 #define OB_IP_IOCB_REQ_U        0x004
 109 #define OB_IP_IOCB_REQ_D        0x002
 110 #define OB_IP_IOCB_REQ_I        0x001
 111
 112         u8 reserved0;
 113
 114         __le32 transaction_id;
 115         __le16 data_len;
 116         __le16 reserved1;
 117         __le32 hncb_ptr_low;
 118         __le32 hncb_ptr_high;
 119         __le32 buf_addr0_low;
 120         __le32 buf_addr0_high;
 121         __le32 buf_0_len;
 122         __le32 buf_addr1_low;
 123         __le32 buf_addr1_high;
 124         __le32 buf_1_len;
 125         __le32 buf_addr2_low;
 126         __le32 buf_addr2_high;
 127         __le32 buf_2_len;
 128         __le32 reserved2;
 129         __le32 reserved3;
 130 };
 131
 132 /* defines for BufferLength fields above */
 133 #define OB_IP_IOCB_REQ_E    0x80000000
 134 #define OB_IP_IOCB_REQ_C    0x40000000
 135 #define OB_IP_IOCB_REQ_L    0x20000000
 136 #define OB_IP_IOCB_REQ_R    0x10000000
 137
 138 struct ob_ip_iocb_rsp {
 139         u8 opcode;
 140         u8 flags;
 141 #define OB_MAC_IOCB_RSP_E       0x08
 142 #define OB_MAC_IOCB_RSP_L       0x04
 143 #define OB_MAC_IOCB_RSP_S       0x02
 144 #define OB_MAC_IOCB_RSP_I       0x01
 145
 146         __le16 reserved0;
 147         __le32 transaction_id;
 148         __le32 reserved1;
 149         __le32 reserved2;
 150 };
 151
 152 struct ob_tcp_iocb_req {
 153         u8 opcode;
 154
 155         u8 flags0;
 156 #define OB_TCP_IOCB_REQ_P       0x80
 157 #define OB_TCP_IOCB_REQ_CI      0x20
 158 #define OB_TCP_IOCB_REQ_H       0x10
 159 #define OB_TCP_IOCB_REQ_LN      0x08
 160 #define OB_TCP_IOCB_REQ_K       0x04
 161 #define OB_TCP_IOCB_REQ_D       0x02
 162 #define OB_TCP_IOCB_REQ_I       0x01
 163
 164         u8 flags1;
 165 #define OB_TCP_IOCB_REQ_OSM     0x40
 166 #define OB_TCP_IOCB_REQ_URG     0x20
 167 #define OB_TCP_IOCB_REQ_ACK     0x10
 168 #define OB_TCP_IOCB_REQ_PSH     0x08
 169 #define OB_TCP_IOCB_REQ_RST     0x04
 170 #define OB_TCP_IOCB_REQ_SYN     0x02
 171 #define OB_TCP_IOCB_REQ_FIN     0x01
 172
 173         u8 options_len;
 174 #define OB_TCP_IOCB_REQ_OMASK   0xF0
 175 #define OB_TCP_IOCB_REQ_SHIFT   4
 176
 177         __le32 transaction_id;
 178         __le32 data_len;
 179         __le32 hncb_ptr_low;
 180         __le32 hncb_ptr_high;
 181         __le32 buf_addr0_low;
 182         __le32 buf_addr0_high;
 183         __le32 buf_0_len;
 184         __le32 buf_addr1_low;
 185         __le32 buf_addr1_high;
 186         __le32 buf_1_len;
 187         __le32 buf_addr2_low;
 188         __le32 buf_addr2_high;
 189         __le32 buf_2_len;
 190         __le32 time_stamp;
 191         __le32 reserved1;
 192 };
 193
 194 struct ob_tcp_iocb_rsp {
 195         u8 opcode;
 196
 197         u8 flags0;
 198 #define OB_TCP_IOCB_RSP_C       0x20
 199 #define OB_TCP_IOCB_RSP_H       0x10
 200 #define OB_TCP_IOCB_RSP_LN      0x08
 201 #define OB_TCP_IOCB_RSP_K       0x04
 202 #define OB_TCP_IOCB_RSP_D       0x02
 203 #define OB_TCP_IOCB_RSP_I       0x01
 204
 205         u8 flags1;
 206 #define OB_TCP_IOCB_RSP_E       0x10
 207 #define OB_TCP_IOCB_RSP_W       0x08
 208 #define OB_TCP_IOCB_RSP_P       0x04
 209 #define OB_TCP_IOCB_RSP_T       0x02
 210 #define OB_TCP_IOCB_RSP_F       0x01
 211
 212         u8 state;
 213 #define OB_TCP_IOCB_RSP_SMASK   0xF0
 214 #define OB_TCP_IOCB_RSP_SHIFT   4
 215
 216         __le32 transaction_id;
 217         __le32 local_ncb_ptr;
 218         __le32 reserved0;
 219 };
 220
 221 struct ib_ip_iocb_rsp {
 222         u8 opcode;
 223         u8 flags;
 224 #define IB_IP_IOCB_RSP_S        0x80
 225 #define IB_IP_IOCB_RSP_H1       0x40
 226 #define IB_IP_IOCB_RSP_H0       0x20
 227 #define IB_IP_IOCB_RSP_B        0x10
 228 #define IB_IP_IOCB_RSP_M        0x08
 229 #define IB_IP_IOCB_RSP_MA       0x07
 230
 231         __le16 length;
 232         __le16 checksum;
 233         __le16 reserved;
 234 #define IB_IP_IOCB_RSP_R        0x01
 235         __le32 ial_low;
 236         __le32 ial_high;
 237 };
 238
 239 struct ib_tcp_iocb_rsp {
 240         u8 opcode;
 241         u8 flags;
 242 #define IB_TCP_IOCB_RSP_P       0x80
 243 #define IB_TCP_IOCB_RSP_T       0x40
 244 #define IB_TCP_IOCB_RSP_D       0x20
 245 #define IB_TCP_IOCB_RSP_N       0x10
 246 #define IB_TCP_IOCB_RSP_IP      0x03
 247 #define IB_TCP_FLAG_MASK        0xf0
 248 #define IB_TCP_FLAG_IOCB_SYN    0x00
 249
 250 #define TCP_IB_RSP_FLAGS(x) (x->flags & ~IB_TCP_FLAG_MASK)
 251
 252         __le16 length;
 253         __le32 hncb_ref_num;
 254         __le32 ial_low;
 255         __le32 ial_high;
 256 };
 257
 258 struct net_rsp_iocb {
 259         u8 opcode;
 260         u8 flags;
 261         __le16 reserved0;
 262         __le32 reserved[3];
 263 };
 264 #pragma pack()
 265
 266 /*
 267  * Register Definitions...
 268  */
 269 #define PORT0_PHY_ADDRESS   0x1e00
 270 #define PORT1_PHY_ADDRESS   0x1f00
 271
 272 #define ETHERNET_CRC_SIZE   4
 273
 274 #define MII_SCAN_REGISTER 0x00000001
 275
 276 /* 32-bit ispControlStatus */
 277 enum {
 278         ISP_CONTROL_NP_MASK = 0x0003,
 279         ISP_CONTROL_NP_PCSR = 0x0000,
 280         ISP_CONTROL_NP_HMCR = 0x0001,
 281         ISP_CONTROL_NP_LRAMCR = 0x0002,
 282         ISP_CONTROL_NP_PSR = 0x0003,
 283         ISP_CONTROL_RI = 0x0008,
 284         ISP_CONTROL_CI = 0x0010,
 285         ISP_CONTROL_PI = 0x0020,
 286         ISP_CONTROL_IN = 0x0040,
 287         ISP_CONTROL_BE = 0x0080,
 288         ISP_CONTROL_FN_MASK = 0x0700,
 289         ISP_CONTROL_FN0_NET = 0x0400,
 290         ISP_CONTROL_FN0_SCSI = 0x0500,
 291         ISP_CONTROL_FN1_NET = 0x0600,
 292         ISP_CONTROL_FN1_SCSI = 0x0700,
 293         ISP_CONTROL_LINK_DN_0 = 0x0800,
 294         ISP_CONTROL_LINK_DN_1 = 0x1000,
 295         ISP_CONTROL_FSR = 0x2000,
 296         ISP_CONTROL_FE = 0x4000,
 297         ISP_CONTROL_SR = 0x8000,
 298 };
 299
 300 /* 32-bit ispInterruptMaskReg */
 301 enum {
 302         ISP_IMR_ENABLE_INT = 0x0004,
 303         ISP_IMR_DISABLE_RESET_INT = 0x0008,
 304         ISP_IMR_DISABLE_CMPL_INT = 0x0010,
 305         ISP_IMR_DISABLE_PROC_INT = 0x0020,
 306 };
 307
 308 /* 32-bit serialPortInterfaceReg */
 309 enum {
 310         ISP_SERIAL_PORT_IF_CLK = 0x0001,
 311         ISP_SERIAL_PORT_IF_CS = 0x0002,
 312         ISP_SERIAL_PORT_IF_D0 = 0x0004,
 313         ISP_SERIAL_PORT_IF_DI = 0x0008,
 314         ISP_NVRAM_MASK = (0x000F << 16),
 315         ISP_SERIAL_PORT_IF_WE = 0x0010,
 316         ISP_SERIAL_PORT_IF_NVR_MASK = 0x001F,
 317         ISP_SERIAL_PORT_IF_SCI = 0x0400,
 318         ISP_SERIAL_PORT_IF_SC0 = 0x0800,
 319         ISP_SERIAL_PORT_IF_SCE = 0x1000,
 320         ISP_SERIAL_PORT_IF_SDI = 0x2000,
 321         ISP_SERIAL_PORT_IF_SDO = 0x4000,
 322         ISP_SERIAL_PORT_IF_SDE = 0x8000,
 323         ISP_SERIAL_PORT_IF_I2C_MASK = 0xFC00,
 324 };
 325
 326 /* semaphoreReg */
 327 enum {
 328         QL_RESOURCE_MASK_BASE_CODE = 0x7,
 329         QL_RESOURCE_BITS_BASE_CODE = 0x4,
 330         QL_DRVR_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 1),
 331         QL_DDR_RAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 4),
 332         QL_PHY_GIO_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 7),
 333         QL_NVRAM_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 10),
 334         QL_FLASH_SEM_BITS = (QL_RESOURCE_BITS_BASE_CODE << 13),
 335         QL_DRVR_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (1 + 16)),
 336         QL_DDR_RAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (4 + 16)),
 337         QL_PHY_GIO_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (7 + 16)),
 338         QL_NVRAM_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (10 + 16)),
 339         QL_FLASH_SEM_MASK = (QL_RESOURCE_MASK_BASE_CODE << (13 + 16)),
 340 };
 341
 342  /*
 343   * QL3XXX memory-mapped registers
 344   * QL3XXX has 4 "pages" of registers, each page occupying
 345   * 256 bytes.  Each page has a "common" area at the start and then
 346   * page-specific registers after that.
 347   */
 348 struct ql3xxx_common_registers {
 349         u32 MB0;                /* Offset 0x00 */
 350         u32 MB1;                /* Offset 0x04 */
 351         u32 MB2;                /* Offset 0x08 */
 352         u32 MB3;                /* Offset 0x0c */
 353         u32 MB4;                /* Offset 0x10 */
 354         u32 MB5;                /* Offset 0x14 */
 355         u32 MB6;                /* Offset 0x18 */
 356         u32 MB7;                /* Offset 0x1c */
 357         u32 flashBiosAddr;
 358         u32 flashBiosData;
 359         u32 ispControlStatus;
 360         u32 ispInterruptMaskReg;
 361         u32 serialPortInterfaceReg;
 362         u32 semaphoreReg;
 363         u32 reqQProducerIndex;
 364         u32 rspQConsumerIndex;
 365
 366         u32 rxLargeQProducerIndex;
 367         u32 rxSmallQProducerIndex;
 368         u32 arcMadiCommand;
 369         u32 arcMadiData;
 370 };
 371
 372 enum {
 373         EXT_HW_CONFIG_SP_MASK = 0x0006,
 374         EXT_HW_CONFIG_SP_NONE = 0x0000,
 375         EXT_HW_CONFIG_SP_BYTE_PARITY = 0x0002,
 376         EXT_HW_CONFIG_SP_ECC = 0x0004,
 377         EXT_HW_CONFIG_SP_ECCx = 0x0006,
 378         EXT_HW_CONFIG_SIZE_MASK = 0x0060,
 379         EXT_HW_CONFIG_SIZE_128M = 0x0000,
 380         EXT_HW_CONFIG_SIZE_256M = 0x0020,
 381         EXT_HW_CONFIG_SIZE_512M = 0x0040,
 382         EXT_HW_CONFIG_SIZE_INVALID = 0x0060,
 383         EXT_HW_CONFIG_PD = 0x0080,
 384         EXT_HW_CONFIG_FW = 0x0200,
 385         EXT_HW_CONFIG_US = 0x0400,
 386         EXT_HW_CONFIG_DCS_MASK = 0x1800,
 387         EXT_HW_CONFIG_DCS_9MA = 0x0000,
 388         EXT_HW_CONFIG_DCS_15MA = 0x0800,
 389         EXT_HW_CONFIG_DCS_18MA = 0x1000,
 390         EXT_HW_CONFIG_DCS_24MA = 0x1800,
 391         EXT_HW_CONFIG_DDS_MASK = 0x6000,
 392         EXT_HW_CONFIG_DDS_9MA = 0x0000,
 393         EXT_HW_CONFIG_DDS_15MA = 0x2000,
 394         EXT_HW_CONFIG_DDS_18MA = 0x4000,
 395         EXT_HW_CONFIG_DDS_24MA = 0x6000,
 396 };
 397
 398 /* InternalChipConfig */
 399 enum {
 400         INTERNAL_CHIP_DM = 0x0001,
 401         INTERNAL_CHIP_SD = 0x0002,
 402         INTERNAL_CHIP_RAP_MASK = 0x000C,
 403         INTERNAL_CHIP_RAP_RR = 0x0000,
 404         INTERNAL_CHIP_RAP_NRM = 0x0004,
 405         INTERNAL_CHIP_RAP_ERM = 0x0008,
 406         INTERNAL_CHIP_RAP_ERMx = 0x000C,
 407         INTERNAL_CHIP_WE = 0x0010,
 408         INTERNAL_CHIP_EF = 0x0020,
 409         INTERNAL_CHIP_FR = 0x0040,
 410         INTERNAL_CHIP_FW = 0x0080,
 411         INTERNAL_CHIP_FI = 0x0100,
 412         INTERNAL_CHIP_FT = 0x0200,
 413 };
 414
 415 /* portControl */
 416 enum {
 417         PORT_CONTROL_DS = 0x0001,
 418         PORT_CONTROL_HH = 0x0002,
 419         PORT_CONTROL_EI = 0x0004,
 420         PORT_CONTROL_ET = 0x0008,
 421         PORT_CONTROL_EF = 0x0010,
 422         PORT_CONTROL_DRM = 0x0020,
 423         PORT_CONTROL_RLB = 0x0040,
 424         PORT_CONTROL_RCB = 0x0080,
 425         PORT_CONTROL_MAC = 0x0100,
 426         PORT_CONTROL_IPV = 0x0200,
 427         PORT_CONTROL_IFP = 0x0400,
 428         PORT_CONTROL_ITP = 0x0800,
 429         PORT_CONTROL_FI = 0x1000,
 430         PORT_CONTROL_DFP = 0x2000,
 431         PORT_CONTROL_OI = 0x4000,
 432         PORT_CONTROL_CC = 0x8000,
 433 };
 434
 435 /* portStatus */
 436 enum {
 437         PORT_STATUS_SM0 = 0x0001,
 438         PORT_STATUS_SM1 = 0x0002,
 439         PORT_STATUS_X = 0x0008,
 440         PORT_STATUS_DL = 0x0080,
 441         PORT_STATUS_IC = 0x0200,
 442         PORT_STATUS_MRC = 0x0400,
 443         PORT_STATUS_NL = 0x0800,
 444         PORT_STATUS_REV_ID_MASK = 0x7000,
 445         PORT_STATUS_REV_ID_1 = 0x1000,
 446         PORT_STATUS_REV_ID_2 = 0x2000,
 447         PORT_STATUS_REV_ID_3 = 0x3000,
 448         PORT_STATUS_64 = 0x8000,
 449         PORT_STATUS_UP0 = 0x10000,
 450         PORT_STATUS_AC0 = 0x20000,
 451         PORT_STATUS_AE0 = 0x40000,
 452         PORT_STATUS_UP1 = 0x100000,
 453         PORT_STATUS_AC1 = 0x200000,
 454         PORT_STATUS_AE1 = 0x400000,
 455         PORT_STATUS_F0_ENABLED = 0x1000000,
 456         PORT_STATUS_F1_ENABLED = 0x2000000,
 457         PORT_STATUS_F2_ENABLED = 0x4000000,
 458         PORT_STATUS_F3_ENABLED = 0x8000000,
 459 };
 460
 461 /* macMIIMgmtControlReg */
 462 enum {
 463         MAC_ADDR_INDIRECT_PTR_REG_RP_MASK = 0x0003,
 464         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_LWR = 0x0000,
 465         MAC_ADDR_INDIRECT_PTR_REG_RP_PRI_UPR = 0x0001,
 466         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_LWR = 0x0002,
 467         MAC_ADDR_INDIRECT_PTR_REG_RP_SEC_UPR = 0x0003,
 468         MAC_ADDR_INDIRECT_PTR_REG_PR = 0x0008,
 469         MAC_ADDR_INDIRECT_PTR_REG_SS = 0x0010,
 470         MAC_ADDR_INDIRECT_PTR_REG_SE = 0x0020,
 471         MAC_ADDR_INDIRECT_PTR_REG_SP = 0x0040,
 472         MAC_ADDR_INDIRECT_PTR_REG_PE = 0x0080,
 473 };
 474
 475 /* macMIIMgmtControlReg */
 476 enum {
 477         MAC_MII_CONTROL_RC = 0x0001,
 478         MAC_MII_CONTROL_SC = 0x0002,
 479         MAC_MII_CONTROL_AS = 0x0004,
 480         MAC_MII_CONTROL_NP = 0x0008,
 481         MAC_MII_CONTROL_CLK_SEL_MASK = 0x0070,
 482         MAC_MII_CONTROL_CLK_SEL_DIV2 = 0x0000,
 483         MAC_MII_CONTROL_CLK_SEL_DIV4 = 0x0010,
 484         MAC_MII_CONTROL_CLK_SEL_DIV6 = 0x0020,
 485         MAC_MII_CONTROL_CLK_SEL_DIV8 = 0x0030,
 486         MAC_MII_CONTROL_CLK_SEL_DIV10 = 0x0040,
 487         MAC_MII_CONTROL_CLK_SEL_DIV14 = 0x0050,
 488         MAC_MII_CONTROL_CLK_SEL_DIV20 = 0x0060,
 489         MAC_MII_CONTROL_CLK_SEL_DIV28 = 0x0070,
 490         MAC_MII_CONTROL_RM = 0x8000,
 491 };
 492
 493 /* macMIIStatusReg */
 494 enum {
 495         MAC_MII_STATUS_BSY = 0x0001,
 496         MAC_MII_STATUS_SC = 0x0002,
 497         MAC_MII_STATUS_NV = 0x0004,
 498 };
 499
 500 enum {
 501         MAC_CONFIG_REG_PE = 0x0001,
 502         MAC_CONFIG_REG_TF = 0x0002,
 503         MAC_CONFIG_REG_RF = 0x0004,
 504         MAC_CONFIG_REG_FD = 0x0008,
 505         MAC_CONFIG_REG_GM = 0x0010,
 506         MAC_CONFIG_REG_LB = 0x0020,
 507         MAC_CONFIG_REG_SR = 0x8000,
 508 };
 509
 510 enum {
 511         MAC_HALF_DUPLEX_REG_ED = 0x10000,
 512         MAC_HALF_DUPLEX_REG_NB = 0x20000,
 513         MAC_HALF_DUPLEX_REG_BNB = 0x40000,
 514         MAC_HALF_DUPLEX_REG_ALT = 0x80000,
 515 };
 516
 517 enum {
 518         IP_ADDR_INDEX_REG_MASK = 0x000f,
 519         IP_ADDR_INDEX_REG_FUNC_0_PRI = 0x0000,
 520         IP_ADDR_INDEX_REG_FUNC_0_SEC = 0x0001,
 521         IP_ADDR_INDEX_REG_FUNC_1_PRI = 0x0002,
 522         IP_ADDR_INDEX_REG_FUNC_1_SEC = 0x0003,
 523         IP_ADDR_INDEX_REG_FUNC_2_PRI = 0x0004,
 524         IP_ADDR_INDEX_REG_FUNC_2_SEC = 0x0005,
 525         IP_ADDR_INDEX_REG_FUNC_3_PRI = 0x0006,
 526         IP_ADDR_INDEX_REG_FUNC_3_SEC = 0x0007,
 527 };
 528
 529 enum {
 530         PROBE_MUX_ADDR_REG_MUX_SEL_MASK = 0x003f,
 531         PROBE_MUX_ADDR_REG_SYSCLK = 0x0000,
 532         PROBE_MUX_ADDR_REG_PCICLK = 0x0040,
 533         PROBE_MUX_ADDR_REG_NRXCLK = 0x0080,
 534         PROBE_MUX_ADDR_REG_CPUCLK = 0x00C0,
 535         PROBE_MUX_ADDR_REG_MODULE_SEL_MASK = 0x3f00,
 536         PROBE_MUX_ADDR_REG_UP = 0x4000,
 537         PROBE_MUX_ADDR_REG_RE = 0x8000,
 538 };
 539
 540 enum {
 541         STATISTICS_INDEX_REG_MASK = 0x01ff,
 542         STATISTICS_INDEX_REG_MAC0_TX_FRAME = 0x0000,
 543         STATISTICS_INDEX_REG_MAC0_TX_BYTES = 0x0001,
 544         STATISTICS_INDEX_REG_MAC0_TX_STAT1 = 0x0002,
 545         STATISTICS_INDEX_REG_MAC0_TX_STAT2 = 0x0003,
 546         STATISTICS_INDEX_REG_MAC0_TX_STAT3 = 0x0004,
 547         STATISTICS_INDEX_REG_MAC0_TX_STAT4 = 0x0005,
 548         STATISTICS_INDEX_REG_MAC0_TX_STAT5 = 0x0006,
 549         STATISTICS_INDEX_REG_MAC0_RX_FRAME = 0x0007,
 550         STATISTICS_INDEX_REG_MAC0_RX_BYTES = 0x0008,
 551         STATISTICS_INDEX_REG_MAC0_RX_STAT1 = 0x0009,
 552         STATISTICS_INDEX_REG_MAC0_RX_STAT2 = 0x000a,
 553         STATISTICS_INDEX_REG_MAC0_RX_STAT3 = 0x000b,
 554         STATISTICS_INDEX_REG_MAC0_RX_ERR_CRC = 0x000c,
 555         STATISTICS_INDEX_REG_MAC0_RX_ERR_ENC = 0x000d,
 556         STATISTICS_INDEX_REG_MAC0_RX_ERR_LEN = 0x000e,
 557         STATISTICS_INDEX_REG_MAC0_RX_STAT4 = 0x000f,
 558         STATISTICS_INDEX_REG_MAC1_TX_FRAME = 0x0010,
 559         STATISTICS_INDEX_REG_MAC1_TX_BYTES = 0x0011,
 560         STATISTICS_INDEX_REG_MAC1_TX_STAT1 = 0x0012,
 561         STATISTICS_INDEX_REG_MAC1_TX_STAT2 = 0x0013,
 562         STATISTICS_INDEX_REG_MAC1_TX_STAT3 = 0x0014,
 563         STATISTICS_INDEX_REG_MAC1_TX_STAT4 = 0x0015,
 564         STATISTICS_INDEX_REG_MAC1_TX_STAT5 = 0x0016,
 565         STATISTICS_INDEX_REG_MAC1_RX_FRAME = 0x0017,
 566         STATISTICS_INDEX_REG_MAC1_RX_BYTES = 0x0018,
 567         STATISTICS_INDEX_REG_MAC1_RX_STAT1 = 0x0019,
 568         STATISTICS_INDEX_REG_MAC1_RX_STAT2 = 0x001a,
 569         STATISTICS_INDEX_REG_MAC1_RX_STAT3 = 0x001b,
 570         STATISTICS_INDEX_REG_MAC1_RX_ERR_CRC = 0x001c,
 571         STATISTICS_INDEX_REG_MAC1_RX_ERR_ENC = 0x001d,
 572         STATISTICS_INDEX_REG_MAC1_RX_ERR_LEN = 0x001e,
 573         STATISTICS_INDEX_REG_MAC1_RX_STAT4 = 0x001f,
 574         STATISTICS_INDEX_REG_IP_TX_PKTS = 0x0020,
 575         STATISTICS_INDEX_REG_IP_TX_BYTES = 0x0021,
 576         STATISTICS_INDEX_REG_IP_TX_FRAG = 0x0022,
 577         STATISTICS_INDEX_REG_IP_RX_PKTS = 0x0023,
 578         STATISTICS_INDEX_REG_IP_RX_BYTES = 0x0024,
 579         STATISTICS_INDEX_REG_IP_RX_FRAG = 0x0025,
 580         STATISTICS_INDEX_REG_IP_DGRM_REASSEMBLY = 0x0026,
 581         STATISTICS_INDEX_REG_IP_V6_RX_PKTS = 0x0027,
 582         STATISTICS_INDEX_REG_IP_RX_PKTERR = 0x0028,
 583         STATISTICS_INDEX_REG_IP_REASSEMBLY_ERR = 0x0029,
 584         STATISTICS_INDEX_REG_TCP_TX_SEG = 0x0030,
 585         STATISTICS_INDEX_REG_TCP_TX_BYTES = 0x0031,
 586         STATISTICS_INDEX_REG_TCP_RX_SEG = 0x0032,
 587         STATISTICS_INDEX_REG_TCP_RX_BYTES = 0x0033,
 588         STATISTICS_INDEX_REG_TCP_TIMER_EXP = 0x0034,
 589         STATISTICS_INDEX_REG_TCP_RX_ACK = 0x0035,
 590         STATISTICS_INDEX_REG_TCP_TX_ACK = 0x0036,
 591         STATISTICS_INDEX_REG_TCP_RX_ERR = 0x0037,
 592         STATISTICS_INDEX_REG_TCP_RX_WIN_PROBE = 0x0038,
 593         STATISTICS_INDEX_REG_TCP_ECC_ERR_CORR = 0x003f,
 594 };
 595
 596 enum {
 597         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC0 = 0x00000001,
 598         PORT_FATAL_ERROR_STATUS_OFB_RE_MAC1 = 0x00000002,
 599         PORT_FATAL_ERROR_STATUS_OFB_WE = 0x00000004,
 600         PORT_FATAL_ERROR_STATUS_IFB_RE = 0x00000008,
 601         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC0 = 0x00000010,
 602         PORT_FATAL_ERROR_STATUS_IFB_WE_MAC1 = 0x00000020,
 603         PORT_FATAL_ERROR_STATUS_ODE_RE = 0x00000040,
 604         PORT_FATAL_ERROR_STATUS_ODE_WE = 0x00000080,
 605         PORT_FATAL_ERROR_STATUS_IDE_RE = 0x00000100,
 606         PORT_FATAL_ERROR_STATUS_IDE_WE = 0x00000200,
 607         PORT_FATAL_ERROR_STATUS_SDE_RE = 0x00000400,
 608         PORT_FATAL_ERROR_STATUS_SDE_WE = 0x00000800,
 609         PORT_FATAL_ERROR_STATUS_BLE = 0x00001000,
 610         PORT_FATAL_ERROR_STATUS_SPE = 0x00002000,
 611         PORT_FATAL_ERROR_STATUS_EP0 = 0x00004000,
 612         PORT_FATAL_ERROR_STATUS_EP1 = 0x00008000,
 613         PORT_FATAL_ERROR_STATUS_ICE = 0x00010000,
 614         PORT_FATAL_ERROR_STATUS_ILE = 0x00020000,
 615         PORT_FATAL_ERROR_STATUS_OPE = 0x00040000,
 616         PORT_FATAL_ERROR_STATUS_TA = 0x00080000,
 617         PORT_FATAL_ERROR_STATUS_MA = 0x00100000,
 618         PORT_FATAL_ERROR_STATUS_SCE = 0x00200000,
 619         PORT_FATAL_ERROR_STATUS_RPE = 0x00400000,
 620         PORT_FATAL_ERROR_STATUS_MPE = 0x00800000,
 621         PORT_FATAL_ERROR_STATUS_OCE = 0x01000000,
 622 };
 623
 624 /*
 625  *  port control and status page - page 0
 626  */
 627
 628 struct ql3xxx_port_registers {
 629         struct ql3xxx_common_registers CommonRegs;
 630
 631         u32 ExternalHWConfig;
 632         u32 InternalChipConfig;
 633         u32 portControl;
 634         u32 portStatus;
 635         u32 macAddrIndirectPtrReg;
 636         u32 macAddrDataReg;
 637         u32 macMIIMgmtControlReg;
 638         u32 macMIIMgmtAddrReg;
 639         u32 macMIIMgmtDataReg;
 640         u32 macMIIStatusReg;
 641         u32 mac0ConfigReg;
 642         u32 mac0IpgIfgReg;
 643         u32 mac0HalfDuplexReg;
 644         u32 mac0MaxFrameLengthReg;
 645         u32 mac0PauseThresholdReg;
 646         u32 mac1ConfigReg;
 647         u32 mac1IpgIfgReg;
 648         u32 mac1HalfDuplexReg;
 649         u32 mac1MaxFrameLengthReg;
 650         u32 mac1PauseThresholdReg;
 651         u32 ipAddrIndexReg;
 652         u32 ipAddrDataReg;
 653         u32 ipReassemblyTimeout;
 654         u32 tcpMaxWindow;
 655         u32 currentTcpTimestamp[2];
 656         u32 internalRamRWAddrReg;
 657         u32 internalRamWDataReg;
 658         u32 reclaimedBufferAddrRegLow;
 659         u32 reclaimedBufferAddrRegHigh;
 660         u32 reserved[2];
 661         u32 fpgaRevID;
 662         u32 localRamAddr;
 663         u32 localRamDataAutoIncr;
 664         u32 localRamDataNonIncr;
 665         u32 gpOutput;
 666         u32 gpInput;
 667         u32 probeMuxAddr;
 668         u32 probeMuxData;
 669         u32 statisticsIndexReg;
 670         u32 statisticsReadDataRegAutoIncr;
 671         u32 statisticsReadDataRegNoIncr;
 672         u32 PortFatalErrStatus;
 673 };
 674
 675 /*
 676  * port host memory config page - page 1
 677  */
 678 struct ql3xxx_host_memory_registers {
 679         struct ql3xxx_common_registers CommonRegs;
 680
 681         u32 reserved[12];
 682
 683         /* Network Request Queue */
 684         u32 reqConsumerIndex;
 685         u32 reqConsumerIndexAddrLow;
 686         u32 reqConsumerIndexAddrHigh;
 687         u32 reqBaseAddrLow;
 688         u32 reqBaseAddrHigh;
 689         u32 reqLength;
 690
 691         /* Network Completion Queue */
 692         u32 rspProducerIndex;
 693         u32 rspProducerIndexAddrLow;
 694         u32 rspProducerIndexAddrHigh;
 695         u32 rspBaseAddrLow;
 696         u32 rspBaseAddrHigh;
 697         u32 rspLength;
 698
 699         /* RX Large Buffer Queue */
 700         u32 rxLargeQConsumerIndex;
 701         u32 rxLargeQBaseAddrLow;
 702         u32 rxLargeQBaseAddrHigh;
 703         u32 rxLargeQLength;
 704         u32 rxLargeBufferLength;
 705
 706         /* RX Small Buffer Queue */
 707         u32 rxSmallQConsumerIndex;
 708         u32 rxSmallQBaseAddrLow;
 709         u32 rxSmallQBaseAddrHigh;
 710         u32 rxSmallQLength;
 711         u32 rxSmallBufferLength;
 712
 713 };
 714
 715 /*
 716  *  port local RAM page - page 2
 717  */
 718 struct ql3xxx_local_ram_registers {
 719         struct ql3xxx_common_registers CommonRegs;
 720         u32 bufletSize;
 721         u32 maxBufletCount;
 722         u32 currentBufletCount;
 723         u32 reserved;
 724         u32 freeBufletThresholdLow;
 725         u32 freeBufletThresholdHigh;
 726         u32 ipHashTableBase;
 727         u32 ipHashTableCount;
 728         u32 tcpHashTableBase;
 729         u32 tcpHashTableCount;
 730         u32 ncbBase;
 731         u32 maxNcbCount;
 732         u32 currentNcbCount;
 733         u32 drbBase;
 734         u32 maxDrbCount;
 735         u32 currentDrbCount;
 736 };
 737
 738 /*
 739  * definitions for Semaphore bits in Semaphore/Serial NVRAM interface register
 740  */
 741
 742 #define LS_64BITS(x)    (u32)(0xffffffff & ((u64)x))
 743 #define MS_64BITS(x)    (u32)(0xffffffff & (((u64)x)>>16>>16) )
 744
 745 /*
 746  * I/O register
 747  */
 748
 749 enum {
 750         CONTROL_REG = 0,
 751         STATUS_REG = 1,
 752         PHY_STAT_LINK_UP = 0x0004,
 753         PHY_CTRL_LOOPBACK = 0x4000,
 754
 755         PETBI_CONTROL_REG = 0x00,
 756         PETBI_CTRL_SOFT_RESET = 0x8000,
 757         PETBI_CTRL_AUTO_NEG = 0x1000,
 758         PETBI_CTRL_RESTART_NEG = 0x0200,
 759         PETBI_CTRL_FULL_DUPLEX = 0x0100,
 760         PETBI_CTRL_SPEED_1000 = 0x0040,
 761
 762         PETBI_STATUS_REG = 0x01,
 763         PETBI_STAT_NEG_DONE = 0x0020,
 764         PETBI_STAT_LINK_UP = 0x0004,
 765
 766         PETBI_NEG_ADVER = 0x04,
 767         PETBI_NEG_PAUSE = 0x0080,
 768         PETBI_NEG_PAUSE_MASK = 0x0180,
 769         PETBI_NEG_DUPLEX = 0x0020,
 770         PETBI_NEG_DUPLEX_MASK = 0x0060,
 771
 772         PETBI_NEG_PARTNER = 0x05,
 773         PETBI_NEG_ERROR_MASK = 0x3000,
 774
 775         PETBI_EXPANSION_REG = 0x06,
 776         PETBI_EXP_PAGE_RX = 0x0002,
 777
 778         PETBI_TBI_CTRL = 0x11,
 779         PETBI_TBI_RESET = 0x8000,
 780         PETBI_TBI_AUTO_SENSE = 0x0100,
 781         PETBI_TBI_SERDES_MODE = 0x0010,
 782         PETBI_TBI_SERDES_WRAP = 0x0002,
 783
 784         AUX_CONTROL_STATUS = 0x1c,
 785         PHY_AUX_NEG_DONE = 0x8000,
 786         PHY_NEG_PARTNER = 5,
 787         PHY_AUX_DUPLEX_STAT = 0x0020,
 788         PHY_AUX_SPEED_STAT = 0x0018,
 789         PHY_AUX_NO_HW_STRAP = 0x0004,
 790         PHY_AUX_RESET_STICK = 0x0002,
 791         PHY_NEG_PAUSE = 0x0400,
 792         PHY_CTRL_SOFT_RESET = 0x8000,
 793         PHY_NEG_ADVER = 4,
 794         PHY_NEG_ADV_SPEED = 0x01e0,
 795         PHY_CTRL_RESTART_NEG = 0x0200,
 796 };
 797 enum {
 798 /* AM29LV Flash definitions     */
 799         FM93C56A_START = 0x1,
 800 /* Commands */
 801         FM93C56A_READ = 0x2,
 802         FM93C56A_WEN = 0x0,
 803         FM93C56A_WRITE = 0x1,
 804         FM93C56A_WRITE_ALL = 0x0,
 805         FM93C56A_WDS = 0x0,
 806         FM93C56A_ERASE = 0x3,
 807         FM93C56A_ERASE_ALL = 0x0,
 808 /* Command Extentions */
 809         FM93C56A_WEN_EXT = 0x3,
 810         FM93C56A_WRITE_ALL_EXT = 0x1,
 811         FM93C56A_WDS_EXT = 0x0,
 812         FM93C56A_ERASE_ALL_EXT = 0x2,
 813 /* Special Bits */
 814         FM93C56A_READ_DUMMY_BITS = 1,
 815         FM93C56A_READY = 0,
 816         FM93C56A_BUSY = 1,
 817         FM93C56A_CMD_BITS = 2,
 818 /* AM29LV Flash definitions     */
 819         FM93C56A_SIZE_8 = 0x100,
 820         FM93C56A_SIZE_16 = 0x80,
 821         FM93C66A_SIZE_8 = 0x200,
 822         FM93C66A_SIZE_16 = 0x100,
 823         FM93C86A_SIZE_16 = 0x400,
 824 /* Address Bits */
 825         FM93C56A_NO_ADDR_BITS_16 = 8,
 826         FM93C56A_NO_ADDR_BITS_8 = 9,
 827         FM93C86A_NO_ADDR_BITS_16 = 10,
 828 /* Data Bits */
 829         FM93C56A_DATA_BITS_16 = 16,
 830         FM93C56A_DATA_BITS_8 = 8,
 831 };
 832 enum {
 833 /* Auburn Bits */
 834             AUBURN_EEPROM_DI = 0x8,
 835         AUBURN_EEPROM_DI_0 = 0x0,
 836         AUBURN_EEPROM_DI_1 = 0x8,
 837         AUBURN_EEPROM_DO = 0x4,
 838         AUBURN_EEPROM_DO_0 = 0x0,
 839         AUBURN_EEPROM_DO_1 = 0x4,
 840         AUBURN_EEPROM_CS = 0x2,
 841         AUBURN_EEPROM_CS_0 = 0x0,
 842         AUBURN_EEPROM_CS_1 = 0x2,
 843         AUBURN_EEPROM_CLK_RISE = 0x1,
 844         AUBURN_EEPROM_CLK_FALL = 0x0,
 845 };
 846 enum {EEPROM_SIZE = FM93C86A_SIZE_16,
 847         EEPROM_NO_ADDR_BITS = FM93C86A_NO_ADDR_BITS_16,
 848         EEPROM_NO_DATA_BITS = FM93C56A_DATA_BITS_16,
 849 };
 850
 851 /*
 852  *  MAC Config data structure
 853  */
 854     struct eeprom_port_cfg {
 855         u16 etherMtu_mac;
 856         u16 pauseThreshold_mac;
 857         u16 resumeThreshold_mac;
 858         u16 portConfiguration;
 859 #define PORT_CONFIG_AUTO_NEG_ENABLED        0x8000
 860 #define PORT_CONFIG_SYM_PAUSE_ENABLED       0x4000
 861 #define PORT_CONFIG_FULL_DUPLEX_ENABLED     0x2000
 862 #define PORT_CONFIG_HALF_DUPLEX_ENABLED     0x1000
 863 #define PORT_CONFIG_1000MB_SPEED            0x0400
 864 #define PORT_CONFIG_100MB_SPEED             0x0200
 865 #define PORT_CONFIG_10MB_SPEED              0x0100
 866 #define PORT_CONFIG_LINK_SPEED_MASK         0x0F00
 867         u16 reserved[12];
 868
 869 };
 870
 871 /*
 872  * BIOS data structure
 873  */
 874 struct eeprom_bios_cfg {
 875         u16 SpinDlyEn:1, disBios:1, EnMemMap:1, EnSelectBoot:1, Reserved:12;
 876
 877         u8 bootID0:7, boodID0Valid:1;
 878         u8 bootLun0[8];
 879
 880         u8 bootID1:7, boodID1Valid:1;
 881         u8 bootLun1[8];
 882
 883         u16 MaxLunsTrgt;
 884         u8 reserved[10];
 885 };
 886
 887 /*
 888  *  Function Specific Data structure
 889  */
 890 struct eeprom_function_cfg {
 891         u8 reserved[30];
 892         u8 macAddress[6];
 893         u8 macAddressSecondary[6];
 894
 895         u16 subsysVendorId;
 896         u16 subsysDeviceId;
 897 };
 898
 899 /*
 900  *  EEPROM format
 901  */
 902 struct eeprom_data {
 903         u8 asicId[4];
 904         u8 version;
 905         u8 numPorts;
 906         u16 boardId;
 907
 908 #define EEPROM_BOARDID_STR_SIZE   16
 909 #define EEPROM_SERIAL_NUM_SIZE    16
 910
 911         u8 boardIdStr[16];
 912         u8 serialNumber[16];
 913         u16 extHwConfig;
 914         struct eeprom_port_cfg macCfg_port0;
 915         struct eeprom_port_cfg macCfg_port1;
 916         u16 bufletSize;
 917         u16 bufletCount;
 918         u16 tcpWindowThreshold50;
 919         u16 tcpWindowThreshold25;
 920         u16 tcpWindowThreshold0;
 921         u16 ipHashTableBaseHi;
 922         u16 ipHashTableBaseLo;
 923         u16 ipHashTableSize;
 924         u16 tcpHashTableBaseHi;
 925         u16 tcpHashTableBaseLo;
 926         u16 tcpHashTableSize;
 927         u16 ncbTableBaseHi;
 928         u16 ncbTableBaseLo;
 929         u16 ncbTableSize;
 930         u16 drbTableBaseHi;
 931         u16 drbTableBaseLo;
 932         u16 drbTableSize;
 933         u16 reserved_142[4];
 934         u16 ipReassemblyTimeout;
 935         u16 tcpMaxWindowSize;
 936         u16 ipSecurity;
 937 #define IPSEC_CONFIG_PRESENT 0x0001
 938         u8 reserved_156[294];
 939         u16 qDebug[8];
 940         struct eeprom_function_cfg funcCfg_fn0;
 941         u16 reserved_510;
 942         u8 oemSpace[432];
 943         struct eeprom_bios_cfg biosCfg_fn1;
 944         struct eeprom_function_cfg funcCfg_fn1;
 945         u16 reserved_1022;
 946         u8 reserved_1024[464];
 947         struct eeprom_function_cfg funcCfg_fn2;
 948         u16 reserved_1534;
 949         u8 reserved_1536[432];
 950         struct eeprom_bios_cfg biosCfg_fn3;
 951         struct eeprom_function_cfg funcCfg_fn3;
 952         u16 checksum;
 953 };
 954
 955 /*
 956  * General definitions...
 957  */
 958
 959 /*
 960  * Below are a number compiler switches for controlling driver behavior.
 961  * Some are not supported under certain conditions and are notated as such.
 962  */
 963
 964 #define QL3XXX_VENDOR_ID    0x1077
 965 #define QL3022_DEVICE_ID    0x3022
 966
 967 /* MTU & Frame Size stuff */
 968 #define NORMAL_MTU_SIZE                 ETH_DATA_LEN
 969 #define JUMBO_MTU_SIZE                  9000
 970 #define VLAN_ID_LEN                         2
 971
 972 /* Request Queue Related Definitions */
 973 #define NUM_REQ_Q_ENTRIES   256 /* so that 64 * 64  = 4096 (1 page) */
 974
 975 /* Response Queue Related Definitions */
 976 #define NUM_RSP_Q_ENTRIES   256 /* so that 256 * 16  = 4096 (1 page) */
 977
 978 /* Transmit and Receive Buffers */
 979 #define NUM_LBUFQ_ENTRIES       128
 980 #define NUM_SBUFQ_ENTRIES       64
 981 #define QL_SMALL_BUFFER_SIZE    32
 982 #define QL_ADDR_ELE_PER_BUFQ_ENTRY \
 983 (sizeof(struct lrg_buf_q_entry) / sizeof(struct bufq_addr_element))
 984     /* Each send has at least control block.  This is how many we keep. */
 985 #define NUM_SMALL_BUFFERS       NUM_SBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
 986 #define NUM_LARGE_BUFFERS       NUM_LBUFQ_ENTRIES * QL_ADDR_ELE_PER_BUFQ_ENTRY
 987 #define QL_HEADER_SPACE 32      /* make header space at top of skb. */
 988 /*
 989  * Large & Small Buffers for Receives
 990  */
 991 struct lrg_buf_q_entry {
 992
 993         u32 addr0_lower;
 994 #define IAL_LAST_ENTRY 0x00000001
 995 #define IAL_CONT_ENTRY 0x00000002
 996 #define IAL_FLAG_MASK  0x00000003
 997         u32 addr0_upper;
 998         u32 addr1_lower;
 999         u32 addr1_upper;
1000         u32 addr2_lower;
1001         u32 addr2_upper;
1002         u32 addr3_lower;
1003         u32 addr3_upper;
1004         u32 addr4_lower;
1005         u32 addr4_upper;
1006         u32 addr5_lower;
1007         u32 addr5_upper;
1008         u32 addr6_lower;
1009         u32 addr6_upper;
1010         u32 addr7_lower;
1011         u32 addr7_upper;
1012
1013 };
1014
1015 struct bufq_addr_element {
1016         u32 addr_low;
1017         u32 addr_high;
1018 };
1019
1020 #define QL_NO_RESET                     0
1021 #define QL_DO_RESET                     1
1022
1023 enum link_state_t {
1024         LS_UNKNOWN = 0,
1025         LS_DOWN,
1026         LS_DEGRADE,
1027         LS_RECOVER,
1028         LS_UP,
1029 };
1030
1031 struct ql_rcv_buf_cb {
1032         struct ql_rcv_buf_cb *next;
1033         struct sk_buff *skb;
1034          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1035          DECLARE_PCI_UNMAP_LEN(maplen);
1036         __le32 buf_phy_addr_low;
1037         __le32 buf_phy_addr_high;
1038         int index;
1039 };
1040
1041 struct ql_tx_buf_cb {
1042         struct sk_buff *skb;
1043         struct ob_mac_iocb_req *queue_entry ;
1044          DECLARE_PCI_UNMAP_ADDR(mapaddr);
1045          DECLARE_PCI_UNMAP_LEN(maplen);
1046 };
1047
1048 /* definitions for type field */
1049 #define QL_BUF_TYPE_MACIOCB 0x01
1050 #define QL_BUF_TYPE_IPIOCB  0x02
1051 #define QL_BUF_TYPE_TCPIOCB 0x03
1052
1053 /* qdev->flags definitions. */
1054 enum { QL_RESET_DONE = 1,       /* Reset finished. */
1055         QL_RESET_ACTIVE = 2,    /* Waiting for reset to finish. */
1056         QL_RESET_START = 3,     /* Please reset the chip. */
1057         QL_RESET_PER_SCSI = 4,  /* SCSI driver requests reset. */
1058         QL_TX_TIMEOUT = 5,      /* Timeout in progress. */
1059         QL_LINK_MASTER = 6,     /* This driver controls the link. */
1060         QL_ADAPTER_UP = 7,      /* Adapter has been brought up. */
1061         QL_THREAD_UP = 8,       /* This flag is available. */
1062         QL_LINK_UP = 9, /* Link Status. */
1063         QL_ALLOC_REQ_RSP_Q_DONE = 10,
1064         QL_ALLOC_BUFQS_DONE = 11,
1065         QL_ALLOC_SMALL_BUF_DONE = 12,
1066         QL_LINK_OPTICAL = 13,
1067         QL_MSI_ENABLED = 14,
1068 };
1069
1070 /*
1071  * ql3_adapter - The main Adapter structure definition.
1072  * This structure has all fields relevant to the hardware.
1073  */
1074
1075 struct ql3_adapter {
1076         u32 reserved_00;
1077         unsigned long flags;
1078
1079         /* PCI Configuration information for this device */
1080         struct pci_dev *pdev;
1081         struct net_device *ndev;        /* Parent NET device */
1082
1083         /* Hardware information */
1084         u8 chip_rev_id;
1085         u8 pci_slot;
1086         u8 pci_width;
1087         u8 pci_x;
1088         u32 msi;
1089         int index;
1090         struct timer_list adapter_timer;        /* timer used for various functions */
1091
1092         spinlock_t adapter_lock;
1093         spinlock_t hw_lock;
1094
1095         /* PCI Bus Relative Register Addresses */
1096         u8 __iomem *mmap_virt_base;     /* stores return value from ioremap() */
1097         struct ql3xxx_port_registers __iomem *mem_map_registers;
1098         u32 current_page;       /* tracks current register page */
1099
1100         u32 msg_enable;
1101         u8 reserved_01[2];
1102         u8 reserved_02[2];
1103
1104         /* Page for Shadow Registers */
1105         void *shadow_reg_virt_addr;
1106         dma_addr_t shadow_reg_phy_addr;
1107
1108         /* Net Request Queue */
1109         u32 req_q_size;
1110         u32 reserved_03;
1111         struct ob_mac_iocb_req *req_q_virt_addr;
1112         dma_addr_t req_q_phy_addr;
1113         u16 req_producer_index;
1114         u16 reserved_04;
1115         u16 *preq_consumer_index;
1116         u32 req_consumer_index_phy_addr_high;
1117         u32 req_consumer_index_phy_addr_low;
1118         atomic_t tx_count;
1119         struct ql_tx_buf_cb tx_buf[NUM_REQ_Q_ENTRIES];
1120
1121         /* Net Response Queue */
1122         u32 rsp_q_size;
1123         u32 eeprom_cmd_data;
1124         struct net_rsp_iocb *rsp_q_virt_addr;
1125         dma_addr_t rsp_q_phy_addr;
1126         struct net_rsp_iocb *rsp_current;
1127         u16 rsp_consumer_index;
1128         u16 reserved_06;
1129         u32 *prsp_producer_index;
1130         u32 rsp_producer_index_phy_addr_high;
1131         u32 rsp_producer_index_phy_addr_low;
1132
1133         /* Large Buffer Queue */
1134         u32 lrg_buf_q_alloc_size;
1135         u32 lrg_buf_q_size;
1136         void *lrg_buf_q_alloc_virt_addr;
1137         void *lrg_buf_q_virt_addr;
1138         dma_addr_t lrg_buf_q_alloc_phy_addr;
1139         dma_addr_t lrg_buf_q_phy_addr;
1140         u32 lrg_buf_q_producer_index;
1141         u32 lrg_buf_release_cnt;
1142         struct bufq_addr_element *lrg_buf_next_free;
1143
1144         /* Large (Receive) Buffers */
1145         struct ql_rcv_buf_cb lrg_buf[NUM_LARGE_BUFFERS];
1146         struct ql_rcv_buf_cb *lrg_buf_free_head;
1147         struct ql_rcv_buf_cb *lrg_buf_free_tail;
1148         u32 lrg_buf_free_count;
1149         u32 lrg_buffer_len;
1150         u32 lrg_buf_index;
1151         u32 lrg_buf_skb_check;
1152
1153         /* Small Buffer Queue */
1154         u32 small_buf_q_alloc_size;
1155         u32 small_buf_q_size;
1156         u32 small_buf_q_producer_index;
1157         void *small_buf_q_alloc_virt_addr;
1158         void *small_buf_q_virt_addr;
1159         dma_addr_t small_buf_q_alloc_phy_addr;
1160         dma_addr_t small_buf_q_phy_addr;
1161         u32 small_buf_index;
1162
1163         /* Small (Receive) Buffers */
1164         void *small_buf_virt_addr;
1165         dma_addr_t small_buf_phy_addr;
1166         u32 small_buf_phy_addr_low;
1167         u32 small_buf_phy_addr_high;
1168         u32 small_buf_release_cnt;
1169         u32 small_buf_total_size;
1170
1171         /* ISR related, saves status for DPC. */
1172         u32 control_status;
1173
1174         struct eeprom_data nvram_data;
1175         struct timer_list ioctl_timer;
1176         u32 port_link_state;
1177         u32 last_rsp_offset;
1178
1179         /* 4022 specific */
1180         u32 mac_index;          /* Driver's MAC number can be 0 or 1 for first and second networking functions respectively */
1181         u32 PHYAddr;            /* Address of PHY 0x1e00 Port 0 and 0x1f00 Port 1 */
1182         u32 mac_ob_opcode;      /* Opcode to use on mac transmission */
1183         u32 tcp_ob_opcode;      /* Opcode to use on tcp transmission */
1184         u32 update_ob_opcode;   /* Opcode to use for updating NCB */
1185         u32 mb_bit_mask;        /* MA Bits mask to use on transmission */
1186         u32 numPorts;
1187         struct net_device_stats stats;
1188         struct workqueue_struct *workqueue;
1189         struct work_struct reset_work;
1190         struct work_struct tx_timeout_work;
1191         u32 max_frame_size;
1192 };
1193
1194 #endif                          /* _QLA3XXX_H_ */