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[hh.org.git] / drivers / pci / hotplug / shpchp.h
blobea2087c34149f23244401e480b9cf491693b8a7c
1 /*
2 * Standard Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29 #ifndef _SHPCHP_H
30 #define _SHPCHP_H
31
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/pci_hotplug.h>
35 #include <linux/delay.h>
36 #include <linux/sched.h> /* signal_pending(), struct timer_list */
37 #include <linux/mutex.h>
38
39 #if !defined(MODULE)
40 #define MY_NAME "shpchp"
41 #else
42 #define MY_NAME THIS_MODULE->name
43 #endif
44
45 extern int shpchp_poll_mode;
46 extern int shpchp_poll_time;
47 extern int shpchp_debug;
48 extern struct workqueue_struct *shpchp_wq;
49
50 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
51 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
52 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
53 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
54 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
55
56 #define SLOT_NAME_SIZE 10
57 struct slot {
58 u8 bus;
59 u8 device;
60 u16 status;
61 u32 number;
62 u8 is_a_board;
63 u8 state;
64 u8 presence_save;
65 u8 pwr_save;
66 struct timer_list task_event;
67 u8 hp_slot;
68 struct controller *ctrl;
69 struct hpc_ops *hpc_ops;
70 struct hotplug_slot *hotplug_slot;
71 struct list_head slot_list;
72 char name[SLOT_NAME_SIZE];
73 struct work_struct work; /* work for button event */
74 struct mutex lock;
75 };
76
77 struct event_info {
78 u32 event_type;
79 struct slot *p_slot;
80 struct work_struct work;
81 };
82
83 struct controller {
84 struct mutex crit_sect; /* critical section mutex */
85 struct mutex cmd_lock; /* command lock */
86 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
87 int num_slots; /* Number of slots on ctlr */
88 int slot_num_inc; /* 1 or -1 */
89 struct pci_dev *pci_dev;
90 struct list_head slot_list;
91 struct hpc_ops *hpc_ops;
92 wait_queue_head_t queue; /* sleep & wake process */
93 u8 bus;
94 u8 device;
95 u8 function;
96 u8 slot_device_offset;
97 u8 add_support;
98 u32 pcix_misc2_reg; /* for amd pogo errata */
99 enum pci_bus_speed speed;
100 u32 first_slot; /* First physical slot number */
101 u8 slot_bus; /* Bus where the slots handled by this controller sit */
102 u32 cap_offset;
103 unsigned long mmio_base;
104 unsigned long mmio_size;
105 };
106
107
108 /* Define AMD SHPC ID */
109 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
110 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
111
112 /* AMD PCIX bridge registers */
113
114 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
115 #define PCIX_MISCII_OFFSET 0x48
116 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
117
118 /* AMD PCIX_MISCII masks and offsets */
119 #define PERRNONFATALENABLE_MASK 0x00040000
120 #define PERRFATALENABLE_MASK 0x00080000
121 #define PERRFLOODENABLE_MASK 0x00100000
122 #define SERRNONFATALENABLE_MASK 0x00200000
123 #define SERRFATALENABLE_MASK 0x00400000
124
125 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
126 #define PERR_OBSERVED_MASK 0x00000001
127
128 /* AMD PCIX_MEM_BASE_LIMIT masks */
129 #define RSE_MASK 0x40000000
130
131 #define INT_BUTTON_IGNORE 0
132 #define INT_PRESENCE_ON 1
133 #define INT_PRESENCE_OFF 2
134 #define INT_SWITCH_CLOSE 3
135 #define INT_SWITCH_OPEN 4
136 #define INT_POWER_FAULT 5
137 #define INT_POWER_FAULT_CLEAR 6
138 #define INT_BUTTON_PRESS 7
139 #define INT_BUTTON_RELEASE 8
140 #define INT_BUTTON_CANCEL 9
141
142 #define STATIC_STATE 0
143 #define BLINKINGON_STATE 1
144 #define BLINKINGOFF_STATE 2
145 #define POWERON_STATE 3
146 #define POWEROFF_STATE 4
147
148 #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
149
150 /* Error messages */
151 #define INTERLOCK_OPEN 0x00000002
152 #define ADD_NOT_SUPPORTED 0x00000003
153 #define CARD_FUNCTIONING 0x00000005
154 #define ADAPTER_NOT_SAME 0x00000006
155 #define NO_ADAPTER_PRESENT 0x00000009
156 #define NOT_ENOUGH_RESOURCES 0x0000000B
157 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
158 #define WRONG_BUS_FREQUENCY 0x0000000D
159 #define POWER_FAILURE 0x0000000E
160
161 #define REMOVE_NOT_SUPPORTED 0x00000003
162
163 #define DISABLE_CARD 1
164
165 /*
166 * error Messages
167 */
168 #define msg_initialization_err "Initialization failure, error=%d\n"
169 #define msg_button_on "PCI slot #%s - powering on due to button press.\n"
170 #define msg_button_off "PCI slot #%s - powering off due to button press.\n"
171 #define msg_button_cancel "PCI slot #%s - action canceled due to button press.\n"
172
173 /* sysfs functions for the hotplug controller info */
174 extern int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
175
176 extern int shpchp_sysfs_enable_slot(struct slot *slot);
177 extern int shpchp_sysfs_disable_slot(struct slot *slot);
178
179 extern u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
180 extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
181 extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
182 extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
183
184 /* pci functions */
185 extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
186 extern int shpchp_configure_device(struct slot *p_slot);
187 extern int shpchp_unconfigure_device(struct slot *p_slot);
188 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
189 extern void cleanup_slots(struct controller *ctrl);
190 extern void queue_pushbutton_work(void *data);
191
192
193 #ifdef CONFIG_ACPI
194 static inline int get_hp_params_from_firmware(struct pci_dev *dev,
195 struct hotplug_params *hpp)
196 {
197 if (ACPI_FAILURE(acpi_get_hp_params_from_firmware(dev->bus, hpp)))
198 return -ENODEV;
199 return 0;
200 }
201 #define get_hp_hw_control_from_firmware(pdev) \
202 do { \
203 if (DEVICE_ACPI_HANDLE(&(pdev->dev))) \
204 acpi_run_oshp(DEVICE_ACPI_HANDLE(&(pdev->dev))); \
205 } while (0)
206 #else
207 #define get_hp_params_from_firmware(dev, hpp) (-ENODEV)
208 #define get_hp_hw_control_from_firmware(dev) do { } while (0)
209 #endif
210
211 struct ctrl_reg {
212 volatile u32 base_offset;
213 volatile u32 slot_avail1;
214 volatile u32 slot_avail2;
215 volatile u32 slot_config;
216 volatile u16 sec_bus_config;
217 volatile u8 msi_ctrl;
218 volatile u8 prog_interface;
219 volatile u16 cmd;
220 volatile u16 cmd_status;
221 volatile u32 intr_loc;
222 volatile u32 serr_loc;
223 volatile u32 serr_intr_enable;
224 volatile u32 slot1;
225 volatile u32 slot2;
226 volatile u32 slot3;
227 volatile u32 slot4;
228 volatile u32 slot5;
229 volatile u32 slot6;
230 volatile u32 slot7;
231 volatile u32 slot8;
232 volatile u32 slot9;
233 volatile u32 slot10;
234 volatile u32 slot11;
235 volatile u32 slot12;
236 } __attribute__ ((packed));
237
238 /* offsets to the controller registers based on the above structure layout */
239 enum ctrl_offsets {
240 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
241 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
242 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
243 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
244 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
245 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
246 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
247 CMD = offsetof(struct ctrl_reg, cmd),
248 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
249 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
250 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
251 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
252 SLOT1 = offsetof(struct ctrl_reg, slot1),
253 SLOT2 = offsetof(struct ctrl_reg, slot2),
254 SLOT3 = offsetof(struct ctrl_reg, slot3),
255 SLOT4 = offsetof(struct ctrl_reg, slot4),
256 SLOT5 = offsetof(struct ctrl_reg, slot5),
257 SLOT6 = offsetof(struct ctrl_reg, slot6),
258 SLOT7 = offsetof(struct ctrl_reg, slot7),
259 SLOT8 = offsetof(struct ctrl_reg, slot8),
260 SLOT9 = offsetof(struct ctrl_reg, slot9),
261 SLOT10 = offsetof(struct ctrl_reg, slot10),
262 SLOT11 = offsetof(struct ctrl_reg, slot11),
263 SLOT12 = offsetof(struct ctrl_reg, slot12),
264 };
265 typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
266 struct php_ctlr_state_s {
267 struct php_ctlr_state_s *pnext;
268 struct pci_dev *pci_dev;
269 unsigned int irq;
270 unsigned long flags; /* spinlock's */
271 u32 slot_device_offset;
272 u32 num_slots;
273 struct timer_list int_poll_timer; /* Added for poll event */
274 php_intr_callback_t attention_button_callback;
275 php_intr_callback_t switch_change_callback;
276 php_intr_callback_t presence_change_callback;
277 php_intr_callback_t power_fault_callback;
278 void *callback_instance_id;
279 void __iomem *creg; /* Ptr to controller register space */
280 };
281 /* Inline functions */
282
283
284 /* Inline functions to check the sanity of a pointer that is passed to us */
285 static inline int slot_paranoia_check (struct slot *slot, const char *function)
286 {
287 if (!slot) {
288 dbg("%s - slot == NULL", function);
289 return -1;
290 }
291 if (!slot->hotplug_slot) {
292 dbg("%s - slot->hotplug_slot == NULL!", function);
293 return -1;
294 }
295 return 0;
296 }
297
298 static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
299 {
300 struct slot *slot;
301
302 if (!hotplug_slot) {
303 dbg("%s - hotplug_slot == NULL\n", function);
304 return NULL;
305 }
306
307 slot = (struct slot *)hotplug_slot->private;
308 if (slot_paranoia_check (slot, function))
309 return NULL;
310 return slot;
311 }
312
313 static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
314 {
315 struct slot *slot;
316
317 if (!ctrl)
318 return NULL;
319
320 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
321 if (slot->device == device)
322 return slot;
323 }
324
325 err("%s: slot (device=0x%x) not found\n", __FUNCTION__, device);
326
327 return NULL;
328 }
329
330 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
331 {
332 u32 pcix_misc2_temp;
333
334 /* save MiscII register */
335 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
336
337 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
338
339 /* clear SERR/PERR enable bits */
340 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
341 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
342 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
343 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
344 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
345 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
346 }
347
348 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
349 {
350 u32 pcix_misc2_temp;
351 u32 pcix_bridge_errors_reg;
352 u32 pcix_mem_base_reg;
353 u8 perr_set;
354 u8 rse_set;
355
356 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
357 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
358 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
359 if (perr_set) {
360 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
361
362 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
363 }
364
365 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
366 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
367 rse_set = pcix_mem_base_reg & RSE_MASK;
368 if (rse_set) {
369 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
370
371 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
372 }
373 /* restore MiscII register */
374 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
375
376 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
377 pcix_misc2_temp |= SERRFATALENABLE_MASK;
378 else
379 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
380
381 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
382 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
383 else
384 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
385
386 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
387 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
388 else
389 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
390
391 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
392 pcix_misc2_temp |= PERRFATALENABLE_MASK;
393 else
394 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
395
396 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
397 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
398 else
399 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
400 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
401 }
402
403 enum php_ctlr_type {
404 PCI,
405 ISA,
406 ACPI
407 };
408
409 int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
410
411 int shpc_get_ctlr_slot_config( struct controller *ctrl,
412 int *num_ctlr_slots,
413 int *first_device_num,
414 int *physical_slot_num,
415 int *updown,
416 int *flags);
417
418 struct hpc_ops {
419 int (*power_on_slot ) (struct slot *slot);
420 int (*slot_enable ) (struct slot *slot);
421 int (*slot_disable ) (struct slot *slot);
422 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed);
423 int (*get_power_status) (struct slot *slot, u8 *status);
424 int (*get_attention_status) (struct slot *slot, u8 *status);
425 int (*set_attention_status) (struct slot *slot, u8 status);
426 int (*get_latch_status) (struct slot *slot, u8 *status);
427 int (*get_adapter_status) (struct slot *slot, u8 *status);
428
429 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
430 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
431 int (*get_adapter_speed) (struct slot *slot, enum pci_bus_speed *speed);
432 int (*get_mode1_ECC_cap) (struct slot *slot, u8 *mode);
433 int (*get_prog_int) (struct slot *slot, u8 *prog_int);
434
435 int (*query_power_fault) (struct slot *slot);
436 void (*green_led_on) (struct slot *slot);
437 void (*green_led_off) (struct slot *slot);
438 void (*green_led_blink) (struct slot *slot);
439 void (*release_ctlr) (struct controller *ctrl);
440 int (*check_cmd_status) (struct controller *ctrl);
441 };
442
443 #endif /* _SHPCHP_H */
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