?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sync hh.org
[hh.org.git] / drivers / pci / hotplug / shpchp_hpc.c
blob83a5226ba9ed4918c4e46fb8f964aaf9a1b90922
1 /*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "shpchp.h"
37
38 #ifdef DEBUG
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
47
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50 #define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #else
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
68 #endif /* DEBUG */
69
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
75
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
84
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
92
93 /*
94 * Interrupt Locator Register definitions
95 */
96 #define CMD_INTR_PENDING (1 << 0)
97 #define SLOT_INTR_PENDING(i) (1 << (i + 1))
98
99 /*
100 * Controller SERR-INT Register
101 */
102 #define GLOBAL_INTR_MASK (1 << 0)
103 #define GLOBAL_SERR_MASK (1 << 1)
104 #define COMMAND_INTR_MASK (1 << 2)
105 #define ARBITER_SERR_MASK (1 << 3)
106 #define COMMAND_DETECTED (1 << 16)
107 #define ARBITER_DETECTED (1 << 17)
108 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
109
110 /*
111 * Logical Slot Register definitions
112 */
113 #define SLOT_REG(i) (SLOT1 + (4 * i))
114
115 #define SLOT_STATE_SHIFT (0)
116 #define SLOT_STATE_MASK (3 << 0)
117 #define SLOT_STATE_PWRONLY (1)
118 #define SLOT_STATE_ENABLED (2)
119 #define SLOT_STATE_DISABLED (3)
120 #define PWR_LED_STATE_SHIFT (2)
121 #define PWR_LED_STATE_MASK (3 << 2)
122 #define ATN_LED_STATE_SHIFT (4)
123 #define ATN_LED_STATE_MASK (3 << 4)
124 #define ATN_LED_STATE_ON (1)
125 #define ATN_LED_STATE_BLINK (2)
126 #define ATN_LED_STATE_OFF (3)
127 #define POWER_FAULT (1 << 6)
128 #define ATN_BUTTON (1 << 7)
129 #define MRL_SENSOR (1 << 8)
130 #define MHZ66_CAP (1 << 9)
131 #define PRSNT_SHIFT (10)
132 #define PRSNT_MASK (3 << 10)
133 #define PCIX_CAP_SHIFT (12)
134 #define PCIX_CAP_MASK_PI1 (3 << 12)
135 #define PCIX_CAP_MASK_PI2 (7 << 12)
136 #define PRSNT_CHANGE_DETECTED (1 << 16)
137 #define ISO_PFAULT_DETECTED (1 << 17)
138 #define BUTTON_PRESS_DETECTED (1 << 18)
139 #define MRL_CHANGE_DETECTED (1 << 19)
140 #define CON_PFAULT_DETECTED (1 << 20)
141 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
142 #define ISO_PFAULT_INTR_MASK (1 << 25)
143 #define BUTTON_PRESS_INTR_MASK (1 << 26)
144 #define MRL_CHANGE_INTR_MASK (1 << 27)
145 #define CON_PFAULT_INTR_MASK (1 << 28)
146 #define MRL_CHANGE_SERR_MASK (1 << 29)
147 #define CON_PFAULT_SERR_MASK (1 << 30)
148 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
149
150 /*
151 * SHPC Command Code definitnions
152 *
153 * Slot Operation 00h - 3Fh
154 * Set Bus Segment Speed/Mode A 40h - 47h
155 * Power-Only All Slots 48h
156 * Enable All Slots 49h
157 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
158 * Reserved Command Codes 60h - BFh
159 * Vendor Specific Commands C0h - FFh
160 */
161 #define SET_SLOT_PWR 0x01 /* Slot Operation */
162 #define SET_SLOT_ENABLE 0x02
163 #define SET_SLOT_DISABLE 0x03
164 #define SET_PWR_ON 0x04
165 #define SET_PWR_BLINK 0x08
166 #define SET_PWR_OFF 0x0c
167 #define SET_ATTN_ON 0x10
168 #define SET_ATTN_BLINK 0x20
169 #define SET_ATTN_OFF 0x30
170 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
171 #define SETA_PCI_66MHZ 0x41
172 #define SETA_PCIX_66MHZ 0x42
173 #define SETA_PCIX_100MHZ 0x43
174 #define SETA_PCIX_133MHZ 0x44
175 #define SETA_RESERVED1 0x45
176 #define SETA_RESERVED2 0x46
177 #define SETA_RESERVED3 0x47
178 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
179 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
180 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
181 #define SETB_PCI_66MHZ 0x51
182 #define SETB_PCIX_66MHZ_PM 0x52
183 #define SETB_PCIX_100MHZ_PM 0x53
184 #define SETB_PCIX_133MHZ_PM 0x54
185 #define SETB_PCIX_66MHZ_EM 0x55
186 #define SETB_PCIX_100MHZ_EM 0x56
187 #define SETB_PCIX_133MHZ_EM 0x57
188 #define SETB_PCIX_66MHZ_266 0x58
189 #define SETB_PCIX_100MHZ_266 0x59
190 #define SETB_PCIX_133MHZ_266 0x5a
191 #define SETB_PCIX_66MHZ_533 0x5b
192 #define SETB_PCIX_100MHZ_533 0x5c
193 #define SETB_PCIX_133MHZ_533 0x5d
194 #define SETB_RESERVED1 0x5e
195 #define SETB_RESERVED2 0x5f
196
197 /*
198 * SHPC controller command error code
199 */
200 #define SWITCH_OPEN 0x1
201 #define INVALID_CMD 0x2
202 #define INVALID_SPEED_MODE 0x4
203
204 /*
205 * For accessing SHPC Working Register Set via PCI Configuration Space
206 */
207 #define DWORD_SELECT 0x2
208 #define DWORD_DATA 0x4
209
210 /* Field Offset in Logical Slot Register - byte boundary */
211 #define SLOT_EVENT_LATCH 0x2
212 #define SLOT_SERR_INT_MASK 0x3
213
214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
215 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
216 static int ctlr_seq_num = 0; /* Controller sequenc # */
217 static spinlock_t list_lock;
218
219 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
220
221 static irqreturn_t shpc_isr(int irq, void *dev_id);
222 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec);
223 static int hpc_check_cmd_status(struct controller *ctrl);
224
225 static inline u8 shpc_readb(struct controller *ctrl, int reg)
226 {
227 return readb(ctrl->hpc_ctlr_handle->creg + reg);
228 }
229
230 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
231 {
232 writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
233 }
234
235 static inline u16 shpc_readw(struct controller *ctrl, int reg)
236 {
237 return readw(ctrl->hpc_ctlr_handle->creg + reg);
238 }
239
240 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
241 {
242 writew(val, ctrl->hpc_ctlr_handle->creg + reg);
243 }
244
245 static inline u32 shpc_readl(struct controller *ctrl, int reg)
246 {
247 return readl(ctrl->hpc_ctlr_handle->creg + reg);
248 }
249
250 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
251 {
252 writel(val, ctrl->hpc_ctlr_handle->creg + reg);
253 }
254
255 static inline int shpc_indirect_read(struct controller *ctrl, int index,
256 u32 *value)
257 {
258 int rc;
259 u32 cap_offset = ctrl->cap_offset;
260 struct pci_dev *pdev = ctrl->pci_dev;
261
262 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
263 if (rc)
264 return rc;
265 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
266 }
267
268 /*
269 * This is the interrupt polling timeout function.
270 */
271 static void int_poll_timeout(unsigned long lphp_ctlr)
272 {
273 struct php_ctlr_state_s *php_ctlr =
274 (struct php_ctlr_state_s *)lphp_ctlr;
275
276 DBG_ENTER_ROUTINE
277
278 /* Poll for interrupt events. regs == NULL => polling */
279 shpc_isr(0, php_ctlr->callback_instance_id);
280
281 init_timer(&php_ctlr->int_poll_timer);
282 if (!shpchp_poll_time)
283 shpchp_poll_time = 2; /* default polling interval is 2 sec */
284
285 start_int_poll_timer(php_ctlr, shpchp_poll_time);
286
287 DBG_LEAVE_ROUTINE
288 }
289
290 /*
291 * This function starts the interrupt polling timer.
292 */
293 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec)
294 {
295 /* Clamp to sane value */
296 if ((sec <= 0) || (sec > 60))
297 sec = 2;
298
299 php_ctlr->int_poll_timer.function = &int_poll_timeout;
300 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;
301 php_ctlr->int_poll_timer.expires = jiffies + sec * HZ;
302 add_timer(&php_ctlr->int_poll_timer);
303 }
304
305 static inline int is_ctrl_busy(struct controller *ctrl)
306 {
307 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
308 return cmd_status & 0x1;
309 }
310
311 /*
312 * Returns 1 if SHPC finishes executing a command within 1 sec,
313 * otherwise returns 0.
314 */
315 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
316 {
317 int i;
318
319 if (!is_ctrl_busy(ctrl))
320 return 1;
321
322 /* Check every 0.1 sec for a total of 1 sec */
323 for (i = 0; i < 10; i++) {
324 msleep(100);
325 if (!is_ctrl_busy(ctrl))
326 return 1;
327 }
328
329 return 0;
330 }
331
332 static inline int shpc_wait_cmd(struct controller *ctrl)
333 {
334 int retval = 0;
335 unsigned long timeout = msecs_to_jiffies(1000);
336 int rc;
337
338 if (shpchp_poll_mode)
339 rc = shpc_poll_ctrl_busy(ctrl);
340 else
341 rc = wait_event_interruptible_timeout(ctrl->queue,
342 !is_ctrl_busy(ctrl), timeout);
343 if (!rc && is_ctrl_busy(ctrl)) {
344 retval = -EIO;
345 err("Command not completed in 1000 msec\n");
346 } else if (rc < 0) {
347 retval = -EINTR;
348 info("Command was interrupted by a signal\n");
349 }
350
351 return retval;
352 }
353
354 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
355 {
356 struct controller *ctrl = slot->ctrl;
357 u16 cmd_status;
358 int retval = 0;
359 u16 temp_word;
360
361 DBG_ENTER_ROUTINE
362
363 mutex_lock(&slot->ctrl->cmd_lock);
364
365 if (!shpc_poll_ctrl_busy(ctrl)) {
366 /* After 1 sec and and the controller is still busy */
367 err("%s : Controller is still busy after 1 sec.\n",
368 __FUNCTION__);
369 retval = -EBUSY;
370 goto out;
371 }
372
373 ++t_slot;
374 temp_word = (t_slot << 8) | (cmd & 0xFF);
375 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
376
377 /* To make sure the Controller Busy bit is 0 before we send out the
378 * command.
379 */
380 shpc_writew(ctrl, CMD, temp_word);
381
382 /*
383 * Wait for command completion.
384 */
385 retval = shpc_wait_cmd(slot->ctrl);
386 if (retval)
387 goto out;
388
389 cmd_status = hpc_check_cmd_status(slot->ctrl);
390 if (cmd_status) {
391 err("%s: Failed to issued command 0x%x (error code = %d)\n",
392 __FUNCTION__, cmd, cmd_status);
393 retval = -EIO;
394 }
395 out:
396 mutex_unlock(&slot->ctrl->cmd_lock);
397
398 DBG_LEAVE_ROUTINE
399 return retval;
400 }
401
402 static int hpc_check_cmd_status(struct controller *ctrl)
403 {
404 u16 cmd_status;
405 int retval = 0;
406
407 DBG_ENTER_ROUTINE
408
409 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
410
411 switch (cmd_status >> 1) {
412 case 0:
413 retval = 0;
414 break;
415 case 1:
416 retval = SWITCH_OPEN;
417 err("%s: Switch opened!\n", __FUNCTION__);
418 break;
419 case 2:
420 retval = INVALID_CMD;
421 err("%s: Invalid HPC command!\n", __FUNCTION__);
422 break;
423 case 4:
424 retval = INVALID_SPEED_MODE;
425 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
426 break;
427 default:
428 retval = cmd_status;
429 }
430
431 DBG_LEAVE_ROUTINE
432 return retval;
433 }
434
435
436 static int hpc_get_attention_status(struct slot *slot, u8 *status)
437 {
438 struct controller *ctrl = slot->ctrl;
439 u32 slot_reg;
440 u8 state;
441
442 DBG_ENTER_ROUTINE
443
444 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
445 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
446
447 switch (state) {
448 case ATN_LED_STATE_ON:
449 *status = 1; /* On */
450 break;
451 case ATN_LED_STATE_BLINK:
452 *status = 2; /* Blink */
453 break;
454 case ATN_LED_STATE_OFF:
455 *status = 0; /* Off */
456 break;
457 default:
458 *status = 0xFF; /* Reserved */
459 break;
460 }
461
462 DBG_LEAVE_ROUTINE
463 return 0;
464 }
465
466 static int hpc_get_power_status(struct slot * slot, u8 *status)
467 {
468 struct controller *ctrl = slot->ctrl;
469 u32 slot_reg;
470 u8 state;
471
472 DBG_ENTER_ROUTINE
473
474 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
475 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
476
477 switch (state) {
478 case SLOT_STATE_PWRONLY:
479 *status = 2; /* Powered only */
480 break;
481 case SLOT_STATE_ENABLED:
482 *status = 1; /* Enabled */
483 break;
484 case SLOT_STATE_DISABLED:
485 *status = 0; /* Disabled */
486 break;
487 default:
488 *status = 0xFF; /* Reserved */
489 break;
490 }
491
492 DBG_LEAVE_ROUTINE
493 return 0;
494 }
495
496
497 static int hpc_get_latch_status(struct slot *slot, u8 *status)
498 {
499 struct controller *ctrl = slot->ctrl;
500 u32 slot_reg;
501
502 DBG_ENTER_ROUTINE
503
504 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
505 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
506
507 DBG_LEAVE_ROUTINE
508 return 0;
509 }
510
511 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
512 {
513 struct controller *ctrl = slot->ctrl;
514 u32 slot_reg;
515 u8 state;
516
517 DBG_ENTER_ROUTINE
518
519 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
520 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
521 *status = (state != 0x3) ? 1 : 0;
522
523 DBG_LEAVE_ROUTINE
524 return 0;
525 }
526
527 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
528 {
529 struct controller *ctrl = slot->ctrl;
530
531 DBG_ENTER_ROUTINE
532
533 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
534
535 DBG_LEAVE_ROUTINE
536 return 0;
537 }
538
539 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
540 {
541 int retval = 0;
542 struct controller *ctrl = slot->ctrl;
543 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
544 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
545 u8 pi, pcix_cap;
546
547 DBG_ENTER_ROUTINE
548
549 if ((retval = hpc_get_prog_int(slot, &pi)))
550 return retval;
551
552 switch (pi) {
553 case 1:
554 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
555 break;
556 case 2:
557 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
558 break;
559 default:
560 return -ENODEV;
561 }
562
563 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
564 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
565
566 switch (pcix_cap) {
567 case 0x0:
568 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
569 break;
570 case 0x1:
571 *value = PCI_SPEED_66MHz_PCIX;
572 break;
573 case 0x3:
574 *value = PCI_SPEED_133MHz_PCIX;
575 break;
576 case 0x4:
577 *value = PCI_SPEED_133MHz_PCIX_266;
578 break;
579 case 0x5:
580 *value = PCI_SPEED_133MHz_PCIX_533;
581 break;
582 case 0x2:
583 default:
584 *value = PCI_SPEED_UNKNOWN;
585 retval = -ENODEV;
586 break;
587 }
588
589 dbg("Adapter speed = %d\n", *value);
590 DBG_LEAVE_ROUTINE
591 return retval;
592 }
593
594 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
595 {
596 struct controller *ctrl = slot->ctrl;
597 u16 sec_bus_status;
598 u8 pi;
599 int retval = 0;
600
601 DBG_ENTER_ROUTINE
602
603 pi = shpc_readb(ctrl, PROG_INTERFACE);
604 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
605
606 if (pi == 2) {
607 *mode = (sec_bus_status & 0x0100) >> 8;
608 } else {
609 retval = -1;
610 }
611
612 dbg("Mode 1 ECC cap = %d\n", *mode);
613
614 DBG_LEAVE_ROUTINE
615 return retval;
616 }
617
618 static int hpc_query_power_fault(struct slot * slot)
619 {
620 struct controller *ctrl = slot->ctrl;
621 u32 slot_reg;
622
623 DBG_ENTER_ROUTINE
624
625 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
626
627 DBG_LEAVE_ROUTINE
628 /* Note: Logic 0 => fault */
629 return !(slot_reg & POWER_FAULT);
630 }
631
632 static int hpc_set_attention_status(struct slot *slot, u8 value)
633 {
634 u8 slot_cmd = 0;
635
636 switch (value) {
637 case 0 :
638 slot_cmd = SET_ATTN_OFF; /* OFF */
639 break;
640 case 1:
641 slot_cmd = SET_ATTN_ON; /* ON */
642 break;
643 case 2:
644 slot_cmd = SET_ATTN_BLINK; /* BLINK */
645 break;
646 default:
647 return -1;
648 }
649
650 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
651 }
652
653
654 static void hpc_set_green_led_on(struct slot *slot)
655 {
656 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
657 }
658
659 static void hpc_set_green_led_off(struct slot *slot)
660 {
661 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
662 }
663
664 static void hpc_set_green_led_blink(struct slot *slot)
665 {
666 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
667 }
668
669 int shpc_get_ctlr_slot_config(struct controller *ctrl,
670 int *num_ctlr_slots, /* number of slots in this HPC */
671 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
672 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
673 int *updown, /* physical_slot_num increament: 1 or -1 */
674 int *flags)
675 {
676 u32 slot_config;
677
678 DBG_ENTER_ROUTINE
679
680 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
681 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
682 *num_ctlr_slots = slot_config & SLOT_NUM;
683 *physical_slot_num = (slot_config & PSN) >> 16;
684 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
685
686 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
687
688 DBG_LEAVE_ROUTINE
689 return 0;
690 }
691
692 static void hpc_release_ctlr(struct controller *ctrl)
693 {
694 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
695 struct php_ctlr_state_s *p, *p_prev;
696 int i;
697 u32 slot_reg, serr_int;
698
699 DBG_ENTER_ROUTINE
700
701 /*
702 * Mask event interrupts and SERRs of all slots
703 */
704 for (i = 0; i < ctrl->num_slots; i++) {
705 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
706 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
707 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
708 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
709 CON_PFAULT_SERR_MASK);
710 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
711 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
712 }
713
714 cleanup_slots(ctrl);
715
716 /*
717 * Mask SERR and System Interrut generation
718 */
719 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
720 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
721 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
722 serr_int &= ~SERR_INTR_RSVDZ_MASK;
723 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
724
725 if (shpchp_poll_mode) {
726 del_timer(&php_ctlr->int_poll_timer);
727 } else {
728 if (php_ctlr->irq) {
729 free_irq(php_ctlr->irq, ctrl);
730 php_ctlr->irq = 0;
731 pci_disable_msi(php_ctlr->pci_dev);
732 }
733 }
734
735 if (php_ctlr->pci_dev) {
736 iounmap(php_ctlr->creg);
737 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
738 php_ctlr->pci_dev = NULL;
739 }
740
741 spin_lock(&list_lock);
742 p = php_ctlr_list_head;
743 p_prev = NULL;
744 while (p) {
745 if (p == php_ctlr) {
746 if (p_prev)
747 p_prev->pnext = p->pnext;
748 else
749 php_ctlr_list_head = p->pnext;
750 break;
751 } else {
752 p_prev = p;
753 p = p->pnext;
754 }
755 }
756 spin_unlock(&list_lock);
757
758 kfree(php_ctlr);
759
760 /*
761 * If this is the last controller to be released, destroy the
762 * shpchpd work queue
763 */
764 if (atomic_dec_and_test(&shpchp_num_controllers))
765 destroy_workqueue(shpchp_wq);
766
767 DBG_LEAVE_ROUTINE
768
769 }
770
771 static int hpc_power_on_slot(struct slot * slot)
772 {
773 int retval;
774
775 DBG_ENTER_ROUTINE
776
777 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
778 if (retval) {
779 err("%s: Write command failed!\n", __FUNCTION__);
780 return retval;
781 }
782
783 DBG_LEAVE_ROUTINE
784
785 return 0;
786 }
787
788 static int hpc_slot_enable(struct slot * slot)
789 {
790 int retval;
791
792 DBG_ENTER_ROUTINE
793
794 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
795 retval = shpc_write_cmd(slot, slot->hp_slot,
796 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
797 if (retval) {
798 err("%s: Write command failed!\n", __FUNCTION__);
799 return retval;
800 }
801
802 DBG_LEAVE_ROUTINE
803 return 0;
804 }
805
806 static int hpc_slot_disable(struct slot * slot)
807 {
808 int retval;
809
810 DBG_ENTER_ROUTINE
811
812 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
813 retval = shpc_write_cmd(slot, slot->hp_slot,
814 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
815 if (retval) {
816 err("%s: Write command failed!\n", __FUNCTION__);
817 return retval;
818 }
819
820 DBG_LEAVE_ROUTINE
821 return 0;
822 }
823
824 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
825 {
826 int retval;
827 struct controller *ctrl = slot->ctrl;
828 u8 pi, cmd;
829
830 DBG_ENTER_ROUTINE
831
832 pi = shpc_readb(ctrl, PROG_INTERFACE);
833 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
834 return -EINVAL;
835
836 switch (value) {
837 case PCI_SPEED_33MHz:
838 cmd = SETA_PCI_33MHZ;
839 break;
840 case PCI_SPEED_66MHz:
841 cmd = SETA_PCI_66MHZ;
842 break;
843 case PCI_SPEED_66MHz_PCIX:
844 cmd = SETA_PCIX_66MHZ;
845 break;
846 case PCI_SPEED_100MHz_PCIX:
847 cmd = SETA_PCIX_100MHZ;
848 break;
849 case PCI_SPEED_133MHz_PCIX:
850 cmd = SETA_PCIX_133MHZ;
851 break;
852 case PCI_SPEED_66MHz_PCIX_ECC:
853 cmd = SETB_PCIX_66MHZ_EM;
854 break;
855 case PCI_SPEED_100MHz_PCIX_ECC:
856 cmd = SETB_PCIX_100MHZ_EM;
857 break;
858 case PCI_SPEED_133MHz_PCIX_ECC:
859 cmd = SETB_PCIX_133MHZ_EM;
860 break;
861 case PCI_SPEED_66MHz_PCIX_266:
862 cmd = SETB_PCIX_66MHZ_266;
863 break;
864 case PCI_SPEED_100MHz_PCIX_266:
865 cmd = SETB_PCIX_100MHZ_266;
866 break;
867 case PCI_SPEED_133MHz_PCIX_266:
868 cmd = SETB_PCIX_133MHZ_266;
869 break;
870 case PCI_SPEED_66MHz_PCIX_533:
871 cmd = SETB_PCIX_66MHZ_533;
872 break;
873 case PCI_SPEED_100MHz_PCIX_533:
874 cmd = SETB_PCIX_100MHZ_533;
875 break;
876 case PCI_SPEED_133MHz_PCIX_533:
877 cmd = SETB_PCIX_133MHZ_533;
878 break;
879 default:
880 return -EINVAL;
881 }
882
883 retval = shpc_write_cmd(slot, 0, cmd);
884 if (retval)
885 err("%s: Write command failed!\n", __FUNCTION__);
886
887 DBG_LEAVE_ROUTINE
888 return retval;
889 }
890
891 static irqreturn_t shpc_isr(int irq, void *dev_id)
892 {
893 struct controller *ctrl = (struct controller *)dev_id;
894 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
895 u32 serr_int, slot_reg, intr_loc, intr_loc2;
896 int hp_slot;
897
898 /* Check to see if it was our interrupt */
899 intr_loc = shpc_readl(ctrl, INTR_LOC);
900 if (!intr_loc)
901 return IRQ_NONE;
902
903 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
904
905 if(!shpchp_poll_mode) {
906 /*
907 * Mask Global Interrupt Mask - see implementation
908 * note on p. 139 of SHPC spec rev 1.0
909 */
910 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
911 serr_int |= GLOBAL_INTR_MASK;
912 serr_int &= ~SERR_INTR_RSVDZ_MASK;
913 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
914
915 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
916 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
917 }
918
919 if (intr_loc & CMD_INTR_PENDING) {
920 /*
921 * Command Complete Interrupt Pending
922 * RO only - clear by writing 1 to the Command Completion
923 * Detect bit in Controller SERR-INT register
924 */
925 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
926 serr_int &= ~SERR_INTR_RSVDZ_MASK;
927 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
928
929 wake_up_interruptible(&ctrl->queue);
930 }
931
932 if (!(intr_loc & ~CMD_INTR_PENDING))
933 goto out;
934
935 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
936 /* To find out which slot has interrupt pending */
937 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
938 continue;
939
940 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
941 dbg("%s: Slot %x with intr, slot register = %x\n",
942 __FUNCTION__, hp_slot, slot_reg);
943
944 if (slot_reg & MRL_CHANGE_DETECTED)
945 php_ctlr->switch_change_callback(
946 hp_slot, php_ctlr->callback_instance_id);
947
948 if (slot_reg & BUTTON_PRESS_DETECTED)
949 php_ctlr->attention_button_callback(
950 hp_slot, php_ctlr->callback_instance_id);
951
952 if (slot_reg & PRSNT_CHANGE_DETECTED)
953 php_ctlr->presence_change_callback(
954 hp_slot , php_ctlr->callback_instance_id);
955
956 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
957 php_ctlr->power_fault_callback(
958 hp_slot, php_ctlr->callback_instance_id);
959
960 /* Clear all slot events */
961 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
962 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
963 }
964 out:
965 if (!shpchp_poll_mode) {
966 /* Unmask Global Interrupt Mask */
967 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
968 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
969 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
970 }
971
972 return IRQ_HANDLED;
973 }
974
975 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
976 {
977 int retval = 0;
978 struct controller *ctrl = slot->ctrl;
979 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
980 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
981 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
982 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
983
984 DBG_ENTER_ROUTINE
985
986 if (pi == 2) {
987 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
988 bus_speed = PCI_SPEED_133MHz_PCIX_533;
989 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
990 bus_speed = PCI_SPEED_100MHz_PCIX_533;
991 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
992 bus_speed = PCI_SPEED_66MHz_PCIX_533;
993 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
994 bus_speed = PCI_SPEED_133MHz_PCIX_266;
995 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
996 bus_speed = PCI_SPEED_100MHz_PCIX_266;
997 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
998 bus_speed = PCI_SPEED_66MHz_PCIX_266;
999 }
1000
1001 if (bus_speed == PCI_SPEED_UNKNOWN) {
1002 if (slot_avail1 & SLOT_133MHZ_PCIX)
1003 bus_speed = PCI_SPEED_133MHz_PCIX;
1004 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1005 bus_speed = PCI_SPEED_100MHz_PCIX;
1006 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1007 bus_speed = PCI_SPEED_66MHz_PCIX;
1008 else if (slot_avail2 & SLOT_66MHZ)
1009 bus_speed = PCI_SPEED_66MHz;
1010 else if (slot_avail1 & SLOT_33MHZ)
1011 bus_speed = PCI_SPEED_33MHz;
1012 else
1013 retval = -ENODEV;
1014 }
1015
1016 *value = bus_speed;
1017 dbg("Max bus speed = %d\n", bus_speed);
1018 DBG_LEAVE_ROUTINE
1019 return retval;
1020 }
1021
1022 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1023 {
1024 int retval = 0;
1025 struct controller *ctrl = slot->ctrl;
1026 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1027 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
1028 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1029 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1030
1031 DBG_ENTER_ROUTINE
1032
1033 if ((pi == 1) && (speed_mode > 4)) {
1034 *value = PCI_SPEED_UNKNOWN;
1035 return -ENODEV;
1036 }
1037
1038 switch (speed_mode) {
1039 case 0x0:
1040 *value = PCI_SPEED_33MHz;
1041 break;
1042 case 0x1:
1043 *value = PCI_SPEED_66MHz;
1044 break;
1045 case 0x2:
1046 *value = PCI_SPEED_66MHz_PCIX;
1047 break;
1048 case 0x3:
1049 *value = PCI_SPEED_100MHz_PCIX;
1050 break;
1051 case 0x4:
1052 *value = PCI_SPEED_133MHz_PCIX;
1053 break;
1054 case 0x5:
1055 *value = PCI_SPEED_66MHz_PCIX_ECC;
1056 break;
1057 case 0x6:
1058 *value = PCI_SPEED_100MHz_PCIX_ECC;
1059 break;
1060 case 0x7:
1061 *value = PCI_SPEED_133MHz_PCIX_ECC;
1062 break;
1063 case 0x8:
1064 *value = PCI_SPEED_66MHz_PCIX_266;
1065 break;
1066 case 0x9:
1067 *value = PCI_SPEED_100MHz_PCIX_266;
1068 break;
1069 case 0xa:
1070 *value = PCI_SPEED_133MHz_PCIX_266;
1071 break;
1072 case 0xb:
1073 *value = PCI_SPEED_66MHz_PCIX_533;
1074 break;
1075 case 0xc:
1076 *value = PCI_SPEED_100MHz_PCIX_533;
1077 break;
1078 case 0xd:
1079 *value = PCI_SPEED_133MHz_PCIX_533;
1080 break;
1081 default:
1082 *value = PCI_SPEED_UNKNOWN;
1083 retval = -ENODEV;
1084 break;
1085 }
1086
1087 dbg("Current bus speed = %d\n", bus_speed);
1088 DBG_LEAVE_ROUTINE
1089 return retval;
1090 }
1091
1092 static struct hpc_ops shpchp_hpc_ops = {
1093 .power_on_slot = hpc_power_on_slot,
1094 .slot_enable = hpc_slot_enable,
1095 .slot_disable = hpc_slot_disable,
1096 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1097 .set_attention_status = hpc_set_attention_status,
1098 .get_power_status = hpc_get_power_status,
1099 .get_attention_status = hpc_get_attention_status,
1100 .get_latch_status = hpc_get_latch_status,
1101 .get_adapter_status = hpc_get_adapter_status,
1102
1103 .get_max_bus_speed = hpc_get_max_bus_speed,
1104 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1105 .get_adapter_speed = hpc_get_adapter_speed,
1106 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1107 .get_prog_int = hpc_get_prog_int,
1108
1109 .query_power_fault = hpc_query_power_fault,
1110 .green_led_on = hpc_set_green_led_on,
1111 .green_led_off = hpc_set_green_led_off,
1112 .green_led_blink = hpc_set_green_led_blink,
1113
1114 .release_ctlr = hpc_release_ctlr,
1115 };
1116
1117 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1118 {
1119 struct php_ctlr_state_s *php_ctlr, *p;
1120 void *instance_id = ctrl;
1121 int rc = -1, num_slots = 0;
1122 u8 hp_slot;
1123 u32 shpc_base_offset;
1124 u32 tempdword, slot_reg, slot_config;
1125 u8 i;
1126
1127 DBG_ENTER_ROUTINE
1128
1129 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1130
1131 spin_lock_init(&list_lock);
1132 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
1133
1134 if (!php_ctlr) { /* allocate controller state data */
1135 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1136 goto abort;
1137 }
1138
1139 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1140
1141 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1142 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1143 /* amd shpc driver doesn't use Base Offset; assume 0 */
1144 ctrl->mmio_base = pci_resource_start(pdev, 0);
1145 ctrl->mmio_size = pci_resource_len(pdev, 0);
1146 } else {
1147 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1148 if (!ctrl->cap_offset) {
1149 err("%s : cap_offset == 0\n", __FUNCTION__);
1150 goto abort_free_ctlr;
1151 }
1152 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1153
1154 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1155 if (rc) {
1156 err("%s: cannot read base_offset\n", __FUNCTION__);
1157 goto abort_free_ctlr;
1158 }
1159
1160 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1161 if (rc) {
1162 err("%s: cannot read slot config\n", __FUNCTION__);
1163 goto abort_free_ctlr;
1164 }
1165 num_slots = tempdword & SLOT_NUM;
1166 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1167
1168 for (i = 0; i < 9 + num_slots; i++) {
1169 rc = shpc_indirect_read(ctrl, i, &tempdword);
1170 if (rc) {
1171 err("%s: cannot read creg (index = %d)\n",
1172 __FUNCTION__, i);
1173 goto abort_free_ctlr;
1174 }
1175 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1176 tempdword);
1177 }
1178
1179 ctrl->mmio_base =
1180 pci_resource_start(pdev, 0) + shpc_base_offset;
1181 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1182 }
1183
1184 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1185 pdev->subsystem_device);
1186
1187 rc = pci_enable_device(pdev);
1188 if (rc) {
1189 err("%s: pci_enable_device failed\n", __FUNCTION__);
1190 goto abort_free_ctlr;
1191 }
1192
1193 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1194 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1195 rc = -1;
1196 goto abort_free_ctlr;
1197 }
1198
1199 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1200 if (!php_ctlr->creg) {
1201 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1202 ctrl->mmio_size, ctrl->mmio_base);
1203 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1204 rc = -1;
1205 goto abort_free_ctlr;
1206 }
1207 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1208
1209 mutex_init(&ctrl->crit_sect);
1210 mutex_init(&ctrl->cmd_lock);
1211
1212 /* Setup wait queue */
1213 init_waitqueue_head(&ctrl->queue);
1214
1215 /* Find the IRQ */
1216 php_ctlr->irq = pdev->irq;
1217 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1218 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1219 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1220 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1221 php_ctlr->callback_instance_id = instance_id;
1222
1223 ctrl->hpc_ctlr_handle = php_ctlr;
1224 ctrl->hpc_ops = &shpchp_hpc_ops;
1225
1226 /* Return PCI Controller Info */
1227 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1228 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1229 php_ctlr->num_slots = slot_config & SLOT_NUM;
1230 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1231 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1232
1233 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1234 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1235 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1236 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1237 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1238 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1239 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1240 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1241 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1242
1243 /* Mask the MRL sensor SERR Mask of individual slot in
1244 * Slot SERR-INT Mask & clear all the existing event if any
1245 */
1246 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1247 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1248 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1249 hp_slot, slot_reg);
1250 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1251 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1252 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1253 CON_PFAULT_SERR_MASK);
1254 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1255 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1256 }
1257
1258 if (shpchp_poll_mode) {/* Install interrupt polling code */
1259 /* Install and start the interrupt polling timer */
1260 init_timer(&php_ctlr->int_poll_timer);
1261 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1262 } else {
1263 /* Installs the interrupt handler */
1264 rc = pci_enable_msi(pdev);
1265 if (rc) {
1266 info("Can't get msi for the hotplug controller\n");
1267 info("Use INTx for the hotplug controller\n");
1268 } else
1269 php_ctlr->irq = pdev->irq;
1270
1271 rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl);
1272 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1273 if (rc) {
1274 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1275 goto abort_free_ctlr;
1276 }
1277 }
1278 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1279 pdev->bus->number, PCI_SLOT(pdev->devfn),
1280 PCI_FUNC(pdev->devfn), pdev->irq);
1281 get_hp_hw_control_from_firmware(pdev);
1282
1283 /* Add this HPC instance into the HPC list */
1284 spin_lock(&list_lock);
1285 if (php_ctlr_list_head == 0) {
1286 php_ctlr_list_head = php_ctlr;
1287 p = php_ctlr_list_head;
1288 p->pnext = NULL;
1289 } else {
1290 p = php_ctlr_list_head;
1291
1292 while (p->pnext)
1293 p = p->pnext;
1294
1295 p->pnext = php_ctlr;
1296 }
1297 spin_unlock(&list_lock);
1298
1299 ctlr_seq_num++;
1300
1301 /*
1302 * If this is the first controller to be initialized,
1303 * initialize the shpchpd work queue
1304 */
1305 if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1306 shpchp_wq = create_singlethread_workqueue("shpchpd");
1307 if (!shpchp_wq) {
1308 rc = -ENOMEM;
1309 goto abort_free_ctlr;
1310 }
1311 }
1312
1313 /*
1314 * Unmask all event interrupts of all slots
1315 */
1316 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1317 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1318 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1319 hp_slot, slot_reg);
1320 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1321 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1322 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1323 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1324 }
1325 if (!shpchp_poll_mode) {
1326 /* Unmask all general input interrupts and SERR */
1327 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1328 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1329 SERR_INTR_RSVDZ_MASK);
1330 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1331 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1332 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1333 }
1334
1335 DBG_LEAVE_ROUTINE
1336 return 0;
1337
1338 /* We end up here for the many possible ways to fail this API. */
1339 abort_free_ctlr:
1340 if (php_ctlr->creg)
1341 iounmap(php_ctlr->creg);
1342 kfree(php_ctlr);
1343 abort:
1344 DBG_LEAVE_ROUTINE
1345 return rc;
1346 }
hh.org GIT migration