| blob | f0f9eab4c08ee519843fe21c31aa8d6feac08e76 |
1 /*
2 * System-on-Chip (SoC) driver for MediaQ 1100/1132 chips.
3 *
4 * Copyright (C) 2003 Andrew Zabolotny <anpaza@mail.ru>
5 * Portions copyright (C) 2003 Keith Packard
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
12 #include <linux/module.h>
13 #include <linux/version.h>
14 #include <linux/config.h>
15 #include <linux/platform_device.h>
16 #include <linux/soc-old.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/spinlock.h>
21 #include <asm/io.h>
23 #include "mq11xx.h"
25 #ifdef MQ_IRQ_MULTIPLEX
26 # include <asm/irq.h>
27 # include <asm/mach/irq.h>
28 #endif
30 #if 0
31 # define debug(s, args...) printk (KERN_INFO s, ##args)
32 #else
33 # define debug(s, args...)
34 #endif
35 #define debug_func(s, args...) debug ("%s: " s, __FUNCTION__, ##args)
37 /* Bitmasks for distinguishing resources for different sets of MediaQ chips */
38 #define MQ_MASK_1100 (1 << CHIP_MEDIAQ_1100)
39 #define MQ_MASK_1132 (1 << CHIP_MEDIAQ_1132)
40 #define MQ_MASK_1168 (1 << CHIP_MEDIAQ_1168)
41 #define MQ_MASK_1178 (1 << CHIP_MEDIAQ_1178)
42 #define MQ_MASK_1188 (1 << CHIP_MEDIAQ_1188)
43 #define MQ_MASK_ALL (MQ_MASK_1100 | MQ_MASK_1132 | MQ_MASK_1168 | \
44 MQ_MASK_1178 | MQ_MASK_1188)
46 struct mq_block
47 {
48 platform_device_id id;
49 const char *name;
50 unsigned start, end;
51 unsigned mask;
52 };
54 #define MQ_SUBDEVS_COUNT ARRAY_SIZE(mq_blocks)
55 #define MQ_SUBDEVS_REAL_COUNT (MQ_SUBDEVS_COUNT - 2)
56 static const struct mq_block mq_blocks[] = {
57 {
58 /* Graphics Controller */
59 { MEDIAQ_11XX_FB_DEVICE_ID },
60 "mq11xx_fb",
61 0x100, 0x17f,
62 MQ_MASK_ALL
63 },
64 {
65 /* Graphics Engine -- tied to framebuffer subdevice */
66 { MEDIAQ_11XX_FB_DEVICE_ID },
67 NULL,
68 0x200, 0x27f,
69 MQ_MASK_ALL
70 },
71 {
72 /* Palette Registers -- tied to framebuffer subdevice */
73 { MEDIAQ_11XX_FB_DEVICE_ID },
74 NULL,
75 0x800, 0xbff,
76 MQ_MASK_ALL
77 },
78 {
79 /* Flat Panel control interface */
80 { MEDIAQ_11XX_FP_DEVICE_ID },
81 "mq11xx_lcd",
82 0x600, 0x7ff,
83 MQ_MASK_ALL
84 },
85 {
86 /* USB Function subdevice */
87 { MEDIAQ_11XX_UDC_DEVICE_ID },
88 "mq11xx_udc",
89 0x1000, 0x107f,
90 MQ_MASK_ALL
91 },
92 {
93 /* USB Host subdevice */
94 { MEDIAQ_11XX_UHC_DEVICE_ID },
95 "mq11xx_uhc",
96 0x500, 0x5ff,
97 MQ_MASK_1132 | MQ_MASK_1188
98 },
99 {
100 /* Serial Port Interface */
101 { MEDIAQ_11XX_SPI_DEVICE_ID },
102 "mq11xx_spi",
103 0x300, 0x37f,
104 MQ_MASK_1132
105 },
106 {
107 /* Synchronous Serial Channel (I2S) */
108 { MEDIAQ_11XX_I2S_DEVICE_ID },
109 "mq11xx_i2s",
110 0x280, 0x2ff,
111 MQ_MASK_1132
112 },
113 };
115 static struct {
116 int id;
117 int chip;
118 const char *name;
119 } mq_device_id [] =
120 {
121 { MQ_PCI_DEVICEID_1100, CHIP_MEDIAQ_1100, "1100" },
122 { MQ_PCI_DEVICEID_1132, CHIP_MEDIAQ_1132, "1132" },
123 { MQ_PCI_DEVICEID_1168, CHIP_MEDIAQ_1168, "1168" },
124 { MQ_PCI_DEVICEID_1178, CHIP_MEDIAQ_1178, "1178" },
125 { MQ_PCI_DEVICEID_1188, CHIP_MEDIAQ_1188, "1188" }
126 };
128 /* Keep free block list no less than this value (minimal slab is 32 bytes) */
129 #define MEMBLOCK_MINCOUNT (32 / sizeof (struct mq_freemem_list))
130 /* Align MediaQ memory blocks by this amount (MediaQ DMA limitation) */
131 #define MEMBLOCK_ALIGN 64
133 struct mq_freemem_list {
134 u32 addr;
135 u32 size;
136 } __attribute__((packed));
138 struct mq_data
139 {
140 /* The exported parameters */
141 struct mediaq11xx_base base;
142 /* MediaQ initialization register data */
143 struct mediaq11xx_init_data *mq_init;
144 /* Number of subdevices */
145 int ndevices;
146 /* The list of subdevices */
147 struct platform_device *devices;
148 /* MediaQ interrupt number */
149 int irq_nr;
150 /* Count the number of poweron requests to every subdevice */
151 u8 power_on [MQ_SUBDEVS_REAL_COUNT];
152 /* Number of free block descriptors */
153 int nfreeblocks, maxfreeblocks;
154 /* The list of free blocks */
155 struct mq_freemem_list *freelist;
156 /* The lock on the free blocks list */
157 spinlock_t mem_lock;
158 /* The amount of RAM at the beginning of address space that
159 is not accessible through the unsynced window */
160 int unsynced_ram_skip;
161 };
163 /* Pointer to initialized devices.
164 * This is a bad practice, but if you don't need too much from the
165 * MediaQ device (such as turning on/off a couple of GPIOs) you can
166 * use the mq_get_device (int index) to get a pointer to one of
167 * available MediaQ device structures.
168 */
169 #define MAX_MQ11XX_DEVICES 8
170 static struct mediaq11xx_base *mq_device_list [MAX_MQ11XX_DEVICES];
171 static spinlock_t mq_device_list_lock = SPIN_LOCK_UNLOCKED;
173 #define to_mq_data(n) container_of(n, struct mq_data, base)
175 /* For PCI & DragonBall register mapping is as described in the specs sheet;
176 * for other microprocessor buses some addresses are tossed (what a perversion).
177 * Worse than that, on MQ1168 and later, the registers are always as normal.
178 */
179 #if defined __arm__
180 // || defined NEC41xx || defined HITACHI 77xx
181 #define MQ_MASK_REGSET1 (MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188)
182 #define MQ_MASK_REGSET2 (MQ_MASK_1100 | MQ_MASK_1132)
183 #else
184 #define MQ_MASK_REGSET1 MQ_MASK_ALL
185 #define MQ_MASK_REGSET2 0
186 #endif
188 static struct mediaq11xx_init_data mqInitValid = {
189 /* DC */
190 {
191 /* dc00 */ 0,
192 /* dc01 */ MQ_MASK_ALL,
193 /* dc02 */ MQ_MASK_ALL,
194 /* dc03 */ 0,
195 /* dc04 */ MQ_MASK_ALL,
196 /* dc05 */ MQ_MASK_ALL,
197 },
198 /* CC */
199 {
200 /* cc00 */ MQ_MASK_ALL,
201 /* cc01 */ MQ_MASK_ALL,
202 /* cc02 */ MQ_MASK_ALL,
203 /* cc03 */ MQ_MASK_ALL,
204 /* cc04 */ MQ_MASK_ALL,
205 },
206 /* MIU */
207 {
208 /* mm00 */ MQ_MASK_ALL,
209 /* mm01 */ MQ_MASK_ALL,
210 /* mm02 */ MQ_MASK_ALL,
211 /* mm03 */ MQ_MASK_ALL,
212 /* mm04 */ MQ_MASK_ALL,
213 /* mm05 */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
214 /* mm06 */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
215 },
216 /* GC */
217 {
218 /* gc00 */ MQ_MASK_ALL,
219 /* gc01 */ MQ_MASK_ALL,
220 /* gc02 */ MQ_MASK_ALL,
221 /* gc03 */ MQ_MASK_ALL,
222 /* gc04 */ MQ_MASK_ALL,
223 /* gc05 */ MQ_MASK_ALL,
224 /* gc06 NOT SET */ 0,
225 /* gc07 NOT SET */ 0,
226 /* gc08 */ MQ_MASK_ALL,
227 /* gc09 */ MQ_MASK_ALL,
228 /* gc0a */ MQ_MASK_ALL,
229 /* gc0b */ MQ_MASK_ALL,
230 /* gc0c */ MQ_MASK_ALL,
231 /* gc0d */ MQ_MASK_ALL,
232 /* gc0e */ MQ_MASK_ALL,
233 /* gc0f NOT SET */ 0,
234 /* gc10 */ MQ_MASK_ALL,
235 /* gc11 */ MQ_MASK_ALL,
236 /* gc12 NOT SET */ 0,
237 /* gc13 NOT SET */ 0,
238 /* gc14 */ MQ_MASK_ALL,
239 /* gc15 */ MQ_MASK_ALL,
240 /* gc16 */ MQ_MASK_ALL,
241 /* gc17 */ MQ_MASK_ALL,
242 /* gc18 */ MQ_MASK_ALL,
243 /* gc19 */ MQ_MASK_ALL,
244 /* gc1a */ MQ_MASK_ALL,
245 },
246 /* FP */
247 {
248 /* fp00 */ MQ_MASK_ALL,
249 /* fp01 */ MQ_MASK_ALL,
250 /* fp02 */ MQ_MASK_ALL,
251 /* fp03 */ MQ_MASK_ALL,
252 /* fp04 */ MQ_MASK_ALL,
253 /* fp05 */ MQ_MASK_ALL,
254 /* fp06 */ MQ_MASK_ALL,
255 /* fp07 */ MQ_MASK_ALL,
256 /* fp08 */ MQ_MASK_ALL,
257 /* fp09 NOT SET */ 0,
258 /* fp0a */ MQ_MASK_ALL,
259 /* fp0b */ MQ_MASK_ALL,
260 /* fp0c */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
261 /* fp0d NOT SET */ 0,
262 /* fp0e NOT SET */ 0,
263 /* fp0f */ MQ_MASK_ALL,
264 /* fp10 */ MQ_MASK_ALL,
265 /* fp11 */ MQ_MASK_ALL,
266 /* fp12 */ MQ_MASK_ALL,
267 /* fp13 */ MQ_MASK_ALL,
268 /* fp14 */ MQ_MASK_ALL,
269 /* fp15 */ MQ_MASK_ALL,
270 /* fp16 */ MQ_MASK_ALL,
271 /* fp17 */ MQ_MASK_ALL,
272 /* fp18 */ MQ_MASK_ALL,
273 /* fp19 */ MQ_MASK_ALL,
274 /* fp1a */ MQ_MASK_ALL,
275 /* fp1b */ MQ_MASK_ALL,
276 /* fp1c */ MQ_MASK_ALL,
277 /* fp1d */ MQ_MASK_ALL,
278 /* fp1e */ MQ_MASK_ALL,
279 /* fp1f */ MQ_MASK_ALL,
280 /* fp20 */ MQ_MASK_REGSET1,
281 /* fp21 */ MQ_MASK_REGSET1,
282 /* fp22 */ MQ_MASK_REGSET1,
283 /* fp23 */ MQ_MASK_REGSET1,
284 /* fp24 */ MQ_MASK_REGSET1,
285 /* fp25 */ MQ_MASK_REGSET1,
286 /* fp26 */ MQ_MASK_REGSET1,
287 /* fp27 */ MQ_MASK_REGSET1,
288 /* fp28 */ MQ_MASK_REGSET1,
289 /* fp29 */ MQ_MASK_REGSET1,
290 /* fp2a */ MQ_MASK_REGSET1,
291 /* fp2b */ MQ_MASK_REGSET1,
292 /* fp2c */ MQ_MASK_REGSET1,
293 /* fp2d */ MQ_MASK_REGSET1,
294 /* fp2e */ MQ_MASK_REGSET1,
295 /* fp2f */ MQ_MASK_REGSET1,
296 /* fp30 */ MQ_MASK_ALL,
297 /* fp31 */ MQ_MASK_ALL,
298 /* fp32 */ MQ_MASK_ALL,
299 /* fp33 */ MQ_MASK_ALL,
300 /* fp34 */ MQ_MASK_ALL,
301 /* fp35 */ MQ_MASK_ALL,
302 /* fp36 */ MQ_MASK_ALL,
303 /* fp37 */ MQ_MASK_ALL,
304 /* fp38 */ MQ_MASK_ALL,
305 /* fp39 */ MQ_MASK_ALL,
306 /* fp3a */ MQ_MASK_ALL,
307 /* fp3b */ MQ_MASK_ALL,
308 /* fp3c */ MQ_MASK_ALL,
309 /* fp3d */ MQ_MASK_ALL,
310 /* fp3e */ MQ_MASK_ALL,
311 /* fp3f */ MQ_MASK_ALL,
312 /* fp40 */ 0,
313 /* fp41 */ 0,
314 /* fp42 */ 0,
315 /* fp43 */ 0,
316 /* fp44 */ 0,
317 /* fp45 */ 0,
318 /* fp46 */ 0,
319 /* fp47 */ 0,
320 /* fp48 */ 0,
321 /* fp49 */ 0,
322 /* fp4a */ 0,
323 /* fp4b */ 0,
324 /* fp4c */ 0,
325 /* fp4d */ 0,
326 /* fp4e */ 0,
327 /* fp4f */ 0,
328 /* fp50 */ 0,
329 /* fp51 */ 0,
330 /* fp52 */ 0,
331 /* fp53 */ 0,
332 /* fp54 */ 0,
333 /* fp55 */ 0,
334 /* fp56 */ 0,
335 /* fp57 */ 0,
336 /* fp58 */ 0,
337 /* fp59 */ 0,
338 /* fp5a */ 0,
339 /* fp5b */ 0,
340 /* fp5c */ 0,
341 /* fp5d */ 0,
342 /* fp5e */ 0,
343 /* fp5f */ 0,
344 /* fp60 */ 0,
345 /* fp61 */ 0,
346 /* fp62 */ 0,
347 /* fp63 */ 0,
348 /* fp64 */ 0,
349 /* fp65 */ 0,
350 /* fp66 */ 0,
351 /* fp67 */ 0,
352 /* fp68 */ 0,
353 /* fp69 */ 0,
354 /* fp6a */ 0,
355 /* fp6b */ 0,
356 /* fp6c */ 0,
357 /* fp6d */ 0,
358 /* fp6e */ 0,
359 /* fp6f */ 0,
360 /* fp70 */ MQ_MASK_REGSET2,
361 /* fp71 */ MQ_MASK_REGSET2,
362 /* fp72 */ MQ_MASK_REGSET2,
363 /* fp73 */ MQ_MASK_REGSET2,
364 /* fp74 */ MQ_MASK_REGSET2,
365 /* fp75 */ MQ_MASK_REGSET2,
366 /* fp76 */ MQ_MASK_REGSET2,
367 /* fp77 */ MQ_MASK_REGSET2,
368 },
369 /* GE */
370 {
371 /* ge00 NOT SET */ 0,
372 /* ge01 NOT SET */ 0,
373 /* ge02 NOT SET */ 0,
374 /* ge03 NOT SET */ 0,
375 /* ge04 NOT SET */ 0,
376 /* ge05 NOT SET */ 0,
377 /* ge06 NOT SET */ 0,
378 /* ge07 NOT SET */ 0,
379 /* ge08 NOT SET */ 0,
380 /* ge09 NOT SET */ 0,
381 /* ge0a */ MQ_MASK_ALL,
382 /* ge0b */ MQ_MASK_ALL,
383 /* ge0c NOT SET */ 0x0,
384 /* ge0d NOT SET */ 0x0,
385 /* ge0e NOT SET */ 0x0,
386 /* ge0f NOT SET */ 0x0,
387 /* ge10 NOT SET */ 0x0,
388 /* ge11 NOT SET */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
389 /* ge12 NOT SET */ 0x0,
390 /* ge13 NOT SET */ 0x0,
391 },
392 /* SPI */
393 {
394 /* sp00 */ MQ_MASK_1132,
395 /* sp01 */ 0,
396 /* sp02 NOT SET */ 0,
397 /* sp03 NOT SET */ 0,
398 /* sp04 */ MQ_MASK_1132,
399 /* sp05 NOT SET */ 0,
400 /* sp06 NOT SET */ 0,
401 /* sp07 */ MQ_MASK_1132,
402 /* sp08 */ MQ_MASK_1132,
403 },
404 };
406 static int
407 mq11xx_loadvals (char *name, int chipmask, volatile u32 *reg,
408 u32 *src, u32 *valid, int n)
409 {
410 int t;
412 for (t = 0; t < n; t++){
413 if (valid[t] & chipmask) {
414 int tries;
415 for (tries = 0; tries < 10; tries++) {
416 reg[t] = src[t];
417 if (reg[t] == src[t])
418 break;
419 mdelay (1);
420 }
421 if (tries == 10) {
422 debug ("mq11xx_loadvals %s%02x %08x FAILED (got %08x)\n", name, t, src[t], reg[t]);
423 return -ENODEV;
424 }
425 }
426 }
427 return 0;
428 }
430 static int
431 mq11xx_init (struct mq_data *mqdata)
432 {
433 int i, chipmask;
434 u16 endian;
436 if (mqdata->mq_init->set_power)
437 mqdata->mq_init->set_power(1);
439 /* Set up chip endianness - see mq docs for notes on special care
440 when writing to this register */
441 endian = mqdata->mq_init->DC [0] & 3;
442 endian = endian | (endian << 2);
443 endian = endian | (endian << 4);
444 endian = endian | (endian << 8);
445 *((u16 *)&mqdata->base.regs->DC.config_0) = endian;
446 /* First of all, enable the oscillator clock */
447 mqdata->base.regs->DC.config_1 = mqdata->mq_init->DC [1];
448 /* Wait for oscillator to run - 30ms doesnt suffice */
449 mdelay (100);
450 /* Enable power to CPU Configuration module */
451 mqdata->base.regs->DC.config_2 = mqdata->mq_init->DC [2];
452 mdelay (10);
453 /* Needed for MediaQ 1178/88 on h2200. */
454 mqdata->base.regs->DC.config_8 = 0x86098609;
455 /* Enable the MQ1132 MIU */
456 mqdata->base.regs->MIU.miu_0 |= MQ_MIU_ENABLE;
457 /* Disable the interrupt controller */
458 mqdata->base.regs->IC.control = 0;
460 /* See if it's actually a MediaQ chip */
461 if (mqdata->base.regs->PCI.vendor_id != MQ_PCI_VENDORID) {
462 unkchip: printk (KERN_ERR "%s:%d Unknown device ID (%04x:%04x)\n",
463 __FILE__, __LINE__,
464 mqdata->base.regs->PCI.vendor_id,
465 mqdata->base.regs->PCI.device_id);
466 return -ENODEV;
467 }
469 for (i = 0; i < ARRAY_SIZE (mq_device_id); i++)
470 if (mqdata->base.regs->PCI.device_id == mq_device_id [i].id) {
471 mqdata->base.chip = mq_device_id [i].chip;
472 mqdata->base.chipname = mq_device_id [i].name;
473 break;
474 }
476 if (!mqdata->base.chipname)
477 goto unkchip;
479 chipmask = 1 << mqdata->base.chip;
481 #define INIT_REGS(id) \
482 if (mq11xx_loadvals (#id, chipmask, mqdata->base.regs->id.a, \
483 mqdata->mq_init->id, mqInitValid.id, \
484 ARRAY_SIZE (mqdata->mq_init->id))) \
485 return -ENODEV
487 INIT_REGS (DC);
488 INIT_REGS (CC);
489 INIT_REGS (MIU);
491 /* XXX Move this stuff to mq1100fb driver some day */
492 INIT_REGS (GC);
493 INIT_REGS (FP);
494 INIT_REGS (GE);
496 #undef INIT_REGS
498 return 0;
499 }
501 static void
502 mq_release (struct device *dev)
503 {
504 }
506 /* This is kind of ugly and complex... well, this is the way GPIOs are
507 * programmed on MediaQ... what a mess...
508 */
509 static int
510 mq_set_GPIO (struct mediaq11xx_base *zis, int num, int state)
511 {
512 u32 andmask = 0, ormask = 0;
514 debug ("mq_set_GPIO (num:%d state:%x)\n", num, state);
516 if ((num <= 7) || ((num >= 20) && (num <= 25))) {
517 andmask = 4;
518 if (state & MQ_GPIO_CHMODE) {
519 andmask |= 3;
520 if (state & MQ_GPIO_IN)
521 ormask |= 1;
522 if (state & MQ_GPIO_OUT)
523 ormask |= 2;
524 }
525 if (state & MQ_GPIO_0)
526 andmask |= 8;
527 if (state & MQ_GPIO_1)
528 ormask |= 8;
529 if (num <= 7) {
530 andmask <<= num * 4;
531 ormask <<= num * 4;
532 zis->regs->CC.gpio_control_0 =
533 (zis->regs->CC.gpio_control_0 & ~andmask) | ormask;
534 } else {
535 andmask <<= (num - 18) * 4;
536 ormask <<= (num - 18) * 4;
537 zis->regs->CC.gpio_control_1 =
538 (zis->regs->CC.gpio_control_1 & ~andmask) | ormask;
539 }
540 } else if (num >= 50 && num <= 55) {
541 int shft;
543 /* Uhh.... what a mess */
544 if (state & MQ_GPIO_CHMODE) {
545 shft = (num <= 53) ? num - 48 : num - 45;
546 andmask |= 3 << shft;
547 if (state & MQ_GPIO_OUT)
548 ormask |= (1 << (shft * 2));
549 if (state & MQ_GPIO_IN)
550 ormask |= (2 << (shft * 2));
551 }
553 if (num == 50)
554 shft = 3;
555 else if (num <= 53)
556 shft = (num - 51);
557 else
558 shft = (num - 38);
560 if (state & MQ_GPIO_0)
561 andmask |= (1 << shft);
562 if (state & MQ_GPIO_1)
563 ormask |= (1 << shft);
564 if ((state & MQ_GPIO_PULLUP) && (num <= 53))
565 ormask |= 0x1000 << (num - 50);
566 zis->regs->SPI.gpio_mode =
567 (zis->regs->SPI.gpio_mode & ~andmask) | ormask;
568 } else if (num >= 60 && num <= 66) {
569 int shft = (num - 60);
570 if (state & MQ_GPIO_0)
571 andmask |= (1 << shft);
572 if (state & MQ_GPIO_1)
573 ormask |= (1 << shft);
574 shft *= 2;
575 if (state & MQ_GPIO_CHMODE) {
576 andmask |= (0x300 << shft);
577 if (state & MQ_GPIO_OUT)
578 ormask |= (0x100 << shft);
579 if (state & MQ_GPIO_IN)
580 ormask |= (0x200 << shft);
581 }
582 zis->regs->SPI.blue_gpio_mode =
583 (zis->regs->SPI.blue_gpio_mode & ~andmask) | ormask;
584 } else
585 return -ENODEV;
587 return 0;
588 }
590 static int
591 mq_get_GPIO (struct mediaq11xx_base *zis, int num)
592 {
593 u32 val;
595 if (num <= 7)
596 val = zis->regs->CC.gpio_control_0 & (8 << (num * 4));
597 else if ((num >= 20) && (num <= 25))
598 val = zis->regs->CC.gpio_control_1 & (8 << ((num - 18) * 4));
599 else if (num == 50)
600 val = zis->regs->SPI.gpio_mode & 0x8;
601 else if ((num >= 51) && (num <= 53))
602 val = zis->regs->SPI.gpio_mode & (0x1 << (num - 51));
603 else if ((num >= 54) && (num <= 55))
604 val = zis->regs->SPI.gpio_mode & (0x1 << (num - 38));
605 else if (num >= 60 && num <= 66)
606 val = zis->regs->SPI.blue_gpio_mode & (1 << (num - 60));
607 else
608 val = 0;
610 if (val) val = 1;
612 return val;
613 }
615 static int
616 global_power (struct mq_data *mqdata)
617 {
618 int i;
619 for (i = 0; i < sizeof (mqdata->power_on); i++)
620 if (mqdata->power_on [i])
621 return 1;
622 return 0;
623 }
625 static void
626 mq_power_on (struct mediaq11xx_base *zis, int subdev_id)
627 {
628 /* The device IDs lower 4 bits contains the subdevice index
629 * (counting from 1). Take care to keep all MEDIAQ_11XX_XXX
630 * contstants with sequential values in their lower 4 bits!
631 */
632 unsigned idx = (subdev_id & 0x0f) - 1;
633 struct mq_data *mqdata = to_mq_data (zis);
635 debug_func ("subdev:%x curstate:%d\n", subdev_id, mqdata->power_on [idx]);
637 /* Check if MediaQ is not totally turned off */
638 if (!global_power (mqdata)) {
639 debug ("-*- Global POWER ON to the MediaQ chip -*-\n");
640 mq11xx_init (mqdata);
641 }
643 if (!mqdata->power_on [idx])
644 switch (subdev_id) {
645 case MEDIAQ_11XX_FB_DEVICE_ID:
646 zis->regs->GC.control |= MQ_GC_CONTROL_ENABLE;
647 /* Enable the graphics engine power */
648 zis->regs->DC.config_5 |= MQ_CONFIG_GE_ENABLE;
649 break;
650 case MEDIAQ_11XX_FP_DEVICE_ID:
651 /* Enable flat panel pin outputs */
652 //zis->regs->FP.pin_control_1 &= ~MQ_FP_DISABLE_FLAT_PANEL_PINS;
653 zis->regs->FP.output_control = mqdata->mq_init->FP [2];
654 break;
655 case MEDIAQ_11XX_UDC_DEVICE_ID:
656 /* Enable power to USB function */
657 zis->regs->DC.config_5 |= MQ_CONFIG_UDC_CLOCK_ENABLE;
658 break;
659 case MEDIAQ_11XX_UHC_DEVICE_ID:
660 /* Enable power to USB host */
661 zis->regs->DC.config_5 |= MQ_CONFIG_UHC_CLOCK_ENABLE;
662 break;
663 case MEDIAQ_11XX_SPI_DEVICE_ID:
664 case MEDIAQ_11XX_I2S_DEVICE_ID:
665 /* There's no explicit way to do it */
666 break;
667 }
668 mqdata->power_on [idx]++;
669 }
671 static void
672 mq_power_off (struct mediaq11xx_base *zis, int subdev_id)
673 {
674 unsigned idx = (subdev_id & 0x0f) - 1;
675 struct mq_data *mqdata = to_mq_data (zis);
677 debug_func ("subdev:%x curstate:%d\n", subdev_id, mqdata->power_on [idx]);
679 if (!mqdata->power_on [idx]) {
680 printk (KERN_ERR "mq11xx: mismatch power on/off request count for subdevice %x\n",
681 subdev_id);
682 return;
683 }
685 switch (subdev_id) {
686 case MEDIAQ_11XX_FB_DEVICE_ID:
687 zis->regs->GC.control &= ~MQ_GC_CONTROL_ENABLE;
688 /* Disable the graphics engine power */
689 zis->regs->DC.config_5 &= ~MQ_CONFIG_GE_ENABLE;
690 break;
691 case MEDIAQ_11XX_FP_DEVICE_ID:
692 /* Disable flat panel pin outputs */
693 zis->regs->FP.output_control = 0;
694 //zis->regs->FP.pin_control_1 |= MQ_FP_DISABLE_FLAT_PANEL_PINS;
695 break;
696 case MEDIAQ_11XX_UDC_DEVICE_ID:
697 /* Disable power to USB function */
698 zis->regs->DC.config_5 &= ~MQ_CONFIG_UDC_CLOCK_ENABLE;
699 break;
700 case MEDIAQ_11XX_UHC_DEVICE_ID:
701 /* Disable power to USB host */
702 zis->regs->DC.config_5 &= ~MQ_CONFIG_UHC_CLOCK_ENABLE;
703 break;
704 case MEDIAQ_11XX_SPI_DEVICE_ID:
705 case MEDIAQ_11XX_I2S_DEVICE_ID:
706 /* There's no explicit way to do it */
707 break;
708 }
710 mqdata->power_on [idx]--;
712 /* Check if we have to totally power off MediaQ */
713 if (!global_power (mqdata)) {
714 debug ("-*- Global POWER OFF to MediaQ chip -*-\n");
715 /* Disable the MQ1132 MIU */
716 zis->regs->MIU.miu_0 &= ~MQ_MIU_ENABLE;
717 /* Disable power to CPU Configuration module */
718 zis->regs->DC.config_2 &= ~MQ_CONFIG_CC_MODULE_ENABLE;
719 /* Disable the oscillator clock */
720 zis->regs->DC.config_1 &= ~MQ_CONFIG_18_OSCILLATOR;
722 if (mqdata->mq_init->set_power)
723 mqdata->mq_init->set_power(0);
724 }
725 }
727 static void
728 mq_set_power (struct mediaq11xx_base *zis, int subdev_id, int state)
729 {
730 if (state)
731 mq_power_on (zis, subdev_id);
732 else
733 mq_power_off (zis, subdev_id);
734 }
736 static int
737 mq_get_power (struct mediaq11xx_base *zis, int subdev_id)
738 {
739 unsigned idx = (subdev_id & 0x0f) - 1;
740 struct mq_data *mqdata = to_mq_data (zis);
741 return mqdata->power_on [idx];
742 }
744 /********************************************* On-chip memory management ******/
746 /**
747 * Since the internal chip RAM may be shared amongst several subdevices
748 * (framebuffer, graphics engine, SPI, UDC and other), we have to implement
749 * a general memory management mechanism to prevent conflicts between drivers
750 * trying to use this resource.
751 *
752 * We could use the "chained free blocks" scheme used in many simple memory
753 * managers, where a { free block size; next free block; } structure is
754 * stuffed directly into the free block itself, to conserve memory. However,
755 * this mechanism is less reliable since it is susceptible to overwrites
756 * past the bounds of an allocated block (because it breaks the free blocks
757 * chain). Of course, a buggy driver is always a bad idea, but we should try
758 * to be as reliable as possible. Thus, the free block chain is kept in kernel
759 * memory (in the device-specific structure), and everything else is done like
760 * in the mentioned scheme.
761 */
763 static void
764 mq_setfreeblocks (struct mq_data *mqdata, int nblocks)
765 {
766 void *temp;
767 int newmax;
769 /* Increase maximum number of free memory descriptors in power-of-two
770 steps. This is due to the fact, that Linux allocates memory in
771 power-of-two chunks, and the minimal chunk (slab) size is 32b.
772 Allocating anything but power-of-two sized memory blocks is just
773 a waste of memory. In fact, in most circumstances we have a small
774 number of free block descriptors. */
775 newmax = (nblocks > 0) ? (1 << fls (nblocks - 1)) : 1;
776 if (likely (newmax < MEMBLOCK_MINCOUNT))
777 newmax = MEMBLOCK_MINCOUNT;
779 if (mqdata->maxfreeblocks != newmax) {
780 int nfb = mqdata->nfreeblocks;
781 if (nfb > nblocks) nfb = nblocks;
782 temp = kmalloc (newmax * sizeof (struct mq_freemem_list),
783 GFP_KERNEL);
784 memcpy (temp, mqdata->freelist, nfb * sizeof (struct mq_freemem_list));
785 kfree (mqdata->freelist);
786 mqdata->freelist = temp;
787 mqdata->maxfreeblocks = newmax;
788 }
790 mqdata->nfreeblocks = nblocks;
791 }
793 /* Check if memory block is suitable for uses other than graphics. */
794 static int mq_suitable_ram (struct mq_data *mqdata, int fbn, unsigned size)
795 {
796 int n, delta;
798 delta = mqdata->unsynced_ram_skip - mqdata->freelist [fbn].addr;
799 if (delta <= 0)
800 return 1;
802 if (mqdata->freelist [fbn].size < size + delta)
803 return 0;
805 /* Ok, split the free block into two */
806 n = mqdata->nfreeblocks;
807 mq_setfreeblocks (mqdata, n + 1);
808 mqdata->freelist [n].addr = mqdata->freelist [fbn].addr;
809 mqdata->freelist [n].size = delta;
810 mqdata->freelist [fbn].addr += delta;
811 mqdata->freelist [fbn].size -= delta;
813 return 1;
814 }
816 /* Not too optimal (just finds the first free block of equal or larger size
817 * than requested) but usually there are a few blocks in MediaQ RAM anyway...
818 * usually a block of 320x240x2 bytes is eaten by the framebuffer, and we
819 * have just 256k total.
820 */
821 static u32
822 mq_alloc (struct mediaq11xx_base *zis, unsigned size, int gfx)
823 {
824 struct mq_data *mqdata = to_mq_data (zis);
825 int i;
827 size = (size + MEMBLOCK_ALIGN - 1) & ~(MEMBLOCK_ALIGN - 1);
829 spin_lock (&mqdata->mem_lock);
831 for (i = mqdata->nfreeblocks - 1; i >= 0; i--) {
832 if ((mqdata->freelist [i].size >= size) &&
833 (gfx || mq_suitable_ram (mqdata, i, size))) {
834 u32 addr = mqdata->freelist [i].addr;
835 mqdata->freelist [i].size -= size;
836 if (mqdata->freelist [i].size)
837 mqdata->freelist [i].addr += size;
838 else {
839 memcpy (mqdata->freelist + i, mqdata->freelist + i + 1,
840 (mqdata->nfreeblocks - 1 - i) * sizeof (struct mq_freemem_list));
841 mq_setfreeblocks (mqdata, mqdata->nfreeblocks - 1);
842 }
843 spin_unlock (&mqdata->mem_lock);
844 return addr;
845 }
846 }
848 spin_unlock (&mqdata->mem_lock);
850 return (u32)-1;
851 }
853 static void
854 mq_free (struct mediaq11xx_base *zis, u32 addr, unsigned size)
855 {
856 int i, j;
857 u32 eaddr;
858 struct mq_data *mqdata = to_mq_data (zis);
860 size = (size + MEMBLOCK_ALIGN - 1) & ~(MEMBLOCK_ALIGN - 1);
861 eaddr = addr + size;
863 spin_lock (&mqdata->mem_lock);
865 /* Look for a free block that starts at the end of the block to free */
866 for (i = mqdata->nfreeblocks - 1; i >= 0; i--)
867 if (mqdata->freelist [i].addr == eaddr) {
868 mqdata->freelist [i].size += size;
869 mqdata->freelist [i].addr = addr;
870 /* Now look for a block that ends where we start */
871 for (j = mqdata->nfreeblocks - 1; j >= 0; j--) {
872 if (mqdata->freelist [j].addr + mqdata->freelist [j].size == addr) {
873 /* Ok, concatenate the two free blocks */
874 mqdata->freelist [i].addr = mqdata->freelist [j].addr;
875 mqdata->freelist [i].size += mqdata->freelist [j].size;
876 memcpy (mqdata->freelist + j, mqdata->freelist + j + 1,
877 (mqdata->nfreeblocks - 1 - j) * sizeof (struct mq_freemem_list));
878 mq_setfreeblocks (mqdata, mqdata->nfreeblocks - 1);
879 break;
880 }
881 }
882 spin_unlock (&mqdata->mem_lock);
883 return;
884 }
886 for (i = mqdata->nfreeblocks - 1; i >= 0; i--)
887 if (mqdata->freelist [i].addr + mqdata->freelist [i].size == addr) {
888 mqdata->freelist [i].size += size;
889 spin_unlock (&mqdata->mem_lock);
890 return;
891 }
893 /* Ok, we have to add a new free block entry */
894 i = mqdata->nfreeblocks;
895 mq_setfreeblocks (mqdata, i + 1);
896 mqdata->freelist [i].addr = addr;
897 mqdata->freelist [i].size = size;
899 spin_unlock (&mqdata->mem_lock);
900 }
902 /**************************** IRQ handling using interrupt multiplexing ******/
904 #ifdef MQ_IRQ_MULTIPLEX
906 static void
907 mq_irq_demux (unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
908 {
909 u32 mask, orig_mask;
910 int i, mq_irq, timeout;
911 struct mq_data *mqdata;
913 mqdata = desc->handler_data;
915 mqdata->base.regs->IC.control &= ~MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE;
917 debug ("mq_irq_demux ENTER\n");
919 /* An IRQ is a expensive operation, thus we're handling here
920 * as much interrupt sources as we can (rather than returning
921 * from interrupt just to get caught once again). On the other
922 * hand, we can't process too much of them since some IRQ may be
923 * continuously triggered. Thus, we'll set an arbitrary upper limit
924 * on the number of interrupts we can handle at once. Note that,
925 * for example, if PCMCIA IRQ is connected to MediaQ, this number
926 * can be very large, e.g. one interrupt for every read sector
927 * from a memory card.
928 */
929 timeout = 1024;
931 /* Read the IRQ status register */
932 while (timeout-- &&
933 (mask = orig_mask = mqdata->base.regs->IC.interrupt_status)) {
934 irq = 0;
935 while ((i = ffs (mask))) {
936 irq += i - 1;
937 mq_irq = mqdata->base.irq_base + irq;
938 desc = irq_desc + mq_irq;
939 debug ("mq_irq_demux (irq:%d)\n", mq_irq);
940 desc->handle_irq(mq_irq, desc, regs);
941 mask >>= i;
942 }
943 }
945 if (!timeout)
946 printk (KERN_ERR "mq11xx: IRQ continuously triggered, mask %08x\n", mask);
948 debug ("mq_irq_demux LEAVE\n");
950 mqdata->base.regs->IC.control |= MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE;
951 }
953 /* Acknowledge, clear _AND_ disable the interrupt. */
954 static void
955 mq_irq_ack (unsigned int irq)
956 {
957 struct mq_data *mqdata = get_irq_chipdata (irq);
958 u32 mask = 1 << (irq - mqdata->base.irq_base);
959 /* Disable the IRQ */
960 mqdata->base.regs->IC.interrupt_mask &= ~mask;
961 /* Acknowledge the IRQ */
962 mqdata->base.regs->IC.interrupt_status = mask;
963 }
965 static void
966 mq_irq_mask (unsigned int irq)
967 {
968 struct mq_data *mqdata = get_irq_chipdata (irq);
969 u32 mask = 1 << (irq - mqdata->base.irq_base);
970 mqdata->base.regs->IC.interrupt_mask &= ~mask;
971 }
973 static void
974 mq_irq_unmask (unsigned int irq)
975 {
976 struct mq_data *mqdata = get_irq_chipdata (irq);
977 u32 mask = 1 << (irq - mqdata->base.irq_base);
978 mqdata->base.regs->IC.interrupt_mask |= mask;
979 }
981 static int
982 mq_irq_type (unsigned int irq, unsigned int type)
983 {
984 struct mq_data *mqdata = get_irq_chipdata (irq);
985 int mask;
987 if ((irq < mqdata->base.irq_base + IRQ_MQ_GPIO_0) ||
988 (irq > mqdata->base.irq_base + IRQ_MQ_GPIO_2))
989 return 0;
991 mask = MQ_INTERRUPT_CONTROL_GPIO_0_INTERRUPT_POLARITY <<
992 (irq - mqdata->base.irq_base - IRQ_MQ_GPIO_0);
994 if (type & (__IRQT_HIGHLVL | __IRQT_RISEDGE))
995 mqdata->base.regs->IC.control |= mask;
996 else if (type & (__IRQT_LOWLVL | __IRQT_FALEDGE))
997 mqdata->base.regs->IC.control &= ~mask;
999 return 0;
1000 }
1002 static struct irqchip mq_irq_chip = {
1003 .ack = mq_irq_ack,
1004 .mask = mq_irq_mask,
1005 .unmask = mq_irq_unmask,
1006 .set_type = mq_irq_type,
1007 };
1009 static int
1010 mq_irq_init (struct mq_data *mqdata)
1011 {
1012 int i;
1014 /* Disable all IRQs */
1015 mqdata->base.regs->IC.control = 0;
1016 mqdata->base.regs->IC.interrupt_mask = 0;
1017 /* Clear IRQ status */
1018 mqdata->base.regs->IC.interrupt_status = 0xffffffff;
1020 mqdata->base.irq_base = alloc_irq_space (MQ11xx_NUMIRQS);
1021 if (mqdata->base.irq_base < 0) {
1022 printk (KERN_ERR "There is no space for %d IRQs in core IRQ table!\n",
1023 MQ11xx_NUMIRQS);
1024 return -ENOMEM;
1025 }
1027 debug_func ("base IRQ number is %d\n", mqdata->base.irq_base);
1029 for (i = 0; i < MQ11xx_NUMIRQS; i++) {
1030 int irq = mqdata->base.irq_base + i;
1031 set_irq_flags (irq, IRQF_VALID);
1032 set_irq_chip (irq, &mq_irq_chip);
1033 set_irq_handler (irq, do_level_IRQ);
1034 set_irq_chipdata (irq, mqdata);
1035 }
1037 i = (mqdata->base.regs->IC.control & MQ_INTERRUPT_CONTROL_INTERRUPT_POLARITY);
1038 set_irq_chained_handler (mqdata->irq_nr, mq_irq_demux);
1039 set_irq_type (mqdata->irq_nr, i ? IRQT_RISING : IRQT_FALLING);
1040 set_irq_data (mqdata->irq_nr, mqdata);
1042 /* Globally enable IRQs from MediaQ */
1043 mqdata->base.regs->IC.control |= MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE;
1045 return 0;
1046 }
1048 static void
1049 mq_irq_free (struct mq_data *mqdata)
1050 {
1051 /* Disable all IRQs */
1052 mqdata->base.regs->IC.control = 0;
1053 mqdata->base.regs->IC.interrupt_mask = 0;
1054 /* Clear IRQ status */
1055 mqdata->base.regs->IC.interrupt_status = 0xffffffff;
1057 set_irq_handler (mqdata->irq_nr, do_edge_IRQ);
1059 free_irq_space (mqdata->base.irq_base, MQ11xx_NUMIRQS);
1060 }
1061 #endif
1063 int
1064 mq_device_enum (struct mediaq11xx_base **list, int list_size)
1065 {
1066 int i, j;
1068 if (!list_size)
1069 return 0;
1071 spin_lock (&mq_device_list_lock);
1072 for (i = j = 0; i < MAX_MQ11XX_DEVICES; i++)
1073 if (mq_device_list [i]) {
1074 list [j++] = mq_device_list [i];
1075 if (j >= list_size)
1076 break;
1077 }
1078 spin_unlock (&mq_device_list_lock);
1080 return j;
1081 }
1082 EXPORT_SYMBOL (mq_device_enum);
1084 int
1085 mq_driver_get (void)
1086 {
1087 return try_module_get (THIS_MODULE) ? 0 : -ENXIO;
1088 }
1089 EXPORT_SYMBOL (mq_driver_get);
1091 void
1092 mq_driver_put (void)
1093 {
1094 module_put (THIS_MODULE);
1095 }
1096 EXPORT_SYMBOL (mq_driver_put);
1098 /*
1099 * Resources specified in resource table for this driver are:
1100 * 0: Synchronous RAM address (physical base + 0 on ARM arch)
1101 * 1: Asynchronous RAM address (physical base + 256K+2K on ARM arch)
1102 * 2: Registers address (physical base + 256K on ARM arch)
1103 * 3: The MediaQ IRQ number
1104 *
1105 * Also the platform_data field of the device should contain a pointer to
1106 * a mq11xx_platform_data structure, which contains the platform-specific
1107 * initialization data for MediaQ chip, the name of framebuffer driver
1108 * and the name of LCD driver.
1109 */
1110 static int
1111 mq_initialize (struct device *dev, int num_resources,
1112 struct resource *resource, int instance)
1113 {
1114 int i, j, k, rc, chipmask;
1115 struct mq_data *mqdata;
1116 struct mediaq11xx_init_data *init_data =
1117 (struct mediaq11xx_init_data *)dev->platform_data;
1119 if (!init_data || num_resources != 4) {
1120 printk (KERN_ERR "mq11xx_base: Incorrect platform resources!\n");
1121 return -ENODEV;
1122 }
1124 mqdata = kmalloc (sizeof (struct mq_data), GFP_KERNEL);
1125 if (!mqdata)
1126 return -ENOMEM;
1127 memset (mqdata, 0, sizeof (struct mq_data));
1128 dev_set_drvdata (dev, mqdata);
1130 #define IOREMAP(v, n, el) \
1131 mqdata->base.v = ioremap (resource[n].start, \
1132 resource[n].end - resource[n].start + 1); \
1133 if (!mqdata->base.v) goto el; \
1134 mqdata->base.paddr_##v = resource[n].start;
1136 IOREMAP (gfxram, 0, err0);
1137 IOREMAP (ram, 1, err1);
1138 IOREMAP (regs, 2, err2);
1140 #undef IOREMAP
1142 /* Check how much RAM is accessible through the unsynced window */
1143 mqdata->unsynced_ram_skip =
1144 (resource [0].end - resource [0].start) -
1145 (resource [1].end - resource [1].start);
1146 mqdata->base.ram -= mqdata->unsynced_ram_skip;
1147 mqdata->base.paddr_ram -= mqdata->unsynced_ram_skip;
1149 mqdata->ndevices = MQ_SUBDEVS_REAL_COUNT;
1150 mqdata->devices = kmalloc (mqdata->ndevices *
1151 (sizeof (struct platform_device)), GFP_KERNEL);
1152 if (!mqdata->devices)
1153 goto err3;
1155 mqdata->mq_init = init_data;
1156 if (mq11xx_init (mqdata)) {
1157 printk (KERN_ERR "MediaQ device initialization failed!\n");
1158 return -ENODEV;
1159 }
1161 mqdata->irq_nr = resource[3].start;
1162 mqdata->base.set_GPIO = mq_set_GPIO;
1163 mqdata->base.get_GPIO = mq_get_GPIO;
1164 mqdata->base.set_power = mq_set_power;
1165 mqdata->base.get_power = mq_get_power;
1166 mqdata->base.alloc = mq_alloc;
1167 mqdata->base.free = mq_free;
1169 /* Initialize memory manager */
1170 spin_lock_init (&mqdata->mem_lock);
1171 mqdata->nfreeblocks = 1;
1172 mqdata->maxfreeblocks = MEMBLOCK_MINCOUNT;
1173 mqdata->freelist = kmalloc (MEMBLOCK_MINCOUNT * sizeof (struct mq_freemem_list),
1174 GFP_KERNEL);
1175 mqdata->freelist [0].addr = 0;
1176 mqdata->freelist [0].size = MQ11xx_FB_SIZE;
1178 #if defined MQ_IRQ_MULTIPLEX
1179 if ((mqdata->irq_nr != -1) && mq_irq_init (mqdata))
1180 goto err4;
1181 #endif
1183 for (i = j = 0; j < MQ_SUBDEVS_COUNT; i++) {
1184 struct platform_device *sdev = &mqdata->devices[i];
1185 const struct mq_block *blk = &mq_blocks[j];
1186 struct resource *res;
1187 int old_j, k;
1189 memset (sdev, 0, sizeof (struct platform_device));
1190 sdev->id = blk->id.id; /* placeholder id */
1191 sdev->name = blk->name;
1192 sdev->dev.parent = dev;
1193 sdev->dev.release = mq_release;
1194 sdev->dev.platform_data = &mqdata->base;
1196 /* Count number of resources */
1197 sdev->num_resources = 2;
1198 old_j = j;
1199 while (mq_blocks [++j].id.id == sdev->id)
1200 sdev->num_resources += 2;
1202 res = kmalloc (sdev->num_resources * sizeof (struct resource), GFP_KERNEL);
1203 sdev->resource = res;
1204 memset (res, 0, sdev->num_resources * sizeof (struct resource));
1206 for (j = old_j, k = 0; mq_blocks [j].id.id == sdev->id; j++) {
1207 blk = &mq_blocks[j];
1208 res[k].start = resource[2].start + blk->start;
1209 res[k].end = resource[2].start + blk->end;
1210 res[k].parent = &resource[2];
1211 res[k++].flags = IORESOURCE_MEM;
1212 res[k].start = (unsigned)mqdata->base.regs + blk->start;
1213 res[k].end = (unsigned)mqdata->base.regs + blk->end;
1214 res[k++].flags = 0;
1215 }
1217 mqdata->power_on [i] = 1;;
1218 }
1220 /* Second pass */
1221 chipmask = 1 << mqdata->base.chip;
1222 for (i = j = k = 0; j < MQ_SUBDEVS_COUNT; i++) {
1223 struct platform_device *sdev = &mqdata->devices[i];
1224 const struct mq_block *blk = &mq_blocks[j];
1226 while (mq_blocks [++j].id.id == sdev->id)
1227 ;
1229 /* Power off all subdevices */
1230 mq_power_off (&mqdata->base, sdev->id);
1232 if (!(blk->mask & chipmask))
1233 continue;
1235 sdev->id = instance;
1236 rc = platform_device_register (sdev);
1237 if (rc) {
1238 printk (KERN_ERR "Failed to register MediaQ subdevice `%s', code %d\n",
1239 blk->name, rc);
1240 goto err5;
1241 }
1242 }
1244 printk (KERN_INFO "MediaQ %s chip detected, ", mqdata->base.chipname);
1245 if (mqdata->base.irq_base)
1246 printk ("base IRQ %d\n", mqdata->base.irq_base);
1247 else
1248 printk ("\n");
1250 spin_lock (&mq_device_list_lock);
1251 for (i = 0; i < MAX_MQ11XX_DEVICES; i++)
1252 if (!mq_device_list [i]) {
1253 mq_device_list [i] = &mqdata->base;
1254 break;
1255 }
1256 spin_unlock (&mq_device_list_lock);
1258 return 0;
1260 err5: while (--i >= 0) {
1261 platform_device_unregister (&mqdata->devices[i]);
1262 kfree (mqdata->devices[i].resource);
1263 }
1265 #if defined MQ_IRQ_MULTIPLEX
1266 if (mqdata->irq_nr != -1)
1267 mq_irq_free (mqdata);
1268 #endif
1269 err4: kfree (mqdata->devices);
1270 err3: iounmap ((void *)mqdata->base.regs);
1271 err2: iounmap ((void *)mqdata->base.ram);
1272 err1: iounmap (mqdata->base.gfxram);
1273 err0: kfree (mqdata);
1275 printk (KERN_ERR "MediaQ base SoC driver initialization failed\n");
1277 return -ENOMEM;
1278 }
1280 static int
1281 mq_finalize (struct device *dev)
1282 {
1283 int i;
1284 struct mq_data *mqdata = dev_get_drvdata (dev);
1286 spin_lock (&mq_device_list_lock);
1287 for (i = 0; i < MAX_MQ11XX_DEVICES; i++)
1288 if (mq_device_list [i] == &mqdata->base) {
1289 mq_device_list [i] = NULL;
1290 break;
1291 }
1292 spin_unlock (&mq_device_list_lock);
1294 for (i = 0; i < mqdata->ndevices; i++) {
1295 platform_device_unregister (&mqdata->devices[i]);
1296 kfree (mqdata->devices[i].resource);
1297 }
1299 #if defined MQ_IRQ_MULTIPLEX
1300 if (mqdata->irq_nr != -1)
1301 mq_irq_free (mqdata);
1302 #endif
1304 kfree (mqdata->devices);
1306 iounmap ((void *)mqdata->base.regs);
1307 iounmap ((void *)mqdata->base.ram);
1308 iounmap (mqdata->base.gfxram);
1310 kfree (mqdata);
1312 return 0;
1313 }
1315 /* This is the platform device handler. If MediaQ is connected to a different
1316 * bus type (e.g. PCI) a similar device_driver structure should be registered
1317 * for that bus. For now this is not implemented.
1318 */
1320 static int
1321 mq_probe (struct device *dev)
1322 {
1323 struct platform_device *pdev = to_platform_device (dev);
1324 return mq_initialize (dev, pdev->num_resources, pdev->resource,
1325 pdev->id);
1326 }
1328 static int
1329 mq_remove (struct device *dev)
1330 {
1331 return mq_finalize (dev);
1332 }
1334 static void
1335 mq_shutdown (struct device *dev)
1336 {
1337 //struct mq_data *mqdata = dev_get_drvdata (dev);
1338 }
1340 static int
1341 mq_suspend (struct device *dev, pm_message_t state)
1342 {
1343 //struct mq_data *mqdata = dev_get_drvdata (dev);
1344 return 0;
1345 }
1347 static int
1348 mq_resume (struct device *dev)
1349 {
1350 //struct mq_data *mqdata = dev_get_drvdata (dev);
1351 return 0;
1352 }
1354 static struct device_driver mq_device_driver = {
1355 .name = "mq11xx",
1356 .bus = &platform_bus_type,
1358 .probe = mq_probe,
1359 .remove = mq_remove,
1360 .suspend = mq_suspend,
1361 .resume = mq_resume,
1362 .shutdown = mq_shutdown,
1363 };
1365 static int __init
1366 mq_base_init (void)
1367 {
1368 return driver_register (&mq_device_driver);
1369 }
1371 static void __exit
1372 mq_base_exit (void)
1373 {
1374 driver_unregister (&mq_device_driver);
1375 }
1377 #ifdef MODULE
1378 module_init (mq_base_init);
1379 #else /* start early for dependencies */
1380 subsys_initcall (mq_base_init);
1381 #endif
1382 module_exit (mq_base_exit)
1384 MODULE_AUTHOR("Andrew Zabolotny <anpaza@mail.ru>");
1385 MODULE_DESCRIPTION("MediaQ 1100/1132 base SoC support");
1386 MODULE_LICENSE("GPL");