2 * drivers/misc/soc/mq11xx.h
4 * Copyright (C) 2003 Andrew Zabolotny <anpaza@mail.ru>
5 * Portions copyright (C) 2003 Keith Packard
7 * This file contains some definitions for the MediaQ 1100/1132.
8 * These definitions are made public because drivers for
9 * MediaQ subdevices need them.
12 #ifndef _PLATFORM_MEDIAQ11XX
13 #define _PLATFORM_MEDIAQ11XX
15 #define MQ11xx_REG_SIZE (8*1024)
16 #define MQ11xx_FB_SIZE (256*1024)
17 #define MQ11xx_NUMIRQS 20
19 /* Interrupt handling for the MediaQ chip is quite tricky.
20 * The chip has 20 internal interrupt sources (numbered from 0 to 19,
21 * see the constants below) which are demultiplexed to a single output
22 * pin which is usually connected to a single IRQ on the mainboard.
23 * Thus the driver has to multiplex it somehow again into twenty
26 * Unfortunately, the mechanisms required for this are missing (as of today)
27 * on all platforms except ARM. Let's hope one day they will be supported on
28 * all platforms; for now no platforms except ARM supports MediaQ interrupts.
30 * The following contants are IRQ offsets relative to the base IRQ number
31 * (driver allocates a range of IRQs).
34 #if defined CONFIG_ARM
35 # define MQ_IRQ_MULTIPLEX
38 #define IRQ_MQ_VSYNC_RISING 0
39 #define IRQ_MQ_VSYNC_FALLING 1
40 #define IRQ_MQ_VENABLE_RISING 2
41 #define IRQ_MQ_VENABLE_FALLING 3
42 #define IRQ_MQ_BUS_CYCLE_ABORT 4
43 #define IRQ_MQ_GPIO_0 5
44 #define IRQ_MQ_GPIO_1 6
45 #define IRQ_MQ_GPIO_2 7
46 #define IRQ_MQ_COMMAND_FIFO_HALF_EMPTY 8
47 #define IRQ_MQ_COMMAND_FIFO_EMPTY 9
48 #define IRQ_MQ_SOURCE_FIFO_HALF_EMPTY 10
49 #define IRQ_MQ_SOURCE_FIFO_EMPTY 11
50 #define IRQ_MQ_GRAPHICS_ENGINE_IDLE 12
51 #define IRQ_MQ_UHC_GLOBAL_SUSPEND_MODE 13
52 #define IRQ_MQ_UHC_REMOTE_WAKE_UP 14
57 #define IRQ_MQ_UDC_WAKE_UP 19
59 /* This union uses unnamed structs. This is a gcc extension, but what the
60 * hell, the kernel is not compilable by anything else anyway...
62 struct mediaq11xx_regs
{
64 * CPU Interface (CC) Module 0x000
69 #define MQ_CPU_CONTROL_MIU_READ_REQUEST_GENERATOR_ON (1 << 0)
70 #define MQ_CPU_CONTROL_DISBABLE_FB_READ_CACHE (1 << 1)
71 #define MQ_CPU_CONTROL_ENABLE_CLKRUN (1 << 3)
72 #define MQ_CPU_CONTROL_GPIO_SOURCE_DATA_SELECT (3 << 4)
73 #define MQ_CPU_CONTROL_CPU_INTERFACE_GPIO_DATA (3 << 6)
75 #define MQ_CPU_COMMAND_FIFO(s) (((s) >> 0) & 0x1f)
76 #define MQ_CPU_SOURCE_FIFO(s) (((s) >> 8) & 0x1f)
77 #define MQ_CPU_GE_BUSY (1 << 16)
86 * Memory Interface Unit Controller 0x080
91 #define MQ_MIU_ENABLE (1 << 0)
92 #define MQ_MIU_RESET_ENABLE (1 << 1)
94 #define MQ_MIU_MEMORY_CLOCK_SOURCE_BUS (1 << 0)
95 #define MQ_MIU_MEMORY_CLOCK_DIVIDER (7 << 2)
96 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_1 (0 << 2)
97 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_1_5 (1 << 2)
98 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_2 (2 << 2)
99 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_2_5 (3 << 2)
100 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_3 (4 << 2)
101 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_4 (5 << 2)
102 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_5 (6 << 2)
103 #define MQ_MIU_MEMORY_CLOCK_DIVIDER_6 (7 << 2)
104 #define MQ_MIU_DISPLAY_BURST_MASK (3 << 5)
105 #define MQ_MIU_DISPLAY_BURST_COUNT_2 (0 << 5)
106 #define MQ_MIU_DISPLAY_BURST_COUNT_4 (1 << 5)
107 #define MQ_MIU_DISPLAY_BURST_COUNT_6 (2 << 5)
108 #define MQ_MIU_DISPLAY_BURST_COUNT_8 (3 << 5)
109 #define MQ_MIU_GRAPHICS_ENGINE_BURST_MASK (3 << 7)
110 #define MQ_MIU_GRAPHICS_ENGINE_BURST_COUNT_2 (0 << 7)
111 #define MQ_MIU_GRAPHICS_ENGINE_BURST_COUNT_4 (1 << 7)
112 #define MQ_MIU_GRAPHICS_ENGINE_BURST_COUNT_6 (2 << 7)
113 #define MQ_MIU_GRAPHICS_ENGINE_BURST_COUNT_8 (3 << 7)
114 #define MQ_MIU_CPU_BURST_MASK (3 << 9)
115 #define MQ_MIU_CPU_BURST_COUNT_2 (0 << 9)
116 #define MQ_MIU_CPU_BURST_COUNT_4 (1 << 9)
117 #define MQ_MIU_CPU_BURST_COUNT_6 (2 << 9)
118 #define MQ_MIU_CPU_BURST_COUNT_8 (3 << 9)
119 #define MQ_MIU_I2S_BURST_MASK (3 << 11)
120 #define MQ_MIU_I2S_BURST_COUNT_2 (0 << 11)
121 #define MQ_MIU_I2S_BURST_COUNT_4 (1 << 11)
122 #define MQ_MIU_I2S_BURST_COUNT_6 (2 << 11)
123 #define MQ_MIU_I2S_BURST_COUNT_8 (3 << 11)
124 #define MQ_MIU_UDC_BURST_MASK (3 << 13)
125 #define MQ_MIU_UDC_BURST_COUNT_2 (0 << 13)
126 #define MQ_MIU_UDC_BURST_COUNT_4 (1 << 13)
127 #define MQ_MIU_UDC_BURST_COUNT_6 (2 << 13)
128 #define MQ_MIU_UDC_BURST_COUNT_8 (3 << 13)
129 #define MQ_MIU_GCI_FIFO_THRESHOLD (0xf << 16)
130 #define MQ_MIU_GCI_FIFO_THRESHOLD_(v) ((v) << 16)
131 #define MQ_MIU_GRAPHICS_ENGINE_SRC_READ_THRESHOLD (7 << 20)
132 #define MQ_MIU_GRAPHICS_ENGINE_SRC_READ_THRESHOLD_(v) ((v) << 20)
133 #define MQ_MIU_GRAPHICS_ENGINE_DST_READ_THRESHOLD (7 << 23)
134 #define MQ_MIU_GRAPHICS_ENGINE_DST_READ_THRESHOLD_(v) ((v) << 23)
135 #define MQ_MIU_I2S_TRANSMIT_THRESHOLD (7 << 26)
136 #define MQ_MIU_I2S_TRANSMIT_THRESHOLD_(v) ((v) << 26)
137 u32 miu_test_control
;
145 * Interrupt Controller 0x100
150 #define MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE (1 << 0)
151 #define MQ_INTERRUPT_CONTROL_INTERRUPT_POLARITY (1 << 1)
152 #define MQ_INTERRUPT_CONTROL_GPIO_0_INTERRUPT_POLARITY (1 << 2)
153 #define MQ_INTERRUPT_CONTROL_GPIO_1_INTERRUPT_POLARITY (1 << 3)
154 #define MQ_INTERRUPT_CONTROL_GPIO_2_INTERRUPT_POLARITY (1 << 4)
156 #define MQ_INTERRUPT_MASK_VSYNC_RISING (1 << 0)
157 #define MQ_INTERRUPT_MASK_VSYNC_FALLING (1 << 1)
158 #define MQ_INTERRUPT_MASK_VENABLE_RISING (1 << 2)
159 #define MQ_INTERRUPT_MASK_VENABLE_FALLING (1 << 3)
160 #define MQ_INTERRUPT_MASK_BUS_CYCLE_ABORT (1 << 4)
161 #define MQ_INTERRUPT_MASK_GPIO_0 (1 << 5)
162 #define MQ_INTERRUPT_MASK_GPIO_1 (1 << 6)
163 #define MQ_INTERRUPT_MASK_GPIO_2 (1 << 7)
164 #define MQ_INTERRUPT_MASK_COMMAND_FIFO_HALF_EMPTY (1 << 8)
165 #define MQ_INTERRUPT_MASK_COMMAND_FIFO_EMPTY (1 << 9)
166 #define MQ_INTERRUPT_MASK_SOURCE_FIFO_HALF_EMPTY (1 << 10)
167 #define MQ_INTERRUPT_MASK_SOURCE_FIFO_EMPTY (1 << 11)
168 #define MQ_INTERRUPT_MASK_GRAPHICS_ENGINE_IDLE (1 << 12)
169 #define MQ_INTERRUPT_MASK_UHC_GLOBAL_SUSPEND_MODE (1 << 13)
170 #define MQ_INTERRUPT_MASK_UHC_REMOTE_WAKE_UP (1 << 14)
171 #define MQ_INTERRUPT_MASK_UHC (1 << 15)
172 #define MQ_INTERRUPT_MASK_UDC (1 << 16)
173 #define MQ_INTERRUPT_MASK_I2S (1 << 17)
174 #define MQ_INTERRUPT_MASK_SPI (1 << 18)
175 #define MQ_INTERRUPT_MASK_UDC_WAKE_UP (1 << 19)
176 u32 interrupt_status
;
177 #define MQ_INTERRUPT_STATUS_VSYNC_RISING (1 << 0)
178 #define MQ_INTERRUPT_STATUS_VSYNC_FALLING (1 << 1)
179 #define MQ_INTERRUPT_STATUS_VENABLE_RISING (1 << 2)
180 #define MQ_INTERRUPT_STATUS_VENABLE_FALLING (1 << 3)
181 #define MQ_INTERRUPT_STATUS_BUS_CYCLE_ABORT (1 << 4)
182 #define MQ_INTERRUPT_STATUS_GPIO_0 (1 << 5)
183 #define MQ_INTERRUPT_STATUS_GPIO_1 (1 << 6)
184 #define MQ_INTERRUPT_STATUS_GPIO_2 (1 << 7)
185 #define MQ_INTERRUPT_STATUS_COMMAND_FIFO_HALF_EMPTY (1 << 8)
186 #define MQ_INTERRUPT_STATUS_COMMAND_FIFO_EMPTY (1 << 9)
187 #define MQ_INTERRUPT_STATUS_SOURCE_FIFO_HALF_EMPTY (1 << 10)
188 #define MQ_INTERRUPT_STATUS_SOURCE_FIFO_EMPTY (1 << 11)
189 #define MQ_INTERRUPT_STATUS_GRAPHICS_ENGINE_IDLE (1 << 12)
190 #define MQ_INTERRUPT_STATUS_UHC_GLOBAL_SUSPEND_MODE (1 << 13)
191 #define MQ_INTERRUPT_STATUS_UHC_REMOTE_WAKE_UP (1 << 14)
192 #define MQ_INTERRUPT_STATUS_UHC (1 << 15)
193 #define MQ_INTERRUPT_STATUS_UDC (1 << 16)
194 #define MQ_INTERRUPT_STATUS_I2S (1 << 17)
195 #define MQ_INTERRUPT_STATUS_SPI (1 << 18)
196 #define MQ_INTERRUPT_STATUS_UDC_WAKE_UP (1 << 19)
197 u32 interrupt_raw_status
;
198 #define MQ_INTERRUPT_RAWSTATUS_VSYNC (1 << 0)
199 #define MQ_INTERRUPT_RAWSTATUS_VENABLE (1 << 1)
200 #define MQ_INTERRUPT_RAWSTATUS_SCC (1 << 2)
201 #define MQ_INTERRUPT_RAWSTATUS_SPI (1 << 3)
202 #define MQ_INTERRUPT_RAWSTATUS_GPIO_0 (1 << 4)
203 #define MQ_INTERRUPT_RAWSTATUS_GPIO_1 (1 << 5)
204 #define MQ_INTERRUPT_RAWSTATUS_GPIO_2 (1 << 6)
205 #define MQ_INTERRUPT_RAWSTATUS_GRAPHICS_ENGINE_BUSY (1 << 8)
206 #define MQ_INTERRUPT_RAWSTATUS_SOURCE_FIFO_EMPTY (1 << 9)
207 #define MQ_INTERRUPT_RAWSTATUS_SOURCE_FIFO_HALF_EMPTY (1 << 10)
208 #define MQ_INTERRUPT_RAWSTATUS_COMMAND_FIFO_EMPTY (1 << 11)
209 #define MQ_INTERRUPT_RAWSTATUS_COMMAND_FIFO_HALF_EMPTY (1 << 12)
210 #define MQ_INTERRUPT_RAWSTATUS_UHC (1 << 13)
211 #define MQ_INTERRUPT_RAWSTATUS_UHC_GLOBAL_SUSPEND (1 << 14)
212 #define MQ_INTERRUPT_RAWSTATUS_UHC_REMOTE_WAKE_UP (1 << 15)
213 #define MQ_INTERRUPT_RAWSTATUS_UDC (1 << 16)
214 #define MQ_INTERRUPT_RAWSTATUS_UDC_WAKE_UP (1 << 17)
220 * Graphics Controller 0x180
225 #define MQ_GC_CONTROL_ENABLE (1 << 0)
226 #define MQ_GC_HORIZONTAL_COUNTER_RESET (1 << 1)
227 #define MQ_GC_VERTICAL_COUNTER_RESET (1 << 2)
228 #define MQ_GC_IMAGE_WINDOW_ENABLE (1 << 3)
229 #define MQ_GC_DEPTH (0xf << 4)
230 #define MQ_GC_DEPTH_PSEUDO_1 (0x0 << 4)
231 #define MQ_GC_DEPTH_PSEUDO_2 (0x1 << 4)
232 #define MQ_GC_DEPTH_PSEUDO_4 (0x2 << 4)
233 #define MQ_GC_DEPTH_PSEUDO_8 (0x3 << 4)
234 #define MQ_GC_DEPTH_GRAY_1 (0x8 << 4)
235 #define MQ_GC_DEPTH_GRAY_2 (0x9 << 4)
236 #define MQ_GC_DEPTH_GRAY_4 (0xa << 4)
237 #define MQ_GC_DEPTH_GRAY_8 (0xb << 4)
238 #define MQ_GC_DEPTH_TRUE_16 (0xc << 4)
239 #define MQ_GC_HARDWARE_CURSOR_ENABLE (1 << 8)
240 #define MQ_GC_DOUBLE_BUFFER_CONTROL (3 << 10)
241 #define MQ_GC_X_SCANNING_DIRECTION (1 << 12)
242 #define MQ_GC_LINE_SCANNING_DIRECTION (1 << 13)
243 #define MQ_GC_HORIZONTAL_DOUBLING (1 << 14)
244 #define MQ_GC_VERTICAL_DOUBLING (1 << 15)
245 #define MQ_GC_GRCLK_SOURCE (3 << 16)
246 #define MQ_GC_GRCLK_SOURCE_BUS (0 << 16)
247 #define MQ_GC_GRCLK_SOURCE_FIRST (1 << 16)
248 #define MQ_GC_GRCLK_SOURCE_SECON (2 << 16)
249 #define MQ_GC_GRCLK_SOURCE_THIRD (3 << 16)
250 #define MQ_GC_ENABLE_TEST_MODE (1 << 18)
251 #define MQ_GC_ENABLE_POLY_SI_TFT (1 << 19)
252 #define MQ_GC_GMCLK_FIRST_DIVISOR (7 << 20)
253 #define MQ_GC_GMCLK_FIRST_DIVISOR_1 (0 << 20)
254 #define MQ_GC_GMCLK_FIRST_DIVISOR_1_5 (1 << 20)
255 #define MQ_GC_GMCLK_FIRST_DIVISOR_2_5 (2 << 20)
256 #define MQ_GC_GMCLK_FIRST_DIVISOR_3_5 (3 << 20)
257 #define MQ_GC_GMCLK_FIRST_DIVISOR_4_5 (4 << 20)
258 #define MQ_GC_GMCLK_FIRST_DIVISOR_5_5 (5 << 20)
259 #define MQ_GC_GMCLK_FIRST_DIVISOR_6_5 (6 << 20)
260 #define MQ_GC_GMCLK_SECOND_DIVISOR (0xf << 24)
261 #define MQ_GC_GMCLK_SECOND_DIVISOR_(v) ((v) << 24)
262 #define MQ_GC_SHARP_160x160_HR_TFT_ENABLE (1 << 31)
263 u32 power_sequencing
;
264 #define MQ_GC_POWER_UP_INTERVAL (7 << 0)
265 #define MQ_GC_POWER_UP_INTERVAL_1 (0 << 0)
266 #define MQ_GC_POWER_UP_INTERVAL_2 (1 << 0)
267 #define MQ_GC_POWER_UP_INTERVAL_4 (2 << 0)
268 #define MQ_GC_POWER_UP_INTERVAL_8 (3 << 0)
269 #define MQ_GC_POWER_UP_INTERVAL_16 (4 << 0)
270 #define MQ_GC_POWER_UP_INTERVAL_32 (5 << 0)
271 #define MQ_GC_POWER_UP_INTERVAL_48 (6 << 0)
272 #define MQ_GC_POWER_UP_INTERVAL_64 (7 << 0)
273 #define MQ_GC_FAST_POWER_UP (1 << 3)
274 #define MQ_GC_POWER_DOWN_INTERVAL (1 << 4)
275 #define MQ_GC_POWER_DOWN_INTERVAL_1 (0 << 4)
276 #define MQ_GC_POWER_DOWN_INTERVAL_2 (1 << 4)
277 #define MQ_GC_POWER_DOWN_INTERVAL_4 (2 << 4)
278 #define MQ_GC_POWER_DOWN_INTERVAL_8 (3 << 4)
279 #define MQ_GC_POWER_DOWN_INTERVAL_16 (4 << 4)
280 #define MQ_GC_POWER_DOWN_INTERVAL_32 (5 << 4)
281 #define MQ_GC_POWER_DOWN_INTERVAL_48 (6 << 4)
282 #define MQ_GC_POWER_DOWN_INTERVAL_64 (7 << 4)
283 #define MQ_GC_FAST_POWER_DOWN (1 << 7)
284 u32 horizontal_display
;
285 #define MQ_GC_HORIZONTAL_DISPLAY_TOTAL (0x7ff << 0)
286 #define MQ_GC_HORIZONTAL_DISPLAY_TOTAL_(s) ((s) << 0)
287 #define MQ_GC_HORIZONTAL_DISPLAY_END (0x7ff << 16)
288 #define MQ_GC_HORIZONTAL_DISPLAY_END_(s) ((s) << 16)
289 u32 vertical_display
;
290 #define MQ_GC_VERTICAL_DISPLAY_TOTAL (0x3ff << 0)
291 #define MQ_GC_VERTICAL_DISPLAY_TOTAL_(s) ((s) << 0)
292 #define MQ_GC_VERTICAL_DISPLAY_END (0x3ff << 16)
293 #define MQ_GC_VERTICAL_DISPLAY_END_(s) ((s) << 16)
295 #define MQ_GC_HORIZONTAL_SYNC_START (0x7ff << 0)
296 #define MQ_GC_HORIZONTAL_SYNC_START_(s) ((s) << 0)
297 #define MQ_GC_HORIZONTAL_SYNC_END (0x7ff << 16)
298 #define MQ_GC_HORIZONTAL_SYNC_END_(s) ((s) << 16)
300 #define MQ_GC_VERTICAL_SYNC_START (0x3ff << 0)
301 #define MQ_GC_VERTICAL_SYNC_START_(s) ((s) << 0)
302 #define MQ_GC_VERTICAL_SYNC_END (0x3ff << 16)
303 #define MQ_GC_VERTICAL_SYNC_END_(s) ((s) << 16)
304 u32 horizontal_counter_init
; /* set to 0 */
305 u32 vertical_counter_init
; /* set to 0 */
306 u32 horizontal_window
;
307 #define MQ_GC_HORIZONTAL_WINDOW_START (0x7ff << 0)
308 #define MQ_GC_HORIZONTAL_WINDOW_START_(s) ((s) << 0)
309 #define MQ_GC_HORIZONTAL_WINDOW_WIDTH (0x7ff << 16)
310 #define MQ_GC_HORIZONTAL_WINDOW_WIDTH_(s) ((s) << 16)
312 #define MQ_GC_VERTICAL_WINDOW_START (0x3ff << 0)
313 #define MQ_GC_VERTICAL_WINDOW_START_(s) ((s) << 0)
314 #define MQ_GC_VERTICAL_WINDOW_HEIGHT (0x3ff << 16)
315 #define MQ_GC_VERTICAL_WINDOW_HEIGHT_(s) ((s) << 16)
318 #define MQ_GC_LINE_CLOCK_START (0x7ff << 0)
319 #define MQ_GC_LINE_CLOCK_START_(s) ((s) << 0)
320 #define MQ_GC_LINE_CLOCK_END (0x7ff << 16)
321 #define MQ_GC_LINE_CLOCK_END_(s) ((s) << 16)
322 u32 window_start_address
;
323 u32 alternate_window_start_address
;
327 #define MQ_GC_HORIZONTAL_CURSOR_START (0x7ff << 0)
328 #define MQ_GC_HORIZONTAL_CURSOR_START_(s) ((s) << 0)
329 #define MQ_GC_VERTICAL_CURSOR_START (0x3ff << 16)
330 #define MQ_GC_VERTICAL_CURSOR_START_(s) ((s) << 16)
331 u32 cursor_start_address
;
332 #define MQ_GC_CURSOR_START_ADDRESS (0xff << 0)
333 #define MQ_GC_CURSOR_START_ADDRESS_(s) ((s) << 0)
334 #define MQ_GC_HORIZONTAL_CURSOR_OFFSET (0x3f << 16)
335 #define MQ_GC_HORIZONTAL_CURSOR_OFFSET_(s) ((s) << 16)
336 #define MQ_GC_VERTICAL_CURSOR_OFFSET (0x3f << 24)
337 #define MQ_GC_VERTICAL_CURSOR_OFFSET_(s) ((s) << 24)
338 u32 cursor_foreground
;
339 u32 cursor_background
;
340 u32 reserved_50_64
[6];
341 u32 frame_clock_control
;
342 #define MQ_GC_FRAME_CLOCK_START (0x3ff << 0)
343 #define MQ_GC_FRAME_CLOCK_START_(s) ((s) << 0)
344 #define MQ_GC_FRAME_CLOCK_END (0x3ff << 16)
345 #define MQ_GC_FRAME_CLOCK_END_(s) ((s) << 16)
347 u32 horizonal_parameter
;
348 u32 vertical_parameter
;
349 u32 window_line_start_address
;
350 u32 cursor_line_start_address
;
356 * Graphics Engine 0x200
363 * Synchronous Serial Controller 0x280
370 * Serial Peripheral Interface 0x300
388 * Device Configuration Space 0x380
393 #define MQ_CONFIG_LITTLE_ENDIAN_ENABLE (1 << 0)
394 #define MQ_CONFIG_BYTE_SWAPPING (1 << 1)
396 #define MQ_CONFIG_18_OSCILLATOR (3 << 0)
397 #define MQ_CONFIG_18_OSCILLATOR_DISABLED (0 << 0)
398 #define MQ_CONFIG_18_OSCILLATOR_OSCFO (1 << 0)
399 #define MQ_CONFIG_18_OSCILLATOR_INTERNAL (3 << 0)
400 #define MQ_CONFIG_CPU_CLOCK_DIVISOR (1 << 8)
401 #define MQ_CONFIG_DTACK_CONTROL (1 << 9)
402 #define MQ_CONFIG_INTERFACE_SYNCHRONIZER_CONTROL (1 << 10)
403 #define MQ_CONFIG_WRITE_DATA_LATCH (1 << 11)
404 #define MQ_CONFIG_CPU_TEST_MODE (1 << 12)
405 #define MQ_CONFIG_SOFTWARE_CHIP_RESET (1 << 16)
406 #define MQ_CONFIG_WEAK_PULL_DOWN_FMOD (1 << 28)
407 #define MQ_CONFIG_WEAK_PULL_DOWN_FLCLK (1 << 29)
408 #define MQ_CONFIG_WEAK_PULL_DOWN_PWM0 (1 << 30)
409 #define MQ_CONFIG_WEAK_PULL_DOWN_PWM1 (1 << 31)
411 #define MQ_CONFIG_CC_MODULE_ENABLE (1 << 0)
413 #define MQ_CONFIG_BUS_INTERFACE_MODE (0x7f << 0)
414 #define MQ_CONFIG_BUS_INTERFACE_MODE_SH7750 (0x01 << 0)
415 #define MQ_CONFIG_BUS_INTERFACE_MODE_SH7709 (0x02 << 0)
416 #define MQ_CONFIG_BUS_INTERFACE_MODE_VR4111 (0x04 << 0)
417 #define MQ_CONFIG_BUS_INTERFACE_MODE_SA1110 (0x08 << 0)
418 #define MQ_CONFIG_BUS_INTERFACE_MODE_PCI (0x20 << 0)
419 #define MQ_CONFIG_BUS_INTERFACE_MODE_DRAGONBALL_EZ (0x40 << 0)
421 #define MQ_CONFIG_GE_FORCE_BUSY_GLOBAL (1 << 0)
422 #define MQ_CONFIG_GE_FORCE_BUSY_LOCAL (1 << 1)
423 #define MQ_CONFIG_GE_CLOCK_SELECT (1 << 2)
424 #define MQ_CONFIG_GE_CLOCK_DIVIDER (7 << 3)
425 #define MQ_CONFIG_GE_CLOCK_DIVIDER_1 (0 << 3)
426 #define MQ_CONFIG_GE_CLOCK_DIVIDER_1_5 (1 << 3)
427 #define MQ_CONFIG_GE_CLOCK_DIVIDER_2 (2 << 3)
428 #define MQ_CONFIG_GE_CLOCK_DIVIDER_2_5 (3 << 3)
429 #define MQ_CONFIG_GE_CLOCK_DIVIDER_3 (4 << 3)
430 #define MQ_CONFIG_GE_CLOCK_DIVIDER_4 (5 << 3)
431 #define MQ_CONFIG_GE_CLOCK_DIVIDER_5 (6 << 3)
432 #define MQ_CONFIG_GE_CLOCK_DIVIDER_6 (7 << 3)
433 #define MQ_CONFIG_GE_FIFO_RESET (1 << 6)
434 #define MQ_CONFIG_GE_SOURCE_FIFO_RESET (1 << 7)
435 #define MQ_CONFIG_USB_SE0_DETECT (1 << 8)
436 #define MQ_CONFIG_UHC_DYNAMIC_POWER (1 << 9)
437 #define MQ_CONFIG_USB_COUNTER_SCALE_ENABLE (1 << 10)
438 #define MQ_CONFIG_UHC_READ_TEST_ENABLE (1 << 11)
439 #define MQ_CONFIG_UHC_TEST_MODE_DATA (0xf << 12)
440 #define MQ_CONFIG_UHC_TRANSCEIVER_TEST_ENABLE (1 << 16)
441 #define MQ_CONFIG_UHC_OVER_CURRENT_DETECT (1 << 17)
442 #define MQ_CONFIG_UDC_DYNAMIC_POWER_ENABLE (1 << 18)
443 #define MQ_CONFIG_UHC_TRANSCEIVER_ENABLE (1 << 19)
444 #define MQ_CONFIG_UDC_TRANSCEIVER_ENABLE (1 << 20)
445 #define MQ_CONFIG_USB_TEST_VECTOR_GENERATION_ENABLE (1 << 21)
447 #define MQ_CONFIG_GE_ENABLE (1 << 0)
448 #define MQ_CONFIG_UHC_CLOCK_ENABLE (1 << 1)
449 #define MQ_CONFIG_UDC_CLOCK_ENABLE (1 << 2)
458 * PCI Configuration Header
464 #define MQ_PCI_VENDORID 0x4d51
466 // This is a wild guess
467 #define MQ_PCI_DEVICEID_1100 0x0100
468 #define MQ_PCI_DEVICEID_1132 0x0120
469 // No confirmation of this IDs yet
470 #define MQ_PCI_DEVICEID_1168 0x0168
471 // No confirmation of this IDs yet
472 #define MQ_PCI_DEVICEID_1178 0x0178
473 #define MQ_PCI_DEVICEID_1188 0x0188
485 u16 subsystem_vendor_id
;
496 u16 power_management_capabilities
;
497 u16 power_management_control_status
;
504 * USB Host Controller (0x500)
511 * Flat Panel Controller (0x600)
516 #define MQ_FP_PANEL_TYPE (0xf << 0)
517 #define MQ_FP_PANEL_TYPE_TFT (0x0 << 0)
518 #define MQ_FP_PANEL_TYPE_STN (0x4 << 0)
519 #define MQ_FP_MONOCHROME_SELECT (1 << 4)
520 #define MQ_FP_FLAT_PANEL_INTERFACE (7 << 5)
521 #define MQ_FP_FLAT_PANEL_INTERFACE_4_BIT (0 << 5)
522 #define MQ_FP_FLAT_PANEL_INTERFACE_6_BIT (1 << 5)
523 #define MQ_FP_FLAT_PANEL_INTERFACE_8_BIT (2 << 5)
524 #define MQ_FP_FLAT_PANEL_INTERFACE_16_BIT (3 << 5)
525 #define MQ_FP_DITHER_PATTERN (3 << 8)
526 #define MQ_FP_DITHER_PATTERN_1 (1 << 8)
527 #define MQ_FP_DITHER_BASE_COLOR (7 << 12)
528 #define MQ_FP_DITHER_BASE_COLOR_DISABLE (7 << 12)
529 #define MQ_FP_DITHER_BASE_COLOR_3_BITS (3 << 12)
530 #define MQ_FP_DITHER_BASE_COLOR_4_BITS (4 << 12)
531 #define MQ_FP_DITHER_BASE_COLOR_5_BITS (5 << 12)
532 #define MQ_FP_DITHER_BASE_COLOR_6_BITS (6 << 12)
533 #define MQ_FP_ALTERNATE_WINDOW_CONTROL (1 << 15)
534 #define MQ_FP_FRC_CONTROL (3 << 16)
535 #define MQ_FP_FRC_CONTROL_2_LEVEL (0 << 16)
536 #define MQ_FP_FRC_CONTROL_4_LEVEL (1 << 16)
537 #define MQ_FP_FRC_CONTROL_8_LEVEL (2 << 16)
538 #define MQ_FP_FRC_CONTROL_16_LEVEL (3 << 16)
539 #define MQ_FP_POLY_SI_TFT_ENABLE (1 << 19)
540 #define MQ_FP_POLY_SI_TFT_FIRST_LINE (1 << 20)
541 #define MQ_FP_POLY_SI_TFT_DISPLAY_DATA_CONTROL (1 << 21)
542 #define MQ_FP_APP_NOTE_SAYS_SET_THIS (1 << 22)
544 #define MQ_FP_DISABLE_FLAT_PANEL_PINS (1 << 0)
545 #define MQ_FP_DISPLAY_ENABLE (1 << 2)
546 #define MQ_FP_AC_MODULATION_ENABLE (1 << 3)
547 #define MQ_FP_PWM_CLOCK_ENABLE (1 << 5)
548 #define MQ_FP_TFT_SHIFT_CLOCK_SELECT (1 << 6)
549 #define MQ_FP_SHIFT_CLOCK_MASK (1 << 7)
550 #define MQ_FP_FHSYNC_CONTROL (1 << 8)
551 #define MQ_FP_STN_SHIFT_CLOCK_CONTROL (1 << 9)
552 #define MQ_FP_STN_EXTRA_LP_ENABLE (1 << 10)
553 #define MQ_FP_TFT_DISPLAY_ENABLE_SELECT (3 << 12)
554 #define MQ_FP_TFT_DISPLAY_ENABLE_SELECT_00 (0 << 12)
555 #define MQ_FP_TFT_DISPLAY_ENABLE_SELECT_01 (1 << 12)
556 #define MQ_FP_TFT_DISPLAY_ENABLE_SELECT_10 (2 << 12)
557 #define MQ_FP_TFT_DISPLAY_ENABLE_SELECT_11 (3 << 12)
558 #define MQ_FP_TFT_HORIZONTAL_SYNC_SELECT (3 << 14)
559 #define MQ_FP_TFT_HORIZONTAL_SYNC_SELECT_00 (0 << 14)
560 #define MQ_FP_TFT_HORIZONTAL_SYNC_SELECT_01 (1 << 14)
561 #define MQ_FP_TFT_HORIZONTAL_SYNC_SELECT_10 (2 << 14)
562 #define MQ_FP_TFT_HORIZONTAL_SYNC_SELECT_11 (3 << 14)
563 #define MQ_FP_TFT_VERTICAL_SYNC_SELECT (3 << 16)
564 #define MQ_FP_TFT_VERTICAL_SYNC_SELECT_00 (0 << 16)
565 #define MQ_FP_TFT_VERTICAL_SYNC_SELECT_01 (1 << 16)
566 #define MQ_FP_TFT_VERTICAL_SYNC_SELECT_10 (2 << 16)
567 #define MQ_FP_TFT_VERTICAL_SYNC_SELECT_11 (3 << 16)
568 #define MQ_FP_LINE_CLOCK_CONTROL (1 << 18)
569 #define MQ_FP_ALTERNATE_LINE_CLOCK_CONTROL (1 << 19)
570 #define MQ_FP_FMOD_CLOCK_CONTROL (1 << 20)
571 #define MQ_FP_FMOD_FRAME_INVERSION (1 << 21)
572 #define MQ_FP_FMOD_FREQUENCY_CONTROL (1 << 22)
573 #define MQ_FP_FMOD_SYNCHRONOUS_RESET (1 << 23)
574 #define MQ_FP_SHIFT_CLOCK_DELAY (7 << 24)
575 #define MQ_FP_EXTENDED_LINE_CLOCK_CONTROL (1 << 27)
578 #define MQ_FP_ENVDD (1 << 0)
579 #define MQ_FP_ENVEE (1 << 1)
580 #define MQ_FP_FD2 (1 << 2)
581 #define MQ_FP_FD3 (1 << 3)
582 #define MQ_FP_FD4 (1 << 4)
583 #define MQ_FP_FD5 (1 << 5)
584 #define MQ_FP_FD6 (1 << 6)
585 #define MQ_FP_FD7 (1 << 7)
586 #define MQ_FP_FD10 (1 << 10)
587 #define MQ_FP_FD11 (1 << 11)
588 #define MQ_FP_FD12 (1 << 12)
589 #define MQ_FP_FD13 (1 << 13)
590 #define MQ_FP_FD14 (1 << 14)
591 #define MQ_FP_FD15 (1 << 15)
592 #define MQ_FP_FD18 (1 << 18)
593 #define MQ_FP_FD19 (1 << 19)
594 #define MQ_FP_FD20 (1 << 20)
595 #define MQ_FP_FD21 (1 << 21)
596 #define MQ_FP_FD22 (1 << 22)
597 #define MQ_FP_FD23 (1 << 23)
598 #define MQ_FP_FSCLK (1 << 24)
599 #define MQ_FP_FDE (1 << 25)
600 #define MQ_FP_FHSYNC (1 << 26)
601 #define MQ_FP_FVSYNC (1 << 27)
602 #define MQ_FP_FMOD (1 << 28)
603 #define MQ_FP_FLCLK (1 << 29)
604 #define MQ_FP_PWM0 (1 << 30)
605 #define MQ_FP_PWM1 (1 << 31)
606 u32 stn_panel_control
;
607 u32 polarity_control
;
608 u32 pin_output_select_0
;
609 u32 pin_output_select_1
;
612 u32 pin_weak_pull_down
;
613 u32 additional_pin_output_select
;
617 u32 pulse_width_mod_control
;
620 u32 pwm_clock_selector_c8
;
621 u32 pwm_clock_selector_cc
;
622 u32 pwm_clock_selector_d0
;
623 u32 pwm_clock_selector_d4
;
631 * Color Palette (0x800)
641 * Source FIFO Space (0xc00)
648 * USB Device Controller (0x1000)
653 #define MQ_UDC_SUSPEND_ENABLE (1 << 0)
654 #define MQ_UDC_REMOTEHOST_WAKEUP_ENABLE (1 << 3)
655 #define MQ_UDC_EP2_ISOCHRONOUS (1 << 5)
656 #define MQ_UDC_EP3_ISOCHRONOUS (1 << 6)
657 #define MQ_UDC_WAKEUP_USBHOST (1 << 8)
658 #define MQ_UDC_IEN_SOF (1 << 16)
659 #define MQ_UDC_IEN_EP0_TX (1 << 17)
660 #define MQ_UDC_IEN_EP0_RX (1 << 18)
661 #define MQ_UDC_IEN_EP1_TX (1 << 19)
662 #define MQ_UDC_IEN_EP2_TX_EOT (1 << 20)
663 #define MQ_UDC_IEN_EP3_RX_EOT (1 << 21)
664 #define MQ_UDC_IEN_DMA_TX (1 << 22)
665 #define MQ_UDC_IEN_DMA_RX (1 << 23)
666 #define MQ_UDC_IEN_DMA_RX_EOT (1 << 24)
667 #define MQ_UDC_IEN_GLOBAL_SUSPEND (1 << 25)
668 #define MQ_UDC_IEN_WAKEUP (1 << 26)
669 #define MQ_UDC_IEN_RESET (1 << 27)
671 #define MQ_UDC_ADDRESS_MASK (127)
673 #define MQ_UDC_FRAME_MASK (2047)
674 #define MQ_UDC_FRAME_CORRUPTED (1 << 11)
675 #define MQ_UDC_FRAME_NEW (1 << 12)
676 #define MQ_UDC_FRAME_MISSING (1 << 13)
677 #define MQ_UDC_EP2_DATA_MISSING (1 << 14)
678 #define MQ_UDC_EP3_DATA_MISSING (1 << 15)
680 #define MQ_UDC_TX_EDT (1 << 1)
681 #define MQ_UDC_STALL (1 << 2)
682 #define MQ_UDC_TX_PID_DATA1 (1 << 3)
683 #define MQ_UDC_TX_LAST_ENABLE_SHIFT (4)
684 #define MQ_UDC_TX_LAST_ENABLE_MASK (15 << MQ_UDC_TX_LAST_ENABLE_SHIFT)
685 #define MQ_UDC_TX_LAST_ENABLE(x) (((1 << (1 + (((x) - 1) & 3))) - 1) << MQ_UDC_TX_LAST_ENABLE_SHIFT)
686 #define MQ_UDC_CLEAR_FIFO (1 << 8)
688 #define MQ_UDC_ACK (1 << 0)
689 #define MQ_UDC_ERR (1 << 1)
690 #define MQ_UDC_TIMEOUT (1 << 2)
691 #define MQ_UDC_EOT (1 << 3)
692 #define MQ_UDC_FIFO_OVERRUN (1 << 6)
693 #define MQ_UDC_NAK (1 << 7)
694 #define MQ_UDC_FIFO_SHIFT (9)
695 #define MQ_UDC_FIFO_MASK (7)
696 #define MQ_UDC_FIFO(x) (((x) >> MQ_UDC_FIFO_SHIFT) & MQ_UDC_FIFO_MASK)
697 #define MQ_UDC_FIFO_DEPTH (4)
699 /* Most bitmasks shared with txstatus */
701 #define MQ_UDC_RX_PID_DATA1 (1 << 4)
702 #define MQ_UDC_RX_TOKEN_SETUP (1 << 5)
703 #define MQ_UDC_RX_VALID_BYTES_SHIFT (12)
704 #define MQ_UDC_RX_VALID_BYTES_MASK (3)
705 #define MQ_UDC_RX_VALID_BYTES(x) (((x) >> MQ_UDC_RX_VALID_BYTES_SHIFT) & MQ_UDC_RX_VALID_BYTES_MASK)
708 /* Most bitmasks shared with ep0txcontrol */
710 #define MQ_UDC_EP_ENABLE (1 << 0)
711 /* Most bitmasks shared with ep0txstatus */
714 /* Most bitmasks shared with ep0txcontrol */
716 #define MQ_UDC_FORCE_DATA0 (1 << 3)
717 #define MQ_UDC_FIFO_THRESHOLD_SHIFT (9)
718 #define MQ_UDC_FIFO_THRESHOLD_MASK (7 << MQ_UDC_FIFO_THRESHOLD_SHIFT)
719 #define MQ_UDC_FIFO_THRESHOLD(x) ((x) << MQ_UDC_FIFO_THRESHOLD_SHIFT)
720 /* Most bitmasks shared with ep0txstatus */
722 /* Most bitmasks shared with ep0rxcontrol */
724 /* Most bitmasks shared with ep0rxstatus */
727 #define MQ_UDC_INT_SOF (1 << 0)
728 #define MQ_UDC_INT_EP0_TX (1 << 1)
729 #define MQ_UDC_INT_EP0_RX (1 << 2)
730 #define MQ_UDC_INT_EP1_TX (1 << 3)
731 #define MQ_UDC_INT_EP2_TX_EOT (1 << 4)
732 #define MQ_UDC_INT_EP3_RX_EOT (1 << 5)
733 #define MQ_UDC_INT_DMA_TX (1 << 6)
734 #define MQ_UDC_INT_DMA_RX (1 << 7)
735 #define MQ_UDC_INT_DMA_RX_EOT (1 << 8)
736 #define MQ_UDC_INT_GLOBAL_SUSPEND (1 << 9)
737 #define MQ_UDC_INT_WAKEUP (1 << 10)
738 #define MQ_UDC_INT_RESET (1 << 11)
739 #define MQ_UDC_INT_EP0 (MQ_UDC_INT_EP0_TX | MQ_UDC_INT_EP0_RX)
740 #define MQ_UDC_INT_EP1 (MQ_UDC_INT_EP1_TX)
741 #define MQ_UDC_INT_EP2 (MQ_UDC_INT_EP2_TX_EOT | MQ_UDC_INT_DMA_TX)
742 #define MQ_UDC_INT_EP3 (MQ_UDC_INT_EP3_RX_EOT | MQ_UDC_INT_DMA_RX | \
743 MQ_UDC_INT_DMA_RX_EOT)
747 /* This is for endpoint 2 */
749 #define MQ_UDC_DMA_ENABLE (1 << 0)
750 #define MQ_UDC_DMA_PINGPONG (1 << 1)
751 #define MQ_UDC_DMA_NUMBUFF_SHIFT (2)
752 #define MQ_UDC_DMA_NUMBUFF_MASK (3 << MQ_UDC_DMA_NUMBUFF_SHIFT)
753 #define MQ_UDC_DMA_NUMBUFF(x) ((x - 1) << MQ_UDC_DMA_NUMBUFF_SHIFT)
754 #define MQ_UDC_DMA_BUFF1_OWNER (1 << 8)
755 #define MQ_UDC_DMA_BUFF2_OWNER (1 << 9)
756 #define MQ_UDC_DMA_BUFF1_EOT (1 << 10)
757 #define MQ_UDC_DMA_BUFF2_EOT (1 << 11)
759 #define MQ_UDC_DMA_BUFFER_ADDR_SHIFT (0)
760 #define MQ_UDC_DMA_BUFFER_ADDR_MASK (32767)
761 #define MQ_UDC_DMA_BUFFER_ADDR(x) (((x) >> 3) << MQ_UDC_DMA_BUFFER_ADDR_SHIFT)
762 #define MQ_UDC_DMA_BUFFER_SIZE_SHIFT (16)
763 #define MQ_UDC_DMA_BUFFER_SIZE_MASK (4095)
764 #define MQ_UDC_DMA_BUFFER_SIZE(x) ((x - 1) << MQ_UDC_DMA_BUFFER_SIZE_SHIFT)
765 #define MQ_UDC_DMA_BUFFER_LAST (1 << 28)
767 /* This shares bitmasks with dmatxcontrol, but refers to endpoint 3 */
769 #define MQ_UDC_ISO_TRANSFER_END (1 << 16)
771 #define MQ_UDC_DMA_BUFFER_EADDR_SHIFT (16)
772 #define MQ_UDC_DMA_BUFFER_EADDR_MASK (32767)
773 #define MQ_UDC_DMA_BUFFER_EADDR(x) (((x - 1) >> 3) << MQ_UDC_DMA_BUFFER_EADDR_SHIFT)
784 * Instead of attempting to figure out how to program this device,
785 * just use canned values for the known display types.
787 struct mediaq11xx_init_data
{
795 void (*set_power
) (int on
);
808 /* This structure is used by the basic MediaQ SoC driver to allow client
809 * drivers to use its functionality. Rather than doing a bunch of
810 * EXPORT_SYMBOL's we're storing a pointer to this structure in every
811 * device->platform_data, and the device_driver receives it with
814 struct mediaq11xx_base
{
815 /* Memory that is serialized between CPU and gfx engine */
817 /* Memory that is not synchronized between CPU and GE.
818 * WARNING: NEVER TOUCH MEMORY ALLOCATED WITH THE 'gfx' FLAG
819 * (SEE BELOW) VIA THE "ram" POINTER!!! SUCH ADDRESSES CAN BE
820 * BOGUS AND POSSIBLY BELONG TO OTHER PROCESS OR DRIVER!!!
823 /* MediaQ registers */
824 volatile struct mediaq11xx_regs
*regs
;
827 /* Chip name (1132, 1178 etc) */
828 const char *chipname
;
829 /* The physical address of MediaQ registers */
831 /* Physical address of serialized & non-serialized RAM */
832 u32 paddr_gfxram
, paddr_ram
;
833 #ifdef MQ_IRQ_MULTIPLEX
834 /* Base IRQ number of our allocated interval of IRQs */
838 /* Set the MediaQ GPIO to given state. Of course only those GPIOs
839 * are supported that exist (see MediaQ specs).
841 int (*set_GPIO
) (struct mediaq11xx_base
*zis
, int num
, int state
);
842 /* Change GPIO input/output mode */
843 #define MQ_GPIO_CHMODE 0x00000010
844 /* Disable GPIO pin */
845 #define MQ_GPIO_NONE 0x00000000
846 /* Enable GPIO input */
847 #define MQ_GPIO_IN 0x00000001
848 /* Enable GPIO output */
849 #define MQ_GPIO_OUT 0x00000002
850 /* Output a '0' on the GPIO pin (if OE is set) */
851 #define MQ_GPIO_0 0x00000020
852 /* Output a '1' on the GPIO pin (if OE is set) */
853 #define MQ_GPIO_1 0x00000040
854 /* Enable the pullup register (works only for GPIOs 50-53) */
855 #define MQ_GPIO_PULLUP 0x00000080
856 /* Handy shortcut - set some GPIO pin to output a '0' */
857 #define MQ_GPIO_OUT0 (MQ_GPIO_CHMODE | MQ_GPIO_OUT | MQ_GPIO_0)
858 /* Handy shortcut - set some GPIO pin to output an '1' */
859 #define MQ_GPIO_OUT1 (MQ_GPIO_CHMODE | MQ_GPIO_OUT | MQ_GPIO_1)
860 /* Set the MediaQ GPIO to input mode */
861 #define MQ_GPIO_INPUT (MQ_GPIO_CHMODE | MQ_GPIO_IN)
863 /* Get the state of a GPIO pin. If pin is in output mode, it
864 * returns the pin output value; if pin is in input mode it
865 * reads the logical level on the pin.
867 int (*get_GPIO
) (struct mediaq11xx_base
*zis
, int num
);
869 /* Apply/remove power to a subdevice.
870 * The base SoC driver keeps a count poweron requests for every
871 * subdevice; when a specific counter reaches zero the subdevice
872 * is powered off. For a list of subdev_id's see the MEDIAQ_11XX_XXX
873 * constants in soc-old.h. When all counts for all subdevices
874 * reaches zero, the MediaQ chip is totally powered off.
876 void (*set_power
) (struct mediaq11xx_base
*zis
, int subdev_id
, int enable
);
878 /* Query the power on count of a subdevice (0 - off, >0 - on) */
879 int (*get_power
) (struct mediaq11xx_base
*zis
, int subdev_id
);
881 /* Allocate a portion of MediaQ RAM. The returned pointer is a
882 * a memory offset from the start of MediaQ RAM; to get a virtual
883 * address you must add it to either "gfxram" or "ram" pointers.
884 * If there is not enough free memory, function returns (u32)-1.
885 * Memory allocated with the 'gfx=1' flag should be always accessed
886 * via the 'gfxram' pointer; however the reverse (accessing 'gfx=0'
887 * memory via the 'gfxram' pointer) is allowed. This is a MediaQ 11xx
888 * limitation: it doesn't allow access to first 8K of RAM via the
889 * graphics-engine-unsynchronized window.
891 u32 (*alloc
) (struct mediaq11xx_base
*zis
, unsigned bytes
, int gfx
);
893 /* Free a portion of MediaQ RAM, previously allocated by malloc() */
894 void (*free
) (struct mediaq11xx_base
*zis
, u32 addr
, unsigned bytes
);
898 * Increment the reference counter of the MediaQ base driver module.
899 * You must call this before enumerating MediaQ drivers; otherwise you
900 * can end with a pointer that points to nowhere in the case when driver
901 * is unloaded between mq_driver_enum() and when you use it.
903 extern int mq_driver_get (void);
906 * Decrement mediaq base SoC driver reference counter.
908 extern void mq_driver_put (void);
911 * Query a list of all MediaQ device drivers.
912 * You must lock the driver in memory by calling mq_driver_get() before
913 * calling this function.
915 extern int mq_device_enum (struct mediaq11xx_base
**list
, int list_size
);
917 #endif /* _PLATFORM_MEDIAQ11XX */