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[hh.org.git] / drivers / soc / mq11xx_base.c
blobf2c8394d30d842d94b598b76407652fe29cc65c8
1 /*
2 * System-on-Chip (SoC) driver for MediaQ 1100/1132 chips.
3 *
4 * Copyright (C) 2003 Andrew Zabolotny <anpaza@mail.ru>
5 * Portions copyright (C) 2003 Keith Packard
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/module.h>
13 #include <linux/version.h>
14 #include <linux/platform_device.h>
15 #include <linux/soc-old.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <asm/io.h>
21
22 #include "mq11xx.h"
23
24 #ifdef MQ_IRQ_MULTIPLEX
25 # include <asm/irq.h>
26 # include <asm/mach/irq.h>
27 #endif
28
29 #if 0
30 # define debug(s, args...) printk (KERN_INFO s, ##args)
31 #else
32 # define debug(s, args...)
33 #endif
34 #define debug_func(s, args...) debug ("%s: " s, __FUNCTION__, ##args)
35
36 /* Bitmasks for distinguishing resources for different sets of MediaQ chips */
37 #define MQ_MASK_1100 (1 << CHIP_MEDIAQ_1100)
38 #define MQ_MASK_1132 (1 << CHIP_MEDIAQ_1132)
39 #define MQ_MASK_1168 (1 << CHIP_MEDIAQ_1168)
40 #define MQ_MASK_1178 (1 << CHIP_MEDIAQ_1178)
41 #define MQ_MASK_1188 (1 << CHIP_MEDIAQ_1188)
42 #define MQ_MASK_ALL (MQ_MASK_1100 | MQ_MASK_1132 | MQ_MASK_1168 | \
43 MQ_MASK_1178 | MQ_MASK_1188)
44
45 struct mq_block
46 {
47 platform_device_id id;
48 const char *name;
49 unsigned start, end;
50 unsigned mask;
51 };
52
53 #define MQ_SUBDEVS_COUNT ARRAY_SIZE(mq_blocks)
54 #define MQ_SUBDEVS_REAL_COUNT (MQ_SUBDEVS_COUNT - 2)
55 static const struct mq_block mq_blocks[] = {
56 {
57 /* Graphics Controller */
58 { MEDIAQ_11XX_FB_DEVICE_ID },
59 "mq11xx_fb",
60 0x100, 0x17f,
61 MQ_MASK_ALL
62 },
63 {
64 /* Graphics Engine -- tied to framebuffer subdevice */
65 { MEDIAQ_11XX_FB_DEVICE_ID },
66 NULL,
67 0x200, 0x27f,
68 MQ_MASK_ALL
69 },
70 {
71 /* Palette Registers -- tied to framebuffer subdevice */
72 { MEDIAQ_11XX_FB_DEVICE_ID },
73 NULL,
74 0x800, 0xbff,
75 MQ_MASK_ALL
76 },
77 {
78 /* Flat Panel control interface */
79 { MEDIAQ_11XX_FP_DEVICE_ID },
80 "mq11xx_lcd",
81 0x600, 0x7ff,
82 MQ_MASK_ALL
83 },
84 {
85 /* USB Function subdevice */
86 { MEDIAQ_11XX_UDC_DEVICE_ID },
87 "mq11xx_udc",
88 0x1000, 0x107f,
89 MQ_MASK_ALL
90 },
91 {
92 /* USB Host subdevice */
93 { MEDIAQ_11XX_UHC_DEVICE_ID },
94 "mq11xx_uhc",
95 0x500, 0x5ff,
96 MQ_MASK_1132 | MQ_MASK_1188
97 },
98 {
99 /* Serial Port Interface */
100 { MEDIAQ_11XX_SPI_DEVICE_ID },
101 "mq11xx_spi",
102 0x300, 0x37f,
103 MQ_MASK_1132
104 },
105 {
106 /* Synchronous Serial Channel (I2S) */
107 { MEDIAQ_11XX_I2S_DEVICE_ID },
108 "mq11xx_i2s",
109 0x280, 0x2ff,
110 MQ_MASK_1132
111 },
112 };
113
114 static struct {
115 int id;
116 int chip;
117 const char *name;
118 } mq_device_id [] =
119 {
120 { MQ_PCI_DEVICEID_1100, CHIP_MEDIAQ_1100, "1100" },
121 { MQ_PCI_DEVICEID_1132, CHIP_MEDIAQ_1132, "1132" },
122 { MQ_PCI_DEVICEID_1168, CHIP_MEDIAQ_1168, "1168" },
123 { MQ_PCI_DEVICEID_1178, CHIP_MEDIAQ_1178, "1178" },
124 { MQ_PCI_DEVICEID_1188, CHIP_MEDIAQ_1188, "1188" }
125 };
126
127 /* Keep free block list no less than this value (minimal slab is 32 bytes) */
128 #define MEMBLOCK_MINCOUNT (32 / sizeof (struct mq_freemem_list))
129 /* Align MediaQ memory blocks by this amount (MediaQ DMA limitation) */
130 #define MEMBLOCK_ALIGN 64
131
132 struct mq_freemem_list {
133 u32 addr;
134 u32 size;
135 } __attribute__((packed));
136
137 struct mq_data
138 {
139 /* The exported parameters */
140 struct mediaq11xx_base base;
141 /* MediaQ initialization register data */
142 struct mediaq11xx_init_data *mq_init;
143 /* Number of subdevices */
144 int ndevices;
145 /* The list of subdevices */
146 struct platform_device *devices;
147 /* MediaQ interrupt number */
148 int irq_nr;
149 /* Count the number of poweron requests to every subdevice */
150 u8 power_on [MQ_SUBDEVS_REAL_COUNT];
151 /* Number of free block descriptors */
152 int nfreeblocks, maxfreeblocks;
153 /* The list of free blocks */
154 struct mq_freemem_list *freelist;
155 /* The lock on the free blocks list */
156 spinlock_t mem_lock;
157 /* The amount of RAM at the beginning of address space that
158 is not accessible through the unsynced window */
159 int unsynced_ram_skip;
160 };
161
162 /* Pointer to initialized devices.
163 * This is a bad practice, but if you don't need too much from the
164 * MediaQ device (such as turning on/off a couple of GPIOs) you can
165 * use the mq_get_device (int index) to get a pointer to one of
166 * available MediaQ device structures.
167 */
168 #define MAX_MQ11XX_DEVICES 8
169 static struct mediaq11xx_base *mq_device_list [MAX_MQ11XX_DEVICES];
170 static spinlock_t mq_device_list_lock = SPIN_LOCK_UNLOCKED;
171
172 #define to_mq_data(n) container_of(n, struct mq_data, base)
173
174 /* For PCI & DragonBall register mapping is as described in the specs sheet;
175 * for other microprocessor buses some addresses are tossed (what a perversion).
176 * Worse than that, on MQ1168 and later, the registers are always as normal.
177 */
178 #if defined __arm__
179 // || defined NEC41xx || defined HITACHI 77xx
180 #define MQ_MASK_REGSET1 (MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188)
181 #define MQ_MASK_REGSET2 (MQ_MASK_1100 | MQ_MASK_1132)
182 #else
183 #define MQ_MASK_REGSET1 MQ_MASK_ALL
184 #define MQ_MASK_REGSET2 0
185 #endif
186
187 static struct mediaq11xx_init_data mqInitValid = {
188 /* DC */
189 {
190 /* dc00 */ 0,
191 /* dc01 */ MQ_MASK_ALL,
192 /* dc02 */ MQ_MASK_ALL,
193 /* dc03 */ 0,
194 /* dc04 */ MQ_MASK_ALL,
195 /* dc05 */ MQ_MASK_ALL,
196 },
197 /* CC */
198 {
199 /* cc00 */ MQ_MASK_ALL,
200 /* cc01 */ MQ_MASK_ALL,
201 /* cc02 */ MQ_MASK_ALL,
202 /* cc03 */ MQ_MASK_ALL,
203 /* cc04 */ MQ_MASK_ALL,
204 },
205 /* MIU */
206 {
207 /* mm00 */ MQ_MASK_ALL,
208 /* mm01 */ MQ_MASK_ALL,
209 /* mm02 */ MQ_MASK_ALL,
210 /* mm03 */ MQ_MASK_ALL,
211 /* mm04 */ MQ_MASK_ALL,
212 /* mm05 */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
213 /* mm06 */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
214 },
215 /* GC */
216 {
217 /* gc00 */ MQ_MASK_ALL,
218 /* gc01 */ MQ_MASK_ALL,
219 /* gc02 */ MQ_MASK_ALL,
220 /* gc03 */ MQ_MASK_ALL,
221 /* gc04 */ MQ_MASK_ALL,
222 /* gc05 */ MQ_MASK_ALL,
223 /* gc06 NOT SET */ 0,
224 /* gc07 NOT SET */ 0,
225 /* gc08 */ MQ_MASK_ALL,
226 /* gc09 */ MQ_MASK_ALL,
227 /* gc0a */ MQ_MASK_ALL,
228 /* gc0b */ MQ_MASK_ALL,
229 /* gc0c */ MQ_MASK_ALL,
230 /* gc0d */ MQ_MASK_ALL,
231 /* gc0e */ MQ_MASK_ALL,
232 /* gc0f NOT SET */ 0,
233 /* gc10 */ MQ_MASK_ALL,
234 /* gc11 */ MQ_MASK_ALL,
235 /* gc12 NOT SET */ 0,
236 /* gc13 NOT SET */ 0,
237 /* gc14 */ MQ_MASK_ALL,
238 /* gc15 */ MQ_MASK_ALL,
239 /* gc16 */ MQ_MASK_ALL,
240 /* gc17 */ MQ_MASK_ALL,
241 /* gc18 */ MQ_MASK_ALL,
242 /* gc19 */ MQ_MASK_ALL,
243 /* gc1a */ MQ_MASK_ALL,
244 },
245 /* FP */
246 {
247 /* fp00 */ MQ_MASK_ALL,
248 /* fp01 */ MQ_MASK_ALL,
249 /* fp02 */ MQ_MASK_ALL,
250 /* fp03 */ MQ_MASK_ALL,
251 /* fp04 */ MQ_MASK_ALL,
252 /* fp05 */ MQ_MASK_ALL,
253 /* fp06 */ MQ_MASK_ALL,
254 /* fp07 */ MQ_MASK_ALL,
255 /* fp08 */ MQ_MASK_ALL,
256 /* fp09 NOT SET */ 0,
257 /* fp0a */ MQ_MASK_ALL,
258 /* fp0b */ MQ_MASK_ALL,
259 /* fp0c */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
260 /* fp0d NOT SET */ 0,
261 /* fp0e NOT SET */ 0,
262 /* fp0f */ MQ_MASK_ALL,
263 /* fp10 */ MQ_MASK_ALL,
264 /* fp11 */ MQ_MASK_ALL,
265 /* fp12 */ MQ_MASK_ALL,
266 /* fp13 */ MQ_MASK_ALL,
267 /* fp14 */ MQ_MASK_ALL,
268 /* fp15 */ MQ_MASK_ALL,
269 /* fp16 */ MQ_MASK_ALL,
270 /* fp17 */ MQ_MASK_ALL,
271 /* fp18 */ MQ_MASK_ALL,
272 /* fp19 */ MQ_MASK_ALL,
273 /* fp1a */ MQ_MASK_ALL,
274 /* fp1b */ MQ_MASK_ALL,
275 /* fp1c */ MQ_MASK_ALL,
276 /* fp1d */ MQ_MASK_ALL,
277 /* fp1e */ MQ_MASK_ALL,
278 /* fp1f */ MQ_MASK_ALL,
279 /* fp20 */ MQ_MASK_REGSET1,
280 /* fp21 */ MQ_MASK_REGSET1,
281 /* fp22 */ MQ_MASK_REGSET1,
282 /* fp23 */ MQ_MASK_REGSET1,
283 /* fp24 */ MQ_MASK_REGSET1,
284 /* fp25 */ MQ_MASK_REGSET1,
285 /* fp26 */ MQ_MASK_REGSET1,
286 /* fp27 */ MQ_MASK_REGSET1,
287 /* fp28 */ MQ_MASK_REGSET1,
288 /* fp29 */ MQ_MASK_REGSET1,
289 /* fp2a */ MQ_MASK_REGSET1,
290 /* fp2b */ MQ_MASK_REGSET1,
291 /* fp2c */ MQ_MASK_REGSET1,
292 /* fp2d */ MQ_MASK_REGSET1,
293 /* fp2e */ MQ_MASK_REGSET1,
294 /* fp2f */ MQ_MASK_REGSET1,
295 /* fp30 */ MQ_MASK_ALL,
296 /* fp31 */ MQ_MASK_ALL,
297 /* fp32 */ MQ_MASK_ALL,
298 /* fp33 */ MQ_MASK_ALL,
299 /* fp34 */ MQ_MASK_ALL,
300 /* fp35 */ MQ_MASK_ALL,
301 /* fp36 */ MQ_MASK_ALL,
302 /* fp37 */ MQ_MASK_ALL,
303 /* fp38 */ MQ_MASK_ALL,
304 /* fp39 */ MQ_MASK_ALL,
305 /* fp3a */ MQ_MASK_ALL,
306 /* fp3b */ MQ_MASK_ALL,
307 /* fp3c */ MQ_MASK_ALL,
308 /* fp3d */ MQ_MASK_ALL,
309 /* fp3e */ MQ_MASK_ALL,
310 /* fp3f */ MQ_MASK_ALL,
311 /* fp40 */ 0,
312 /* fp41 */ 0,
313 /* fp42 */ 0,
314 /* fp43 */ 0,
315 /* fp44 */ 0,
316 /* fp45 */ 0,
317 /* fp46 */ 0,
318 /* fp47 */ 0,
319 /* fp48 */ 0,
320 /* fp49 */ 0,
321 /* fp4a */ 0,
322 /* fp4b */ 0,
323 /* fp4c */ 0,
324 /* fp4d */ 0,
325 /* fp4e */ 0,
326 /* fp4f */ 0,
327 /* fp50 */ 0,
328 /* fp51 */ 0,
329 /* fp52 */ 0,
330 /* fp53 */ 0,
331 /* fp54 */ 0,
332 /* fp55 */ 0,
333 /* fp56 */ 0,
334 /* fp57 */ 0,
335 /* fp58 */ 0,
336 /* fp59 */ 0,
337 /* fp5a */ 0,
338 /* fp5b */ 0,
339 /* fp5c */ 0,
340 /* fp5d */ 0,
341 /* fp5e */ 0,
342 /* fp5f */ 0,
343 /* fp60 */ 0,
344 /* fp61 */ 0,
345 /* fp62 */ 0,
346 /* fp63 */ 0,
347 /* fp64 */ 0,
348 /* fp65 */ 0,
349 /* fp66 */ 0,
350 /* fp67 */ 0,
351 /* fp68 */ 0,
352 /* fp69 */ 0,
353 /* fp6a */ 0,
354 /* fp6b */ 0,
355 /* fp6c */ 0,
356 /* fp6d */ 0,
357 /* fp6e */ 0,
358 /* fp6f */ 0,
359 /* fp70 */ MQ_MASK_REGSET2,
360 /* fp71 */ MQ_MASK_REGSET2,
361 /* fp72 */ MQ_MASK_REGSET2,
362 /* fp73 */ MQ_MASK_REGSET2,
363 /* fp74 */ MQ_MASK_REGSET2,
364 /* fp75 */ MQ_MASK_REGSET2,
365 /* fp76 */ MQ_MASK_REGSET2,
366 /* fp77 */ MQ_MASK_REGSET2,
367 },
368 /* GE */
369 {
370 /* ge00 NOT SET */ 0,
371 /* ge01 NOT SET */ 0,
372 /* ge02 NOT SET */ 0,
373 /* ge03 NOT SET */ 0,
374 /* ge04 NOT SET */ 0,
375 /* ge05 NOT SET */ 0,
376 /* ge06 NOT SET */ 0,
377 /* ge07 NOT SET */ 0,
378 /* ge08 NOT SET */ 0,
379 /* ge09 NOT SET */ 0,
380 /* ge0a */ MQ_MASK_ALL,
381 /* ge0b */ MQ_MASK_ALL,
382 /* ge0c NOT SET */ 0x0,
383 /* ge0d NOT SET */ 0x0,
384 /* ge0e NOT SET */ 0x0,
385 /* ge0f NOT SET */ 0x0,
386 /* ge10 NOT SET */ 0x0,
387 /* ge11 NOT SET */ MQ_MASK_1168 | MQ_MASK_1178 | MQ_MASK_1188,
388 /* ge12 NOT SET */ 0x0,
389 /* ge13 NOT SET */ 0x0,
390 },
391 /* SPI */
392 {
393 /* sp00 */ MQ_MASK_1132,
394 /* sp01 */ 0,
395 /* sp02 NOT SET */ 0,
396 /* sp03 NOT SET */ 0,
397 /* sp04 */ MQ_MASK_1132,
398 /* sp05 NOT SET */ 0,
399 /* sp06 NOT SET */ 0,
400 /* sp07 */ MQ_MASK_1132,
401 /* sp08 */ MQ_MASK_1132,
402 },
403 };
404
405 static int
406 mq11xx_loadvals (char *name, int chipmask, volatile u32 *reg,
407 u32 *src, u32 *valid, int n)
408 {
409 int t;
410
411 for (t = 0; t < n; t++){
412 if (valid[t] & chipmask) {
413 int tries;
414 for (tries = 0; tries < 10; tries++) {
415 reg[t] = src[t];
416 if (reg[t] == src[t])
417 break;
418 mdelay (1);
419 }
420 if (tries == 10) {
421 debug ("mq11xx_loadvals %s%02x %08x FAILED (got %08x)\n", name, t, src[t], reg[t]);
422 return -ENODEV;
423 }
424 }
425 }
426 return 0;
427 }
428
429 static int
430 mq11xx_init (struct mq_data *mqdata)
431 {
432 int i, chipmask;
433 u16 endian;
434
435 if (mqdata->mq_init->set_power)
436 mqdata->mq_init->set_power(1);
437
438 /* Set up chip endianness - see mq docs for notes on special care
439 when writing to this register */
440 endian = mqdata->mq_init->DC [0] & 3;
441 endian = endian | (endian << 2);
442 endian = endian | (endian << 4);
443 endian = endian | (endian << 8);
444 *((u16 *)&mqdata->base.regs->DC.config_0) = endian;
445 /* First of all, enable the oscillator clock */
446 mqdata->base.regs->DC.config_1 = mqdata->mq_init->DC [1];
447 /* Wait for oscillator to run - 30ms doesnt suffice */
448 mdelay (100);
449 /* Enable power to CPU Configuration module */
450 mqdata->base.regs->DC.config_2 = mqdata->mq_init->DC [2];
451 mdelay (10);
452 /* Needed for MediaQ 1178/88 on h2200. */
453 mqdata->base.regs->DC.config_8 = 0x86098609;
454 /* Enable the MQ1132 MIU */
455 mqdata->base.regs->MIU.miu_0 |= MQ_MIU_ENABLE;
456 /* Disable the interrupt controller */
457 mqdata->base.regs->IC.control = 0;
458
459 /* See if it's actually a MediaQ chip */
460 if (mqdata->base.regs->PCI.vendor_id != MQ_PCI_VENDORID) {
461 unkchip: printk (KERN_ERR "%s:%d Unknown device ID (%04x:%04x)\n",
462 __FILE__, __LINE__,
463 mqdata->base.regs->PCI.vendor_id,
464 mqdata->base.regs->PCI.device_id);
465 return -ENODEV;
466 }
467
468 for (i = 0; i < ARRAY_SIZE (mq_device_id); i++)
469 if (mqdata->base.regs->PCI.device_id == mq_device_id [i].id) {
470 mqdata->base.chip = mq_device_id [i].chip;
471 mqdata->base.chipname = mq_device_id [i].name;
472 break;
473 }
474
475 if (!mqdata->base.chipname)
476 goto unkchip;
477
478 chipmask = 1 << mqdata->base.chip;
479
480 #define INIT_REGS(id) \
481 if (mq11xx_loadvals (#id, chipmask, mqdata->base.regs->id.a, \
482 mqdata->mq_init->id, mqInitValid.id, \
483 ARRAY_SIZE (mqdata->mq_init->id))) \
484 return -ENODEV
485
486 INIT_REGS (DC);
487 INIT_REGS (CC);
488 INIT_REGS (MIU);
489
490 /* XXX Move this stuff to mq1100fb driver some day */
491 INIT_REGS (GC);
492 INIT_REGS (FP);
493 INIT_REGS (GE);
494
495 #undef INIT_REGS
496
497 return 0;
498 }
499
500 static void
501 mq_release (struct device *dev)
502 {
503 }
504
505 /* This is kind of ugly and complex... well, this is the way GPIOs are
506 * programmed on MediaQ... what a mess...
507 */
508 static int
509 mq_set_GPIO (struct mediaq11xx_base *zis, int num, int state)
510 {
511 u32 andmask = 0, ormask = 0;
512
513 debug ("mq_set_GPIO (num:%d state:%x)\n", num, state);
514
515 if ((num <= 7) || ((num >= 20) && (num <= 25))) {
516 andmask = 4;
517 if (state & MQ_GPIO_CHMODE) {
518 andmask |= 3;
519 if (state & MQ_GPIO_IN)
520 ormask |= 1;
521 if (state & MQ_GPIO_OUT)
522 ormask |= 2;
523 }
524 if (state & MQ_GPIO_0)
525 andmask |= 8;
526 if (state & MQ_GPIO_1)
527 ormask |= 8;
528 if (num <= 7) {
529 andmask <<= num * 4;
530 ormask <<= num * 4;
531 zis->regs->CC.gpio_control_0 =
532 (zis->regs->CC.gpio_control_0 & ~andmask) | ormask;
533 } else {
534 andmask <<= (num - 18) * 4;
535 ormask <<= (num - 18) * 4;
536 zis->regs->CC.gpio_control_1 =
537 (zis->regs->CC.gpio_control_1 & ~andmask) | ormask;
538 }
539 } else if (num >= 50 && num <= 55) {
540 int shft;
541
542 /* Uhh.... what a mess */
543 if (state & MQ_GPIO_CHMODE) {
544 shft = (num <= 53) ? num - 48 : num - 45;
545 andmask |= 3 << shft;
546 if (state & MQ_GPIO_OUT)
547 ormask |= (1 << (shft * 2));
548 if (state & MQ_GPIO_IN)
549 ormask |= (2 << (shft * 2));
550 }
551
552 if (num == 50)
553 shft = 3;
554 else if (num <= 53)
555 shft = (num - 51);
556 else
557 shft = (num - 38);
558
559 if (state & MQ_GPIO_0)
560 andmask |= (1 << shft);
561 if (state & MQ_GPIO_1)
562 ormask |= (1 << shft);
563 if ((state & MQ_GPIO_PULLUP) && (num <= 53))
564 ormask |= 0x1000 << (num - 50);
565 zis->regs->SPI.gpio_mode =
566 (zis->regs->SPI.gpio_mode & ~andmask) | ormask;
567 } else if (num >= 60 && num <= 66) {
568 int shft = (num - 60);
569 if (state & MQ_GPIO_0)
570 andmask |= (1 << shft);
571 if (state & MQ_GPIO_1)
572 ormask |= (1 << shft);
573 shft *= 2;
574 if (state & MQ_GPIO_CHMODE) {
575 andmask |= (0x300 << shft);
576 if (state & MQ_GPIO_OUT)
577 ormask |= (0x100 << shft);
578 if (state & MQ_GPIO_IN)
579 ormask |= (0x200 << shft);
580 }
581 zis->regs->SPI.blue_gpio_mode =
582 (zis->regs->SPI.blue_gpio_mode & ~andmask) | ormask;
583 } else
584 return -ENODEV;
585
586 return 0;
587 }
588
589 static int
590 mq_get_GPIO (struct mediaq11xx_base *zis, int num)
591 {
592 u32 val;
593
594 if (num <= 7)
595 val = zis->regs->CC.gpio_control_0 & (8 << (num * 4));
596 else if ((num >= 20) && (num <= 25))
597 val = zis->regs->CC.gpio_control_1 & (8 << ((num - 18) * 4));
598 else if (num == 50)
599 val = zis->regs->SPI.gpio_mode & 0x8;
600 else if ((num >= 51) && (num <= 53))
601 val = zis->regs->SPI.gpio_mode & (0x1 << (num - 51));
602 else if ((num >= 54) && (num <= 55))
603 val = zis->regs->SPI.gpio_mode & (0x1 << (num - 38));
604 else if (num >= 60 && num <= 66)
605 val = zis->regs->SPI.blue_gpio_mode & (1 << (num - 60));
606 else
607 val = 0;
608
609 if (val) val = 1;
610
611 return val;
612 }
613
614 static int
615 global_power (struct mq_data *mqdata)
616 {
617 int i;
618 for (i = 0; i < sizeof (mqdata->power_on); i++)
619 if (mqdata->power_on [i])
620 return 1;
621 return 0;
622 }
623
624 static void
625 mq_power_on (struct mediaq11xx_base *zis, int subdev_id)
626 {
627 /* The device IDs lower 4 bits contains the subdevice index
628 * (counting from 1). Take care to keep all MEDIAQ_11XX_XXX
629 * contstants with sequential values in their lower 4 bits!
630 */
631 unsigned idx = (subdev_id & 0x0f) - 1;
632 struct mq_data *mqdata = to_mq_data (zis);
633
634 debug_func ("subdev:%x curstate:%d\n", subdev_id, mqdata->power_on [idx]);
635
636 /* Check if MediaQ is not totally turned off */
637 if (!global_power (mqdata)) {
638 debug ("-*- Global POWER ON to the MediaQ chip -*-\n");
639 mq11xx_init (mqdata);
640 }
641
642 if (!mqdata->power_on [idx])
643 switch (subdev_id) {
644 case MEDIAQ_11XX_FB_DEVICE_ID:
645 zis->regs->GC.control |= MQ_GC_CONTROL_ENABLE;
646 /* Enable the graphics engine power */
647 zis->regs->DC.config_5 |= MQ_CONFIG_GE_ENABLE;
648 break;
649 case MEDIAQ_11XX_FP_DEVICE_ID:
650 /* Enable flat panel pin outputs */
651 //zis->regs->FP.pin_control_1 &= ~MQ_FP_DISABLE_FLAT_PANEL_PINS;
652 zis->regs->FP.output_control = mqdata->mq_init->FP [2];
653 break;
654 case MEDIAQ_11XX_UDC_DEVICE_ID:
655 /* Enable power to USB function */
656 zis->regs->DC.config_5 |= MQ_CONFIG_UDC_CLOCK_ENABLE;
657 break;
658 case MEDIAQ_11XX_UHC_DEVICE_ID:
659 /* Enable power to USB host */
660 zis->regs->DC.config_5 |= MQ_CONFIG_UHC_CLOCK_ENABLE;
661 break;
662 case MEDIAQ_11XX_SPI_DEVICE_ID:
663 case MEDIAQ_11XX_I2S_DEVICE_ID:
664 /* There's no explicit way to do it */
665 break;
666 }
667 mqdata->power_on [idx]++;
668 }
669
670 static void
671 mq_power_off (struct mediaq11xx_base *zis, int subdev_id)
672 {
673 unsigned idx = (subdev_id & 0x0f) - 1;
674 struct mq_data *mqdata = to_mq_data (zis);
675
676 debug_func ("subdev:%x curstate:%d\n", subdev_id, mqdata->power_on [idx]);
677
678 if (!mqdata->power_on [idx]) {
679 printk (KERN_ERR "mq11xx: mismatch power on/off request count for subdevice %x\n",
680 subdev_id);
681 return;
682 }
683
684 switch (subdev_id) {
685 case MEDIAQ_11XX_FB_DEVICE_ID:
686 zis->regs->GC.control &= ~MQ_GC_CONTROL_ENABLE;
687 /* Disable the graphics engine power */
688 zis->regs->DC.config_5 &= ~MQ_CONFIG_GE_ENABLE;
689 break;
690 case MEDIAQ_11XX_FP_DEVICE_ID:
691 /* Disable flat panel pin outputs */
692 zis->regs->FP.output_control = 0;
693 //zis->regs->FP.pin_control_1 |= MQ_FP_DISABLE_FLAT_PANEL_PINS;
694 break;
695 case MEDIAQ_11XX_UDC_DEVICE_ID:
696 /* Disable power to USB function */
697 zis->regs->DC.config_5 &= ~MQ_CONFIG_UDC_CLOCK_ENABLE;
698 break;
699 case MEDIAQ_11XX_UHC_DEVICE_ID:
700 /* Disable power to USB host */
701 zis->regs->DC.config_5 &= ~MQ_CONFIG_UHC_CLOCK_ENABLE;
702 break;
703 case MEDIAQ_11XX_SPI_DEVICE_ID:
704 case MEDIAQ_11XX_I2S_DEVICE_ID:
705 /* There's no explicit way to do it */
706 break;
707 }
708
709 mqdata->power_on [idx]--;
710
711 /* Check if we have to totally power off MediaQ */
712 if (!global_power (mqdata)) {
713 debug ("-*- Global POWER OFF to MediaQ chip -*-\n");
714 /* Disable the MQ1132 MIU */
715 zis->regs->MIU.miu_0 &= ~MQ_MIU_ENABLE;
716 /* Disable power to CPU Configuration module */
717 zis->regs->DC.config_2 &= ~MQ_CONFIG_CC_MODULE_ENABLE;
718 /* Disable the oscillator clock */
719 zis->regs->DC.config_1 &= ~MQ_CONFIG_18_OSCILLATOR;
720
721 if (mqdata->mq_init->set_power)
722 mqdata->mq_init->set_power(0);
723 }
724 }
725
726 static void
727 mq_set_power (struct mediaq11xx_base *zis, int subdev_id, int state)
728 {
729 if (state)
730 mq_power_on (zis, subdev_id);
731 else
732 mq_power_off (zis, subdev_id);
733 }
734
735 static int
736 mq_get_power (struct mediaq11xx_base *zis, int subdev_id)
737 {
738 unsigned idx = (subdev_id & 0x0f) - 1;
739 struct mq_data *mqdata = to_mq_data (zis);
740 return mqdata->power_on [idx];
741 }
742
743 /********************************************* On-chip memory management ******/
744
745 /**
746 * Since the internal chip RAM may be shared amongst several subdevices
747 * (framebuffer, graphics engine, SPI, UDC and other), we have to implement
748 * a general memory management mechanism to prevent conflicts between drivers
749 * trying to use this resource.
750 *
751 * We could use the "chained free blocks" scheme used in many simple memory
752 * managers, where a { free block size; next free block; } structure is
753 * stuffed directly into the free block itself, to conserve memory. However,
754 * this mechanism is less reliable since it is susceptible to overwrites
755 * past the bounds of an allocated block (because it breaks the free blocks
756 * chain). Of course, a buggy driver is always a bad idea, but we should try
757 * to be as reliable as possible. Thus, the free block chain is kept in kernel
758 * memory (in the device-specific structure), and everything else is done like
759 * in the mentioned scheme.
760 */
761
762 static void
763 mq_setfreeblocks (struct mq_data *mqdata, int nblocks)
764 {
765 void *temp;
766 int newmax;
767
768 /* Increase maximum number of free memory descriptors in power-of-two
769 steps. This is due to the fact, that Linux allocates memory in
770 power-of-two chunks, and the minimal chunk (slab) size is 32b.
771 Allocating anything but power-of-two sized memory blocks is just
772 a waste of memory. In fact, in most circumstances we have a small
773 number of free block descriptors. */
774 newmax = (nblocks > 0) ? (1 << fls (nblocks - 1)) : 1;
775 if (likely (newmax < MEMBLOCK_MINCOUNT))
776 newmax = MEMBLOCK_MINCOUNT;
777
778 if (mqdata->maxfreeblocks != newmax) {
779 int nfb = mqdata->nfreeblocks;
780 if (nfb > nblocks) nfb = nblocks;
781 temp = kmalloc (newmax * sizeof (struct mq_freemem_list),
782 GFP_KERNEL);
783 memcpy (temp, mqdata->freelist, nfb * sizeof (struct mq_freemem_list));
784 kfree (mqdata->freelist);
785 mqdata->freelist = temp;
786 mqdata->maxfreeblocks = newmax;
787 }
788
789 mqdata->nfreeblocks = nblocks;
790 }
791
792 /* Check if memory block is suitable for uses other than graphics. */
793 static int mq_suitable_ram (struct mq_data *mqdata, int fbn, unsigned size)
794 {
795 int n, delta;
796
797 delta = mqdata->unsynced_ram_skip - mqdata->freelist [fbn].addr;
798 if (delta <= 0)
799 return 1;
800
801 if (mqdata->freelist [fbn].size < size + delta)
802 return 0;
803
804 /* Ok, split the free block into two */
805 n = mqdata->nfreeblocks;
806 mq_setfreeblocks (mqdata, n + 1);
807 mqdata->freelist [n].addr = mqdata->freelist [fbn].addr;
808 mqdata->freelist [n].size = delta;
809 mqdata->freelist [fbn].addr += delta;
810 mqdata->freelist [fbn].size -= delta;
811
812 return 1;
813 }
814
815 /* Not too optimal (just finds the first free block of equal or larger size
816 * than requested) but usually there are a few blocks in MediaQ RAM anyway...
817 * usually a block of 320x240x2 bytes is eaten by the framebuffer, and we
818 * have just 256k total.
819 */
820 static u32
821 mq_alloc (struct mediaq11xx_base *zis, unsigned size, int gfx)
822 {
823 struct mq_data *mqdata = to_mq_data (zis);
824 int i;
825
826 size = (size + MEMBLOCK_ALIGN - 1) & ~(MEMBLOCK_ALIGN - 1);
827
828 spin_lock (&mqdata->mem_lock);
829
830 for (i = mqdata->nfreeblocks - 1; i >= 0; i--) {
831 if ((mqdata->freelist [i].size >= size) &&
832 (gfx || mq_suitable_ram (mqdata, i, size))) {
833 u32 addr = mqdata->freelist [i].addr;
834 mqdata->freelist [i].size -= size;
835 if (mqdata->freelist [i].size)
836 mqdata->freelist [i].addr += size;
837 else {
838 memcpy (mqdata->freelist + i, mqdata->freelist + i + 1,
839 (mqdata->nfreeblocks - 1 - i) * sizeof (struct mq_freemem_list));
840 mq_setfreeblocks (mqdata, mqdata->nfreeblocks - 1);
841 }
842 spin_unlock (&mqdata->mem_lock);
843 return addr;
844 }
845 }
846
847 spin_unlock (&mqdata->mem_lock);
848
849 return (u32)-1;
850 }
851
852 static void
853 mq_free (struct mediaq11xx_base *zis, u32 addr, unsigned size)
854 {
855 int i, j;
856 u32 eaddr;
857 struct mq_data *mqdata = to_mq_data (zis);
858
859 size = (size + MEMBLOCK_ALIGN - 1) & ~(MEMBLOCK_ALIGN - 1);
860 eaddr = addr + size;
861
862 spin_lock (&mqdata->mem_lock);
863
864 /* Look for a free block that starts at the end of the block to free */
865 for (i = mqdata->nfreeblocks - 1; i >= 0; i--)
866 if (mqdata->freelist [i].addr == eaddr) {
867 mqdata->freelist [i].size += size;
868 mqdata->freelist [i].addr = addr;
869 /* Now look for a block that ends where we start */
870 for (j = mqdata->nfreeblocks - 1; j >= 0; j--) {
871 if (mqdata->freelist [j].addr + mqdata->freelist [j].size == addr) {
872 /* Ok, concatenate the two free blocks */
873 mqdata->freelist [i].addr = mqdata->freelist [j].addr;
874 mqdata->freelist [i].size += mqdata->freelist [j].size;
875 memcpy (mqdata->freelist + j, mqdata->freelist + j + 1,
876 (mqdata->nfreeblocks - 1 - j) * sizeof (struct mq_freemem_list));
877 mq_setfreeblocks (mqdata, mqdata->nfreeblocks - 1);
878 break;
879 }
880 }
881 spin_unlock (&mqdata->mem_lock);
882 return;
883 }
884
885 for (i = mqdata->nfreeblocks - 1; i >= 0; i--)
886 if (mqdata->freelist [i].addr + mqdata->freelist [i].size == addr) {
887 mqdata->freelist [i].size += size;
888 spin_unlock (&mqdata->mem_lock);
889 return;
890 }
891
892 /* Ok, we have to add a new free block entry */
893 i = mqdata->nfreeblocks;
894 mq_setfreeblocks (mqdata, i + 1);
895 mqdata->freelist [i].addr = addr;
896 mqdata->freelist [i].size = size;
897
898 spin_unlock (&mqdata->mem_lock);
899 }
900
901 /**************************** IRQ handling using interrupt multiplexing ******/
902
903 #ifdef MQ_IRQ_MULTIPLEX
904
905 static void
906 mq_irq_demux (unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
907 {
908 u32 mask, orig_mask;
909 int i, mq_irq, timeout;
910 struct mq_data *mqdata;
911
912 mqdata = desc->handler_data;
913
914 mqdata->base.regs->IC.control &= ~MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE;
915
916 debug ("mq_irq_demux ENTER\n");
917
918 /* An IRQ is a expensive operation, thus we're handling here
919 * as much interrupt sources as we can (rather than returning
920 * from interrupt just to get caught once again). On the other
921 * hand, we can't process too much of them since some IRQ may be
922 * continuously triggered. Thus, we'll set an arbitrary upper limit
923 * on the number of interrupts we can handle at once. Note that,
924 * for example, if PCMCIA IRQ is connected to MediaQ, this number
925 * can be very large, e.g. one interrupt for every read sector
926 * from a memory card.
927 */
928 timeout = 1024;
929
930 /* Read the IRQ status register */
931 while (timeout-- &&
932 (mask = orig_mask = mqdata->base.regs->IC.interrupt_status)) {
933 irq = 0;
934 while ((i = ffs (mask))) {
935 irq += i - 1;
936 mq_irq = mqdata->base.irq_base + irq;
937 desc = irq_desc + mq_irq;
938 debug ("mq_irq_demux (irq:%d)\n", mq_irq);
939 desc->handle_irq(mq_irq, desc, regs);
940 mask >>= i;
941 }
942 }
943
944 if (!timeout)
945 printk (KERN_ERR "mq11xx: IRQ continuously triggered, mask %08x\n", mask);
946
947 debug ("mq_irq_demux LEAVE\n");
948
949 mqdata->base.regs->IC.control |= MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE;
950 }
951
952 /* Acknowledge, clear _AND_ disable the interrupt. */
953 static void
954 mq_irq_ack (unsigned int irq)
955 {
956 struct mq_data *mqdata = get_irq_chipdata (irq);
957 u32 mask = 1 << (irq - mqdata->base.irq_base);
958 /* Disable the IRQ */
959 mqdata->base.regs->IC.interrupt_mask &= ~mask;
960 /* Acknowledge the IRQ */
961 mqdata->base.regs->IC.interrupt_status = mask;
962 }
963
964 static void
965 mq_irq_mask (unsigned int irq)
966 {
967 struct mq_data *mqdata = get_irq_chipdata (irq);
968 u32 mask = 1 << (irq - mqdata->base.irq_base);
969 mqdata->base.regs->IC.interrupt_mask &= ~mask;
970 }
971
972 static void
973 mq_irq_unmask (unsigned int irq)
974 {
975 struct mq_data *mqdata = get_irq_chipdata (irq);
976 u32 mask = 1 << (irq - mqdata->base.irq_base);
977 mqdata->base.regs->IC.interrupt_mask |= mask;
978 }
979
980 static int
981 mq_irq_type (unsigned int irq, unsigned int type)
982 {
983 struct mq_data *mqdata = get_irq_chipdata (irq);
984 int mask;
985
986 if ((irq < mqdata->base.irq_base + IRQ_MQ_GPIO_0) ||
987 (irq > mqdata->base.irq_base + IRQ_MQ_GPIO_2))
988 return 0;
989
990 mask = MQ_INTERRUPT_CONTROL_GPIO_0_INTERRUPT_POLARITY <<
991 (irq - mqdata->base.irq_base - IRQ_MQ_GPIO_0);
992
993 if (type & (__IRQT_HIGHLVL | __IRQT_RISEDGE))
994 mqdata->base.regs->IC.control |= mask;
995 else if (type & (__IRQT_LOWLVL | __IRQT_FALEDGE))
996 mqdata->base.regs->IC.control &= ~mask;
997
998 return 0;
999 }
1000
1001 static struct irqchip mq_irq_chip = {
1002 .ack = mq_irq_ack,
1003 .mask = mq_irq_mask,
1004 .unmask = mq_irq_unmask,
1005 .set_type = mq_irq_type,
1006 };
1007
1008 static int
1009 mq_irq_init (struct mq_data *mqdata)
1010 {
1011 int i;
1012
1013 /* Disable all IRQs */
1014 mqdata->base.regs->IC.control = 0;
1015 mqdata->base.regs->IC.interrupt_mask = 0;
1016 /* Clear IRQ status */
1017 mqdata->base.regs->IC.interrupt_status = 0xffffffff;
1018
1019 mqdata->base.irq_base = alloc_irq_space (MQ11xx_NUMIRQS);
1020 if (mqdata->base.irq_base < 0) {
1021 printk (KERN_ERR "There is no space for %d IRQs in core IRQ table!\n",
1022 MQ11xx_NUMIRQS);
1023 return -ENOMEM;
1024 }
1025
1026 debug_func ("base IRQ number is %d\n", mqdata->base.irq_base);
1027
1028 for (i = 0; i < MQ11xx_NUMIRQS; i++) {
1029 int irq = mqdata->base.irq_base + i;
1030 set_irq_flags (irq, IRQF_VALID);
1031 set_irq_chip (irq, &mq_irq_chip);
1032 set_irq_handler (irq, do_level_IRQ);
1033 set_irq_chipdata (irq, mqdata);
1034 }
1035
1036 i = (mqdata->base.regs->IC.control & MQ_INTERRUPT_CONTROL_INTERRUPT_POLARITY);
1037 set_irq_chained_handler (mqdata->irq_nr, mq_irq_demux);
1038 set_irq_type (mqdata->irq_nr, i ? IRQT_RISING : IRQT_FALLING);
1039 set_irq_data (mqdata->irq_nr, mqdata);
1040
1041 /* Globally enable IRQs from MediaQ */
1042 mqdata->base.regs->IC.control |= MQ_INTERRUPT_CONTROL_INTERRUPT_ENABLE;
1043
1044 return 0;
1045 }
1046
1047 static void
1048 mq_irq_free (struct mq_data *mqdata)
1049 {
1050 /* Disable all IRQs */
1051 mqdata->base.regs->IC.control = 0;
1052 mqdata->base.regs->IC.interrupt_mask = 0;
1053 /* Clear IRQ status */
1054 mqdata->base.regs->IC.interrupt_status = 0xffffffff;
1055
1056 set_irq_handler (mqdata->irq_nr, do_edge_IRQ);
1057
1058 free_irq_space (mqdata->base.irq_base, MQ11xx_NUMIRQS);
1059 }
1060 #endif
1061
1062 int
1063 mq_device_enum (struct mediaq11xx_base **list, int list_size)
1064 {
1065 int i, j;
1066
1067 if (!list_size)
1068 return 0;
1069
1070 spin_lock (&mq_device_list_lock);
1071 for (i = j = 0; i < MAX_MQ11XX_DEVICES; i++)
1072 if (mq_device_list [i]) {
1073 list [j++] = mq_device_list [i];
1074 if (j >= list_size)
1075 break;
1076 }
1077 spin_unlock (&mq_device_list_lock);
1078
1079 return j;
1080 }
1081 EXPORT_SYMBOL (mq_device_enum);
1082
1083 int
1084 mq_driver_get (void)
1085 {
1086 return try_module_get (THIS_MODULE) ? 0 : -ENXIO;
1087 }
1088 EXPORT_SYMBOL (mq_driver_get);
1089
1090 void
1091 mq_driver_put (void)
1092 {
1093 module_put (THIS_MODULE);
1094 }
1095 EXPORT_SYMBOL (mq_driver_put);
1096
1097 /*
1098 * Resources specified in resource table for this driver are:
1099 * 0: Synchronous RAM address (physical base + 0 on ARM arch)
1100 * 1: Asynchronous RAM address (physical base + 256K+2K on ARM arch)
1101 * 2: Registers address (physical base + 256K on ARM arch)
1102 * 3: The MediaQ IRQ number
1103 *
1104 * Also the platform_data field of the device should contain a pointer to
1105 * a mq11xx_platform_data structure, which contains the platform-specific
1106 * initialization data for MediaQ chip, the name of framebuffer driver
1107 * and the name of LCD driver.
1108 */
1109 static int
1110 mq_initialize (struct device *dev, int num_resources,
1111 struct resource *resource, int instance)
1112 {
1113 int i, j, k, rc, chipmask;
1114 struct mq_data *mqdata;
1115 struct mediaq11xx_init_data *init_data =
1116 (struct mediaq11xx_init_data *)dev->platform_data;
1117
1118 if (!init_data || num_resources != 4) {
1119 printk (KERN_ERR "mq11xx_base: Incorrect platform resources!\n");
1120 return -ENODEV;
1121 }
1122
1123 mqdata = kmalloc (sizeof (struct mq_data), GFP_KERNEL);
1124 if (!mqdata)
1125 return -ENOMEM;
1126 memset (mqdata, 0, sizeof (struct mq_data));
1127 dev_set_drvdata (dev, mqdata);
1128
1129 #define IOREMAP(v, n, el) \
1130 mqdata->base.v = ioremap (resource[n].start, \
1131 resource[n].end - resource[n].start + 1); \
1132 if (!mqdata->base.v) goto el; \
1133 mqdata->base.paddr_##v = resource[n].start;
1134
1135 IOREMAP (gfxram, 0, err0);
1136 IOREMAP (ram, 1, err1);
1137 IOREMAP (regs, 2, err2);
1138
1139 #undef IOREMAP
1140
1141 /* Check how much RAM is accessible through the unsynced window */
1142 mqdata->unsynced_ram_skip =
1143 (resource [0].end - resource [0].start) -
1144 (resource [1].end - resource [1].start);
1145 mqdata->base.ram -= mqdata->unsynced_ram_skip;
1146 mqdata->base.paddr_ram -= mqdata->unsynced_ram_skip;
1147
1148 mqdata->ndevices = MQ_SUBDEVS_REAL_COUNT;
1149 mqdata->devices = kmalloc (mqdata->ndevices *
1150 (sizeof (struct platform_device)), GFP_KERNEL);
1151 if (!mqdata->devices)
1152 goto err3;
1153
1154 mqdata->mq_init = init_data;
1155 if (mq11xx_init (mqdata)) {
1156 printk (KERN_ERR "MediaQ device initialization failed!\n");
1157 return -ENODEV;
1158 }
1159
1160 mqdata->irq_nr = resource[3].start;
1161 mqdata->base.set_GPIO = mq_set_GPIO;
1162 mqdata->base.get_GPIO = mq_get_GPIO;
1163 mqdata->base.set_power = mq_set_power;
1164 mqdata->base.get_power = mq_get_power;
1165 mqdata->base.alloc = mq_alloc;
1166 mqdata->base.free = mq_free;
1167
1168 /* Initialize memory manager */
1169 spin_lock_init (&mqdata->mem_lock);
1170 mqdata->nfreeblocks = 1;
1171 mqdata->maxfreeblocks = MEMBLOCK_MINCOUNT;
1172 mqdata->freelist = kmalloc (MEMBLOCK_MINCOUNT * sizeof (struct mq_freemem_list),
1173 GFP_KERNEL);
1174 mqdata->freelist [0].addr = 0;
1175 mqdata->freelist [0].size = MQ11xx_FB_SIZE;
1176
1177 #if defined MQ_IRQ_MULTIPLEX
1178 if ((mqdata->irq_nr != -1) && mq_irq_init (mqdata))
1179 goto err4;
1180 #endif
1181
1182 for (i = j = 0; j < MQ_SUBDEVS_COUNT; i++) {
1183 struct platform_device *sdev = &mqdata->devices[i];
1184 const struct mq_block *blk = &mq_blocks[j];
1185 struct resource *res;
1186 int old_j, k;
1187
1188 memset (sdev, 0, sizeof (struct platform_device));
1189 sdev->id = blk->id.id; /* placeholder id */
1190 sdev->name = blk->name;
1191 sdev->dev.parent = dev;
1192 sdev->dev.release = mq_release;
1193 sdev->dev.platform_data = &mqdata->base;
1194
1195 /* Count number of resources */
1196 sdev->num_resources = 2;
1197 old_j = j;
1198 while (mq_blocks [++j].id.id == sdev->id)
1199 sdev->num_resources += 2;
1200
1201 res = kmalloc (sdev->num_resources * sizeof (struct resource), GFP_KERNEL);
1202 sdev->resource = res;
1203 memset (res, 0, sdev->num_resources * sizeof (struct resource));
1204
1205 for (j = old_j, k = 0; mq_blocks [j].id.id == sdev->id; j++) {
1206 blk = &mq_blocks[j];
1207 res[k].start = resource[2].start + blk->start;
1208 res[k].end = resource[2].start + blk->end;
1209 res[k].parent = &resource[2];
1210 res[k++].flags = IORESOURCE_MEM;
1211 res[k].start = (unsigned)mqdata->base.regs + blk->start;
1212 res[k].end = (unsigned)mqdata->base.regs + blk->end;
1213 res[k++].flags = 0;
1214 }
1215
1216 mqdata->power_on [i] = 1;;
1217 }
1218
1219 /* Second pass */
1220 chipmask = 1 << mqdata->base.chip;
1221 for (i = j = k = 0; j < MQ_SUBDEVS_COUNT; i++) {
1222 struct platform_device *sdev = &mqdata->devices[i];
1223 const struct mq_block *blk = &mq_blocks[j];
1224
1225 while (mq_blocks [++j].id.id == sdev->id)
1226 ;
1227
1228 /* Power off all subdevices */
1229 mq_power_off (&mqdata->base, sdev->id);
1230
1231 if (!(blk->mask & chipmask))
1232 continue;
1233
1234 sdev->id = instance;
1235 rc = platform_device_register (sdev);
1236 if (rc) {
1237 printk (KERN_ERR "Failed to register MediaQ subdevice `%s', code %d\n",
1238 blk->name, rc);
1239 goto err5;
1240 }
1241 }
1242
1243 printk (KERN_INFO "MediaQ %s chip detected, ", mqdata->base.chipname);
1244 if (mqdata->base.irq_base)
1245 printk ("base IRQ %d\n", mqdata->base.irq_base);
1246 else
1247 printk ("\n");
1248
1249 spin_lock (&mq_device_list_lock);
1250 for (i = 0; i < MAX_MQ11XX_DEVICES; i++)
1251 if (!mq_device_list [i]) {
1252 mq_device_list [i] = &mqdata->base;
1253 break;
1254 }
1255 spin_unlock (&mq_device_list_lock);
1256
1257 return 0;
1258
1259 err5: while (--i >= 0) {
1260 platform_device_unregister (&mqdata->devices[i]);
1261 kfree (mqdata->devices[i].resource);
1262 }
1263
1264 #if defined MQ_IRQ_MULTIPLEX
1265 if (mqdata->irq_nr != -1)
1266 mq_irq_free (mqdata);
1267 #endif
1268 err4: kfree (mqdata->devices);
1269 err3: iounmap ((void *)mqdata->base.regs);
1270 err2: iounmap ((void *)mqdata->base.ram);
1271 err1: iounmap (mqdata->base.gfxram);
1272 err0: kfree (mqdata);
1273
1274 printk (KERN_ERR "MediaQ base SoC driver initialization failed\n");
1275
1276 return -ENOMEM;
1277 }
1278
1279 static int
1280 mq_finalize (struct device *dev)
1281 {
1282 int i;
1283 struct mq_data *mqdata = dev_get_drvdata (dev);
1284
1285 spin_lock (&mq_device_list_lock);
1286 for (i = 0; i < MAX_MQ11XX_DEVICES; i++)
1287 if (mq_device_list [i] == &mqdata->base) {
1288 mq_device_list [i] = NULL;
1289 break;
1290 }
1291 spin_unlock (&mq_device_list_lock);
1292
1293 for (i = 0; i < mqdata->ndevices; i++) {
1294 platform_device_unregister (&mqdata->devices[i]);
1295 kfree (mqdata->devices[i].resource);
1296 }
1297
1298 #if defined MQ_IRQ_MULTIPLEX
1299 if (mqdata->irq_nr != -1)
1300 mq_irq_free (mqdata);
1301 #endif
1302
1303 kfree (mqdata->devices);
1304
1305 iounmap ((void *)mqdata->base.regs);
1306 iounmap ((void *)mqdata->base.ram);
1307 iounmap (mqdata->base.gfxram);
1308
1309 kfree (mqdata);
1310
1311 return 0;
1312 }
1313
1314 /* This is the platform device handler. If MediaQ is connected to a different
1315 * bus type (e.g. PCI) a similar device_driver structure should be registered
1316 * for that bus. For now this is not implemented.
1317 */
1318
1319 static int
1320 mq_probe (struct device *dev)
1321 {
1322 struct platform_device *pdev = to_platform_device (dev);
1323 return mq_initialize (dev, pdev->num_resources, pdev->resource,
1324 pdev->id);
1325 }
1326
1327 static int
1328 mq_remove (struct device *dev)
1329 {
1330 return mq_finalize (dev);
1331 }
1332
1333 static void
1334 mq_shutdown (struct device *dev)
1335 {
1336 //struct mq_data *mqdata = dev_get_drvdata (dev);
1337 }
1338
1339 static int
1340 mq_suspend (struct device *dev, pm_message_t state)
1341 {
1342 //struct mq_data *mqdata = dev_get_drvdata (dev);
1343 return 0;
1344 }
1345
1346 static int
1347 mq_resume (struct device *dev)
1348 {
1349 //struct mq_data *mqdata = dev_get_drvdata (dev);
1350 return 0;
1351 }
1352
1353 static struct device_driver mq_device_driver = {
1354 .name = "mq11xx",
1355 .bus = &platform_bus_type,
1356
1357 .probe = mq_probe,
1358 .remove = mq_remove,
1359 .suspend = mq_suspend,
1360 .resume = mq_resume,
1361 .shutdown = mq_shutdown,
1362 };
1363
1364 static int __init
1365 mq_base_init (void)
1366 {
1367 return driver_register (&mq_device_driver);
1368 }
1369
1370 static void __exit
1371 mq_base_exit (void)
1372 {
1373 driver_unregister (&mq_device_driver);
1374 }
1375
1376 #ifdef MODULE
1377 module_init (mq_base_init);
1378 #else /* start early for dependencies */
1379 subsys_initcall (mq_base_init);
1380 #endif
1381 module_exit (mq_base_exit)
1382
1383 MODULE_AUTHOR("Andrew Zabolotny <anpaza@mail.ru>");
1384 MODULE_DESCRIPTION("MediaQ 1100/1132 base SoC support");
1385 MODULE_LICENSE("GPL");
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