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[hh.org.git] / drivers / video / aty / aty128fb.c
blob276a21530b9527c4e5dbf1d4624ea116488f5163
1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
3 *
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
6 *
7 * Ani Joshi / Jeff Garzik
8 * - Code cleanup
9 *
10 * Michel Danzer <michdaen@iiic.ethz.ch>
11 * - 15/16 bit cleanup
12 * - fix panning
13 *
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
17 *
18 * Andreas Hundt <andi@convergence.de>
19 * - FB_ACTIVATE fixes
20 *
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
24 *
25 * Paul Mundt
26 * - PCI hotplug
27 *
28 * Jon Smirl <jonsmirl@yahoo.com>
29 * - PCI ID update
30 * - replace ROM BIOS search
31 *
32 * Based off of Geert's atyfb.c and vfb.c.
33 *
34 * TODO:
35 * - monitor sensing (DDC)
36 * - virtual display
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
39 *
40 * Please cc: your patches to brad@neruo.com.
41 */
42
43 /*
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
46 */
47
48
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
54 #include <linux/mm.h>
55 #include <linux/slab.h>
56 #include <linux/vmalloc.h>
57 #include <linux/delay.h>
58 #include <linux/interrupt.h>
59 #include <asm/uaccess.h>
60 #include <linux/fb.h>
61 #include <linux/init.h>
62 #include <linux/pci.h>
63 #include <linux/ioport.h>
64 #include <linux/console.h>
65 #include <linux/backlight.h>
66 #include <asm/io.h>
67
68 #ifdef CONFIG_PPC_PMAC
69 #include <asm/machdep.h>
70 #include <asm/pmac_feature.h>
71 #include <asm/prom.h>
72 #include <asm/pci-bridge.h>
73 #include "../macmodes.h"
74 #endif
75
76 #ifdef CONFIG_PMAC_BACKLIGHT
77 #include <asm/backlight.h>
78 #endif
79
80 #ifdef CONFIG_BOOTX_TEXT
81 #include <asm/btext.h>
82 #endif /* CONFIG_BOOTX_TEXT */
83
84 #ifdef CONFIG_MTRR
85 #include <asm/mtrr.h>
86 #endif
87
88 #include <video/aty128.h>
89
90 /* Debug flag */
91 #undef DEBUG
92
93 #ifdef DEBUG
94 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
95 #else
96 #define DBG(fmt, args...)
97 #endif
98
99 #ifndef CONFIG_PPC_PMAC
100 /* default mode */
101 static struct fb_var_screeninfo default_var __devinitdata = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
107 };
108
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
119 };
120 #endif /* CONFIG_PPC_PMAC */
121
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode __devinitdata = {
125 .refresh = 60,
126 .xres = 640,
127 .yres = 480,
128 .pixclock = 39722,
129 .left_margin = 48,
130 .right_margin = 16,
131 .upper_margin = 33,
132 .lower_margin = 10,
133 .hsync_len = 96,
134 .vsync_len = 2,
135 .sync = 0,
136 .vmode = FB_VMODE_NONINTERLACED
137 };
138
139 /* Chip generations */
140 enum {
141 rage_128,
142 rage_128_pci,
143 rage_128_pro,
144 rage_128_pro_pci,
145 rage_M3,
146 rage_M3_pci,
147 rage_M4,
148 rage_128_ultra,
149 };
150
151 /* Must match above enum */
152 static const char *r128_family[] __devinitdata = {
153 "AGP",
154 "PCI",
155 "PRO AGP",
156 "PRO PCI",
157 "M3 AGP",
158 "M3 PCI",
159 "M4 AGP",
160 "Ultra AGP",
161 };
162
163 /*
164 * PCI driver prototypes
165 */
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
172
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
269 { 0, }
270 };
271
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
273
274 static struct pci_driver aty128fb_driver = {
275 .name = "aty128fb",
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = __devexit_p(aty128_remove),
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
281 };
282
283 /* packed BIOS settings */
284 #ifndef CONFIG_PPC
285 typedef struct {
286 u8 clock_chip_type;
287 u8 struct_size;
288 u8 accelerator_entry;
289 u8 VGA_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
292 u16 XCLK;
293 u16 MCLK;
294 u8 num_PLL_blocks;
295 u8 size_PLL_blocks;
296 u16 PCLK_ref_freq;
297 u16 PCLK_ref_divider;
298 u32 PCLK_min_freq;
299 u32 PCLK_max_freq;
300 u16 MCLK_ref_freq;
301 u16 MCLK_ref_divider;
302 u32 MCLK_min_freq;
303 u32 MCLK_max_freq;
304 u16 XCLK_ref_freq;
305 u16 XCLK_ref_divider;
306 u32 XCLK_min_freq;
307 u32 XCLK_max_freq;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
310
311 /* onboard memory information */
312 struct aty128_meminfo {
313 u8 ML;
314 u8 MB;
315 u8 Trcd;
316 u8 Trp;
317 u8 Twr;
318 u8 CL;
319 u8 Tr2w;
320 u8 LoopLatency;
321 u8 DspOn;
322 u8 Rloop;
323 const char *name;
324 };
325
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331 static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333 static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
335
336 static struct fb_fix_screeninfo aty128fb_fix __devinitdata = {
337 .id = "ATY Rage128",
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
340 .xpanstep = 8,
341 .ypanstep = 1,
342 .mmio_len = 0x2000,
343 .accel = FB_ACCEL_ATI_RAGE128,
344 };
345
346 static char *mode_option __devinitdata = NULL;
347
348 #ifdef CONFIG_PPC_PMAC
349 static int default_vmode __devinitdata = VMODE_1024_768_60;
350 static int default_cmode __devinitdata = CMODE_8;
351 #endif
352
353 static int default_crt_on __devinitdata = 0;
354 static int default_lcd_on __devinitdata = 1;
355
356 #ifdef CONFIG_MTRR
357 static int mtrr = 1;
358 #endif
359
360 /* PLL constants */
361 struct aty128_constants {
362 u32 ref_clk;
363 u32 ppll_min;
364 u32 ppll_max;
365 u32 ref_divider;
366 u32 xclk;
367 u32 fifo_width;
368 u32 fifo_depth;
369 };
370
371 struct aty128_crtc {
372 u32 gen_cntl;
373 u32 h_total, h_sync_strt_wid;
374 u32 v_total, v_sync_strt_wid;
375 u32 pitch;
376 u32 offset, offset_cntl;
377 u32 xoffset, yoffset;
378 u32 vxres, vyres;
379 u32 depth, bpp;
380 };
381
382 struct aty128_pll {
383 u32 post_divider;
384 u32 feedback_divider;
385 u32 vclk;
386 };
387
388 struct aty128_ddafifo {
389 u32 dda_config;
390 u32 dda_on_off;
391 };
392
393 /* register values for a specific mode */
394 struct aty128fb_par {
395 struct aty128_crtc crtc;
396 struct aty128_pll pll;
397 struct aty128_ddafifo fifo_reg;
398 u32 accel_flags;
399 struct aty128_constants constants; /* PLL and others */
400 void __iomem *regbase; /* remapped mmio */
401 u32 vram_size; /* onboard video ram */
402 int chip_gen;
403 const struct aty128_meminfo *mem; /* onboard mem info */
404 #ifdef CONFIG_MTRR
405 struct { int vram; int vram_valid; } mtrr;
406 #endif
407 int blitter_may_be_busy;
408 int fifo_slots; /* free slots in FIFO (64 max) */
409
410 int pm_reg;
411 int crt_on, lcd_on;
412 struct pci_dev *pdev;
413 struct fb_info *next;
414 int asleep;
415 int lock_blank;
416
417 u8 red[32]; /* see aty128fb_setcolreg */
418 u8 green[64];
419 u8 blue[32];
420 u32 pseudo_palette[16]; /* used for TRUECOLOR */
421 };
422
423
424 #define round_div(n, d) ((n+(d/2))/d)
425
426 static int aty128fb_check_var(struct fb_var_screeninfo *var,
427 struct fb_info *info);
428 static int aty128fb_set_par(struct fb_info *info);
429 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
430 u_int transp, struct fb_info *info);
431 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
432 struct fb_info *fb);
433 static int aty128fb_blank(int blank, struct fb_info *fb);
434 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
435 static int aty128fb_sync(struct fb_info *info);
436
437 /*
438 * Internal routines
439 */
440
441 static int aty128_encode_var(struct fb_var_screeninfo *var,
442 const struct aty128fb_par *par);
443 static int aty128_decode_var(struct fb_var_screeninfo *var,
444 struct aty128fb_par *par);
445 #if 0
446 static void __devinit aty128_get_pllinfo(struct aty128fb_par *par,
447 void __iomem *bios);
448 static void __devinit __iomem *aty128_map_ROM(struct pci_dev *pdev, const struct aty128fb_par *par);
449 #endif
450 static void aty128_timings(struct aty128fb_par *par);
451 static void aty128_init_engine(struct aty128fb_par *par);
452 static void aty128_reset_engine(const struct aty128fb_par *par);
453 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
454 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
455 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
456 static void wait_for_idle(struct aty128fb_par *par);
457 static u32 depth_to_dst(u32 depth);
458
459 #ifdef CONFIG_FB_ATY128_BACKLIGHT
460 static void aty128_bl_set_power(struct fb_info *info, int power);
461 #endif
462
463 #define BIOS_IN8(v) (readb(bios + (v)))
464 #define BIOS_IN16(v) (readb(bios + (v)) | \
465 (readb(bios + (v) + 1) << 8))
466 #define BIOS_IN32(v) (readb(bios + (v)) | \
467 (readb(bios + (v) + 1) << 8) | \
468 (readb(bios + (v) + 2) << 16) | \
469 (readb(bios + (v) + 3) << 24))
470
471
472 static struct fb_ops aty128fb_ops = {
473 .owner = THIS_MODULE,
474 .fb_check_var = aty128fb_check_var,
475 .fb_set_par = aty128fb_set_par,
476 .fb_setcolreg = aty128fb_setcolreg,
477 .fb_pan_display = aty128fb_pan_display,
478 .fb_blank = aty128fb_blank,
479 .fb_ioctl = aty128fb_ioctl,
480 .fb_sync = aty128fb_sync,
481 .fb_fillrect = cfb_fillrect,
482 .fb_copyarea = cfb_copyarea,
483 .fb_imageblit = cfb_imageblit,
484 };
485
486 /*
487 * Functions to read from/write to the mmio registers
488 * - endian conversions may possibly be avoided by
489 * using the other register aperture. TODO.
490 */
491 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
492 const struct aty128fb_par *par)
493 {
494 return readl (par->regbase + regindex);
495 }
496
497 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
498 const struct aty128fb_par *par)
499 {
500 writel (val, par->regbase + regindex);
501 }
502
503 static inline u8 _aty_ld_8(unsigned int regindex,
504 const struct aty128fb_par *par)
505 {
506 return readb (par->regbase + regindex);
507 }
508
509 static inline void _aty_st_8(unsigned int regindex, u8 val,
510 const struct aty128fb_par *par)
511 {
512 writeb (val, par->regbase + regindex);
513 }
514
515 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
516 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
517 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
518 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
519
520 /*
521 * Functions to read from/write to the pll registers
522 */
523
524 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
525 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
526
527
528 static u32 _aty_ld_pll(unsigned int pll_index,
529 const struct aty128fb_par *par)
530 {
531 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
532 return aty_ld_le32(CLOCK_CNTL_DATA);
533 }
534
535
536 static void _aty_st_pll(unsigned int pll_index, u32 val,
537 const struct aty128fb_par *par)
538 {
539 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
540 aty_st_le32(CLOCK_CNTL_DATA, val);
541 }
542
543
544 /* return true when the PLL has completed an atomic update */
545 static int aty_pll_readupdate(const struct aty128fb_par *par)
546 {
547 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
548 }
549
550
551 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
552 {
553 unsigned long timeout = jiffies + HZ/100; // should be more than enough
554 int reset = 1;
555
556 while (time_before(jiffies, timeout))
557 if (aty_pll_readupdate(par)) {
558 reset = 0;
559 break;
560 }
561
562 if (reset) /* reset engine?? */
563 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
564 }
565
566
567 /* tell PLL to update */
568 static void aty_pll_writeupdate(const struct aty128fb_par *par)
569 {
570 aty_pll_wait_readupdate(par);
571
572 aty_st_pll(PPLL_REF_DIV,
573 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
574 }
575
576
577 /* write to the scratch register to test r/w functionality */
578 static int __devinit register_test(const struct aty128fb_par *par)
579 {
580 u32 val;
581 int flag = 0;
582
583 val = aty_ld_le32(BIOS_0_SCRATCH);
584
585 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
586 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
587 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
588
589 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
590 flag = 1;
591 }
592
593 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
594 return flag;
595 }
596
597
598 /*
599 * Accelerator engine functions
600 */
601 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
602 {
603 int i;
604
605 for (;;) {
606 for (i = 0; i < 2000000; i++) {
607 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
608 if (par->fifo_slots >= entries)
609 return;
610 }
611 aty128_reset_engine(par);
612 }
613 }
614
615
616 static void wait_for_idle(struct aty128fb_par *par)
617 {
618 int i;
619
620 do_wait_for_fifo(64, par);
621
622 for (;;) {
623 for (i = 0; i < 2000000; i++) {
624 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
625 aty128_flush_pixel_cache(par);
626 par->blitter_may_be_busy = 0;
627 return;
628 }
629 }
630 aty128_reset_engine(par);
631 }
632 }
633
634
635 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
636 {
637 if (par->fifo_slots < entries)
638 do_wait_for_fifo(64, par);
639 par->fifo_slots -= entries;
640 }
641
642
643 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
644 {
645 int i;
646 u32 tmp;
647
648 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
649 tmp &= ~(0x00ff);
650 tmp |= 0x00ff;
651 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
652
653 for (i = 0; i < 2000000; i++)
654 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
655 break;
656 }
657
658
659 static void aty128_reset_engine(const struct aty128fb_par *par)
660 {
661 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
662
663 aty128_flush_pixel_cache(par);
664
665 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
666 mclk_cntl = aty_ld_pll(MCLK_CNTL);
667
668 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
669
670 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
671 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
672 aty_ld_le32(GEN_RESET_CNTL);
673 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
674 aty_ld_le32(GEN_RESET_CNTL);
675
676 aty_st_pll(MCLK_CNTL, mclk_cntl);
677 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
678 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
679
680 /* use old pio mode */
681 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
682
683 DBG("engine reset");
684 }
685
686
687 static void aty128_init_engine(struct aty128fb_par *par)
688 {
689 u32 pitch_value;
690
691 wait_for_idle(par);
692
693 /* 3D scaler not spoken here */
694 wait_for_fifo(1, par);
695 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
696
697 aty128_reset_engine(par);
698
699 pitch_value = par->crtc.pitch;
700 if (par->crtc.bpp == 24) {
701 pitch_value = pitch_value * 3;
702 }
703
704 wait_for_fifo(4, par);
705 /* setup engine offset registers */
706 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
707
708 /* setup engine pitch registers */
709 aty_st_le32(DEFAULT_PITCH, pitch_value);
710
711 /* set the default scissor register to max dimensions */
712 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
713
714 /* set the drawing controls registers */
715 aty_st_le32(DP_GUI_MASTER_CNTL,
716 GMC_SRC_PITCH_OFFSET_DEFAULT |
717 GMC_DST_PITCH_OFFSET_DEFAULT |
718 GMC_SRC_CLIP_DEFAULT |
719 GMC_DST_CLIP_DEFAULT |
720 GMC_BRUSH_SOLIDCOLOR |
721 (depth_to_dst(par->crtc.depth) << 8) |
722 GMC_SRC_DSTCOLOR |
723 GMC_BYTE_ORDER_MSB_TO_LSB |
724 GMC_DP_CONVERSION_TEMP_6500 |
725 ROP3_PATCOPY |
726 GMC_DP_SRC_RECT |
727 GMC_3D_FCN_EN_CLR |
728 GMC_DST_CLR_CMP_FCN_CLEAR |
729 GMC_AUX_CLIP_CLEAR |
730 GMC_WRITE_MASK_SET);
731
732 wait_for_fifo(8, par);
733 /* clear the line drawing registers */
734 aty_st_le32(DST_BRES_ERR, 0);
735 aty_st_le32(DST_BRES_INC, 0);
736 aty_st_le32(DST_BRES_DEC, 0);
737
738 /* set brush color registers */
739 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
740 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
741
742 /* set source color registers */
743 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
744 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
745
746 /* default write mask */
747 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
748
749 /* Wait for all the writes to be completed before returning */
750 wait_for_idle(par);
751 }
752
753
754 /* convert depth values to their register representation */
755 static u32 depth_to_dst(u32 depth)
756 {
757 if (depth <= 8)
758 return DST_8BPP;
759 else if (depth <= 15)
760 return DST_15BPP;
761 else if (depth == 16)
762 return DST_16BPP;
763 else if (depth <= 24)
764 return DST_24BPP;
765 else if (depth <= 32)
766 return DST_32BPP;
767
768 return -EINVAL;
769 }
770
771 /*
772 * PLL informations retreival
773 */
774
775
776 #ifndef __sparc__
777 static void __iomem * __devinit aty128_map_ROM(const struct aty128fb_par *par, struct pci_dev *dev)
778 {
779 u16 dptr;
780 u8 rom_type;
781 void __iomem *bios;
782 size_t rom_size;
783
784 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
785 unsigned int temp;
786 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
787 temp &= 0x00ffffffu;
788 temp |= 0x04 << 24;
789 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
790 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
791
792 bios = pci_map_rom(dev, &rom_size);
793
794 if (!bios) {
795 printk(KERN_ERR "aty128fb: ROM failed to map\n");
796 return NULL;
797 }
798
799 /* Very simple test to make sure it appeared */
800 if (BIOS_IN16(0) != 0xaa55) {
801 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
802 " be 0xaa55\n", BIOS_IN16(0));
803 goto failed;
804 }
805
806 /* Look for the PCI data to check the ROM type */
807 dptr = BIOS_IN16(0x18);
808
809 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
810 * for now, until I've verified this works everywhere. The goal here is more
811 * to phase out Open Firmware images.
812 *
813 * Currently, we only look at the first PCI data, we could iteratre and deal with
814 * them all, and we should use fb_bios_start relative to start of image and not
815 * relative start of ROM, but so far, I never found a dual-image ATI card
816 *
817 * typedef struct {
818 * u32 signature; + 0x00
819 * u16 vendor; + 0x04
820 * u16 device; + 0x06
821 * u16 reserved_1; + 0x08
822 * u16 dlen; + 0x0a
823 * u8 drevision; + 0x0c
824 * u8 class_hi; + 0x0d
825 * u16 class_lo; + 0x0e
826 * u16 ilen; + 0x10
827 * u16 irevision; + 0x12
828 * u8 type; + 0x14
829 * u8 indicator; + 0x15
830 * u16 reserved_2; + 0x16
831 * } pci_data_t;
832 */
833 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
834 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
835 BIOS_IN32(dptr));
836 goto anyway;
837 }
838 rom_type = BIOS_IN8(dptr + 0x14);
839 switch(rom_type) {
840 case 0:
841 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
842 break;
843 case 1:
844 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
845 goto failed;
846 case 2:
847 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
848 goto failed;
849 default:
850 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n", rom_type);
851 goto failed;
852 }
853 anyway:
854 return bios;
855
856 failed:
857 pci_unmap_rom(dev, bios);
858 return NULL;
859 }
860
861 static void __devinit aty128_get_pllinfo(struct aty128fb_par *par, unsigned char __iomem *bios)
862 {
863 unsigned int bios_hdr;
864 unsigned int bios_pll;
865
866 bios_hdr = BIOS_IN16(0x48);
867 bios_pll = BIOS_IN16(bios_hdr + 0x30);
868
869 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
870 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
871 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
872 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
873 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
874
875 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
876 par->constants.ppll_max, par->constants.ppll_min,
877 par->constants.xclk, par->constants.ref_divider,
878 par->constants.ref_clk);
879
880 }
881
882 #ifdef CONFIG_X86
883 static void __iomem * __devinit aty128_find_mem_vbios(struct aty128fb_par *par)
884 {
885 /* I simplified this code as we used to miss the signatures in
886 * a lot of case. It's now closer to XFree, we just don't check
887 * for signatures at all... Something better will have to be done
888 * if we end up having conflicts
889 */
890 u32 segstart;
891 unsigned char __iomem *rom_base = NULL;
892
893 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
894 rom_base = ioremap(segstart, 0x10000);
895 if (rom_base == NULL)
896 return NULL;
897 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
898 break;
899 iounmap(rom_base);
900 rom_base = NULL;
901 }
902 return rom_base;
903 }
904 #endif
905 #endif /* ndef(__sparc__) */
906
907 /* fill in known card constants if pll_block is not available */
908 static void __devinit aty128_timings(struct aty128fb_par *par)
909 {
910 #ifdef CONFIG_PPC_OF
911 /* instead of a table lookup, assume OF has properly
912 * setup the PLL registers and use their values
913 * to set the XCLK values and reference divider values */
914
915 u32 x_mpll_ref_fb_div;
916 u32 xclk_cntl;
917 u32 Nx, M;
918 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
919 #endif
920
921 if (!par->constants.ref_clk)
922 par->constants.ref_clk = 2950;
923
924 #ifdef CONFIG_PPC_OF
925 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
926 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
927 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
928 M = x_mpll_ref_fb_div & 0x0000ff;
929
930 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
931 (M * PostDivSet[xclk_cntl]));
932
933 par->constants.ref_divider =
934 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
935 #endif
936
937 if (!par->constants.ref_divider) {
938 par->constants.ref_divider = 0x3b;
939
940 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
941 aty_pll_writeupdate(par);
942 }
943 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
944 aty_pll_writeupdate(par);
945
946 /* from documentation */
947 if (!par->constants.ppll_min)
948 par->constants.ppll_min = 12500;
949 if (!par->constants.ppll_max)
950 par->constants.ppll_max = 25000; /* 23000 on some cards? */
951 if (!par->constants.xclk)
952 par->constants.xclk = 0x1d4d; /* same as mclk */
953
954 par->constants.fifo_width = 128;
955 par->constants.fifo_depth = 32;
956
957 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
958 case 0:
959 par->mem = &sdr_128;
960 break;
961 case 1:
962 par->mem = &sdr_sgram;
963 break;
964 case 2:
965 par->mem = &ddr_sgram;
966 break;
967 default:
968 par->mem = &sdr_sgram;
969 }
970 }
971
972
973
974 /*
975 * CRTC programming
976 */
977
978 /* Program the CRTC registers */
979 static void aty128_set_crtc(const struct aty128_crtc *crtc,
980 const struct aty128fb_par *par)
981 {
982 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
983 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
984 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
985 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
986 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
987 aty_st_le32(CRTC_PITCH, crtc->pitch);
988 aty_st_le32(CRTC_OFFSET, crtc->offset);
989 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
990 /* Disable ATOMIC updating. Is this the right place? */
991 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
992 }
993
994
995 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
996 struct aty128_crtc *crtc,
997 const struct aty128fb_par *par)
998 {
999 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1000 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1001 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1002 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1003 u32 depth, bytpp;
1004 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1005
1006 /* input */
1007 xres = var->xres;
1008 yres = var->yres;
1009 vxres = var->xres_virtual;
1010 vyres = var->yres_virtual;
1011 xoffset = var->xoffset;
1012 yoffset = var->yoffset;
1013 bpp = var->bits_per_pixel;
1014 left = var->left_margin;
1015 right = var->right_margin;
1016 upper = var->upper_margin;
1017 lower = var->lower_margin;
1018 hslen = var->hsync_len;
1019 vslen = var->vsync_len;
1020 sync = var->sync;
1021 vmode = var->vmode;
1022
1023 if (bpp != 16)
1024 depth = bpp;
1025 else
1026 depth = (var->green.length == 6) ? 16 : 15;
1027
1028 /* check for mode eligibility
1029 * accept only non interlaced modes */
1030 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1031 return -EINVAL;
1032
1033 /* convert (and round up) and validate */
1034 xres = (xres + 7) & ~7;
1035 xoffset = (xoffset + 7) & ~7;
1036
1037 if (vxres < xres + xoffset)
1038 vxres = xres + xoffset;
1039
1040 if (vyres < yres + yoffset)
1041 vyres = yres + yoffset;
1042
1043 /* convert depth into ATI register depth */
1044 dst = depth_to_dst(depth);
1045
1046 if (dst == -EINVAL) {
1047 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1048 return -EINVAL;
1049 }
1050
1051 /* convert register depth to bytes per pixel */
1052 bytpp = mode_bytpp[dst];
1053
1054 /* make sure there is enough video ram for the mode */
1055 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1056 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1057 return -EINVAL;
1058 }
1059
1060 h_disp = (xres >> 3) - 1;
1061 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1062
1063 v_disp = yres - 1;
1064 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1065
1066 /* check to make sure h_total and v_total are in range */
1067 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1068 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1069 return -EINVAL;
1070 }
1071
1072 h_sync_wid = (hslen + 7) >> 3;
1073 if (h_sync_wid == 0)
1074 h_sync_wid = 1;
1075 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1076 h_sync_wid = 0x3f;
1077
1078 h_sync_strt = (h_disp << 3) + right;
1079
1080 v_sync_wid = vslen;
1081 if (v_sync_wid == 0)
1082 v_sync_wid = 1;
1083 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1084 v_sync_wid = 0x1f;
1085
1086 v_sync_strt = v_disp + lower;
1087
1088 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1089 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1090
1091 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1092
1093 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1094
1095 crtc->h_total = h_total | (h_disp << 16);
1096 crtc->v_total = v_total | (v_disp << 16);
1097
1098 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1099 (h_sync_pol << 23);
1100 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1101 (v_sync_pol << 23);
1102
1103 crtc->pitch = vxres >> 3;
1104
1105 crtc->offset = 0;
1106
1107 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1108 crtc->offset_cntl = 0x00010000;
1109 else
1110 crtc->offset_cntl = 0;
1111
1112 crtc->vxres = vxres;
1113 crtc->vyres = vyres;
1114 crtc->xoffset = xoffset;
1115 crtc->yoffset = yoffset;
1116 crtc->depth = depth;
1117 crtc->bpp = bpp;
1118
1119 return 0;
1120 }
1121
1122
1123 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1124 {
1125
1126 /* fill in pixel info */
1127 var->red.msb_right = 0;
1128 var->green.msb_right = 0;
1129 var->blue.offset = 0;
1130 var->blue.msb_right = 0;
1131 var->transp.offset = 0;
1132 var->transp.length = 0;
1133 var->transp.msb_right = 0;
1134 switch (pix_width) {
1135 case CRTC_PIX_WIDTH_8BPP:
1136 var->bits_per_pixel = 8;
1137 var->red.offset = 0;
1138 var->red.length = 8;
1139 var->green.offset = 0;
1140 var->green.length = 8;
1141 var->blue.length = 8;
1142 break;
1143 case CRTC_PIX_WIDTH_15BPP:
1144 var->bits_per_pixel = 16;
1145 var->red.offset = 10;
1146 var->red.length = 5;
1147 var->green.offset = 5;
1148 var->green.length = 5;
1149 var->blue.length = 5;
1150 break;
1151 case CRTC_PIX_WIDTH_16BPP:
1152 var->bits_per_pixel = 16;
1153 var->red.offset = 11;
1154 var->red.length = 5;
1155 var->green.offset = 5;
1156 var->green.length = 6;
1157 var->blue.length = 5;
1158 break;
1159 case CRTC_PIX_WIDTH_24BPP:
1160 var->bits_per_pixel = 24;
1161 var->red.offset = 16;
1162 var->red.length = 8;
1163 var->green.offset = 8;
1164 var->green.length = 8;
1165 var->blue.length = 8;
1166 break;
1167 case CRTC_PIX_WIDTH_32BPP:
1168 var->bits_per_pixel = 32;
1169 var->red.offset = 16;
1170 var->red.length = 8;
1171 var->green.offset = 8;
1172 var->green.length = 8;
1173 var->blue.length = 8;
1174 var->transp.offset = 24;
1175 var->transp.length = 8;
1176 break;
1177 default:
1178 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1179 return -EINVAL;
1180 }
1181
1182 return 0;
1183 }
1184
1185
1186 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1187 struct fb_var_screeninfo *var)
1188 {
1189 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1190 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1191 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1192 u32 pix_width;
1193
1194 /* fun with masking */
1195 h_total = crtc->h_total & 0x1ff;
1196 h_disp = (crtc->h_total >> 16) & 0xff;
1197 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1198 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1199 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1200 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1201 v_total = crtc->v_total & 0x7ff;
1202 v_disp = (crtc->v_total >> 16) & 0x7ff;
1203 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1204 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1205 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1206 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1207 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1208
1209 /* do conversions */
1210 xres = (h_disp + 1) << 3;
1211 yres = v_disp + 1;
1212 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1213 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1214 hslen = h_sync_wid << 3;
1215 upper = v_total - v_sync_strt - v_sync_wid;
1216 lower = v_sync_strt - v_disp;
1217 vslen = v_sync_wid;
1218 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1219 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1220 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1221
1222 aty128_pix_width_to_var(pix_width, var);
1223
1224 var->xres = xres;
1225 var->yres = yres;
1226 var->xres_virtual = crtc->vxres;
1227 var->yres_virtual = crtc->vyres;
1228 var->xoffset = crtc->xoffset;
1229 var->yoffset = crtc->yoffset;
1230 var->left_margin = left;
1231 var->right_margin = right;
1232 var->upper_margin = upper;
1233 var->lower_margin = lower;
1234 var->hsync_len = hslen;
1235 var->vsync_len = vslen;
1236 var->sync = sync;
1237 var->vmode = FB_VMODE_NONINTERLACED;
1238
1239 return 0;
1240 }
1241
1242 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1243 {
1244 if (on) {
1245 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1246 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1247 } else
1248 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1249 }
1250
1251 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1252 {
1253 u32 reg;
1254 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1255 struct fb_info *info = pci_get_drvdata(par->pdev);
1256 #endif
1257
1258 if (on) {
1259 reg = aty_ld_le32(LVDS_GEN_CNTL);
1260 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1261 reg &= ~LVDS_DISPLAY_DIS;
1262 aty_st_le32(LVDS_GEN_CNTL, reg);
1263 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1264 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1265 #endif
1266 } else {
1267 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1268 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1269 #endif
1270 reg = aty_ld_le32(LVDS_GEN_CNTL);
1271 reg |= LVDS_DISPLAY_DIS;
1272 aty_st_le32(LVDS_GEN_CNTL, reg);
1273 mdelay(100);
1274 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1275 aty_st_le32(LVDS_GEN_CNTL, reg);
1276 }
1277 }
1278
1279 static void aty128_set_pll(struct aty128_pll *pll, const struct aty128fb_par *par)
1280 {
1281 u32 div3;
1282
1283 unsigned char post_conv[] = /* register values for post dividers */
1284 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1285
1286 /* select PPLL_DIV_3 */
1287 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1288
1289 /* reset PLL */
1290 aty_st_pll(PPLL_CNTL,
1291 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1292
1293 /* write the reference divider */
1294 aty_pll_wait_readupdate(par);
1295 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1296 aty_pll_writeupdate(par);
1297
1298 div3 = aty_ld_pll(PPLL_DIV_3);
1299 div3 &= ~PPLL_FB3_DIV_MASK;
1300 div3 |= pll->feedback_divider;
1301 div3 &= ~PPLL_POST3_DIV_MASK;
1302 div3 |= post_conv[pll->post_divider] << 16;
1303
1304 /* write feedback and post dividers */
1305 aty_pll_wait_readupdate(par);
1306 aty_st_pll(PPLL_DIV_3, div3);
1307 aty_pll_writeupdate(par);
1308
1309 aty_pll_wait_readupdate(par);
1310 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1311 aty_pll_writeupdate(par);
1312
1313 /* clear the reset, just in case */
1314 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1315 }
1316
1317
1318 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1319 const struct aty128fb_par *par)
1320 {
1321 const struct aty128_constants c = par->constants;
1322 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1323 u32 output_freq;
1324 u32 vclk; /* in .01 MHz */
1325 int i = 0;
1326 u32 n, d;
1327
1328 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1329
1330 /* adjust pixel clock if necessary */
1331 if (vclk > c.ppll_max)
1332 vclk = c.ppll_max;
1333 if (vclk * 12 < c.ppll_min)
1334 vclk = c.ppll_min/12;
1335
1336 /* now, find an acceptable divider */
1337 for (i = 0; i < sizeof(post_dividers); i++) {
1338 output_freq = post_dividers[i] * vclk;
1339 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1340 pll->post_divider = post_dividers[i];
1341 break;
1342 }
1343 }
1344
1345 /* calculate feedback divider */
1346 n = c.ref_divider * output_freq;
1347 d = c.ref_clk;
1348
1349 pll->feedback_divider = round_div(n, d);
1350 pll->vclk = vclk;
1351
1352 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1353 "vclk_per: %d\n", pll->post_divider,
1354 pll->feedback_divider, vclk, output_freq,
1355 c.ref_divider, period_in_ps);
1356
1357 return 0;
1358 }
1359
1360
1361 static int aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var)
1362 {
1363 var->pixclock = 100000000 / pll->vclk;
1364
1365 return 0;
1366 }
1367
1368
1369 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1370 const struct aty128fb_par *par)
1371 {
1372 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1373 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1374 }
1375
1376
1377 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1378 const struct aty128_pll *pll,
1379 u32 depth,
1380 const struct aty128fb_par *par)
1381 {
1382 const struct aty128_meminfo *m = par->mem;
1383 u32 xclk = par->constants.xclk;
1384 u32 fifo_width = par->constants.fifo_width;
1385 u32 fifo_depth = par->constants.fifo_depth;
1386 s32 x, b, p, ron, roff;
1387 u32 n, d, bpp;
1388
1389 /* round up to multiple of 8 */
1390 bpp = (depth+7) & ~7;
1391
1392 n = xclk * fifo_width;
1393 d = pll->vclk * bpp;
1394 x = round_div(n, d);
1395
1396 ron = 4 * m->MB +
1397 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1398 2 * m->Trp +
1399 m->Twr +
1400 m->CL +
1401 m->Tr2w +
1402 x;
1403
1404 DBG("x %x\n", x);
1405
1406 b = 0;
1407 while (x) {
1408 x >>= 1;
1409 b++;
1410 }
1411 p = b + 1;
1412
1413 ron <<= (11 - p);
1414
1415 n <<= (11 - p);
1416 x = round_div(n, d);
1417 roff = x * (fifo_depth - 4);
1418
1419 if ((ron + m->Rloop) >= roff) {
1420 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1421 return -EINVAL;
1422 }
1423
1424 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1425 p, m->Rloop, x, ron, roff);
1426
1427 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1428 dsp->dda_on_off = ron << 16 | roff;
1429
1430 return 0;
1431 }
1432
1433
1434 /*
1435 * This actually sets the video mode.
1436 */
1437 static int aty128fb_set_par(struct fb_info *info)
1438 {
1439 struct aty128fb_par *par = info->par;
1440 u32 config;
1441 int err;
1442
1443 if ((err = aty128_decode_var(&info->var, par)) != 0)
1444 return err;
1445
1446 if (par->blitter_may_be_busy)
1447 wait_for_idle(par);
1448
1449 /* clear all registers that may interfere with mode setting */
1450 aty_st_le32(OVR_CLR, 0);
1451 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1452 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1453 aty_st_le32(OV0_SCALE_CNTL, 0);
1454 aty_st_le32(MPP_TB_CONFIG, 0);
1455 aty_st_le32(MPP_GP_CONFIG, 0);
1456 aty_st_le32(SUBPIC_CNTL, 0);
1457 aty_st_le32(VIPH_CONTROL, 0);
1458 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1459 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1460 aty_st_le32(CAP0_TRIG_CNTL, 0);
1461 aty_st_le32(CAP1_TRIG_CNTL, 0);
1462
1463 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1464
1465 aty128_set_crtc(&par->crtc, par);
1466 aty128_set_pll(&par->pll, par);
1467 aty128_set_fifo(&par->fifo_reg, par);
1468
1469 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1470
1471 #if defined(__BIG_ENDIAN)
1472 if (par->crtc.bpp == 32)
1473 config |= 2; /* make aperture do 32 bit swapping */
1474 else if (par->crtc.bpp == 16)
1475 config |= 1; /* make aperture do 16 bit swapping */
1476 #endif
1477
1478 aty_st_le32(CONFIG_CNTL, config);
1479 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1480
1481 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1482 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1483 : FB_VISUAL_DIRECTCOLOR;
1484
1485 if (par->chip_gen == rage_M3) {
1486 aty128_set_crt_enable(par, par->crt_on);
1487 aty128_set_lcd_enable(par, par->lcd_on);
1488 }
1489 if (par->accel_flags & FB_ACCELF_TEXT)
1490 aty128_init_engine(par);
1491
1492 #ifdef CONFIG_BOOTX_TEXT
1493 btext_update_display(info->fix.smem_start,
1494 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1495 ((par->crtc.v_total>>16) & 0x7ff)+1,
1496 par->crtc.bpp,
1497 par->crtc.vxres*par->crtc.bpp/8);
1498 #endif /* CONFIG_BOOTX_TEXT */
1499
1500 return 0;
1501 }
1502
1503 /*
1504 * encode/decode the User Defined Part of the Display
1505 */
1506
1507 static int aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par)
1508 {
1509 int err;
1510 struct aty128_crtc crtc;
1511 struct aty128_pll pll;
1512 struct aty128_ddafifo fifo_reg;
1513
1514 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1515 return err;
1516
1517 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1518 return err;
1519
1520 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1521 return err;
1522
1523 par->crtc = crtc;
1524 par->pll = pll;
1525 par->fifo_reg = fifo_reg;
1526 par->accel_flags = var->accel_flags;
1527
1528 return 0;
1529 }
1530
1531
1532 static int aty128_encode_var(struct fb_var_screeninfo *var,
1533 const struct aty128fb_par *par)
1534 {
1535 int err;
1536
1537 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1538 return err;
1539
1540 if ((err = aty128_pll_to_var(&par->pll, var)))
1541 return err;
1542
1543 var->nonstd = 0;
1544 var->activate = 0;
1545
1546 var->height = -1;
1547 var->width = -1;
1548 var->accel_flags = par->accel_flags;
1549
1550 return 0;
1551 }
1552
1553
1554 static int aty128fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1555 {
1556 struct aty128fb_par par;
1557 int err;
1558
1559 par = *(struct aty128fb_par *)info->par;
1560 if ((err = aty128_decode_var(var, &par)) != 0)
1561 return err;
1562 aty128_encode_var(var, &par);
1563 return 0;
1564 }
1565
1566
1567 /*
1568 * Pan or Wrap the Display
1569 */
1570 static int aty128fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb)
1571 {
1572 struct aty128fb_par *par = fb->par;
1573 u32 xoffset, yoffset;
1574 u32 offset;
1575 u32 xres, yres;
1576
1577 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1578 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1579
1580 xoffset = (var->xoffset +7) & ~7;
1581 yoffset = var->yoffset;
1582
1583 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1584 return -EINVAL;
1585
1586 par->crtc.xoffset = xoffset;
1587 par->crtc.yoffset = yoffset;
1588
1589 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1590
1591 if (par->crtc.bpp == 24)
1592 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1593
1594 aty_st_le32(CRTC_OFFSET, offset);
1595
1596 return 0;
1597 }
1598
1599
1600 /*
1601 * Helper function to store a single palette register
1602 */
1603 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1604 struct aty128fb_par *par)
1605 {
1606 if (par->chip_gen == rage_M3) {
1607 #if 0
1608 /* Note: For now, on M3, we set palette on both heads, which may
1609 * be useless. Can someone with a M3 check this ?
1610 *
1611 * This code would still be useful if using the second CRTC to
1612 * do mirroring
1613 */
1614
1615 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1616 aty_st_8(PALETTE_INDEX, regno);
1617 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1618 #endif
1619 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1620 }
1621
1622 aty_st_8(PALETTE_INDEX, regno);
1623 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1624 }
1625
1626 static int aty128fb_sync(struct fb_info *info)
1627 {
1628 struct aty128fb_par *par = info->par;
1629
1630 if (par->blitter_may_be_busy)
1631 wait_for_idle(par);
1632 return 0;
1633 }
1634
1635 #ifndef MODULE
1636 static int __devinit aty128fb_setup(char *options)
1637 {
1638 char *this_opt;
1639
1640 if (!options || !*options)
1641 return 0;
1642
1643 while ((this_opt = strsep(&options, ",")) != NULL) {
1644 if (!strncmp(this_opt, "lcd:", 4)) {
1645 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1646 continue;
1647 } else if (!strncmp(this_opt, "crt:", 4)) {
1648 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1649 continue;
1650 }
1651 #ifdef CONFIG_MTRR
1652 if(!strncmp(this_opt, "nomtrr", 6)) {
1653 mtrr = 0;
1654 continue;
1655 }
1656 #endif
1657 #ifdef CONFIG_PPC_PMAC
1658 /* vmode and cmode deprecated */
1659 if (!strncmp(this_opt, "vmode:", 6)) {
1660 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1661 if (vmode > 0 && vmode <= VMODE_MAX)
1662 default_vmode = vmode;
1663 continue;
1664 } else if (!strncmp(this_opt, "cmode:", 6)) {
1665 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1666 switch (cmode) {
1667 case 0:
1668 case 8:
1669 default_cmode = CMODE_8;
1670 break;
1671 case 15:
1672 case 16:
1673 default_cmode = CMODE_16;
1674 break;
1675 case 24:
1676 case 32:
1677 default_cmode = CMODE_32;
1678 break;
1679 }
1680 continue;
1681 }
1682 #endif /* CONFIG_PPC_PMAC */
1683 mode_option = this_opt;
1684 }
1685 return 0;
1686 }
1687 #endif /* MODULE */
1688
1689 /* Backlight */
1690 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1691 #define MAX_LEVEL 0xFF
1692
1693 static struct backlight_properties aty128_bl_data;
1694
1695 /* Call with fb_info->bl_mutex held */
1696 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1697 int level)
1698 {
1699 struct fb_info *info = pci_get_drvdata(par->pdev);
1700 int atylevel;
1701
1702 /* Get and convert the value */
1703 atylevel = MAX_LEVEL -
1704 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1705
1706 if (atylevel < 0)
1707 atylevel = 0;
1708 else if (atylevel > MAX_LEVEL)
1709 atylevel = MAX_LEVEL;
1710
1711 return atylevel;
1712 }
1713
1714 /* We turn off the LCD completely instead of just dimming the backlight.
1715 * This provides greater power saving and the display is useless without
1716 * backlight anyway
1717 */
1718 #define BACKLIGHT_LVDS_OFF
1719 /* That one prevents proper CRT output with LCD off */
1720 #undef BACKLIGHT_DAC_OFF
1721
1722 /* Call with fb_info->bl_mutex held */
1723 static int __aty128_bl_update_status(struct backlight_device *bd)
1724 {
1725 struct aty128fb_par *par = class_get_devdata(&bd->class_dev);
1726 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1727 int level;
1728
1729 if (bd->props->power != FB_BLANK_UNBLANK ||
1730 bd->props->fb_blank != FB_BLANK_UNBLANK ||
1731 !par->lcd_on)
1732 level = 0;
1733 else
1734 level = bd->props->brightness;
1735
1736 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1737 if (level > 0) {
1738 reg |= LVDS_DIGION;
1739 if (!(reg & LVDS_ON)) {
1740 reg &= ~LVDS_BLON;
1741 aty_st_le32(LVDS_GEN_CNTL, reg);
1742 aty_ld_le32(LVDS_GEN_CNTL);
1743 mdelay(10);
1744 reg |= LVDS_BLON;
1745 aty_st_le32(LVDS_GEN_CNTL, reg);
1746 }
1747 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1748 reg |= (aty128_bl_get_level_brightness(par, level) << LVDS_BL_MOD_LEVEL_SHIFT);
1749 #ifdef BACKLIGHT_LVDS_OFF
1750 reg |= LVDS_ON | LVDS_EN;
1751 reg &= ~LVDS_DISPLAY_DIS;
1752 #endif
1753 aty_st_le32(LVDS_GEN_CNTL, reg);
1754 #ifdef BACKLIGHT_DAC_OFF
1755 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1756 #endif
1757 } else {
1758 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1759 reg |= (aty128_bl_get_level_brightness(par, 0) << LVDS_BL_MOD_LEVEL_SHIFT);
1760 #ifdef BACKLIGHT_LVDS_OFF
1761 reg |= LVDS_DISPLAY_DIS;
1762 aty_st_le32(LVDS_GEN_CNTL, reg);
1763 aty_ld_le32(LVDS_GEN_CNTL);
1764 udelay(10);
1765 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1766 #endif
1767 aty_st_le32(LVDS_GEN_CNTL, reg);
1768 #ifdef BACKLIGHT_DAC_OFF
1769 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1770 #endif
1771 }
1772
1773 return 0;
1774 }
1775
1776 static int aty128_bl_update_status(struct backlight_device *bd)
1777 {
1778 struct aty128fb_par *par = class_get_devdata(&bd->class_dev);
1779 struct fb_info *info = pci_get_drvdata(par->pdev);
1780 int ret;
1781
1782 mutex_lock(&info->bl_mutex);
1783 ret = __aty128_bl_update_status(bd);
1784 mutex_unlock(&info->bl_mutex);
1785
1786 return ret;
1787 }
1788
1789 static int aty128_bl_get_brightness(struct backlight_device *bd)
1790 {
1791 return bd->props->brightness;
1792 }
1793
1794 static struct backlight_properties aty128_bl_data = {
1795 .owner = THIS_MODULE,
1796 .get_brightness = aty128_bl_get_brightness,
1797 .update_status = aty128_bl_update_status,
1798 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
1799 };
1800
1801 static void aty128_bl_set_power(struct fb_info *info, int power)
1802 {
1803 mutex_lock(&info->bl_mutex);
1804
1805 if (info->bl_dev) {
1806 down(&info->bl_dev->sem);
1807 info->bl_dev->props->power = power;
1808 __aty128_bl_update_status(info->bl_dev);
1809 up(&info->bl_dev->sem);
1810 }
1811
1812 mutex_unlock(&info->bl_mutex);
1813 }
1814
1815 static void aty128_bl_init(struct aty128fb_par *par)
1816 {
1817 struct fb_info *info = pci_get_drvdata(par->pdev);
1818 struct backlight_device *bd;
1819 char name[12];
1820
1821 /* Could be extended to Rage128Pro LVDS output too */
1822 if (par->chip_gen != rage_M3)
1823 return;
1824
1825 #ifdef CONFIG_PMAC_BACKLIGHT
1826 if (!pmac_has_backlight_type("ati"))
1827 return;
1828 #endif
1829
1830 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1831
1832 bd = backlight_device_register(name, par, &aty128_bl_data);
1833 if (IS_ERR(bd)) {
1834 info->bl_dev = NULL;
1835 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1836 goto error;
1837 }
1838
1839 mutex_lock(&info->bl_mutex);
1840 info->bl_dev = bd;
1841 fb_bl_default_curve(info, 0,
1842 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1843 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1844 mutex_unlock(&info->bl_mutex);
1845
1846 down(&bd->sem);
1847 bd->props->brightness = aty128_bl_data.max_brightness;
1848 bd->props->power = FB_BLANK_UNBLANK;
1849 bd->props->update_status(bd);
1850 up(&bd->sem);
1851
1852 #ifdef CONFIG_PMAC_BACKLIGHT
1853 mutex_lock(&pmac_backlight_mutex);
1854 if (!pmac_backlight)
1855 pmac_backlight = bd;
1856 mutex_unlock(&pmac_backlight_mutex);
1857 #endif
1858
1859 printk("aty128: Backlight initialized (%s)\n", name);
1860
1861 return;
1862
1863 error:
1864 return;
1865 }
1866
1867 static void aty128_bl_exit(struct aty128fb_par *par)
1868 {
1869 struct fb_info *info = pci_get_drvdata(par->pdev);
1870
1871 #ifdef CONFIG_PMAC_BACKLIGHT
1872 mutex_lock(&pmac_backlight_mutex);
1873 #endif
1874
1875 mutex_lock(&info->bl_mutex);
1876 if (info->bl_dev) {
1877 #ifdef CONFIG_PMAC_BACKLIGHT
1878 if (pmac_backlight == info->bl_dev)
1879 pmac_backlight = NULL;
1880 #endif
1881
1882 backlight_device_unregister(info->bl_dev);
1883 info->bl_dev = NULL;
1884
1885 printk("aty128: Backlight unloaded\n");
1886 }
1887 mutex_unlock(&info->bl_mutex);
1888
1889 #ifdef CONFIG_PMAC_BACKLIGHT
1890 mutex_unlock(&pmac_backlight_mutex);
1891 #endif
1892 }
1893 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1894
1895 /*
1896 * Initialisation
1897 */
1898
1899 #ifdef CONFIG_PPC_PMAC
1900 static void aty128_early_resume(void *data)
1901 {
1902 struct aty128fb_par *par = data;
1903
1904 if (try_acquire_console_sem())
1905 return;
1906 aty128_do_resume(par->pdev);
1907 release_console_sem();
1908 }
1909 #endif /* CONFIG_PPC_PMAC */
1910
1911 static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1912 {
1913 struct fb_info *info = pci_get_drvdata(pdev);
1914 struct aty128fb_par *par = info->par;
1915 struct fb_var_screeninfo var;
1916 char video_card[DEVICE_NAME_SIZE];
1917 u8 chip_rev;
1918 u32 dac;
1919
1920 /* Get the chip revision */
1921 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1922
1923 strcpy(video_card, "Rage128 XX ");
1924 video_card[8] = ent->device >> 8;
1925 video_card[9] = ent->device & 0xFF;
1926
1927 /* range check to make sure */
1928 if (ent->driver_data < ARRAY_SIZE(r128_family))
1929 strncat(video_card, r128_family[ent->driver_data], sizeof(video_card));
1930
1931 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1932
1933 if (par->vram_size % (1024 * 1024) == 0)
1934 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1935 else
1936 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1937
1938 par->chip_gen = ent->driver_data;
1939
1940 /* fill in info */
1941 info->fbops = &aty128fb_ops;
1942 info->flags = FBINFO_FLAG_DEFAULT;
1943
1944 par->lcd_on = default_lcd_on;
1945 par->crt_on = default_crt_on;
1946
1947 var = default_var;
1948 #ifdef CONFIG_PPC_PMAC
1949 if (machine_is(powermac)) {
1950 /* Indicate sleep capability */
1951 if (par->chip_gen == rage_M3) {
1952 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1953 pmac_set_early_video_resume(aty128_early_resume, par);
1954 }
1955
1956 /* Find default mode */
1957 if (mode_option) {
1958 if (!mac_find_mode(&var, info, mode_option, 8))
1959 var = default_var;
1960 } else {
1961 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1962 default_vmode = VMODE_1024_768_60;
1963
1964 /* iMacs need that resolution
1965 * PowerMac2,1 first r128 iMacs
1966 * PowerMac2,2 summer 2000 iMacs
1967 * PowerMac4,1 january 2001 iMacs "flower power"
1968 */
1969 if (machine_is_compatible("PowerMac2,1") ||
1970 machine_is_compatible("PowerMac2,2") ||
1971 machine_is_compatible("PowerMac4,1"))
1972 default_vmode = VMODE_1024_768_75;
1973
1974 /* iBook SE */
1975 if (machine_is_compatible("PowerBook2,2"))
1976 default_vmode = VMODE_800_600_60;
1977
1978 /* PowerBook Firewire (Pismo), iBook Dual USB */
1979 if (machine_is_compatible("PowerBook3,1") ||
1980 machine_is_compatible("PowerBook4,1"))
1981 default_vmode = VMODE_1024_768_60;
1982
1983 /* PowerBook Titanium */
1984 if (machine_is_compatible("PowerBook3,2"))
1985 default_vmode = VMODE_1152_768_60;
1986
1987 if (default_cmode > 16)
1988 default_cmode = CMODE_32;
1989 else if (default_cmode > 8)
1990 default_cmode = CMODE_16;
1991 else
1992 default_cmode = CMODE_8;
1993
1994 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1995 var = default_var;
1996 }
1997 } else
1998 #endif /* CONFIG_PPC_PMAC */
1999 {
2000 if (mode_option)
2001 if (fb_find_mode(&var, info, mode_option, NULL,
2002 0, &defaultmode, 8) == 0)
2003 var = default_var;
2004 }
2005
2006 var.accel_flags &= ~FB_ACCELF_TEXT;
2007 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
2008
2009 if (aty128fb_check_var(&var, info)) {
2010 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
2011 return 0;
2012 }
2013
2014 /* setup the DAC the way we like it */
2015 dac = aty_ld_le32(DAC_CNTL);
2016 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2017 dac |= DAC_MASK;
2018 if (par->chip_gen == rage_M3)
2019 dac |= DAC_PALETTE2_SNOOP_EN;
2020 aty_st_le32(DAC_CNTL, dac);
2021
2022 /* turn off bus mastering, just in case */
2023 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2024
2025 info->var = var;
2026 fb_alloc_cmap(&info->cmap, 256, 0);
2027
2028 var.activate = FB_ACTIVATE_NOW;
2029
2030 aty128_init_engine(par);
2031
2032 par->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
2033 par->pdev = pdev;
2034 par->asleep = 0;
2035 par->lock_blank = 0;
2036
2037 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2038 aty128_bl_init(par);
2039 #endif
2040
2041 if (register_framebuffer(info) < 0)
2042 return 0;
2043
2044 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
2045 info->node, info->fix.id, video_card);
2046
2047 return 1; /* success! */
2048 }
2049
2050 #ifdef CONFIG_PCI
2051 /* register a card ++ajoshi */
2052 static int __devinit aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2053 {
2054 unsigned long fb_addr, reg_addr;
2055 struct aty128fb_par *par;
2056 struct fb_info *info;
2057 int err;
2058 #ifndef __sparc__
2059 void __iomem *bios = NULL;
2060 #endif
2061
2062 /* Enable device in PCI config */
2063 if ((err = pci_enable_device(pdev))) {
2064 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2065 err);
2066 return -ENODEV;
2067 }
2068
2069 fb_addr = pci_resource_start(pdev, 0);
2070 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2071 "aty128fb FB")) {
2072 printk(KERN_ERR "aty128fb: cannot reserve frame "
2073 "buffer memory\n");
2074 return -ENODEV;
2075 }
2076
2077 reg_addr = pci_resource_start(pdev, 2);
2078 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2079 "aty128fb MMIO")) {
2080 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2081 goto err_free_fb;
2082 }
2083
2084 /* We have the resources. Now virtualize them */
2085 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2086 if (info == NULL) {
2087 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2088 goto err_free_mmio;
2089 }
2090 par = info->par;
2091
2092 info->pseudo_palette = par->pseudo_palette;
2093
2094 /* Virtualize mmio region */
2095 info->fix.mmio_start = reg_addr;
2096 par->regbase = ioremap(reg_addr, pci_resource_len(pdev, 2));
2097 if (!par->regbase)
2098 goto err_free_info;
2099
2100 /* Grab memory size from the card */
2101 // How does this relate to the resource length from the PCI hardware?
2102 par->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2103
2104 /* Virtualize the framebuffer */
2105 info->screen_base = ioremap(fb_addr, par->vram_size);
2106 if (!info->screen_base)
2107 goto err_unmap_out;
2108
2109 /* Set up info->fix */
2110 info->fix = aty128fb_fix;
2111 info->fix.smem_start = fb_addr;
2112 info->fix.smem_len = par->vram_size;
2113 info->fix.mmio_start = reg_addr;
2114
2115 /* If we can't test scratch registers, something is seriously wrong */
2116 if (!register_test(par)) {
2117 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2118 goto err_out;
2119 }
2120
2121 #ifndef __sparc__
2122 bios = aty128_map_ROM(par, pdev);
2123 #ifdef CONFIG_X86
2124 if (bios == NULL)
2125 bios = aty128_find_mem_vbios(par);
2126 #endif
2127 if (bios == NULL)
2128 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2129 else {
2130 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2131 aty128_get_pllinfo(par, bios);
2132 pci_unmap_rom(pdev, bios);
2133 }
2134 #endif /* __sparc__ */
2135
2136 aty128_timings(par);
2137 pci_set_drvdata(pdev, info);
2138
2139 if (!aty128_init(pdev, ent))
2140 goto err_out;
2141
2142 #ifdef CONFIG_MTRR
2143 if (mtrr) {
2144 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2145 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2146 par->mtrr.vram_valid = 1;
2147 /* let there be speed */
2148 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2149 }
2150 #endif /* CONFIG_MTRR */
2151 return 0;
2152
2153 err_out:
2154 iounmap(info->screen_base);
2155 err_unmap_out:
2156 iounmap(par->regbase);
2157 err_free_info:
2158 framebuffer_release(info);
2159 err_free_mmio:
2160 release_mem_region(pci_resource_start(pdev, 2),
2161 pci_resource_len(pdev, 2));
2162 err_free_fb:
2163 release_mem_region(pci_resource_start(pdev, 0),
2164 pci_resource_len(pdev, 0));
2165 return -ENODEV;
2166 }
2167
2168 static void __devexit aty128_remove(struct pci_dev *pdev)
2169 {
2170 struct fb_info *info = pci_get_drvdata(pdev);
2171 struct aty128fb_par *par;
2172
2173 if (!info)
2174 return;
2175
2176 par = info->par;
2177
2178 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2179 aty128_bl_exit(par);
2180 #endif
2181
2182 unregister_framebuffer(info);
2183 #ifdef CONFIG_MTRR
2184 if (par->mtrr.vram_valid)
2185 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2186 par->vram_size);
2187 #endif /* CONFIG_MTRR */
2188 iounmap(par->regbase);
2189 iounmap(info->screen_base);
2190
2191 release_mem_region(pci_resource_start(pdev, 0),
2192 pci_resource_len(pdev, 0));
2193 release_mem_region(pci_resource_start(pdev, 2),
2194 pci_resource_len(pdev, 2));
2195 framebuffer_release(info);
2196 }
2197 #endif /* CONFIG_PCI */
2198
2199
2200
2201 /*
2202 * Blank the display.
2203 */
2204 static int aty128fb_blank(int blank, struct fb_info *fb)
2205 {
2206 struct aty128fb_par *par = fb->par;
2207 u8 state = 0;
2208
2209 if (par->lock_blank || par->asleep)
2210 return 0;
2211
2212 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2213 if (machine_is(powermac) && blank)
2214 aty128_bl_set_power(fb, FB_BLANK_POWERDOWN);
2215 #endif
2216
2217 if (blank & FB_BLANK_VSYNC_SUSPEND)
2218 state |= 2;
2219 if (blank & FB_BLANK_HSYNC_SUSPEND)
2220 state |= 1;
2221 if (blank & FB_BLANK_POWERDOWN)
2222 state |= 4;
2223
2224 aty_st_8(CRTC_EXT_CNTL+1, state);
2225
2226 if (par->chip_gen == rage_M3) {
2227 aty128_set_crt_enable(par, par->crt_on && !blank);
2228 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2229 }
2230
2231 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2232 if (machine_is(powermac) && !blank)
2233 aty128_bl_set_power(fb, FB_BLANK_UNBLANK);
2234 #endif
2235
2236 return 0;
2237 }
2238
2239 /*
2240 * Set a single color register. The values supplied are already
2241 * rounded down to the hardware's capabilities (according to the
2242 * entries in the var structure). Return != 0 for invalid regno.
2243 */
2244 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2245 u_int transp, struct fb_info *info)
2246 {
2247 struct aty128fb_par *par = info->par;
2248
2249 if (regno > 255
2250 || (par->crtc.depth == 16 && regno > 63)
2251 || (par->crtc.depth == 15 && regno > 31))
2252 return 1;
2253
2254 red >>= 8;
2255 green >>= 8;
2256 blue >>= 8;
2257
2258 if (regno < 16) {
2259 int i;
2260 u32 *pal = info->pseudo_palette;
2261
2262 switch (par->crtc.depth) {
2263 case 15:
2264 pal[regno] = (regno << 10) | (regno << 5) | regno;
2265 break;
2266 case 16:
2267 pal[regno] = (regno << 11) | (regno << 6) | regno;
2268 break;
2269 case 24:
2270 pal[regno] = (regno << 16) | (regno << 8) | regno;
2271 break;
2272 case 32:
2273 i = (regno << 8) | regno;
2274 pal[regno] = (i << 16) | i;
2275 break;
2276 }
2277 }
2278
2279 if (par->crtc.depth == 16 && regno > 0) {
2280 /*
2281 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2282 * have 32 slots for R and B values but 64 slots for G values.
2283 * Thus the R and B values go in one slot but the G value
2284 * goes in a different slot, and we have to avoid disturbing
2285 * the other fields in the slots we touch.
2286 */
2287 par->green[regno] = green;
2288 if (regno < 32) {
2289 par->red[regno] = red;
2290 par->blue[regno] = blue;
2291 aty128_st_pal(regno * 8, red, par->green[regno*2],
2292 blue, par);
2293 }
2294 red = par->red[regno/2];
2295 blue = par->blue[regno/2];
2296 regno <<= 2;
2297 } else if (par->crtc.bpp == 16)
2298 regno <<= 3;
2299 aty128_st_pal(regno, red, green, blue, par);
2300
2301 return 0;
2302 }
2303
2304 #define ATY_MIRROR_LCD_ON 0x00000001
2305 #define ATY_MIRROR_CRT_ON 0x00000002
2306
2307 /* out param: u32* backlight value: 0 to 15 */
2308 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2309 /* in param: u32* backlight value: 0 to 15 */
2310 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2311
2312 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2313 {
2314 struct aty128fb_par *par = info->par;
2315 u32 value;
2316 int rc;
2317
2318 switch (cmd) {
2319 case FBIO_ATY128_SET_MIRROR:
2320 if (par->chip_gen != rage_M3)
2321 return -EINVAL;
2322 rc = get_user(value, (__u32 __user *)arg);
2323 if (rc)
2324 return rc;
2325 par->lcd_on = (value & 0x01) != 0;
2326 par->crt_on = (value & 0x02) != 0;
2327 if (!par->crt_on && !par->lcd_on)
2328 par->lcd_on = 1;
2329 aty128_set_crt_enable(par, par->crt_on);
2330 aty128_set_lcd_enable(par, par->lcd_on);
2331 return 0;
2332 case FBIO_ATY128_GET_MIRROR:
2333 if (par->chip_gen != rage_M3)
2334 return -EINVAL;
2335 value = (par->crt_on << 1) | par->lcd_on;
2336 return put_user(value, (__u32 __user *)arg);
2337 }
2338 return -EINVAL;
2339 }
2340
2341 #if 0
2342 /*
2343 * Accelerated functions
2344 */
2345
2346 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2347 u_int width, u_int height,
2348 struct fb_info_aty128 *par)
2349 {
2350 u32 save_dp_datatype, save_dp_cntl, dstval;
2351
2352 if (!width || !height)
2353 return;
2354
2355 dstval = depth_to_dst(par->current_par.crtc.depth);
2356 if (dstval == DST_24BPP) {
2357 srcx *= 3;
2358 dstx *= 3;
2359 width *= 3;
2360 } else if (dstval == -EINVAL) {
2361 printk("aty128fb: invalid depth or RGBA\n");
2362 return;
2363 }
2364
2365 wait_for_fifo(2, par);
2366 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2367 save_dp_cntl = aty_ld_le32(DP_CNTL);
2368
2369 wait_for_fifo(6, par);
2370 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2371 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2372 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2373 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2374
2375 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2376 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2377
2378 par->blitter_may_be_busy = 1;
2379
2380 wait_for_fifo(2, par);
2381 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2382 aty_st_le32(DP_CNTL, save_dp_cntl);
2383 }
2384
2385
2386 /*
2387 * Text mode accelerated functions
2388 */
2389
2390 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2391 int height, int width)
2392 {
2393 sx *= fontwidth(p);
2394 sy *= fontheight(p);
2395 dx *= fontwidth(p);
2396 dy *= fontheight(p);
2397 width *= fontwidth(p);
2398 height *= fontheight(p);
2399
2400 aty128_rectcopy(sx, sy, dx, dy, width, height,
2401 (struct fb_info_aty128 *)p->fb_info);
2402 }
2403 #endif /* 0 */
2404
2405 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2406 {
2407 u32 pmgt;
2408 u16 pwr_command;
2409 struct pci_dev *pdev = par->pdev;
2410
2411 if (!par->pm_reg)
2412 return;
2413
2414 /* Set the chip into the appropriate suspend mode (we use D2,
2415 * D3 would require a complete re-initialisation of the chip,
2416 * including PCI config registers, clocks, AGP configuration, ...)
2417 */
2418 if (suspend) {
2419 /* Make sure CRTC2 is reset. Remove that the day we decide to
2420 * actually use CRTC2 and replace it with real code for disabling
2421 * the CRTC2 output during sleep
2422 */
2423 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2424 ~(CRTC2_EN));
2425
2426 /* Set the power management mode to be PCI based */
2427 /* Use this magic value for now */
2428 pmgt = 0x0c005407;
2429 aty_st_pll(POWER_MANAGEMENT, pmgt);
2430 (void)aty_ld_pll(POWER_MANAGEMENT);
2431 aty_st_le32(BUS_CNTL1, 0x00000010);
2432 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2433 mdelay(100);
2434 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2435 /* Switch PCI power management to D2 */
2436 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL,
2437 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2438 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2439 } else {
2440 /* Switch back PCI power management to D0 */
2441 mdelay(100);
2442 pci_write_config_word(pdev, par->pm_reg+PCI_PM_CTRL, 0);
2443 pci_read_config_word(pdev, par->pm_reg+PCI_PM_CTRL, &pwr_command);
2444 mdelay(100);
2445 }
2446 }
2447
2448 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2449 {
2450 struct fb_info *info = pci_get_drvdata(pdev);
2451 struct aty128fb_par *par = info->par;
2452
2453 /* We don't do anything but D2, for now we return 0, but
2454 * we may want to change that. How do we know if the BIOS
2455 * can properly take care of D3 ? Also, with swsusp, we
2456 * know we'll be rebooted, ...
2457 */
2458 #ifndef CONFIG_PPC_PMAC
2459 /* HACK ALERT ! Once I find a proper way to say to each driver
2460 * individually what will happen with it's PCI slot, I'll change
2461 * that. On laptops, the AGP slot is just unclocked, so D2 is
2462 * expected, while on desktops, the card is powered off
2463 */
2464 return 0;
2465 #endif /* CONFIG_PPC_PMAC */
2466
2467 if (state.event == pdev->dev.power.power_state.event)
2468 return 0;
2469
2470 printk(KERN_DEBUG "aty128fb: suspending...\n");
2471
2472 acquire_console_sem();
2473
2474 fb_set_suspend(info, 1);
2475
2476 /* Make sure engine is reset */
2477 wait_for_idle(par);
2478 aty128_reset_engine(par);
2479 wait_for_idle(par);
2480
2481 /* Blank display and LCD */
2482 aty128fb_blank(VESA_POWERDOWN, info);
2483
2484 /* Sleep */
2485 par->asleep = 1;
2486 par->lock_blank = 1;
2487
2488 #ifdef CONFIG_PPC_PMAC
2489 /* On powermac, we have hooks to properly suspend/resume AGP now,
2490 * use them here. We'll ultimately need some generic support here,
2491 * but the generic code isn't quite ready for that yet
2492 */
2493 pmac_suspend_agp_for_card(pdev);
2494 #endif /* CONFIG_PPC_PMAC */
2495
2496 /* We need a way to make sure the fbdev layer will _not_ touch the
2497 * framebuffer before we put the chip to suspend state. On 2.4, I
2498 * used dummy fb ops, 2.5 need proper support for this at the
2499 * fbdev level
2500 */
2501 if (state.event != PM_EVENT_ON)
2502 aty128_set_suspend(par, 1);
2503
2504 release_console_sem();
2505
2506 pdev->dev.power.power_state = state;
2507
2508 return 0;
2509 }
2510
2511 static int aty128_do_resume(struct pci_dev *pdev)
2512 {
2513 struct fb_info *info = pci_get_drvdata(pdev);
2514 struct aty128fb_par *par = info->par;
2515
2516 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2517 return 0;
2518
2519 /* Wakeup chip */
2520 aty128_set_suspend(par, 0);
2521 par->asleep = 0;
2522
2523 /* Restore display & engine */
2524 aty128_reset_engine(par);
2525 wait_for_idle(par);
2526 aty128fb_set_par(info);
2527 fb_pan_display(info, &info->var);
2528 fb_set_cmap(&info->cmap, info);
2529
2530 /* Refresh */
2531 fb_set_suspend(info, 0);
2532
2533 /* Unblank */
2534 par->lock_blank = 0;
2535 aty128fb_blank(0, info);
2536
2537 #ifdef CONFIG_PPC_PMAC
2538 /* On powermac, we have hooks to properly suspend/resume AGP now,
2539 * use them here. We'll ultimately need some generic support here,
2540 * but the generic code isn't quite ready for that yet
2541 */
2542 pmac_resume_agp_for_card(pdev);
2543 #endif /* CONFIG_PPC_PMAC */
2544
2545 pdev->dev.power.power_state = PMSG_ON;
2546
2547 printk(KERN_DEBUG "aty128fb: resumed !\n");
2548
2549 return 0;
2550 }
2551
2552 static int aty128_pci_resume(struct pci_dev *pdev)
2553 {
2554 int rc;
2555
2556 acquire_console_sem();
2557 rc = aty128_do_resume(pdev);
2558 release_console_sem();
2559
2560 return rc;
2561 }
2562
2563
2564 static int __devinit aty128fb_init(void)
2565 {
2566 #ifndef MODULE
2567 char *option = NULL;
2568
2569 if (fb_get_options("aty128fb", &option))
2570 return -ENODEV;
2571 aty128fb_setup(option);
2572 #endif
2573
2574 return pci_register_driver(&aty128fb_driver);
2575 }
2576
2577 static void __exit aty128fb_exit(void)
2578 {
2579 pci_unregister_driver(&aty128fb_driver);
2580 }
2581
2582 module_init(aty128fb_init);
2583
2584 module_exit(aty128fb_exit);
2585
2586 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2587 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2588 MODULE_LICENSE("GPL");
2589 module_param(mode_option, charp, 0);
2590 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2591 #ifdef CONFIG_MTRR
2592 module_param_named(nomtrr, mtrr, invbool, 0);
2593 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");
2594 #endif
2595
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