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[hh.org.git] / drivers / video / savage / savagefb.h
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1 /*
2 * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
3 *
4 * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
5 *
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
9 */
10
11
12 #ifndef __SAVAGEFB_H__
13 #define __SAVAGEFB_H__
14
15 #include <linux/i2c.h>
16 #include <linux/i2c-id.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "../edid.h"
19
20 #ifdef SAVAGEFB_DEBUG
21 # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
22 #else
23 # define DBG(x)
24 # define SavagePrintRegs(...)
25 #endif
26
27
28 #define PCI_CHIP_SAVAGE4 0x8a22
29 #define PCI_CHIP_SAVAGE3D 0x8a20
30 #define PCI_CHIP_SAVAGE3D_MV 0x8a21
31 #define PCI_CHIP_SAVAGE2000 0x9102
32 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
33 #define PCI_CHIP_SAVAGE_MX 0x8c11
34 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
35 #define PCI_CHIP_SAVAGE_IX 0x8c13
36 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
37 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
38 /* Twister is a code name; hope I get the real name soon. */
39 #define PCI_CHIP_S3TWISTER_P 0x8d01
40 #define PCI_CHIP_S3TWISTER_K 0x8d02
41 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
42 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
43 #define PCI_CHIP_SUPSAV_MX128 0x8c22
44 #define PCI_CHIP_SUPSAV_MX64 0x8c24
45 #define PCI_CHIP_SUPSAV_MX64C 0x8c26
46 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
47 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
48 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
49 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
50 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
51 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
52
53
54
55 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
56
57 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
58
59 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
60
61 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
62
63 /* Chip tags. These are used to group the adapters into
64 * related families.
65 */
66
67 typedef enum {
68 S3_UNKNOWN = 0,
69 S3_SAVAGE3D,
70 S3_SAVAGE_MX,
71 S3_SAVAGE4,
72 S3_PROSAVAGE,
73 S3_SUPERSAVAGE,
74 S3_SAVAGE2000,
75 S3_LAST
76 } savage_chipset;
77
78 #define BIOS_BSIZE 1024
79 #define BIOS_BASE 0xc0000
80
81 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
82 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
83 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
84 #define SAVAGE_NEWMMIO_VGABASE 0x8000
85
86 #define BASE_FREQ 14318
87 #define HALF_BASE_FREQ 7159
88
89 #define FIFO_CONTROL_REG 0x8200
90 #define MIU_CONTROL_REG 0x8204
91 #define STREAMS_TIMEOUT_REG 0x8208
92 #define MISC_TIMEOUT_REG 0x820c
93
94 #define MONO_PAT_0 0xa4e8
95 #define MONO_PAT_1 0xa4ec
96
97 #define MAXFIFO 0x7f00
98
99 #define BCI_CMD_NOP 0x40000000
100 #define BCI_CMD_SETREG 0x96000000
101 #define BCI_CMD_RECT 0x48000000
102 #define BCI_CMD_RECT_XP 0x01000000
103 #define BCI_CMD_RECT_YP 0x02000000
104 #define BCI_CMD_SEND_COLOR 0x00008000
105 #define BCI_CMD_DEST_GBD 0x00000000
106 #define BCI_CMD_SRC_GBD 0x00000020
107 #define BCI_CMD_SRC_SOLID 0x00000000
108 #define BCI_CMD_SRC_MONO 0x00000060
109 #define BCI_CMD_CLIP_NEW 0x00006000
110 #define BCI_CMD_CLIP_LR 0x00004000
111
112 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
113 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
114 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
115 #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
116 #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
117
118 #define BCI_GBD1 0xE0
119 #define BCI_GBD2 0xE1
120
121 #define BCI_BUFFER_OFFSET 0x10000
122 #define BCI_SIZE 0x4000
123
124 #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
125
126 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
127 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
128 #define BCI_CMD_SEND_COLOR 0x00008000
129
130 #define DISP_CRT 1
131 #define DISP_LCD 2
132 #define DISP_DFP 3
133
134 struct xtimings {
135 unsigned int Clock;
136 unsigned int HDisplay;
137 unsigned int HSyncStart;
138 unsigned int HSyncEnd;
139 unsigned int HTotal;
140 unsigned int HAdjusted;
141 unsigned int VDisplay;
142 unsigned int VSyncStart;
143 unsigned int VSyncEnd;
144 unsigned int VTotal;
145 unsigned int sync;
146 int dblscan;
147 int interlaced;
148 };
149
150 struct savage_reg {
151 unsigned char MiscOutReg; /* Misc */
152 unsigned char CRTC[25]; /* Crtc Controller */
153 unsigned char Sequencer[5]; /* Video Sequencer */
154 unsigned char Graphics[9]; /* Video Graphics */
155 unsigned char Attribute[21]; /* Video Atribute */
156
157 unsigned int mode, refresh;
158 unsigned char SR08, SR0E, SR0F;
159 unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
160 unsigned char SR54[8];
161 unsigned char Clock;
162 unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
163 unsigned char CR40, CR41, CR42, CR43, CR45;
164 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
165 unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
166 unsigned char CR86, CR88;
167 unsigned char CR90, CR91, CRB0;
168 unsigned int STREAMS[22]; /* yuck, streams regs */
169 unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
170 };
171 /* --------------------------------------------------------------------- */
172
173 #define NR_PALETTE 256
174
175
176 struct savagefb_par;
177
178 struct savagefb_i2c_chan {
179 struct savagefb_par *par;
180 struct i2c_adapter adapter;
181 struct i2c_algo_bit_data algo;
182 volatile u8 __iomem *ioaddr;
183 u32 reg;
184 };
185
186 struct savagefb_par {
187 struct pci_dev *pcidev;
188 savage_chipset chip;
189 struct savagefb_i2c_chan chan;
190 struct savage_reg state;
191 struct savage_reg save;
192 unsigned char *edid;
193 u32 pseudo_palette[16];
194 int paletteEnabled;
195 int pm_state;
196 int display_type;
197 int dvi;
198 int crtonly;
199 int dacSpeedBpp;
200 int maxClock;
201 int minClock;
202 int numClocks;
203 int clock[4];
204 int MCLK, REFCLK, LCDclk;
205 struct {
206 u8 __iomem *vbase;
207 u32 pbase;
208 u32 len;
209 #ifdef CONFIG_MTRR
210 int mtrr;
211 #endif
212 } video;
213
214 struct {
215 volatile u8 __iomem *vbase;
216 u32 pbase;
217 u32 len;
218 } mmio;
219
220 volatile u32 __iomem *bci_base;
221 unsigned int bci_ptr;
222 u32 cob_offset;
223 u32 cob_size;
224 int cob_index;
225
226 void (*SavageWaitIdle) (struct savagefb_par *par);
227 void (*SavageWaitFifo) (struct savagefb_par *par, int space);
228
229 int HorizScaleFactor;
230
231 /* Panels size */
232 int SavagePanelWidth;
233 int SavagePanelHeight;
234
235 struct {
236 u16 red, green, blue, transp;
237 } palette[NR_PALETTE];
238
239 int depth;
240 int vwidth;
241 };
242
243 #define BCI_BD_BW_DISABLE 0x10000000
244 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
245 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
246
247
248 /* IO functions */
249 static inline u8 savage_in8(u32 addr, struct savagefb_par *par)
250 {
251 return readb(par->mmio.vbase + addr);
252 }
253
254 static inline u16 savage_in16(u32 addr, struct savagefb_par *par)
255 {
256 return readw(par->mmio.vbase + addr);
257 }
258
259 static inline u32 savage_in32(u32 addr, struct savagefb_par *par)
260 {
261 return readl(par->mmio.vbase + addr);
262 }
263
264 static inline void savage_out8(u32 addr, u8 val, struct savagefb_par *par)
265 {
266 writeb(val, par->mmio.vbase + addr);
267 }
268
269 static inline void savage_out16(u32 addr, u16 val, struct savagefb_par *par)
270 {
271 writew(val, par->mmio.vbase + addr);
272 }
273
274 static inline void savage_out32(u32 addr, u32 val, struct savagefb_par *par)
275 {
276 writel(val, par->mmio.vbase + addr);
277 }
278
279 static inline u8 vga_in8(int addr, struct savagefb_par *par)
280 {
281 return savage_in8(0x8000 + addr, par);
282 }
283
284 static inline u16 vga_in16(int addr, struct savagefb_par *par)
285 {
286 return savage_in16(0x8000 + addr, par);
287 }
288
289 static inline u8 vga_in32(int addr, struct savagefb_par *par)
290 {
291 return savage_in32(0x8000 + addr, par);
292 }
293
294 static inline void vga_out8(int addr, u8 val, struct savagefb_par *par)
295 {
296 savage_out8(0x8000 + addr, val, par);
297 }
298
299 static inline void vga_out16(int addr, u16 val, struct savagefb_par *par)
300 {
301 savage_out16(0x8000 + addr, val, par);
302 }
303
304 static inline void vga_out32(int addr, u32 val, struct savagefb_par *par)
305 {
306 savage_out32(0x8000 + addr, val, par);
307 }
308
309 static inline u8 VGArCR (u8 index, struct savagefb_par *par)
310 {
311 vga_out8(0x3d4, index, par);
312 return vga_in8(0x3d5, par);
313 }
314
315 static inline u8 VGArGR (u8 index, struct savagefb_par *par)
316 {
317 vga_out8(0x3ce, index, par);
318 return vga_in8(0x3cf, par);
319 }
320
321 static inline u8 VGArSEQ (u8 index, struct savagefb_par *par)
322 {
323 vga_out8(0x3c4, index, par);
324 return vga_in8(0x3c5, par);
325 }
326
327 static inline void VGAwCR(u8 index, u8 val, struct savagefb_par *par)
328 {
329 vga_out8(0x3d4, index, par);
330 vga_out8(0x3d5, val, par);
331 }
332
333 static inline void VGAwGR(u8 index, u8 val, struct savagefb_par *par)
334 {
335 vga_out8(0x3ce, index, par);
336 vga_out8(0x3cf, val, par);
337 }
338
339 static inline void VGAwSEQ(u8 index, u8 val, struct savagefb_par *par)
340 {
341 vga_out8(0x3c4, index, par);
342 vga_out8 (0x3c5, val, par);
343 }
344
345 static inline void VGAenablePalette(struct savagefb_par *par)
346 {
347 u8 tmp;
348
349 tmp = vga_in8(0x3da, par);
350 vga_out8(0x3c0, 0x00, par);
351 par->paletteEnabled = 1;
352 }
353
354 static inline void VGAdisablePalette(struct savagefb_par *par)
355 {
356 u8 tmp;
357
358 tmp = vga_in8(0x3da, par);
359 vga_out8(0x3c0, 0x20, par);
360 par->paletteEnabled = 0;
361 }
362
363 static inline void VGAwATTR(u8 index, u8 value, struct savagefb_par *par)
364 {
365 u8 tmp;
366
367 if (par->paletteEnabled)
368 index &= ~0x20;
369 else
370 index |= 0x20;
371
372 tmp = vga_in8(0x3da, par);
373 vga_out8(0x3c0, index, par);
374 vga_out8 (0x3c0, value, par);
375 }
376
377 static inline void VGAwMISC(u8 value, struct savagefb_par *par)
378 {
379 vga_out8(0x3c2, value, par);
380 }
381
382 #ifndef CONFIG_FB_SAVAGE_ACCEL
383 #define savagefb_set_clip(x)
384 #endif
385
386 static inline void VerticalRetraceWait(struct savagefb_par *par)
387 {
388 vga_out8(0x3d4, 0x17, par);
389 if (vga_in8(0x3d5, par) & 0x80) {
390 while ((vga_in8(0x3da, par) & 0x08) == 0x08);
391 while ((vga_in8(0x3da, par) & 0x08) == 0x00);
392 }
393 }
394
395 extern int savagefb_probe_i2c_connector(struct fb_info *info,
396 u8 **out_edid);
397 extern void savagefb_create_i2c_busses(struct fb_info *info);
398 extern void savagefb_delete_i2c_busses(struct fb_info *info);
399 extern int savagefb_sync(struct fb_info *info);
400 extern void savagefb_copyarea(struct fb_info *info,
401 const struct fb_copyarea *region);
402 extern void savagefb_fillrect(struct fb_info *info,
403 const struct fb_fillrect *rect);
404 extern void savagefb_imageblit(struct fb_info *info,
405 const struct fb_image *image);
406
407
408 #endif /* __SAVAGEFB_H__ */
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