| blob | 4ea107344b48b8c7b1537ce3b865622c9e5a0a48 |
1 /*
2 * Dell Axim X5 initial GPIO machinery state.
3 *
4 * Authors: Martin Demin <demo@twincar.sk>,
5 * Andrew Zabolotny <anpaza@mail.ru>
6 */
8 #ifndef _AXIMX5_INIT_H_
9 #define _AXIMX5_INIT_H_
11 /* GPIO pin direction setup */
12 #define GPIO00_Dir 0
13 #define GPIO01_Dir 0
14 #define GPIO02_Dir 0
15 #define GPIO03_Dir 0
16 #define GPIO04_Dir 0
17 #define GPIO05_Dir 0
18 #define GPIO06_Dir 0
19 #define GPIO07_Dir 0
20 #define GPIO08_Dir 0
21 #define GPIO09_Dir 0
22 #define GPIO10_Dir 0
23 #define GPIO11_Dir 0
24 #define GPIO12_Dir 0
25 #define GPIO13_Dir 0
26 #define GPIO14_Dir 0
27 #define GPIO15_Dir 1
28 #define GPIO16_Dir 1
29 #define GPIO17_Dir 0
30 #define GPIO18_Dir 0
31 #define GPIO19_Dir 1
32 #define GPIO20_Dir 1
33 #define GPIO21_Dir 0
34 #define GPIO22_Dir 1
35 #define GPIO23_Dir 1
36 #define GPIO24_Dir 1
37 #define GPIO25_Dir 0
38 #define GPIO26_Dir 1
39 #define GPIO27_Dir 0
40 #define GPIO28_Dir 0
41 #define GPIO29_Dir 0
42 #define GPIO30_Dir 1
43 #define GPIO31_Dir 1
44 #define GPIO32_Dir 0
45 #define GPIO33_Dir 1
46 #define GPIO34_Dir 0
47 #define GPIO35_Dir 0
48 #define GPIO36_Dir 0
49 #define GPIO37_Dir 0
50 #define GPIO38_Dir 0
51 #define GPIO39_Dir 1
52 #define GPIO40_Dir 1
53 #define GPIO41_Dir 1
54 #define GPIO42_Dir 0
55 #define GPIO43_Dir 1
56 #define GPIO44_Dir 0
57 #define GPIO45_Dir 1
58 #define GPIO46_Dir 0
59 #define GPIO47_Dir 1
60 #define GPIO48_Dir 1
61 #define GPIO49_Dir 1
62 #define GPIO50_Dir 1
63 #define GPIO51_Dir 1
64 #define GPIO52_Dir 1
65 #define GPIO53_Dir 1
66 #define GPIO54_Dir 1
67 #define GPIO55_Dir 1
68 #define GPIO56_Dir 0
69 #define GPIO57_Dir 0
70 #define GPIO58_Dir 1
71 #define GPIO59_Dir 0
72 #define GPIO60_Dir 1
73 #define GPIO61_Dir 0
74 #define GPIO62_Dir 1
75 #define GPIO63_Dir 1
76 #define GPIO64_Dir 0
77 #define GPIO65_Dir 0
78 #define GPIO66_Dir 0
79 #define GPIO67_Dir 0
80 #define GPIO68_Dir 0
81 #define GPIO69_Dir 0
82 #define GPIO70_Dir 0
83 #define GPIO71_Dir 1
84 #define GPIO72_Dir 1
85 #define GPIO73_Dir 1
86 #define GPIO74_Dir 1
87 #define GPIO75_Dir 0
88 #define GPIO76_Dir 0
89 #define GPIO77_Dir 0
90 #define GPIO78_Dir 1
91 #define GPIO79_Dir 1
92 #define GPIO80_Dir 1
94 /* GPIO Alternate Function (Select Function 0 ~ 3) */
95 #define GPIO00_AltFunc 0
96 #define GPIO01_AltFunc 1
97 #define GPIO02_AltFunc 0
98 #define GPIO03_AltFunc 0
99 #define GPIO04_AltFunc 0
100 #define GPIO05_AltFunc 0
101 #define GPIO06_AltFunc 0
102 #define GPIO07_AltFunc 0
103 #define GPIO08_AltFunc 0
104 #define GPIO09_AltFunc 0
105 #define GPIO10_AltFunc 0
106 #define GPIO11_AltFunc 0
107 #define GPIO12_AltFunc 0
108 #define GPIO13_AltFunc 0
109 #define GPIO14_AltFunc 0
110 #define GPIO15_AltFunc 2
111 #define GPIO16_AltFunc 2
112 #define GPIO17_AltFunc 0
113 #define GPIO18_AltFunc 1
114 #define GPIO19_AltFunc 0
115 #define GPIO20_AltFunc 0
116 #define GPIO21_AltFunc 0
117 #define GPIO22_AltFunc 0
118 #define GPIO23_AltFunc 0
119 #define GPIO24_AltFunc 0
120 #define GPIO25_AltFunc 0
121 #define GPIO26_AltFunc 0
122 #define GPIO27_AltFunc 0
123 #define GPIO28_AltFunc 1
124 #define GPIO29_AltFunc 1
125 #define GPIO30_AltFunc 2
126 #define GPIO31_AltFunc 2
127 #define GPIO32_AltFunc 0
128 #define GPIO33_AltFunc 2
129 #define GPIO34_AltFunc 1
130 #define GPIO35_AltFunc 1
131 #define GPIO36_AltFunc 1
132 #define GPIO37_AltFunc 1
133 #define GPIO38_AltFunc 1
134 #define GPIO39_AltFunc 2
135 #define GPIO40_AltFunc 2
136 #define GPIO41_AltFunc 2
137 #define GPIO42_AltFunc 1
138 #define GPIO43_AltFunc 2
139 #define GPIO44_AltFunc 1
140 #define GPIO45_AltFunc 2
141 #define GPIO46_AltFunc 2
142 #define GPIO47_AltFunc 1
143 #define GPIO48_AltFunc 2
144 #define GPIO49_AltFunc 2
145 #define GPIO50_AltFunc 2
146 #define GPIO51_AltFunc 2
147 #define GPIO52_AltFunc 2
148 #define GPIO53_AltFunc 2
149 #define GPIO54_AltFunc 2
150 #define GPIO55_AltFunc 2
151 #define GPIO56_AltFunc 1
152 #define GPIO57_AltFunc 1
153 #define GPIO58_AltFunc 0
154 #define GPIO59_AltFunc 0
155 #define GPIO60_AltFunc 0
156 #define GPIO61_AltFunc 0
157 #define GPIO62_AltFunc 0
158 #define GPIO63_AltFunc 0
159 #define GPIO64_AltFunc 0
160 #define GPIO65_AltFunc 0
161 #define GPIO66_AltFunc 0
162 #define GPIO67_AltFunc 0
163 #define GPIO68_AltFunc 0
164 #define GPIO69_AltFunc 0
165 #define GPIO70_AltFunc 0
166 #define GPIO71_AltFunc 0
167 #define GPIO72_AltFunc 0
168 #define GPIO73_AltFunc 0
169 #define GPIO74_AltFunc 0
170 #define GPIO75_AltFunc 0
171 #define GPIO76_AltFunc 0
172 #define GPIO77_AltFunc 0
173 #define GPIO78_AltFunc 2
174 #define GPIO79_AltFunc 2
175 #define GPIO80_AltFunc 0
177 /* GPIO Pin Init State */
178 #define GPIO00_Level 0
179 #define GPIO01_Level 0
180 #define GPIO02_Level 0
181 #define GPIO03_Level 0
182 #define GPIO04_Level 0
183 #define GPIO05_Level 0
184 #define GPIO06_Level 0
185 #define GPIO07_Level 0
186 #define GPIO08_Level 0
187 #define GPIO09_Level 0
188 #define GPIO10_Level 0
189 #define GPIO11_Level 0
190 #define GPIO12_Level 0
191 #define GPIO13_Level 0
192 #define GPIO14_Level 0
193 #define GPIO15_Level 1
194 #define GPIO16_Level 1
195 #define GPIO17_Level 0
196 #define GPIO18_Level 0
197 #define GPIO19_Level 0
198 #define GPIO20_Level 0
199 #define GPIO21_Level 0
200 #define GPIO22_Level 1
201 #define GPIO23_Level 1
202 #define GPIO24_Level 0
203 #define GPIO25_Level 0
204 #define GPIO26_Level 0
205 #define GPIO27_Level 0
206 #define GPIO28_Level 0
207 #define GPIO29_Level 0
208 #define GPIO30_Level 0
209 #define GPIO31_Level 0
210 #define GPIO32_Level 0
211 #define GPIO33_Level 1
212 #define GPIO34_Level 0
213 #define GPIO35_Level 0
214 #define GPIO36_Level 0
215 #define GPIO37_Level 0
216 #define GPIO38_Level 0
217 #define GPIO39_Level 1
218 #define GPIO40_Level 1
219 #define GPIO41_Level 1
220 #define GPIO42_Level 0
221 #define GPIO43_Level 1
222 #define GPIO44_Level 0
223 #define GPIO45_Level 1
224 #define GPIO46_Level 0
225 #define GPIO47_Level 0
226 #define GPIO48_Level 1
227 #define GPIO49_Level 1
228 #define GPIO50_Level 1
229 #define GPIO51_Level 1
230 #define GPIO52_Level 1
231 #define GPIO53_Level 1
232 #define GPIO54_Level 1
233 #define GPIO55_Level 1
234 #define GPIO56_Level 0
235 #define GPIO57_Level 0
236 #define GPIO58_Level 1
237 #define GPIO59_Level 0
238 #define GPIO60_Level 0
239 #define GPIO61_Level 0
240 #define GPIO62_Level 0
241 #define GPIO63_Level 0
242 #define GPIO64_Level 0
243 #define GPIO65_Level 0
244 #define GPIO66_Level 0
245 #define GPIO67_Level 0
246 #define GPIO68_Level 0
247 #define GPIO69_Level 0
248 #define GPIO70_Level 0
249 #define GPIO71_Level 0
250 #define GPIO72_Level 1
251 #define GPIO73_Level 1
252 #define GPIO74_Level 1
253 #define GPIO75_Level 0
254 #define GPIO76_Level 0
255 #define GPIO77_Level 0
256 #define GPIO78_Level 1
257 #define GPIO79_Level 1
258 #define GPIO80_Level 1
260 /* GPIO Pin Sleep Level */
261 #define GPIO00_Sleep_Level 1
262 #define GPIO01_Sleep_Level 1
263 #define GPIO02_Sleep_Level 1
264 #define GPIO03_Sleep_Level 1
265 #define GPIO04_Sleep_Level 0
266 #define GPIO05_Sleep_Level 1
267 #define GPIO06_Sleep_Level 0
268 #define GPIO07_Sleep_Level 0
269 #define GPIO08_Sleep_Level 0
270 #define GPIO09_Sleep_Level 1
271 #define GPIO10_Sleep_Level 0
272 #define GPIO11_Sleep_Level 0
273 #define GPIO12_Sleep_Level 0
274 #define GPIO13_Sleep_Level 0
275 #define GPIO14_Sleep_Level 0
276 #define GPIO15_Sleep_Level 1
277 #define GPIO16_Sleep_Level 0
278 #define GPIO17_Sleep_Level 0
279 #define GPIO18_Sleep_Level 1
280 #define GPIO19_Sleep_Level 0
281 #define GPIO20_Sleep_Level 0
282 #define GPIO21_Sleep_Level 1
283 #define GPIO22_Sleep_Level 1
284 #define GPIO23_Sleep_Level 1
285 #define GPIO24_Sleep_Level 1
286 #define GPIO25_Sleep_Level 1
287 #define GPIO26_Sleep_Level 1
288 #define GPIO27_Sleep_Level 1
289 #define GPIO28_Sleep_Level 0
290 #define GPIO29_Sleep_Level 0
291 #define GPIO30_Sleep_Level 0
292 #define GPIO31_Sleep_Level 0
293 #define GPIO32_Sleep_Level 0
294 #define GPIO33_Sleep_Level 1
295 #define GPIO34_Sleep_Level 1
296 #define GPIO35_Sleep_Level 1
297 #define GPIO36_Sleep_Level 1
298 #define GPIO37_Sleep_Level 1
299 #define GPIO38_Sleep_Level 1
300 #define GPIO39_Sleep_Level 0
301 #define GPIO40_Sleep_Level 0
302 #define GPIO41_Sleep_Level 0
303 #define GPIO42_Sleep_Level 1
304 #define GPIO43_Sleep_Level 1
305 #define GPIO44_Sleep_Level 1
306 #define GPIO45_Sleep_Level 1
307 #define GPIO46_Sleep_Level 1
308 #define GPIO47_Sleep_Level 0
309 #define GPIO48_Sleep_Level 1
310 #define GPIO49_Sleep_Level 1
311 #define GPIO50_Sleep_Level 1
312 #define GPIO51_Sleep_Level 1
313 #define GPIO52_Sleep_Level 1
314 #define GPIO53_Sleep_Level 1
315 #define GPIO54_Sleep_Level 1
316 #define GPIO55_Sleep_Level 1
317 #define GPIO56_Sleep_Level 1
318 #define GPIO57_Sleep_Level 0
319 #define GPIO58_Sleep_Level 1
320 #define GPIO59_Sleep_Level 0
321 #define GPIO60_Sleep_Level 0
322 #define GPIO61_Sleep_Level 0
323 #define GPIO62_Sleep_Level 0
324 #define GPIO63_Sleep_Level 1
325 #define GPIO64_Sleep_Level 1
326 #define GPIO65_Sleep_Level 1
327 #define GPIO66_Sleep_Level 1
328 #define GPIO67_Sleep_Level 1
329 #define GPIO68_Sleep_Level 0
330 #define GPIO69_Sleep_Level 0
331 #define GPIO70_Sleep_Level 0
332 #define GPIO71_Sleep_Level 0
333 #define GPIO72_Sleep_Level 1
334 #define GPIO73_Sleep_Level 1
335 #define GPIO74_Sleep_Level 1
336 #define GPIO75_Sleep_Level 1
337 #define GPIO76_Sleep_Level 1
338 #define GPIO77_Sleep_Level 0
339 #define GPIO78_Sleep_Level 1
340 #define GPIO79_Sleep_Level 1
341 #define GPIO80_Sleep_Level 1
343 /*****************************************************
344 Init Value base on Cotulla CPU Register definition
345 *****************************************************/
346 #define GPDRx_i0 (GPIO00_Dir << 0) + (GPIO01_Dir << 1) + (GPIO02_Dir << 2) + (GPIO03_Dir << 3)
347 #define GPDRx_i1 (GPIO04_Dir << 4) + (GPIO05_Dir << 5) + (GPIO06_Dir << 6) + (GPIO07_Dir << 7)
348 #define GPDRx_i2 (GPIO08_Dir << 8) + (GPIO09_Dir << 9) + (GPIO10_Dir << 10) + (GPIO11_Dir << 11)
349 #define GPDRx_i3 (GPIO12_Dir << 12) + (GPIO13_Dir << 13) + (GPIO14_Dir << 14) + (GPIO15_Dir << 15)
350 #define GPDRx_i4 (GPIO16_Dir << 16) + (GPIO17_Dir << 17) + (GPIO18_Dir << 18) + (GPIO19_Dir << 19)
351 #define GPDRx_i5 (GPIO20_Dir << 20) + (GPIO21_Dir << 21) + (GPIO22_Dir << 22) + (GPIO23_Dir << 23)
352 #define GPDRx_i6 (GPIO24_Dir << 24) + (GPIO25_Dir << 25) + (GPIO26_Dir << 26) + (GPIO27_Dir << 27)
353 #define GPDRx_i7 (GPIO28_Dir << 28) + (GPIO29_Dir << 29) + (GPIO30_Dir << 30) + (GPIO31_Dir << 31)
354 #define GPDRx_InitValue (GPDRx_i0+GPDRx_i1+GPDRx_i2+GPDRx_i3+GPDRx_i4+GPDRx_i5+GPDRx_i6+GPDRx_i7)
356 #define GPDRy_i0 (GPIO32_Dir << 0) + (GPIO33_Dir << 1) + (GPIO34_Dir << 2) + (GPIO35_Dir << 3)
357 #define GPDRy_i1 (GPIO36_Dir << 4) + (GPIO37_Dir << 5) + (GPIO38_Dir << 6) + (GPIO39_Dir << 7)
358 #define GPDRy_i2 (GPIO40_Dir << 8) + (GPIO41_Dir << 9) + (GPIO42_Dir << 10) + (GPIO43_Dir << 11)
359 #define GPDRy_i3 (GPIO44_Dir << 12) + (GPIO45_Dir << 13) + (GPIO46_Dir << 14) + (GPIO47_Dir << 15)
360 #define GPDRy_i4 (GPIO48_Dir << 16) + (GPIO49_Dir << 17) + (GPIO50_Dir << 18) + (GPIO51_Dir << 19)
361 #define GPDRy_i5 (GPIO52_Dir << 20) + (GPIO53_Dir << 21) + (GPIO54_Dir << 22) + (GPIO55_Dir << 23)
362 #define GPDRy_i6 (GPIO56_Dir << 24) + (GPIO57_Dir << 25) + (GPIO58_Dir << 26) + (GPIO59_Dir << 27)
363 #define GPDRy_i7 (GPIO60_Dir << 28) + (GPIO61_Dir << 29) + (GPIO62_Dir << 30) + (GPIO63_Dir << 31)
364 #define GPDRy_InitValue (GPDRy_i0+GPDRy_i1+GPDRy_i2+GPDRy_i3+GPDRy_i4+GPDRy_i5+GPDRy_i6+GPDRy_i7)
366 #define GPDRz_i0 (GPIO64_Dir << 0) + (GPIO65_Dir << 1) + (GPIO66_Dir << 2) + (GPIO67_Dir << 3)
367 #define GPDRz_i1 (GPIO68_Dir << 4) + (GPIO69_Dir << 5) + (GPIO70_Dir << 6) + (GPIO71_Dir << 7)
368 #define GPDRz_i2 (GPIO72_Dir << 8) + (GPIO73_Dir << 9) + (GPIO74_Dir << 10) + (GPIO75_Dir << 11)
369 #define GPDRz_i3 (GPIO76_Dir << 12) + (GPIO77_Dir << 13) + (GPIO78_Dir << 14) + (GPIO79_Dir << 15)
370 #define GPDRz_i4 (GPIO80_Dir << 16)
371 #define GPDRz_InitValue (GPDRz_i0+GPDRz_i1+GPDRz_i2+GPDRz_i3+GPDRz_i4)
373 #define GAFR0x_i0 (GPIO00_AltFunc << 0) + (GPIO01_AltFunc << 2) + (GPIO02_AltFunc << 4) + (GPIO03_AltFunc << 6)
374 #define GAFR0x_i1 (GPIO04_AltFunc << 8) + (GPIO05_AltFunc << 10) + (GPIO06_AltFunc << 12) + (GPIO07_AltFunc << 14)
375 #define GAFR0x_i2 (GPIO08_AltFunc << 16) + (GPIO09_AltFunc << 18) + (GPIO10_AltFunc << 20) + (GPIO11_AltFunc << 22)
376 #define GAFR0x_i3 (GPIO12_AltFunc << 24) + (GPIO13_AltFunc << 26) + (GPIO14_AltFunc << 28) + (GPIO15_AltFunc << 30)
377 #define GAFR0x_InitValue (GAFR0x_i0+GAFR0x_i1+GAFR0x_i2+GAFR0x_i3)
379 #define GAFR1x_i0 (GPIO16_AltFunc << 0) + (GPIO17_AltFunc << 2) + (GPIO18_AltFunc << 4) + (GPIO19_AltFunc << 6)
380 #define GAFR1x_i1 (GPIO20_AltFunc << 8) + (GPIO21_AltFunc << 10) + (GPIO22_AltFunc << 12) + (GPIO23_AltFunc << 14)
381 #define GAFR1x_i2 (GPIO24_AltFunc << 16) + (GPIO25_AltFunc << 18) + (GPIO26_AltFunc << 20) + (GPIO27_AltFunc << 22)
382 #define GAFR1x_i3 (GPIO28_AltFunc << 24) + (GPIO29_AltFunc << 26) + (GPIO30_AltFunc << 28) + (GPIO31_AltFunc << 30)
383 #define GAFR1x_InitValue (GAFR1x_i0+GAFR1x_i1+GAFR1x_i2+GAFR1x_i3)
385 #define GAFR0y_i0 (GPIO32_AltFunc << 0) + (GPIO33_AltFunc << 2) + (GPIO34_AltFunc << 4) + (GPIO35_AltFunc << 6)
386 #define GAFR0y_i1 (GPIO36_AltFunc << 8) + (GPIO37_AltFunc << 10) + (GPIO38_AltFunc << 12) + (GPIO39_AltFunc << 14)
387 #define GAFR0y_i2 (GPIO40_AltFunc << 16) + (GPIO41_AltFunc << 18) + (GPIO42_AltFunc << 20) + (GPIO43_AltFunc << 22)
388 #define GAFR0y_i3 (GPIO44_AltFunc << 24) + (GPIO45_AltFunc << 26) + (GPIO46_AltFunc << 28) + (GPIO47_AltFunc << 30)
389 #define GAFR0y_InitValue (GAFR0y_i0+GAFR0y_i1+GAFR0y_i2+GAFR0y_i3)
391 #define GAFR1y_i0 (GPIO48_AltFunc << 0) + (GPIO49_AltFunc << 2) + (GPIO50_AltFunc << 4) + (GPIO51_AltFunc << 6)
392 #define GAFR1y_i1 (GPIO52_AltFunc << 8) + (GPIO53_AltFunc << 10) + (GPIO54_AltFunc << 12) + (GPIO55_AltFunc << 14)
393 #define GAFR1y_i2 (GPIO56_AltFunc << 16) + (GPIO57_AltFunc << 18) + (GPIO58_AltFunc << 20) + (GPIO59_AltFunc << 22)
394 #define GAFR1y_i3 (GPIO60_AltFunc << 24) + (GPIO61_AltFunc << 26) + (GPIO62_AltFunc << 28) + (GPIO63_AltFunc << 30)
395 #define GAFR1y_InitValue (GAFR1y_i0+GAFR1y_i1+GAFR1y_i2+GAFR1y_i3)
397 #define GAFR0z_i0 (GPIO64_AltFunc << 0) + (GPIO65_AltFunc << 2) + (GPIO66_AltFunc << 4) + (GPIO67_AltFunc << 6)
398 #define GAFR0z_i1 (GPIO68_AltFunc << 8) + (GPIO69_AltFunc << 10) + (GPIO70_AltFunc << 12) + (GPIO71_AltFunc << 14)
399 #define GAFR0z_i2 (GPIO72_AltFunc << 16) + (GPIO73_AltFunc << 18) + (GPIO74_AltFunc << 20) + (GPIO75_AltFunc << 22)
400 #define GAFR0z_i3 (GPIO76_AltFunc << 24) + (GPIO77_AltFunc << 26) + (GPIO78_AltFunc << 28) + (GPIO79_AltFunc << 30)
401 #define GAFR0z_InitValue (GAFR0z_i0+GAFR0z_i1+GAFR0z_i2+GAFR0z_i3)
403 #define GAFR1z_InitValue (GPIO80_AltFunc << 0)
405 #define GPSRx_i0 (GPIO00_Level << 0) + (GPIO01_Level << 1) + (GPIO02_Level << 2) + (GPIO03_Level << 3)
406 #define GPSRx_i1 (GPIO04_Level << 4) + (GPIO05_Level << 5) + (GPIO06_Level << 6) + (GPIO07_Level << 7)
407 #define GPSRx_i2 (GPIO08_Level << 8) + (GPIO09_Level << 9) + (GPIO10_Level << 10) + (GPIO11_Level << 11)
408 #define GPSRx_i3 (GPIO12_Level << 12) + (GPIO13_Level << 13) + (GPIO14_Level << 14) + (GPIO15_Level << 15)
409 #define GPSRx_i4 (GPIO16_Level << 16) + (GPIO17_Level << 17) + (GPIO18_Level << 18) + (GPIO19_Level << 19)
410 #define GPSRx_i5 (GPIO20_Level << 20) + (GPIO21_Level << 21) + (GPIO22_Level << 22) + (GPIO23_Level << 23)
411 #define GPSRx_i6 (GPIO24_Level << 24) + (GPIO25_Level << 25) + (GPIO26_Level << 26) + (GPIO27_Level << 27)
412 #define GPSRx_i7 (GPIO28_Level << 28) + (GPIO29_Level << 29) + (GPIO30_Level << 30) + (GPIO31_Level << 31)
413 #define GPSRx_InitValue (GPSRx_i0+GPSRx_i1+GPSRx_i2+GPSRx_i3+GPSRx_i4+GPSRx_i5+GPSRx_i6+GPSRx_i7)
415 #define GPSRy_i0 (GPIO32_Level << 0) + (GPIO33_Level << 1) + (GPIO34_Level << 2) + (GPIO35_Level << 3)
416 #define GPSRy_i1 (GPIO36_Level << 4) + (GPIO37_Level << 5) + (GPIO38_Level << 6) + (GPIO39_Level << 7)
417 #define GPSRy_i2 (GPIO40_Level << 8) + (GPIO41_Level << 9) + (GPIO42_Level << 10) + (GPIO43_Level << 11)
418 #define GPSRy_i3 (GPIO44_Level << 12) + (GPIO45_Level << 13) + (GPIO46_Level << 14) + (GPIO47_Level << 15)
419 #define GPSRy_i4 (GPIO48_Level << 16) + (GPIO49_Level << 17) + (GPIO50_Level << 18) + (GPIO51_Level << 19)
420 #define GPSRy_i5 (GPIO52_Level << 20) + (GPIO53_Level << 21) + (GPIO54_Level << 22) + (GPIO55_Level << 23)
421 #define GPSRy_i6 (GPIO56_Level << 24) + (GPIO57_Level << 25) + (GPIO58_Level << 26) + (GPIO59_Level << 27)
422 #define GPSRy_i7 (GPIO60_Level << 28) + (GPIO61_Level << 29) + (GPIO62_Level << 30) + (GPIO63_Level << 31)
423 #define GPSRy_InitValue (GPSRy_i0+GPSRy_i1+GPSRy_i2+GPSRy_i3+GPSRy_i4+GPSRy_i5+GPSRy_i6+GPSRy_i7)
425 #define GPSRz_i0 (GPIO64_Level << 0) + (GPIO65_Level << 1) + (GPIO66_Level << 2) + (GPIO67_Level << 3)
426 #define GPSRz_i1 (GPIO68_Level << 4) + (GPIO69_Level << 5) + (GPIO70_Level << 6) + (GPIO71_Level << 7)
427 #define GPSRz_i2 (GPIO72_Level << 8) + (GPIO73_Level << 9) + (GPIO74_Level << 10) + (GPIO75_Level << 11)
428 #define GPSRz_i3 (GPIO76_Level << 12) + (GPIO77_Level << 13) + (GPIO78_Level << 14) + (GPIO79_Level << 15)
429 #define GPSRz_i4 (GPIO80_Level << 16)
430 #define GPSRz_InitValue (GPSRz_i0+GPSRz_i1+GPSRz_i2+GPSRz_i3+GPSRz_i4)
432 /**************************
433 value for set when sleep
434 **************************/
436 #define GPSRx_si0 (GPIO00_Sleep_Level << 0) + (GPIO01_Sleep_Level << 1) + (GPIO02_Sleep_Level << 2) + (GPIO03_Sleep_Level << 3)
437 #define GPSRx_si1 (GPIO04_Sleep_Level << 4) + (GPIO05_Sleep_Level << 5) + (GPIO06_Sleep_Level << 6) + (GPIO07_Sleep_Level << 7)
438 #define GPSRx_si2 (GPIO08_Sleep_Level << 8) + (GPIO09_Sleep_Level << 9) + (GPIO10_Sleep_Level << 10) + (GPIO11_Sleep_Level << 11)
439 #define GPSRx_si3 (GPIO12_Sleep_Level << 12) + (GPIO13_Sleep_Level << 13) + (GPIO14_Sleep_Level << 14) + (GPIO15_Sleep_Level << 15)
440 #define GPSRx_si4 (GPIO16_Sleep_Level << 16) + (GPIO17_Sleep_Level << 17) + (GPIO18_Sleep_Level << 18) + (GPIO19_Sleep_Level << 19)
441 #define GPSRx_si5 (GPIO20_Sleep_Level << 20) + (GPIO21_Sleep_Level << 21) + (GPIO22_Sleep_Level << 22) + (GPIO23_Sleep_Level << 23)
442 #define GPSRx_si6 (GPIO24_Sleep_Level << 24) + (GPIO25_Sleep_Level << 25) + (GPIO26_Sleep_Level << 26) + (GPIO27_Sleep_Level << 27)
443 #define GPSRx_si7 (GPIO28_Sleep_Level << 28) + (GPIO29_Sleep_Level << 29) + (GPIO30_Sleep_Level << 30) + (GPIO31_Sleep_Level << 31)
444 #define GPSRx_SleepValue (GPSRx_si0+GPSRx_si1+GPSRx_si2+GPSRx_si3+GPSRx_si4+GPSRx_si5+GPSRx_si6+GPSRx_si7)
446 #define GPSRy_si0 (GPIO32_Sleep_Level << 0) + (GPIO33_Sleep_Level << 1) + (GPIO34_Sleep_Level << 2) + (GPIO35_Sleep_Level << 3)
447 #define GPSRy_si1 (GPIO36_Sleep_Level << 4) + (GPIO37_Sleep_Level << 5) + (GPIO38_Sleep_Level << 6) + (GPIO39_Sleep_Level << 7)
448 #define GPSRy_si2 (GPIO40_Sleep_Level << 8) + (GPIO41_Sleep_Level << 9) + (GPIO42_Sleep_Level << 10) + (GPIO43_Sleep_Level << 11)
449 #define GPSRy_si3 (GPIO44_Sleep_Level << 12) + (GPIO45_Sleep_Level << 13) + (GPIO46_Sleep_Level << 14) + (GPIO47_Sleep_Level << 15)
450 #define GPSRy_si4 (GPIO48_Sleep_Level << 16) + (GPIO49_Sleep_Level << 17) + (GPIO50_Sleep_Level << 18) + (GPIO51_Sleep_Level << 19)
451 #define GPSRy_si5 (GPIO52_Sleep_Level << 20) + (GPIO53_Sleep_Level << 21) + (GPIO54_Sleep_Level << 22) + (GPIO55_Sleep_Level << 23)
452 #define GPSRy_si6 (GPIO56_Sleep_Level << 24) + (GPIO57_Sleep_Level << 25) + (GPIO58_Sleep_Level << 26) + (GPIO59_Sleep_Level << 27)
453 #define GPSRy_si7 (GPIO60_Sleep_Level << 28) + (GPIO61_Sleep_Level << 29) + (GPIO62_Sleep_Level << 30) + (GPIO63_Sleep_Level << 31)
454 #define GPSRy_SleepValue (GPSRy_si0+GPSRy_si1+GPSRy_si2+GPSRy_si3+GPSRy_si4+GPSRy_si5+GPSRy_si6+GPSRy_si7)
456 #define GPSRz_si0 (GPIO64_Sleep_Level << 0) + (GPIO65_Sleep_Level << 1) + (GPIO66_Sleep_Level << 2) + (GPIO67_Sleep_Level << 3)
457 #define GPSRz_si1 (GPIO68_Sleep_Level << 4) + (GPIO69_Sleep_Level << 5) + (GPIO70_Sleep_Level << 6) + (GPIO71_Sleep_Level << 7)
458 #define GPSRz_si2 (GPIO72_Sleep_Level << 8) + (GPIO73_Sleep_Level << 9) + (GPIO74_Sleep_Level << 10) + (GPIO75_Sleep_Level << 11)
459 #define GPSRz_si3 (GPIO76_Sleep_Level << 12) + (GPIO77_Sleep_Level << 13) + (GPIO78_Sleep_Level << 14) + (GPIO79_Sleep_Level << 15)
460 #define GPSRz_si4 (GPIO80_Sleep_Level << 16)
461 #define GPSRz_SleepValue (GPSRz_si0+GPSRz_si1+GPSRz_si2+GPSRz_si3+GPSRz_si4)