include/asm-cris/arch-v32/hwregs/asm/ata_defs_asm.h

   1 #ifndef __ata_defs_asm_h
   2 #define __ata_defs_asm_h
   3
   4 /*
   5  * This file is autogenerated from
   6  *   file:           ../../inst/ata/rtl/ata_regs.r
   7  *     id:           ata_regs.r,v 1.11 2005/02/09 08:27:36 kriskn Exp
   8  *     last modfied: Mon Apr 11 16:06:25 2005
   9  *
  10  *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/ata_defs_asm.h ../../inst/ata/rtl/ata_regs.r
  11  *      id: $Id: ata_defs_asm.h,v 1.1 2005/04/24 18:31:04 starvik Exp $
  12  * Any changes here will be lost.
  13  *
  14  * -*- buffer-read-only: t -*-
  15  */
  16
  17 #ifndef REG_FIELD
  18 #define REG_FIELD( scope, reg, field, value ) \
  19   REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
  20 #define REG_FIELD_X_( value, shift ) ((value) << shift)
  21 #endif
  22
  23 #ifndef REG_STATE
  24 #define REG_STATE( scope, reg, field, symbolic_value ) \
  25   REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
  26 #define REG_STATE_X_( k, shift ) (k << shift)
  27 #endif
  28
  29 #ifndef REG_MASK
  30 #define REG_MASK( scope, reg, field ) \
  31   REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
  32 #define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
  33 #endif
  34
  35 #ifndef REG_LSB
  36 #define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
  37 #endif
  38
  39 #ifndef REG_BIT
  40 #define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
  41 #endif
  42
  43 #ifndef REG_ADDR
  44 #define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
  45 #define REG_ADDR_X_( inst, offs ) ((inst) + offs)
  46 #endif
  47
  48 #ifndef REG_ADDR_VECT
  49 #define REG_ADDR_VECT( scope, inst, reg, index ) \
  50          REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
  51                          STRIDE_##scope##_##reg )
  52 #define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
  53                           ((inst) + offs + (index) * stride)
  54 #endif
  55
  56 /* Register rw_ctrl0, scope ata, type rw */
  57 #define reg_ata_rw_ctrl0___pio_hold___lsb 0
  58 #define reg_ata_rw_ctrl0___pio_hold___width 6
  59 #define reg_ata_rw_ctrl0___pio_strb___lsb 6
  60 #define reg_ata_rw_ctrl0___pio_strb___width 6
  61 #define reg_ata_rw_ctrl0___pio_setup___lsb 12
  62 #define reg_ata_rw_ctrl0___pio_setup___width 6
  63 #define reg_ata_rw_ctrl0___dma_hold___lsb 18
  64 #define reg_ata_rw_ctrl0___dma_hold___width 6
  65 #define reg_ata_rw_ctrl0___dma_strb___lsb 24
  66 #define reg_ata_rw_ctrl0___dma_strb___width 6
  67 #define reg_ata_rw_ctrl0___rst___lsb 30
  68 #define reg_ata_rw_ctrl0___rst___width 1
  69 #define reg_ata_rw_ctrl0___rst___bit 30
  70 #define reg_ata_rw_ctrl0___en___lsb 31
  71 #define reg_ata_rw_ctrl0___en___width 1
  72 #define reg_ata_rw_ctrl0___en___bit 31
  73 #define reg_ata_rw_ctrl0_offset 12
  74
  75 /* Register rw_ctrl1, scope ata, type rw */
  76 #define reg_ata_rw_ctrl1___udma_tcyc___lsb 0
  77 #define reg_ata_rw_ctrl1___udma_tcyc___width 4
  78 #define reg_ata_rw_ctrl1___udma_tdvs___lsb 4
  79 #define reg_ata_rw_ctrl1___udma_tdvs___width 4
  80 #define reg_ata_rw_ctrl1_offset 16
  81
  82 /* Register rw_ctrl2, scope ata, type rw */
  83 #define reg_ata_rw_ctrl2___data___lsb 0
  84 #define reg_ata_rw_ctrl2___data___width 16
  85 #define reg_ata_rw_ctrl2___dma_size___lsb 19
  86 #define reg_ata_rw_ctrl2___dma_size___width 1
  87 #define reg_ata_rw_ctrl2___dma_size___bit 19
  88 #define reg_ata_rw_ctrl2___multi___lsb 20
  89 #define reg_ata_rw_ctrl2___multi___width 1
  90 #define reg_ata_rw_ctrl2___multi___bit 20
  91 #define reg_ata_rw_ctrl2___hsh___lsb 21
  92 #define reg_ata_rw_ctrl2___hsh___width 2
  93 #define reg_ata_rw_ctrl2___trf_mode___lsb 23
  94 #define reg_ata_rw_ctrl2___trf_mode___width 1
  95 #define reg_ata_rw_ctrl2___trf_mode___bit 23
  96 #define reg_ata_rw_ctrl2___rw___lsb 24
  97 #define reg_ata_rw_ctrl2___rw___width 1
  98 #define reg_ata_rw_ctrl2___rw___bit 24
  99 #define reg_ata_rw_ctrl2___addr___lsb 25
 100 #define reg_ata_rw_ctrl2___addr___width 3
 101 #define reg_ata_rw_ctrl2___cs0___lsb 28
 102 #define reg_ata_rw_ctrl2___cs0___width 1
 103 #define reg_ata_rw_ctrl2___cs0___bit 28
 104 #define reg_ata_rw_ctrl2___cs1___lsb 29
 105 #define reg_ata_rw_ctrl2___cs1___width 1
 106 #define reg_ata_rw_ctrl2___cs1___bit 29
 107 #define reg_ata_rw_ctrl2___sel___lsb 30
 108 #define reg_ata_rw_ctrl2___sel___width 2
 109 #define reg_ata_rw_ctrl2_offset 0
 110
 111 /* Register rs_stat_data, scope ata, type rs */
 112 #define reg_ata_rs_stat_data___data___lsb 0
 113 #define reg_ata_rs_stat_data___data___width 16
 114 #define reg_ata_rs_stat_data___dav___lsb 16
 115 #define reg_ata_rs_stat_data___dav___width 1
 116 #define reg_ata_rs_stat_data___dav___bit 16
 117 #define reg_ata_rs_stat_data___busy___lsb 17
 118 #define reg_ata_rs_stat_data___busy___width 1
 119 #define reg_ata_rs_stat_data___busy___bit 17
 120 #define reg_ata_rs_stat_data_offset 4
 121
 122 /* Register r_stat_data, scope ata, type r */
 123 #define reg_ata_r_stat_data___data___lsb 0
 124 #define reg_ata_r_stat_data___data___width 16
 125 #define reg_ata_r_stat_data___dav___lsb 16
 126 #define reg_ata_r_stat_data___dav___width 1
 127 #define reg_ata_r_stat_data___dav___bit 16
 128 #define reg_ata_r_stat_data___busy___lsb 17
 129 #define reg_ata_r_stat_data___busy___width 1
 130 #define reg_ata_r_stat_data___busy___bit 17
 131 #define reg_ata_r_stat_data_offset 8
 132
 133 /* Register rw_trf_cnt, scope ata, type rw */
 134 #define reg_ata_rw_trf_cnt___cnt___lsb 0
 135 #define reg_ata_rw_trf_cnt___cnt___width 17
 136 #define reg_ata_rw_trf_cnt_offset 20
 137
 138 /* Register r_stat_misc, scope ata, type r */
 139 #define reg_ata_r_stat_misc___crc___lsb 0
 140 #define reg_ata_r_stat_misc___crc___width 16
 141 #define reg_ata_r_stat_misc_offset 24
 142
 143 /* Register rw_intr_mask, scope ata, type rw */
 144 #define reg_ata_rw_intr_mask___bus0___lsb 0
 145 #define reg_ata_rw_intr_mask___bus0___width 1
 146 #define reg_ata_rw_intr_mask___bus0___bit 0
 147 #define reg_ata_rw_intr_mask___bus1___lsb 1
 148 #define reg_ata_rw_intr_mask___bus1___width 1
 149 #define reg_ata_rw_intr_mask___bus1___bit 1
 150 #define reg_ata_rw_intr_mask___bus2___lsb 2
 151 #define reg_ata_rw_intr_mask___bus2___width 1
 152 #define reg_ata_rw_intr_mask___bus2___bit 2
 153 #define reg_ata_rw_intr_mask___bus3___lsb 3
 154 #define reg_ata_rw_intr_mask___bus3___width 1
 155 #define reg_ata_rw_intr_mask___bus3___bit 3
 156 #define reg_ata_rw_intr_mask_offset 28
 157
 158 /* Register rw_ack_intr, scope ata, type rw */
 159 #define reg_ata_rw_ack_intr___bus0___lsb 0
 160 #define reg_ata_rw_ack_intr___bus0___width 1
 161 #define reg_ata_rw_ack_intr___bus0___bit 0
 162 #define reg_ata_rw_ack_intr___bus1___lsb 1
 163 #define reg_ata_rw_ack_intr___bus1___width 1
 164 #define reg_ata_rw_ack_intr___bus1___bit 1
 165 #define reg_ata_rw_ack_intr___bus2___lsb 2
 166 #define reg_ata_rw_ack_intr___bus2___width 1
 167 #define reg_ata_rw_ack_intr___bus2___bit 2
 168 #define reg_ata_rw_ack_intr___bus3___lsb 3
 169 #define reg_ata_rw_ack_intr___bus3___width 1
 170 #define reg_ata_rw_ack_intr___bus3___bit 3
 171 #define reg_ata_rw_ack_intr_offset 32
 172
 173 /* Register r_intr, scope ata, type r */
 174 #define reg_ata_r_intr___bus0___lsb 0
 175 #define reg_ata_r_intr___bus0___width 1
 176 #define reg_ata_r_intr___bus0___bit 0
 177 #define reg_ata_r_intr___bus1___lsb 1
 178 #define reg_ata_r_intr___bus1___width 1
 179 #define reg_ata_r_intr___bus1___bit 1
 180 #define reg_ata_r_intr___bus2___lsb 2
 181 #define reg_ata_r_intr___bus2___width 1
 182 #define reg_ata_r_intr___bus2___bit 2
 183 #define reg_ata_r_intr___bus3___lsb 3
 184 #define reg_ata_r_intr___bus3___width 1
 185 #define reg_ata_r_intr___bus3___bit 3
 186 #define reg_ata_r_intr_offset 36
 187
 188 /* Register r_masked_intr, scope ata, type r */
 189 #define reg_ata_r_masked_intr___bus0___lsb 0
 190 #define reg_ata_r_masked_intr___bus0___width 1
 191 #define reg_ata_r_masked_intr___bus0___bit 0
 192 #define reg_ata_r_masked_intr___bus1___lsb 1
 193 #define reg_ata_r_masked_intr___bus1___width 1
 194 #define reg_ata_r_masked_intr___bus1___bit 1
 195 #define reg_ata_r_masked_intr___bus2___lsb 2
 196 #define reg_ata_r_masked_intr___bus2___width 1
 197 #define reg_ata_r_masked_intr___bus2___bit 2
 198 #define reg_ata_r_masked_intr___bus3___lsb 3
 199 #define reg_ata_r_masked_intr___bus3___width 1
 200 #define reg_ata_r_masked_intr___bus3___bit 3
 201 #define reg_ata_r_masked_intr_offset 40
 202
 203
 204 /* Constants */
 205 #define regk_ata_active                           0x00000001
 206 #define regk_ata_byte                             0x00000001
 207 #define regk_ata_data                             0x00000001
 208 #define regk_ata_dma                              0x00000001
 209 #define regk_ata_inactive                         0x00000000
 210 #define regk_ata_no                               0x00000000
 211 #define regk_ata_nodata                           0x00000000
 212 #define regk_ata_pio                              0x00000000
 213 #define regk_ata_rd                               0x00000001
 214 #define regk_ata_reg                              0x00000000
 215 #define regk_ata_rw_ctrl0_default                 0x00000000
 216 #define regk_ata_rw_ctrl2_default                 0x00000000
 217 #define regk_ata_rw_intr_mask_default             0x00000000
 218 #define regk_ata_udma                             0x00000002
 219 #define regk_ata_word                             0x00000000
 220 #define regk_ata_wr                               0x00000000
 221 #define regk_ata_yes                              0x00000001
 222 #endif /* __ata_defs_asm_h */