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[NETFILTER]: ip_tables: fix module refcount leaks in compat error paths
[hh.org.git] / drivers / video / controlfb.c
blob8cc6c0e2d27aa74935776168562aa5b1f0d26f1c
1 /*
2 * controlfb.c -- frame buffer device for the PowerMac 'control' display
3 *
4 * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
5 * Copyright (C) 1998 Dan Jacobowitz
6 * Copyright (C) 2001 Takashi Oe
7 *
8 * Mmap code by Michel Lanners <mlan@cpu.lu>
9 *
10 * Frame buffer structure from:
11 * drivers/video/chipsfb.c -- frame buffer device for
12 * Chips & Technologies 65550 chip.
13 *
14 * Copyright (C) 1998 Paul Mackerras
15 *
16 * This file is derived from the Powermac "chips" driver:
17 * Copyright (C) 1997 Fabio Riccardi.
18 * And from the frame buffer device for Open Firmware-initialized devices:
19 * Copyright (C) 1997 Geert Uytterhoeven.
20 *
21 * Hardware information from:
22 * control.c: Console support for PowerMac "control" display adaptor.
23 * Copyright (C) 1996 Paul Mackerras
24 *
25 * Updated to 2.5 framebuffer API by Ben Herrenschmidt
26 * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
27 * and James Simmons <jsimmons@infradead.org>.
28 *
29 * This file is subject to the terms and conditions of the GNU General Public
30 * License. See the file COPYING in the main directory of this archive for
31 * more details.
32 */
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/errno.h>
37 #include <linux/string.h>
38 #include <linux/mm.h>
39 #include <linux/slab.h>
40 #include <linux/vmalloc.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/fb.h>
44 #include <linux/init.h>
45 #include <linux/pci.h>
46 #include <linux/nvram.h>
47 #include <linux/adb.h>
48 #include <linux/cuda.h>
49 #include <asm/io.h>
50 #include <asm/prom.h>
51 #include <asm/pgtable.h>
52 #include <asm/btext.h>
53
54 #include "macmodes.h"
55 #include "controlfb.h"
56
57 struct fb_par_control {
58 int vmode, cmode;
59 int xres, yres;
60 int vxres, vyres;
61 int xoffset, yoffset;
62 int pitch;
63 struct control_regvals regvals;
64 unsigned long sync;
65 unsigned char ctrl;
66 };
67
68 #define DIRTY(z) ((x)->z != (y)->z)
69 #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
70 static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
71 {
72 int i, results;
73
74 results = 1;
75 for (i = 0; i < 3; i++)
76 results &= !DIRTY(regvals.clock_params[i]);
77 if (!results)
78 return 0;
79 for (i = 0; i < 16; i++)
80 results &= !DIRTY(regvals.regs[i]);
81 if (!results)
82 return 0;
83 return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
84 && !DIRTY(vxres) && !DIRTY(vyres));
85 }
86 static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
87 {
88 return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
89 && !DIRTY(yres) && !DIRTY(xres_virtual)
90 && !DIRTY(yres_virtual)
91 && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
92 }
93
94 struct fb_info_control {
95 struct fb_info info;
96 struct fb_par_control par;
97 u32 pseudo_palette[17];
98
99 struct cmap_regs __iomem *cmap_regs;
100 unsigned long cmap_regs_phys;
101
102 struct control_regs __iomem *control_regs;
103 unsigned long control_regs_phys;
104 unsigned long control_regs_size;
105
106 __u8 __iomem *frame_buffer;
107 unsigned long frame_buffer_phys;
108 unsigned long fb_orig_base;
109 unsigned long fb_orig_size;
110
111 int control_use_bank2;
112 unsigned long total_vram;
113 unsigned char vram_attr;
114 };
115
116 /* control register access macro */
117 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
118
119
120 /******************** Prototypes for exported functions ********************/
121 /*
122 * struct fb_ops
123 */
124 static int controlfb_pan_display(struct fb_var_screeninfo *var,
125 struct fb_info *info);
126 static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
127 u_int transp, struct fb_info *info);
128 static int controlfb_blank(int blank_mode, struct fb_info *info);
129 static int controlfb_mmap(struct fb_info *info,
130 struct vm_area_struct *vma);
131 static int controlfb_set_par (struct fb_info *info);
132 static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info);
133
134 /******************** Prototypes for internal functions **********************/
135
136 static void set_control_clock(unsigned char *params);
137 static int init_control(struct fb_info_control *p);
138 static void control_set_hardware(struct fb_info_control *p,
139 struct fb_par_control *par);
140 static int control_of_init(struct device_node *dp);
141 static void find_vram_size(struct fb_info_control *p);
142 static int read_control_sense(struct fb_info_control *p);
143 static int calc_clock_params(unsigned long clk, unsigned char *param);
144 static int control_var_to_par(struct fb_var_screeninfo *var,
145 struct fb_par_control *par, const struct fb_info *fb_info);
146 static inline void control_par_to_var(struct fb_par_control *par,
147 struct fb_var_screeninfo *var);
148 static void control_init_info(struct fb_info *info, struct fb_info_control *p);
149 static void control_cleanup(void);
150
151
152 /************************** Internal variables *******************************/
153
154 static struct fb_info_control *control_fb;
155
156 static int default_vmode __initdata = VMODE_NVRAM;
157 static int default_cmode __initdata = CMODE_NVRAM;
158
159
160 static struct fb_ops controlfb_ops = {
161 .owner = THIS_MODULE,
162 .fb_check_var = controlfb_check_var,
163 .fb_set_par = controlfb_set_par,
164 .fb_setcolreg = controlfb_setcolreg,
165 .fb_pan_display = controlfb_pan_display,
166 .fb_blank = controlfb_blank,
167 .fb_mmap = controlfb_mmap,
168 .fb_fillrect = cfb_fillrect,
169 .fb_copyarea = cfb_copyarea,
170 .fb_imageblit = cfb_imageblit,
171 };
172
173
174 /******************** The functions for controlfb_ops ********************/
175
176 #ifdef MODULE
177 MODULE_LICENSE("GPL");
178
179 int init_module(void)
180 {
181 struct device_node *dp;
182
183 dp = find_devices("control");
184 if (dp != 0 && !control_of_init(dp))
185 return 0;
186
187 return -ENXIO;
188 }
189
190 void cleanup_module(void)
191 {
192 control_cleanup();
193 }
194 #endif
195
196 /*
197 * Checks a var structure
198 */
199 static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
200 {
201 struct fb_par_control par;
202 int err;
203
204 err = control_var_to_par(var, &par, info);
205 if (err)
206 return err;
207 control_par_to_var(&par, var);
208
209 return 0;
210 }
211
212 /*
213 * Applies current var to display
214 */
215 static int controlfb_set_par (struct fb_info *info)
216 {
217 struct fb_info_control *p = (struct fb_info_control *) info;
218 struct fb_par_control par;
219 int err;
220
221 if((err = control_var_to_par(&info->var, &par, info))) {
222 printk (KERN_ERR "controlfb_set_par: error calling"
223 " control_var_to_par: %d.\n", err);
224 return err;
225 }
226
227 control_set_hardware(p, &par);
228
229 info->fix.visual = (p->par.cmode == CMODE_8) ?
230 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
231 info->fix.line_length = p->par.pitch;
232 info->fix.xpanstep = 32 >> p->par.cmode;
233 info->fix.ypanstep = 1;
234
235 return 0;
236 }
237
238 /*
239 * Set screen start address according to var offset values
240 */
241 static inline void set_screen_start(int xoffset, int yoffset,
242 struct fb_info_control *p)
243 {
244 struct fb_par_control *par = &p->par;
245
246 par->xoffset = xoffset;
247 par->yoffset = yoffset;
248 out_le32(CNTRL_REG(p,start_addr),
249 par->yoffset * par->pitch + (par->xoffset << par->cmode));
250 }
251
252
253 static int controlfb_pan_display(struct fb_var_screeninfo *var,
254 struct fb_info *info)
255 {
256 unsigned int xoffset, hstep;
257 struct fb_info_control *p = (struct fb_info_control *)info;
258 struct fb_par_control *par = &p->par;
259
260 /*
261 * make sure start addr will be 32-byte aligned
262 */
263 hstep = 0x1f >> par->cmode;
264 xoffset = (var->xoffset + hstep) & ~hstep;
265
266 if (xoffset+par->xres > par->vxres ||
267 var->yoffset+par->yres > par->vyres)
268 return -EINVAL;
269
270 set_screen_start(xoffset, var->yoffset, p);
271
272 return 0;
273 }
274
275
276 /*
277 * Private mmap since we want to have a different caching on the framebuffer
278 * for controlfb.
279 * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
280 */
281 static int controlfb_mmap(struct fb_info *info,
282 struct vm_area_struct *vma)
283 {
284 unsigned long off, start;
285 u32 len;
286
287 off = vma->vm_pgoff << PAGE_SHIFT;
288
289 /* frame buffer memory */
290 start = info->fix.smem_start;
291 len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.smem_len);
292 if (off >= len) {
293 /* memory mapped io */
294 off -= len;
295 if (info->var.accel_flags)
296 return -EINVAL;
297 start = info->fix.mmio_start;
298 len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.mmio_len);
299 pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE|_PAGE_GUARDED;
300 } else {
301 /* framebuffer */
302 pgprot_val(vma->vm_page_prot) |= _PAGE_WRITETHRU;
303 }
304 start &= PAGE_MASK;
305 if ((vma->vm_end - vma->vm_start + off) > len)
306 return -EINVAL;
307 off += start;
308 vma->vm_pgoff = off >> PAGE_SHIFT;
309 if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
310 vma->vm_end - vma->vm_start, vma->vm_page_prot))
311 return -EAGAIN;
312
313 return 0;
314 }
315
316 static int controlfb_blank(int blank_mode, struct fb_info *info)
317 {
318 struct fb_info_control *p = (struct fb_info_control *) info;
319 unsigned ctrl;
320
321 ctrl = ld_le32(CNTRL_REG(p,ctrl));
322 if (blank_mode > 0)
323 switch (blank_mode) {
324 case FB_BLANK_VSYNC_SUSPEND:
325 ctrl &= ~3;
326 break;
327 case FB_BLANK_HSYNC_SUSPEND:
328 ctrl &= ~0x30;
329 break;
330 case FB_BLANK_POWERDOWN:
331 ctrl &= ~0x33;
332 /* fall through */
333 case FB_BLANK_NORMAL:
334 ctrl |= 0x400;
335 break;
336 default:
337 break;
338 }
339 else {
340 ctrl &= ~0x400;
341 ctrl |= 0x33;
342 }
343 out_le32(CNTRL_REG(p,ctrl), ctrl);
344
345 return 0;
346 }
347
348 static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
349 u_int transp, struct fb_info *info)
350 {
351 struct fb_info_control *p = (struct fb_info_control *) info;
352 __u8 r, g, b;
353
354 if (regno > 255)
355 return 1;
356
357 r = red >> 8;
358 g = green >> 8;
359 b = blue >> 8;
360
361 out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
362 out_8(&p->cmap_regs->lut, r); /* send one color channel at */
363 out_8(&p->cmap_regs->lut, g); /* a time... */
364 out_8(&p->cmap_regs->lut, b);
365
366 if (regno < 16) {
367 int i;
368 switch (p->par.cmode) {
369 case CMODE_16:
370 p->pseudo_palette[regno] =
371 (regno << 10) | (regno << 5) | regno;
372 break;
373 case CMODE_32:
374 i = (regno << 8) | regno;
375 p->pseudo_palette[regno] = (i << 16) | i;
376 break;
377 }
378 }
379
380 return 0;
381 }
382
383
384 /******************** End of controlfb_ops implementation ******************/
385
386
387
388 static void set_control_clock(unsigned char *params)
389 {
390 #ifdef CONFIG_ADB_CUDA
391 struct adb_request req;
392 int i;
393
394 for (i = 0; i < 3; ++i) {
395 cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
396 0x50, i + 1, params[i]);
397 while (!req.complete)
398 cuda_poll();
399 }
400 #endif
401 }
402
403
404 /*
405 * finish off the driver initialization and register
406 */
407 static int __init init_control(struct fb_info_control *p)
408 {
409 int full, sense, vmode, cmode, vyres;
410 struct fb_var_screeninfo var;
411 int rc;
412
413 printk(KERN_INFO "controlfb: ");
414
415 full = p->total_vram == 0x400000;
416
417 /* Try to pick a video mode out of NVRAM if we have one. */
418 if (default_cmode == CMODE_NVRAM){
419 cmode = nvram_read_byte(NV_CMODE);
420 if(cmode < CMODE_8 || cmode > CMODE_32)
421 cmode = CMODE_8;
422 } else
423 cmode=default_cmode;
424
425 if (default_vmode == VMODE_NVRAM) {
426 vmode = nvram_read_byte(NV_VMODE);
427 if (vmode < 1 || vmode > VMODE_MAX ||
428 control_mac_modes[vmode - 1].m[full] < cmode) {
429 sense = read_control_sense(p);
430 printk("Monitor sense value = 0x%x, ", sense);
431 vmode = mac_map_monitor_sense(sense);
432 if (control_mac_modes[vmode - 1].m[full] < cmode)
433 vmode = VMODE_640_480_60;
434 }
435 } else {
436 vmode=default_vmode;
437 if (control_mac_modes[vmode - 1].m[full] < cmode) {
438 if (cmode > CMODE_8)
439 cmode--;
440 else
441 vmode = VMODE_640_480_60;
442 }
443 }
444
445 /* Initialize info structure */
446 control_init_info(&p->info, p);
447
448 /* Setup default var */
449 if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
450 /* This shouldn't happen! */
451 printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
452 try_again:
453 vmode = VMODE_640_480_60;
454 cmode = CMODE_8;
455 if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
456 printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
457 return -ENXIO;
458 }
459 printk(KERN_INFO "controlfb: ");
460 }
461 printk("using video mode %d and color mode %d.\n", vmode, cmode);
462
463 vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
464 if (vyres > var.yres)
465 var.yres_virtual = vyres;
466
467 /* Apply default var */
468 var.activate = FB_ACTIVATE_NOW;
469 rc = fb_set_var(&p->info, &var);
470 if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
471 goto try_again;
472
473 /* Register with fbdev layer */
474 if (register_framebuffer(&p->info) < 0)
475 return -ENXIO;
476
477 printk(KERN_INFO "fb%d: control display adapter\n", p->info.node);
478
479 return 0;
480 }
481
482 #define RADACAL_WRITE(a,d) \
483 out_8(&p->cmap_regs->addr, (a)); \
484 out_8(&p->cmap_regs->dat, (d))
485
486 /* Now how about actually saying, Make it so! */
487 /* Some things in here probably don't need to be done each time. */
488 static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
489 {
490 struct control_regvals *r;
491 volatile struct preg __iomem *rp;
492 int i, cmode;
493
494 if (PAR_EQUAL(&p->par, par)) {
495 /*
496 * check if only xoffset or yoffset differs.
497 * this prevents flickers in typical VT switch case.
498 */
499 if (p->par.xoffset != par->xoffset ||
500 p->par.yoffset != par->yoffset)
501 set_screen_start(par->xoffset, par->yoffset, p);
502
503 return;
504 }
505
506 p->par = *par;
507 cmode = p->par.cmode;
508 r = &par->regvals;
509
510 /* Turn off display */
511 out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
512
513 set_control_clock(r->clock_params);
514
515 RADACAL_WRITE(0x20, r->radacal_ctrl);
516 RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
517 RADACAL_WRITE(0x10, 0);
518 RADACAL_WRITE(0x11, 0);
519
520 rp = &p->control_regs->vswin;
521 for (i = 0; i < 16; ++i, ++rp)
522 out_le32(&rp->r, r->regs[i]);
523
524 out_le32(CNTRL_REG(p,pitch), par->pitch);
525 out_le32(CNTRL_REG(p,mode), r->mode);
526 out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
527 out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
528 + (par->xoffset << cmode));
529 out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
530 out_le32(CNTRL_REG(p,intr_ena), 0);
531
532 /* Turn on display */
533 out_le32(CNTRL_REG(p,ctrl), par->ctrl);
534
535 #ifdef CONFIG_BOOTX_TEXT
536 btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
537 p->par.xres, p->par.yres,
538 (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
539 p->par.pitch);
540 #endif /* CONFIG_BOOTX_TEXT */
541 }
542
543
544 /*
545 * Parse user speficied options (`video=controlfb:')
546 */
547 static void __init control_setup(char *options)
548 {
549 char *this_opt;
550
551 if (!options || !*options)
552 return;
553
554 while ((this_opt = strsep(&options, ",")) != NULL) {
555 if (!strncmp(this_opt, "vmode:", 6)) {
556 int vmode = simple_strtoul(this_opt+6, NULL, 0);
557 if (vmode > 0 && vmode <= VMODE_MAX &&
558 control_mac_modes[vmode - 1].m[1] >= 0)
559 default_vmode = vmode;
560 } else if (!strncmp(this_opt, "cmode:", 6)) {
561 int depth = simple_strtoul(this_opt+6, NULL, 0);
562 switch (depth) {
563 case CMODE_8:
564 case CMODE_16:
565 case CMODE_32:
566 default_cmode = depth;
567 break;
568 case 8:
569 default_cmode = CMODE_8;
570 break;
571 case 15:
572 case 16:
573 default_cmode = CMODE_16;
574 break;
575 case 24:
576 case 32:
577 default_cmode = CMODE_32;
578 break;
579 }
580 }
581 }
582 }
583
584 static int __init control_init(void)
585 {
586 struct device_node *dp;
587 char *option = NULL;
588
589 if (fb_get_options("controlfb", &option))
590 return -ENODEV;
591 control_setup(option);
592
593 dp = find_devices("control");
594 if (dp != 0 && !control_of_init(dp))
595 return 0;
596
597 return -ENXIO;
598 }
599
600 module_init(control_init);
601
602 /* Work out which banks of VRAM we have installed. */
603 /* danj: I guess the card just ignores writes to nonexistant VRAM... */
604
605 static void __init find_vram_size(struct fb_info_control *p)
606 {
607 int bank1, bank2;
608
609 /*
610 * Set VRAM in 2MB (bank 1) mode
611 * VRAM Bank 2 will be accessible through offset 0x600000 if present
612 * and VRAM Bank 1 will not respond at that offset even if present
613 */
614 out_le32(CNTRL_REG(p,vram_attr), 0x31);
615
616 out_8(&p->frame_buffer[0x600000], 0xb3);
617 out_8(&p->frame_buffer[0x600001], 0x71);
618 asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0x600000])
619 : "memory" );
620 mb();
621 asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0x600000])
622 : "memory" );
623 mb();
624
625 bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
626 && (in_8(&p->frame_buffer[0x600001]) == 0x71);
627
628 /*
629 * Set VRAM in 2MB (bank 2) mode
630 * VRAM Bank 1 will be accessible through offset 0x000000 if present
631 * and VRAM Bank 2 will not respond at that offset even if present
632 */
633 out_le32(CNTRL_REG(p,vram_attr), 0x39);
634
635 out_8(&p->frame_buffer[0], 0x5a);
636 out_8(&p->frame_buffer[1], 0xc7);
637 asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0])
638 : "memory" );
639 mb();
640 asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0])
641 : "memory" );
642 mb();
643
644 bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
645 && (in_8(&p->frame_buffer[1]) == 0xc7);
646
647 if (bank2) {
648 if (!bank1) {
649 /*
650 * vram bank 2 only
651 */
652 p->control_use_bank2 = 1;
653 p->vram_attr = 0x39;
654 p->frame_buffer += 0x600000;
655 p->frame_buffer_phys += 0x600000;
656 } else {
657 /*
658 * 4 MB vram
659 */
660 p->vram_attr = 0x51;
661 }
662 } else {
663 /*
664 * vram bank 1 only
665 */
666 p->vram_attr = 0x31;
667 }
668
669 p->total_vram = (bank1 + bank2) * 0x200000;
670
671 printk(KERN_INFO "controlfb: VRAM Total = %dMB "
672 "(%dMB @ bank 1, %dMB @ bank 2)\n",
673 (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
674 }
675
676
677 /*
678 * find "control" and initialize
679 */
680 static int __init control_of_init(struct device_node *dp)
681 {
682 struct fb_info_control *p;
683 struct resource fb_res, reg_res;
684
685 if (control_fb) {
686 printk(KERN_ERR "controlfb: only one control is supported\n");
687 return -ENXIO;
688 }
689
690 if (of_pci_address_to_resource(dp, 2, &fb_res) ||
691 of_pci_address_to_resource(dp, 1, &reg_res)) {
692 printk(KERN_ERR "can't get 2 addresses for control\n");
693 return -ENXIO;
694 }
695 p = kmalloc(sizeof(*p), GFP_KERNEL);
696 if (p == 0)
697 return -ENXIO;
698 control_fb = p; /* save it for cleanups */
699 memset(p, 0, sizeof(*p));
700
701 /* Map in frame buffer and registers */
702 p->fb_orig_base = fb_res.start;
703 p->fb_orig_size = fb_res.end - fb_res.start + 1;
704 /* use the big-endian aperture (??) */
705 p->frame_buffer_phys = fb_res.start + 0x800000;
706 p->control_regs_phys = reg_res.start;
707 p->control_regs_size = reg_res.end - reg_res.start + 1;
708
709 if (!p->fb_orig_base ||
710 !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
711 p->fb_orig_base = 0;
712 goto error_out;
713 }
714 /* map at most 8MB for the frame buffer */
715 p->frame_buffer = __ioremap(p->frame_buffer_phys, 0x800000,
716 _PAGE_WRITETHRU);
717
718 if (!p->control_regs_phys ||
719 !request_mem_region(p->control_regs_phys, p->control_regs_size,
720 "controlfb regs")) {
721 p->control_regs_phys = 0;
722 goto error_out;
723 }
724 p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
725
726 p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
727 if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
728 p->cmap_regs_phys = 0;
729 goto error_out;
730 }
731 p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
732
733 if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
734 goto error_out;
735
736 find_vram_size(p);
737 if (!p->total_vram)
738 goto error_out;
739
740 if (init_control(p) < 0)
741 goto error_out;
742
743 return 0;
744
745 error_out:
746 control_cleanup();
747 return -ENXIO;
748 }
749
750 /*
751 * Get the monitor sense value.
752 * Note that this can be called before calibrate_delay,
753 * so we can't use udelay.
754 */
755 static int read_control_sense(struct fb_info_control *p)
756 {
757 int sense;
758
759 out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
760 __delay(200);
761 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
762 __delay(2000);
763 sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
764
765 /* drive each sense line low in turn and collect the other 2 */
766 out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
767 __delay(2000);
768 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
769 out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
770 __delay(2000);
771 sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
772 | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
773 out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
774 __delay(2000);
775 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
776
777 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
778
779 return sense;
780 }
781
782 /********************** Various translation functions **********************/
783
784 #define CONTROL_PIXCLOCK_BASE 256016
785 #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
786
787 /*
788 * calculate the clock paramaters to be sent to CUDA according to given
789 * pixclock in pico second.
790 */
791 static int calc_clock_params(unsigned long clk, unsigned char *param)
792 {
793 unsigned long p0, p1, p2, k, l, m, n, min;
794
795 if (clk > (CONTROL_PIXCLOCK_BASE << 3))
796 return 1;
797
798 p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
799 l = clk << p2;
800 p0 = 0;
801 p1 = 0;
802 for (k = 1, min = l; k < 32; k++) {
803 unsigned long rem;
804
805 m = CONTROL_PIXCLOCK_BASE * k;
806 n = m / l;
807 rem = m % l;
808 if (n && (n < 128) && rem < min) {
809 p0 = k;
810 p1 = n;
811 min = rem;
812 }
813 }
814 if (!p0 || !p1)
815 return 1;
816
817 param[0] = p0;
818 param[1] = p1;
819 param[2] = p2;
820
821 return 0;
822 }
823
824
825 /*
826 * This routine takes a user-supplied var, and picks the best vmode/cmode
827 * from it.
828 */
829
830 static int control_var_to_par(struct fb_var_screeninfo *var,
831 struct fb_par_control *par, const struct fb_info *fb_info)
832 {
833 int cmode, piped_diff, hstep;
834 unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
835 hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
836 unsigned long pixclock;
837 struct fb_info_control *p = (struct fb_info_control *) fb_info;
838 struct control_regvals *r = &par->regvals;
839
840 switch (var->bits_per_pixel) {
841 case 8:
842 par->cmode = CMODE_8;
843 if (p->total_vram > 0x200000) {
844 r->mode = 3;
845 r->radacal_ctrl = 0x20;
846 piped_diff = 13;
847 } else {
848 r->mode = 2;
849 r->radacal_ctrl = 0x10;
850 piped_diff = 9;
851 }
852 break;
853 case 15:
854 case 16:
855 par->cmode = CMODE_16;
856 if (p->total_vram > 0x200000) {
857 r->mode = 2;
858 r->radacal_ctrl = 0x24;
859 piped_diff = 5;
860 } else {
861 r->mode = 1;
862 r->radacal_ctrl = 0x14;
863 piped_diff = 3;
864 }
865 break;
866 case 32:
867 par->cmode = CMODE_32;
868 if (p->total_vram > 0x200000) {
869 r->mode = 1;
870 r->radacal_ctrl = 0x28;
871 } else {
872 r->mode = 0;
873 r->radacal_ctrl = 0x18;
874 }
875 piped_diff = 1;
876 break;
877 default:
878 return -EINVAL;
879 }
880
881 /*
882 * adjust xres and vxres so that the corresponding memory widths are
883 * 32-byte aligned
884 */
885 hstep = 31 >> par->cmode;
886 par->xres = (var->xres + hstep) & ~hstep;
887 par->vxres = (var->xres_virtual + hstep) & ~hstep;
888 par->xoffset = (var->xoffset + hstep) & ~hstep;
889 if (par->vxres < par->xres)
890 par->vxres = par->xres;
891 par->pitch = par->vxres << par->cmode;
892
893 par->yres = var->yres;
894 par->vyres = var->yres_virtual;
895 par->yoffset = var->yoffset;
896 if (par->vyres < par->yres)
897 par->vyres = par->yres;
898
899 par->sync = var->sync;
900
901 if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
902 return -EINVAL;
903
904 if (par->xoffset + par->xres > par->vxres)
905 par->xoffset = par->vxres - par->xres;
906 if (par->yoffset + par->yres > par->vyres)
907 par->yoffset = par->vyres - par->yres;
908
909 pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
910 var->pixclock;
911 if (calc_clock_params(pixclock, r->clock_params))
912 return -EINVAL;
913
914 hperiod = ((var->left_margin + par->xres + var->right_margin
915 + var->hsync_len) >> 1) - 2;
916 hssync = hperiod + 1;
917 hsblank = hssync - (var->right_margin >> 1);
918 hesync = (var->hsync_len >> 1) - 1;
919 heblank = (var->left_margin >> 1) + hesync;
920 piped = heblank - piped_diff;
921 heq = var->hsync_len >> 2;
922 hlfln = (hperiod+2) >> 1;
923 hserr = hssync-hesync;
924 vperiod = (var->vsync_len + var->lower_margin + par->yres
925 + var->upper_margin) << 1;
926 vssync = vperiod - 2;
927 vesync = (var->vsync_len << 1) - vperiod + vssync;
928 veblank = (var->upper_margin << 1) + vesync;
929 vsblank = vssync - (var->lower_margin << 1);
930 vswin = (vsblank+vssync) >> 1;
931 vewin = (vesync+veblank) >> 1;
932
933 r->regs[0] = vswin;
934 r->regs[1] = vsblank;
935 r->regs[2] = veblank;
936 r->regs[3] = vewin;
937 r->regs[4] = vesync;
938 r->regs[5] = vssync;
939 r->regs[6] = vperiod;
940 r->regs[7] = piped;
941 r->regs[8] = hperiod;
942 r->regs[9] = hsblank;
943 r->regs[10] = heblank;
944 r->regs[11] = hesync;
945 r->regs[12] = hssync;
946 r->regs[13] = heq;
947 r->regs[14] = hlfln;
948 r->regs[15] = hserr;
949
950 if (par->xres >= 1280 && par->cmode >= CMODE_16)
951 par->ctrl = 0x7f;
952 else
953 par->ctrl = 0x3b;
954
955 if (mac_var_to_vmode(var, &par->vmode, &cmode))
956 par->vmode = 0;
957
958 return 0;
959 }
960
961
962 /*
963 * Convert hardware data in par to an fb_var_screeninfo
964 */
965
966 static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
967 {
968 struct control_regints *rv;
969
970 rv = (struct control_regints *) par->regvals.regs;
971
972 memset(var, 0, sizeof(*var));
973 var->xres = par->xres;
974 var->yres = par->yres;
975 var->xres_virtual = par->vxres;
976 var->yres_virtual = par->vyres;
977 var->xoffset = par->xoffset;
978 var->yoffset = par->yoffset;
979
980 switch(par->cmode) {
981 default:
982 case CMODE_8:
983 var->bits_per_pixel = 8;
984 var->red.length = 8;
985 var->green.length = 8;
986 var->blue.length = 8;
987 break;
988 case CMODE_16: /* RGB 555 */
989 var->bits_per_pixel = 16;
990 var->red.offset = 10;
991 var->red.length = 5;
992 var->green.offset = 5;
993 var->green.length = 5;
994 var->blue.length = 5;
995 break;
996 case CMODE_32: /* RGB 888 */
997 var->bits_per_pixel = 32;
998 var->red.offset = 16;
999 var->red.length = 8;
1000 var->green.offset = 8;
1001 var->green.length = 8;
1002 var->blue.length = 8;
1003 var->transp.offset = 24;
1004 var->transp.length = 8;
1005 break;
1006 }
1007 var->height = -1;
1008 var->width = -1;
1009 var->vmode = FB_VMODE_NONINTERLACED;
1010
1011 var->left_margin = (rv->heblank - rv->hesync) << 1;
1012 var->right_margin = (rv->hssync - rv->hsblank) << 1;
1013 var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
1014
1015 var->upper_margin = (rv->veblank - rv->vesync) >> 1;
1016 var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
1017 var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
1018
1019 var->sync = par->sync;
1020
1021 /*
1022 * 10^12 * clock_params[0] / (3906400 * clock_params[1]
1023 * * 2^clock_params[2])
1024 * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
1025 * >> clock_params[2]
1026 */
1027 /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
1028 var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
1029 var->pixclock /= par->regvals.clock_params[1];
1030 var->pixclock >>= par->regvals.clock_params[2];
1031 }
1032
1033 /*
1034 * Set misc info vars for this driver
1035 */
1036 static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
1037 {
1038 /* Fill fb_info */
1039 info->par = &p->par;
1040 info->fbops = &controlfb_ops;
1041 info->pseudo_palette = p->pseudo_palette;
1042 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1043 info->screen_base = p->frame_buffer + CTRLFB_OFF;
1044
1045 fb_alloc_cmap(&info->cmap, 256, 0);
1046
1047 /* Fill fix common fields */
1048 strcpy(info->fix.id, "control");
1049 info->fix.mmio_start = p->control_regs_phys;
1050 info->fix.mmio_len = sizeof(struct control_regs);
1051 info->fix.type = FB_TYPE_PACKED_PIXELS;
1052 info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
1053 info->fix.smem_len = p->total_vram - CTRLFB_OFF;
1054 info->fix.ywrapstep = 0;
1055 info->fix.type_aux = 0;
1056 info->fix.accel = FB_ACCEL_NONE;
1057 }
1058
1059
1060 static void control_cleanup(void)
1061 {
1062 struct fb_info_control *p = control_fb;
1063
1064 if (!p)
1065 return;
1066
1067 if (p->cmap_regs)
1068 iounmap(p->cmap_regs);
1069 if (p->control_regs)
1070 iounmap(p->control_regs);
1071 if (p->frame_buffer) {
1072 if (p->control_use_bank2)
1073 p->frame_buffer -= 0x600000;
1074 iounmap(p->frame_buffer);
1075 }
1076 if (p->cmap_regs_phys)
1077 release_mem_region(p->cmap_regs_phys, 0x1000);
1078 if (p->control_regs_phys)
1079 release_mem_region(p->control_regs_phys, p->control_regs_size);
1080 if (p->fb_orig_base)
1081 release_mem_region(p->fb_orig_base, p->fb_orig_size);
1082 kfree(p);
1083 }
1084
1085
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