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[NETFILTER]: ip_tables: fix module refcount leaks in compat error paths
[hh.org.git] / drivers / video / tdfxfb.c
blob689ce0270b81adc8108c0db78d34f9be37a2cbc3
1 /*
2 *
3 * tdfxfb.c
4 *
5 * Author: Hannu Mallat <hmallat@cc.hut.fi>
6 *
7 * Copyright © 1999 Hannu Mallat
8 * All rights reserved
9 *
10 * Created : Thu Sep 23 18:17:43 1999, hmallat
11 * Last modified: Tue Nov 2 21:19:47 1999, hmallat
12 *
13 * Lots of the information here comes from the Daryll Strauss' Banshee
14 * patches to the XF86 server, and the rest comes from the 3dfx
15 * Banshee specification. I'm very much indebted to Daryll for his
16 * work on the X server.
17 *
18 * Voodoo3 support was contributed Harold Oga. Lots of additions
19 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
20 * Kesmarki. Thanks guys!
21 *
22 * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
23 * behave very differently from the Voodoo3/4/5. For anyone wanting to
24 * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
25 * located at http://www.sourceforge.net/projects/sstfb).
26 *
27 * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
28 * I do wish the next version is a bit more complete. Without the XF86
29 * patches I couldn't have gotten even this far... for instance, the
30 * extensions to the VGA register set go completely unmentioned in the
31 * spec! Also, lots of references are made to the 'SST core', but no
32 * spec is publicly available, AFAIK.
33 *
34 * The structure of this driver comes pretty much from the Permedia
35 * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
36 *
37 * TODO:
38 * - support for 16/32 bpp needs fixing (funky bootup penguin)
39 * - multihead support (basically need to support an array of fb_infos)
40 * - support other architectures (PPC, Alpha); does the fact that the VGA
41 * core can be accessed only thru I/O (not memory mapped) complicate
42 * things?
43 *
44 * Version history:
45 *
46 * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
47 *
48 * 0.1.3 (released 1999-11-02) added Attila's panning support, code
49 * reorg, hwcursor address page size alignment
50 * (for mmaping both frame buffer and regs),
51 * and my changes to get rid of hardcoded
52 * VGA i/o register locations (uses PCI
53 * configuration info now)
54 * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
55 * improvements
56 * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
57 * 0.1.0 (released 1999-10-06) initial version
58 *
59 */
60
61 #include <linux/module.h>
62 #include <linux/kernel.h>
63 #include <linux/errno.h>
64 #include <linux/string.h>
65 #include <linux/mm.h>
66 #include <linux/slab.h>
67 #include <linux/delay.h>
68 #include <linux/interrupt.h>
69 #include <linux/fb.h>
70 #include <linux/init.h>
71 #include <linux/pci.h>
72 #include <linux/nvram.h>
73 #include <asm/io.h>
74 #include <linux/timer.h>
75 #include <linux/spinlock.h>
76
77 #include <video/tdfx.h>
78
79 #undef TDFXFB_DEBUG
80 #ifdef TDFXFB_DEBUG
81 #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
82 #else
83 #define DPRINTK(a,b...)
84 #endif
85
86 #define BANSHEE_MAX_PIXCLOCK 270000
87 #define VOODOO3_MAX_PIXCLOCK 300000
88 #define VOODOO5_MAX_PIXCLOCK 350000
89
90 static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
91 .id = "3Dfx",
92 .type = FB_TYPE_PACKED_PIXELS,
93 .visual = FB_VISUAL_PSEUDOCOLOR,
94 .ypanstep = 1,
95 .ywrapstep = 1,
96 .accel = FB_ACCEL_3DFX_BANSHEE
97 };
98
99 static struct fb_var_screeninfo tdfx_var __devinitdata = {
100 /* "640x480, 8 bpp @ 60 Hz */
101 .xres = 640,
102 .yres = 480,
103 .xres_virtual = 640,
104 .yres_virtual = 1024,
105 .bits_per_pixel =8,
106 .red = {0, 8, 0},
107 .blue = {0, 8, 0},
108 .green = {0, 8, 0},
109 .activate = FB_ACTIVATE_NOW,
110 .height = -1,
111 .width = -1,
112 .accel_flags = FB_ACCELF_TEXT,
113 .pixclock = 39722,
114 .left_margin = 40,
115 .right_margin = 24,
116 .upper_margin = 32,
117 .lower_margin = 11,
118 .hsync_len = 96,
119 .vsync_len = 2,
120 .vmode = FB_VMODE_NONINTERLACED
121 };
122
123 /*
124 * PCI driver prototypes
125 */
126 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
127 const struct pci_device_id *id);
128 static void __devexit tdfxfb_remove(struct pci_dev *pdev);
129
130 static struct pci_device_id tdfxfb_id_table[] = {
131 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
132 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
133 0xff0000, 0 },
134 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
135 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
136 0xff0000, 0 },
137 { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
138 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
139 0xff0000, 0 },
140 { 0, }
141 };
142
143 static struct pci_driver tdfxfb_driver = {
144 .name = "tdfxfb",
145 .id_table = tdfxfb_id_table,
146 .probe = tdfxfb_probe,
147 .remove = __devexit_p(tdfxfb_remove),
148 };
149
150 MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
151
152 /*
153 * Frame buffer device API
154 */
155 static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
156 static int tdfxfb_set_par(struct fb_info *info);
157 static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
158 u_int transp, struct fb_info *info);
159 static int tdfxfb_blank(int blank, struct fb_info *info);
160 static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
161 static int banshee_wait_idle(struct fb_info *info);
162 #ifdef CONFIG_FB_3DFX_ACCEL
163 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
164 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
165 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
166 #endif /* CONFIG_FB_3DFX_ACCEL */
167
168 static struct fb_ops tdfxfb_ops = {
169 .owner = THIS_MODULE,
170 .fb_check_var = tdfxfb_check_var,
171 .fb_set_par = tdfxfb_set_par,
172 .fb_setcolreg = tdfxfb_setcolreg,
173 .fb_blank = tdfxfb_blank,
174 .fb_pan_display = tdfxfb_pan_display,
175 .fb_sync = banshee_wait_idle,
176 #ifdef CONFIG_FB_3DFX_ACCEL
177 .fb_fillrect = tdfxfb_fillrect,
178 .fb_copyarea = tdfxfb_copyarea,
179 .fb_imageblit = tdfxfb_imageblit,
180 #else
181 .fb_fillrect = cfb_fillrect,
182 .fb_copyarea = cfb_copyarea,
183 .fb_imageblit = cfb_imageblit,
184 #endif
185 };
186
187 /*
188 * do_xxx: Hardware-specific functions
189 */
190 static u32 do_calc_pll(int freq, int *freq_out);
191 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
192 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
193
194 /*
195 * Driver data
196 */
197 static int nopan = 0;
198 static int nowrap = 1; // not implemented (yet)
199 static char *mode_option __devinitdata = NULL;
200
201 /* -------------------------------------------------------------------------
202 * Hardware-specific funcions
203 * ------------------------------------------------------------------------- */
204
205 #ifdef VGA_REG_IO
206 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
207
208 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
209 #else
210 static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
211 return inb(par->iobase + reg - 0x300);
212 }
213 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
214 outb(val, par->iobase + reg - 0x300);
215 }
216 #endif
217
218 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
219 vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
220 }
221
222 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
223 vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
224 }
225
226 static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
227 vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
228 }
229
230 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
231 vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
232 }
233
234 static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
235 vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
236 }
237
238 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
239 {
240 unsigned char tmp;
241
242 tmp = vga_inb(par, IS1_R);
243 vga_outb(par, ATT_IW, idx);
244 vga_outb(par, ATT_IW, val);
245 }
246
247 static inline void vga_disable_video(struct tdfx_par *par)
248 {
249 unsigned char s;
250
251 s = seq_inb(par, 0x01) | 0x20;
252 seq_outb(par, 0x00, 0x01);
253 seq_outb(par, 0x01, s);
254 seq_outb(par, 0x00, 0x03);
255 }
256
257 static inline void vga_enable_video(struct tdfx_par *par)
258 {
259 unsigned char s;
260
261 s = seq_inb(par, 0x01) & 0xdf;
262 seq_outb(par, 0x00, 0x01);
263 seq_outb(par, 0x01, s);
264 seq_outb(par, 0x00, 0x03);
265 }
266
267 static inline void vga_enable_palette(struct tdfx_par *par)
268 {
269 vga_inb(par, IS1_R);
270 vga_outb(par, ATT_IW, 0x20);
271 }
272
273 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
274 {
275 return readl(par->regbase_virt + reg);
276 }
277
278 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
279 {
280 writel(val, par->regbase_virt + reg);
281 }
282
283 static inline void banshee_make_room(struct tdfx_par *par, int size)
284 {
285 /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
286 * won't quit if you ask for more. */
287 while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
288 }
289
290 static int banshee_wait_idle(struct fb_info *info)
291 {
292 struct tdfx_par *par = info->par;
293 int i = 0;
294
295 banshee_make_room(par, 1);
296 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
297
298 while(1) {
299 i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
300 if(i == 3) break;
301 }
302 return 0;
303 }
304
305 /*
306 * Set the color of a palette entry in 8bpp mode
307 */
308 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
309 {
310 banshee_make_room(par, 2);
311 tdfx_outl(par, DACADDR, regno);
312 tdfx_outl(par, DACDATA, c);
313 }
314
315 static u32 do_calc_pll(int freq, int* freq_out)
316 {
317 int m, n, k, best_m, best_n, best_k, best_error;
318 int fref = 14318;
319
320 best_error = freq;
321 best_n = best_m = best_k = 0;
322
323 for (k = 3; k >= 0; k--) {
324 for (m = 63; m >= 0; m--) {
325 /*
326 * Estimate value of n that produces target frequency
327 * with current m and k
328 */
329 int n_estimated = (freq * (m + 2) * (1 << k) / fref) - 2;
330
331 /* Search neighborhood of estimated n */
332 for (n = max(0, n_estimated - 1);
333 n <= min(255, n_estimated + 1); n++) {
334 /*
335 * Calculate PLL freqency with current m, k and
336 * estimated n
337 */
338 int f = fref * (n + 2) / (m + 2) / (1 << k);
339 int error = abs (f - freq);
340
341 /*
342 * If this is the closest we've come to the
343 * target frequency then remember n, m and k
344 */
345 if (error < best_error) {
346 best_error = error;
347 best_n = n;
348 best_m = m;
349 best_k = k;
350 }
351 }
352 }
353 }
354
355 n = best_n;
356 m = best_m;
357 k = best_k;
358 *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
359
360 return (n << 8) | (m << 2) | k;
361 }
362
363 static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
364 {
365 struct tdfx_par *par = info->par;
366 int i;
367
368 banshee_wait_idle(info);
369
370 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
371
372 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
373
374 banshee_make_room(par, 3);
375 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
376 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
377 #if 0
378 tdfx_outl(par, PLLCTRL1, reg->mempll);
379 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
380 #endif
381 tdfx_outl(par, PLLCTRL0, reg->vidpll);
382
383 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
384
385 for (i = 0; i < 5; i++)
386 seq_outb(par, i, reg->seq[i]);
387
388 for (i = 0; i < 25; i++)
389 crt_outb(par, i, reg->crt[i]);
390
391 for (i = 0; i < 9; i++)
392 gra_outb(par, i, reg->gra[i]);
393
394 for (i = 0; i < 21; i++)
395 att_outb(par, i, reg->att[i]);
396
397 crt_outb(par, 0x1a, reg->ext[0]);
398 crt_outb(par, 0x1b, reg->ext[1]);
399
400 vga_enable_palette(par);
401 vga_enable_video(par);
402
403 banshee_make_room(par, 11);
404 tdfx_outl(par, VGAINIT0, reg->vgainit0);
405 tdfx_outl(par, DACMODE, reg->dacmode);
406 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
407 tdfx_outl(par, HWCURPATADDR, 0);
408
409 tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
410 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
411 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
412 tdfx_outl(par, VGAINIT1, reg->vgainit1);
413 tdfx_outl(par, MISCINIT0, reg->miscinit0);
414
415 banshee_make_room(par, 8);
416 tdfx_outl(par, SRCBASE, reg->srcbase);
417 tdfx_outl(par, DSTBASE, reg->dstbase);
418 tdfx_outl(par, COMMANDEXTRA_2D, 0);
419 tdfx_outl(par, CLIP0MIN, 0);
420 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
421 tdfx_outl(par, CLIP1MIN, 0);
422 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
423 tdfx_outl(par, SRCXY, 0);
424
425 banshee_wait_idle(info);
426 }
427
428 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
429 {
430 u32 draminit0;
431 u32 draminit1;
432 u32 miscinit1;
433
434 int num_chips;
435 int chip_size; /* in MB */
436 u32 lfbsize;
437 int has_sgram;
438
439 draminit0 = tdfx_inl(par, DRAMINIT0);
440 draminit1 = tdfx_inl(par, DRAMINIT1);
441
442 num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
443
444 if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
445 /* Banshee/Voodoo3 */
446 has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
447 chip_size = has_sgram ? ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 2 : 1)
448 : 2;
449 } else {
450 /* Voodoo4/5 */
451 has_sgram = 0;
452 chip_size = 1 << ((draminit0 & DRAMINIT0_SGRAM_TYPE_MASK) >> DRAMINIT0_SGRAM_TYPE_SHIFT);
453 }
454 lfbsize = num_chips * chip_size * 1024 * 1024;
455
456 /* disable block writes for SDRAM */
457 miscinit1 = tdfx_inl(par, MISCINIT1);
458 miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
459 miscinit1 |= MISCINIT1_CLUT_INV;
460
461 banshee_make_room(par, 1);
462 tdfx_outl(par, MISCINIT1, miscinit1);
463 return lfbsize;
464 }
465
466 /* ------------------------------------------------------------------------- */
467
468 static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
469 {
470 struct tdfx_par *par = info->par;
471 u32 lpitch;
472
473 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
474 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
475 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
476 return -EINVAL;
477 }
478
479 if (var->xres != var->xres_virtual)
480 var->xres_virtual = var->xres;
481
482 if (var->yres > var->yres_virtual)
483 var->yres_virtual = var->yres;
484
485 if (var->xoffset) {
486 DPRINTK("xoffset not supported\n");
487 return -EINVAL;
488 }
489
490 /* Banshee doesn't support interlace, but Voodoo4/5 and probably Voodoo3 do. */
491 /* no direct information about device id now? use max_pixclock for this... */
492 if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
493 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
494 DPRINTK("interlace not supported\n");
495 return -EINVAL;
496 }
497
498 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
499 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
500
501 if (var->xres < 320 || var->xres > 2048) {
502 DPRINTK("width not supported: %u\n", var->xres);
503 return -EINVAL;
504 }
505
506 if (var->yres < 200 || var->yres > 2048) {
507 DPRINTK("height not supported: %u\n", var->yres);
508 return -EINVAL;
509 }
510
511 if (lpitch * var->yres_virtual > info->fix.smem_len) {
512 var->yres_virtual = info->fix.smem_len/lpitch;
513 if (var->yres_virtual < var->yres) {
514 DPRINTK("no memory for screen (%ux%ux%u)\n",
515 var->xres, var->yres_virtual, var->bits_per_pixel);
516 return -EINVAL;
517 }
518 }
519
520 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
521 DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
522 return -EINVAL;
523 }
524
525 switch(var->bits_per_pixel) {
526 case 8:
527 var->red.length = var->green.length = var->blue.length = 8;
528 break;
529 case 16:
530 var->red.offset = 11;
531 var->red.length = 5;
532 var->green.offset = 5;
533 var->green.length = 6;
534 var->blue.offset = 0;
535 var->blue.length = 5;
536 break;
537 case 24:
538 var->red.offset=16;
539 var->green.offset=8;
540 var->blue.offset=0;
541 var->red.length = var->green.length = var->blue.length = 8;
542 case 32:
543 var->red.offset = 16;
544 var->green.offset = 8;
545 var->blue.offset = 0;
546 var->red.length = var->green.length = var->blue.length = 8;
547 break;
548 }
549 var->height = var->width = -1;
550
551 var->accel_flags = FB_ACCELF_TEXT;
552
553 DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
554 return 0;
555 }
556
557 static int tdfxfb_set_par(struct fb_info *info)
558 {
559 struct tdfx_par *par = info->par;
560 u32 hdispend, hsyncsta, hsyncend, htotal;
561 u32 hd, hs, he, ht, hbs, hbe;
562 u32 vd, vs, ve, vt, vbs, vbe;
563 struct banshee_reg reg;
564 int fout, freq;
565 u32 wd, cpp;
566
567 par->baseline = 0;
568
569 memset(&reg, 0, sizeof(reg));
570 cpp = (info->var.bits_per_pixel + 7)/8;
571
572 reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
573
574 /* PLL settings */
575 freq = PICOS2KHZ(info->var.pixclock);
576
577 reg.dacmode = 0;
578 reg.vidcfg &= ~VIDCFG_2X;
579
580 hdispend = info->var.xres;
581 hsyncsta = hdispend + info->var.right_margin;
582 hsyncend = hsyncsta + info->var.hsync_len;
583 htotal = hsyncend + info->var.left_margin;
584
585 if (freq > par->max_pixclock/2) {
586 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
587 reg.dacmode |= DACMODE_2X;
588 reg.vidcfg |= VIDCFG_2X;
589 hdispend >>= 1;
590 hsyncsta >>= 1;
591 hsyncend >>= 1;
592 htotal >>= 1;
593 }
594
595 hd = wd = (hdispend >> 3) - 1;
596 hs = (hsyncsta >> 3) - 1;
597 he = (hsyncend >> 3) - 1;
598 ht = (htotal >> 3) - 1;
599 hbs = hd;
600 hbe = ht;
601
602 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
603 vbs = vd = (info->var.yres << 1) - 1;
604 vs = vd + (info->var.lower_margin << 1);
605 ve = vs + (info->var.vsync_len << 1);
606 vbe = vt = ve + (info->var.upper_margin << 1) - 1;
607 } else {
608 vbs = vd = info->var.yres - 1;
609 vs = vd + info->var.lower_margin;
610 ve = vs + info->var.vsync_len;
611 vbe = vt = ve + info->var.upper_margin - 1;
612 }
613
614 /* this is all pretty standard VGA register stuffing */
615 reg.misc[0x00] = 0x0f |
616 (info->var.xres < 400 ? 0xa0 :
617 info->var.xres < 480 ? 0x60 :
618 info->var.xres < 768 ? 0xe0 : 0x20);
619
620 reg.gra[0x00] = 0x00;
621 reg.gra[0x01] = 0x00;
622 reg.gra[0x02] = 0x00;
623 reg.gra[0x03] = 0x00;
624 reg.gra[0x04] = 0x00;
625 reg.gra[0x05] = 0x40;
626 reg.gra[0x06] = 0x05;
627 reg.gra[0x07] = 0x0f;
628 reg.gra[0x08] = 0xff;
629
630 reg.att[0x00] = 0x00;
631 reg.att[0x01] = 0x01;
632 reg.att[0x02] = 0x02;
633 reg.att[0x03] = 0x03;
634 reg.att[0x04] = 0x04;
635 reg.att[0x05] = 0x05;
636 reg.att[0x06] = 0x06;
637 reg.att[0x07] = 0x07;
638 reg.att[0x08] = 0x08;
639 reg.att[0x09] = 0x09;
640 reg.att[0x0a] = 0x0a;
641 reg.att[0x0b] = 0x0b;
642 reg.att[0x0c] = 0x0c;
643 reg.att[0x0d] = 0x0d;
644 reg.att[0x0e] = 0x0e;
645 reg.att[0x0f] = 0x0f;
646 reg.att[0x10] = 0x41;
647 reg.att[0x11] = 0x00;
648 reg.att[0x12] = 0x0f;
649 reg.att[0x13] = 0x00;
650 reg.att[0x14] = 0x00;
651
652 reg.seq[0x00] = 0x03;
653 reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
654 reg.seq[0x02] = 0x0f;
655 reg.seq[0x03] = 0x00;
656 reg.seq[0x04] = 0x0e;
657
658 reg.crt[0x00] = ht - 4;
659 reg.crt[0x01] = hd;
660 reg.crt[0x02] = hbs;
661 reg.crt[0x03] = 0x80 | (hbe & 0x1f);
662 reg.crt[0x04] = hs;
663 reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
664 reg.crt[0x06] = vt;
665 reg.crt[0x07] = ((vs & 0x200) >> 2) |
666 ((vd & 0x200) >> 3) |
667 ((vt & 0x200) >> 4) | 0x10 |
668 ((vbs & 0x100) >> 5) |
669 ((vs & 0x100) >> 6) |
670 ((vd & 0x100) >> 7) |
671 ((vt & 0x100) >> 8);
672 reg.crt[0x08] = 0x00;
673 reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
674 reg.crt[0x0a] = 0x00;
675 reg.crt[0x0b] = 0x00;
676 reg.crt[0x0c] = 0x00;
677 reg.crt[0x0d] = 0x00;
678 reg.crt[0x0e] = 0x00;
679 reg.crt[0x0f] = 0x00;
680 reg.crt[0x10] = vs;
681 reg.crt[0x11] = (ve & 0x0f) | 0x20;
682 reg.crt[0x12] = vd;
683 reg.crt[0x13] = wd;
684 reg.crt[0x14] = 0x00;
685 reg.crt[0x15] = vbs;
686 reg.crt[0x16] = vbe + 1;
687 reg.crt[0x17] = 0xc3;
688 reg.crt[0x18] = 0xff;
689
690 /* Banshee's nonvga stuff */
691 reg.ext[0x00] = (((ht & 0x100) >> 8) |
692 ((hd & 0x100) >> 6) |
693 ((hbs & 0x100) >> 4) |
694 ((hbe & 0x40) >> 1) |
695 ((hs & 0x100) >> 2) |
696 ((he & 0x20) << 2));
697 reg.ext[0x01] = (((vt & 0x400) >> 10) |
698 ((vd & 0x400) >> 8) |
699 ((vbs & 0x400) >> 6) |
700 ((vbe & 0x400) >> 4));
701
702 reg.vgainit0 = VGAINIT0_8BIT_DAC |
703 VGAINIT0_EXT_ENABLE |
704 VGAINIT0_WAKEUP_3C3 |
705 VGAINIT0_ALT_READBACK |
706 VGAINIT0_EXTSHIFTOUT;
707 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
708
709 reg.cursloc = 0;
710
711 reg.cursc0 = 0;
712 reg.cursc1 = 0xffffff;
713
714 reg.stride = info->var.xres * cpp;
715 reg.startaddr = par->baseline * reg.stride;
716 reg.srcbase = reg.startaddr;
717 reg.dstbase = reg.startaddr;
718
719 /* PLL settings */
720 freq = PICOS2KHZ(info->var.pixclock);
721
722 reg.dacmode &= ~DACMODE_2X;
723 reg.vidcfg &= ~VIDCFG_2X;
724 if (freq > par->max_pixclock/2) {
725 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
726 reg.dacmode |= DACMODE_2X;
727 reg.vidcfg |= VIDCFG_2X;
728 }
729 reg.vidpll = do_calc_pll(freq, &fout);
730 #if 0
731 reg.mempll = do_calc_pll(..., &fout);
732 reg.gfxpll = do_calc_pll(..., &fout);
733 #endif
734
735 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
736 reg.screensize = info->var.xres | (info->var.yres << 13);
737 reg.vidcfg |= VIDCFG_HALF_MODE;
738 reg.crt[0x09] |= 0x80;
739 } else {
740 reg.screensize = info->var.xres | (info->var.yres << 12);
741 reg.vidcfg &= ~VIDCFG_HALF_MODE;
742 }
743 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
744 reg.vidcfg |= VIDCFG_INTERLACE;
745 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
746
747 #if defined(__BIG_ENDIAN)
748 switch (info->var.bits_per_pixel) {
749 case 8:
750 case 24:
751 reg.miscinit0 &= ~(1 << 30);
752 reg.miscinit0 &= ~(1 << 31);
753 break;
754 case 16:
755 reg.miscinit0 |= (1 << 30);
756 reg.miscinit0 |= (1 << 31);
757 break;
758 case 32:
759 reg.miscinit0 |= (1 << 30);
760 reg.miscinit0 &= ~(1 << 31);
761 break;
762 }
763 #endif
764 do_write_regs(info, &reg);
765
766 /* Now change fb_fix_screeninfo according to changes in par */
767 info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
768 info->fix.visual = (info->var.bits_per_pixel == 8)
769 ? FB_VISUAL_PSEUDOCOLOR
770 : FB_VISUAL_TRUECOLOR;
771 DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
772 return 0;
773 }
774
775 /* A handy macro shamelessly pinched from matroxfb */
776 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
777
778 static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
779 unsigned blue,unsigned transp,struct fb_info *info)
780 {
781 struct tdfx_par *par = info->par;
782 u32 rgbcol;
783
784 if (regno >= info->cmap.len || regno > 255) return 1;
785
786 switch (info->fix.visual) {
787 case FB_VISUAL_PSEUDOCOLOR:
788 rgbcol =(((u32)red & 0xff00) << 8) |
789 (((u32)green & 0xff00) << 0) |
790 (((u32)blue & 0xff00) >> 8);
791 do_setpalentry(par, regno, rgbcol);
792 break;
793 /* Truecolor has no hardware color palettes. */
794 case FB_VISUAL_TRUECOLOR:
795 if (regno < 16) {
796 rgbcol = (CNVT_TOHW( red, info->var.red.length) <<
797 info->var.red.offset) |
798 (CNVT_TOHW( green, info->var.green.length) <<
799 info->var.green.offset) |
800 (CNVT_TOHW( blue, info->var.blue.length) <<
801 info->var.blue.offset) |
802 (CNVT_TOHW( transp, info->var.transp.length) <<
803 info->var.transp.offset);
804 par->palette[regno] = rgbcol;
805 }
806
807 break;
808 default:
809 DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
810 break;
811 }
812
813 return 0;
814 }
815
816 /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
817 static int tdfxfb_blank(int blank, struct fb_info *info)
818 {
819 struct tdfx_par *par = info->par;
820 u32 dacmode, state = 0, vgablank = 0;
821
822 dacmode = tdfx_inl(par, DACMODE);
823
824 switch (blank) {
825 case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
826 state = 0;
827 vgablank = 0;
828 break;
829 case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
830 state = 0;
831 vgablank = 1;
832 break;
833 case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
834 state = BIT(3);
835 vgablank = 1;
836 break;
837 case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
838 state = BIT(1);
839 vgablank = 1;
840 break;
841 case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
842 state = BIT(1) | BIT(3);
843 vgablank = 1;
844 break;
845 }
846
847 dacmode &= ~(BIT(1) | BIT(3));
848 dacmode |= state;
849 banshee_make_room(par, 1);
850 tdfx_outl(par, DACMODE, dacmode);
851 if (vgablank)
852 vga_disable_video(par);
853 else
854 vga_enable_video(par);
855 return 0;
856 }
857
858 /*
859 * Set the starting position of the visible screen to var->yoffset
860 */
861 static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
862 struct fb_info *info)
863 {
864 struct tdfx_par *par = info->par;
865 u32 addr;
866
867 if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
868 return -EINVAL;
869 if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
870 return -EINVAL;
871
872 addr = var->yoffset * info->fix.line_length;
873 banshee_make_room(par, 1);
874 tdfx_outl(par, VIDDESKSTART, addr);
875
876 info->var.xoffset = var->xoffset;
877 info->var.yoffset = var->yoffset;
878 return 0;
879 }
880
881 #ifdef CONFIG_FB_3DFX_ACCEL
882 /*
883 * FillRect 2D command (solidfill or invert (via ROP_XOR))
884 */
885 static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
886 {
887 struct tdfx_par *par = info->par;
888 u32 bpp = info->var.bits_per_pixel;
889 u32 stride = info->fix.line_length;
890 u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
891 int tdfx_rop;
892
893 if (rect->rop == ROP_COPY)
894 tdfx_rop = TDFX_ROP_COPY;
895 else
896 tdfx_rop = TDFX_ROP_XOR;
897
898 banshee_make_room(par, 5);
899 tdfx_outl(par, DSTFORMAT, fmt);
900 if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
901 tdfx_outl(par, COLORFORE, rect->color);
902 } else { /* FB_VISUAL_TRUECOLOR */
903 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
904 }
905 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
906 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
907 tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
908 }
909
910 /*
911 * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
912 */
913 static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
914 {
915 struct tdfx_par *par = info->par;
916 u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
917 u32 bpp = info->var.bits_per_pixel;
918 u32 stride = info->fix.line_length;
919 u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
920 u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
921
922 if (area->sx <= area->dx) {
923 //-X
924 blitcmd |= BIT(14);
925 sx += area->width - 1;
926 dx += area->width - 1;
927 }
928 if (area->sy <= area->dy) {
929 //-Y
930 blitcmd |= BIT(15);
931 sy += area->height - 1;
932 dy += area->height - 1;
933 }
934
935 banshee_make_room(par, 6);
936
937 tdfx_outl(par, SRCFORMAT, fmt);
938 tdfx_outl(par, DSTFORMAT, fmt);
939 tdfx_outl(par, COMMAND_2D, blitcmd);
940 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
941 tdfx_outl(par, DSTXY, dx | (dy << 16));
942 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
943 }
944
945 static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
946 {
947 struct tdfx_par *par = info->par;
948 int size = image->height * ((image->width * image->depth + 7)>>3);
949 int fifo_free;
950 int i, stride = info->fix.line_length;
951 u32 bpp = info->var.bits_per_pixel;
952 u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
953 u8 *chardata = (u8 *) image->data;
954 u32 srcfmt;
955
956 if (image->depth != 1) {
957 //banshee_make_room(par, 6 + ((size + 3) >> 2));
958 //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
959 cfb_imageblit(info, image);
960 return;
961 } else {
962 banshee_make_room(par, 8);
963 switch (info->fix.visual) {
964 case FB_VISUAL_PSEUDOCOLOR:
965 tdfx_outl(par, COLORFORE, image->fg_color);
966 tdfx_outl(par, COLORBACK, image->bg_color);
967 break;
968 case FB_VISUAL_TRUECOLOR:
969 default:
970 tdfx_outl(par, COLORFORE,
971 par->palette[image->fg_color]);
972 tdfx_outl(par, COLORBACK,
973 par->palette[image->bg_color]);
974 }
975 #ifdef __BIG_ENDIAN
976 srcfmt = 0x400000 | BIT(20);
977 #else
978 srcfmt = 0x400000;
979 #endif
980 }
981
982 tdfx_outl(par, SRCXY, 0);
983 tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
984 tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
985 tdfx_outl(par, SRCFORMAT, srcfmt);
986 tdfx_outl(par, DSTFORMAT, dstfmt);
987 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
988
989 /* A count of how many free FIFO entries we've requested.
990 * When this goes negative, we need to request more. */
991 fifo_free = 0;
992
993 /* Send four bytes at a time of data */
994 for (i = (size >> 2) ; i > 0; i--) {
995 if(--fifo_free < 0) {
996 fifo_free=31;
997 banshee_make_room(par,fifo_free);
998 }
999 tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
1000 chardata += 4;
1001 }
1002
1003 /* Send the leftovers now */
1004 banshee_make_room(par,3);
1005 i = size%4;
1006 switch (i) {
1007 case 0: break;
1008 case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
1009 case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
1010 case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
1011 }
1012 }
1013 #endif /* CONFIG_FB_3DFX_ACCEL */
1014
1015 #ifdef TDFX_HARDWARE_CURSOR
1016 static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1017 {
1018 struct tdfx_par *par = info->par;
1019 unsigned long flags;
1020
1021 /*
1022 * If the cursor is not be changed this means either we want the
1023 * current cursor state (if enable is set) or we want to query what
1024 * we can do with the cursor (if enable is not set)
1025 */
1026 if (!cursor->set) return 0;
1027
1028 /* Too large of a cursor :-( */
1029 if (cursor->image.width > 64 || cursor->image.height > 64)
1030 return -ENXIO;
1031
1032 /*
1033 * If we are going to be changing things we should disable
1034 * the cursor first
1035 */
1036 if (info->cursor.enable) {
1037 spin_lock_irqsave(&par->DAClock, flags);
1038 info->cursor.enable = 0;
1039 del_timer(&(par->hwcursor.timer));
1040 tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
1041 spin_unlock_irqrestore(&par->DAClock, flags);
1042 }
1043
1044 /* Disable the Cursor */
1045 if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
1046 return 0;
1047
1048 /* fix cursor color - XFree86 forgets to restore it properly */
1049 if (cursor->set && FB_CUR_SETCMAP) {
1050 struct fb_cmap cmap = cursor->image.cmap;
1051 unsigned long bg_color, fg_color;
1052
1053 cmap.len = 2; /* Voodoo 3+ only support 2 color cursors */
1054 fg_color = ((cmap.red[cmap.start] << 16) |
1055 (cmap.green[cmap.start] << 8) |
1056 (cmap.blue[cmap.start]));
1057 bg_color = ((cmap.red[cmap.start+1] << 16) |
1058 (cmap.green[cmap.start+1] << 8) |
1059 (cmap.blue[cmap.start+1]));
1060 fb_copy_cmap(&cmap, &info->cursor.image.cmap);
1061 spin_lock_irqsave(&par->DAClock, flags);
1062 banshee_make_room(par, 2);
1063 tdfx_outl(par, HWCURC0, bg_color);
1064 tdfx_outl(par, HWCURC1, fg_color);
1065 spin_unlock_irqrestore(&par->DAClock, flags);
1066 }
1067
1068 if (cursor->set && FB_CUR_SETPOS) {
1069 int x, y;
1070
1071 x = cursor->image.dx;
1072 y = cursor->image.dy;
1073 y -= info->var.yoffset;
1074 info->cursor.image.dx = x;
1075 info->cursor.image.dy = y;
1076 x += 63;
1077 y += 63;
1078 spin_lock_irqsave(&par->DAClock, flags);
1079 banshee_make_room(par, 1);
1080 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1081 spin_unlock_irqrestore(&par->DAClock, flags);
1082 }
1083
1084 /* Not supported so we fake it */
1085 if (cursor->set && FB_CUR_SETHOT) {
1086 info->cursor.hot.x = cursor->hot.x;
1087 info->cursor.hot.y = cursor->hot.y;
1088 }
1089
1090 if (cursor->set && FB_CUR_SETSHAPE) {
1091 /*
1092 * Voodoo 3 and above cards use 2 monochrome cursor patterns.
1093 * The reason is so the card can fetch 8 words at a time
1094 * and are stored on chip for use for the next 8 scanlines.
1095 * This reduces the number of times for access to draw the
1096 * cursor for each screen refresh.
1097 * Each pattern is a bitmap of 64 bit wide and 64 bit high
1098 * (total of 8192 bits or 1024 Kbytes). The two patterns are
1099 * stored in such a way that pattern 0 always resides in the
1100 * lower half (least significant 64 bits) of a 128 bit word
1101 * and pattern 1 the upper half. If you examine the data of
1102 * the cursor image the graphics card uses then from the
1103 * begining you see line one of pattern 0, line one of
1104 * pattern 1, line two of pattern 0, line two of pattern 1,
1105 * etc etc. The linear stride for the cursor is always 16 bytes
1106 * (128 bits) which is the maximum cursor width times two for
1107 * the two monochrome patterns.
1108 */
1109 u8 *cursorbase = (u8 *) info->cursor.image.data;
1110 char *bitmap = (char *)cursor->image.data;
1111 char *mask = (char *) cursor->mask;
1112 int i, j, k, h = 0;
1113
1114 for (i = 0; i < 64; i++) {
1115 if (i < cursor->image.height) {
1116 j = (cursor->image.width + 7) >> 3;
1117 k = 8 - j;
1118
1119 for (;j > 0; j--) {
1120 /* Pattern 0. Copy the cursor bitmap to it */
1121 fb_writeb(*bitmap, cursorbase + h);
1122 bitmap++;
1123 /* Pattern 1. Copy the cursor mask to it */
1124 fb_writeb(*mask, cursorbase + h + 8);
1125 mask++;
1126 h++;
1127 }
1128 for (;k > 0; k--) {
1129 fb_writeb(0, cursorbase + h);
1130 fb_writeb(~0, cursorbase + h + 8);
1131 h++;
1132 }
1133 } else {
1134 fb_writel(0, cursorbase + h);
1135 fb_writel(0, cursorbase + h + 4);
1136 fb_writel(~0, cursorbase + h + 8);
1137 fb_writel(~0, cursorbase + h + 12);
1138 h += 16;
1139 }
1140 }
1141 }
1142 /* Turn the cursor on */
1143 cursor->enable = 1;
1144 info->cursor = *cursor;
1145 mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
1146 spin_lock_irqsave(&par->DAClock, flags);
1147 banshee_make_room(par, 1);
1148 tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
1149 spin_unlock_irqrestore(&par->DAClock, flags);
1150 return 0;
1151 }
1152 #endif
1153
1154 /**
1155 * tdfxfb_probe - Device Initializiation
1156 *
1157 * @pdev: PCI Device to initialize
1158 * @id: PCI Device ID
1159 *
1160 * Initializes and allocates resources for PCI device @pdev.
1161 *
1162 */
1163 static int __devinit tdfxfb_probe(struct pci_dev *pdev,
1164 const struct pci_device_id *id)
1165 {
1166 struct tdfx_par *default_par;
1167 struct fb_info *info;
1168 int err, lpitch;
1169
1170 if ((err = pci_enable_device(pdev))) {
1171 printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
1172 return err;
1173 }
1174
1175 info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
1176
1177 if (!info)
1178 return -ENOMEM;
1179
1180 default_par = info->par;
1181
1182 /* Configure the default fb_fix_screeninfo first */
1183 switch (pdev->device) {
1184 case PCI_DEVICE_ID_3DFX_BANSHEE:
1185 strcat(tdfx_fix.id, " Banshee");
1186 default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
1187 break;
1188 case PCI_DEVICE_ID_3DFX_VOODOO3:
1189 strcat(tdfx_fix.id, " Voodoo3");
1190 default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
1191 break;
1192 case PCI_DEVICE_ID_3DFX_VOODOO5:
1193 strcat(tdfx_fix.id, " Voodoo5");
1194 default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
1195 break;
1196 }
1197
1198 tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
1199 tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
1200 default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
1201 if (!default_par->regbase_virt) {
1202 printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
1203 goto out_err;
1204 }
1205
1206 if (!request_mem_region(pci_resource_start(pdev, 0),
1207 pci_resource_len(pdev, 0), "tdfx regbase")) {
1208 printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
1209 goto out_err;
1210 }
1211
1212 tdfx_fix.smem_start = pci_resource_start(pdev, 1);
1213 if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
1214 printk("fb: Can't count %s memory.\n", tdfx_fix.id);
1215 release_mem_region(pci_resource_start(pdev, 0),
1216 pci_resource_len(pdev, 0));
1217 goto out_err;
1218 }
1219
1220 if (!request_mem_region(pci_resource_start(pdev, 1),
1221 pci_resource_len(pdev, 1), "tdfx smem")) {
1222 printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
1223 release_mem_region(pci_resource_start(pdev, 0),
1224 pci_resource_len(pdev, 0));
1225 goto out_err;
1226 }
1227
1228 info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
1229 tdfx_fix.smem_len);
1230 if (!info->screen_base) {
1231 printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
1232 release_mem_region(pci_resource_start(pdev, 1),
1233 pci_resource_len(pdev, 1));
1234 release_mem_region(pci_resource_start(pdev, 0),
1235 pci_resource_len(pdev, 0));
1236 goto out_err;
1237 }
1238
1239 default_par->iobase = pci_resource_start(pdev, 2);
1240
1241 if (!request_region(pci_resource_start(pdev, 2),
1242 pci_resource_len(pdev, 2), "tdfx iobase")) {
1243 printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
1244 release_mem_region(pci_resource_start(pdev, 1),
1245 pci_resource_len(pdev, 1));
1246 release_mem_region(pci_resource_start(pdev, 0),
1247 pci_resource_len(pdev, 0));
1248 goto out_err;
1249 }
1250
1251 printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
1252
1253 tdfx_fix.ypanstep = nopan ? 0 : 1;
1254 tdfx_fix.ywrapstep = nowrap ? 0 : 1;
1255
1256 info->fbops = &tdfxfb_ops;
1257 info->fix = tdfx_fix;
1258 info->pseudo_palette = default_par->palette;
1259 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1260 #ifdef CONFIG_FB_3DFX_ACCEL
1261 info->flags |= FBINFO_HWACCEL_FILLRECT |
1262 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_IMAGEBLIT;
1263 #endif
1264
1265 if (!mode_option)
1266 mode_option = "640x480@60";
1267
1268 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
1269 if (!err || err == 4)
1270 info->var = tdfx_var;
1271
1272 /* maximize virtual vertical length */
1273 lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
1274 info->var.yres_virtual = info->fix.smem_len/lpitch;
1275 if (info->var.yres_virtual < info->var.yres)
1276 goto out_err;
1277
1278 #ifdef CONFIG_FB_3DFX_ACCEL
1279 /*
1280 * FIXME: Limit var->yres_virtual to 4096 because of screen artifacts
1281 * during scrolling. This is only present if 2D acceleration is
1282 * enabled.
1283 */
1284 if (info->var.yres_virtual > 4096)
1285 info->var.yres_virtual = 4096;
1286 #endif /* CONFIG_FB_3DFX_ACCEL */
1287
1288 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
1289 printk(KERN_WARNING "tdfxfb: Can't allocate color map\n");
1290 goto out_err;
1291 }
1292
1293 if (register_framebuffer(info) < 0) {
1294 printk("tdfxfb: can't register framebuffer\n");
1295 fb_dealloc_cmap(&info->cmap);
1296 goto out_err;
1297 }
1298 /*
1299 * Our driver data
1300 */
1301 pci_set_drvdata(pdev, info);
1302 return 0;
1303
1304 out_err:
1305 /*
1306 * Cleanup after anything that was remapped/allocated.
1307 */
1308 if (default_par->regbase_virt)
1309 iounmap(default_par->regbase_virt);
1310 if (info->screen_base)
1311 iounmap(info->screen_base);
1312 framebuffer_release(info);
1313 return -ENXIO;
1314 }
1315
1316 #ifndef MODULE
1317 static void tdfxfb_setup(char *options)
1318 {
1319 char* this_opt;
1320
1321 if (!options || !*options)
1322 return;
1323
1324 while ((this_opt = strsep(&options, ",")) != NULL) {
1325 if (!*this_opt)
1326 continue;
1327 if(!strcmp(this_opt, "nopan")) {
1328 nopan = 1;
1329 } else if(!strcmp(this_opt, "nowrap")) {
1330 nowrap = 1;
1331 } else {
1332 mode_option = this_opt;
1333 }
1334 }
1335 }
1336 #endif
1337
1338 /**
1339 * tdfxfb_remove - Device removal
1340 *
1341 * @pdev: PCI Device to cleanup
1342 *
1343 * Releases all resources allocated during the course of the driver's
1344 * lifetime for the PCI device @pdev.
1345 *
1346 */
1347 static void __devexit tdfxfb_remove(struct pci_dev *pdev)
1348 {
1349 struct fb_info *info = pci_get_drvdata(pdev);
1350 struct tdfx_par *par = info->par;
1351
1352 unregister_framebuffer(info);
1353 iounmap(par->regbase_virt);
1354 iounmap(info->screen_base);
1355
1356 /* Clean up after reserved regions */
1357 release_region(pci_resource_start(pdev, 2),
1358 pci_resource_len(pdev, 2));
1359 release_mem_region(pci_resource_start(pdev, 1),
1360 pci_resource_len(pdev, 1));
1361 release_mem_region(pci_resource_start(pdev, 0),
1362 pci_resource_len(pdev, 0));
1363 pci_set_drvdata(pdev, NULL);
1364 framebuffer_release(info);
1365 }
1366
1367 static int __init tdfxfb_init(void)
1368 {
1369 #ifndef MODULE
1370 char *option = NULL;
1371
1372 if (fb_get_options("tdfxfb", &option))
1373 return -ENODEV;
1374
1375 tdfxfb_setup(option);
1376 #endif
1377 return pci_register_driver(&tdfxfb_driver);
1378 }
1379
1380 static void __exit tdfxfb_exit(void)
1381 {
1382 pci_unregister_driver(&tdfxfb_driver);
1383 }
1384
1385 MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
1386 MODULE_DESCRIPTION("3Dfx framebuffer device driver");
1387 MODULE_LICENSE("GPL");
1388
1389 module_init(tdfxfb_init);
1390 module_exit(tdfxfb_exit);
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