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[NETFILTER]: ip_tables: fix module refcount leaks in compat error paths
[hh.org.git] / drivers / video / tgafb.c
blob94fde625a6c070b61a96b786720e4c3be2ac060e
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/fb.h>
24 #include <linux/pci.h>
25 #include <linux/selection.h>
26 #include <asm/io.h>
27 #include <video/tgafb.h>
28
29 /*
30 * Local functions.
31 */
32
33 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
34 static int tgafb_set_par(struct fb_info *);
35 static void tgafb_set_pll(struct tga_par *, int);
36 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
37 unsigned, struct fb_info *);
38 static int tgafb_blank(int, struct fb_info *);
39 static void tgafb_init_fix(struct fb_info *);
40
41 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
42 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
43 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
44
45 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
46 static void tgafb_pci_unregister(struct pci_dev *);
47
48 static const char *mode_option = "640x480@60";
49
50
51 /*
52 * Frame buffer operations
53 */
54
55 static struct fb_ops tgafb_ops = {
56 .owner = THIS_MODULE,
57 .fb_check_var = tgafb_check_var,
58 .fb_set_par = tgafb_set_par,
59 .fb_setcolreg = tgafb_setcolreg,
60 .fb_blank = tgafb_blank,
61 .fb_fillrect = tgafb_fillrect,
62 .fb_copyarea = tgafb_copyarea,
63 .fb_imageblit = tgafb_imageblit,
64 };
65
66
67 /*
68 * PCI registration operations
69 */
70
71 static struct pci_device_id const tgafb_pci_table[] = {
72 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
73 0, 0, 0 }
74 };
75
76 static struct pci_driver tgafb_driver = {
77 .name = "tgafb",
78 .id_table = tgafb_pci_table,
79 .probe = tgafb_pci_register,
80 .remove = __devexit_p(tgafb_pci_unregister),
81 };
82
83
84 /**
85 * tgafb_check_var - Optional function. Validates a var passed in.
86 * @var: frame buffer variable screen structure
87 * @info: frame buffer structure that represents a single frame buffer
88 */
89 static int
90 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
91 {
92 struct tga_par *par = (struct tga_par *)info->par;
93
94 if (par->tga_type == TGA_TYPE_8PLANE) {
95 if (var->bits_per_pixel != 8)
96 return -EINVAL;
97 } else {
98 if (var->bits_per_pixel != 32)
99 return -EINVAL;
100 }
101
102 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
103 return -EINVAL;
104 if (var->nonstd)
105 return -EINVAL;
106 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
107 return -EINVAL;
108 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
109 return -EINVAL;
110
111 /* Some of the acceleration routines assume the line width is
112 a multiple of 64 bytes. */
113 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
114 return -EINVAL;
115
116 return 0;
117 }
118
119 /**
120 * tgafb_set_par - Optional function. Alters the hardware state.
121 * @info: frame buffer structure that represents a single frame buffer
122 */
123 static int
124 tgafb_set_par(struct fb_info *info)
125 {
126 static unsigned int const deep_presets[4] = {
127 0x00014000,
128 0x0001440d,
129 0xffffffff,
130 0x0001441d
131 };
132 static unsigned int const rasterop_presets[4] = {
133 0x00000003,
134 0x00000303,
135 0xffffffff,
136 0x00000303
137 };
138 static unsigned int const mode_presets[4] = {
139 0x00002000,
140 0x00002300,
141 0xffffffff,
142 0x00002300
143 };
144 static unsigned int const base_addr_presets[4] = {
145 0x00000000,
146 0x00000001,
147 0xffffffff,
148 0x00000001
149 };
150
151 struct tga_par *par = (struct tga_par *) info->par;
152 u32 htimings, vtimings, pll_freq;
153 u8 tga_type;
154 int i, j;
155
156 /* Encode video timings. */
157 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
158 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
159 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
160 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
161 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
162 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
163 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
164 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
165 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
166
167 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
168 htimings |= TGA_HORIZ_POLARITY;
169 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
170 vtimings |= TGA_VERT_POLARITY;
171
172 par->htimings = htimings;
173 par->vtimings = vtimings;
174
175 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
176
177 /* Store other useful values in par. */
178 par->xres = info->var.xres;
179 par->yres = info->var.yres;
180 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
181 par->bits_per_pixel = info->var.bits_per_pixel;
182
183 tga_type = par->tga_type;
184
185 /* First, disable video. */
186 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
187
188 /* Write the DEEP register. */
189 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
190 continue;
191 mb();
192 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
193 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
194 continue;
195 mb();
196
197 /* Write some more registers. */
198 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
199 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
200 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
201
202 /* Calculate & write the PLL. */
203 tgafb_set_pll(par, pll_freq);
204
205 /* Write some more registers. */
206 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
207 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
208
209 /* Init video timing regs. */
210 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
211 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
212
213 /* Initalise RAMDAC. */
214 if (tga_type == TGA_TYPE_8PLANE) {
215
216 /* Init BT485 RAMDAC registers. */
217 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
218 BT485_CMD_0);
219 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
220 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
221 BT485_WRITE(par, 0x40, BT485_CMD_1);
222 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
223 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
224
225 /* Fill palette registers. */
226 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
227 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
228
229 for (i = 0; i < 16; i++) {
230 j = color_table[i];
231 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
232 TGA_RAMDAC_REG);
233 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
234 TGA_RAMDAC_REG);
235 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
236 TGA_RAMDAC_REG);
237 }
238 for (i = 0; i < 240*3; i += 4) {
239 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
240 TGA_RAMDAC_REG);
241 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
242 TGA_RAMDAC_REG);
243 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
244 TGA_RAMDAC_REG);
245 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
246 TGA_RAMDAC_REG);
247 }
248
249 } else { /* 24-plane or 24plusZ */
250
251 /* Init BT463 registers. */
252 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
253 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
254 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
255 (par->sync_on_green ? 0x80 : 0x40));
256
257 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
258 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
259 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
260 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
261
262 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
264 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
266
267 /* Fill the palette. */
268 BT463_LOAD_ADDR(par, 0x0000);
269 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
270
271 for (i = 0; i < 16; i++) {
272 j = color_table[i];
273 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
274 TGA_RAMDAC_REG);
275 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
276 TGA_RAMDAC_REG);
277 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
278 TGA_RAMDAC_REG);
279 }
280 for (i = 0; i < 512*3; i += 4) {
281 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
282 TGA_RAMDAC_REG);
283 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
284 TGA_RAMDAC_REG);
285 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
286 TGA_RAMDAC_REG);
287 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
288 TGA_RAMDAC_REG);
289 }
290
291 /* Fill window type table after start of vertical retrace. */
292 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
293 continue;
294 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
295 mb();
296 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
297 continue;
298 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
299
300 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
301 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
302
303 for (i = 0; i < 16; i++) {
304 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
305 TGA_RAMDAC_REG);
306 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
307 TGA_RAMDAC_REG);
308 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
309 TGA_RAMDAC_REG);
310 }
311
312 }
313
314 /* Finally, enable video scan (and pray for the monitor... :-) */
315 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
316
317 return 0;
318 }
319
320 #define DIFFCHECK(X) \
321 do { \
322 if (m <= 0x3f) { \
323 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
324 if (delta < 0) \
325 delta = -delta; \
326 if (delta < min_diff) \
327 min_diff = delta, vm = m, va = a, vr = r; \
328 } \
329 } while (0)
330
331 static void
332 tgafb_set_pll(struct tga_par *par, int f)
333 {
334 int n, shift, base, min_diff, target;
335 int r,a,m,vm = 34, va = 1, vr = 30;
336
337 for (r = 0 ; r < 12 ; r++)
338 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
339
340 if (f > TGA_PLL_MAX_FREQ)
341 f = TGA_PLL_MAX_FREQ;
342
343 if (f >= TGA_PLL_MAX_FREQ / 2)
344 shift = 0;
345 else if (f >= TGA_PLL_MAX_FREQ / 4)
346 shift = 1;
347 else
348 shift = 2;
349
350 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
351 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
352
353 for (r = 0 ; r < 10 ; r++)
354 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
355
356 if (f <= 120000) {
357 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
358 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
359 }
360 else if (f <= 200000) {
361 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
362 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
363 }
364 else {
365 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
366 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
367 }
368
369 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
370 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
371 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
372 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
375
376 target = (f << shift) / TGA_PLL_BASE_FREQ;
377 min_diff = TGA_PLL_MAX_FREQ;
378
379 r = 7 / target;
380 if (!r) r = 1;
381
382 base = target * r;
383 while (base < 449) {
384 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
385 m = ((n + 3) / 7) - 1;
386 a = 0;
387 DIFFCHECK((m + 1) * 7);
388 m++;
389 DIFFCHECK((m + 1) * 7);
390 m = (n / 6) - 1;
391 if ((a = n % 6))
392 DIFFCHECK(n);
393 }
394 r++;
395 base += target;
396 }
397
398 vr--;
399
400 for (r = 0; r < 8; r++)
401 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
402 for (r = 0; r < 8 ; r++)
403 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
404 for (r = 0; r < 7 ; r++)
405 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
406 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
407 }
408
409
410 /**
411 * tgafb_setcolreg - Optional function. Sets a color register.
412 * @regno: boolean, 0 copy local, 1 get_user() function
413 * @red: frame buffer colormap structure
414 * @green: The green value which can be up to 16 bits wide
415 * @blue: The blue value which can be up to 16 bits wide.
416 * @transp: If supported the alpha value which can be up to 16 bits wide.
417 * @info: frame buffer info structure
418 */
419 static int
420 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
421 unsigned transp, struct fb_info *info)
422 {
423 struct tga_par *par = (struct tga_par *) info->par;
424
425 if (regno > 255)
426 return 1;
427 red >>= 8;
428 green >>= 8;
429 blue >>= 8;
430
431 if (par->tga_type == TGA_TYPE_8PLANE) {
432 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
433 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
434 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
435 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
436 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
437 } else if (regno < 16) {
438 u32 value = (red << 16) | (green << 8) | blue;
439 ((u32 *)info->pseudo_palette)[regno] = value;
440 }
441
442 return 0;
443 }
444
445
446 /**
447 * tgafb_blank - Optional function. Blanks the display.
448 * @blank_mode: the blank mode we want.
449 * @info: frame buffer structure that represents a single frame buffer
450 */
451 static int
452 tgafb_blank(int blank, struct fb_info *info)
453 {
454 struct tga_par *par = (struct tga_par *) info->par;
455 u32 vhcr, vvcr, vvvr;
456 unsigned long flags;
457
458 local_irq_save(flags);
459
460 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
461 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
462 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
463 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
464
465 switch (blank) {
466 case FB_BLANK_UNBLANK: /* Unblanking */
467 if (par->vesa_blanked) {
468 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
469 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
470 par->vesa_blanked = 0;
471 }
472 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
473 break;
474
475 case FB_BLANK_NORMAL: /* Normal blanking */
476 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
477 TGA_VALID_REG);
478 break;
479
480 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
481 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
482 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
483 par->vesa_blanked = 1;
484 break;
485
486 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
487 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
488 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
489 par->vesa_blanked = 1;
490 break;
491
492 case FB_BLANK_POWERDOWN: /* Poweroff */
493 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
494 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
495 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
496 par->vesa_blanked = 1;
497 break;
498 }
499
500 local_irq_restore(flags);
501 return 0;
502 }
503
504
505 /*
506 * Acceleration.
507 */
508
509 /**
510 * tgafb_imageblit - REQUIRED function. Can use generic routines if
511 * non acclerated hardware and packed pixel based.
512 * Copies a image from system memory to the screen.
513 *
514 * @info: frame buffer structure that represents a single frame buffer
515 * @image: structure defining the image.
516 */
517 static void
518 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
519 {
520 static unsigned char const bitrev[256] = {
521 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
522 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
523 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
524 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
525 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
526 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
527 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
528 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
529 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
530 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
531 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
532 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
533 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
534 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
535 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
536 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
537 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
538 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
539 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
540 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
541 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
542 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
543 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
544 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
545 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
546 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
547 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
548 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
549 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
550 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
551 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
552 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
553 };
554
555 struct tga_par *par = (struct tga_par *) info->par;
556 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
557 unsigned long rincr, line_length, shift, pos, is8bpp;
558 unsigned long i, j;
559 const unsigned char *data;
560 void __iomem *regs_base;
561 void __iomem *fb_base;
562
563 dx = image->dx;
564 dy = image->dy;
565 width = image->width;
566 height = image->height;
567 vxres = info->var.xres_virtual;
568 vyres = info->var.yres_virtual;
569 line_length = info->fix.line_length;
570 rincr = (width + 7) / 8;
571
572 /* Crop the image to the screen. */
573 if (dx > vxres || dy > vyres)
574 return;
575 if (dx + width > vxres)
576 width = vxres - dx;
577 if (dy + height > vyres)
578 height = vyres - dy;
579
580 /* For copies that aren't pixel expansion, there's little we
581 can do better than the generic code. */
582 /* ??? There is a DMA write mode; I wonder if that could be
583 made to pull the data from the image buffer... */
584 if (image->depth > 1) {
585 cfb_imageblit(info, image);
586 return;
587 }
588
589 regs_base = par->tga_regs_base;
590 fb_base = par->tga_fb_base;
591 is8bpp = info->var.bits_per_pixel == 8;
592
593 /* Expand the color values to fill 32-bits. */
594 /* ??? Would be nice to notice colour changes elsewhere, so
595 that we can do this only when necessary. */
596 fgcolor = image->fg_color;
597 bgcolor = image->bg_color;
598 if (is8bpp) {
599 fgcolor |= fgcolor << 8;
600 fgcolor |= fgcolor << 16;
601 bgcolor |= bgcolor << 8;
602 bgcolor |= bgcolor << 16;
603 } else {
604 if (fgcolor < 16)
605 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
606 if (bgcolor < 16)
607 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
608 }
609 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
610 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
611
612 /* Acquire proper alignment; set up the PIXELMASK register
613 so that we only write the proper character cell. */
614 pos = dy * line_length;
615 if (is8bpp) {
616 pos += dx;
617 shift = pos & 3;
618 pos &= -4;
619 } else {
620 pos += dx * 4;
621 shift = (pos & 7) >> 2;
622 pos &= -8;
623 }
624
625 data = (const unsigned char *) image->data;
626
627 /* Enable opaque stipple mode. */
628 __raw_writel((is8bpp
629 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
630 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
631 regs_base + TGA_MODE_REG);
632
633 if (width + shift <= 32) {
634 unsigned long bwidth;
635
636 /* Handle common case of imaging a single character, in
637 a font less than 32 pixels wide. */
638
639 pixelmask = (1 << width) - 1;
640 pixelmask <<= shift;
641 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
642 wmb();
643
644 bwidth = (width + 7) / 8;
645
646 for (i = 0; i < height; ++i) {
647 u32 mask = 0;
648
649 /* The image data is bit big endian; we need
650 little endian. */
651 for (j = 0; j < bwidth; ++j)
652 mask |= bitrev[data[j]] << (j * 8);
653
654 __raw_writel(mask << shift, fb_base + pos);
655
656 pos += line_length;
657 data += rincr;
658 }
659 wmb();
660 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
661 } else if (shift == 0) {
662 unsigned long pos0 = pos;
663 const unsigned char *data0 = data;
664 unsigned long bincr = (is8bpp ? 8 : 8*4);
665 unsigned long bwidth;
666
667 /* Handle another common case in which accel_putcs
668 generates a large bitmap, which happens to be aligned.
669 Allow the tail to be misaligned. This case is
670 interesting because we've not got to hold partial
671 bytes across the words being written. */
672
673 wmb();
674
675 bwidth = (width / 8) & -4;
676 for (i = 0; i < height; ++i) {
677 for (j = 0; j < bwidth; j += 4) {
678 u32 mask = 0;
679 mask |= bitrev[data[j+0]] << (0 * 8);
680 mask |= bitrev[data[j+1]] << (1 * 8);
681 mask |= bitrev[data[j+2]] << (2 * 8);
682 mask |= bitrev[data[j+3]] << (3 * 8);
683 __raw_writel(mask, fb_base + pos + j*bincr);
684 }
685 pos += line_length;
686 data += rincr;
687 }
688 wmb();
689
690 pixelmask = (1ul << (width & 31)) - 1;
691 if (pixelmask) {
692 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
693 wmb();
694
695 pos = pos0 + bwidth*bincr;
696 data = data0 + bwidth;
697 bwidth = ((width & 31) + 7) / 8;
698
699 for (i = 0; i < height; ++i) {
700 u32 mask = 0;
701 for (j = 0; j < bwidth; ++j)
702 mask |= bitrev[data[j]] << (j * 8);
703 __raw_writel(mask, fb_base + pos);
704 pos += line_length;
705 data += rincr;
706 }
707 wmb();
708 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
709 }
710 } else {
711 unsigned long pos0 = pos;
712 const unsigned char *data0 = data;
713 unsigned long bincr = (is8bpp ? 8 : 8*4);
714 unsigned long bwidth;
715
716 /* Finally, handle the generic case of misaligned start.
717 Here we split the write into 16-bit spans. This allows
718 us to use only one pixel mask, instead of four as would
719 be required by writing 24-bit spans. */
720
721 pixelmask = 0xffff << shift;
722 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
723 wmb();
724
725 bwidth = (width / 8) & -2;
726 for (i = 0; i < height; ++i) {
727 for (j = 0; j < bwidth; j += 2) {
728 u32 mask = 0;
729 mask |= bitrev[data[j+0]] << (0 * 8);
730 mask |= bitrev[data[j+1]] << (1 * 8);
731 mask <<= shift;
732 __raw_writel(mask, fb_base + pos + j*bincr);
733 }
734 pos += line_length;
735 data += rincr;
736 }
737 wmb();
738
739 pixelmask = ((1ul << (width & 15)) - 1) << shift;
740 if (pixelmask) {
741 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
742 wmb();
743
744 pos = pos0 + bwidth*bincr;
745 data = data0 + bwidth;
746 bwidth = (width & 15) > 8;
747
748 for (i = 0; i < height; ++i) {
749 u32 mask = bitrev[data[0]];
750 if (bwidth)
751 mask |= bitrev[data[1]] << 8;
752 mask <<= shift;
753 __raw_writel(mask, fb_base + pos);
754 pos += line_length;
755 data += rincr;
756 }
757 wmb();
758 }
759 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
760 }
761
762 /* Disable opaque stipple mode. */
763 __raw_writel((is8bpp
764 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
765 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
766 regs_base + TGA_MODE_REG);
767 }
768
769 /**
770 * tgafb_fillrect - REQUIRED function. Can use generic routines if
771 * non acclerated hardware and packed pixel based.
772 * Draws a rectangle on the screen.
773 *
774 * @info: frame buffer structure that represents a single frame buffer
775 * @rect: structure defining the rectagle and operation.
776 */
777 static void
778 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
779 {
780 struct tga_par *par = (struct tga_par *) info->par;
781 int is8bpp = info->var.bits_per_pixel == 8;
782 u32 dx, dy, width, height, vxres, vyres, color;
783 unsigned long pos, align, line_length, i, j;
784 void __iomem *regs_base;
785 void __iomem *fb_base;
786
787 dx = rect->dx;
788 dy = rect->dy;
789 width = rect->width;
790 height = rect->height;
791 vxres = info->var.xres_virtual;
792 vyres = info->var.yres_virtual;
793 line_length = info->fix.line_length;
794 regs_base = par->tga_regs_base;
795 fb_base = par->tga_fb_base;
796
797 /* Crop the rectangle to the screen. */
798 if (dx > vxres || dy > vyres || !width || !height)
799 return;
800 if (dx + width > vxres)
801 width = vxres - dx;
802 if (dy + height > vyres)
803 height = vyres - dy;
804
805 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
806
807 /* ??? We could implement ROP_XOR with opaque fill mode
808 and a RasterOp setting of GXxor, but as far as I can
809 tell, this mode is not actually used in the kernel.
810 Thus I am ignoring it for now. */
811 if (rect->rop != ROP_COPY) {
812 cfb_fillrect(info, rect);
813 return;
814 }
815
816 /* Expand the color value to fill 8 pixels. */
817 color = rect->color;
818 if (is8bpp) {
819 color |= color << 8;
820 color |= color << 16;
821 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
822 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
823 } else {
824 if (color < 16)
825 color = ((u32 *)info->pseudo_palette)[color];
826 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
827 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
828 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
829 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
830 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
834 }
835
836 /* The DATA register holds the fill mask for block fill mode.
837 Since we're not stippling, this is all ones. */
838 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
839
840 /* Enable block fill mode. */
841 __raw_writel((is8bpp
842 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
843 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
844 regs_base + TGA_MODE_REG);
845 wmb();
846
847 /* We can fill 2k pixels per operation. Notice blocks that fit
848 the width of the screen so that we can take advantage of this
849 and fill more than one line per write. */
850 if (width == line_length)
851 width *= height, height = 1;
852
853 /* The write into the frame buffer must be aligned to 4 bytes,
854 but we are allowed to encode the offset within the word in
855 the data word written. */
856 align = (pos & 3) << 16;
857 pos &= -4;
858
859 if (width <= 2048) {
860 u32 data;
861
862 data = (width - 1) | align;
863
864 for (i = 0; i < height; ++i) {
865 __raw_writel(data, fb_base + pos);
866 pos += line_length;
867 }
868 } else {
869 unsigned long Bpp = (is8bpp ? 1 : 4);
870 unsigned long nwidth = width & -2048;
871 u32 fdata, ldata;
872
873 fdata = (2048 - 1) | align;
874 ldata = ((width & 2047) - 1) | align;
875
876 for (i = 0; i < height; ++i) {
877 for (j = 0; j < nwidth; j += 2048)
878 __raw_writel(fdata, fb_base + pos + j*Bpp);
879 if (j < width)
880 __raw_writel(ldata, fb_base + pos + j*Bpp);
881 pos += line_length;
882 }
883 }
884 wmb();
885
886 /* Disable block fill mode. */
887 __raw_writel((is8bpp
888 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
889 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
890 regs_base + TGA_MODE_REG);
891 }
892
893 /**
894 * tgafb_copyarea - REQUIRED function. Can use generic routines if
895 * non acclerated hardware and packed pixel based.
896 * Copies on area of the screen to another area.
897 *
898 * @info: frame buffer structure that represents a single frame buffer
899 * @area: structure defining the source and destination.
900 */
901
902 /* Handle the special case of copying entire lines, e.g. during scrolling.
903 We can avoid a lot of needless computation in this case. In the 8bpp
904 case we need to use the COPY64 registers instead of mask writes into
905 the frame buffer to achieve maximum performance. */
906
907 static inline void
908 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
909 u32 height, u32 width)
910 {
911 struct tga_par *par = (struct tga_par *) info->par;
912 void __iomem *tga_regs = par->tga_regs_base;
913 unsigned long dpos, spos, i, n64;
914
915 /* Set up the MODE and PIXELSHIFT registers. */
916 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
917 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
918 wmb();
919
920 n64 = (height * width) / 64;
921
922 if (dy < sy) {
923 spos = (sy + height) * width;
924 dpos = (dy + height) * width;
925
926 for (i = 0; i < n64; ++i) {
927 spos -= 64;
928 dpos -= 64;
929 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
930 wmb();
931 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
932 wmb();
933 }
934 } else {
935 spos = sy * width;
936 dpos = dy * width;
937
938 for (i = 0; i < n64; ++i) {
939 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
940 wmb();
941 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
942 wmb();
943 spos += 64;
944 dpos += 64;
945 }
946 }
947
948 /* Reset the MODE register to normal. */
949 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
950 }
951
952 static inline void
953 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
954 u32 height, u32 width)
955 {
956 struct tga_par *par = (struct tga_par *) info->par;
957 void __iomem *tga_regs = par->tga_regs_base;
958 void __iomem *tga_fb = par->tga_fb_base;
959 void __iomem *src;
960 void __iomem *dst;
961 unsigned long i, n16;
962
963 /* Set up the MODE and PIXELSHIFT registers. */
964 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
965 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
966 wmb();
967
968 n16 = (height * width) / 16;
969
970 if (dy < sy) {
971 src = tga_fb + (sy + height) * width * 4;
972 dst = tga_fb + (dy + height) * width * 4;
973
974 for (i = 0; i < n16; ++i) {
975 src -= 64;
976 dst -= 64;
977 __raw_writel(0xffff, src);
978 wmb();
979 __raw_writel(0xffff, dst);
980 wmb();
981 }
982 } else {
983 src = tga_fb + sy * width * 4;
984 dst = tga_fb + dy * width * 4;
985
986 for (i = 0; i < n16; ++i) {
987 __raw_writel(0xffff, src);
988 wmb();
989 __raw_writel(0xffff, dst);
990 wmb();
991 src += 64;
992 dst += 64;
993 }
994 }
995
996 /* Reset the MODE register to normal. */
997 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
998 }
999
1000 /* The general case of forward copy in 8bpp mode. */
1001 static inline void
1002 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1003 u32 height, u32 width, u32 line_length)
1004 {
1005 struct tga_par *par = (struct tga_par *) info->par;
1006 unsigned long i, copied, left;
1007 unsigned long dpos, spos, dalign, salign, yincr;
1008 u32 smask_first, dmask_first, dmask_last;
1009 int pixel_shift, need_prime, need_second;
1010 unsigned long n64, n32, xincr_first;
1011 void __iomem *tga_regs;
1012 void __iomem *tga_fb;
1013
1014 yincr = line_length;
1015 if (dy > sy) {
1016 dy += height - 1;
1017 sy += height - 1;
1018 yincr = -yincr;
1019 }
1020
1021 /* Compute the offsets and alignments in the frame buffer.
1022 More than anything else, these control how we do copies. */
1023 dpos = dy * line_length + dx;
1024 spos = sy * line_length + sx;
1025 dalign = dpos & 7;
1026 salign = spos & 7;
1027 dpos &= -8;
1028 spos &= -8;
1029
1030 /* Compute the value for the PIXELSHIFT register. This controls
1031 both non-co-aligned source and destination and copy direction. */
1032 if (dalign >= salign)
1033 pixel_shift = dalign - salign;
1034 else
1035 pixel_shift = 8 - (salign - dalign);
1036
1037 /* Figure out if we need an additional priming step for the
1038 residue register. */
1039 need_prime = (salign > dalign);
1040 if (need_prime)
1041 dpos -= 8;
1042
1043 /* Begin by copying the leading unaligned destination. Copy enough
1044 to make the next destination address 32-byte aligned. */
1045 copied = 32 - (dalign + (dpos & 31));
1046 if (copied == 32)
1047 copied = 0;
1048 xincr_first = (copied + 7) & -8;
1049 smask_first = dmask_first = (1ul << copied) - 1;
1050 smask_first <<= salign;
1051 dmask_first <<= dalign + need_prime*8;
1052 if (need_prime && copied > 24)
1053 copied -= 8;
1054 left = width - copied;
1055
1056 /* Care for small copies. */
1057 if (copied > width) {
1058 u32 t;
1059 t = (1ul << width) - 1;
1060 t <<= dalign + need_prime*8;
1061 dmask_first &= t;
1062 left = 0;
1063 }
1064
1065 /* Attempt to use 64-byte copies. This is only possible if the
1066 source and destination are co-aligned at 64 bytes. */
1067 n64 = need_second = 0;
1068 if ((dpos & 63) == (spos & 63)
1069 && (height == 1 || line_length % 64 == 0)) {
1070 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1071 need_second = (dpos + xincr_first) & 63;
1072 if ((need_second & 32) != need_second)
1073 printk(KERN_ERR "tgafb: need_second wrong\n");
1074 if (left >= need_second + 64) {
1075 left -= need_second;
1076 n64 = left / 64;
1077 left %= 64;
1078 } else
1079 need_second = 0;
1080 }
1081
1082 /* Copy trailing full 32-byte sections. This will be the main
1083 loop if the 64 byte loop can't be used. */
1084 n32 = left / 32;
1085 left %= 32;
1086
1087 /* Copy the trailing unaligned destination. */
1088 dmask_last = (1ul << left) - 1;
1089
1090 tga_regs = par->tga_regs_base;
1091 tga_fb = par->tga_fb_base;
1092
1093 /* Set up the MODE and PIXELSHIFT registers. */
1094 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1095 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1096 wmb();
1097
1098 for (i = 0; i < height; ++i) {
1099 unsigned long j;
1100 void __iomem *sfb;
1101 void __iomem *dfb;
1102
1103 sfb = tga_fb + spos;
1104 dfb = tga_fb + dpos;
1105 if (dmask_first) {
1106 __raw_writel(smask_first, sfb);
1107 wmb();
1108 __raw_writel(dmask_first, dfb);
1109 wmb();
1110 sfb += xincr_first;
1111 dfb += xincr_first;
1112 }
1113
1114 if (need_second) {
1115 __raw_writel(0xffffffff, sfb);
1116 wmb();
1117 __raw_writel(0xffffffff, dfb);
1118 wmb();
1119 sfb += 32;
1120 dfb += 32;
1121 }
1122
1123 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1124 printk(KERN_ERR
1125 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1126 sfb, dfb);
1127
1128 for (j = 0; j < n64; ++j) {
1129 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1130 wmb();
1131 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1132 wmb();
1133 sfb += 64;
1134 dfb += 64;
1135 }
1136
1137 for (j = 0; j < n32; ++j) {
1138 __raw_writel(0xffffffff, sfb);
1139 wmb();
1140 __raw_writel(0xffffffff, dfb);
1141 wmb();
1142 sfb += 32;
1143 dfb += 32;
1144 }
1145
1146 if (dmask_last) {
1147 __raw_writel(0xffffffff, sfb);
1148 wmb();
1149 __raw_writel(dmask_last, dfb);
1150 wmb();
1151 }
1152
1153 spos += yincr;
1154 dpos += yincr;
1155 }
1156
1157 /* Reset the MODE register to normal. */
1158 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1159 }
1160
1161 /* The (almost) general case of backward copy in 8bpp mode. */
1162 static inline void
1163 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1164 u32 height, u32 width, u32 line_length,
1165 const struct fb_copyarea *area)
1166 {
1167 struct tga_par *par = (struct tga_par *) info->par;
1168 unsigned long i, left, yincr;
1169 unsigned long depos, sepos, dealign, sealign;
1170 u32 mask_first, mask_last;
1171 unsigned long n32;
1172 void __iomem *tga_regs;
1173 void __iomem *tga_fb;
1174
1175 yincr = line_length;
1176 if (dy > sy) {
1177 dy += height - 1;
1178 sy += height - 1;
1179 yincr = -yincr;
1180 }
1181
1182 /* Compute the offsets and alignments in the frame buffer.
1183 More than anything else, these control how we do copies. */
1184 depos = dy * line_length + dx + width;
1185 sepos = sy * line_length + sx + width;
1186 dealign = depos & 7;
1187 sealign = sepos & 7;
1188
1189 /* ??? The documentation appears to be incorrect (or very
1190 misleading) wrt how pixel shifting works in backward copy
1191 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1192 Do handle the common case of co-aligned backward copies,
1193 but frob everything else back on generic code. */
1194 if (dealign != sealign) {
1195 cfb_copyarea(info, area);
1196 return;
1197 }
1198
1199 /* We begin the copy with the trailing pixels of the
1200 unaligned destination. */
1201 mask_first = (1ul << dealign) - 1;
1202 left = width - dealign;
1203
1204 /* Care for small copies. */
1205 if (dealign > width) {
1206 mask_first ^= (1ul << (dealign - width)) - 1;
1207 left = 0;
1208 }
1209
1210 /* Next copy full words at a time. */
1211 n32 = left / 32;
1212 left %= 32;
1213
1214 /* Finally copy the unaligned head of the span. */
1215 mask_last = -1 << (32 - left);
1216
1217 tga_regs = par->tga_regs_base;
1218 tga_fb = par->tga_fb_base;
1219
1220 /* Set up the MODE and PIXELSHIFT registers. */
1221 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1222 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1223 wmb();
1224
1225 for (i = 0; i < height; ++i) {
1226 unsigned long j;
1227 void __iomem *sfb;
1228 void __iomem *dfb;
1229
1230 sfb = tga_fb + sepos;
1231 dfb = tga_fb + depos;
1232 if (mask_first) {
1233 __raw_writel(mask_first, sfb);
1234 wmb();
1235 __raw_writel(mask_first, dfb);
1236 wmb();
1237 }
1238
1239 for (j = 0; j < n32; ++j) {
1240 sfb -= 32;
1241 dfb -= 32;
1242 __raw_writel(0xffffffff, sfb);
1243 wmb();
1244 __raw_writel(0xffffffff, dfb);
1245 wmb();
1246 }
1247
1248 if (mask_last) {
1249 sfb -= 32;
1250 dfb -= 32;
1251 __raw_writel(mask_last, sfb);
1252 wmb();
1253 __raw_writel(mask_last, dfb);
1254 wmb();
1255 }
1256
1257 sepos += yincr;
1258 depos += yincr;
1259 }
1260
1261 /* Reset the MODE register to normal. */
1262 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1263 }
1264
1265 static void
1266 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1267 {
1268 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1269 unsigned long line_length, bpp;
1270
1271 dx = area->dx;
1272 dy = area->dy;
1273 width = area->width;
1274 height = area->height;
1275 sx = area->sx;
1276 sy = area->sy;
1277 vxres = info->var.xres_virtual;
1278 vyres = info->var.yres_virtual;
1279 line_length = info->fix.line_length;
1280
1281 /* The top left corners must be in the virtual screen. */
1282 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1283 return;
1284
1285 /* Clip the destination. */
1286 if (dx + width > vxres)
1287 width = vxres - dx;
1288 if (dy + height > vyres)
1289 height = vyres - dy;
1290
1291 /* The source must be completely inside the virtual screen. */
1292 if (sx + width > vxres || sy + height > vyres)
1293 return;
1294
1295 bpp = info->var.bits_per_pixel;
1296
1297 /* Detect copies of the entire line. */
1298 if (width * (bpp >> 3) == line_length) {
1299 if (bpp == 8)
1300 copyarea_line_8bpp(info, dy, sy, height, width);
1301 else
1302 copyarea_line_32bpp(info, dy, sy, height, width);
1303 }
1304
1305 /* ??? The documentation is unclear to me exactly how the pixelshift
1306 register works in 32bpp mode. Since I don't have hardware to test,
1307 give up for now and fall back on the generic routines. */
1308 else if (bpp == 32)
1309 cfb_copyarea(info, area);
1310
1311 /* Detect overlapping source and destination that requires
1312 a backward copy. */
1313 else if (dy == sy && dx > sx && dx < sx + width)
1314 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1315 width, line_length, area);
1316 else
1317 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1318 width, line_length);
1319 }
1320
1321
1322 /*
1323 * Initialisation
1324 */
1325
1326 static void
1327 tgafb_init_fix(struct fb_info *info)
1328 {
1329 struct tga_par *par = (struct tga_par *)info->par;
1330 u8 tga_type = par->tga_type;
1331 const char *tga_type_name;
1332
1333 switch (tga_type) {
1334 case TGA_TYPE_8PLANE:
1335 tga_type_name = "Digital ZLXp-E1";
1336 break;
1337 case TGA_TYPE_24PLANE:
1338 tga_type_name = "Digital ZLXp-E2";
1339 break;
1340 case TGA_TYPE_24PLUSZ:
1341 tga_type_name = "Digital ZLXp-E3";
1342 break;
1343 default:
1344 tga_type_name = "Unknown";
1345 break;
1346 }
1347
1348 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1349
1350 info->fix.type = FB_TYPE_PACKED_PIXELS;
1351 info->fix.type_aux = 0;
1352 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1353 ? FB_VISUAL_PSEUDOCOLOR
1354 : FB_VISUAL_TRUECOLOR);
1355
1356 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1357 info->fix.smem_start = (size_t) par->tga_fb_base;
1358 info->fix.smem_len = info->fix.line_length * par->yres;
1359 info->fix.mmio_start = (size_t) par->tga_regs_base;
1360 info->fix.mmio_len = 512;
1361
1362 info->fix.xpanstep = 0;
1363 info->fix.ypanstep = 0;
1364 info->fix.ywrapstep = 0;
1365
1366 info->fix.accel = FB_ACCEL_DEC_TGA;
1367 }
1368
1369 static __devinit int
1370 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1371 {
1372 static unsigned int const fb_offset_presets[4] = {
1373 TGA_8PLANE_FB_OFFSET,
1374 TGA_24PLANE_FB_OFFSET,
1375 0xffffffff,
1376 TGA_24PLUSZ_FB_OFFSET
1377 };
1378
1379 struct all_info {
1380 struct fb_info info;
1381 struct tga_par par;
1382 u32 pseudo_palette[16];
1383 } *all;
1384
1385 void __iomem *mem_base;
1386 unsigned long bar0_start, bar0_len;
1387 u8 tga_type;
1388 int ret;
1389
1390 /* Enable device in PCI config. */
1391 if (pci_enable_device(pdev)) {
1392 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1393 return -ENODEV;
1394 }
1395
1396 /* Allocate the fb and par structures. */
1397 all = kmalloc(sizeof(*all), GFP_KERNEL);
1398 if (!all) {
1399 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1400 return -ENOMEM;
1401 }
1402 memset(all, 0, sizeof(*all));
1403 pci_set_drvdata(pdev, all);
1404
1405 /* Request the mem regions. */
1406 bar0_start = pci_resource_start(pdev, 0);
1407 bar0_len = pci_resource_len(pdev, 0);
1408 ret = -ENODEV;
1409 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1410 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1411 goto err0;
1412 }
1413
1414 /* Map the framebuffer. */
1415 mem_base = ioremap(bar0_start, bar0_len);
1416 if (!mem_base) {
1417 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1418 goto err1;
1419 }
1420
1421 /* Grab info about the card. */
1422 tga_type = (readl(mem_base) >> 12) & 0x0f;
1423 all->par.pdev = pdev;
1424 all->par.tga_mem_base = mem_base;
1425 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1426 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1427 all->par.tga_type = tga_type;
1428 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1429
1430 /* Setup framebuffer. */
1431 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1432 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1433 all->info.fbops = &tgafb_ops;
1434 all->info.screen_base = all->par.tga_fb_base;
1435 all->info.par = &all->par;
1436 all->info.pseudo_palette = all->pseudo_palette;
1437
1438 /* This should give a reasonable default video mode. */
1439
1440 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1441 NULL, 0, NULL,
1442 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1443 if (ret == 0 || ret == 4) {
1444 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1445 ret = -EINVAL;
1446 goto err1;
1447 }
1448
1449 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1450 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1451 ret = -ENOMEM;
1452 goto err1;
1453 }
1454
1455 tgafb_set_par(&all->info);
1456 tgafb_init_fix(&all->info);
1457
1458 all->info.device = &pdev->dev;
1459 if (register_framebuffer(&all->info) < 0) {
1460 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1461 ret = -EINVAL;
1462 goto err1;
1463 }
1464
1465 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1466 all->par.tga_chip_rev);
1467 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1468 pdev->bus->number, PCI_SLOT(pdev->devfn),
1469 PCI_FUNC(pdev->devfn));
1470 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1471 all->info.node, all->info.fix.id, bar0_start);
1472
1473 return 0;
1474
1475 err1:
1476 release_mem_region(bar0_start, bar0_len);
1477 err0:
1478 kfree(all);
1479 return ret;
1480 }
1481
1482 static void __exit
1483 tgafb_pci_unregister(struct pci_dev *pdev)
1484 {
1485 struct fb_info *info = pci_get_drvdata(pdev);
1486 struct tga_par *par = info->par;
1487
1488 if (!info)
1489 return;
1490 unregister_framebuffer(info);
1491 iounmap(par->tga_mem_base);
1492 release_mem_region(pci_resource_start(pdev, 0),
1493 pci_resource_len(pdev, 0));
1494 kfree(info);
1495 }
1496
1497 #ifdef MODULE
1498 static void __exit
1499 tgafb_exit(void)
1500 {
1501 pci_unregister_driver(&tgafb_driver);
1502 }
1503 #endif /* MODULE */
1504
1505 #ifndef MODULE
1506 int __init
1507 tgafb_setup(char *arg)
1508 {
1509 char *this_opt;
1510
1511 if (arg && *arg) {
1512 while ((this_opt = strsep(&arg, ","))) {
1513 if (!*this_opt)
1514 continue;
1515 if (!strncmp(this_opt, "mode:", 5))
1516 mode_option = this_opt+5;
1517 else
1518 printk(KERN_ERR
1519 "tgafb: unknown parameter %s\n",
1520 this_opt);
1521 }
1522 }
1523
1524 return 0;
1525 }
1526 #endif /* !MODULE */
1527
1528 int __init
1529 tgafb_init(void)
1530 {
1531 #ifndef MODULE
1532 char *option = NULL;
1533
1534 if (fb_get_options("tgafb", &option))
1535 return -ENODEV;
1536 tgafb_setup(option);
1537 #endif
1538 return pci_register_driver(&tgafb_driver);
1539 }
1540
1541 /*
1542 * Modularisation
1543 */
1544
1545 module_init(tgafb_init);
1546
1547 #ifdef MODULE
1548 module_exit(tgafb_exit);
1549 #endif
1550
1551 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1552 MODULE_LICENSE("GPL");
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