arch/ppc/syslib/m8xx_setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   6  *  Further modified for generic 8xx by Dan.
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/sched.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/stddef.h>
  18 #include <linux/unistd.h>
  19 #include <linux/ptrace.h>
  20 #include <linux/slab.h>
  21 #include <linux/user.h>
  22 #include <linux/a.out.h>
  23 #include <linux/tty.h>
  24 #include <linux/major.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/reboot.h>
  27 #include <linux/init.h>
  28 #include <linux/initrd.h>
  29 #include <linux/ioport.h>
  30 #include <linux/bootmem.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/root_dev.h>
  33
  34 #if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/mtd/physmap.h>
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/map.h>
  39 #endif
  40
  41 #include <asm/mmu.h>
  42 #include <asm/reg.h>
  43 #include <asm/residual.h>
  44 #include <asm/io.h>
  45 #include <asm/pgtable.h>
  46 #include <asm/mpc8xx.h>
  47 #include <asm/8xx_immap.h>
  48 #include <asm/machdep.h>
  49 #include <asm/bootinfo.h>
  50 #include <asm/time.h>
  51 #include <asm/xmon.h>
  52 #include <asm/ppc_sys.h>
  53
  54 #include "ppc8xx_pic.h"
  55
  56 #ifdef CONFIG_MTD_PHYSMAP
  57 #define MPC8xxADS_BANK_WIDTH 4
  58 #endif
  59
  60 #define MPC8xxADS_U_BOOT_SIZE          0x80000
  61 #define MPC8xxADS_FREE_AREA_OFFSET     MPC8xxADS_U_BOOT_SIZE
  62
  63 #if defined(CONFIG_MTD_PARTITIONS)
  64  /*
  65    NOTE: bank width and interleave relative to the installed flash
  66    should have been chosen within MTD_CFI_GEOMETRY options.
  67  */
  68 static struct mtd_partition mpc8xxads_partitions[] = {
  69         {
  70                 .name = "bootloader",
  71                 .size = MPC8xxADS_U_BOOT_SIZE,
  72                 .offset = 0,
  73                 .mask_flags   = MTD_WRITEABLE,  /* force read-only */
  74         }, {
  75                 .name = "User FS",
  76                 .offset = MPC8xxADS_FREE_AREA_OFFSET
  77         }
  78 };
  79
  80 #define mpc8xxads_part_num (sizeof (mpc8xxads_partitions) / sizeof (mpc8xxads_partitions[0]))
  81
  82 #endif
  83
  84 static int m8xx_set_rtc_time(unsigned long time);
  85 static unsigned long m8xx_get_rtc_time(void);
  86 void m8xx_calibrate_decr(void);
  87
  88 unsigned char __res[sizeof(bd_t)];
  89
  90 extern void m8xx_ide_init(void);
  91
  92 extern unsigned long find_available_memory(void);
  93 extern void m8xx_cpm_reset(void);
  94 extern void m8xx_wdt_handler_install(bd_t *bp);
  95 extern void rpxfb_alloc_pages(void);
  96 extern void cpm_interrupt_init(void);
  97
  98 void __attribute__ ((weak))
  99 board_init(void)
 100 {
 101 }
 102
 103 void __init
 104 m8xx_setup_arch(void)
 105 {
 106 #if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
 107         bd_t *binfo = (bd_t *)__res;
 108 #endif
 109
 110         /* Reset the Communication Processor Module.
 111         */
 112         m8xx_cpm_reset();
 113
 114 #ifdef CONFIG_FB_RPX
 115         rpxfb_alloc_pages();
 116 #endif
 117
 118 #ifdef notdef
 119         ROOT_DEV = Root_HDA1; /* hda1 */
 120 #endif
 121
 122 #ifdef CONFIG_BLK_DEV_INITRD
 123 #if 0
 124         ROOT_DEV = Root_FD0; /* floppy */
 125         rd_prompt = 1;
 126         rd_doload = 1;
 127         rd_image_start = 0;
 128 #endif
 129 #if 0   /* XXX this may need to be updated for the new bootmem stuff,
 130            or possibly just deleted (see set_phys_avail() in init.c).
 131            - paulus. */
 132         /* initrd_start and size are setup by boot/head.S and kernel/head.S */
 133         if ( initrd_start )
 134         {
 135                 if (initrd_end > *memory_end_p)
 136                 {
 137                         printk("initrd extends beyond end of memory "
 138                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 139                                initrd_end,*memory_end_p);
 140                         initrd_start = 0;
 141                 }
 142         }
 143 #endif
 144 #endif
 145
 146 #if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
 147 #if defined(CONFIG_MTD_PHYSMAP)
 148        physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
 149                                                MPC8xxADS_BANK_WIDTH, NULL);
 150 #ifdef CONFIG_MTD_PARTITIONS
 151        physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
 152 #endif /* CONFIG_MTD_PARTITIONS */
 153 #endif /* CONFIG_MTD_PHYSMAP */
 154 #endif
 155
 156         board_init();
 157 }
 158
 159 void
 160 abort(void)
 161 {
 162 #ifdef CONFIG_XMON
 163         xmon(0);
 164 #endif
 165         machine_restart(NULL);
 166
 167         /* not reached */
 168         for (;;);
 169 }
 170
 171 /* A place holder for time base interrupts, if they are ever enabled. */
 172 irqreturn_t timebase_interrupt(int irq, void * dev, struct pt_regs * regs)
 173 {
 174         printk ("timebase_interrupt()\n");
 175
 176         return IRQ_HANDLED;
 177 }
 178
 179 static struct irqaction tbint_irqaction = {
 180         .handler = timebase_interrupt,
 181         .mask = CPU_MASK_NONE,
 182         .name = "tbint",
 183 };
 184
 185 /* per-board overridable init_internal_rtc() function. */
 186 void __init __attribute__ ((weak))
 187 init_internal_rtc(void)
 188 {
 189         /* Disable the RTC one second and alarm interrupts. */
 190         clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
 191
 192         /* Enable the RTC */
 193         setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
 194
 195 }
 196
 197 /* The decrementer counts at the system (internal) clock frequency divided by
 198  * sixteen, or external oscillator divided by four.  We force the processor
 199  * to use system clock divided by sixteen.
 200  */
 201 void __init m8xx_calibrate_decr(void)
 202 {
 203         bd_t    *binfo = (bd_t *)__res;
 204         int freq, fp, divisor;
 205
 206         /* Unlock the SCCR. */
 207         out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY);
 208         out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
 209
 210         /* Force all 8xx processors to use divide by 16 processor clock. */
 211         setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
 212         /* Processor frequency is MHz.
 213          * The value 'fp' is the number of decrementer ticks per second.
 214          */
 215         fp = binfo->bi_intfreq / 16;
 216         freq = fp*60;   /* try to make freq/1e6 an integer */
 217         divisor = 60;
 218         printk("Decrementer Frequency = %d/%d\n", freq, divisor);
 219         tb_ticks_per_jiffy = freq / HZ / divisor;
 220         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
 221
 222         /* Perform some more timer/timebase initialization.  This used
 223          * to be done elsewhere, but other changes caused it to get
 224          * called more than once....that is a bad thing.
 225          *
 226          * First, unlock all of the registers we are going to modify.
 227          * To protect them from corruption during power down, registers
 228          * that are maintained by keep alive power are "locked".  To
 229          * modify these registers we have to write the key value to
 230          * the key location associated with the register.
 231          * Some boards power up with these unlocked, while others
 232          * are locked.  Writing anything (including the unlock code?)
 233          * to the unlocked registers will lock them again.  So, here
 234          * we guarantee the registers are locked, then we unlock them
 235          * for our use.
 236          */
 237         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY);
 238         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY);
 239         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY);
 240         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY);
 241         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
 242         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
 243
 244         init_internal_rtc();
 245
 246         /* Enabling the decrementer also enables the timebase interrupts
 247          * (or from the other point of view, to get decrementer interrupts
 248          * we have to enable the timebase).  The decrementer interrupt
 249          * is wired into the vector table, nothing to do here for that.
 250          */
 251         out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE));
 252
 253         if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
 254                 panic("Could not allocate timer IRQ!");
 255
 256 #ifdef CONFIG_8xx_WDT
 257         /* Install watchdog timer handler early because it might be
 258          * already enabled by the bootloader
 259          */
 260         m8xx_wdt_handler_install(binfo);
 261 #endif
 262 }
 263
 264 /* The RTC on the MPC8xx is an internal register.
 265  * We want to protect this during power down, so we need to unlock,
 266  * modify, and re-lock.
 267  */
 268 static int
 269 m8xx_set_rtc_time(unsigned long time)
 270 {
 271         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY);
 272         out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time);
 273         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY);
 274         return(0);
 275 }
 276
 277 static unsigned long
 278 m8xx_get_rtc_time(void)
 279 {
 280         /* Get time from the RTC. */
 281         return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc);
 282 }
 283
 284 static void
 285 m8xx_restart(char *cmd)
 286 {
 287         __volatile__ unsigned char dummy;
 288
 289         local_irq_disable();
 290
 291         setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
 292         /* Clear the ME bit in MSR to cause checkstop on machine check
 293         */
 294         mtmsr(mfmsr() & ~0x1000);
 295
 296         dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]);
 297         printk("Restart failed\n");
 298         while(1);
 299 }
 300
 301 static void
 302 m8xx_power_off(void)
 303 {
 304    m8xx_restart(NULL);
 305 }
 306
 307 static void
 308 m8xx_halt(void)
 309 {
 310    m8xx_restart(NULL);
 311 }
 312
 313
 314 static int
 315 m8xx_show_percpuinfo(struct seq_file *m, int i)
 316 {
 317         bd_t    *bp;
 318
 319         bp = (bd_t *)__res;
 320
 321         seq_printf(m, "clock\t\t: %uMHz\n"
 322                    "bus clock\t: %uMHz\n",
 323                    bp->bi_intfreq / 1000000,
 324                    bp->bi_busfreq / 1000000);
 325
 326         return 0;
 327 }
 328
 329 #ifdef CONFIG_PCI
 330 static struct irqaction mbx_i8259_irqaction = {
 331         .handler = mbx_i8259_action,
 332         .mask = CPU_MASK_NONE,
 333         .name = "i8259 cascade",
 334 };
 335 #endif
 336
 337 /* Initialize the internal interrupt controller.  The number of
 338  * interrupts supported can vary with the processor type, and the
 339  * 82xx family can have up to 64.
 340  * External interrupts can be either edge or level triggered, and
 341  * need to be initialized by the appropriate driver.
 342  */
 343 static void __init
 344 m8xx_init_IRQ(void)
 345 {
 346         int i;
 347
 348         for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
 349                 irq_desc[i].chip = &ppc8xx_pic;
 350
 351         cpm_interrupt_init();
 352
 353 #if defined(CONFIG_PCI)
 354         for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
 355                 irq_desc[i].chip = &i8259_pic;
 356
 357         i8259_pic_irq_offset = I8259_IRQ_OFFSET;
 358         i8259_init(0);
 359
 360         /* The i8259 cascade interrupt must be level sensitive. */
 361
 362         clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
 363         if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
 364                 enable_irq(ISA_BRIDGE_INT);
 365 #endif  /* CONFIG_PCI */
 366 }
 367
 368 /* -------------------------------------------------------------------- */
 369
 370 /*
 371  * This is a big hack right now, but it may turn into something real
 372  * someday.
 373  *
 374  * For the 8xx boards (at this time anyway), there is nothing to initialize
 375  * associated the PROM.  Rather than include all of the prom.c
 376  * functions in the image just to get prom_init, all we really need right
 377  * now is the initialization of the physical memory region.
 378  */
 379 static unsigned long __init
 380 m8xx_find_end_of_memory(void)
 381 {
 382         bd_t    *binfo;
 383         extern unsigned char __res[];
 384
 385         binfo = (bd_t *)__res;
 386
 387         return binfo->bi_memsize;
 388 }
 389
 390 /*
 391  * Now map in some of the I/O space that is generically needed
 392  * or shared with multiple devices.
 393  * All of this fits into the same 4Mbyte region, so it only
 394  * requires one page table page.  (or at least it used to  -- paulus)
 395  */
 396 static void __init
 397 m8xx_map_io(void)
 398 {
 399         io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
 400 #ifdef CONFIG_MBX
 401         io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
 402         io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
 403         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 404
 405         /* Map some of the PCI/ISA I/O space to get the IDE interface.
 406         */
 407         io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
 408         io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
 409 #endif
 410 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 411         io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
 412 #if !defined(CONFIG_PCI)
 413         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 414 #endif
 415 #endif
 416 #if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
 417         io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
 418 #endif
 419 #ifdef CONFIG_FADS
 420         io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
 421 #endif
 422 #ifdef CONFIG_PCI
 423         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 424 #endif
 425 #if defined(CONFIG_NETTA)
 426         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 427 #endif
 428 }
 429
 430 void __init
 431 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 432                 unsigned long r6, unsigned long r7)
 433 {
 434         parse_bootinfo(find_bootinfo());
 435
 436         if ( r3 )
 437                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 438
 439 #ifdef CONFIG_PCI
 440         m8xx_setup_pci_ptrs();
 441 #endif
 442
 443 #ifdef CONFIG_BLK_DEV_INITRD
 444         /* take care of initrd if we have one */
 445         if ( r4 )
 446         {
 447                 initrd_start = r4 + KERNELBASE;
 448                 initrd_end = r5 + KERNELBASE;
 449         }
 450 #endif /* CONFIG_BLK_DEV_INITRD */
 451         /* take care of cmd line */
 452         if ( r6 )
 453         {
 454                 *(char *)(r7+KERNELBASE) = 0;
 455                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 456         }
 457
 458         identify_ppc_sys_by_name(BOARD_CHIP_NAME);
 459
 460         ppc_md.setup_arch               = m8xx_setup_arch;
 461         ppc_md.show_percpuinfo          = m8xx_show_percpuinfo;
 462         ppc_md.init_IRQ                 = m8xx_init_IRQ;
 463         ppc_md.get_irq                  = m8xx_get_irq;
 464         ppc_md.init                     = NULL;
 465
 466         ppc_md.restart                  = m8xx_restart;
 467         ppc_md.power_off                = m8xx_power_off;
 468         ppc_md.halt                     = m8xx_halt;
 469
 470         ppc_md.time_init                = NULL;
 471         ppc_md.set_rtc_time             = m8xx_set_rtc_time;
 472         ppc_md.get_rtc_time             = m8xx_get_rtc_time;
 473         ppc_md.calibrate_decr           = m8xx_calibrate_decr;
 474
 475         ppc_md.find_end_of_memory       = m8xx_find_end_of_memory;
 476         ppc_md.setup_io_mappings        = m8xx_map_io;
 477
 478 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE)
 479         m8xx_ide_init();
 480 #endif
 481 }