2 * Common routines for the Marvell/Galileo Discovery line of host bridges
3 * (gt64260, mv64360, mv64460, ...).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/string.h>
18 #include <linux/spinlock.h>
19 #include <linux/mv643xx.h>
20 #include <linux/platform_device.h>
22 #include <asm/byteorder.h>
25 #include <asm/uaccess.h>
26 #include <asm/machdep.h>
27 #include <asm/pci-bridge.h>
28 #include <asm/delay.h>
29 #include <asm/mv64x60.h>
32 u8 mv64x60_pci_exclude_bridge
= 1;
33 DEFINE_SPINLOCK(mv64x60_lock
);
35 static phys_addr_t mv64x60_bridge_pbase
;
36 static void __iomem
*mv64x60_bridge_vbase
;
37 static u32 mv64x60_bridge_type
= MV64x60_TYPE_INVALID
;
38 static u32 mv64x60_bridge_rev
;
39 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
40 static struct pci_controller sysfs_hose_a
;
43 static u32
gt64260_translate_size(u32 base
, u32 size
, u32 num_bits
);
44 static u32
gt64260_untranslate_size(u32 base
, u32 size
, u32 num_bits
);
45 static void gt64260_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
,
46 u32 window
, u32 base
);
47 static void gt64260_set_pci2regs_window(struct mv64x60_handle
*bh
,
48 struct pci_controller
*hose
, u32 bus
, u32 base
);
49 static u32
gt64260_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
);
50 static void gt64260_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
51 static void gt64260_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
52 static void gt64260_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
53 static void gt64260_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
54 static void gt64260_disable_all_windows(struct mv64x60_handle
*bh
,
55 struct mv64x60_setup_info
*si
);
56 static void gt64260a_chip_specific_init(struct mv64x60_handle
*bh
,
57 struct mv64x60_setup_info
*si
);
58 static void gt64260b_chip_specific_init(struct mv64x60_handle
*bh
,
59 struct mv64x60_setup_info
*si
);
61 static u32
mv64360_translate_size(u32 base
, u32 size
, u32 num_bits
);
62 static u32
mv64360_untranslate_size(u32 base
, u32 size
, u32 num_bits
);
63 static void mv64360_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
,
64 u32 window
, u32 base
);
65 static void mv64360_set_pci2regs_window(struct mv64x60_handle
*bh
,
66 struct pci_controller
*hose
, u32 bus
, u32 base
);
67 static u32
mv64360_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
);
68 static void mv64360_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
69 static void mv64360_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
);
70 static void mv64360_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
71 static void mv64360_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
);
72 static void mv64360_disable_all_windows(struct mv64x60_handle
*bh
,
73 struct mv64x60_setup_info
*si
);
74 static void mv64360_config_io2mem_windows(struct mv64x60_handle
*bh
,
75 struct mv64x60_setup_info
*si
,
76 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2]);
77 static void mv64360_set_mpsc2regs_window(struct mv64x60_handle
*bh
, u32 base
);
78 static void mv64360_chip_specific_init(struct mv64x60_handle
*bh
,
79 struct mv64x60_setup_info
*si
);
80 static void mv64460_chip_specific_init(struct mv64x60_handle
*bh
,
81 struct mv64x60_setup_info
*si
);
85 * Define tables that have the chip-specific info for each type of
86 * Marvell bridge chip.
88 static struct mv64x60_chip_info gt64260a_ci __initdata
= { /* GT64260A */
89 .translate_size
= gt64260_translate_size
,
90 .untranslate_size
= gt64260_untranslate_size
,
91 .set_pci2mem_window
= gt64260_set_pci2mem_window
,
92 .set_pci2regs_window
= gt64260_set_pci2regs_window
,
93 .is_enabled_32bit
= gt64260_is_enabled_32bit
,
94 .enable_window_32bit
= gt64260_enable_window_32bit
,
95 .disable_window_32bit
= gt64260_disable_window_32bit
,
96 .enable_window_64bit
= gt64260_enable_window_64bit
,
97 .disable_window_64bit
= gt64260_disable_window_64bit
,
98 .disable_all_windows
= gt64260_disable_all_windows
,
99 .chip_specific_init
= gt64260a_chip_specific_init
,
100 .window_tab_32bit
= gt64260_32bit_windows
,
101 .window_tab_64bit
= gt64260_64bit_windows
,
104 static struct mv64x60_chip_info gt64260b_ci __initdata
= { /* GT64260B */
105 .translate_size
= gt64260_translate_size
,
106 .untranslate_size
= gt64260_untranslate_size
,
107 .set_pci2mem_window
= gt64260_set_pci2mem_window
,
108 .set_pci2regs_window
= gt64260_set_pci2regs_window
,
109 .is_enabled_32bit
= gt64260_is_enabled_32bit
,
110 .enable_window_32bit
= gt64260_enable_window_32bit
,
111 .disable_window_32bit
= gt64260_disable_window_32bit
,
112 .enable_window_64bit
= gt64260_enable_window_64bit
,
113 .disable_window_64bit
= gt64260_disable_window_64bit
,
114 .disable_all_windows
= gt64260_disable_all_windows
,
115 .chip_specific_init
= gt64260b_chip_specific_init
,
116 .window_tab_32bit
= gt64260_32bit_windows
,
117 .window_tab_64bit
= gt64260_64bit_windows
,
120 static struct mv64x60_chip_info mv64360_ci __initdata
= { /* MV64360 */
121 .translate_size
= mv64360_translate_size
,
122 .untranslate_size
= mv64360_untranslate_size
,
123 .set_pci2mem_window
= mv64360_set_pci2mem_window
,
124 .set_pci2regs_window
= mv64360_set_pci2regs_window
,
125 .is_enabled_32bit
= mv64360_is_enabled_32bit
,
126 .enable_window_32bit
= mv64360_enable_window_32bit
,
127 .disable_window_32bit
= mv64360_disable_window_32bit
,
128 .enable_window_64bit
= mv64360_enable_window_64bit
,
129 .disable_window_64bit
= mv64360_disable_window_64bit
,
130 .disable_all_windows
= mv64360_disable_all_windows
,
131 .config_io2mem_windows
= mv64360_config_io2mem_windows
,
132 .set_mpsc2regs_window
= mv64360_set_mpsc2regs_window
,
133 .chip_specific_init
= mv64360_chip_specific_init
,
134 .window_tab_32bit
= mv64360_32bit_windows
,
135 .window_tab_64bit
= mv64360_64bit_windows
,
138 static struct mv64x60_chip_info mv64460_ci __initdata
= { /* MV64460 */
139 .translate_size
= mv64360_translate_size
,
140 .untranslate_size
= mv64360_untranslate_size
,
141 .set_pci2mem_window
= mv64360_set_pci2mem_window
,
142 .set_pci2regs_window
= mv64360_set_pci2regs_window
,
143 .is_enabled_32bit
= mv64360_is_enabled_32bit
,
144 .enable_window_32bit
= mv64360_enable_window_32bit
,
145 .disable_window_32bit
= mv64360_disable_window_32bit
,
146 .enable_window_64bit
= mv64360_enable_window_64bit
,
147 .disable_window_64bit
= mv64360_disable_window_64bit
,
148 .disable_all_windows
= mv64360_disable_all_windows
,
149 .config_io2mem_windows
= mv64360_config_io2mem_windows
,
150 .set_mpsc2regs_window
= mv64360_set_mpsc2regs_window
,
151 .chip_specific_init
= mv64460_chip_specific_init
,
152 .window_tab_32bit
= mv64360_32bit_windows
,
153 .window_tab_64bit
= mv64360_64bit_windows
,
157 *****************************************************************************
159 * Platform Device Definitions
161 *****************************************************************************
163 #ifdef CONFIG_SERIAL_MPSC
164 static struct mpsc_shared_pdata mv64x60_mpsc_shared_pdata
= {
165 .mrr_val
= 0x3ffffe38,
172 static struct resource mv64x60_mpsc_shared_resources
[] = {
173 /* Do not change the order of the IORESOURCE_MEM resources */
175 .name
= "mpsc routing base",
176 .start
= MV64x60_MPSC_ROUTING_OFFSET
,
177 .end
= MV64x60_MPSC_ROUTING_OFFSET
+
178 MPSC_ROUTING_REG_BLOCK_SIZE
- 1,
179 .flags
= IORESOURCE_MEM
,
182 .name
= "sdma intr base",
183 .start
= MV64x60_SDMA_INTR_OFFSET
,
184 .end
= MV64x60_SDMA_INTR_OFFSET
+
185 MPSC_SDMA_INTR_REG_BLOCK_SIZE
- 1,
186 .flags
= IORESOURCE_MEM
,
190 static struct platform_device mpsc_shared_device
= { /* Shared device */
191 .name
= MPSC_SHARED_NAME
,
193 .num_resources
= ARRAY_SIZE(mv64x60_mpsc_shared_resources
),
194 .resource
= mv64x60_mpsc_shared_resources
,
196 .platform_data
= &mv64x60_mpsc_shared_pdata
,
200 static struct mpsc_pdata mv64x60_mpsc0_pdata
= {
204 .default_baud
= 9600,
206 .default_parity
= 'n',
208 .chr_1_val
= 0x00000000,
209 .chr_2_val
= 0x00000000,
210 .chr_10_val
= 0x00000003,
214 .brg_clk_src
= 8, /* Default to TCLK */
215 .brg_clk_freq
= 100000000, /* Default to 100 MHz */
218 static struct resource mv64x60_mpsc0_resources
[] = {
219 /* Do not change the order of the IORESOURCE_MEM resources */
221 .name
= "mpsc 0 base",
222 .start
= MV64x60_MPSC_0_OFFSET
,
223 .end
= MV64x60_MPSC_0_OFFSET
+ MPSC_REG_BLOCK_SIZE
- 1,
224 .flags
= IORESOURCE_MEM
,
227 .name
= "sdma 0 base",
228 .start
= MV64x60_SDMA_0_OFFSET
,
229 .end
= MV64x60_SDMA_0_OFFSET
+ MPSC_SDMA_REG_BLOCK_SIZE
- 1,
230 .flags
= IORESOURCE_MEM
,
233 .name
= "brg 0 base",
234 .start
= MV64x60_BRG_0_OFFSET
,
235 .end
= MV64x60_BRG_0_OFFSET
+ MPSC_BRG_REG_BLOCK_SIZE
- 1,
236 .flags
= IORESOURCE_MEM
,
239 .name
= "sdma 0 irq",
240 .start
= MV64x60_IRQ_SDMA_0
,
241 .end
= MV64x60_IRQ_SDMA_0
,
242 .flags
= IORESOURCE_IRQ
,
246 static struct platform_device mpsc0_device
= {
247 .name
= MPSC_CTLR_NAME
,
249 .num_resources
= ARRAY_SIZE(mv64x60_mpsc0_resources
),
250 .resource
= mv64x60_mpsc0_resources
,
252 .platform_data
= &mv64x60_mpsc0_pdata
,
256 static struct mpsc_pdata mv64x60_mpsc1_pdata
= {
260 .default_baud
= 9600,
262 .default_parity
= 'n',
264 .chr_1_val
= 0x00000000,
265 .chr_1_val
= 0x00000000,
266 .chr_2_val
= 0x00000000,
267 .chr_10_val
= 0x00000003,
271 .brg_clk_src
= 8, /* Default to TCLK */
272 .brg_clk_freq
= 100000000, /* Default to 100 MHz */
275 static struct resource mv64x60_mpsc1_resources
[] = {
276 /* Do not change the order of the IORESOURCE_MEM resources */
278 .name
= "mpsc 1 base",
279 .start
= MV64x60_MPSC_1_OFFSET
,
280 .end
= MV64x60_MPSC_1_OFFSET
+ MPSC_REG_BLOCK_SIZE
- 1,
281 .flags
= IORESOURCE_MEM
,
284 .name
= "sdma 1 base",
285 .start
= MV64x60_SDMA_1_OFFSET
,
286 .end
= MV64x60_SDMA_1_OFFSET
+ MPSC_SDMA_REG_BLOCK_SIZE
- 1,
287 .flags
= IORESOURCE_MEM
,
290 .name
= "brg 1 base",
291 .start
= MV64x60_BRG_1_OFFSET
,
292 .end
= MV64x60_BRG_1_OFFSET
+ MPSC_BRG_REG_BLOCK_SIZE
- 1,
293 .flags
= IORESOURCE_MEM
,
296 .name
= "sdma 1 irq",
297 .start
= MV64360_IRQ_SDMA_1
,
298 .end
= MV64360_IRQ_SDMA_1
,
299 .flags
= IORESOURCE_IRQ
,
303 static struct platform_device mpsc1_device
= {
304 .name
= MPSC_CTLR_NAME
,
306 .num_resources
= ARRAY_SIZE(mv64x60_mpsc1_resources
),
307 .resource
= mv64x60_mpsc1_resources
,
309 .platform_data
= &mv64x60_mpsc1_pdata
,
314 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
315 static struct resource mv64x60_eth_shared_resources
[] = {
317 .name
= "ethernet shared base",
318 .start
= MV643XX_ETH_SHARED_REGS
,
319 .end
= MV643XX_ETH_SHARED_REGS
+
320 MV643XX_ETH_SHARED_REGS_SIZE
- 1,
321 .flags
= IORESOURCE_MEM
,
325 static struct platform_device mv64x60_eth_shared_device
= {
326 .name
= MV643XX_ETH_SHARED_NAME
,
328 .num_resources
= ARRAY_SIZE(mv64x60_eth_shared_resources
),
329 .resource
= mv64x60_eth_shared_resources
,
332 #ifdef CONFIG_MV643XX_ETH_0
333 static struct resource mv64x60_eth0_resources
[] = {
336 .start
= MV64x60_IRQ_ETH_0
,
337 .end
= MV64x60_IRQ_ETH_0
,
338 .flags
= IORESOURCE_IRQ
,
342 static struct mv643xx_eth_platform_data eth0_pd
;
344 static struct platform_device eth0_device
= {
345 .name
= MV643XX_ETH_NAME
,
347 .num_resources
= ARRAY_SIZE(mv64x60_eth0_resources
),
348 .resource
= mv64x60_eth0_resources
,
350 .platform_data
= ð0_pd
,
355 #ifdef CONFIG_MV643XX_ETH_1
356 static struct resource mv64x60_eth1_resources
[] = {
359 .start
= MV64x60_IRQ_ETH_1
,
360 .end
= MV64x60_IRQ_ETH_1
,
361 .flags
= IORESOURCE_IRQ
,
365 static struct mv643xx_eth_platform_data eth1_pd
;
367 static struct platform_device eth1_device
= {
368 .name
= MV643XX_ETH_NAME
,
370 .num_resources
= ARRAY_SIZE(mv64x60_eth1_resources
),
371 .resource
= mv64x60_eth1_resources
,
373 .platform_data
= ð1_pd
,
378 #ifdef CONFIG_MV643XX_ETH_2
379 static struct resource mv64x60_eth2_resources
[] = {
382 .start
= MV64x60_IRQ_ETH_2
,
383 .end
= MV64x60_IRQ_ETH_2
,
384 .flags
= IORESOURCE_IRQ
,
388 static struct mv643xx_eth_platform_data eth2_pd
;
390 static struct platform_device eth2_device
= {
391 .name
= MV643XX_ETH_NAME
,
393 .num_resources
= ARRAY_SIZE(mv64x60_eth2_resources
),
394 .resource
= mv64x60_eth2_resources
,
396 .platform_data
= ð2_pd
,
402 #ifdef CONFIG_I2C_MV64XXX
403 static struct mv64xxx_i2c_pdata mv64xxx_i2c_pdata
= {
406 .timeout
= 1000, /* Default timeout of 1 second */
410 static struct resource mv64xxx_i2c_resources
[] = {
411 /* Do not change the order of the IORESOURCE_MEM resources */
413 .name
= "mv64xxx i2c base",
414 .start
= MV64XXX_I2C_OFFSET
,
415 .end
= MV64XXX_I2C_OFFSET
+ MV64XXX_I2C_REG_BLOCK_SIZE
- 1,
416 .flags
= IORESOURCE_MEM
,
419 .name
= "mv64xxx i2c irq",
420 .start
= MV64x60_IRQ_I2C
,
421 .end
= MV64x60_IRQ_I2C
,
422 .flags
= IORESOURCE_IRQ
,
426 static struct platform_device i2c_device
= {
427 .name
= MV64XXX_I2C_CTLR_NAME
,
429 .num_resources
= ARRAY_SIZE(mv64xxx_i2c_resources
),
430 .resource
= mv64xxx_i2c_resources
,
432 .platform_data
= &mv64xxx_i2c_pdata
,
437 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
438 static struct mv64xxx_pdata mv64xxx_pdata
= {
442 static struct platform_device mv64xxx_device
= { /* general mv64x60 stuff */
443 .name
= MV64XXX_DEV_NAME
,
446 .platform_data
= &mv64xxx_pdata
,
451 static struct platform_device
*mv64x60_pd_devs
[] __initdata
= {
452 #ifdef CONFIG_SERIAL_MPSC
457 #if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
458 &mv64x60_eth_shared_device
,
460 #ifdef CONFIG_MV643XX_ETH_0
463 #ifdef CONFIG_MV643XX_ETH_1
466 #ifdef CONFIG_MV643XX_ETH_2
469 #ifdef CONFIG_I2C_MV64XXX
472 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
478 *****************************************************************************
480 * Bridge Initialization Routines
482 *****************************************************************************
487 * Initialze the bridge based on setting passed in via 'si'. The bridge
488 * handle, 'bh', will be set so that it can be used to make subsequent
489 * calls to routines in this file.
492 mv64x60_init(struct mv64x60_handle
*bh
, struct mv64x60_setup_info
*si
)
494 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2];
497 ppc_md
.progress("mv64x60 initialization", 0x0);
499 spin_lock_init(&mv64x60_lock
);
500 mv64x60_early_init(bh
, si
);
502 if (mv64x60_get_type(bh
) || mv64x60_setup_for_chip(bh
)) {
506 ppc_md
.progress("mv64x60_init: Can't determine chip",0);
510 bh
->ci
->disable_all_windows(bh
, si
);
511 mv64x60_get_mem_windows(bh
, mem_windows
);
512 mv64x60_config_cpu2mem_windows(bh
, si
, mem_windows
);
514 if (bh
->ci
->config_io2mem_windows
)
515 bh
->ci
->config_io2mem_windows(bh
, si
, mem_windows
);
516 if (bh
->ci
->set_mpsc2regs_window
)
517 bh
->ci
->set_mpsc2regs_window(bh
, si
->phys_reg_base
);
519 if (si
->pci_1
.enable_bus
) {
520 bh
->io_base_b
= (u32
)ioremap(si
->pci_1
.pci_io
.cpu_base
,
521 si
->pci_1
.pci_io
.size
);
522 isa_io_base
= bh
->io_base_b
;
525 if (si
->pci_0
.enable_bus
) {
526 bh
->io_base_a
= (u32
)ioremap(si
->pci_0
.pci_io
.cpu_base
,
527 si
->pci_0
.pci_io
.size
);
528 isa_io_base
= bh
->io_base_a
;
530 mv64x60_alloc_hose(bh
, MV64x60_PCI0_CONFIG_ADDR
,
531 MV64x60_PCI0_CONFIG_DATA
, &bh
->hose_a
);
532 mv64x60_config_resources(bh
->hose_a
, &si
->pci_0
, bh
->io_base_a
);
533 mv64x60_config_pci_params(bh
->hose_a
, &si
->pci_0
);
535 mv64x60_config_cpu2pci_windows(bh
, &si
->pci_0
, 0);
536 mv64x60_config_pci2mem_windows(bh
, bh
->hose_a
, &si
->pci_0
, 0,
538 bh
->ci
->set_pci2regs_window(bh
, bh
->hose_a
, 0,
542 if (si
->pci_1
.enable_bus
) {
543 mv64x60_alloc_hose(bh
, MV64x60_PCI1_CONFIG_ADDR
,
544 MV64x60_PCI1_CONFIG_DATA
, &bh
->hose_b
);
545 mv64x60_config_resources(bh
->hose_b
, &si
->pci_1
, bh
->io_base_b
);
546 mv64x60_config_pci_params(bh
->hose_b
, &si
->pci_1
);
548 mv64x60_config_cpu2pci_windows(bh
, &si
->pci_1
, 1);
549 mv64x60_config_pci2mem_windows(bh
, bh
->hose_b
, &si
->pci_1
, 1,
551 bh
->ci
->set_pci2regs_window(bh
, bh
->hose_b
, 1,
555 bh
->ci
->chip_specific_init(bh
, si
);
556 mv64x60_pd_fixup(bh
, mv64x60_pd_devs
, ARRAY_SIZE(mv64x60_pd_devs
));
562 * mv64x60_early_init()
564 * Do some bridge work that must take place before we start messing with
565 * the bridge for real.
568 mv64x60_early_init(struct mv64x60_handle
*bh
, struct mv64x60_setup_info
*si
)
570 struct pci_controller hose_a
, hose_b
;
572 memset(bh
, 0, sizeof(*bh
));
574 bh
->p_base
= si
->phys_reg_base
;
575 bh
->v_base
= ioremap(bh
->p_base
, MV64x60_INTERNAL_SPACE_SIZE
);
577 mv64x60_bridge_pbase
= bh
->p_base
;
578 mv64x60_bridge_vbase
= bh
->v_base
;
580 /* Assuming pci mode [reserved] bits 4:5 on 64260 are 0 */
581 bh
->pci_mode_a
= mv64x60_read(bh
, MV64x60_PCI0_MODE
) &
582 MV64x60_PCIMODE_MASK
;
583 bh
->pci_mode_b
= mv64x60_read(bh
, MV64x60_PCI1_MODE
) &
584 MV64x60_PCIMODE_MASK
;
586 /* Need temporary hose structs to call mv64x60_set_bus() */
587 memset(&hose_a
, 0, sizeof(hose_a
));
588 memset(&hose_b
, 0, sizeof(hose_b
));
589 setup_indirect_pci_nomap(&hose_a
, bh
->v_base
+ MV64x60_PCI0_CONFIG_ADDR
,
590 bh
->v_base
+ MV64x60_PCI0_CONFIG_DATA
);
591 setup_indirect_pci_nomap(&hose_b
, bh
->v_base
+ MV64x60_PCI1_CONFIG_ADDR
,
592 bh
->v_base
+ MV64x60_PCI1_CONFIG_DATA
);
593 bh
->hose_a
= &hose_a
;
594 bh
->hose_b
= &hose_b
;
596 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
597 /* Save a copy of hose_a for sysfs functions -- hack */
598 memcpy(&sysfs_hose_a
, &hose_a
, sizeof(hose_a
));
601 mv64x60_set_bus(bh
, 0, 0);
602 mv64x60_set_bus(bh
, 1, 0);
607 /* Clear bit 0 of PCI addr decode control so PCI->CPU remap 1:1 */
608 mv64x60_clr_bits(bh
, MV64x60_PCI0_PCI_DECODE_CNTL
, 0x00000001);
609 mv64x60_clr_bits(bh
, MV64x60_PCI1_PCI_DECODE_CNTL
, 0x00000001);
611 /* Bit 12 MUST be 0; set bit 27--don't auto-update cpu remap regs */
612 mv64x60_clr_bits(bh
, MV64x60_CPU_CONFIG
, (1<<12));
613 mv64x60_set_bits(bh
, MV64x60_CPU_CONFIG
, (1<<27));
615 mv64x60_set_bits(bh
, MV64x60_PCI0_TO_RETRY
, 0xffff);
616 mv64x60_set_bits(bh
, MV64x60_PCI1_TO_RETRY
, 0xffff);
620 *****************************************************************************
622 * Window Config Routines
624 *****************************************************************************
627 * mv64x60_get_32bit_window()
629 * Determine the base address and size of a 32-bit window on the bridge.
632 mv64x60_get_32bit_window(struct mv64x60_handle
*bh
, u32 window
,
633 u32
*base
, u32
*size
)
635 u32 val
, base_reg
, size_reg
, base_bits
, size_bits
;
636 u32 (*get_from_field
)(u32 val
, u32 num_bits
);
638 base_reg
= bh
->ci
->window_tab_32bit
[window
].base_reg
;
641 size_reg
= bh
->ci
->window_tab_32bit
[window
].size_reg
;
642 base_bits
= bh
->ci
->window_tab_32bit
[window
].base_bits
;
643 size_bits
= bh
->ci
->window_tab_32bit
[window
].size_bits
;
644 get_from_field
= bh
->ci
->window_tab_32bit
[window
].get_from_field
;
646 val
= mv64x60_read(bh
, base_reg
);
647 *base
= get_from_field(val
, base_bits
);
650 val
= mv64x60_read(bh
, size_reg
);
651 val
= get_from_field(val
, size_bits
);
652 *size
= bh
->ci
->untranslate_size(*base
, val
, size_bits
);
660 pr_debug("get 32bit window: %d, base: 0x%x, size: 0x%x\n",
661 window
, *base
, *size
);
665 * mv64x60_set_32bit_window()
667 * Set the base address and size of a 32-bit window on the bridge.
670 mv64x60_set_32bit_window(struct mv64x60_handle
*bh
, u32 window
,
671 u32 base
, u32 size
, u32 other_bits
)
673 u32 val
, base_reg
, size_reg
, base_bits
, size_bits
;
674 u32 (*map_to_field
)(u32 val
, u32 num_bits
);
676 pr_debug("set 32bit window: %d, base: 0x%x, size: 0x%x, other: 0x%x\n",
677 window
, base
, size
, other_bits
);
679 base_reg
= bh
->ci
->window_tab_32bit
[window
].base_reg
;
682 size_reg
= bh
->ci
->window_tab_32bit
[window
].size_reg
;
683 base_bits
= bh
->ci
->window_tab_32bit
[window
].base_bits
;
684 size_bits
= bh
->ci
->window_tab_32bit
[window
].size_bits
;
685 map_to_field
= bh
->ci
->window_tab_32bit
[window
].map_to_field
;
687 val
= map_to_field(base
, base_bits
) | other_bits
;
688 mv64x60_write(bh
, base_reg
, val
);
691 val
= bh
->ci
->translate_size(base
, size
, size_bits
);
692 val
= map_to_field(val
, size_bits
);
693 mv64x60_write(bh
, size_reg
, val
);
696 (void)mv64x60_read(bh
, base_reg
); /* Flush FIFO */
701 * mv64x60_get_64bit_window()
703 * Determine the base address and size of a 64-bit window on the bridge.
706 mv64x60_get_64bit_window(struct mv64x60_handle
*bh
, u32 window
,
707 u32
*base_hi
, u32
*base_lo
, u32
*size
)
709 u32 val
, base_lo_reg
, size_reg
, base_lo_bits
, size_bits
;
710 u32 (*get_from_field
)(u32 val
, u32 num_bits
);
712 base_lo_reg
= bh
->ci
->window_tab_64bit
[window
].base_lo_reg
;
714 if (base_lo_reg
!= 0) {
715 size_reg
= bh
->ci
->window_tab_64bit
[window
].size_reg
;
716 base_lo_bits
= bh
->ci
->window_tab_64bit
[window
].base_lo_bits
;
717 size_bits
= bh
->ci
->window_tab_64bit
[window
].size_bits
;
718 get_from_field
= bh
->ci
->window_tab_64bit
[window
].get_from_field
;
720 *base_hi
= mv64x60_read(bh
,
721 bh
->ci
->window_tab_64bit
[window
].base_hi_reg
);
723 val
= mv64x60_read(bh
, base_lo_reg
);
724 *base_lo
= get_from_field(val
, base_lo_bits
);
727 val
= mv64x60_read(bh
, size_reg
);
728 val
= get_from_field(val
, size_bits
);
729 *size
= bh
->ci
->untranslate_size(*base_lo
, val
,
739 pr_debug("get 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
740 "size: 0x%x\n", window
, *base_hi
, *base_lo
, *size
);
744 * mv64x60_set_64bit_window()
746 * Set the base address and size of a 64-bit window on the bridge.
749 mv64x60_set_64bit_window(struct mv64x60_handle
*bh
, u32 window
,
750 u32 base_hi
, u32 base_lo
, u32 size
, u32 other_bits
)
752 u32 val
, base_lo_reg
, size_reg
, base_lo_bits
, size_bits
;
753 u32 (*map_to_field
)(u32 val
, u32 num_bits
);
755 pr_debug("set 64bit window: %d, base hi: 0x%x, base lo: 0x%x, "
756 "size: 0x%x, other: 0x%x\n",
757 window
, base_hi
, base_lo
, size
, other_bits
);
759 base_lo_reg
= bh
->ci
->window_tab_64bit
[window
].base_lo_reg
;
761 if (base_lo_reg
!= 0) {
762 size_reg
= bh
->ci
->window_tab_64bit
[window
].size_reg
;
763 base_lo_bits
= bh
->ci
->window_tab_64bit
[window
].base_lo_bits
;
764 size_bits
= bh
->ci
->window_tab_64bit
[window
].size_bits
;
765 map_to_field
= bh
->ci
->window_tab_64bit
[window
].map_to_field
;
767 mv64x60_write(bh
, bh
->ci
->window_tab_64bit
[window
].base_hi_reg
,
770 val
= map_to_field(base_lo
, base_lo_bits
) | other_bits
;
771 mv64x60_write(bh
, base_lo_reg
, val
);
774 val
= bh
->ci
->translate_size(base_lo
, size
, size_bits
);
775 val
= map_to_field(val
, size_bits
);
776 mv64x60_write(bh
, size_reg
, val
);
779 (void)mv64x60_read(bh
, base_lo_reg
); /* Flush FIFO */
786 * Take the high-order 'num_bits' of 'val' & mask off low bits.
789 mv64x60_mask(u32 val
, u32 num_bits
)
791 return val
& (0xffffffff << (32 - num_bits
));
795 * mv64x60_shift_left()
797 * Take the low-order 'num_bits' of 'val', shift left to align at bit 31 (MSB).
800 mv64x60_shift_left(u32 val
, u32 num_bits
)
802 return val
<< (32 - num_bits
);
806 * mv64x60_shift_right()
808 * Take the high-order 'num_bits' of 'val', shift right to align at bit 0 (LSB).
811 mv64x60_shift_right(u32 val
, u32 num_bits
)
813 return val
>> (32 - num_bits
);
817 *****************************************************************************
819 * Chip Identification Routines
821 *****************************************************************************
826 * Determine the type of bridge chip we have.
829 mv64x60_get_type(struct mv64x60_handle
*bh
)
831 struct pci_controller hose
;
835 memset(&hose
, 0, sizeof(hose
));
836 setup_indirect_pci_nomap(&hose
, bh
->v_base
+ MV64x60_PCI0_CONFIG_ADDR
,
837 bh
->v_base
+ MV64x60_PCI0_CONFIG_DATA
);
839 save_exclude
= mv64x60_pci_exclude_bridge
;
840 mv64x60_pci_exclude_bridge
= 0;
841 /* Sanity check of bridge's Vendor ID */
842 early_read_config_word(&hose
, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID
, &val
);
844 if (val
!= PCI_VENDOR_ID_MARVELL
) {
845 mv64x60_pci_exclude_bridge
= save_exclude
;
849 /* Get the revision of the chip */
850 early_read_config_word(&hose
, 0, PCI_DEVFN(0, 0), PCI_CLASS_REVISION
,
852 bh
->rev
= (u32
)(val
& 0xff);
854 /* Figure out the type of Marvell bridge it is */
855 early_read_config_word(&hose
, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID
, &val
);
856 mv64x60_pci_exclude_bridge
= save_exclude
;
859 case PCI_DEVICE_ID_MARVELL_GT64260
:
862 bh
->type
= MV64x60_TYPE_GT64260A
;
866 printk(KERN_WARNING
"Unsupported GT64260 rev %04x\n",
868 /* Assume its similar to a 'B' rev and fallthru */
870 bh
->type
= MV64x60_TYPE_GT64260B
;
875 case PCI_DEVICE_ID_MARVELL_MV64360
:
876 /* Marvell won't tell me how to distinguish a 64361 & 64362 */
877 bh
->type
= MV64x60_TYPE_MV64360
;
880 case PCI_DEVICE_ID_MARVELL_MV64460
:
881 bh
->type
= MV64x60_TYPE_MV64460
;
885 printk(KERN_ERR
"Unknown Marvell bridge type %04x\n", val
);
889 /* Hang onto bridge type & rev for PIC code */
890 mv64x60_bridge_type
= bh
->type
;
891 mv64x60_bridge_rev
= bh
->rev
;
897 * mv64x60_setup_for_chip()
899 * Set 'bh' to use the proper set of routine for the bridge chip that we have.
902 mv64x60_setup_for_chip(struct mv64x60_handle
*bh
)
906 /* Set up chip-specific info based on the chip/bridge type */
908 case MV64x60_TYPE_GT64260A
:
909 bh
->ci
= >64260a_ci
;
912 case MV64x60_TYPE_GT64260B
:
913 bh
->ci
= >64260b_ci
;
916 case MV64x60_TYPE_MV64360
:
917 bh
->ci
= &mv64360_ci
;
920 case MV64x60_TYPE_MV64460
:
921 bh
->ci
= &mv64460_ci
;
924 case MV64x60_TYPE_INVALID
:
927 ppc_md
.progress("mv64x60: Unsupported bridge", 0x0);
928 printk(KERN_ERR
"mv64x60: Unsupported bridge\n");
936 * mv64x60_get_bridge_vbase()
938 * Return the virtual address of the bridge's registers.
941 mv64x60_get_bridge_vbase(void)
943 return mv64x60_bridge_vbase
;
947 * mv64x60_get_bridge_type()
949 * Return the type of bridge on the platform.
952 mv64x60_get_bridge_type(void)
954 return mv64x60_bridge_type
;
958 * mv64x60_get_bridge_rev()
960 * Return the revision of the bridge on the platform.
963 mv64x60_get_bridge_rev(void)
965 return mv64x60_bridge_rev
;
969 *****************************************************************************
971 * System Memory Window Related Routines
973 *****************************************************************************
976 * mv64x60_get_mem_size()
978 * Calculate the amount of memory that the memory controller is set up for.
979 * This should only be used by board-specific code if there is no other
980 * way to determine the amount of memory in the system.
983 mv64x60_get_mem_size(u32 bridge_base
, u32 chip_type
)
985 struct mv64x60_handle bh
;
986 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2];
989 memset(&bh
, 0, sizeof(bh
));
992 bh
.v_base
= (void *)bridge_base
;
994 if (!mv64x60_setup_for_chip(&bh
)) {
995 mv64x60_get_mem_windows(&bh
, mem_windows
);
996 rc
= mv64x60_calc_mem_size(&bh
, mem_windows
);
1003 * mv64x60_get_mem_windows()
1005 * Get the values in the memory controller & return in the 'mem_windows' array.
1008 mv64x60_get_mem_windows(struct mv64x60_handle
*bh
,
1009 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1013 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
1014 if (bh
->ci
->is_enabled_32bit(bh
, win
))
1015 mv64x60_get_32bit_window(bh
, win
,
1016 &mem_windows
[i
][0], &mem_windows
[i
][1]);
1018 mem_windows
[i
][0] = 0;
1019 mem_windows
[i
][1] = 0;
1024 * mv64x60_calc_mem_size()
1026 * Using the memory controller register values in 'mem_windows', determine
1027 * how much memory it is set up for.
1030 mv64x60_calc_mem_size(struct mv64x60_handle
*bh
,
1031 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1035 for (i
=0; i
<MV64x60_CPU2MEM_WINDOWS
; i
++)
1036 total
+= mem_windows
[i
][1];
1042 *****************************************************************************
1044 * CPU->System MEM, PCI Config Routines
1046 *****************************************************************************
1049 * mv64x60_config_cpu2mem_windows()
1051 * Configure CPU->Memory windows on the bridge.
1053 static u32 prot_tab
[] __initdata
= {
1054 MV64x60_CPU_PROT_0_WIN
, MV64x60_CPU_PROT_1_WIN
,
1055 MV64x60_CPU_PROT_2_WIN
, MV64x60_CPU_PROT_3_WIN
1058 static u32 cpu_snoop_tab
[] __initdata
= {
1059 MV64x60_CPU_SNOOP_0_WIN
, MV64x60_CPU_SNOOP_1_WIN
,
1060 MV64x60_CPU_SNOOP_2_WIN
, MV64x60_CPU_SNOOP_3_WIN
1064 mv64x60_config_cpu2mem_windows(struct mv64x60_handle
*bh
,
1065 struct mv64x60_setup_info
*si
,
1066 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1070 /* Set CPU protection & snoop windows */
1071 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
1072 if (bh
->ci
->is_enabled_32bit(bh
, win
)) {
1073 mv64x60_set_32bit_window(bh
, prot_tab
[i
],
1074 mem_windows
[i
][0], mem_windows
[i
][1],
1075 si
->cpu_prot_options
[i
]);
1076 bh
->ci
->enable_window_32bit(bh
, prot_tab
[i
]);
1078 if (bh
->ci
->window_tab_32bit
[cpu_snoop_tab
[i
]].
1080 mv64x60_set_32bit_window(bh
, cpu_snoop_tab
[i
],
1081 mem_windows
[i
][0], mem_windows
[i
][1],
1082 si
->cpu_snoop_options
[i
]);
1083 bh
->ci
->enable_window_32bit(bh
,
1091 * mv64x60_config_cpu2pci_windows()
1093 * Configure the CPU->PCI windows for one of the PCI buses.
1095 static u32 win_tab
[2][4] __initdata
= {
1096 { MV64x60_CPU2PCI0_IO_WIN
, MV64x60_CPU2PCI0_MEM_0_WIN
,
1097 MV64x60_CPU2PCI0_MEM_1_WIN
, MV64x60_CPU2PCI0_MEM_2_WIN
},
1098 { MV64x60_CPU2PCI1_IO_WIN
, MV64x60_CPU2PCI1_MEM_0_WIN
,
1099 MV64x60_CPU2PCI1_MEM_1_WIN
, MV64x60_CPU2PCI1_MEM_2_WIN
},
1102 static u32 remap_tab
[2][4] __initdata
= {
1103 { MV64x60_CPU2PCI0_IO_REMAP_WIN
, MV64x60_CPU2PCI0_MEM_0_REMAP_WIN
,
1104 MV64x60_CPU2PCI0_MEM_1_REMAP_WIN
, MV64x60_CPU2PCI0_MEM_2_REMAP_WIN
},
1105 { MV64x60_CPU2PCI1_IO_REMAP_WIN
, MV64x60_CPU2PCI1_MEM_0_REMAP_WIN
,
1106 MV64x60_CPU2PCI1_MEM_1_REMAP_WIN
, MV64x60_CPU2PCI1_MEM_2_REMAP_WIN
}
1110 mv64x60_config_cpu2pci_windows(struct mv64x60_handle
*bh
,
1111 struct mv64x60_pci_info
*pi
, u32 bus
)
1115 if (pi
->pci_io
.size
> 0) {
1116 mv64x60_set_32bit_window(bh
, win_tab
[bus
][0],
1117 pi
->pci_io
.cpu_base
, pi
->pci_io
.size
, pi
->pci_io
.swap
);
1118 mv64x60_set_32bit_window(bh
, remap_tab
[bus
][0],
1119 pi
->pci_io
.pci_base_lo
, 0, 0);
1120 bh
->ci
->enable_window_32bit(bh
, win_tab
[bus
][0]);
1121 } else /* Actually, the window should already be disabled */
1122 bh
->ci
->disable_window_32bit(bh
, win_tab
[bus
][0]);
1125 if (pi
->pci_mem
[i
].size
> 0) {
1126 mv64x60_set_32bit_window(bh
, win_tab
[bus
][i
+1],
1127 pi
->pci_mem
[i
].cpu_base
, pi
->pci_mem
[i
].size
,
1128 pi
->pci_mem
[i
].swap
);
1129 mv64x60_set_64bit_window(bh
, remap_tab
[bus
][i
+1],
1130 pi
->pci_mem
[i
].pci_base_hi
,
1131 pi
->pci_mem
[i
].pci_base_lo
, 0, 0);
1132 bh
->ci
->enable_window_32bit(bh
, win_tab
[bus
][i
+1]);
1133 } else /* Actually, the window should already be disabled */
1134 bh
->ci
->disable_window_32bit(bh
, win_tab
[bus
][i
+1]);
1138 *****************************************************************************
1140 * PCI->System MEM Config Routines
1142 *****************************************************************************
1145 * mv64x60_config_pci2mem_windows()
1147 * Configure the PCI->Memory windows on the bridge.
1149 static u32 pci_acc_tab
[2][4] __initdata
= {
1150 { MV64x60_PCI02MEM_ACC_CNTL_0_WIN
, MV64x60_PCI02MEM_ACC_CNTL_1_WIN
,
1151 MV64x60_PCI02MEM_ACC_CNTL_2_WIN
, MV64x60_PCI02MEM_ACC_CNTL_3_WIN
},
1152 { MV64x60_PCI12MEM_ACC_CNTL_0_WIN
, MV64x60_PCI12MEM_ACC_CNTL_1_WIN
,
1153 MV64x60_PCI12MEM_ACC_CNTL_2_WIN
, MV64x60_PCI12MEM_ACC_CNTL_3_WIN
}
1156 static u32 pci_snoop_tab
[2][4] __initdata
= {
1157 { MV64x60_PCI02MEM_SNOOP_0_WIN
, MV64x60_PCI02MEM_SNOOP_1_WIN
,
1158 MV64x60_PCI02MEM_SNOOP_2_WIN
, MV64x60_PCI02MEM_SNOOP_3_WIN
},
1159 { MV64x60_PCI12MEM_SNOOP_0_WIN
, MV64x60_PCI12MEM_SNOOP_1_WIN
,
1160 MV64x60_PCI12MEM_SNOOP_2_WIN
, MV64x60_PCI12MEM_SNOOP_3_WIN
}
1163 static u32 pci_size_tab
[2][4] __initdata
= {
1164 { MV64x60_PCI0_MEM_0_SIZE
, MV64x60_PCI0_MEM_1_SIZE
,
1165 MV64x60_PCI0_MEM_2_SIZE
, MV64x60_PCI0_MEM_3_SIZE
},
1166 { MV64x60_PCI1_MEM_0_SIZE
, MV64x60_PCI1_MEM_1_SIZE
,
1167 MV64x60_PCI1_MEM_2_SIZE
, MV64x60_PCI1_MEM_3_SIZE
}
1171 mv64x60_config_pci2mem_windows(struct mv64x60_handle
*bh
,
1172 struct pci_controller
*hose
, struct mv64x60_pci_info
*pi
,
1173 u32 bus
, u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
1178 * Set the access control, snoop, BAR size, and window base addresses.
1179 * PCI->MEM windows base addresses will match exactly what the
1180 * CPU->MEM windows are.
1182 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
1183 if (bh
->ci
->is_enabled_32bit(bh
, win
)) {
1184 mv64x60_set_64bit_window(bh
,
1185 pci_acc_tab
[bus
][i
], 0,
1186 mem_windows
[i
][0], mem_windows
[i
][1],
1187 pi
->acc_cntl_options
[i
]);
1188 bh
->ci
->enable_window_64bit(bh
, pci_acc_tab
[bus
][i
]);
1190 if (bh
->ci
->window_tab_64bit
[
1191 pci_snoop_tab
[bus
][i
]].base_lo_reg
!= 0) {
1193 mv64x60_set_64bit_window(bh
,
1194 pci_snoop_tab
[bus
][i
], 0,
1195 mem_windows
[i
][0], mem_windows
[i
][1],
1196 pi
->snoop_options
[i
]);
1197 bh
->ci
->enable_window_64bit(bh
,
1198 pci_snoop_tab
[bus
][i
]);
1201 bh
->ci
->set_pci2mem_window(hose
, bus
, i
,
1203 mv64x60_write(bh
, pci_size_tab
[bus
][i
],
1204 mv64x60_mask(mem_windows
[i
][1] - 1, 20));
1206 /* Enable the window */
1207 mv64x60_clr_bits(bh
, ((bus
== 0) ?
1208 MV64x60_PCI0_BAR_ENABLE
:
1209 MV64x60_PCI1_BAR_ENABLE
), (1 << i
));
1214 *****************************************************************************
1216 * Hose & Resource Alloc/Init Routines
1218 *****************************************************************************
1221 * mv64x60_alloc_hoses()
1223 * Allocate the PCI hose structures for the bridge's PCI buses.
1226 mv64x60_alloc_hose(struct mv64x60_handle
*bh
, u32 cfg_addr
, u32 cfg_data
,
1227 struct pci_controller
**hose
)
1229 *hose
= pcibios_alloc_controller();
1230 setup_indirect_pci_nomap(*hose
, bh
->v_base
+ cfg_addr
,
1231 bh
->v_base
+ cfg_data
);
1235 * mv64x60_config_resources()
1237 * Calculate the offsets, etc. for the hose structures to reflect all of
1238 * the address remapping that happens as you go from CPU->PCI and PCI->MEM.
1241 mv64x60_config_resources(struct pci_controller
*hose
,
1242 struct mv64x60_pci_info
*pi
, u32 io_base
)
1245 /* 2 hoses; 4 resources/hose; string <= 64 bytes */
1246 static char s
[2][4][64];
1248 if (pi
->pci_io
.size
!= 0) {
1249 sprintf(s
[hose
->index
][0], "PCI hose %d I/O Space",
1251 pci_init_resource(&hose
->io_resource
, io_base
- isa_io_base
,
1252 io_base
- isa_io_base
+ pi
->pci_io
.size
- 1,
1253 IORESOURCE_IO
, s
[hose
->index
][0]);
1254 hose
->io_space
.start
= pi
->pci_io
.pci_base_lo
;
1255 hose
->io_space
.end
= pi
->pci_io
.pci_base_lo
+ pi
->pci_io
.size
-1;
1256 hose
->io_base_phys
= pi
->pci_io
.cpu_base
;
1257 hose
->io_base_virt
= (void *)isa_io_base
;
1261 if (pi
->pci_mem
[i
].size
!= 0) {
1262 sprintf(s
[hose
->index
][i
+1], "PCI hose %d MEM Space %d",
1264 pci_init_resource(&hose
->mem_resources
[i
],
1265 pi
->pci_mem
[i
].cpu_base
,
1266 pi
->pci_mem
[i
].cpu_base
+ pi
->pci_mem
[i
].size
-1,
1267 IORESOURCE_MEM
, s
[hose
->index
][i
+1]);
1270 hose
->mem_space
.end
= pi
->pci_mem
[0].pci_base_lo
+
1271 pi
->pci_mem
[0].size
- 1;
1272 hose
->pci_mem_offset
= pi
->pci_mem
[0].cpu_base
-
1273 pi
->pci_mem
[0].pci_base_lo
;
1277 * mv64x60_config_pci_params()
1279 * Configure a hose's PCI config space parameters.
1282 mv64x60_config_pci_params(struct pci_controller
*hose
,
1283 struct mv64x60_pci_info
*pi
)
1289 devfn
= PCI_DEVFN(0,0);
1291 save_exclude
= mv64x60_pci_exclude_bridge
;
1292 mv64x60_pci_exclude_bridge
= 0;
1294 /* Set class code to indicate host bridge */
1295 u16_val
= PCI_CLASS_BRIDGE_HOST
; /* 0x0600 (host bridge) */
1296 early_write_config_word(hose
, 0, devfn
, PCI_CLASS_DEVICE
, u16_val
);
1298 /* Enable bridge to be PCI master & respond to PCI MEM cycles */
1299 early_read_config_word(hose
, 0, devfn
, PCI_COMMAND
, &u16_val
);
1300 u16_val
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_INVALIDATE
|
1301 PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| PCI_COMMAND_FAST_BACK
);
1302 u16_val
|= pi
->pci_cmd_bits
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
1303 early_write_config_word(hose
, 0, devfn
, PCI_COMMAND
, u16_val
);
1305 /* Set latency timer, cache line size, clear BIST */
1306 u16_val
= (pi
->latency_timer
<< 8) | (L1_CACHE_BYTES
>> 2);
1307 early_write_config_word(hose
, 0, devfn
, PCI_CACHE_LINE_SIZE
, u16_val
);
1309 mv64x60_pci_exclude_bridge
= save_exclude
;
1313 *****************************************************************************
1315 * PCI Related Routine
1317 *****************************************************************************
1322 * Set the bus number for the hose directly under the bridge.
1325 mv64x60_set_bus(struct mv64x60_handle
*bh
, u32 bus
, u32 child_bus
)
1327 struct pci_controller
*hose
;
1328 u32 pci_mode
, p2p_cfg
, pci_cfg_offset
, val
;
1332 pci_mode
= bh
->pci_mode_a
;
1333 p2p_cfg
= MV64x60_PCI0_P2P_CONFIG
;
1334 pci_cfg_offset
= 0x64;
1337 pci_mode
= bh
->pci_mode_b
;
1338 p2p_cfg
= MV64x60_PCI1_P2P_CONFIG
;
1339 pci_cfg_offset
= 0xe4;
1344 val
= mv64x60_read(bh
, p2p_cfg
);
1346 if (pci_mode
== MV64x60_PCIMODE_CONVENTIONAL
) {
1347 val
&= 0xe0000000; /* Force dev num to 0, turn off P2P bridge */
1348 val
|= (child_bus
<< 16) | 0xff;
1349 mv64x60_write(bh
, p2p_cfg
, val
);
1350 (void)mv64x60_read(bh
, p2p_cfg
); /* Flush FIFO */
1351 } else { /* PCI-X */
1353 * Need to use the current bus/dev number (that's in the
1354 * P2P CONFIG reg) to access the bridge's pci config space.
1356 save_exclude
= mv64x60_pci_exclude_bridge
;
1357 mv64x60_pci_exclude_bridge
= 0;
1358 early_write_config_dword(hose
, (val
& 0x00ff0000) >> 16,
1359 PCI_DEVFN(((val
& 0x1f000000) >> 24), 0),
1360 pci_cfg_offset
, child_bus
<< 8);
1361 mv64x60_pci_exclude_bridge
= save_exclude
;
1366 * mv64x60_pci_exclude_device()
1368 * This routine is used to make the bridge not appear when the
1369 * PCI subsystem is accessing PCI devices (in PCI config space).
1372 mv64x60_pci_exclude_device(u8 bus
, u8 devfn
)
1374 struct pci_controller
*hose
;
1376 hose
= pci_bus_to_hose(bus
);
1378 /* Skip slot 0 on both hoses */
1379 if ((mv64x60_pci_exclude_bridge
== 1) && (PCI_SLOT(devfn
) == 0) &&
1380 (hose
->first_busno
== bus
))
1382 return PCIBIOS_DEVICE_NOT_FOUND
;
1384 return PCIBIOS_SUCCESSFUL
;
1385 } /* mv64x60_pci_exclude_device() */
1388 *****************************************************************************
1390 * Platform Device Routines
1392 *****************************************************************************
1396 * mv64x60_pd_fixup()
1398 * Need to add the base addr of where the bridge's regs are mapped in the
1399 * physical addr space so drivers can ioremap() them.
1402 mv64x60_pd_fixup(struct mv64x60_handle
*bh
, struct platform_device
*pd_devs
[],
1408 for (i
=0; i
<entries
; i
++) {
1411 while ((r
= platform_get_resource(pd_devs
[i
],IORESOURCE_MEM
,j
))
1414 r
->start
+= bh
->p_base
;
1415 r
->end
+= bh
->p_base
;
1424 * Add the mv64x60 platform devices to the list of platform devices.
1427 mv64x60_add_pds(void)
1429 return platform_add_devices(mv64x60_pd_devs
,
1430 ARRAY_SIZE(mv64x60_pd_devs
));
1432 arch_initcall(mv64x60_add_pds
);
1435 *****************************************************************************
1437 * GT64260-Specific Routines
1439 *****************************************************************************
1442 * gt64260_translate_size()
1444 * On the GT64260, the size register is really the "top" address of the window.
1447 gt64260_translate_size(u32 base
, u32 size
, u32 num_bits
)
1449 return base
+ mv64x60_mask(size
- 1, num_bits
);
1453 * gt64260_untranslate_size()
1455 * Translate the top address of a window into a window size.
1458 gt64260_untranslate_size(u32 base
, u32 size
, u32 num_bits
)
1461 size
= size
- base
+ (1 << (32 - num_bits
));
1469 * gt64260_set_pci2mem_window()
1471 * The PCI->MEM window registers are actually in PCI config space so need
1472 * to set them by setting the correct config space BARs.
1474 static u32 gt64260_reg_addrs
[2][4] __initdata
= {
1475 { 0x10, 0x14, 0x18, 0x1c }, { 0x90, 0x94, 0x98, 0x9c }
1479 gt64260_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
, u32 window
,
1484 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window
,
1487 save_exclude
= mv64x60_pci_exclude_bridge
;
1488 mv64x60_pci_exclude_bridge
= 0;
1489 early_write_config_dword(hose
, 0, PCI_DEVFN(0, 0),
1490 gt64260_reg_addrs
[bus
][window
], mv64x60_mask(base
, 20) | 0x8);
1491 mv64x60_pci_exclude_bridge
= save_exclude
;
1495 * gt64260_set_pci2regs_window()
1497 * Set where the bridge's registers appear in PCI MEM space.
1499 static u32 gt64260_offset
[2] __initdata
= {0x20, 0xa0};
1502 gt64260_set_pci2regs_window(struct mv64x60_handle
*bh
,
1503 struct pci_controller
*hose
, u32 bus
, u32 base
)
1507 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose
->index
,
1510 save_exclude
= mv64x60_pci_exclude_bridge
;
1511 mv64x60_pci_exclude_bridge
= 0;
1512 early_write_config_dword(hose
, 0, PCI_DEVFN(0,0), gt64260_offset
[bus
],
1514 mv64x60_pci_exclude_bridge
= save_exclude
;
1518 * gt64260_is_enabled_32bit()
1520 * On a GT64260, a window is enabled iff its top address is >= to its base
1524 gt64260_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
)
1528 if ((gt64260_32bit_windows
[window
].base_reg
!= 0) &&
1529 (gt64260_32bit_windows
[window
].size_reg
!= 0) &&
1530 ((mv64x60_read(bh
, gt64260_32bit_windows
[window
].size_reg
) &
1531 ((1 << gt64260_32bit_windows
[window
].size_bits
) - 1)) >=
1532 (mv64x60_read(bh
, gt64260_32bit_windows
[window
].base_reg
) &
1533 ((1 << gt64260_32bit_windows
[window
].base_bits
) - 1))))
1541 * gt64260_enable_window_32bit()
1543 * On the GT64260, a window is enabled iff the top address is >= to the base
1544 * address of the window. Since the window has already been configured by
1545 * the time this routine is called, we have nothing to do here.
1548 gt64260_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
1550 pr_debug("enable 32bit window: %d\n", window
);
1554 * gt64260_disable_window_32bit()
1556 * On a GT64260, you disable a window by setting its top address to be less
1557 * than its base address.
1560 gt64260_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
1562 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1563 window
, gt64260_32bit_windows
[window
].base_reg
,
1564 gt64260_32bit_windows
[window
].size_reg
);
1566 if ((gt64260_32bit_windows
[window
].base_reg
!= 0) &&
1567 (gt64260_32bit_windows
[window
].size_reg
!= 0)) {
1569 /* To disable, make bottom reg higher than top reg */
1570 mv64x60_write(bh
, gt64260_32bit_windows
[window
].base_reg
,0xfff);
1571 mv64x60_write(bh
, gt64260_32bit_windows
[window
].size_reg
, 0);
1576 * gt64260_enable_window_64bit()
1578 * On the GT64260, a window is enabled iff the top address is >= to the base
1579 * address of the window. Since the window has already been configured by
1580 * the time this routine is called, we have nothing to do here.
1583 gt64260_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
1585 pr_debug("enable 64bit window: %d\n", window
);
1589 * gt64260_disable_window_64bit()
1591 * On a GT64260, you disable a window by setting its top address to be less
1592 * than its base address.
1595 gt64260_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
1597 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
1598 window
, gt64260_64bit_windows
[window
].base_lo_reg
,
1599 gt64260_64bit_windows
[window
].size_reg
);
1601 if ((gt64260_64bit_windows
[window
].base_lo_reg
!= 0) &&
1602 (gt64260_64bit_windows
[window
].size_reg
!= 0)) {
1604 /* To disable, make bottom reg higher than top reg */
1605 mv64x60_write(bh
, gt64260_64bit_windows
[window
].base_lo_reg
,
1607 mv64x60_write(bh
, gt64260_64bit_windows
[window
].base_hi_reg
, 0);
1608 mv64x60_write(bh
, gt64260_64bit_windows
[window
].size_reg
, 0);
1613 * gt64260_disable_all_windows()
1615 * The GT64260 has several windows that aren't represented in the table of
1616 * windows at the top of this file. This routine turns all of them off
1617 * except for the memory controller windows, of course.
1620 gt64260_disable_all_windows(struct mv64x60_handle
*bh
,
1621 struct mv64x60_setup_info
*si
)
1625 /* Disable 32bit windows (don't disable cpu->mem windows) */
1626 for (i
=MV64x60_CPU2DEV_0_WIN
; i
<MV64x60_32BIT_WIN_COUNT
; i
++) {
1628 preserve
= si
->window_preserve_mask_32_lo
& (1 << i
);
1630 preserve
= si
->window_preserve_mask_32_hi
& (1<<(i
-32));
1633 gt64260_disable_window_32bit(bh
, i
);
1636 /* Disable 64bit windows */
1637 for (i
=0; i
<MV64x60_64BIT_WIN_COUNT
; i
++)
1638 if (!(si
->window_preserve_mask_64
& (1<<i
)))
1639 gt64260_disable_window_64bit(bh
, i
);
1641 /* Turn off cpu protection windows not in gt64260_32bit_windows[] */
1642 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_4
, 0xfff);
1643 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_4
, 0);
1644 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_5
, 0xfff);
1645 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_5
, 0);
1646 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_6
, 0xfff);
1647 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_6
, 0);
1648 mv64x60_write(bh
, GT64260_CPU_PROT_BASE_7
, 0xfff);
1649 mv64x60_write(bh
, GT64260_CPU_PROT_SIZE_7
, 0);
1651 /* Turn off PCI->MEM access cntl wins not in gt64260_64bit_windows[] */
1652 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_4_BASE_LO
, 0xfff);
1653 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_4_BASE_HI
, 0);
1654 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_4_SIZE
, 0);
1655 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_5_BASE_LO
, 0xfff);
1656 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_5_BASE_HI
, 0);
1657 mv64x60_write(bh
, MV64x60_PCI0_ACC_CNTL_5_SIZE
, 0);
1658 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_6_BASE_LO
, 0xfff);
1659 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_6_BASE_HI
, 0);
1660 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_6_SIZE
, 0);
1661 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_7_BASE_LO
, 0xfff);
1662 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_7_BASE_HI
, 0);
1663 mv64x60_write(bh
, GT64260_PCI0_ACC_CNTL_7_SIZE
, 0);
1665 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_4_BASE_LO
, 0xfff);
1666 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_4_BASE_HI
, 0);
1667 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_4_SIZE
, 0);
1668 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_5_BASE_LO
, 0xfff);
1669 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_5_BASE_HI
, 0);
1670 mv64x60_write(bh
, MV64x60_PCI1_ACC_CNTL_5_SIZE
, 0);
1671 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_6_BASE_LO
, 0xfff);
1672 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_6_BASE_HI
, 0);
1673 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_6_SIZE
, 0);
1674 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_7_BASE_LO
, 0xfff);
1675 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_7_BASE_HI
, 0);
1676 mv64x60_write(bh
, GT64260_PCI1_ACC_CNTL_7_SIZE
, 0);
1678 /* Disable all PCI-><whatever> windows */
1679 mv64x60_set_bits(bh
, MV64x60_PCI0_BAR_ENABLE
, 0x07fffdff);
1680 mv64x60_set_bits(bh
, MV64x60_PCI1_BAR_ENABLE
, 0x07fffdff);
1683 * Some firmwares enable a bunch of intr sources
1684 * for the PCI INT output pins.
1686 mv64x60_write(bh
, GT64260_IC_CPU_INTR_MASK_LO
, 0);
1687 mv64x60_write(bh
, GT64260_IC_CPU_INTR_MASK_HI
, 0);
1688 mv64x60_write(bh
, GT64260_IC_PCI0_INTR_MASK_LO
, 0);
1689 mv64x60_write(bh
, GT64260_IC_PCI0_INTR_MASK_HI
, 0);
1690 mv64x60_write(bh
, GT64260_IC_PCI1_INTR_MASK_LO
, 0);
1691 mv64x60_write(bh
, GT64260_IC_PCI1_INTR_MASK_HI
, 0);
1692 mv64x60_write(bh
, GT64260_IC_CPU_INT_0_MASK
, 0);
1693 mv64x60_write(bh
, GT64260_IC_CPU_INT_1_MASK
, 0);
1694 mv64x60_write(bh
, GT64260_IC_CPU_INT_2_MASK
, 0);
1695 mv64x60_write(bh
, GT64260_IC_CPU_INT_3_MASK
, 0);
1699 * gt64260a_chip_specific_init()
1701 * Implement errata work arounds for the GT64260A.
1704 gt64260a_chip_specific_init(struct mv64x60_handle
*bh
,
1705 struct mv64x60_setup_info
*si
)
1707 #ifdef CONFIG_SERIAL_MPSC
1710 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1715 if (si
->pci_0
.enable_bus
)
1716 mv64x60_set_bits(bh
, MV64x60_PCI0_CMD
,
1717 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1719 if (si
->pci_1
.enable_bus
)
1720 mv64x60_set_bits(bh
, MV64x60_PCI1_CMD
,
1721 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1724 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1725 * be set if you are using cache coherency.
1727 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1728 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1729 if ((mv64x60_read(bh
, MV64x60_CPU_MODE
) & 0xf0) == 0x40)
1730 mv64x60_set_bits(bh
, GT64260_SDRAM_CONFIG
, (1<<26));
1732 save_exclude
= mv64x60_pci_exclude_bridge
;
1733 mv64x60_pci_exclude_bridge
= 0;
1734 if (si
->pci_0
.enable_bus
) {
1735 early_read_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1737 val
|= PCI_COMMAND_INVALIDATE
;
1738 early_write_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1742 if (si
->pci_1
.enable_bus
) {
1743 early_read_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1745 val
|= PCI_COMMAND_INVALIDATE
;
1746 early_write_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1749 mv64x60_pci_exclude_bridge
= save_exclude
;
1752 /* Disable buffer/descriptor snooping */
1753 mv64x60_clr_bits(bh
, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1754 mv64x60_clr_bits(bh
, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1756 #ifdef CONFIG_SERIAL_MPSC
1757 mv64x60_mpsc0_pdata
.mirror_regs
= 1;
1758 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
1759 mv64x60_mpsc1_pdata
.mirror_regs
= 1;
1760 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
1762 if ((r
= platform_get_resource(&mpsc1_device
, IORESOURCE_IRQ
, 0))
1764 r
->start
= MV64x60_IRQ_SDMA_0
;
1765 r
->end
= MV64x60_IRQ_SDMA_0
;
1771 * gt64260b_chip_specific_init()
1773 * Implement errata work arounds for the GT64260B.
1776 gt64260b_chip_specific_init(struct mv64x60_handle
*bh
,
1777 struct mv64x60_setup_info
*si
)
1779 #ifdef CONFIG_SERIAL_MPSC
1782 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1787 if (si
->pci_0
.enable_bus
)
1788 mv64x60_set_bits(bh
, MV64x60_PCI0_CMD
,
1789 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1791 if (si
->pci_1
.enable_bus
)
1792 mv64x60_set_bits(bh
, MV64x60_PCI1_CMD
,
1793 ((1<<4) | (1<<5) | (1<<9) | (1<<13)));
1796 * Dave Wilhardt found that bit 4 in the PCI Command registers must
1797 * be set if you are using cache coherency.
1799 #if !defined(CONFIG_NOT_COHERENT_CACHE)
1800 mv64x60_set_bits(bh
, GT64260_CPU_WB_PRIORITY_BUFFER_DEPTH
, 0xf);
1802 /* Res #MEM-4 -- cpu read buffer to buffer 1 */
1803 if ((mv64x60_read(bh
, MV64x60_CPU_MODE
) & 0xf0) == 0x40)
1804 mv64x60_set_bits(bh
, GT64260_SDRAM_CONFIG
, (1<<26));
1806 save_exclude
= mv64x60_pci_exclude_bridge
;
1807 mv64x60_pci_exclude_bridge
= 0;
1808 if (si
->pci_0
.enable_bus
) {
1809 early_read_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1811 val
|= PCI_COMMAND_INVALIDATE
;
1812 early_write_config_dword(bh
->hose_a
, 0, PCI_DEVFN(0,0),
1816 if (si
->pci_1
.enable_bus
) {
1817 early_read_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1819 val
|= PCI_COMMAND_INVALIDATE
;
1820 early_write_config_dword(bh
->hose_b
, 0, PCI_DEVFN(0,0),
1823 mv64x60_pci_exclude_bridge
= save_exclude
;
1826 /* Disable buffer/descriptor snooping */
1827 mv64x60_clr_bits(bh
, 0xf280, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1828 mv64x60_clr_bits(bh
, 0xf2c0, (1<< 6) | (1<<14) | (1<<22) | (1<<30));
1830 #ifdef CONFIG_SERIAL_MPSC
1832 * The 64260B is not supposed to have the bug where the MPSC & ENET
1833 * can't access cache coherent regions. However, testing has shown
1834 * that the MPSC, at least, still has this bug.
1836 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
1837 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
1839 if ((r
= platform_get_resource(&mpsc1_device
, IORESOURCE_IRQ
, 0))
1841 r
->start
= MV64x60_IRQ_SDMA_0
;
1842 r
->end
= MV64x60_IRQ_SDMA_0
;
1848 *****************************************************************************
1850 * MV64360-Specific Routines
1852 *****************************************************************************
1855 * mv64360_translate_size()
1857 * On the MV64360, the size register is set similar to the size you get
1858 * from a pci config space BAR register. That is, programmed from LSB to MSB
1859 * as a sequence of 1's followed by a sequence of 0's. IOW, "size -1" with the
1860 * assumption that the size is a power of 2.
1863 mv64360_translate_size(u32 base_addr
, u32 size
, u32 num_bits
)
1865 return mv64x60_mask(size
- 1, num_bits
);
1869 * mv64360_untranslate_size()
1871 * Translate the size register value of a window into a window size.
1874 mv64360_untranslate_size(u32 base_addr
, u32 size
, u32 num_bits
)
1877 size
>>= (32 - num_bits
);
1879 size
<<= (32 - num_bits
);
1886 * mv64360_set_pci2mem_window()
1888 * The PCI->MEM window registers are actually in PCI config space so need
1889 * to set them by setting the correct config space BARs.
1895 } static mv64360_reg_addrs
[2][4] __initdata
= {
1896 {{ 0, 0x14, 0x10 }, { 0, 0x1c, 0x18 },
1897 { 1, 0x14, 0x10 }, { 1, 0x1c, 0x18 }},
1898 {{ 0, 0x94, 0x90 }, { 0, 0x9c, 0x98 },
1899 { 1, 0x94, 0x90 }, { 1, 0x9c, 0x98 }}
1903 mv64360_set_pci2mem_window(struct pci_controller
*hose
, u32 bus
, u32 window
,
1908 pr_debug("set pci->mem window: %d, hose: %d, base: 0x%x\n", window
,
1911 save_exclude
= mv64x60_pci_exclude_bridge
;
1912 mv64x60_pci_exclude_bridge
= 0;
1913 early_write_config_dword(hose
, 0,
1914 PCI_DEVFN(0, mv64360_reg_addrs
[bus
][window
].fcn
),
1915 mv64360_reg_addrs
[bus
][window
].base_hi_bar
, 0);
1916 early_write_config_dword(hose
, 0,
1917 PCI_DEVFN(0, mv64360_reg_addrs
[bus
][window
].fcn
),
1918 mv64360_reg_addrs
[bus
][window
].base_lo_bar
,
1919 mv64x60_mask(base
,20) | 0xc);
1920 mv64x60_pci_exclude_bridge
= save_exclude
;
1924 * mv64360_set_pci2regs_window()
1926 * Set where the bridge's registers appear in PCI MEM space.
1928 static u32 mv64360_offset
[2][2] __initdata
= {{0x20, 0x24}, {0xa0, 0xa4}};
1931 mv64360_set_pci2regs_window(struct mv64x60_handle
*bh
,
1932 struct pci_controller
*hose
, u32 bus
, u32 base
)
1936 pr_debug("set pci->internal regs hose: %d, base: 0x%x\n", hose
->index
,
1939 save_exclude
= mv64x60_pci_exclude_bridge
;
1940 mv64x60_pci_exclude_bridge
= 0;
1941 early_write_config_dword(hose
, 0, PCI_DEVFN(0,0),
1942 mv64360_offset
[bus
][0], (base
<< 16));
1943 early_write_config_dword(hose
, 0, PCI_DEVFN(0,0),
1944 mv64360_offset
[bus
][1], 0);
1945 mv64x60_pci_exclude_bridge
= save_exclude
;
1949 * mv64360_is_enabled_32bit()
1951 * On a MV64360, a window is enabled by either clearing a bit in the
1952 * CPU BAR Enable reg or setting a bit in the window's base reg.
1953 * Note that this doesn't work for windows on the PCI slave side but we don't
1954 * check those so its okay.
1957 mv64360_is_enabled_32bit(struct mv64x60_handle
*bh
, u32 window
)
1961 if (((mv64360_32bit_windows
[window
].base_reg
!= 0) &&
1962 (mv64360_32bit_windows
[window
].size_reg
!= 0)) ||
1963 (window
== MV64x60_CPU2SRAM_WIN
)) {
1965 extra
= mv64360_32bit_windows
[window
].extra
;
1967 switch (extra
& MV64x60_EXTRA_MASK
) {
1968 case MV64x60_EXTRA_CPUWIN_ENAB
:
1969 rc
= (mv64x60_read(bh
, MV64360_CPU_BAR_ENABLE
) &
1970 (1 << (extra
& 0x1f))) == 0;
1973 case MV64x60_EXTRA_CPUPROT_ENAB
:
1974 rc
= (mv64x60_read(bh
,
1975 mv64360_32bit_windows
[window
].base_reg
) &
1976 (1 << (extra
& 0x1f))) != 0;
1979 case MV64x60_EXTRA_ENET_ENAB
:
1980 rc
= (mv64x60_read(bh
, MV64360_ENET2MEM_BAR_ENABLE
) &
1981 (1 << (extra
& 0x7))) == 0;
1984 case MV64x60_EXTRA_MPSC_ENAB
:
1985 rc
= (mv64x60_read(bh
, MV64360_MPSC2MEM_BAR_ENABLE
) &
1986 (1 << (extra
& 0x3))) == 0;
1989 case MV64x60_EXTRA_IDMA_ENAB
:
1990 rc
= (mv64x60_read(bh
, MV64360_IDMA2MEM_BAR_ENABLE
) &
1991 (1 << (extra
& 0x7))) == 0;
1995 printk(KERN_ERR
"mv64360_is_enabled: %s\n",
1996 "32bit table corrupted");
2004 * mv64360_enable_window_32bit()
2006 * On a MV64360, a window is enabled by either clearing a bit in the
2007 * CPU BAR Enable reg or setting a bit in the window's base reg.
2010 mv64360_enable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
2014 pr_debug("enable 32bit window: %d\n", window
);
2016 if (((mv64360_32bit_windows
[window
].base_reg
!= 0) &&
2017 (mv64360_32bit_windows
[window
].size_reg
!= 0)) ||
2018 (window
== MV64x60_CPU2SRAM_WIN
)) {
2020 extra
= mv64360_32bit_windows
[window
].extra
;
2022 switch (extra
& MV64x60_EXTRA_MASK
) {
2023 case MV64x60_EXTRA_CPUWIN_ENAB
:
2024 mv64x60_clr_bits(bh
, MV64360_CPU_BAR_ENABLE
,
2025 (1 << (extra
& 0x1f)));
2028 case MV64x60_EXTRA_CPUPROT_ENAB
:
2029 mv64x60_set_bits(bh
,
2030 mv64360_32bit_windows
[window
].base_reg
,
2031 (1 << (extra
& 0x1f)));
2034 case MV64x60_EXTRA_ENET_ENAB
:
2035 mv64x60_clr_bits(bh
, MV64360_ENET2MEM_BAR_ENABLE
,
2036 (1 << (extra
& 0x7)));
2039 case MV64x60_EXTRA_MPSC_ENAB
:
2040 mv64x60_clr_bits(bh
, MV64360_MPSC2MEM_BAR_ENABLE
,
2041 (1 << (extra
& 0x3)));
2044 case MV64x60_EXTRA_IDMA_ENAB
:
2045 mv64x60_clr_bits(bh
, MV64360_IDMA2MEM_BAR_ENABLE
,
2046 (1 << (extra
& 0x7)));
2050 printk(KERN_ERR
"mv64360_enable: %s\n",
2051 "32bit table corrupted");
2057 * mv64360_disable_window_32bit()
2059 * On a MV64360, a window is disabled by either setting a bit in the
2060 * CPU BAR Enable reg or clearing a bit in the window's base reg.
2063 mv64360_disable_window_32bit(struct mv64x60_handle
*bh
, u32 window
)
2067 pr_debug("disable 32bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2068 window
, mv64360_32bit_windows
[window
].base_reg
,
2069 mv64360_32bit_windows
[window
].size_reg
);
2071 if (((mv64360_32bit_windows
[window
].base_reg
!= 0) &&
2072 (mv64360_32bit_windows
[window
].size_reg
!= 0)) ||
2073 (window
== MV64x60_CPU2SRAM_WIN
)) {
2075 extra
= mv64360_32bit_windows
[window
].extra
;
2077 switch (extra
& MV64x60_EXTRA_MASK
) {
2078 case MV64x60_EXTRA_CPUWIN_ENAB
:
2079 mv64x60_set_bits(bh
, MV64360_CPU_BAR_ENABLE
,
2080 (1 << (extra
& 0x1f)));
2083 case MV64x60_EXTRA_CPUPROT_ENAB
:
2084 mv64x60_clr_bits(bh
,
2085 mv64360_32bit_windows
[window
].base_reg
,
2086 (1 << (extra
& 0x1f)));
2089 case MV64x60_EXTRA_ENET_ENAB
:
2090 mv64x60_set_bits(bh
, MV64360_ENET2MEM_BAR_ENABLE
,
2091 (1 << (extra
& 0x7)));
2094 case MV64x60_EXTRA_MPSC_ENAB
:
2095 mv64x60_set_bits(bh
, MV64360_MPSC2MEM_BAR_ENABLE
,
2096 (1 << (extra
& 0x3)));
2099 case MV64x60_EXTRA_IDMA_ENAB
:
2100 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_BAR_ENABLE
,
2101 (1 << (extra
& 0x7)));
2105 printk(KERN_ERR
"mv64360_disable: %s\n",
2106 "32bit table corrupted");
2112 * mv64360_enable_window_64bit()
2114 * On the MV64360, a 64-bit window is enabled by setting a bit in the window's
2118 mv64360_enable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
2120 pr_debug("enable 64bit window: %d\n", window
);
2122 if ((mv64360_64bit_windows
[window
].base_lo_reg
!= 0) &&
2123 (mv64360_64bit_windows
[window
].size_reg
!= 0)) {
2125 if ((mv64360_64bit_windows
[window
].extra
& MV64x60_EXTRA_MASK
)
2126 == MV64x60_EXTRA_PCIACC_ENAB
)
2127 mv64x60_set_bits(bh
,
2128 mv64360_64bit_windows
[window
].base_lo_reg
,
2129 (1 << (mv64360_64bit_windows
[window
].extra
&
2132 printk(KERN_ERR
"mv64360_enable: %s\n",
2133 "64bit table corrupted");
2138 * mv64360_disable_window_64bit()
2140 * On a MV64360, a 64-bit window is disabled by clearing a bit in the window's
2144 mv64360_disable_window_64bit(struct mv64x60_handle
*bh
, u32 window
)
2146 pr_debug("disable 64bit window: %d, base_reg: 0x%x, size_reg: 0x%x\n",
2147 window
, mv64360_64bit_windows
[window
].base_lo_reg
,
2148 mv64360_64bit_windows
[window
].size_reg
);
2150 if ((mv64360_64bit_windows
[window
].base_lo_reg
!= 0) &&
2151 (mv64360_64bit_windows
[window
].size_reg
!= 0)) {
2152 if ((mv64360_64bit_windows
[window
].extra
& MV64x60_EXTRA_MASK
)
2153 == MV64x60_EXTRA_PCIACC_ENAB
)
2154 mv64x60_clr_bits(bh
,
2155 mv64360_64bit_windows
[window
].base_lo_reg
,
2156 (1 << (mv64360_64bit_windows
[window
].extra
&
2159 printk(KERN_ERR
"mv64360_disable: %s\n",
2160 "64bit table corrupted");
2165 * mv64360_disable_all_windows()
2167 * The MV64360 has a few windows that aren't represented in the table of
2168 * windows at the top of this file. This routine turns all of them off
2169 * except for the memory controller windows, of course.
2172 mv64360_disable_all_windows(struct mv64x60_handle
*bh
,
2173 struct mv64x60_setup_info
*si
)
2177 /* Disable 32bit windows (don't disable cpu->mem windows) */
2178 for (i
=MV64x60_CPU2DEV_0_WIN
; i
<MV64x60_32BIT_WIN_COUNT
; i
++) {
2180 preserve
= si
->window_preserve_mask_32_lo
& (1 << i
);
2182 preserve
= si
->window_preserve_mask_32_hi
& (1<<(i
-32));
2185 mv64360_disable_window_32bit(bh
, i
);
2188 /* Disable 64bit windows */
2189 for (i
=0; i
<MV64x60_64BIT_WIN_COUNT
; i
++)
2190 if (!(si
->window_preserve_mask_64
& (1<<i
)))
2191 mv64360_disable_window_64bit(bh
, i
);
2193 /* Turn off PCI->MEM access cntl wins not in mv64360_64bit_windows[] */
2194 mv64x60_clr_bits(bh
, MV64x60_PCI0_ACC_CNTL_4_BASE_LO
, 0);
2195 mv64x60_clr_bits(bh
, MV64x60_PCI0_ACC_CNTL_5_BASE_LO
, 0);
2196 mv64x60_clr_bits(bh
, MV64x60_PCI1_ACC_CNTL_4_BASE_LO
, 0);
2197 mv64x60_clr_bits(bh
, MV64x60_PCI1_ACC_CNTL_5_BASE_LO
, 0);
2199 /* Disable all PCI-><whatever> windows */
2200 mv64x60_set_bits(bh
, MV64x60_PCI0_BAR_ENABLE
, 0x0000f9ff);
2201 mv64x60_set_bits(bh
, MV64x60_PCI1_BAR_ENABLE
, 0x0000f9ff);
2205 * mv64360_config_io2mem_windows()
2207 * ENET, MPSC, and IDMA ctlrs on the MV64[34]60 have separate windows that
2208 * must be set up so that the respective ctlr can access system memory.
2210 static u32 enet_tab
[MV64x60_CPU2MEM_WINDOWS
] __initdata
= {
2211 MV64x60_ENET2MEM_0_WIN
, MV64x60_ENET2MEM_1_WIN
,
2212 MV64x60_ENET2MEM_2_WIN
, MV64x60_ENET2MEM_3_WIN
,
2215 static u32 mpsc_tab
[MV64x60_CPU2MEM_WINDOWS
] __initdata
= {
2216 MV64x60_MPSC2MEM_0_WIN
, MV64x60_MPSC2MEM_1_WIN
,
2217 MV64x60_MPSC2MEM_2_WIN
, MV64x60_MPSC2MEM_3_WIN
,
2220 static u32 idma_tab
[MV64x60_CPU2MEM_WINDOWS
] __initdata
= {
2221 MV64x60_IDMA2MEM_0_WIN
, MV64x60_IDMA2MEM_1_WIN
,
2222 MV64x60_IDMA2MEM_2_WIN
, MV64x60_IDMA2MEM_3_WIN
,
2225 static u32 dram_selects
[MV64x60_CPU2MEM_WINDOWS
] __initdata
=
2226 { 0xe, 0xd, 0xb, 0x7 };
2229 mv64360_config_io2mem_windows(struct mv64x60_handle
*bh
,
2230 struct mv64x60_setup_info
*si
,
2231 u32 mem_windows
[MV64x60_CPU2MEM_WINDOWS
][2])
2235 pr_debug("config_io2regs_windows: enet, mpsc, idma -> bridge regs\n");
2237 mv64x60_write(bh
, MV64360_ENET2MEM_ACC_PROT_0
, 0);
2238 mv64x60_write(bh
, MV64360_ENET2MEM_ACC_PROT_1
, 0);
2239 mv64x60_write(bh
, MV64360_ENET2MEM_ACC_PROT_2
, 0);
2241 mv64x60_write(bh
, MV64360_MPSC2MEM_ACC_PROT_0
, 0);
2242 mv64x60_write(bh
, MV64360_MPSC2MEM_ACC_PROT_1
, 0);
2244 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_0
, 0);
2245 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_1
, 0);
2246 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_2
, 0);
2247 mv64x60_write(bh
, MV64360_IDMA2MEM_ACC_PROT_3
, 0);
2249 /* Assume that mem ctlr has no more windows than embedded I/O ctlr */
2250 for (win
=MV64x60_CPU2MEM_0_WIN
,i
=0;win
<=MV64x60_CPU2MEM_3_WIN
;win
++,i
++)
2251 if (bh
->ci
->is_enabled_32bit(bh
, win
)) {
2252 mv64x60_set_32bit_window(bh
, enet_tab
[i
],
2253 mem_windows
[i
][0], mem_windows
[i
][1],
2254 (dram_selects
[i
] << 8) |
2255 (si
->enet_options
[i
] & 0x3000));
2256 bh
->ci
->enable_window_32bit(bh
, enet_tab
[i
]);
2258 /* Give enet r/w access to memory region */
2259 mv64x60_set_bits(bh
, MV64360_ENET2MEM_ACC_PROT_0
,
2261 mv64x60_set_bits(bh
, MV64360_ENET2MEM_ACC_PROT_1
,
2263 mv64x60_set_bits(bh
, MV64360_ENET2MEM_ACC_PROT_2
,
2266 mv64x60_set_32bit_window(bh
, mpsc_tab
[i
],
2267 mem_windows
[i
][0], mem_windows
[i
][1],
2268 (dram_selects
[i
] << 8) |
2269 (si
->mpsc_options
[i
] & 0x3000));
2270 bh
->ci
->enable_window_32bit(bh
, mpsc_tab
[i
]);
2272 /* Give mpsc r/w access to memory region */
2273 mv64x60_set_bits(bh
, MV64360_MPSC2MEM_ACC_PROT_0
,
2275 mv64x60_set_bits(bh
, MV64360_MPSC2MEM_ACC_PROT_1
,
2278 mv64x60_set_32bit_window(bh
, idma_tab
[i
],
2279 mem_windows
[i
][0], mem_windows
[i
][1],
2280 (dram_selects
[i
] << 8) |
2281 (si
->idma_options
[i
] & 0x3000));
2282 bh
->ci
->enable_window_32bit(bh
, idma_tab
[i
]);
2284 /* Give idma r/w access to memory region */
2285 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_0
,
2287 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_1
,
2289 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_2
,
2291 mv64x60_set_bits(bh
, MV64360_IDMA2MEM_ACC_PROT_3
,
2297 * mv64360_set_mpsc2regs_window()
2299 * MPSC has a window to the bridge's internal registers. Call this routine
2300 * to change that window so it doesn't conflict with the windows mapping the
2301 * mpsc to system memory.
2304 mv64360_set_mpsc2regs_window(struct mv64x60_handle
*bh
, u32 base
)
2306 pr_debug("set mpsc->internal regs, base: 0x%x\n", base
);
2307 mv64x60_write(bh
, MV64360_MPSC2REGS_BASE
, base
& 0xffff0000);
2311 * mv64360_chip_specific_init()
2313 * Implement errata work arounds for the MV64360.
2316 mv64360_chip_specific_init(struct mv64x60_handle
*bh
,
2317 struct mv64x60_setup_info
*si
)
2319 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2320 mv64x60_set_bits(bh
, MV64360_D_UNIT_CONTROL_HIGH
, (1<<24));
2322 #ifdef CONFIG_SERIAL_MPSC
2323 mv64x60_mpsc0_pdata
.brg_can_tune
= 1;
2324 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
2325 mv64x60_mpsc1_pdata
.brg_can_tune
= 1;
2326 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
2331 * mv64460_chip_specific_init()
2333 * Implement errata work arounds for the MV64460.
2336 mv64460_chip_specific_init(struct mv64x60_handle
*bh
,
2337 struct mv64x60_setup_info
*si
)
2339 #if !defined(CONFIG_NOT_COHERENT_CACHE)
2340 mv64x60_set_bits(bh
, MV64360_D_UNIT_CONTROL_HIGH
, (1<<24) | (1<<25));
2341 mv64x60_set_bits(bh
, MV64460_D_UNIT_MMASK
, (1<<1) | (1<<4));
2343 #ifdef CONFIG_SERIAL_MPSC
2344 mv64x60_mpsc0_pdata
.brg_can_tune
= 1;
2345 mv64x60_mpsc0_pdata
.cache_mgmt
= 1;
2346 mv64x60_mpsc1_pdata
.brg_can_tune
= 1;
2347 mv64x60_mpsc1_pdata
.cache_mgmt
= 1;
2352 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
2353 /* Export the hotswap register via sysfs for enum event monitoring */
2354 #define VAL_LEN_MAX 11 /* 32-bit hex or dec stringified number + '\n' */
2356 DECLARE_MUTEX(mv64xxx_hs_lock
);
2359 mv64xxx_hs_reg_read(struct kobject
*kobj
, char *buf
, loff_t off
, size_t count
)
2366 if (count
< VAL_LEN_MAX
)
2369 if (down_interruptible(&mv64xxx_hs_lock
))
2370 return -ERESTARTSYS
;
2371 save_exclude
= mv64x60_pci_exclude_bridge
;
2372 mv64x60_pci_exclude_bridge
= 0;
2373 early_read_config_dword(&sysfs_hose_a
, 0, PCI_DEVFN(0, 0),
2374 MV64360_PCICFG_CPCI_HOTSWAP
, &v
);
2375 mv64x60_pci_exclude_bridge
= save_exclude
;
2376 up(&mv64xxx_hs_lock
);
2378 return sprintf(buf
, "0x%08x\n", v
);
2382 mv64xxx_hs_reg_write(struct kobject
*kobj
, char *buf
, loff_t off
, size_t count
)
2392 if (sscanf(buf
, "%i", &v
) == 1) {
2393 if (down_interruptible(&mv64xxx_hs_lock
))
2394 return -ERESTARTSYS
;
2395 save_exclude
= mv64x60_pci_exclude_bridge
;
2396 mv64x60_pci_exclude_bridge
= 0;
2397 early_write_config_dword(&sysfs_hose_a
, 0, PCI_DEVFN(0, 0),
2398 MV64360_PCICFG_CPCI_HOTSWAP
, v
);
2399 mv64x60_pci_exclude_bridge
= save_exclude
;
2400 up(&mv64xxx_hs_lock
);
2408 static struct bin_attribute mv64xxx_hs_reg_attr
= { /* Hotswap register */
2411 .mode
= S_IRUGO
| S_IWUSR
,
2412 .owner
= THIS_MODULE
,
2414 .size
= VAL_LEN_MAX
,
2415 .read
= mv64xxx_hs_reg_read
,
2416 .write
= mv64xxx_hs_reg_write
,
2419 /* Provide sysfs file indicating if this platform supports the hs_reg */
2421 mv64xxx_hs_reg_valid_show(struct device
*dev
, struct device_attribute
*attr
,
2424 struct platform_device
*pdev
;
2425 struct mv64xxx_pdata
*pdp
;
2428 pdev
= container_of(dev
, struct platform_device
, dev
);
2429 pdp
= (struct mv64xxx_pdata
*)pdev
->dev
.platform_data
;
2431 if (down_interruptible(&mv64xxx_hs_lock
))
2432 return -ERESTARTSYS
;
2433 v
= pdp
->hs_reg_valid
;
2434 up(&mv64xxx_hs_lock
);
2436 return sprintf(buf
, "%i\n", v
);
2438 static DEVICE_ATTR(hs_reg_valid
, S_IRUGO
, mv64xxx_hs_reg_valid_show
, NULL
);
2441 mv64xxx_sysfs_init(void)
2443 sysfs_create_bin_file(&mv64xxx_device
.dev
.kobj
, &mv64xxx_hs_reg_attr
);
2444 sysfs_create_file(&mv64xxx_device
.dev
.kobj
,&dev_attr_hs_reg_valid
.attr
);
2447 subsys_initcall(mv64xxx_sysfs_init
);