[NETFILTER]: PPTP conntrack: simplify expectation handling
[hh.org.git] / arch / v850 / kernel / anna.c
blob40892d3e3c247ea2dbada930d4f65b5675f05993
1 /*
2 * arch/v850/kernel/anna.c -- Anna V850E2 evaluation chip/board
4 * Copyright (C) 2002,03 NEC Electronics Corporation
5 * Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
11 * Written by Miles Bader <miles@gnu.org>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/bootmem.h>
18 #include <linux/major.h>
19 #include <linux/irq.h>
21 #include <asm/machdep.h>
22 #include <asm/atomic.h>
23 #include <asm/page.h>
24 #include <asm/v850e_timer_d.h>
25 #include <asm/v850e_uart.h>
27 #include "mach.h"
30 /* SRAM and SDRAM are vaguely contiguous (with a big hole in between; see
31 mach_reserve_bootmem for details); use both as one big area. */
32 #define RAM_START SRAM_ADDR
33 #define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
35 /* The bits of this port are connected to an 8-LED bar-graph. */
36 #define LEDS_PORT 0
39 static void anna_led_tick (void);
42 void __init mach_early_init (void)
44 ANNA_ILBEN = 0;
46 V850E2_CSC(0) = 0x402F;
47 V850E2_CSC(1) = 0x4000;
48 V850E2_BPC = 0;
49 V850E2_BSC = 0xAAAA;
50 V850E2_BEC = 0;
52 #if 0
53 V850E2_BHC = 0xFFFF; /* icache all memory, dcache all */
54 #else
55 V850E2_BHC = 0; /* cache no memory */
56 #endif
57 V850E2_BCT(0) = 0xB088;
58 V850E2_BCT(1) = 0x0008;
59 V850E2_DWC(0) = 0x0027;
60 V850E2_DWC(1) = 0;
61 V850E2_BCC = 0x0006;
62 V850E2_ASC = 0;
63 V850E2_LBS = 0x0089;
64 V850E2_SCR(3) = 0x21A9;
65 V850E2_RFS(3) = 0x8121;
67 v850e_intc_disable_irqs ();
70 void __init mach_setup (char **cmdline)
72 ANNA_PORT_PM (LEDS_PORT) = 0; /* Make all LED pins output pins. */
73 mach_tick = anna_led_tick;
76 void __init mach_get_physical_ram (unsigned long *ram_start,
77 unsigned long *ram_len)
79 *ram_start = RAM_START;
80 *ram_len = RAM_END - RAM_START;
83 void __init mach_reserve_bootmem ()
85 /* The space between SRAM and SDRAM is filled with duplicate
86 images of SRAM. Prevent the kernel from using them. */
87 reserve_bootmem (SRAM_ADDR + SRAM_SIZE,
88 SDRAM_ADDR - (SRAM_ADDR + SRAM_SIZE));
91 void mach_gettimeofday (struct timespec *tv)
93 tv->tv_sec = 0;
94 tv->tv_nsec = 0;
97 void __init mach_sched_init (struct irqaction *timer_action)
99 /* Start hardware timer. */
100 v850e_timer_d_configure (0, HZ);
101 /* Install timer interrupt handler. */
102 setup_irq (IRQ_INTCMD(0), timer_action);
105 static struct v850e_intc_irq_init irq_inits[] = {
106 { "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
107 { "PIN", IRQ_INTP(0), IRQ_INTP_NUM, 1, 4 },
108 { "CCC", IRQ_INTCCC(0), IRQ_INTCCC_NUM, 1, 5 },
109 { "CMD", IRQ_INTCMD(0), IRQ_INTCMD_NUM, 1, 5 },
110 { "DMA", IRQ_INTDMA(0), IRQ_INTDMA_NUM, 1, 2 },
111 { "DMXER", IRQ_INTDMXER,1, 1, 2 },
112 { "SRE", IRQ_INTSRE(0), IRQ_INTSRE_NUM, 3, 3 },
113 { "SR", IRQ_INTSR(0), IRQ_INTSR_NUM, 3, 4 },
114 { "ST", IRQ_INTST(0), IRQ_INTST_NUM, 3, 5 },
115 { 0 }
117 #define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)
119 static struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
121 void __init mach_init_irqs (void)
123 v850e_intc_init_irq_types (irq_inits, hw_itypes);
126 void machine_restart (char *__unused)
128 #ifdef CONFIG_RESET_GUARD
129 disable_reset_guard ();
130 #endif
131 asm ("jmp r0"); /* Jump to the reset vector. */
134 void machine_halt (void)
136 #ifdef CONFIG_RESET_GUARD
137 disable_reset_guard ();
138 #endif
139 local_irq_disable (); /* Ignore all interrupts. */
140 ANNA_PORT_IO(LEDS_PORT) = 0xAA; /* Note that we halted. */
141 for (;;)
142 asm ("halt; nop; nop; nop; nop; nop");
145 void machine_power_off (void)
147 machine_halt ();
150 /* Called before configuring an on-chip UART. */
151 void anna_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud)
153 /* The Anna connects some general-purpose I/O pins on the CPU to
154 the RTS/CTS lines of UART 1's serial connection. I/O pins P07
155 and P37 are RTS and CTS respectively. */
156 if (chan == 1) {
157 ANNA_PORT_PM(0) &= ~0x80; /* P07 in output mode */
158 ANNA_PORT_PM(3) |= 0x80; /* P37 in input mode */
162 /* Minimum and maximum bounds for the moving upper LED boundary in the
163 clock tick display. We can't use the last bit because it's used for
164 UART0's CTS output. */
165 #define MIN_MAX_POS 0
166 #define MAX_MAX_POS 6
168 /* There are MAX_MAX_POS^2 - MIN_MAX_POS^2 cycles in the animation, so if
169 we pick 6 and 0 as above, we get 49 cycles, which is when divided into
170 the standard 100 value for HZ, gives us an almost 1s total time. */
171 #define TICKS_PER_FRAME \
172 (HZ / (MAX_MAX_POS * MAX_MAX_POS - MIN_MAX_POS * MIN_MAX_POS))
174 static void anna_led_tick ()
176 static unsigned counter = 0;
178 if (++counter == TICKS_PER_FRAME) {
179 static int pos = 0, max_pos = MAX_MAX_POS, dir = 1;
181 if (dir > 0 && pos == max_pos) {
182 dir = -1;
183 if (max_pos == MIN_MAX_POS)
184 max_pos = MAX_MAX_POS;
185 else
186 max_pos--;
187 } else {
188 if (dir < 0 && pos == 0)
189 dir = 1;
191 if (pos + dir <= max_pos) {
192 /* Each bit of port 0 has a LED. */
193 clear_bit (pos, &ANNA_PORT_IO(LEDS_PORT));
194 pos += dir;
195 set_bit (pos, &ANNA_PORT_IO(LEDS_PORT));
199 counter = 0;