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[NETFILTER]: PPTP conntrack: simplify expectation handling
[hh.org.git] / arch / x86_64 / kernel / mpparse.c
bloba1ab4197f8a11594e59c57b20c67d5a6511c6cfa
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
25
26 #include <asm/smp.h>
27 #include <asm/mtrr.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
32 #include <asm/acpi.h>
33
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
37
38 int acpi_found_madt;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 unsigned char apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47
48 static int mp_current_pci_id = 0;
49 /* I/O APIC entries */
50 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
51
52 /* # of MP IRQ source entries */
53 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
54
55 /* MP IRQ source entries */
56 int mp_irq_entries;
57
58 int nr_ioapics;
59 int pic_mode;
60 unsigned long mp_lapic_addr = 0;
61
62
63
64 /* Processor that is doing the boot up */
65 unsigned int boot_cpu_id = -1U;
66 /* Internal processor count */
67 unsigned int num_processors __initdata = 0;
68
69 unsigned disabled_cpus __initdata;
70
71 /* Bitmask of physically existing CPUs */
72 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
73
74 /* ACPI MADT entry parsing functions */
75 #ifdef CONFIG_ACPI
76 extern struct acpi_boot_flags acpi_boot;
77 #ifdef CONFIG_X86_LOCAL_APIC
78 extern int acpi_parse_lapic (acpi_table_entry_header *header);
79 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
80 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
81 #endif /*CONFIG_X86_LOCAL_APIC*/
82 #ifdef CONFIG_X86_IO_APIC
83 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
84 #endif /*CONFIG_X86_IO_APIC*/
85 #endif /*CONFIG_ACPI*/
86
87 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
88
89
90 /*
91 * Intel MP BIOS table parsing routines:
92 */
93
94 /*
95 * Checksum an MP configuration block.
96 */
97
98 static int __init mpf_checksum(unsigned char *mp, int len)
99 {
100 int sum = 0;
101
102 while (len--)
103 sum += *mp++;
104
105 return sum & 0xFF;
106 }
107
108 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
109 {
110 int cpu;
111 unsigned char ver;
112 cpumask_t tmp_map;
113
114 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
115 disabled_cpus++;
116 return;
117 }
118
119 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
120 m->mpc_apicid,
121 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
122 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
123 m->mpc_apicver);
124
125 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
126 Dprintk(" Bootup CPU\n");
127 boot_cpu_id = m->mpc_apicid;
128 }
129 if (num_processors >= NR_CPUS) {
130 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
131 " Processor ignored.\n", NR_CPUS);
132 return;
133 }
134
135 num_processors++;
136 cpus_complement(tmp_map, cpu_present_map);
137 cpu = first_cpu(tmp_map);
138
139 #if MAX_APICS < 255
140 if ((int)m->mpc_apicid > MAX_APICS) {
141 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
142 m->mpc_apicid, MAX_APICS);
143 return;
144 }
145 #endif
146 ver = m->mpc_apicver;
147
148 physid_set(m->mpc_apicid, phys_cpu_present_map);
149 /*
150 * Validate version
151 */
152 if (ver == 0x0) {
153 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
154 ver = 0x10;
155 }
156 apic_version[m->mpc_apicid] = ver;
157 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
158 /*
159 * bios_cpu_apicid is required to have processors listed
160 * in same order as logical cpu numbers. Hence the first
161 * entry is BSP, and so on.
162 */
163 cpu = 0;
164 }
165 bios_cpu_apicid[cpu] = m->mpc_apicid;
166 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
167
168 cpu_set(cpu, cpu_possible_map);
169 cpu_set(cpu, cpu_present_map);
170 }
171
172 static void __init MP_bus_info (struct mpc_config_bus *m)
173 {
174 char str[7];
175
176 memcpy(str, m->mpc_bustype, 6);
177 str[6] = 0;
178 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
179
180 if (strncmp(str, "ISA", 3) == 0) {
181 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
182 } else if (strncmp(str, "EISA", 4) == 0) {
183 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
184 } else if (strncmp(str, "PCI", 3) == 0) {
185 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
186 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
187 mp_current_pci_id++;
188 } else if (strncmp(str, "MCA", 3) == 0) {
189 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
190 } else {
191 printk(KERN_ERR "Unknown bustype %s\n", str);
192 }
193 }
194
195 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
196 {
197 if (!(m->mpc_flags & MPC_APIC_USABLE))
198 return;
199
200 printk("I/O APIC #%d Version %d at 0x%X.\n",
201 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
202 if (nr_ioapics >= MAX_IO_APICS) {
203 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
204 MAX_IO_APICS, nr_ioapics);
205 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
206 }
207 if (!m->mpc_apicaddr) {
208 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
209 " found in MP table, skipping!\n");
210 return;
211 }
212 mp_ioapics[nr_ioapics] = *m;
213 nr_ioapics++;
214 }
215
216 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
217 {
218 mp_irqs [mp_irq_entries] = *m;
219 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
220 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
221 m->mpc_irqtype, m->mpc_irqflag & 3,
222 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
223 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
224 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
225 panic("Max # of irq sources exceeded!!\n");
226 }
227
228 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
229 {
230 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
231 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
232 m->mpc_irqtype, m->mpc_irqflag & 3,
233 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
234 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
235 /*
236 * Well it seems all SMP boards in existence
237 * use ExtINT/LVT1 == LINT0 and
238 * NMI/LVT2 == LINT1 - the following check
239 * will show us if this assumptions is false.
240 * Until then we do not have to add baggage.
241 */
242 if ((m->mpc_irqtype == mp_ExtINT) &&
243 (m->mpc_destapiclint != 0))
244 BUG();
245 if ((m->mpc_irqtype == mp_NMI) &&
246 (m->mpc_destapiclint != 1))
247 BUG();
248 }
249
250 /*
251 * Read/parse the MPC
252 */
253
254 static int __init smp_read_mpc(struct mp_config_table *mpc)
255 {
256 char str[16];
257 int count=sizeof(*mpc);
258 unsigned char *mpt=((unsigned char *)mpc)+count;
259
260 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
261 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
262 mpc->mpc_signature[0],
263 mpc->mpc_signature[1],
264 mpc->mpc_signature[2],
265 mpc->mpc_signature[3]);
266 return 0;
267 }
268 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
269 printk("SMP mptable: checksum error!\n");
270 return 0;
271 }
272 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
273 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
274 mpc->mpc_spec);
275 return 0;
276 }
277 if (!mpc->mpc_lapic) {
278 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
279 return 0;
280 }
281 memcpy(str,mpc->mpc_oem,8);
282 str[8]=0;
283 printk(KERN_INFO "OEM ID: %s ",str);
284
285 memcpy(str,mpc->mpc_productid,12);
286 str[12]=0;
287 printk("Product ID: %s ",str);
288
289 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
290
291 /* save the local APIC address, it might be non-default */
292 if (!acpi_lapic)
293 mp_lapic_addr = mpc->mpc_lapic;
294
295 /*
296 * Now process the configuration blocks.
297 */
298 while (count < mpc->mpc_length) {
299 switch(*mpt) {
300 case MP_PROCESSOR:
301 {
302 struct mpc_config_processor *m=
303 (struct mpc_config_processor *)mpt;
304 if (!acpi_lapic)
305 MP_processor_info(m);
306 mpt += sizeof(*m);
307 count += sizeof(*m);
308 break;
309 }
310 case MP_BUS:
311 {
312 struct mpc_config_bus *m=
313 (struct mpc_config_bus *)mpt;
314 MP_bus_info(m);
315 mpt += sizeof(*m);
316 count += sizeof(*m);
317 break;
318 }
319 case MP_IOAPIC:
320 {
321 struct mpc_config_ioapic *m=
322 (struct mpc_config_ioapic *)mpt;
323 MP_ioapic_info(m);
324 mpt+=sizeof(*m);
325 count+=sizeof(*m);
326 break;
327 }
328 case MP_INTSRC:
329 {
330 struct mpc_config_intsrc *m=
331 (struct mpc_config_intsrc *)mpt;
332
333 MP_intsrc_info(m);
334 mpt+=sizeof(*m);
335 count+=sizeof(*m);
336 break;
337 }
338 case MP_LINTSRC:
339 {
340 struct mpc_config_lintsrc *m=
341 (struct mpc_config_lintsrc *)mpt;
342 MP_lintsrc_info(m);
343 mpt+=sizeof(*m);
344 count+=sizeof(*m);
345 break;
346 }
347 }
348 }
349 clustered_apic_check();
350 if (!num_processors)
351 printk(KERN_ERR "SMP mptable: no processors registered!\n");
352 return num_processors;
353 }
354
355 static int __init ELCR_trigger(unsigned int irq)
356 {
357 unsigned int port;
358
359 port = 0x4d0 + (irq >> 3);
360 return (inb(port) >> (irq & 7)) & 1;
361 }
362
363 static void __init construct_default_ioirq_mptable(int mpc_default_type)
364 {
365 struct mpc_config_intsrc intsrc;
366 int i;
367 int ELCR_fallback = 0;
368
369 intsrc.mpc_type = MP_INTSRC;
370 intsrc.mpc_irqflag = 0; /* conforming */
371 intsrc.mpc_srcbus = 0;
372 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
373
374 intsrc.mpc_irqtype = mp_INT;
375
376 /*
377 * If true, we have an ISA/PCI system with no IRQ entries
378 * in the MP table. To prevent the PCI interrupts from being set up
379 * incorrectly, we try to use the ELCR. The sanity check to see if
380 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
381 * never be level sensitive, so we simply see if the ELCR agrees.
382 * If it does, we assume it's valid.
383 */
384 if (mpc_default_type == 5) {
385 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
386
387 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
388 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
389 else {
390 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
391 ELCR_fallback = 1;
392 }
393 }
394
395 for (i = 0; i < 16; i++) {
396 switch (mpc_default_type) {
397 case 2:
398 if (i == 0 || i == 13)
399 continue; /* IRQ0 & IRQ13 not connected */
400 /* fall through */
401 default:
402 if (i == 2)
403 continue; /* IRQ2 is never connected */
404 }
405
406 if (ELCR_fallback) {
407 /*
408 * If the ELCR indicates a level-sensitive interrupt, we
409 * copy that information over to the MP table in the
410 * irqflag field (level sensitive, active high polarity).
411 */
412 if (ELCR_trigger(i))
413 intsrc.mpc_irqflag = 13;
414 else
415 intsrc.mpc_irqflag = 0;
416 }
417
418 intsrc.mpc_srcbusirq = i;
419 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
420 MP_intsrc_info(&intsrc);
421 }
422
423 intsrc.mpc_irqtype = mp_ExtINT;
424 intsrc.mpc_srcbusirq = 0;
425 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
426 MP_intsrc_info(&intsrc);
427 }
428
429 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
430 {
431 struct mpc_config_processor processor;
432 struct mpc_config_bus bus;
433 struct mpc_config_ioapic ioapic;
434 struct mpc_config_lintsrc lintsrc;
435 int linttypes[2] = { mp_ExtINT, mp_NMI };
436 int i;
437
438 /*
439 * local APIC has default address
440 */
441 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
442
443 /*
444 * 2 CPUs, numbered 0 & 1.
445 */
446 processor.mpc_type = MP_PROCESSOR;
447 /* Either an integrated APIC or a discrete 82489DX. */
448 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
449 processor.mpc_cpuflag = CPU_ENABLED;
450 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
451 (boot_cpu_data.x86_model << 4) |
452 boot_cpu_data.x86_mask;
453 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
454 processor.mpc_reserved[0] = 0;
455 processor.mpc_reserved[1] = 0;
456 for (i = 0; i < 2; i++) {
457 processor.mpc_apicid = i;
458 MP_processor_info(&processor);
459 }
460
461 bus.mpc_type = MP_BUS;
462 bus.mpc_busid = 0;
463 switch (mpc_default_type) {
464 default:
465 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
466 mpc_default_type);
467 /* fall through */
468 case 1:
469 case 5:
470 memcpy(bus.mpc_bustype, "ISA ", 6);
471 break;
472 case 2:
473 case 6:
474 case 3:
475 memcpy(bus.mpc_bustype, "EISA ", 6);
476 break;
477 case 4:
478 case 7:
479 memcpy(bus.mpc_bustype, "MCA ", 6);
480 }
481 MP_bus_info(&bus);
482 if (mpc_default_type > 4) {
483 bus.mpc_busid = 1;
484 memcpy(bus.mpc_bustype, "PCI ", 6);
485 MP_bus_info(&bus);
486 }
487
488 ioapic.mpc_type = MP_IOAPIC;
489 ioapic.mpc_apicid = 2;
490 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
491 ioapic.mpc_flags = MPC_APIC_USABLE;
492 ioapic.mpc_apicaddr = 0xFEC00000;
493 MP_ioapic_info(&ioapic);
494
495 /*
496 * We set up most of the low 16 IO-APIC pins according to MPS rules.
497 */
498 construct_default_ioirq_mptable(mpc_default_type);
499
500 lintsrc.mpc_type = MP_LINTSRC;
501 lintsrc.mpc_irqflag = 0; /* conforming */
502 lintsrc.mpc_srcbusid = 0;
503 lintsrc.mpc_srcbusirq = 0;
504 lintsrc.mpc_destapic = MP_APIC_ALL;
505 for (i = 0; i < 2; i++) {
506 lintsrc.mpc_irqtype = linttypes[i];
507 lintsrc.mpc_destapiclint = i;
508 MP_lintsrc_info(&lintsrc);
509 }
510 }
511
512 static struct intel_mp_floating *mpf_found;
513
514 /*
515 * Scan the memory blocks for an SMP configuration block.
516 */
517 void __init get_smp_config (void)
518 {
519 struct intel_mp_floating *mpf = mpf_found;
520
521 /*
522 * ACPI supports both logical (e.g. Hyper-Threading) and physical
523 * processors, where MPS only supports physical.
524 */
525 if (acpi_lapic && acpi_ioapic) {
526 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
527 return;
528 }
529 else if (acpi_lapic)
530 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
531
532 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
533 if (mpf->mpf_feature2 & (1<<7)) {
534 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
535 pic_mode = 1;
536 } else {
537 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
538 pic_mode = 0;
539 }
540
541 /*
542 * Now see if we need to read further.
543 */
544 if (mpf->mpf_feature1 != 0) {
545
546 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
547 construct_default_ISA_mptable(mpf->mpf_feature1);
548
549 } else if (mpf->mpf_physptr) {
550
551 /*
552 * Read the physical hardware table. Anything here will
553 * override the defaults.
554 */
555 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
556 smp_found_config = 0;
557 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
558 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
559 return;
560 }
561 /*
562 * If there are no explicit MP IRQ entries, then we are
563 * broken. We set up most of the low 16 IO-APIC pins to
564 * ISA defaults and hope it will work.
565 */
566 if (!mp_irq_entries) {
567 struct mpc_config_bus bus;
568
569 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
570
571 bus.mpc_type = MP_BUS;
572 bus.mpc_busid = 0;
573 memcpy(bus.mpc_bustype, "ISA ", 6);
574 MP_bus_info(&bus);
575
576 construct_default_ioirq_mptable(0);
577 }
578
579 } else
580 BUG();
581
582 printk(KERN_INFO "Processors: %d\n", num_processors);
583 /*
584 * Only use the first configuration found.
585 */
586 }
587
588 static int __init smp_scan_config (unsigned long base, unsigned long length)
589 {
590 extern void __bad_mpf_size(void);
591 unsigned int *bp = phys_to_virt(base);
592 struct intel_mp_floating *mpf;
593
594 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
595 if (sizeof(*mpf) != 16)
596 __bad_mpf_size();
597
598 while (length > 0) {
599 mpf = (struct intel_mp_floating *)bp;
600 if ((*bp == SMP_MAGIC_IDENT) &&
601 (mpf->mpf_length == 1) &&
602 !mpf_checksum((unsigned char *)bp, 16) &&
603 ((mpf->mpf_specification == 1)
604 || (mpf->mpf_specification == 4)) ) {
605
606 smp_found_config = 1;
607 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
608 if (mpf->mpf_physptr)
609 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
610 mpf_found = mpf;
611 return 1;
612 }
613 bp += 4;
614 length -= 16;
615 }
616 return 0;
617 }
618
619 void __init find_intel_smp (void)
620 {
621 unsigned int address;
622
623 /*
624 * FIXME: Linux assumes you have 640K of base ram..
625 * this continues the error...
626 *
627 * 1) Scan the bottom 1K for a signature
628 * 2) Scan the top 1K of base RAM
629 * 3) Scan the 64K of bios
630 */
631 if (smp_scan_config(0x0,0x400) ||
632 smp_scan_config(639*0x400,0x400) ||
633 smp_scan_config(0xF0000,0x10000))
634 return;
635 /*
636 * If it is an SMP machine we should know now, unless the
637 * configuration is in an EISA/MCA bus machine with an
638 * extended bios data area.
639 *
640 * there is a real-mode segmented pointer pointing to the
641 * 4K EBDA area at 0x40E, calculate and scan it here.
642 *
643 * NOTE! There are Linux loaders that will corrupt the EBDA
644 * area, and as such this kind of SMP config may be less
645 * trustworthy, simply because the SMP table may have been
646 * stomped on during early boot. These loaders are buggy and
647 * should be fixed.
648 */
649
650 address = *(unsigned short *)phys_to_virt(0x40E);
651 address <<= 4;
652 if (smp_scan_config(address, 0x1000))
653 return;
654
655 /* If we have come this far, we did not find an MP table */
656 printk(KERN_INFO "No mptable found.\n");
657 }
658
659 /*
660 * - Intel MP Configuration Table
661 */
662 void __init find_smp_config (void)
663 {
664 #ifdef CONFIG_X86_LOCAL_APIC
665 find_intel_smp();
666 #endif
667 }
668
669
670 /* --------------------------------------------------------------------------
671 ACPI-based MP Configuration
672 -------------------------------------------------------------------------- */
673
674 #ifdef CONFIG_ACPI
675
676 void __init mp_register_lapic_address (
677 u64 address)
678 {
679 mp_lapic_addr = (unsigned long) address;
680
681 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
682
683 if (boot_cpu_id == -1U)
684 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
685
686 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
687 }
688
689
690 void __cpuinit mp_register_lapic (
691 u8 id,
692 u8 enabled)
693 {
694 struct mpc_config_processor processor;
695 int boot_cpu = 0;
696
697 if (id >= MAX_APICS) {
698 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
699 id, MAX_APICS);
700 return;
701 }
702
703 if (id == boot_cpu_physical_apicid)
704 boot_cpu = 1;
705
706 processor.mpc_type = MP_PROCESSOR;
707 processor.mpc_apicid = id;
708 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
709 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
710 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
711 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
712 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
713 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
714 processor.mpc_reserved[0] = 0;
715 processor.mpc_reserved[1] = 0;
716
717 MP_processor_info(&processor);
718 }
719
720 #ifdef CONFIG_X86_IO_APIC
721
722 #define MP_ISA_BUS 0
723 #define MP_MAX_IOAPIC_PIN 127
724
725 static struct mp_ioapic_routing {
726 int apic_id;
727 int gsi_start;
728 int gsi_end;
729 u32 pin_programmed[4];
730 } mp_ioapic_routing[MAX_IO_APICS];
731
732
733 static int mp_find_ioapic (
734 int gsi)
735 {
736 int i = 0;
737
738 /* Find the IOAPIC that manages this GSI. */
739 for (i = 0; i < nr_ioapics; i++) {
740 if ((gsi >= mp_ioapic_routing[i].gsi_start)
741 && (gsi <= mp_ioapic_routing[i].gsi_end))
742 return i;
743 }
744
745 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
746
747 return -1;
748 }
749
750
751 void __init mp_register_ioapic (
752 u8 id,
753 u32 address,
754 u32 gsi_base)
755 {
756 int idx = 0;
757
758 if (nr_ioapics >= MAX_IO_APICS) {
759 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
760 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
761 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
762 }
763 if (!address) {
764 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
765 " found in MADT table, skipping!\n");
766 return;
767 }
768
769 idx = nr_ioapics++;
770
771 mp_ioapics[idx].mpc_type = MP_IOAPIC;
772 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
773 mp_ioapics[idx].mpc_apicaddr = address;
774
775 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
776 mp_ioapics[idx].mpc_apicid = id;
777 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
778
779 /*
780 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
781 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
782 */
783 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
784 mp_ioapic_routing[idx].gsi_start = gsi_base;
785 mp_ioapic_routing[idx].gsi_end = gsi_base +
786 io_apic_get_redir_entries(idx);
787
788 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
789 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
790 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
791 mp_ioapic_routing[idx].gsi_start,
792 mp_ioapic_routing[idx].gsi_end);
793
794 return;
795 }
796
797
798 void __init mp_override_legacy_irq (
799 u8 bus_irq,
800 u8 polarity,
801 u8 trigger,
802 u32 gsi)
803 {
804 struct mpc_config_intsrc intsrc;
805 int ioapic = -1;
806 int pin = -1;
807
808 /*
809 * Convert 'gsi' to 'ioapic.pin'.
810 */
811 ioapic = mp_find_ioapic(gsi);
812 if (ioapic < 0)
813 return;
814 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
815
816 /*
817 * TBD: This check is for faulty timer entries, where the override
818 * erroneously sets the trigger to level, resulting in a HUGE
819 * increase of timer interrupts!
820 */
821 if ((bus_irq == 0) && (trigger == 3))
822 trigger = 1;
823
824 intsrc.mpc_type = MP_INTSRC;
825 intsrc.mpc_irqtype = mp_INT;
826 intsrc.mpc_irqflag = (trigger << 2) | polarity;
827 intsrc.mpc_srcbus = MP_ISA_BUS;
828 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
829 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
830 intsrc.mpc_dstirq = pin; /* INTIN# */
831
832 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
833 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
834 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
835 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
836
837 mp_irqs[mp_irq_entries] = intsrc;
838 if (++mp_irq_entries == MAX_IRQ_SOURCES)
839 panic("Max # of irq sources exceeded!\n");
840
841 return;
842 }
843
844
845 void __init mp_config_acpi_legacy_irqs (void)
846 {
847 struct mpc_config_intsrc intsrc;
848 int i = 0;
849 int ioapic = -1;
850
851 /*
852 * Fabricate the legacy ISA bus (bus #31).
853 */
854 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
855 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
856
857 /*
858 * Locate the IOAPIC that manages the ISA IRQs (0-15).
859 */
860 ioapic = mp_find_ioapic(0);
861 if (ioapic < 0)
862 return;
863
864 intsrc.mpc_type = MP_INTSRC;
865 intsrc.mpc_irqflag = 0; /* Conforming */
866 intsrc.mpc_srcbus = MP_ISA_BUS;
867 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
868
869 /*
870 * Use the default configuration for the IRQs 0-15. Unless
871 * overridden by (MADT) interrupt source override entries.
872 */
873 for (i = 0; i < 16; i++) {
874 int idx;
875
876 for (idx = 0; idx < mp_irq_entries; idx++) {
877 struct mpc_config_intsrc *irq = mp_irqs + idx;
878
879 /* Do we already have a mapping for this ISA IRQ? */
880 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
881 break;
882
883 /* Do we already have a mapping for this IOAPIC pin */
884 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
885 (irq->mpc_dstirq == i))
886 break;
887 }
888
889 if (idx != mp_irq_entries) {
890 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
891 continue; /* IRQ already used */
892 }
893
894 intsrc.mpc_irqtype = mp_INT;
895 intsrc.mpc_srcbusirq = i; /* Identity mapped */
896 intsrc.mpc_dstirq = i;
897
898 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
899 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
900 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
901 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
902 intsrc.mpc_dstirq);
903
904 mp_irqs[mp_irq_entries] = intsrc;
905 if (++mp_irq_entries == MAX_IRQ_SOURCES)
906 panic("Max # of irq sources exceeded!\n");
907 }
908
909 return;
910 }
911
912 #define MAX_GSI_NUM 4096
913
914 int mp_register_gsi(u32 gsi, int triggering, int polarity)
915 {
916 int ioapic = -1;
917 int ioapic_pin = 0;
918 int idx, bit = 0;
919 static int pci_irq = 16;
920 /*
921 * Mapping between Global System Interrupts, which
922 * represent all possible interrupts, to the IRQs
923 * assigned to actual devices.
924 */
925 static int gsi_to_irq[MAX_GSI_NUM];
926
927 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
928 return gsi;
929
930 /* Don't set up the ACPI SCI because it's already set up */
931 if (acpi_fadt.sci_int == gsi)
932 return gsi;
933
934 ioapic = mp_find_ioapic(gsi);
935 if (ioapic < 0) {
936 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
937 return gsi;
938 }
939
940 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
941
942 /*
943 * Avoid pin reprogramming. PRTs typically include entries
944 * with redundant pin->gsi mappings (but unique PCI devices);
945 * we only program the IOAPIC on the first.
946 */
947 bit = ioapic_pin % 32;
948 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
949 if (idx > 3) {
950 printk(KERN_ERR "Invalid reference to IOAPIC pin "
951 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
952 ioapic_pin);
953 return gsi;
954 }
955 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
956 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
957 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
958 return gsi_to_irq[gsi];
959 }
960
961 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
962
963 if (triggering == ACPI_LEVEL_SENSITIVE) {
964 /*
965 * For PCI devices assign IRQs in order, avoiding gaps
966 * due to unused I/O APIC pins.
967 */
968 int irq = gsi;
969 if (gsi < MAX_GSI_NUM) {
970 /*
971 * Retain the VIA chipset work-around (gsi > 15), but
972 * avoid a problem where the 8254 timer (IRQ0) is setup
973 * via an override (so it's not on pin 0 of the ioapic),
974 * and at the same time, the pin 0 interrupt is a PCI
975 * type. The gsi > 15 test could cause these two pins
976 * to be shared as IRQ0, and they are not shareable.
977 * So test for this condition, and if necessary, avoid
978 * the pin collision.
979 */
980 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
981 gsi = pci_irq++;
982 /*
983 * Don't assign IRQ used by ACPI SCI
984 */
985 if (gsi == acpi_fadt.sci_int)
986 gsi = pci_irq++;
987 gsi_to_irq[irq] = gsi;
988 } else {
989 printk(KERN_ERR "GSI %u is too high\n", gsi);
990 return gsi;
991 }
992 }
993
994 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
995 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
996 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
997 return gsi;
998 }
999
1000 #endif /*CONFIG_X86_IO_APIC*/
1001 #endif /*CONFIG_ACPI*/
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