include/asm-frv/dma.h

   1 /* dma.h: FRV DMA controller management
   2  *
   3  * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
   4  * Written by David Howells (dhowells@redhat.com)
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #ifndef _ASM_DMA_H
  13 #define _ASM_DMA_H
  14
  15 //#define DMA_DEBUG 1
  16
  17 #include <linux/interrupt.h>
  18
  19 #undef MAX_DMA_CHANNELS         /* don't use kernel/dma.c */
  20
  21 /* under 2.4 this is actually needed by the new bootmem allocator */
  22 #define MAX_DMA_ADDRESS         PAGE_OFFSET
  23
  24 /*
  25  * FRV DMA controller management
  26  */
  27 struct pt_regs;
  28
  29 typedef irqreturn_t (*dma_irq_handler_t)(int dmachan, unsigned long cstr, void *data,
  30                                          struct pt_regs *regs);
  31
  32 extern void frv_dma_init(void);
  33
  34 extern int frv_dma_open(const char *devname,
  35                         unsigned long dmamask,
  36                         int dmacap,
  37                         dma_irq_handler_t handler,
  38                         unsigned long irq_flags,
  39                         void *data);
  40
  41 /* channels required */
  42 #define FRV_DMA_MASK_ANY        ULONG_MAX       /* any channel */
  43
  44 /* capabilities required */
  45 #define FRV_DMA_CAP_DREQ        0x01            /* DMA request pin */
  46 #define FRV_DMA_CAP_DACK        0x02            /* DMA ACK pin */
  47 #define FRV_DMA_CAP_DONE        0x04            /* DMA done pin */
  48
  49 extern void frv_dma_close(int dma);
  50
  51 extern void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr);
  52
  53 extern void frv_dma_start(int dma,
  54                           unsigned long sba, unsigned long dba,
  55                           unsigned long pix, unsigned long six, unsigned long bcl);
  56
  57 extern void frv_dma_restart_circular(int dma, unsigned long six);
  58
  59 extern void frv_dma_stop(int dma);
  60
  61 extern int is_frv_dma_interrupting(int dma);
  62
  63 extern void frv_dma_dump(int dma);
  64
  65 extern void frv_dma_status_clear(int dma);
  66
  67 #define FRV_DMA_NCHANS  8
  68 #define FRV_DMA_4CHANS  4
  69 #define FRV_DMA_8CHANS  8
  70
  71 #define DMAC_CCFRx              0x00    /* channel configuration reg */
  72 #define DMAC_CCFRx_CM_SHIFT     16
  73 #define DMAC_CCFRx_CM_DA        0x00000000
  74 #define DMAC_CCFRx_CM_SCA       0x00010000
  75 #define DMAC_CCFRx_CM_DCA       0x00020000
  76 #define DMAC_CCFRx_CM_2D        0x00030000
  77 #define DMAC_CCFRx_ATS_SHIFT    8
  78 #define DMAC_CCFRx_RS_INTERN    0x00000000
  79 #define DMAC_CCFRx_RS_EXTERN    0x00000001
  80 #define DMAC_CCFRx_RS_SHIFT     0
  81
  82 #define DMAC_CSTRx              0x08    /* channel status reg */
  83 #define DMAC_CSTRx_FS           0x0000003f
  84 #define DMAC_CSTRx_NE           0x00000100
  85 #define DMAC_CSTRx_FED          0x00000200
  86 #define DMAC_CSTRx_WER          0x00000800
  87 #define DMAC_CSTRx_RER          0x00001000
  88 #define DMAC_CSTRx_CE           0x00002000
  89 #define DMAC_CSTRx_INT          0x00800000
  90 #define DMAC_CSTRx_BUSY         0x80000000
  91
  92 #define DMAC_CCTRx              0x10    /* channel control reg */
  93 #define DMAC_CCTRx_DSIZ_1       0x00000000
  94 #define DMAC_CCTRx_DSIZ_2       0x00000001
  95 #define DMAC_CCTRx_DSIZ_4       0x00000002
  96 #define DMAC_CCTRx_DSIZ_32      0x00000005
  97 #define DMAC_CCTRx_DAU_HOLD     0x00000000
  98 #define DMAC_CCTRx_DAU_INC      0x00000010
  99 #define DMAC_CCTRx_DAU_DEC      0x00000020
 100 #define DMAC_CCTRx_SSIZ_1       0x00000000
 101 #define DMAC_CCTRx_SSIZ_2       0x00000100
 102 #define DMAC_CCTRx_SSIZ_4       0x00000200
 103 #define DMAC_CCTRx_SSIZ_32      0x00000500
 104 #define DMAC_CCTRx_SAU_HOLD     0x00000000
 105 #define DMAC_CCTRx_SAU_INC      0x00001000
 106 #define DMAC_CCTRx_SAU_DEC      0x00002000
 107 #define DMAC_CCTRx_FC           0x08000000
 108 #define DMAC_CCTRx_ICE          0x10000000
 109 #define DMAC_CCTRx_IE           0x40000000
 110 #define DMAC_CCTRx_ACT          0x80000000
 111
 112 #define DMAC_SBAx               0x18    /* source base address reg */
 113 #define DMAC_DBAx               0x20    /* data base address reg */
 114 #define DMAC_PIXx               0x28    /* primary index reg */
 115 #define DMAC_SIXx               0x30    /* secondary index reg */
 116 #define DMAC_BCLx               0x38    /* byte count limit reg */
 117 #define DMAC_APRx               0x40    /* alternate pointer reg */
 118
 119 /*
 120  * required for PCI + MODULES
 121  */
 122 #ifdef CONFIG_PCI
 123 extern int isa_dma_bridge_buggy;
 124 #else
 125 #define isa_dma_bridge_buggy    (0)
 126 #endif
 127
 128 #endif /* _ASM_DMA_H */