include/asm-mips/sibyte/sb1250_int.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  Interrupt Mapper definitions             File: sb1250_int.h
   5     *
   6     *  This module contains constants for manipulating the SB1250's
   7     *  interrupt mapper and definitions for the interrupt sources.
   8     *
   9     *  SB1250 specification level:  User's manual 1/02/02
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This program is free software; you can redistribute it and/or
  17     *  modify it under the terms of the GNU General Public License as
  18     *  published by the Free Software Foundation; either version 2 of
  19     *  the License, or (at your option) any later version.
  20     *
  21     *  This program is distributed in the hope that it will be useful,
  22     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  23     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24     *  GNU General Public License for more details.
  25     *
  26     *  You should have received a copy of the GNU General Public License
  27     *  along with this program; if not, write to the Free Software
  28     *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29     *  MA 02111-1307 USA
  30     ********************************************************************* */
  31
  32
  33 #ifndef _SB1250_INT_H
  34 #define _SB1250_INT_H
  35
  36 #include "sb1250_defs.h"
  37
  38 /*  *********************************************************************
  39     *  Interrupt Mapper Constants
  40     ********************************************************************* */
  41
  42 /*
  43  * Interrupt sources (Table 4-8, UM 0.2)
  44  *
  45  * First, the interrupt numbers.
  46  */
  47
  48 #if SIBYTE_HDR_FEATURE_1250_112x
  49
  50 #define K_INT_SOURCES               64
  51
  52 #define K_INT_WATCHDOG_TIMER_0      0
  53 #define K_INT_WATCHDOG_TIMER_1      1
  54 #define K_INT_TIMER_0               2
  55 #define K_INT_TIMER_1               3
  56 #define K_INT_TIMER_2               4
  57 #define K_INT_TIMER_3               5
  58 #define K_INT_SMB_0                 6
  59 #define K_INT_SMB_1                 7
  60 #define K_INT_UART_0                8
  61 #define K_INT_UART_1                9
  62 #define K_INT_SER_0                 10
  63 #define K_INT_SER_1                 11
  64 #define K_INT_PCMCIA                12
  65 #define K_INT_ADDR_TRAP             13
  66 #define K_INT_PERF_CNT              14
  67 #define K_INT_TRACE_FREEZE          15
  68 #define K_INT_BAD_ECC               16
  69 #define K_INT_COR_ECC               17
  70 #define K_INT_IO_BUS                18
  71 #define K_INT_MAC_0                 19
  72 #define K_INT_MAC_1                 20
  73 #define K_INT_MAC_2                 21
  74 #define K_INT_DM_CH_0               22
  75 #define K_INT_DM_CH_1               23
  76 #define K_INT_DM_CH_2               24
  77 #define K_INT_DM_CH_3               25
  78 #define K_INT_MBOX_0                26
  79 #define K_INT_MBOX_1                27
  80 #define K_INT_MBOX_2                28
  81 #define K_INT_MBOX_3                29
  82 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
  83 #define K_INT_CYCLE_CP0_INT         30
  84 #define K_INT_CYCLE_CP1_INT         31
  85 #endif /* 1250 PASS2 || 112x PASS1 */
  86 #define K_INT_GPIO_0                32
  87 #define K_INT_GPIO_1                33
  88 #define K_INT_GPIO_2                34
  89 #define K_INT_GPIO_3                35
  90 #define K_INT_GPIO_4                36
  91 #define K_INT_GPIO_5                37
  92 #define K_INT_GPIO_6                38
  93 #define K_INT_GPIO_7                39
  94 #define K_INT_GPIO_8                40
  95 #define K_INT_GPIO_9                41
  96 #define K_INT_GPIO_10               42
  97 #define K_INT_GPIO_11               43
  98 #define K_INT_GPIO_12               44
  99 #define K_INT_GPIO_13               45
 100 #define K_INT_GPIO_14               46
 101 #define K_INT_GPIO_15               47
 102 #define K_INT_LDT_FATAL             48
 103 #define K_INT_LDT_NONFATAL          49
 104 #define K_INT_LDT_SMI               50
 105 #define K_INT_LDT_NMI               51
 106 #define K_INT_LDT_INIT              52
 107 #define K_INT_LDT_STARTUP           53
 108 #define K_INT_LDT_EXT               54
 109 #define K_INT_PCI_ERROR             55
 110 #define K_INT_PCI_INTA              56
 111 #define K_INT_PCI_INTB              57
 112 #define K_INT_PCI_INTC              58
 113 #define K_INT_PCI_INTD              59
 114 #define K_INT_SPARE_2               60
 115 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 116 #define K_INT_MAC_0_CH1             61
 117 #define K_INT_MAC_1_CH1             62
 118 #define K_INT_MAC_2_CH1             63
 119 #endif /* 1250 PASS2 || 112x PASS1 */
 120
 121 /*
 122  * Mask values for each interrupt
 123  */
 124
 125 #define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
 126 #define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
 127 #define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
 128 #define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
 129 #define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
 130 #define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
 131 #define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
 132 #define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
 133 #define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
 134 #define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
 135 #define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
 136 #define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
 137 #define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
 138 #define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
 139 #define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
 140 #define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
 141 #define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
 142 #define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
 143 #define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
 144 #define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
 145 #define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
 146 #define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
 147 #define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
 148 #define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
 149 #define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
 150 #define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
 151 #define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
 152 #define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
 153 #define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
 154 #define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
 155 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 156 #define M_INT_CYCLE_CP0_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
 157 #define M_INT_CYCLE_CP1_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
 158 #endif /* 1250 PASS2 || 112x PASS1 */
 159 #define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
 160 #define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
 161 #define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
 162 #define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
 163 #define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
 164 #define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
 165 #define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
 166 #define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
 167 #define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
 168 #define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
 169 #define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
 170 #define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
 171 #define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
 172 #define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
 173 #define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
 174 #define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
 175 #define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
 176 #define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
 177 #define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
 178 #define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
 179 #define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
 180 #define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
 181 #define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
 182 #define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
 183 #define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
 184 #define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
 185 #define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
 186 #define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
 187 #define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
 188 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 189 #define M_INT_MAC_0_CH1             _SB_MAKEMASK1(K_INT_MAC_0_CH1)
 190 #define M_INT_MAC_1_CH1             _SB_MAKEMASK1(K_INT_MAC_1_CH1)
 191 #define M_INT_MAC_2_CH1             _SB_MAKEMASK1(K_INT_MAC_2_CH1)
 192 #endif /* 1250 PASS2 || 112x PASS1 */
 193
 194 /*
 195  * Interrupt mappings
 196  */
 197
 198 #define K_INT_MAP_I0    0               /* interrupt pins on processor */
 199 #define K_INT_MAP_I1    1
 200 #define K_INT_MAP_I2    2
 201 #define K_INT_MAP_I3    3
 202 #define K_INT_MAP_I4    4
 203 #define K_INT_MAP_I5    5
 204 #define K_INT_MAP_NMI   6               /* nonmaskable */
 205 #define K_INT_MAP_DINT  7               /* debug interrupt */
 206
 207 /*
 208  * LDT Interrupt Set Register (table 4-5)
 209  */
 210
 211 #define S_INT_LDT_INTMSG              0
 212 #define M_INT_LDT_INTMSG              _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
 213 #define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
 214 #define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
 215
 216 #define K_INT_LDT_INTMSG_FIXED        0
 217 #define K_INT_LDT_INTMSG_ARBITRATED   1
 218 #define K_INT_LDT_INTMSG_SMI          2
 219 #define K_INT_LDT_INTMSG_NMI          3
 220 #define K_INT_LDT_INTMSG_INIT         4
 221 #define K_INT_LDT_INTMSG_STARTUP      5
 222 #define K_INT_LDT_INTMSG_EXTINT       6
 223 #define K_INT_LDT_INTMSG_RESERVED     7
 224
 225 #define M_INT_LDT_EDGETRIGGER         0
 226 #define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
 227
 228 #define M_INT_LDT_PHYSICALDEST        0
 229 #define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
 230
 231 #define S_INT_LDT_INTDEST             5
 232 #define M_INT_LDT_INTDEST             _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
 233 #define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
 234 #define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
 235
 236 #define S_INT_LDT_VECTOR              13
 237 #define M_INT_LDT_VECTOR              _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
 238 #define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
 239 #define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
 240
 241 /*
 242  * Vector format (Table 4-6)
 243  */
 244
 245 #define M_LDTVECT_RAISEINT              0x00
 246 #define M_LDTVECT_RAISEMBOX             0x40
 247
 248
 249 #endif  /* 1250/112x */
 250
 251 #endif