icv196/include/Z8536CIO.h

   1
   2 /*
   3   _________________________________________________________________
   4  |                                                                 |
   5  |   file name :        Z8536CIO.h                                 |
   6  |                                                                 |
   7  |   created: 02-mar-1992 Alain Gagnaire, Fridtjof Berlin          |
   8  |   updated: 02-mar-1992 A.G.                                     |
   9  |                                                                 |
  10  | Define value to use the Z8536CIO chip                           |
  11  | currently present in the following VME modules:                 |
  12  |             - sdvme  camac loop vme serial driver               |
  13  |             - fpiplsvme: front panel and plsTgm  vme interrup   |
  14  |_________________________________________________________________|
  15
  16  Updated :
  17  ========
  18  20-aug-1991 Fridtjof Berlin (removed uneccessary declarations)
  19
  20 */
  21 #ifndef _Z8536CIO_
  22 #define _Z8536CIO_
  23
  24 /* ICV196 VME module: offset of interface registers */
  25 #define ICV_AM       0x3d /* A24D16 for ICV module */
  26
  27 #define CSCLR_ICV    0x00 /* Clear ICV (Read/Write 16 bits) */
  28 #define CSGbase_ICV  0x02 /* R/W group base */
  29 #define CSG1G0_ICV   0x02 /* R/W Groups 1,  0   Lines  8-15,  0-7  */
  30 #define CSG3G2_ICV   0x04 /* R/W Group2 3,  2   Lines 24-31, 16-23 */
  31 #define CSG5G4_ICV   0x06 /* R/W Group2 5,  4   Lines 40-47, 32-39 */
  32 #define CSG7G6_ICV   0x08 /* R/W Group2 7,  6   Lines 56-63, 48-55 */
  33 #define CSG9G8_ICV   0x0A /* R/W Group2 9,  8   Lines 72-79, 64-71 */
  34 #define CSG11G10_ICV 0x0C /* R/W Group2 11, 10  Lines 88-95, 80-87 */
  35
  36 #define CSDIR_ICV    0x0E /* To define group dir(in/out): 12-9, 8-1 */
  37
  38 #define PortC_Z8536  0x81 /* Port C of chip Z8536 */
  39 #define PortB_Z8536  0x83 /* Port B of chip Z8536 */
  40 #define PortA_Z8536  0x85 /* Port A of chip Z8536 */
  41 #define CoReg_Z8536  0x87 /* Control Register of chip Z8536 */
  42
  43 #define CSNIT_ICV    0xC1 /* Mask reg. to define int.level used */
  44
  45 /*
  46                 For Programming Z8536 chip,
  47         some hints picked up from  description manual
  48         of the ADAS ICV 196 module (manual in french)
  49         Definition of register add in ICV196 chip: Z8536 CI/O
  50         This register are accessed via ICV196 control register:
  51         The acces to the chip must be done according to chip state
  52
  53                 - It is always possible to read the control register
  54                   * A read set the chip in "state 0"
  55                 - Write must be done in "state 0"
  56                   * First write in state 0 set the register pointer
  57                   * Second write access the currently pointed to register
  58        State diagram:
  59           <State 0>
  60                 --> Read  -> <state 0>
  61                 --> Write pointer -> <state 1>
  62           <state 1>
  63                 --> Read -> <state 0>
  64                 --> Write reset bit 1 --> <State reset>
  65                 --> Write data -> <state 0>
  66           <state reset>
  67                 --> Read -> <state reset>
  68                 --> Write reset bit(0)= 1 --> <State reset>
  69                 --> Write reset bit(0)= 0 --> <State 0>
  70 */
  71
  72 /* Register address offsets */
  73 #define MIC_reg          0x00 /* Master Interrupt Control register */
  74 #define MCC_reg          0x01 /* Master Config Control register */
  75 #define ItVct_Areg       0x02 /* Port A Interrupt Vector */
  76 #define ItVct_Breg       0x03 /* Port B Interrupt Vector */
  77 #define CtIVct_reg       0x04 /* Counter/Timer Int. Vector register */
  78 #define DPPol_Creg       0x05 /* Port C Data Path polarity register */
  79 #define DDir_Creg        0x06 /* Port C Data direction register */
  80 #define SIO_Creg         0x07 /* Port C Special I/O control register */
  81
  82 #define CSt_Areg         0x08 /* Port A Command & Status register */
  83 #define CSt_Breg         0x09 /* Port B Command & Status register */
  84 #define CtCSt_1reg       0x0A /* Counter/Timer 1 Cmd & Status reg. */
  85 #define CtCSt_2reg       0x0B /* Counter/Timer 2 Cmd & Status reg. */
  86 #define CtCSt_3reg       0x0C /* Counter/Timer 3 Cmd & Status reg. */
  87 #define Data_Areg        0x0D /* Port A data ( directly addressable) */
  88 #define Data_Breg        0x0E /* Port B data ( directly addressable) */
  89 #define Data_Creg        0x0F /* Port C data ( directly addressable) */
  90
  91 #define CtCMsb_1         0x10 /* C/T 1 Current Count Most  sign. bit */
  92 #define CtCLsb_1         0x11 /* C/T 1 Current Count Least sign. bit */
  93 #define CtCMsb_2         0x12 /* C/T 2 Current Count Most  sign. bit */
  94 #define CtCLsb_2         0x13 /* C/T 2 Current Count Least sign. bit */
  95 #define CtCMsb_3         0x14 /* C/T 3 Current Count Most  sign. bit */
  96 #define CtCLsb_3         0x15 /* C/T 3 Current Count Least sign. bit */
  97 #define CtTMsb_1         0x16 /* C/T 1 Cur. Time cstant MsBit        */
  98 #define CtTLsb_1         0x17 /* C/T 1 Cur. Time constant LsBit      */
  99
 100 #define CtTMsb_2         0x18 /* C/T 2 Cur. Time constant MsBit      */
 101 #define CtTLsb_2         0x19 /* C/T 2 Cur. Time constant LsBit      */
 102 #define CtTMsb_3         0x1A /* C/T 3 Cur. Time constant MsBit      */
 103 #define CtTLsb_3         0x1B /* C/T 3 Cur. Time constant LsBit      */
 104 #define CtMS_1           0x1C /* C/T 1 Mode specification */
 105 #define CtMS_2           0x1D /* C/T 2 Mode specification */
 106 #define CtMS_3           0x1E /* C/T 3 Mode specification */
 107 #define CurVct_reg       0x1F /* Current Vector */
 108
 109 #define MSpec_Areg       0x20 /* Port A Mode Specification register */
 110 #define Hspec_Areg       0x21 /* Port A Handshake Spec. register */
 111 #define DPPol_Areg       0x22 /* Port A Data Path polarity register */
 112 #define DDir_Areg        0x23 /* Port A Data direction register */
 113 #define SIO_Areg         0x24 /* Port A Special I/O control register */
 114 #define PtrPo_Areg       0x25 /* Port A Pattern Polarity register */
 115 #define PtrTr_Areg       0x26 /* Port A Pattern Transition register */
 116 #define PtrMsk_Areg      0x27 /* Port A Pattern Mask register */
 117
 118 #define MSpec_Breg       0x28 /* Port B Mode Specification register */
 119 #define HSpec_Breg       0x29 /* Port B Handshake Spec. register */
 120 #define DPPol_Breg       0x2A /* Port B Data Path polarity register*/
 121 #define DDir_Breg        0x2B /* Port B Data direction register */
 122 #define SIO_Breg         0x2C /* Port B Special I/O control register */
 123 #define PtrPo_Breg       0x2D /* Port B Pattern Polarity register */
 124 #define PtrTr_Breg       0x2E /* Port B Pattern Transition register */
 125 #define PtrMsk_Breg      0x2F /* Port B Pattern Mask register */
 126
 127 /* Command code ( bit 7, 6, 5) in Command and Status register */
 128 #define CoSt_NULL        0<<5 /* Null code           */
 129 #define CoSt_ClIpIus     1<<5 /* Clear IP & IUS bits */
 130 #define CoSt_SeIus       2<<5 /* Set   IUS           */
 131 #define CoSt_ClIus       3<<5 /* Clear IUS           */
 132 #define CoSt_SeIp        4<<5 /* Set   IP            */
 133 #define CoSt_ClIp        5<<5 /* Clear IP            */
 134 #define CoSt_SeIe        6<<5 /* Set   IE            */
 135 #define CoSt_ClIe        7<<5 /* Clear IE            */
 136
 137 #define CoSt_Ius         1<<7 /* Interrupt under Service (status) */
 138
 139 #define PtrM_OrVect      3<<1 /* Pattern OR prior encoded vect. mode */
 140 #define PtrM_Or          2<<1 /* Pattern OR */
 141 #define PtrM_And         1<<1 /* Pattern AND */
 142 #define PtrM_Dis         0<<1 /* Pattern Disable */
 143
 144 /* Mask bit for setting Master Interrupt Control register */
 145 #define b_0              1
 146 #define b_1              b_0<<1
 147 #define b_2              b_1<<1
 148 #define b_3              b_2<<1
 149 #define b_4              b_3<<1
 150 #define b_5              b_4<<1
 151 #define b_6              b_5<<1
 152 #define b_7              b_6<<1
 153
 154 #define b_MIE              b_7
 155 #define b_PAVIS            b_4
 156 #define b_PBVIS            b_3
 157 #define b_RIJUST           b_1
 158 #define b_RESET            b_0
 159
 160 #define PortA_Enable       b_2
 161 #define PortB_Enable       b_7
 162 #define Latch_On_Pat_Match b_0
 163
 164 #define All_Input   0xFF
 165 #define All_Masked  0
 166 #define Norm_Inp    0
 167 #define Non_Invert  0
 168 #define Zero_To_One 0xFF
 169 #define StInfMask   0xE
 170
 171 #define ICV_nln     16 /* Number of interrupt lines */
 172 #define ICV_nboards 4  /* Number of interrupt lines */
 173 #define PortA_nln   8
 174
 175 #endif  /* _Z8536CIO_ */