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vmod/vmodttl: fixed bug related to luns not ordered and/or not starting from zero.
[ht-drivers.git] / vmebridge / driver / tsi148.c
blob41faf7113d2c98cfca37b08c988e31b526a6b165
1 /*
2 * tsi148.c - Low level support for the Tundra TSI148 PCI-VME Bridge Chip
3 *
4 * Copyright (c) 2009 Sebastien Dugue
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <asm/byteorder.h>
16
17 #include "vme_bridge.h"
18 #include "tsi148.h"
19
20 #undef DEBUG_DMA
21
22 static struct tsi148_chip *chip;
23 static struct dma_pool *dma_desc_pool;
24
25 static inline void reg_join(u32 high, u32 low, u64 *out)
26 {
27 *out = (unsigned long long)high << 32;
28 *out |= low;
29 }
30
31 /*
32 * Procfs support
33 */
34
35 #ifdef CONFIG_PROC_FS
36 static struct proc_dir_entry *tsi148_proc_root;
37
38 /**
39 * tsi148_proc_pcfs_show() - Dump the PCFS register group
40 *
41 */
42 static int tsi148_proc_pcfs_show(char *page, char **start, off_t off, int count,
43 int *eof, void *data)
44 {
45 char *p = page;
46 unsigned int tmp;
47
48 p += sprintf(p, "\nPCFS Register Group:\n");
49
50 tmp = ioread32(&chip->pcfs.veni);
51 p += sprintf(p, "\tpciveni 0x%04x\n", tmp & 0xffff);
52 p += sprintf(p, "\tpcidevi 0x%04x\n", (tmp>>16) & 0xffff);
53 tmp = ioread32(&chip->pcfs.cmmd);
54 p += sprintf(p, "\tpcicmd 0x%04x\n", tmp & 0xffff);
55 p += sprintf(p, "\tpcistat 0x%04x\n", (tmp>>16) & 0xffff);
56 tmp = ioread32(&chip->pcfs.rev_class);
57 p += sprintf(p, "\tpcirev 0x%02x\n", tmp & 0xff);
58 p += sprintf(p, "\tpciclass 0x%06x\n", (tmp >> 8) & 0xffffff);
59 tmp = ioread32(&chip->pcfs.clsz);
60 p += sprintf(p, "\tpciclsz 0x%02x\n", tmp & 0xff);
61 p += sprintf(p, "\tpcimlat 0x%02x\n", (tmp>>8) & 0xff);
62 tmp = ioread32(&chip->pcfs.mbarl);
63 p += sprintf(p, "\tpcimbarl 0x%08x\n", tmp);
64 tmp = ioread32(&chip->pcfs.mbaru);
65 p += sprintf(p, "\tpcimbaru 0x%08x\n", tmp);
66 tmp = ioread32(&chip->pcfs.subv);
67 p += sprintf(p, "\tpcisubv 0x%04x\n", tmp & 0xffff);
68 p += sprintf(p, "\tpcisubi 0x%04x\n", (tmp>>16) & 0xffff);
69 tmp = ioread32(&chip->pcfs.intl);
70 p += sprintf(p, "\tpciintl 0x%02x\n", tmp & 0xff);
71 p += sprintf(p, "\tpciintp 0x%02x\n", (tmp>>8) & 0xff);
72 p += sprintf(p, "\tpcimngn 0x%02x\n", (tmp>>16) & 0xff);
73 p += sprintf(p, "\tpcimxla 0x%02x\n", (tmp>>24) & 0xff);
74 tmp = ioread32(&chip->pcfs.pcix_cap_id);
75 p += sprintf(p, "\tpcixcap 0x%02x\n", tmp & 0xff);
76 tmp = ioread32(&chip->pcfs.pcix_status);
77 p += sprintf(p, "\tpcixstat 0x%08x\n", tmp);
78
79 return p - page;
80 }
81
82 /**
83 * tsi148_proc_lcsr_show() - Dump the LCSR register group
84 *
85 */
86 static int tsi148_proc_lcsr_show(char *page, char **start, off_t off, int count,
87 int *eof, void *data)
88 {
89 int i;
90 char *p = page;
91
92 p += sprintf(p, "\n");
93
94 /* Display outbound decoders */
95 p += sprintf(p, "Local Control and Status Register Group (LCSR):\n");
96 p += sprintf(p, "\nOutbound Translations:\n");
97
98 p += sprintf(p, "No. otat otsau:otsal oteau:oteal"
99 " otofu:otofl\n");
100
101 for (i = 0; i < 8; i++) {
102 unsigned int otat, otsau, otsal, oteau, oteal, otofu, otofl;
103
104 otat = ioread32be(&chip->lcsr.otrans[i].otat);
105 otsau = ioread32be(&chip->lcsr.otrans[i].otsau);
106 otsal = ioread32be(&chip->lcsr.otrans[i].otsal);
107 oteau = ioread32be(&chip->lcsr.otrans[i].oteau);
108 oteal = ioread32be(&chip->lcsr.otrans[i].oteal);
109 otofu = ioread32be(&chip->lcsr.otrans[i].otofu);
110 otofl = ioread32be(&chip->lcsr.otrans[i].otofl);
111
112 p += sprintf(p,
113 "%d: %08X %08X:%08X %08X:%08X: %08X:%08X\n", i,
114 otat, otsau, otsal, oteau, oteal, otofu, otofl);
115 }
116
117 /* Display inbound decoders */
118 p += sprintf(p, "\nInbound Translations:\n");
119 p += sprintf(p, "No. itat itsau:itsal iteau:iteal"
120 " itofu:itofl\n");
121
122 for (i = 0; i < 8; i++) {
123 unsigned int itat, itsau, itsal, iteau, iteal, itofu, itofl;
124
125 itat = ioread32be(&chip->lcsr.itrans[i].itat);
126 itsau = ioread32be(&chip->lcsr.itrans[i].itsau);
127 itsal = ioread32be(&chip->lcsr.itrans[i].itsal);
128 iteau = ioread32be(&chip->lcsr.itrans[i].iteau);
129 iteal = ioread32be(&chip->lcsr.itrans[i].iteal);
130 itofu = ioread32be(&chip->lcsr.itrans[i].itofu);
131 itofl = ioread32be(&chip->lcsr.itrans[i].itofl);
132
133 p += sprintf(p,
134 "%d: %08X %08X:%08X %08X:%08X: %08X:%08X\n", i,
135 itat, itsau, itsal, iteau, iteal, itofu, itofl);
136 }
137
138 p += sprintf(p, "\nVME Bus Control:\n");
139 p += sprintf(p, "\tvmctrl 0x%08x\n", ioread32be(&chip->lcsr.vmctrl));
140 p += sprintf(p, "\tvctrl 0x%08x\n", ioread32be(&chip->lcsr.vctrl));
141 p += sprintf(p, "\tvstat 0x%08x\n", ioread32be(&chip->lcsr.vstat));
142
143 p += sprintf(p, "PCI Status:\n");
144 p += sprintf(p, "\tpcsr 0x%08x\n", ioread32be(&chip->lcsr.pstat));
145
146 p += sprintf(p, "VME Exception Status:\n");
147 p += sprintf(p, "\tveau:veal 0x%08x:%08x\n",
148 ioread32be(&chip->lcsr.veau),
149 ioread32be(&chip->lcsr.veal));
150 p += sprintf(p, "\tveat 0x%08x\n", ioread32be(&chip->lcsr.veat));
151
152 p += sprintf(p, "PCI Error Status:\n");
153 p += sprintf(p, "\tedpau:edpal 0x%08x:%08x\n",
154 ioread32be(&chip->lcsr.edpau),
155 ioread32be(&chip->lcsr.edpal));
156 p += sprintf(p, "\tedpxa 0x%08x\n", ioread32be(&chip->lcsr.edpxa));
157 p += sprintf(p, "\tedpxs 0x%08x\n", ioread32be(&chip->lcsr.edpxs));
158 p += sprintf(p, "\tedpat 0x%08x\n", ioread32be(&chip->lcsr.edpat));
159
160 p += sprintf(p, "Inbound Translation Location Monitor:\n");
161 p += sprintf(p, "\tlmbau:lmbal 0x%08x:%08x:\n",
162 ioread32be(&chip->lcsr.lmbau),
163 ioread32be(&chip->lcsr.lmbal));
164 p += sprintf(p, "\tlmat 0x%08x\n", ioread32be(&chip->lcsr.lmat));
165
166 p += sprintf(p, "Local bus Interrupt Control:\n");
167 p += sprintf(p, "\tinten 0x%08x\n", ioread32be(&chip->lcsr.inten));
168 p += sprintf(p, "\tinteo 0x%08x\n", ioread32be(&chip->lcsr.inteo));
169 p += sprintf(p, "\tints 0x%08x\n", ioread32be(&chip->lcsr.ints));
170 p += sprintf(p, "\tintc 0x%08x\n", ioread32be(&chip->lcsr.intc));
171 p += sprintf(p, "\tintm1 0x%08x\n", ioread32be(&chip->lcsr.intm1));
172 p += sprintf(p, "\tintm2 0x%08x\n", ioread32be(&chip->lcsr.intm2));
173
174 p += sprintf(p, "VMEbus Interrupt Control:\n");
175 p += sprintf(p, "\tbcu64 0x%08x\n", ioread32be(&chip->lcsr.bcu));
176 p += sprintf(p, "\tbcl64 0x%08x\n", ioread32be(&chip->lcsr.bcl));
177 p += sprintf(p, "\tbpgtr 0x%08x\n", ioread32be(&chip->lcsr.bpgtr));
178 p += sprintf(p, "\tbpctr 0x%08x\n", ioread32be(&chip->lcsr.bpctr));
179 p += sprintf(p, "\tvicr 0x%08x\n", ioread32be(&chip->lcsr.vicr));
180
181 p += sprintf(p, "RMW Register Group:\n");
182 p += sprintf(p, "\trmwau 0x%08x\n", ioread32be(&chip->lcsr.rmwau));
183 p += sprintf(p, "\trmwal 0x%08x\n", ioread32be(&chip->lcsr.rmwal));
184 p += sprintf(p, "\trmwen 0x%08x\n", ioread32be(&chip->lcsr.rmwen));
185 p += sprintf(p, "\trmwc 0x%08x\n", ioread32be(&chip->lcsr.rmwc));
186 p += sprintf(p, "\trmws 0x%08x\n", ioread32be(&chip->lcsr.rmws));
187
188 for(i = 0; i < TSI148_NUM_DMA_CHANNELS; i++){
189 p += sprintf(p, "DMA Controler %d Registers\n", i);
190 p += sprintf(p, "\tdctl 0x%08x\n",
191 ioread32be(&chip->lcsr.dma[i].dctl));
192 p += sprintf(p, "\tdsta 0x%08x\n",
193 ioread32be(&chip->lcsr.dma[i].dsta));
194 p += sprintf(p, "\tdcsau 0x%08x\n",
195 ioread32be(&chip->lcsr.dma[i].dcsau));
196 p += sprintf(p, "\tdcsal 0x%08x\n",
197 ioread32be(&chip->lcsr.dma[i].dcsal));
198 p += sprintf(p, "\tdcdau 0x%08x\n",
199 ioread32be(&chip->lcsr.dma[i].dcdau));
200 p += sprintf(p, "\tdcdal 0x%08x\n",
201 ioread32be(&chip->lcsr.dma[i].dcdal));
202 p += sprintf(p, "\tdclau 0x%08x\n",
203 ioread32be(&chip->lcsr.dma[i].dclau));
204 p += sprintf(p, "\tdclal 0x%08x\n",
205 ioread32be(&chip->lcsr.dma[i].dclal));
206 p += sprintf(p, "\tdsau 0x%08x\n",
207 ioread32be(&chip->lcsr.dma[i].dma_desc.dsau));
208 p += sprintf(p, "\tdsal 0x%08x\n",
209 ioread32be(&chip->lcsr.dma[i].dma_desc.dsal));
210 p += sprintf(p, "\tddau 0x%08x\n",
211 ioread32be(&chip->lcsr.dma[i].dma_desc.ddau));
212 p += sprintf(p, "\tddal 0x%08x\n",
213 ioread32be(&chip->lcsr.dma[i].dma_desc.ddal));
214 p += sprintf(p, "\tdsat 0x%08x\n",
215 ioread32be(&chip->lcsr.dma[i].dma_desc.dsat));
216 p += sprintf(p, "\tddat 0x%08x\n",
217 ioread32be(&chip->lcsr.dma[i].dma_desc.ddat));
218 p += sprintf(p, "\tdnlau 0x%08x\n",
219 ioread32be(&chip->lcsr.dma[i].dma_desc.dnlau));
220 p += sprintf(p, "\tdnlal 0x%08x\n",
221 ioread32be(&chip->lcsr.dma[i].dma_desc.dnlal));
222 p += sprintf(p, "\tdcnt 0x%08x\n",
223 ioread32be(&chip->lcsr.dma[i].dma_desc.dcnt));
224 p += sprintf(p, "\tddbs 0x%08x\n",
225 ioread32be(&chip->lcsr.dma[i].dma_desc.ddbs));
226 }
227
228 return p - page;
229 }
230
231 /**
232 * tsi148_proc_gcsr_show() - Dump the GCSR register group
233 *
234 */
235 static int tsi148_proc_gcsr_show(char *page, char **start, off_t off, int count,
236 int *eof, void *data)
237 {
238 char *p = page;
239 int i;
240 unsigned int tmp;
241
242 p += sprintf(p, "\nGlobal Control and Status Register Group (GCSR):\n");
243
244 tmp = ioread32be(&chip->gcsr.devi);
245 p += sprintf(p, "\tveni 0x%04x\n", tmp & 0xffff);
246 p += sprintf(p, "\tdevi 0x%04x\n", (tmp >> 16) & 0xffff);
247
248 tmp = ioread32be(&chip->gcsr.ctrl);
249 p += sprintf(p, "\tgctrl 0x%04x\n", (tmp >> 16) & 0xffff);
250 p += sprintf(p, "\tga 0x%02x\n", (tmp >> 8) & 0x3f);
251 p += sprintf(p, "\trevid 0x%02x\n", tmp & 0xff);
252
253 p += sprintf(p, "Semaphores:\n");
254 tmp = ioread32be(&chip->gcsr.semaphore[0]);
255 p += sprintf(p, "\tsem0 0x%02x\n", (tmp >> 24) & 0xff);
256 p += sprintf(p, "\tsem1 0x%02x\n", (tmp >> 16) & 0xff);
257 p += sprintf(p, "\tsem2 0x%02x\n", (tmp >> 8) & 0xff);
258 p += sprintf(p, "\tsem3 0x%02x\n", tmp & 0xff);
259
260 tmp = ioread32be(&chip->gcsr.semaphore[4]);
261 p += sprintf(p, "\tsem4 0x%02x\n", (tmp >> 24) & 0xff);
262 p += sprintf(p, "\tsem5 0x%02x\n", (tmp >> 16) & 0xff);
263 p += sprintf(p, "\tsem6 0x%02x\n", (tmp >> 8) & 0xff);
264 p += sprintf(p, "\tsem7 0x%02x\n", tmp & 0xff);
265
266 p += sprintf(p, "Mailboxes:\n");
267 for (i = 0; i <= TSI148_NUM_MAILBOXES; i++){
268 p += sprintf(p,"\t Mailbox #%d: 0x%08x\n", i,
269 ioread32be(&chip->gcsr.mbox[i]));
270 }
271
272 return p - page;
273 }
274
275 /**
276 * tsi148_proc_crcsr_show() - Dump the CRCSR register group
277 *
278 */
279 int tsi148_proc_crcsr_show(char *page, char **start, off_t off, int count,
280 int *eof, void *data)
281 {
282 char *p = page;
283
284 p += sprintf(p, "\nCR/CSR Register Group:\n");
285 p += sprintf(p, "\tbcr 0x%08x\n", ioread32be(&chip->crcsr.csrbcr));
286 p += sprintf(p, "\tbsr 0x%08x\n", ioread32be(&chip->crcsr.csrbsr));
287 p += sprintf(p, "\tbar 0x%08x\n", ioread32be(&chip->crcsr.cbar));
288
289 return p - page;
290 }
291
292 /**
293 * tsi148_procfs_register() - Create the VME proc tree
294 * @vme_root: Root directory of the VME proc tree
295 */
296 void __devinit tsi148_procfs_register(struct proc_dir_entry *vme_root)
297 {
298 struct proc_dir_entry *entry;
299
300 tsi148_proc_root = proc_mkdir("tsi148", vme_root);
301
302 entry = create_proc_entry("pcfs", S_IFREG | S_IRUGO, tsi148_proc_root);
303
304 if (!entry)
305 printk(KERN_WARNING PFX "Failed to create proc pcfs node\n");
306
307 entry->read_proc = tsi148_proc_pcfs_show;
308
309 entry = create_proc_entry("lcsr", S_IFREG | S_IRUGO, tsi148_proc_root);
310
311 if (!entry)
312 printk(KERN_WARNING PFX "Failed to create proc lcsr node\n");
313
314 entry->read_proc = tsi148_proc_lcsr_show;
315
316 entry = create_proc_entry("gcsr", S_IFREG | S_IRUGO, tsi148_proc_root);
317
318 if (!entry)
319 printk(KERN_WARNING PFX "Failed to create proc gcsr node\n");
320
321 entry->read_proc = tsi148_proc_gcsr_show;
322
323 entry = create_proc_entry("crcsr", S_IFREG | S_IRUGO, tsi148_proc_root);
324
325 if (!entry)
326 printk(KERN_WARNING PFX "Failed to create proc crcsr node\n");
327
328 entry->read_proc = tsi148_proc_crcsr_show;
329 }
330
331 /**
332 * tsi148_procfs_unregister() - Remove the VME proc tree
333 *
334 */
335 void __devexit tsi148_procfs_unregister(struct proc_dir_entry *vme_root)
336 {
337 remove_proc_entry("pcfs", tsi148_proc_root);
338 remove_proc_entry("lcsr", tsi148_proc_root);
339 remove_proc_entry("gcsr", tsi148_proc_root);
340 remove_proc_entry("crcsr", tsi148_proc_root);
341 remove_proc_entry(tsi148_proc_root->name, vme_root);
342 }
343 #endif /* CONFIG_PROC_FS */
344
345 /*
346 * PCI and VME bus interrupt handlers
347 */
348
349
350 /**
351 * tsi148_handle_pci_error() - Handle a PCI bus error reported by the bridge
352 *
353 * This handler simply displays a message on the console and clears
354 * the error.
355 */
356 void tsi148_handle_pci_error(void)
357 {
358 /* Display raw error information */
359 printk(KERN_ERR PFX
360 "PCI error at address: %.8x %.8x - attributes: %.8x\n"
361 "PCI-X attributes: %.8x - PCI-X split completion: %.8x\n",
362 ioread32be(&chip->lcsr.edpau), ioread32be(&chip->lcsr.edpal),
363 ioread32be(&chip->lcsr.edpat),
364 ioread32be(&chip->lcsr.edpxa), ioread32be(&chip->lcsr.edpxs));
365
366 /* Clear error */
367 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, &chip->lcsr.edpat);
368 }
369
370 /**
371 * tsi148_handle_vme_error() - Handle a VME bus error reported by the bridge
372 *
373 * Retrieve and report the offending VME address and Address Modifier, clearing
374 * the error.
375 */
376 void tsi148_handle_vme_error(struct vme_bus_error *error)
377 {
378 u32 attr;
379 u32 addru, addrl;
380
381 /* Store the address */
382 addru = ioread32be(&chip->lcsr.veau);
383 addrl = ioread32be(&chip->lcsr.veal);
384 reg_join(addru, addrl, &error->address);
385
386 /* Get the Address Modifier from the attributes */
387 attr = ioread32be(&chip->lcsr.veat);
388 error->am = (attr & TSI148_LCSR_VEAT_AM) >> TSI148_LCSR_VEAT_AM_SHIFT;
389
390 /* Display raw error information */
391 if (vme_report_bus_errors) {
392 printk(KERN_ERR PFX "VME bus error at address: %.8x %.8x - "
393 "AM: 0x%x - tsi148 attributes: %.8x\n",
394 addru, addrl, error->am, attr);
395 }
396
397 /* Overflow detected: not much we can do about it */
398 if (attr & TSI148_LCSR_VEAT_VEOF)
399 printk(KERN_ERR PFX "VME Bus Exception Overflow Detected\n");
400
401 /* Clear error */
402 iowrite32be(TSI148_LCSR_VEAT_VESCL, &chip->lcsr.veat);
403 }
404
405 /**
406 * tsi148_generate_interrupt() - Generate an interrupt on the VME bus
407 * @level: IRQ level (1-7)
408 * @vector: IRQ vector (0-255)
409 * @msecs: Timeout for IACK in milliseconds
410 *
411 * This function generates an interrupt on the VME bus and waits for IACK
412 * for msecs milliseconds.
413 *
414 * Returns 0 on success or -ETIME if the timeout expired.
415 *
416 */
417 int tsi148_generate_interrupt(int level, int vector, signed long msecs)
418 {
419 unsigned int val;
420 signed long timeout = msecs_to_jiffies(msecs);
421
422
423 if ((level < 1) || (level > 7))
424 return -EINVAL;
425
426 if ((vector < 0) || (vector > 255))
427 return -EINVAL;
428
429 /* Generate VME IRQ */
430 val = ioread32be(&chip->lcsr.vicr) & ~TSI148_LCSR_VICR_STID_M;
431 val |= ((level << 8) | vector);
432 iowrite32be(val, &chip->lcsr.vicr);
433
434 /* Wait until IACK */
435 while (ioread32be(&chip->lcsr.vicr) & TSI148_LCSR_VICR_IRQS) {
436 set_current_state(TASK_INTERRUPTIBLE);
437 timeout = schedule_timeout(timeout);
438
439 if (timeout == 0)
440 break;
441 }
442
443 if (ioread32be(&chip->lcsr.vicr) & TSI148_LCSR_VICR_IRQS) {
444 /* No IACK received, clear the IRQ */
445 val = ioread32be(&chip->lcsr.vicr);
446
447 val &= ~(TSI148_LCSR_VICR_IRQL_M | TSI148_LCSR_VICR_STID_M);
448 val |= TSI148_LCSR_VICR_IRQC;
449 iowrite32be(val, &chip->lcsr.vicr);
450
451 return -ETIME;
452 }
453
454
455 return 0;
456 }
457
458 /*
459 * Utility functions
460 */
461
462 /**
463 * am_to_attr() - Convert a standard VME address modifier to TSI148 attributes
464 * @am: Address modifier
465 * @addr_size: Address size
466 * @transfer_mode: Transfer Mode
467 * @user_access: User / Supervisor access
468 * @data_access: Data / Program access
469 *
470 */
471 static int am_to_attr(enum vme_address_modifier am,
472 unsigned int *addr_size,
473 unsigned int *transfer_mode,
474 unsigned int *user_access,
475 unsigned int *data_access)
476 {
477 switch (am) {
478 case VME_A16_USER:
479 *addr_size = TSI148_A16;
480 *transfer_mode = TSI148_SCT;
481 *data_access = TSI148_DATA;
482 *user_access = TSI148_USER;
483 break;
484 case VME_A16_SUP:
485 *addr_size = TSI148_A16;
486 *transfer_mode = TSI148_SCT;
487 *data_access = TSI148_DATA;
488 *user_access = TSI148_SUPER;
489 break;
490 case VME_A24_USER_MBLT:
491 *addr_size = TSI148_A24;
492 *transfer_mode = TSI148_MBLT;
493 *data_access = TSI148_DATA;
494 *user_access = TSI148_USER;
495 break;
496 case VME_A24_USER_DATA_SCT:
497 *addr_size = TSI148_A24;
498 *transfer_mode = TSI148_SCT;
499 *data_access = TSI148_DATA;
500 *user_access = TSI148_USER;
501 break;
502 case VME_A24_USER_PRG_SCT:
503 *addr_size = TSI148_A24;
504 *transfer_mode = TSI148_SCT;
505 *data_access = TSI148_PROG;
506 *user_access = TSI148_USER;
507 break;
508 case VME_A24_USER_BLT:
509 *addr_size = TSI148_A24;
510 *transfer_mode = TSI148_BLT;
511 *data_access = TSI148_DATA;
512 *user_access = TSI148_USER;
513 break;
514 case VME_A24_SUP_MBLT:
515 *addr_size = TSI148_A24;
516 *transfer_mode = TSI148_MBLT;
517 *data_access = TSI148_DATA;
518 *user_access = TSI148_SUPER;
519 break;
520 case VME_A24_SUP_DATA_SCT:
521 *addr_size = TSI148_A24;
522 *transfer_mode = TSI148_SCT;
523 *data_access = TSI148_DATA;
524 *user_access = TSI148_SUPER;
525 break;
526 case VME_A24_SUP_PRG_SCT:
527 *addr_size = TSI148_A24;
528 *transfer_mode = TSI148_SCT;
529 *data_access = TSI148_PROG;
530 *user_access = TSI148_SUPER;
531 break;
532 case VME_A24_SUP_BLT:
533 *addr_size = TSI148_A24;
534 *transfer_mode = TSI148_BLT;
535 *data_access = TSI148_DATA;
536 *user_access = TSI148_SUPER;
537 break;
538 case VME_A32_USER_MBLT:
539 *addr_size = TSI148_A32;
540 *transfer_mode = TSI148_MBLT;
541 *data_access = TSI148_DATA;
542 *user_access = TSI148_USER;
543 break;
544 case VME_A32_USER_DATA_SCT:
545 *addr_size = TSI148_A32;
546 *transfer_mode = TSI148_SCT;
547 *data_access = TSI148_DATA;
548 *user_access = TSI148_USER;
549 break;
550 case VME_A32_USER_PRG_SCT:
551 *addr_size = TSI148_A32;
552 *transfer_mode = TSI148_SCT;
553 *data_access = TSI148_PROG;
554 *user_access = TSI148_USER;
555 break;
556 case VME_A32_USER_BLT:
557 *addr_size = TSI148_A32;
558 *transfer_mode = TSI148_BLT;
559 *data_access = TSI148_DATA;
560 *user_access = TSI148_USER;
561 break;
562 case VME_A32_SUP_MBLT:
563 *addr_size = TSI148_A32;
564 *transfer_mode = TSI148_MBLT;
565 *data_access = TSI148_DATA;
566 *user_access = TSI148_SUPER;
567 break;
568 case VME_A32_SUP_DATA_SCT:
569 *addr_size = TSI148_A32;
570 *transfer_mode = TSI148_SCT;
571 *data_access = TSI148_DATA;
572 *user_access = TSI148_SUPER;
573 break;
574 case VME_A32_SUP_PRG_SCT:
575 *addr_size = TSI148_A32;
576 *transfer_mode = TSI148_SCT;
577 *data_access = TSI148_PROG;
578 *user_access = TSI148_SUPER;
579 break;
580 case VME_A32_SUP_BLT:
581 *addr_size = TSI148_A32;
582 *transfer_mode = TSI148_BLT;
583 *data_access = TSI148_DATA;
584 *user_access = TSI148_SUPER;
585 break;
586 case VME_A64_SCT:
587 *addr_size = TSI148_A64;
588 *transfer_mode = TSI148_SCT;
589 *data_access = TSI148_DATA;
590 *user_access = TSI148_SUPER;
591 break;
592 case VME_A64_BLT:
593 *addr_size = TSI148_A64;
594 *transfer_mode = TSI148_BLT;
595 *data_access = TSI148_DATA;
596 *user_access = TSI148_SUPER;
597 break;
598 case VME_A64_MBLT:
599 *addr_size = TSI148_A64;
600 *transfer_mode = TSI148_MBLT;
601 *data_access = TSI148_DATA;
602 *user_access = TSI148_SUPER;
603 break;
604 case VME_CR_CSR:
605 *addr_size = TSI148_CRCSR;
606 *transfer_mode = TSI148_SCT;
607 *data_access = TSI148_DATA;
608 *user_access = TSI148_USER;
609 break;
610
611 default:
612 return -1;
613 }
614
615 return 0;
616 }
617
618 /**
619 * attr_to_am() - Convert TSI148 attributes to a standard VME address modifier
620 * @addr_size: Address size
621 * @transfer_mode: Transfer Mode
622 * @user_access: User / Supervisor access
623 * @data_access: Data / Program access
624 * @am: Address modifier
625 *
626 */
627 static void attr_to_am(unsigned int addr_size, unsigned int transfer_mode,
628 unsigned int user_access, unsigned int data_access,
629 int *am)
630 {
631
632 if (addr_size == TSI148_A16) {
633 if (user_access == TSI148_USER)
634 *am = VME_A16_USER;
635 else
636 *am = VME_A16_SUP;
637 }
638 else if (addr_size == TSI148_A24) {
639 if (user_access == TSI148_USER) {
640 if (transfer_mode == TSI148_SCT) {
641 if (data_access == TSI148_DATA)
642 *am = VME_A24_USER_DATA_SCT;
643 else
644 *am = VME_A24_USER_PRG_SCT;
645 } else if (transfer_mode == TSI148_BLT)
646 *am = VME_A24_USER_BLT;
647 else if (transfer_mode == TSI148_MBLT)
648 *am = VME_A24_USER_MBLT;
649 } else if (user_access == TSI148_SUPER) {
650 if (transfer_mode == TSI148_SCT) {
651 if (data_access == TSI148_DATA)
652 *am = VME_A24_SUP_DATA_SCT;
653 else
654 *am = VME_A24_SUP_PRG_SCT;
655 } else if (transfer_mode == TSI148_BLT)
656 *am = VME_A24_SUP_BLT;
657 else if (transfer_mode == TSI148_MBLT)
658 *am = VME_A24_SUP_MBLT;
659 }
660 }
661 else if (addr_size == TSI148_A32) {
662 if (user_access == TSI148_USER) {
663 if (transfer_mode == TSI148_SCT) {
664 if (data_access == TSI148_DATA)
665 *am = VME_A32_USER_DATA_SCT;
666 else
667 *am = VME_A32_USER_PRG_SCT;
668 } else if (transfer_mode == TSI148_BLT)
669 *am = VME_A32_USER_BLT;
670 else if (transfer_mode == TSI148_MBLT)
671 *am = VME_A32_USER_MBLT;
672 } else if (user_access == TSI148_SUPER) {
673 if (transfer_mode == TSI148_SCT) {
674 if (data_access == TSI148_DATA)
675 *am = VME_A32_SUP_DATA_SCT;
676 else
677 *am = VME_A32_SUP_PRG_SCT;
678 } else if (transfer_mode == TSI148_BLT)
679 *am = VME_A32_SUP_BLT;
680 else if (transfer_mode == TSI148_MBLT)
681 *am = VME_A32_SUP_MBLT;
682 }
683 }
684 else if (addr_size == TSI148_A64) {
685 if (transfer_mode == TSI148_SCT)
686 *am = VME_A64_SCT;
687 else if (transfer_mode == TSI148_BLT)
688 *am = VME_A64_BLT;
689 else if (transfer_mode == TSI148_MBLT)
690 *am = VME_A64_MBLT;
691 }
692 else if (addr_size == TSI148_CRCSR)
693 *am = VME_CR_CSR;
694 }
695
696 /*
697 * sub64hi() - Calculate the upper 32 bits of the 64 bit difference
698 * hi/lo0 - hi/lo1
699 */
700 static int sub64hi(unsigned int lo0, unsigned int hi0,
701 unsigned int lo1, unsigned int hi1)
702 {
703 if (lo0 < lo1)
704 return hi0 - hi1 - 1;
705 return hi0 - hi1;
706 }
707
708 /*
709 * sub64hi() - Calculate the upper 32 bits of the 64 bit sum
710 * hi/lo0 + hi/lo1
711 */
712 static int add64hi(unsigned int lo0, unsigned int hi0,
713 unsigned int lo1, unsigned int hi1)
714 {
715 if ((lo0 + lo1) < lo1)
716 return hi0 + hi1 + 1;
717 return hi0 + hi1;
718 }
719
720 /*
721 * TSI148 DMA support
722 */
723
724 /**
725 * tsi148_dma_get_status() - Get the status of a DMA channel
726 * @chan: DMA channel descriptor
727 *
728 **/
729 int tsi148_dma_get_status(struct dma_channel *chan)
730 {
731 return ioread32be(&chip->lcsr.dma[chan->num].dsta);
732 }
733
734 /**
735 * tsi148_dma_busy() - Get the busy status of a DMA channel
736 * @chan: DMA channel descriptor
737 *
738 **/
739 int tsi148_dma_busy(struct dma_channel *chan)
740 {
741 return tsi148_dma_get_status(chan) & TSI148_LCSR_DSTA_BSY;
742 }
743
744 /**
745 * tsi148_dma_done() - Get the done status of a DMA channel
746 * @chan: DMA channel descriptor
747 *
748 */
749 int tsi148_dma_done(struct dma_channel *chan)
750 {
751 return tsi148_dma_get_status(chan) & TSI148_LCSR_DSTA_DON;
752 }
753
754 /**
755 * tsi148_setup_dma_attributes() - Build the DMA attributes word
756 * @v2esst_mode: VME 2eSST transfer speed
757 * @data_width: VME data width (D16 or D32 only)
758 * @am: VME address modifier
759 *
760 * This function builds the DMA attributes word. All parameters are
761 * checked.
762 *
763 * NOTE: The function relies on the fact that the DSAT and DDAT registers have
764 * the same layout.
765 *
766 * Returns %EINVAL if any parameter is not consistent.
767 */
768 static int tsi148_setup_dma_attributes(enum vme_2esst_mode v2esst_mode,
769 enum vme_data_width data_width,
770 enum vme_address_modifier am)
771 {
772 unsigned int attrs = 0;
773 unsigned int addr_size;
774 unsigned int user_access;
775 unsigned int data_access;
776 unsigned int transfer_mode;
777
778 switch (v2esst_mode) {
779 case VME_SST160:
780 case VME_SST267:
781 case VME_SST320:
782 attrs |= ((v2esst_mode << TSI148_LCSR_DSAT_2eSSTM_SHIFT) &
783 TSI148_LCSR_DSAT_2eSSTM_M);
784 break;
785 default:
786 printk(KERN_ERR
787 "%s: invalid v2esst_mode %d\n",
788 __func__, v2esst_mode);
789 return -EINVAL;
790 }
791
792 switch (data_width) {
793 case VME_D16:
794 attrs |= ((TSI148_DW_16 << TSI148_LCSR_DSAT_DBW_SHIFT) &
795 TSI148_LCSR_DSAT_DBW_M);
796 break;
797 case VME_D32:
798 attrs |= ((TSI148_DW_32 << TSI148_LCSR_DSAT_DBW_SHIFT) &
799 TSI148_LCSR_DSAT_DBW_M);
800 break;
801 default:
802 printk(KERN_ERR
803 "%s: invalid data_width %d\n",
804 __func__, data_width);
805 return -EINVAL;
806 }
807
808 if (am_to_attr(am, &addr_size, &transfer_mode, &user_access,
809 &data_access)) {
810 printk(KERN_ERR
811 "%s: invalid am %x\n",
812 __func__, am);
813 return -EINVAL;
814 }
815
816 switch (transfer_mode) {
817 case TSI148_SCT:
818 case TSI148_BLT:
819 case TSI148_MBLT:
820 case TSI148_2eVME:
821 case TSI148_2eSST:
822 case TSI148_2eSSTB:
823 attrs |= ((transfer_mode << TSI148_LCSR_DSAT_TM_SHIFT) &
824 TSI148_LCSR_DSAT_TM_M);
825 break;
826 default:
827 printk(KERN_ERR
828 "%s: invalid transfer_mode %d\n",
829 __func__, transfer_mode);
830 return -EINVAL;
831 }
832
833 switch (user_access) {
834 case TSI148_SUPER:
835 attrs |= TSI148_LCSR_DSAT_SUP;
836 break;
837 case TSI148_USER:
838 break;
839 default:
840 printk(KERN_ERR
841 "%s: invalid user_access %d\n",
842 __func__, user_access);
843 return -EINVAL;
844 }
845
846 switch (data_access) {
847 case TSI148_PROG:
848 attrs |= TSI148_LCSR_DSAT_PGM;
849 break;
850 case TSI148_DATA:
851 break;
852 default:
853 printk(KERN_ERR
854 "%s: invalid data_access %d\n",
855 __func__, data_access);
856 return -EINVAL;
857 }
858
859 switch (addr_size) {
860 case TSI148_A16:
861 case TSI148_A24:
862 case TSI148_A32:
863 case TSI148_A64:
864 case TSI148_CRCSR:
865 case TSI148_USER1:
866 case TSI148_USER2:
867 case TSI148_USER3:
868 case TSI148_USER4:
869 attrs |= ((addr_size << TSI148_LCSR_DSAT_AMODE_SHIFT) &
870 TSI148_LCSR_DSAT_AMODE_M);
871 break;
872 default:
873 printk(KERN_ERR
874 "%s: invalid addr_size %d\n",
875 __func__, addr_size);
876 return -EINVAL;
877 }
878
879 return attrs;
880 }
881
882 /**
883 * tsi148_dma_setup_src() - Setup the source attributes for a DMA transfer
884 * @desc: DMA transfer descriptor
885 *
886 */
887 static int tsi148_dma_setup_src(struct vme_dma *desc)
888 {
889 int rc;
890
891 switch (desc->dir) {
892 case VME_DMA_TO_DEVICE: /* src = PCI */
893 rc = TSI148_LCSR_DSAT_TYP_PCI;
894 break;
895 case VME_DMA_FROM_DEVICE: /* src = VME */
896 rc = tsi148_setup_dma_attributes(desc->src.v2esst_mode,
897 desc->src.data_width,
898 desc->src.am);
899
900 if (rc >= 0)
901 rc |= TSI148_LCSR_DSAT_TYP_VME;
902
903 break;
904 default:
905 printk(KERN_ERR
906 "%s: invalid direction %d\n",
907 __func__, desc->dir);
908 rc = -EINVAL;
909 }
910
911 return rc;
912 }
913
914 /**
915 * tsi148_dma_setup_dst() - Setup the destination attributes for a DMA transfer
916 * @desc: DMA transfer descriptor
917 *
918 */
919 static int tsi148_dma_setup_dst(struct vme_dma *desc)
920 {
921 int rc;
922
923 switch (desc->dir) {
924 case VME_DMA_TO_DEVICE: /* dst = VME */
925 rc = tsi148_setup_dma_attributes(desc->dst.v2esst_mode,
926 desc->dst.data_width,
927 desc->dst.am);
928
929 if (rc >= 0)
930 rc |= TSI148_LCSR_DDAT_TYP_VME;
931
932 break;
933 case VME_DMA_FROM_DEVICE: /* dst = PCI */
934 rc = TSI148_LCSR_DDAT_TYP_PCI;
935 break;
936 default:
937 printk(KERN_ERR
938 "%s: invalid direction %d\n",
939 __func__, desc->dir);
940 rc = -EINVAL;
941 }
942
943 return rc;
944 }
945
946 /**
947 * tsi148_dma_setup_ctl() - Setup the DMA control word
948 * @desc: DMA transfer descriptor
949 *
950 */
951 static int tsi148_dma_setup_ctl(struct vme_dma *desc)
952 {
953 int rc = 0;
954
955 /* A little bit of checking. Could be done earlier, dunno. */
956 if ((desc->ctrl.vme_block_size < VME_DMA_BSIZE_32) ||
957 (desc->ctrl.vme_block_size > VME_DMA_BSIZE_4096))
958 return -EINVAL;
959
960 if ((desc->ctrl.vme_backoff_time < VME_DMA_BACKOFF_0) ||
961 (desc->ctrl.vme_backoff_time > VME_DMA_BACKOFF_64))
962 return -EINVAL;
963
964 if ((desc->ctrl.pci_block_size < VME_DMA_BSIZE_32) ||
965 (desc->ctrl.pci_block_size > VME_DMA_BSIZE_4096))
966 return -EINVAL;
967
968 if ((desc->ctrl.pci_backoff_time < VME_DMA_BACKOFF_0) ||
969 (desc->ctrl.pci_backoff_time > VME_DMA_BACKOFF_64))
970 return -EINVAL;
971
972 rc |= (desc->ctrl.vme_block_size << TSI148_LCSR_DCTL_VBKS_SHIFT) &
973 TSI148_LCSR_DCTL_VBKS_M;
974
975 rc |= (desc->ctrl.vme_backoff_time << TSI148_LCSR_DCTL_VBOT_SHIFT) &
976 TSI148_LCSR_DCTL_VBOT_M;
977
978 rc |= (desc->ctrl.pci_block_size << TSI148_LCSR_DCTL_PBKS_SHIFT) &
979 TSI148_LCSR_DCTL_PBKS_M;
980
981 rc |= (desc->ctrl.pci_backoff_time << TSI148_LCSR_DCTL_PBOT_SHIFT) &
982 TSI148_LCSR_DCTL_PBOT_M;
983
984 return rc;
985 }
986
987 /**
988 * tsi148_dma_free_chain() - Free all the linked HW DMA descriptors of a channel
989 * @chan: DMA channel
990 *
991 */
992 void tsi148_dma_free_chain(struct dma_channel *chan)
993 {
994 struct hw_desc_entry *hw_desc;
995 struct hw_desc_entry *tmp;
996 int count = 1;
997
998 list_for_each_entry_safe(hw_desc, tmp, &chan->hw_desc_list, list) {
999 pci_pool_free(dma_desc_pool, hw_desc->va, hw_desc->phys);
1000 list_del(&hw_desc->list);
1001 kfree(hw_desc);
1002 count++;
1003 }
1004 }
1005
1006 static inline int get_vmeaddr(struct vme_dma *desc, unsigned int *vme_addr)
1007 {
1008 switch (desc->dir) {
1009 case VME_DMA_TO_DEVICE: /* src = PCI - dst = VME */
1010 *vme_addr = desc->dst.addrl;
1011 return 0;
1012 case VME_DMA_FROM_DEVICE: /* src = VME - dst = PCI */
1013 *vme_addr = desc->src.addrl;
1014 return 0;
1015 default:
1016 return -EINVAL;
1017 }
1018 }
1019
1020 static int
1021 hwdesc_init(struct dma_channel *chan, dma_addr_t *phys,
1022 struct tsi148_dma_desc **virt, struct hw_desc_entry **hw_desc)
1023 {
1024 struct hw_desc_entry *entry;
1025
1026 /* Allocate a HW DMA descriptor from the pool */
1027 *virt = pci_pool_alloc(dma_desc_pool, GFP_KERNEL, phys);
1028 if (!*virt)
1029 return -ENOMEM;
1030
1031 /* keep the virt. and phys. addresses of the descriptor in a list */
1032 *hw_desc = kmalloc(sizeof(struct hw_desc_entry), GFP_KERNEL);
1033 if (!*hw_desc) {
1034 pci_pool_free(dma_desc_pool, *virt, *phys);
1035 return -ENOMEM;
1036 }
1037
1038 entry = *hw_desc;
1039 entry->va = *virt;
1040 entry->phys = *phys;
1041 list_add_tail(&entry->list, &chan->hw_desc_list);
1042
1043 return 0;
1044 }
1045
1046 /*
1047 * Setup the hardware descriptors for the link list.
1048 * Beware that the fields have to be setup in big endian mode.
1049 */
1050 static int
1051 tsi148_fill_dma_desc(struct dma_channel *chan, struct tsi148_dma_desc *tsi,
1052 unsigned int vme_addr, dma_addr_t dma_addr, unsigned int len,
1053 unsigned int dsat, unsigned int ddat)
1054 {
1055 struct vme_dma *desc = &chan->desc;
1056
1057 /* Setup the source and destination addresses */
1058 tsi->dsau = 0;
1059 tsi->ddau = 0;
1060
1061 switch (desc->dir) {
1062 case VME_DMA_TO_DEVICE: /* src = PCI - dst = VME */
1063 tsi->dsal = cpu_to_be32(dma_addr);
1064 tsi->ddal = cpu_to_be32(vme_addr);
1065 tsi->ddbs = cpu_to_be32(desc->dst.bcast_select);
1066 break;
1067
1068 case VME_DMA_FROM_DEVICE: /* src = VME - dst = PCI */
1069 tsi->dsal = cpu_to_be32(vme_addr);
1070 tsi->ddal = cpu_to_be32(dma_addr);
1071 tsi->ddbs = 0;
1072 break;
1073
1074 default:
1075 return -EINVAL;
1076 }
1077
1078 tsi->dcnt = cpu_to_be32(len);
1079 tsi->dsat = cpu_to_be32(dsat);
1080 tsi->ddat = cpu_to_be32(ddat);
1081
1082 /* By default behave as if we were at the end of the list */
1083 tsi->dnlau = 0;
1084 tsi->dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
1085
1086 return 0;
1087 }
1088
1089 #ifdef DEBUG_DMA
1090 static void tsi148_dma_debug_info(struct tsi148_dma_desc *tsi, int i, int j)
1091 {
1092 printk(KERN_DEBUG PFX "descriptor %d-%d @%p\n", i, j, tsi);
1093 printk(KERN_DEBUG PFX " src : %08x:%08x %08x\n",
1094 be32_to_cpu(tsi->dsau), be32_to_cpu(tsi->dsal),
1095 be32_to_cpu(tsi->dsat));
1096 printk(KERN_DEBUG PFX " dst : %08x:%08x %08x\n",
1097 be32_to_cpu(tsi->ddau), be32_to_cpu(tsi->ddal),
1098 be32_to_cpu(tsi->ddat));
1099 printk(KERN_DEBUG PFX " cnt : %08x\n", be32_to_cpu(tsi->dcnt));
1100 printk(KERN_DEBUG PFX " nxt : %08x:%08x\n",
1101 be32_to_cpu(tsi->dnlau), be32_to_cpu(tsi->dnlal));
1102 }
1103 #else
1104 static void tsi148_dma_debug_info(struct tsi148_dma_desc *tsi, int i, int j)
1105 {
1106 }
1107 #endif
1108
1109 /*
1110 * verbatim from the VME64 standard:
1111 * 2.3.7 Block Transfer Capabilities, p. 42.
1112 * RULE 2.12a: D08(EO), D16, D32 and MD32 block transfer cycles
1113 * (BLT) *MUST NOT* cross any 256 byte boundary.
1114 * RULE 2.78: MBLT cycles *MUST NOT* cross any 2048 byte boundary.
1115 */
1116 static inline int __tsi148_get_bshift(int am)
1117 {
1118 switch (am) {
1119 case VME_A64_MBLT:
1120 case VME_A32_USER_MBLT:
1121 case VME_A32_SUP_MBLT:
1122 case VME_A24_USER_MBLT:
1123 case VME_A24_SUP_MBLT:
1124 return 11;
1125 case VME_A64_BLT:
1126 case VME_A32_USER_BLT:
1127 case VME_A32_SUP_BLT:
1128 case VME_A40_BLT:
1129 case VME_A24_USER_BLT:
1130 case VME_A24_SUP_BLT:
1131 return 8;
1132 default:
1133 return 0;
1134 }
1135 }
1136
1137 static int tsi148_get_bshift(struct dma_channel *chan)
1138 {
1139 struct vme_dma *desc = &chan->desc;
1140 int am;
1141
1142 if (desc->dir == VME_DMA_FROM_DEVICE)
1143 am = desc->src.am;
1144 else
1145 am = desc->dst.am;
1146 return __tsi148_get_bshift(am);
1147 }
1148
1149 /* Note: block sizes are always powers of 2 */
1150 static inline unsigned long tsi148_get_bsize(int bshift)
1151 {
1152 return 1 << bshift;
1153 }
1154
1155 static inline unsigned long tsi148_get_bmask(unsigned long bsize)
1156 {
1157 return bsize - 1;
1158 }
1159
1160 /*
1161 * Add a certain chunk of data to the TSI DMA linked list.
1162 * Note that this function deals with physical addresses on the
1163 * host CPU and VME addresses on the VME bus.
1164 */
1165 static int
1166 tsi148_dma_link_add(struct dma_channel *chan, struct tsi148_dma_desc **virt,
1167 unsigned int vme_addr, dma_addr_t dma_addr, unsigned int size,
1168 int numpages, int index, int bshift, unsigned int dsat,
1169 unsigned int ddat)
1170
1171 {
1172 struct hw_desc_entry *hw_desc = NULL;
1173 struct tsi148_dma_desc *curr;
1174 struct tsi148_dma_desc *next = NULL;
1175 struct vme_dma *desc = &chan->desc;
1176 dma_addr_t phys_next;
1177 dma_addr_t dma;
1178 dma_addr_t dma_end;
1179 unsigned int vme;
1180 unsigned int vme_end;
1181 unsigned int len;
1182 int rc;
1183 int i = 0;
1184
1185 /*
1186 * The function expects **virt to be already initialised.
1187 * When calling this function in a loop, it will always set virt
1188 * to point to the next link in the chain, or to NULL when the
1189 * current link is the last in the chain.
1190 */
1191 BUG_ON(virt == NULL || *virt == NULL);
1192 curr = *virt;
1193
1194 vme = vme_addr;
1195 vme_end = vme_addr + size;
1196
1197 dma = dma_addr;
1198 dma_end = dma_addr + size;
1199
1200 len = size;
1201
1202 while (vme < vme_end && dma < dma_end) {
1203
1204 /* calculate the length up to the next block boundary */
1205 if (bshift) {
1206 unsigned long bsize = tsi148_get_bsize(bshift);
1207 unsigned long bmask = tsi148_get_bmask(bsize);
1208 unsigned int unaligned = vme & bmask;
1209
1210 len = bsize - unaligned;
1211 }
1212
1213 /* check the VME block won't overflow */
1214 if (dma + len > dma_end)
1215 len = dma_end - dma;
1216
1217 tsi148_fill_dma_desc(chan, curr, vme, dma, len, dsat, ddat);
1218
1219 /* increment the VME address unless novmeinc is set */
1220 if (!desc->novmeinc)
1221 vme += len;
1222 dma += len;
1223
1224 /* chain consecutive links together */
1225 if (index < numpages - 1 || dma < dma_end) {
1226 rc = hwdesc_init(chan, &phys_next, &next, &hw_desc);
1227 if (rc)
1228 return rc;
1229
1230 curr->dnlau = 0;
1231 curr->dnlal = cpu_to_be32(phys_next &
1232 TSI148_LCSR_DNLAL_DNLAL_M);
1233 }
1234
1235 tsi148_dma_debug_info(curr, index, i);
1236
1237 curr = next;
1238 i++;
1239 }
1240
1241 *virt = next;
1242 return 0;
1243 }
1244
1245 /**
1246 * tsi148_dma_setup_chain() - Setup the linked list of TSI148 DMA descriptors
1247 * @chan: DMA channel descriptor
1248 * @dsat: DMA source attributes
1249 * @ddat: DMA destination attributes
1250 *
1251 */
1252 static int tsi148_dma_setup_chain(struct dma_channel *chan,
1253 unsigned int dsat, unsigned int ddat)
1254 {
1255 int i;
1256 int rc;
1257 struct scatterlist *sg;
1258 struct vme_dma *desc = &chan->desc;
1259 dma_addr_t phys_start;
1260 struct tsi148_dma_desc *curr = NULL;
1261 struct hw_desc_entry *hw_desc = NULL;
1262 unsigned int vme_addr = 0;
1263 dma_addr_t dma_addr;
1264 unsigned int len;
1265 int bshift = tsi148_get_bshift(chan);
1266
1267 rc = hwdesc_init(chan, &phys_start, &curr, &hw_desc);
1268 if (rc)
1269 return rc;
1270
1271 rc = get_vmeaddr(desc, &vme_addr);
1272 if (rc)
1273 goto out_free;
1274
1275 for_each_sg(chan->sgl, sg, chan->sg_mapped, i) {
1276 dma_addr = sg_dma_address(sg);
1277 len = sg_dma_len(sg);
1278
1279 rc = tsi148_dma_link_add(chan, &curr, vme_addr, dma_addr, len,
1280 chan->sg_mapped, i, bshift, dsat, ddat);
1281 if (rc)
1282 goto out_free;
1283 /* For non incrementing DMA, reset the VME address */
1284 if (!desc->novmeinc)
1285 vme_addr += len;
1286 }
1287
1288 /* Now program the DMA registers with the first entry in the list */
1289 iowrite32be(0, &chip->lcsr.dma[chan->num].dma_desc.dnlau);
1290 iowrite32be(phys_start & TSI148_LCSR_DNLAL_DNLAL_M,
1291 &chip->lcsr.dma[chan->num].dma_desc.dnlal);
1292
1293 return 0;
1294
1295 out_free:
1296 tsi148_dma_free_chain(chan);
1297
1298
1299 return rc;
1300 }
1301
1302 /**
1303 * tsi148_dma_setup() - Setup a TSI148 DMA channel for a transfer
1304 * @chan: DMA channel descriptor
1305 *
1306 */
1307 int tsi148_dma_setup(struct dma_channel *chan)
1308 {
1309 int rc;
1310 struct vme_dma *desc = &chan->desc;
1311 unsigned int dsat;
1312 unsigned int ddat;
1313 unsigned int dctl;
1314
1315 /* Setup DMA source attributes */
1316 if ((rc = tsi148_dma_setup_src(desc)) < 0) {
1317 printk(KERN_ERR "%s: src setup failed\n", __func__);
1318 return rc;
1319 }
1320
1321 dsat = rc;
1322
1323 /* Setup DMA destination attributes */
1324 if ((rc = tsi148_dma_setup_dst(desc)) < 0) {
1325 printk(KERN_ERR "%s: dst setup failed\n", __func__);
1326 return rc;
1327 }
1328
1329 ddat = rc;
1330
1331 /* Setup DMA control */
1332 if ((rc = tsi148_dma_setup_ctl(desc)) < 0) {
1333 printk(KERN_ERR "%s: ctl setup failed\n", __func__);
1334 return rc;
1335 }
1336
1337 dctl = rc;
1338
1339 /* always use the scatter-gather list */
1340 chan->chained = 1;
1341 dctl &= ~TSI148_LCSR_DCTL_MOD;
1342 iowrite32be(dctl, &chip->lcsr.dma[chan->num].dctl);
1343 rc = tsi148_dma_setup_chain(chan, dsat, ddat);
1344
1345 return rc;
1346 }
1347
1348 /**
1349 * tsi148_dma_start() - Start DMA transfer on a channel
1350 * @chan: DMA channel descriptor
1351 *
1352 */
1353 void tsi148_dma_start(struct dma_channel *chan)
1354 {
1355 unsigned int dctl;
1356
1357 dctl = ioread32be(&chip->lcsr.dma[chan->num].dctl);
1358 dctl |= TSI148_LCSR_DCTL_DGO;
1359
1360 iowrite32be(dctl, &chip->lcsr.dma[chan->num].dctl);
1361 }
1362
1363 /**
1364 * tsi148_dma_abort() - Abort a DMA transfer
1365 * @chan: DMA channel descriptor
1366 *
1367 */
1368 void tsi148_dma_abort(struct dma_channel *chan)
1369 {
1370 unsigned int dctl;
1371
1372 dctl = ioread32be(&chip->lcsr.dma[chan->num].dctl);
1373 dctl |= TSI148_LCSR_DCTL_ABT;
1374
1375 iowrite32be(dctl, &chip->lcsr.dma[chan->num].dctl);
1376 }
1377
1378 /**
1379 * tsi148_dma_release() - Release resources used for a DMA transfer
1380 * @chan: DMA channel descriptor
1381 *
1382 * Only chained transfer are allocating memory. For direct transfer, there
1383 * is nothig to free.
1384 */
1385 void tsi148_dma_release(struct dma_channel *chan)
1386 {
1387 if (chan->chained)
1388 tsi148_dma_free_chain(chan);
1389 }
1390
1391 void __devexit tsi148_dma_exit(void)
1392 {
1393 pci_pool_destroy(dma_desc_pool);
1394 }
1395
1396 int __devinit tsi148_dma_init(void)
1397 {
1398 /*
1399 * Create the DMA chained descriptor pool.
1400 * Those descriptors must be 64-bit aligned as specified in the
1401 * TSI148 User Manual. Also do not allow descriptors to cross a
1402 * page boundary as the 2 pages may not be contiguous.
1403 */
1404 dma_desc_pool = pci_pool_create("vme_dma_desc_pool", vme_bridge->pdev,
1405 sizeof(struct tsi148_dma_desc),
1406 8, 4096);
1407
1408 if (dma_desc_pool == NULL) {
1409 printk(KERN_WARNING PFX "Failed to allocate DMA pool\n");
1410 return -ENOMEM;
1411 }
1412
1413 return 0;
1414
1415 }
1416
1417 /*
1418 * TSI148 window support
1419 */
1420
1421 /**
1422 * tsi148_setup_window_attributes() - Build the window attributes word
1423 * @v2esst_mode: VME 2eSST transfer speed
1424 * @data_width: VME data width (D16 or D32 only)
1425 * @am: VME address modifier
1426 *
1427 * This function builds the window attributes word. All parameters are
1428 * checked.
1429 *
1430 * Returns %EINVAL if any parameter is not consistent.
1431 */
1432 static int tsi148_setup_window_attributes(enum vme_2esst_mode v2esst_mode,
1433 enum vme_data_width data_width,
1434 enum vme_address_modifier am)
1435 {
1436 unsigned int attrs = 0;
1437 unsigned int addr_size;
1438 unsigned int user_access;
1439 unsigned int data_access;
1440 unsigned int transfer_mode;
1441
1442 switch (v2esst_mode) {
1443 case VME_SST160:
1444 case VME_SST267:
1445 case VME_SST320:
1446 attrs |= ((v2esst_mode << TSI148_LCSR_OTAT_2eSSTM_SHIFT) &
1447 TSI148_LCSR_OTAT_2eSSTM_M);
1448 break;
1449 default:
1450 return -EINVAL;
1451 }
1452
1453 switch (data_width) {
1454 case VME_D16:
1455 attrs |= ((TSI148_DW_16 << TSI148_LCSR_OTAT_DBW_SHIFT) &
1456 TSI148_LCSR_OTAT_DBW_M);
1457 break;
1458 case VME_D32:
1459 attrs |= ((TSI148_DW_32 << TSI148_LCSR_OTAT_DBW_SHIFT) &
1460 TSI148_LCSR_OTAT_DBW_M);
1461 break;
1462 default:
1463 return -EINVAL;
1464 }
1465
1466 if (am_to_attr(am, &addr_size, &transfer_mode, &user_access,
1467 &data_access))
1468 return -EINVAL;
1469
1470 switch (transfer_mode) {
1471 case TSI148_SCT:
1472 case TSI148_BLT:
1473 case TSI148_MBLT:
1474 case TSI148_2eVME:
1475 case TSI148_2eSST:
1476 case TSI148_2eSSTB:
1477 attrs |= ((transfer_mode << TSI148_LCSR_OTAT_TM_SHIFT) &
1478 TSI148_LCSR_OTAT_TM_M);
1479 break;
1480 default:
1481 return -EINVAL;
1482 }
1483
1484 switch (user_access) {
1485 case TSI148_SUPER:
1486 attrs |= TSI148_LCSR_OTAT_SUP;
1487 break;
1488 case TSI148_USER:
1489 break;
1490 default:
1491 return -EINVAL;
1492 }
1493
1494 switch (data_access) {
1495 case TSI148_PROG:
1496 attrs |= TSI148_LCSR_OTAT_PGM;
1497 break;
1498 case TSI148_DATA:
1499 break;
1500 default:
1501 return -EINVAL;
1502 }
1503
1504 switch (addr_size) {
1505 case TSI148_A16:
1506 case TSI148_A24:
1507 case TSI148_A32:
1508 case TSI148_A64:
1509 case TSI148_CRCSR:
1510 case TSI148_USER1:
1511 case TSI148_USER2:
1512 case TSI148_USER3:
1513 case TSI148_USER4:
1514 attrs |= ((addr_size << TSI148_LCSR_OTAT_AMODE_SHIFT) &
1515 TSI148_LCSR_OTAT_AMODE_M);
1516 break;
1517 default:
1518 return -EINVAL;
1519 }
1520
1521 return attrs;
1522 }
1523
1524 /**
1525 * tsi148_get_window_attr() - Get a hardware window attributes
1526 * @desc: Descriptor of the window (only the window number is used)
1527 *
1528 */
1529 void tsi148_get_window_attr(struct vme_mapping *desc)
1530 {
1531 int window_num = desc->window_num;
1532 unsigned int transfer_mode;
1533 unsigned int user_access;
1534 unsigned int data_access;
1535 unsigned int addr_size;
1536 int am = -1;
1537 struct tsi148_otrans *trans = &chip->lcsr.otrans[window_num];
1538 unsigned int otat;
1539 unsigned int otsau, otsal;
1540 unsigned int oteau, oteal;
1541 unsigned int otofu, otofl;
1542
1543 /* Get window Control & Bus attributes register */
1544 otat = ioread32be(&trans->otat);
1545
1546 if (otat & TSI148_LCSR_OTAT_EN)
1547 desc->window_enabled = 1;
1548
1549 if (!(otat & TSI148_LCSR_OTAT_MRPFD))
1550 desc->read_prefetch_enabled = 1;
1551
1552 desc->read_prefetch_size = (otat & TSI148_LCSR_OTAT_PFS_M) >>
1553 TSI148_LCSR_OTAT_PFS_SHIFT;
1554
1555 desc->v2esst_mode = (otat & TSI148_LCSR_OTAT_2eSSTM_M) >>
1556 TSI148_LCSR_OTAT_2eSSTM_SHIFT;
1557
1558 switch ((otat & TSI148_LCSR_OTAT_DBW_M) >> TSI148_LCSR_OTAT_DBW_SHIFT) {
1559 case TSI148_LCSR_OTAT_DBW_16:
1560 desc->data_width = VME_D16;
1561 break;
1562 case TSI148_LCSR_OTAT_DBW_32:
1563 desc->data_width = VME_D32;
1564 break;
1565 }
1566
1567 desc->bcast_select = ioread32be(&chip->lcsr.otrans[window_num].otbs);
1568
1569 /*
1570 * The VME address modifiers is encoded into the 4 following registers.
1571 * Here we then have to map that back to a single value - This is
1572 * coming out real ugly (sigh).
1573 */
1574 addr_size = (otat & TSI148_LCSR_OTAT_AMODE_M) >>
1575 TSI148_LCSR_OTAT_AMODE_SHIFT;
1576
1577 transfer_mode = (otat & TSI148_LCSR_OTAT_TM_M) >>
1578 TSI148_LCSR_OTAT_TM_SHIFT;
1579
1580 user_access = (otat & TSI148_LCSR_OTAT_SUP) ?
1581 TSI148_SUPER : TSI148_USER;
1582
1583 data_access = (otat & TSI148_LCSR_OTAT_PGM) ?
1584 TSI148_PROG : TSI148_DATA;
1585
1586 attr_to_am(addr_size, transfer_mode, user_access, data_access, &am);
1587
1588 if (am == -1)
1589 printk(KERN_WARNING PFX
1590 "%s - unsupported AM:\n"
1591 "\taddr size: %x TM: %x usr/sup: %d data/prg:%d\n",
1592 __func__, addr_size, transfer_mode, user_access,
1593 data_access);
1594
1595 desc->am = am;
1596
1597 /* Get window mappings */
1598 otsal = ioread32be(&chip->lcsr.otrans[window_num].otsal);
1599 otsau = ioread32be(&chip->lcsr.otrans[window_num].otsau);
1600 oteal = ioread32be(&chip->lcsr.otrans[window_num].oteal);
1601 oteau = ioread32be(&chip->lcsr.otrans[window_num].oteau);
1602 otofl = ioread32be(&chip->lcsr.otrans[window_num].otofl);
1603 otofu = ioread32be(&chip->lcsr.otrans[window_num].otofu);
1604
1605
1606 desc->pci_addrl = otsal;
1607 desc->pci_addru = otsau;
1608
1609 desc->sizel = oteal - otsal;
1610 desc->sizeu = sub64hi(oteal, oteau, otsal, otsau);
1611
1612 desc->vme_addrl = otofl + otsal;
1613
1614 if (addr_size == TSI148_A64)
1615 desc->vme_addru = add64hi(otofl, otofu, otsal, otsau);
1616 else
1617 desc->vme_addru = 0;
1618 }
1619
1620 /**
1621 * tsi148_create_window() - Create a PCI-VME window
1622 * @desc: Window descriptor
1623 *
1624 * Setup the TSI148 outbound window registers and enable the window for
1625 * use.
1626 *
1627 * Returns 0 on success, %EINVAL in case of wrong parameter.
1628 */
1629 int tsi148_create_window(struct vme_mapping *desc)
1630 {
1631 int window_num = desc->window_num;
1632 int rc;
1633 unsigned int addr;
1634 unsigned int size;
1635 struct tsi148_otrans *trans = &chip->lcsr.otrans[window_num];
1636 unsigned int otat = 0;
1637 unsigned int oteal, oteau;
1638 unsigned int otofl, otofu;
1639
1640 /*
1641 * Do some sanity checking on the window descriptor.
1642 * PCI address, VME address and window size should be aligned
1643 * on 64k boudaries. So round down the VME address and round up the
1644 * VME size to 64K boundaries.
1645 * The PCI address should already have been rounded.
1646 */
1647 addr = desc->vme_addrl;
1648 size = desc->sizel;
1649
1650 if (addr & 0xffff)
1651 addr = desc->vme_addrl & ~0xffff;
1652
1653 if (size & 0xffff)
1654 size = (desc->vme_addrl + desc->sizel + 0x10000) & ~0xffff;
1655
1656 desc->vme_addrl = addr;
1657 desc->sizel = size;
1658
1659 if (desc->pci_addrl & 0xffff)
1660 return -EINVAL;
1661
1662 /* Setup the window attributes */
1663 rc = tsi148_setup_window_attributes(desc->v2esst_mode,
1664 desc->data_width,
1665 desc->am);
1666
1667 if (rc < 0)
1668 return rc;
1669
1670 otat = (unsigned int)rc;
1671
1672 /* Enable the window */
1673 otat |= TSI148_LCSR_OTAT_EN;
1674
1675 if (desc->read_prefetch_enabled) {
1676 /* clear Read prefetch disable bit */
1677 otat &= ~TSI148_LCSR_OTAT_MRPFD;
1678 otat |= ((desc->read_prefetch_size <<
1679 TSI148_LCSR_OTAT_PFS_SHIFT) & TSI148_LCSR_OTAT_PFS_M);
1680 } else {
1681 /* Set Read prefetch disable bit */
1682 otat |= TSI148_LCSR_OTAT_MRPFD;
1683 }
1684
1685 /* Setup the VME 2eSST broadcast select */
1686 iowrite32be(desc->bcast_select & TSI148_LCSR_OTBS_M,
1687 &trans->otbs);
1688
1689 /* Setup the PCI side start address */
1690 iowrite32be(desc->pci_addrl & TSI148_LCSR_OTSAL_M,
1691 &trans->otsal);
1692 iowrite32be(desc->pci_addru, &trans->otsau);
1693
1694 /*
1695 * Setup the PCI side end address
1696 * Note that 'oteal' is formed by the upper 2 bytes common to the
1697 * addresses in the last 64K chunk of the window.
1698 */
1699 oteal = (desc->pci_addrl + desc->sizel - 1) & ~0xffff;
1700 oteau = add64hi(desc->pci_addrl, desc->pci_addru,
1701 desc->sizel, desc->sizeu);
1702 iowrite32be(oteal, &trans->oteal);
1703 iowrite32be(oteau, &trans->oteau);
1704
1705 /* Setup the VME offset */
1706 otofl = desc->vme_addrl - desc->pci_addrl;
1707 otofu = sub64hi(desc->vme_addrl, desc->vme_addru,
1708 desc->pci_addrl, desc->pci_addru);
1709 iowrite32be(otofl, &trans->otofl);
1710 iowrite32be(otofu, &trans->otofu);
1711
1712 /*
1713 * Finally, write the window attributes, also enabling the
1714 * window
1715 */
1716 iowrite32be(otat, &trans->otat);
1717 desc->window_enabled = 1;
1718
1719 return 0;
1720 }
1721
1722 /**
1723 * tsi148_remove_window() - Disable a PCI-VME window
1724 * @desc: Window descriptor (only the window number is used)
1725 *
1726 * Disable the PCI-VME window specified in the descriptor.
1727 */
1728 void tsi148_remove_window(struct vme_mapping *desc)
1729 {
1730 int window_num = desc->window_num;
1731 struct tsi148_otrans *trans = &chip->lcsr.otrans[window_num];
1732
1733 /* Clear the attribute register thus disabling the window */
1734 iowrite32be(0, &trans->otat);
1735
1736 /* Wipe the window registers */
1737 iowrite32be(0, &trans->otsal);
1738 iowrite32be(0, &trans->otsau);
1739 iowrite32be(0, &trans->oteal);
1740 iowrite32be(0, &trans->oteau);
1741 iowrite32be(0, &trans->otofl);
1742 iowrite32be(0, &trans->otofu);
1743 iowrite32be(0, &trans->otbs);
1744
1745 desc->window_enabled = 0;
1746 }
1747
1748 /**
1749 * am_to_crgattrs() - Convert address modifier to CRG Attributes
1750 * @am: Address modifier
1751 */
1752 static int am_to_crgattrs(enum vme_address_modifier am)
1753 {
1754 unsigned int attrs = 0;
1755 unsigned int addr_size;
1756 unsigned int user_access;
1757 unsigned int data_access;
1758 unsigned int transfer_mode;
1759
1760 if (am_to_attr(am, &addr_size, &transfer_mode, &user_access,
1761 &data_access))
1762 return -EINVAL;
1763
1764 switch (addr_size) {
1765 case TSI148_A16:
1766 attrs |= TSI148_LCSR_CRGAT_AS_16;
1767 break;
1768 case TSI148_A24:
1769 attrs |= TSI148_LCSR_CRGAT_AS_24;
1770 break;
1771 case TSI148_A32:
1772 attrs |= TSI148_LCSR_CRGAT_AS_32;
1773 break;
1774 case TSI148_A64:
1775 attrs |= TSI148_LCSR_CRGAT_AS_64;
1776 break;
1777 default:
1778 return -EINVAL;
1779 }
1780
1781 switch (data_access) {
1782 case TSI148_PROG:
1783 attrs |= TSI148_LCSR_CRGAT_PGM;
1784 break;
1785 case TSI148_DATA:
1786 attrs |= TSI148_LCSR_CRGAT_DATA;
1787 break;
1788 default:
1789 return -EINVAL;
1790 }
1791
1792 switch (user_access) {
1793 case TSI148_SUPER:
1794 attrs |= TSI148_LCSR_CRGAT_SUPR;
1795 break;
1796 case TSI148_USER:
1797 attrs |= TSI148_LCSR_CRGAT_NPRIV;
1798 break;
1799 default:
1800 return -EINVAL;
1801 }
1802
1803 return attrs;
1804 }
1805
1806 /**
1807 * tsi148_setup_crg() - Setup the CRG inbound mapping
1808 * @vme_base: VME base address for the CRG mapping
1809 * @am: Address modifier for the mapping
1810 */
1811 int __devinit tsi148_setup_crg(unsigned int vme_base,
1812 enum vme_address_modifier am)
1813 {
1814 int attrs;
1815
1816 iowrite32be(0, &chip->lcsr.cbau);
1817 iowrite32be(vme_base, &chip->lcsr.cbal);
1818
1819 attrs = am_to_crgattrs(am);
1820
1821 if (attrs < 0) {
1822 iowrite32be(0, &chip->lcsr.cbal);
1823 return -1;
1824 }
1825
1826 attrs |= TSI148_LCSR_CRGAT_EN;
1827
1828 iowrite32be(attrs, &chip->lcsr.crgat);
1829
1830 return 0;
1831 }
1832
1833 /**
1834 * tsi148_disable_crg() - Disable the CRG VME mapping
1835 *
1836 */
1837 void __devexit tsi148_disable_crg(struct tsi148_chip *regs)
1838 {
1839 iowrite32be(0, &regs->lcsr.crgat);
1840 iowrite32be(0, &regs->lcsr.cbau);
1841 iowrite32be(0, &regs->lcsr.cbal);
1842 }
1843
1844
1845 /**
1846 * tsi148_quiesce() - Shutdown the TSI148 chip
1847 *
1848 * Put VME bridge in quiescent state. Disable all decoders,
1849 * clear all interrupts.
1850 */
1851 void __devexit tsi148_quiesce(struct tsi148_chip *regs)
1852 {
1853 int i;
1854 unsigned int val;
1855
1856 /* Shutdown all inbound and outbound windows. */
1857 for (i = 0; i < TSI148_NUM_OUT_WINDOWS; i++) {
1858 iowrite32be(0, &regs->lcsr.itrans[i].itat);
1859 iowrite32be(0, &regs->lcsr.otrans[i].otat);
1860 }
1861
1862 for (i= 0; i < TSI148_NUM_DMA_CHANNELS; i++) {
1863 iowrite32be(0, &regs->lcsr.dma[i].dma_desc.dnlau);
1864 iowrite32be(0, &regs->lcsr.dma[i].dma_desc.dnlal);
1865 iowrite32be(0, &regs->lcsr.dma[i].dma_desc.dcnt);
1866 }
1867
1868 /* Shutdown Location monitor. */
1869 iowrite32be(0, &regs->lcsr.lmat);
1870
1871 /* Shutdown CRG map. */
1872 tsi148_disable_crg(regs);
1873
1874 /* Clear error status. */
1875 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, &regs->lcsr.edpat);
1876 iowrite32be(TSI148_LCSR_VEAT_VESCL, &regs->lcsr.veat);
1877 iowrite32be(TSI148_LCSR_PCSR_SRTO | TSI148_LCSR_PCSR_SRTE |
1878 TSI148_LCSR_PCSR_DTTE | TSI148_LCSR_PCSR_MRCE,
1879 &regs->lcsr.pstat);
1880
1881 /* Clear VIRQ interrupt (if any) */
1882 iowrite32be(TSI148_LCSR_VICR_IRQC, &regs->lcsr.vicr);
1883
1884 /* Disable and clear all interrupts. */
1885 iowrite32be(0, &regs->lcsr.inteo);
1886 iowrite32be(0xffffffff, &regs->lcsr.intc);
1887 iowrite32be(0xffffffff, &regs->lcsr.inten);
1888
1889 /* Map all Interrupts to PCI INTA */
1890 iowrite32be(0, &regs->lcsr.intm1);
1891 iowrite32be(0, &regs->lcsr.intm2);
1892
1893 /*
1894 * Set bus master timeout
1895 * The timeout overrides the DMA block size if set too low.
1896 * Enable release on request so that there will not be a re-arbitration
1897 * for each transfer.
1898 */
1899 val = ioread32be(&regs->lcsr.vmctrl);
1900 val &= ~(TSI148_LCSR_VMCTRL_VTON_M | TSI148_LCSR_VMCTRL_VREL_M);
1901 val |= (TSI148_LCSR_VMCTRL_VTON_512 | TSI148_LCSR_VMCTRL_VREL_T_D_R);
1902 iowrite32be(val, &regs->lcsr.vmctrl);
1903 }
1904
1905 /*
1906 *
1907 */
1908
1909 /**
1910 * tsi148_init() - Chip initialization
1911 * @regs: Chip registers base address
1912 *
1913 */
1914 void __devinit tsi148_init(struct tsi148_chip *regs)
1915 {
1916 unsigned int vme_stat_reg;
1917
1918 /* Clear board fail, and power-up reset */
1919 vme_stat_reg = ioread32be(&regs->lcsr.vstat);
1920 vme_stat_reg &= ~TSI148_LCSR_VSTAT_BDFAIL;
1921 vme_stat_reg |= TSI148_LCSR_VSTAT_CPURST;
1922 iowrite32be(vme_stat_reg, &regs->lcsr.vstat);
1923
1924 /* Store the chip base address */
1925 chip = regs;
1926 }
Drivers, Libraries and test programs for Linux and LynxOS