?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
vmod/vmodttl: fixed bug related to luns not ordered and/or not starting from zero.
[ht-drivers.git] / vmebridge / driver / tsi148.h
blobc925194094f300c1ad4549b7cb2ab182bab443d7
1 /*
2 * tsi148.h - Low level support for the Tundra TSI148 PCI-VME Bridge Chip
3 *
4 * Copyright (c) 2009 Sebastien Dugue
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Borrowed and modified from the tsi148.h file from:
12 * Tom Armistead, Updated and maintained by Ajit Prem and
13 * copyrighted 2004 Motorola Inc.
14 *
15 */
16
17 #ifndef _TSI148_H
18 #define _TSI148_H
19
20 #ifdef CONFIG_PROC_FS
21 #include <linux/proc_fs.h>
22 #endif /* CONFIG_PROC_FS */
23
24 #include <asm-generic/iomap.h>
25
26 #include "vme_dma.h"
27 #include "vmebus.h"
28
29 /*
30 * Define the number of each resources that the Tsi148 supports.
31 */
32 #define TSI148_NUM_OUT_WINDOWS 8 /* Number of outbound windows */
33 #define TSI148_NUM_IN_WINDOWS 8 /* Nuber of inbound windows */
34 #define TSI148_NUM_DMA_CHANNELS 2 /* Number of DMA channels */
35 #define TSI148_NUM_MAILBOXES 4 /* Number of mailboxes */
36 #define TSI148_NUM_SEMAPHORES 8 /* Number of semaphores */
37
38 #define PCI_VENDOR_ID_TUNDRA 0x10e3
39 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
40
41 /*
42 * VME constants for the TSI148
43 */
44 /* Address mode */
45 enum tsi148_address_size {
46 TSI148_A16 = 0,
47 TSI148_A24 = 1,
48 TSI148_A32 = 2,
49 TSI148_A64 = 4,
50 TSI148_CRCSR = 5,
51 TSI148_USER1 = 8,
52 TSI148_USER2 = 9,
53 TSI148_USER3 = 10,
54 TSI148_USER4 = 11
55 };
56
57 /* VME access type definitions */
58 enum tsi148_user_access_type {
59 TSI148_USER = 0,
60 TSI148_SUPER
61 };
62
63 enum tsi148_data_access_type {
64 TSI148_DATA = 0,
65 TSI148_PROG
66 };
67
68 /* VME transfer mode */
69 enum tsi148_transfer_mode {
70 TSI148_SCT = 0,
71 TSI148_BLT,
72 TSI148_MBLT,
73 TSI148_2eVME,
74 TSI148_2eSST,
75 TSI148_2eSSTB
76 };
77
78 enum tsi148_data_width {
79 TSI148_DW_16 = 0,
80 TSI148_DW_32
81 };
82
83
84
85 /*
86 * TSI148 CRG registers structure.
87 *
88 * The TSI148 Combined Register Group (CRG) consists of the following
89 * combination of registers:
90 *
91 * 0x000 PCFS - PCI Configuration Space Registers
92 * 0x100 LCSR - Local Control and Status Registers
93 * 0x600 GCSR - Global Control and Status Registers
94 * 0xff4 CR/CSR - Subset of Configuration ROM / Control and Status Registers
95 */
96
97
98 /*
99 * Misc structures used in the LCSR registers description
100 */
101
102 /* Outbound translation registers in LCSR group */
103 struct tsi148_otrans {
104 unsigned int otsau; /* Starting address */
105 unsigned int otsal;
106 unsigned int oteau; /* Ending address */
107 unsigned int oteal;
108 unsigned int otofu; /* Translation offset */
109 unsigned int otofl;
110 unsigned int otbs; /* 2eSST broadcast select */
111 unsigned int otat; /* Attributes */
112 };
113
114 /* Inbound translation registers in LCSR group */
115 struct tsi148_itrans {
116 unsigned int itsau; /* Starting address */
117 unsigned int itsal;
118 unsigned int iteau; /* Ending address */
119 unsigned int iteal;
120 unsigned int itofu; /* Translation offset */
121 unsigned int itofl;
122 unsigned int itat; /* Attributes */
123 unsigned char reserved[4];
124 };
125
126 /* DMAC linked-list descriptor */
127 struct tsi148_dma_desc {
128 unsigned int dsau; /* Source Address */
129 unsigned int dsal;
130 unsigned int ddau; /* Destination Address */
131 unsigned int ddal;
132 unsigned int dsat; /* Source attributes */
133 unsigned int ddat; /* Destination attributes */
134 unsigned int dnlau; /* Next link address */
135 unsigned int dnlal;
136 unsigned int dcnt; /* Byte count */
137 unsigned int ddbs; /* 2eSST Broadcast select */
138 };
139
140 /* DMAC registers in LCSR group */
141 struct tsi148_dma {
142 unsigned int dctl; /* Control */
143 unsigned int dsta; /* Status */
144 unsigned int dcsau; /* Current Source address */
145 unsigned int dcsal;
146 unsigned int dcdau; /* Current Destination address */
147 unsigned int dcdal;
148 unsigned int dclau; /* Current Link address */
149 unsigned int dclal;
150 struct tsi148_dma_desc dma_desc;
151 unsigned char reserved[0x38];
152 };
153
154 /*
155 *
156 * PCFS register group - PCI configuration space
157 *
158 */
159 struct tsi148_pcfs {
160 unsigned short veni;
161 unsigned short devi;
162 unsigned short cmmd;
163 unsigned short stat;
164 unsigned int rev_class;
165 unsigned char clsz;
166 unsigned char mlat;
167 unsigned char head;
168 unsigned char reserved0[1];
169 unsigned int mbarl;
170 unsigned int mbaru;
171 unsigned char reserved1[20];
172 unsigned short subv;
173 unsigned short subi;
174 unsigned char reserved2[4];
175 unsigned char capp;
176 unsigned char reserved3[7];
177 unsigned char intl;
178 unsigned char intp;
179 unsigned char mngn;
180 unsigned char mxla;
181
182 /*
183 * offset 0x40 - PCI-X Capp PCIXCD/NCAPP/PCIXCAP
184 * offset 0x44 - PCI-X Capp PCIXSTAT
185 */
186 unsigned char pcix_cap_id;
187 unsigned char pcix_next_cap_ptr;
188 unsigned short pcix_command;
189 unsigned int pcix_status;
190
191 /*
192 * offset 0x48 to 0xff - Reserved
193 */
194 unsigned char reserved4[0xb8];
195 };
196
197 /*
198 *
199 * LCSR registers group definition
200 *
201 * offsets are given relative to the Combined Register Group (CRG)
202 *
203 */
204 struct tsi148_lcsr {
205
206 /* Outbound translations offset 0x100 */
207 struct tsi148_otrans otrans[TSI148_NUM_OUT_WINDOWS];
208
209 /*
210 * VME bus IACK registers offset 0x200
211 *
212 * Note: Even though the registers are defined as 32-bits in
213 * the spec, we only want to issue 8-bit IACK cycles on the bus.
214 */
215 unsigned char viack[8 * 4];
216
217 /* RMW registers offset 0x220 */
218 unsigned int rmwau;
219 unsigned int rmwal;
220 unsigned int rmwen;
221 unsigned int rmwc;
222 unsigned int rmws;
223
224 /* VMEbus control offset 0x234 */
225 unsigned int vmctrl;
226 unsigned int vctrl;
227 unsigned int vstat;
228
229 /* PCI status offset 0x240 */
230 unsigned int pstat;
231 unsigned char pstatrsvd[0xc];
232
233 /* VME filter offset 0x250 */
234 unsigned int vmefl;
235 unsigned char vmeflrsvd[0xc];
236
237 /* VME exception offset 0x260 */
238 unsigned int veau;
239 unsigned int veal;
240 unsigned int veat;
241 unsigned char vearsvd[0x4];
242
243 /* PCI error offset 0x270 */
244 unsigned int edpau;
245 unsigned int edpal;
246 unsigned int edpxa;
247 unsigned int edpxs;
248 unsigned int edpat;
249 unsigned char edparsvd[0x7c];
250
251 /* Inbound Translations offset 0x300 */
252 struct tsi148_itrans itrans[TSI148_NUM_IN_WINDOWS];
253
254 /* Inbound Translation for GCSR offset 0x400 */
255 unsigned int gbau;
256 unsigned int gbal;
257 unsigned int gcsrat;
258
259 /* Inbound Translation for CRG offset 0x40C */
260 unsigned int cbau;
261 unsigned int cbal;
262 unsigned int crgat;
263
264 /* Inbound Translation for CR/CSR offset 0x418 */
265 unsigned int crou;
266 unsigned int crol;
267 unsigned int crat;
268
269 /* Inbound Translation for Location Monitor offset 0x424 */
270 unsigned int lmbau;
271 unsigned int lmbal;
272 unsigned int lmat;
273
274 /* VME bus Interrupt Control offset 0x430 */
275 unsigned int bcu;
276 unsigned int bcl;
277 unsigned int bpgtr;
278 unsigned int bpctr;
279 unsigned int vicr;
280
281 unsigned char vicrsvd[0x4];
282
283 /* Local Bus Interrupt Control offset 0x448 */
284 unsigned int inten;
285 unsigned int inteo;
286 unsigned int ints;
287 unsigned int intc;
288 unsigned int intm1;
289 unsigned int intm2;
290
291 unsigned char reserved[0xa0];
292
293 /* DMA Controllers offset 500 */
294 struct tsi148_dma dma[TSI148_NUM_DMA_CHANNELS];
295 };
296
297 /*
298 *
299 * GCSR registers group definition
300 *
301 * offsets are given relative to the Combined Register Group (CRG)
302 *
303 */
304 struct tsi148_gcsr {
305 /* Header offset 0x600 */
306 unsigned short devi;
307 unsigned short veni;
308
309 /* Control offset 0x604 */
310 unsigned short ctrl;
311 unsigned char ga;
312 unsigned char revid;
313
314 /* Semaphores offset 0x608
315 *
316 * semaphores 3/2/1/0 are at offset 0x608
317 * 7/6/5/4 are at offset 0x60C
318 */
319 unsigned char semaphore[TSI148_NUM_SEMAPHORES];
320
321 /* Mail Boxes offset 0x610 */
322 unsigned int mbox[TSI148_NUM_MAILBOXES];
323 };
324
325
326 /*
327 *
328 * CR/CSR registers group definition
329 *
330 * offsets are given relative to the Combined Register Group (CRG)
331 *
332 */
333 struct tsi148_crcsr {
334 unsigned int csrbcr; /* offset 0xff4 */
335 unsigned int csrbsr; /* offset 0xff8 */
336 unsigned int cbar; /* offset 0xffc */
337 };
338
339
340 /*
341 *
342 * TSI148 CRG definition
343 *
344 */
345 struct tsi148_chip {
346 struct tsi148_pcfs pcfs;
347 struct tsi148_lcsr lcsr;
348 struct tsi148_gcsr gcsr;
349 unsigned char reserved[0xFF4 - 0x61C - 4];
350 struct tsi148_crcsr crcsr;
351 };
352
353
354 /*
355 * TSI148 Register Bit Definitions
356 */
357
358 /*
359 * PFCS Register Set
360 */
361
362 /* Command/Status Registers (CRG + $004) */
363 #define TSI148_PCFS_CMMD_SERR (1<<8) /* SERR_L out pin ssys err */
364 #define TSI148_PCFS_CMMD_PERR (1<<6) /* PERR_L out pin parity */
365 #define TSI148_PCFS_CMMD_MSTR (1<<2) /* PCI bus master */
366 #define TSI148_PCFS_CMMD_MEMSP (1<<1) /* PCI mem space access */
367 #define TSI148_PCFS_CMMD_IOSP (1<<0) /* PCI I/O space enable */
368
369 #define TSI148_PCFS_STAT_DPE (1<<15) /* Detected Parity Error */
370 #define TSI148_PCFS_STAT_SIGSE (1<<14) /* Signalled System Error */
371 #define TSI148_PCFS_STAT_RCVMA (1<<13) /* Received Master Abort */
372 #define TSI148_PCFS_STAT_RCVTA (1<<12) /* Received Target Abort */
373 #define TSI148_PCFS_STAT_SIGTA (1<<11) /* Signalled Target Abort */
374 #define TSI148_PCFS_STAT_SELTIM (3<<9) /* DELSEL Timing */
375 #define TSI148_PCFS_STAT_DPED (1<<8) /* Data Parity Err Reported */
376 #define TSI148_PCFS_STAT_FAST (1<<7) /* Fast back-to-back Cap */
377 #define TSI148_PCFS_STAT_P66M (1<<5) /* 66 MHz Capable */
378 #define TSI148_PCFS_STAT_CAPL (1<<4) /* Capab List - address $34 */
379
380 /* Revision ID/Class Code Registers (CRG +$008) */
381 #define TSI148_PCFS_BCLAS_M (0xFF<<24) /* Class ID */
382 #define TSI148_PCFS_SCLAS_M (0xFF<<16) /* Sub-Class ID */
383 #define TSI148_PCFS_PIC_M (0xFF<<8) /* Sub-Class ID */
384 #define TSI148_PCFS_REVID_M (0xFF<<0) /* Rev ID */
385
386 /* Cache Line Size/ Master Latency Timer/ Header Type Registers (CRG + $00C) */
387 #define TSI148_PCFS_HEAD_M (0xFF<<16) /* Master Lat Timer */
388 #define TSI148_PCFS_MLAT_M (0xFF<<8) /* Master Lat Timer */
389 #define TSI148_PCFS_CLSZ_M (0xFF<<0) /* Cache Line Size */
390
391 /* Memory Base Address Lower Reg (CRG + $010) */
392 #define TSI148_PCFS_MBARL_BASEL_M (0xFFFFF<<12) /* Base Addr Lower Mask */
393 #define TSI148_PCFS_MBARL_PRE (1<<3) /* Prefetch */
394 #define TSI148_PCFS_MBARL_MTYPE_M (3<<1) /* Memory Type Mask */
395 #define TSI148_PCFS_MBARL_IOMEM (1<<0) /* I/O Space Indicator */
396
397 /* PCI-X Capabilities Register (CRG + $040) */
398 #define TSI148_PCFS_PCIXCAP_MOST_M (7<<4) /* Max outstanding Split Tran */
399 #define TSI148_PCFS_PCIXCAP_MMRBC_M (3<<2) /* Max Mem Read byte cnt */
400 #define TSI148_PCFS_PCIXCAP_ERO (1<<1) /* Enable Relaxed Ordering */
401 #define TSI148_PCFS_PCIXCAP_DPERE (1<<0) /* Data Parity Recover Enable */
402
403 /* PCI-X Status Register (CRG +$054) */
404 #define TSI148_PCFS_PCIXSTAT_RSCEM (1<<29) /* Recieved Split Comp Error */
405 #define TSI148_PCFS_PCIXSTAT_DMCRS_M (7<<26) /* max Cumulative Read Size */
406 #define TSI148_PCFS_PCIXSTAT_DMOST_M (7<<23) /* max outstanding Split Tr */
407 #define TSI148_PCFS_PCIXSTAT_DMMRC_M (3<<21) /* max mem read byte count */
408 #define TSI148_PCFS_PCIXSTAT_DC (1<<20) /* Device Complexity */
409 #define TSI148_PCFS_PCIXSTAT_USC (1<<19) /* Unexpected Split comp */
410 #define TSI148_PCFS_PCIXSTAT_SCD (1<<18) /* Split completion discard */
411 #define TSI148_PCFS_PCIXSTAT_133C (1<<17) /* 133MHz capable */
412 #define TSI148_PCFS_PCIXSTAT_64D (1<<16) /* 64 bit device */
413 #define TSI148_PCFS_PCIXSTAT_BN_M (0xFF<<8) /* Bus number */
414 #define TSI148_PCFS_PCIXSTAT_DN_M (0x1F<<3) /* Device number */
415 #define TSI148_PCFS_PCIXSTAT_FN_M (7<<0) /* Function Number */
416
417 /*
418 * LCSR Registers
419 */
420
421 /* Outbound Translation Starting Address Lower */
422 #define TSI148_LCSR_OTSAL_M (0xFFFF<<16) /* Mask */
423
424 /* Outbound Translation Ending Address Lower */
425 #define TSI148_LCSR_OTEAL_M (0xFFFF<<16) /* Mask */
426
427 /* Outbound Translation Offset Lower */
428 #define TSI148_LCSR_OTOFFL_M (0xFFFF<<16) /* Mask */
429
430 /* Outbound Translation 2eSST Broadcast Select */
431 #define TSI148_LCSR_OTBS_M (0xFFFFF<<0) /* Mask */
432
433 /* Outbound Translation Attribute */
434 #define TSI148_LCSR_OTAT_EN (1<<31) /* Window Enable */
435 #define TSI148_LCSR_OTAT_MRPFD (1<<18) /* Prefetch Disable */
436
437 #define TSI148_LCSR_OTAT_PFS_SHIFT 16
438 #define TSI148_LCSR_OTAT_PFS_M (3<<16) /* Prefetch Size Mask */
439 #define TSI148_LCSR_OTAT_PFS_2 (0<<16) /* 2 Cache Lines P Size */
440 #define TSI148_LCSR_OTAT_PFS_4 (1<<16) /* 4 Cache Lines P Size */
441 #define TSI148_LCSR_OTAT_PFS_8 (2<<16) /* 8 Cache Lines P Size */
442 #define TSI148_LCSR_OTAT_PFS_16 (3<<16) /* 16 Cache Lines P Size */
443
444 #define TSI148_LCSR_OTAT_2eSSTM_SHIFT 11
445 #define TSI148_LCSR_OTAT_2eSSTM_M (7<<11) /* 2eSST Xfer Rate Mask */
446 #define TSI148_LCSR_OTAT_2eSSTM_160 (0<<11) /* 160MB/s 2eSST Xfer Rate */
447 #define TSI148_LCSR_OTAT_2eSSTM_267 (1<<11) /* 267MB/s 2eSST Xfer Rate */
448 #define TSI148_LCSR_OTAT_2eSSTM_320 (2<<11) /* 320MB/s 2eSST Xfer Rate */
449
450 #define TSI148_LCSR_OTAT_TM_SHIFT 8
451 #define TSI148_LCSR_OTAT_TM_M (7<<8) /* Xfer Protocol Mask */
452 #define TSI148_LCSR_OTAT_TM_SCT (0<<8) /* SCT Xfer Protocol */
453 #define TSI148_LCSR_OTAT_TM_BLT (1<<8) /* BLT Xfer Protocol */
454 #define TSI148_LCSR_OTAT_TM_MBLT (2<<8) /* MBLT Xfer Protocol */
455 #define TSI148_LCSR_OTAT_TM_2eVME (3<<8) /* 2eVME Xfer Protocol */
456 #define TSI148_LCSR_OTAT_TM_2eSST (4<<8) /* 2eSST Xfer Protocol */
457 #define TSI148_LCSR_OTAT_TM_2eSSTB (5<<8) /* 2eSST Bcast Xfer Protocol */
458
459 #define TSI148_LCSR_OTAT_DBW_SHIFT 6
460 #define TSI148_LCSR_OTAT_DBW_M (3<<6) /* Max Data Width */
461 #define TSI148_LCSR_OTAT_DBW_16 (0<<6) /* 16-bit Data Width */
462 #define TSI148_LCSR_OTAT_DBW_32 (1<<6) /* 32-bit Data Width */
463
464 #define TSI148_LCSR_OTAT_SUP (1<<5) /* Supervisory Access */
465 #define TSI148_LCSR_OTAT_PGM (1<<4) /* Program Access */
466
467 #define TSI148_LCSR_OTAT_AMODE_SHIFT 0
468 #define TSI148_LCSR_OTAT_AMODE_M (0xf<<0) /* Address Mode Mask */
469 #define TSI148_LCSR_OTAT_AMODE_A16 (0<<0) /* A16 Address Space */
470 #define TSI148_LCSR_OTAT_AMODE_A24 (1<<0) /* A24 Address Space */
471 #define TSI148_LCSR_OTAT_AMODE_A32 (2<<0) /* A32 Address Space */
472 #define TSI148_LCSR_OTAT_AMODE_A64 (4<<0) /* A32 Address Space */
473 #define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */
474 #define TSI148_LCSR_OTAT_AMODE_USER1 (8<<0) /* User1 Address Space */
475 #define TSI148_LCSR_OTAT_AMODE_USER2 (9<<0) /* User2 Address Space */
476 #define TSI148_LCSR_OTAT_AMODE_USER3 (0xa<<0) /* User3 Address Space */
477 #define TSI148_LCSR_OTAT_AMODE_USER4 (0xb<<0) /* User4 Address Space */
478
479 /* VME Master Control Register CRG+$234 */
480 #define TSI148_LCSR_VMCTRL_VSA (1<<27) /* VMEbus Stop Ack */
481 #define TSI148_LCSR_VMCTRL_VS (1<<26) /* VMEbus Stop */
482 #define TSI148_LCSR_VMCTRL_DHB (1<<25) /* Device Has Bus */
483 #define TSI148_LCSR_VMCTRL_DWB (1<<24) /* Device Wants Bus */
484
485 #define TSI148_LCSR_VMCTRL_RMWEN (1<<20) /* RMW Enable */
486 #define TSI148_LCSR_VMCTRL_A64DS (1<<16) /* A64 Data strobes */
487
488 #define TSI148_LCSR_VMCTRL_VTOFF_M (7<<12) /* VMEbus Master Time off */
489 #define TSI148_LCSR_VMCTRL_VTOFF_0 (0<<12) /* 0us */
490 #define TSI148_LCSR_VMCTRL_VTOFF_1 (1<<12) /* 1us */
491 #define TSI148_LCSR_VMCTRL_VTOFF_2 (2<<12) /* 2us */
492 #define TSI148_LCSR_VMCTRL_VTOFF_4 (3<<12) /* 4us */
493 #define TSI148_LCSR_VMCTRL_VTOFF_8 (4<<12) /* 8us */
494 #define TSI148_LCSR_VMCTRL_VTOFF_16 (5<<12) /* 16us */
495 #define TSI148_LCSR_VMCTRL_VTOFF_32 (6<<12) /* 32us */
496 #define TSI148_LCSR_VMCTRL_VTOFF_64 (7<<12) /* 64us */
497
498 #define TSI148_LCSR_VMCTRL_VTON_M (7<<8) /* VMEbus Master Time On */
499 #define TSI148_LCSR_VMCTRL_VTON_4 (0<<8) /* 4us */
500 #define TSI148_LCSR_VMCTRL_VTON_8 (1<<8) /* 8us */
501 #define TSI148_LCSR_VMCTRL_VTON_16 (2<<8) /* 16us */
502 #define TSI148_LCSR_VMCTRL_VTON_32 (3<<8) /* 32us */
503 #define TSI148_LCSR_VMCTRL_VTON_64 (4<<8) /* 64us */
504 #define TSI148_LCSR_VMCTRL_VTON_128 (5<<8) /* 128us */
505 #define TSI148_LCSR_VMCTRL_VTON_256 (6<<8) /* 256us */
506 #define TSI148_LCSR_VMCTRL_VTON_512 (7<<8) /* 512us */
507
508 #define TSI148_LCSR_VMCTRL_VREL_M (3<<3) /* Master Rel Mode Mask */
509 #define TSI148_LCSR_VMCTRL_VREL_T_D (0<<3) /* Time on or Done */
510 #define TSI148_LCSR_VMCTRL_VREL_T_R_D (1<<3) /* Time on and REQ or Done */
511 #define TSI148_LCSR_VMCTRL_VREL_T_B_D (2<<3) /* Time on and BCLR or Done */
512 #define TSI148_LCSR_VMCTRL_VREL_T_D_R (3<<3) /* Time on or Done and REQ */
513
514 #define TSI148_LCSR_VMCTRL_VFAIR (1<<2) /* VMEbus Master Fair Mode */
515 #define TSI148_LCSR_VMCTRL_VREQL_M (3<<0) /* VMEbus Master Req Level Mask */
516
517 /* VMEbus Control Register CRG+$238 */
518 #define TSI148_LCSR_VCTRL_DLT_M (0xF<<24) /* Deadlock Timer */
519 #define TSI148_LCSR_VCTRL_DLT_OFF (0<<24) /* Deadlock Timer Off */
520 #define TSI148_LCSR_VCTRL_DLT_16 (1<<24) /* 16 VCLKS */
521 #define TSI148_LCSR_VCTRL_DLT_32 (2<<24) /* 32 VCLKS */
522 #define TSI148_LCSR_VCTRL_DLT_64 (3<<24) /* 64 VCLKS */
523 #define TSI148_LCSR_VCTRL_DLT_128 (4<<24) /* 128 VCLKS */
524 #define TSI148_LCSR_VCTRL_DLT_256 (5<<24) /* 256 VCLKS */
525 #define TSI148_LCSR_VCTRL_DLT_512 (6<<24) /* 512 VCLKS */
526 #define TSI148_LCSR_VCTRL_DLT_1024 (7<<24) /* 1024 VCLKS */
527 #define TSI148_LCSR_VCTRL_DLT_2048 (8<<24) /* 2048 VCLKS */
528 #define TSI148_LCSR_VCTRL_DLT_4096 (9<<24) /* 4096 VCLKS */
529 #define TSI148_LCSR_VCTRL_DLT_8192 (0xa<<24) /* 8192 VCLKS */
530 #define TSI148_LCSR_VCTRL_DLT_16384 (0xb<<24) /* 16384 VCLKS */
531 #define TSI148_LCSR_VCTRL_DLT_32768 (0xc<<24) /* 32768 VCLKS */
532
533 #define TSI148_LCSR_VCTRL_NERBB (1<<20) /* No Early Release of Bus Busy */
534
535 #define TSI148_LCSR_VCTRL_SRESET (1<<17) /* System Reset */
536 #define TSI148_LCSR_VCTRL_LRESET (1<<16) /* Local Reset */
537
538 #define TSI148_LCSR_VCTRL_SFAILAI (1<<15) /* SYSFAIL Auto Slot ID */
539 #define TSI148_LCSR_VCTRL_BID_M (0x1F<<8) /* Broadcast ID Mask */
540
541 #define TSI148_LCSR_VCTRL_ATOEN (1<<7) /* Arbiter Time-out Enable */
542 #define TSI148_LCSR_VCTRL_ROBIN (1<<6) /* VMEbus Round Robin */
543
544 #define TSI148_LCSR_VCTRL_GTO_M (0xf<<0) /* VMEbus Global Time-out Mask */
545 #define TSI148_LCSR_VCTRL_GTO_8 (0<<0) /* 8 us */
546 #define TSI148_LCSR_VCTRL_GTO_16 (1<<0) /* 16 us */
547 #define TSI148_LCSR_VCTRL_GTO_32 (2<<0) /* 32 us */
548 #define TSI148_LCSR_VCTRL_GTO_64 (3<<0) /* 64 us */
549 #define TSI148_LCSR_VCTRL_GTO_128 (4<<0) /* 128 us */
550 #define TSI148_LCSR_VCTRL_GTO_256 (5<<0) /* 256 us */
551 #define TSI148_LCSR_VCTRL_GTO_512 (6<<0) /* 512 us */
552 #define TSI148_LCSR_VCTRL_GTO_1024 (7<<0) /* 1024 us */
553 #define TSI148_LCSR_VCTRL_GTO_2048 (7<<0) /* 2048 us */
554
555 /* VMEbus Status Register CRG + $23C */
556 #define TSI148_LCSR_VSTAT_CPURST (1<<15) /* Clear power up reset */
557 #define TSI148_LCSR_VSTAT_BDFAIL (1<<14) /* Board fail */
558 #define TSI148_LCSR_VSTAT_PURSTS (1<<12) /* Power up reset status */
559 #define TSI148_LCSR_VSTAT_BDFAILS (1<<11) /* Board Fail Status */
560 #define TSI148_LCSR_VSTAT_SYSFAILS (1<<10) /* System Fail Status */
561 #define TSI148_LCSR_VSTAT_ACFAILS (1<<9) /* AC fail status */
562 #define TSI148_LCSR_VSTAT_SCONS (1<<8) /* System Cont Status */
563 #define TSI148_LCSR_VSTAT_GAP (1<<5) /* Geographic Addr Parity */
564 #define TSI148_LCSR_VSTAT_GA_M (0x1F<<0) /* Geographic Addr Mask */
565
566 /* PCI Configuration Status Register CRG+$240 */
567 #define TSI148_LCSR_PCSR_SRTO (7<<24) /* */
568 #define TSI148_LCSR_PCSR_SRTT (1<<22) /* */
569 #define TSI148_LCSR_PCSR_CCTM (1<<21) /* */
570 #define TSI148_LCSR_PCSR_DRQ (1<<20) /* */
571 #define TSI148_LCSR_PCSR_DTTT (1<<19) /* */
572 #define TSI148_LCSR_PCSR_MRCT (1<<18) /* */
573 #define TSI148_LCSR_PCSR_MRC (1<<17) /* */
574 #define TSI148_LCSR_PCSR_SBH (1<<16) /* */
575 #define TSI148_LCSR_PCSR_SRTE (1<<10) /* */
576 #define TSI148_LCSR_PCSR_DTTE (1<<9) /* */
577 #define TSI148_LCSR_PCSR_MRCE (1<<8) /* */
578 #define TSI148_LCSR_PCSR_REQ64S (1<<6) /* Request 64 status set */
579 #define TSI148_LCSR_PCSR_M66ENS (1<<5) /* M66ENS 66Mhz enable */
580 #define TSI148_LCSR_PCSR_FRAMES (1<<4) /* Frame Status */
581 #define TSI148_LCSR_PCSR_IRDYS (1<<3) /* IRDY status */
582 #define TSI148_LCSR_PCSR_DEVSELS (1<<2) /* DEVL status */
583 #define TSI148_LCSR_PCSR_STOPS (1<<1) /* STOP status */
584 #define TSI148_LCSR_PCSR_TRDYS (1<<0) /* TRDY status */
585
586 /* VMEbus Exception Attributes Register CRG+0x268 */
587 #define TSI148_LCSR_VEAT_VES (1<<31)
588 #define TSI148_LCSR_VEAT_VEOF (1<<30)
589 #define TSI148_LCSR_VEAT_VESCL (1<<29)
590 #define TSI148_LCSR_VEAT_2EOT (1<<21)
591 #define TSI148_LCSR_VEAT_2EST (1<<20)
592 #define TSI148_LCSR_VEAT_BERR (1<<19)
593 #define TSI148_LCSR_VEAT_LWORD (1<<18)
594 #define TSI148_LCSR_VEAT_WRITE (1<<17)
595 #define TSI148_LCSR_VEAT_IACK (1<<16)
596 #define TSI148_LCSR_VEAT_DS1 (1<<15)
597 #define TSI148_LCSR_VEAT_DS0 (1<<14)
598 #define TSI148_LCSR_VEAT_AM_SHIFT 8
599 #define TSI148_LCSR_VEAT_AM (0x3f<<8)
600 #define TSI148_LCSR_VEAT_XAM (0xff<<0)
601
602 /* PCI/X Error diagnostic attributes register CRG + 0x280 */
603 #define TSI148_LCSR_EDPAT_EDPST (1<<31)
604 #define TSI148_LCSR_EDPAT_EDPOF (1<<30)
605 #define TSI148_LCSR_EDPAT_EDPCL (1<<29)
606 #define TSI148_LCSR_EDPAT_SCD (1<<17)
607 #define TSI148_LCSR_EDPAT_USC (1<<16)
608 #define TSI148_LCSR_EDPAT_SRT (1<<15)
609 #define TSI148_LCSR_EDPAT_SCEM (1<<14)
610 #define TSI148_LCSR_EDPAT_DPED (1<<13)
611 #define TSI148_LCSR_EDPAT_DPE (1<<12)
612 #define TSI148_LCSR_EDPAT_MRC (1<<11)
613 #define TSI148_LCSR_EDPAT_RMA (1<<10)
614 #define TSI148_LCSR_EDPAT_RTA (1<<9)
615 #define TSI148_LCSR_EDPAT_DTT (1<<8)
616 #define TSI148_LCSR_EDPAT_CBEA_M (0xf<<4)
617 #define TSI148_LCSR_EDPAT_COMM_M (0xf<<0)
618
619 /* Inbound Translation Starting Address Lower */
620 #define TSI148_LCSR_ITSAL6432_M (0xFFFF<<16) /* Mask */
621 #define TSI148_LCSR_ITSAL24_M (0x00FFF<<12) /* Mask */
622 #define TSI148_LCSR_ITSAL16_M (0x0000FFF<<4) /* Mask */
623
624 /* Inbound Translation Ending Address Lower */
625 #define TSI148_LCSR_ITEAL6432_M (0xFFFF<<16) /* Mask */
626 #define TSI148_LCSR_ITEAL24_M (0x00FFF<<12) /* Mask */
627 #define TSI148_LCSR_ITEAL16_M (0x0000FFF<<4) /* Mask */
628
629 /* Inbound Translation Offset Lower */
630 #define TSI148_LCSR_ITOFFL6432_M (0xFFFF<<16) /* Mask */
631 #define TSI148_LCSR_ITOFFL24_M (0xFFFFF<<12) /* Mask */
632 #define TSI148_LCSR_ITOFFL16_M (0xFFFFFFF<<4) /* Mask */
633
634 /* Inbound Translation Attribute */
635 #define TSI148_LCSR_ITAT_EN (1<<31) /* Window Enable */
636 #define TSI148_LCSR_ITAT_TH (1<<18) /* Prefetch Threshold */
637
638 #define TSI148_LCSR_ITAT_VFS_M (3<<16) /* Virtual FIFO Size Mask */
639 #define TSI148_LCSR_ITAT_VFS_64 (0<<16) /* 64 bytes Virtual FIFO Size */
640 #define TSI148_LCSR_ITAT_VFS_128 (1<<16) /* 128 bytes Virtual FIFO Sz */
641 #define TSI148_LCSR_ITAT_VFS_256 (2<<16) /* 256 bytes Virtual FIFO Sz */
642 #define TSI148_LCSR_ITAT_VFS_512 (3<<16) /* 512 bytes Virtual FIFO Sz */
643
644 #define TSI148_LCSR_ITAT_2eSSTM_M (7<<12) /* 2eSST Xfer Rate Mask */
645 #define TSI148_LCSR_ITAT_2eSSTM_160 (0<<12) /* 160MB/s 2eSST Xfer Rate */
646 #define TSI148_LCSR_ITAT_2eSSTM_267 (1<<12) /* 267MB/s 2eSST Xfer Rate */
647 #define TSI148_LCSR_ITAT_2eSSTM_320 (2<<12) /* 320MB/s 2eSST Xfer Rate */
648
649 #define TSI148_LCSR_ITAT_2eSSTB (1<<11) /* 2eSST Bcast Xfer Protocol */
650 #define TSI148_LCSR_ITAT_2eSST (1<<10) /* 2eSST Xfer Protocol */
651 #define TSI148_LCSR_ITAT_2eVME (1<<9) /* 2eVME Xfer Protocol */
652 #define TSI148_LCSR_ITAT_MBLT (1<<8) /* MBLT Xfer Protocol */
653 #define TSI148_LCSR_ITAT_BLT (1<<7) /* BLT Xfer Protocol */
654
655 #define TSI148_LCSR_ITAT_AS_M (7<<4) /* Address Space Mask */
656 #define TSI148_LCSR_ITAT_AS_A16 (0<<4) /* A16 Address Space */
657 #define TSI148_LCSR_ITAT_AS_A24 (1<<4) /* A24 Address Space */
658 #define TSI148_LCSR_ITAT_AS_A32 (2<<4) /* A32 Address Space */
659 #define TSI148_LCSR_ITAT_AS_A64 (4<<4) /* A64 Address Space */
660
661 #define TSI148_LCSR_ITAT_SUPR (1<<3) /* Supervisor Access */
662 #define TSI148_LCSR_ITAT_NPRIV (1<<2) /* Non-Priv (User) Access */
663 #define TSI148_LCSR_ITAT_PGM (1<<1) /* Program Access */
664 #define TSI148_LCSR_ITAT_DATA (1<<0) /* Data Access */
665
666 /* GCSR Base Address Lower Address CRG +$404 */
667 #define TSI148_LCSR_GBAL_M (0x7FFFFFF<<5) /* Mask */
668
669 /* GCSR Attribute Register CRG + $408 */
670 #define TSI148_LCSR_GCSRAT_EN (1<<7) /* Enable access to GCSR */
671
672 #define TSI148_LCSR_GCSRAT_AS_M (7<<4) /* Address Space Mask */
673 #define TSI148_LCSR_GCSRAT_AS_16 (0<<4) /* Address Space 16 */
674 #define TSI148_LCSR_GCSRAT_AS_24 (1<<4) /* Address Space 24 */
675 #define TSI148_LCSR_GCSRAT_AS_32 (2<<4) /* Address Space 32 */
676 #define TSI148_LCSR_GCSRAT_AS_64 (4<<4) /* Address Space 64 */
677
678 #define TSI148_LCSR_GCSRAT_SUPR (1<<3) /* Sup set -GCSR decoder */
679 #define TSI148_LCSR_GCSRAT_NPRIV (1<<2) /* Non-Privliged set - CGSR */
680 #define TSI148_LCSR_GCSRAT_PGM (1<<1) /* Program set - GCSR decoder */
681 #define TSI148_LCSR_GCSRAT_DATA (1<<0) /* DATA set GCSR decoder */
682
683 /* CRG Base Address Lower Address CRG + $410 */
684 #define TSI148_LCSR_CBAL_M (0xFFFFF<<12)
685
686 /* CRG Attribute Register CRG + $414 */
687 #define TSI148_LCSR_CRGAT_EN (1<<7) /* Enable PRG Access */
688
689 #define TSI148_LCSR_CRGAT_AS_M (7<<4) /* Address Space */
690 #define TSI148_LCSR_CRGAT_AS_16 (0<<4) /* Address Space 16 */
691 #define TSI148_LCSR_CRGAT_AS_24 (1<<4) /* Address Space 24 */
692 #define TSI148_LCSR_CRGAT_AS_32 (2<<4) /* Address Space 32 */
693 #define TSI148_LCSR_CRGAT_AS_64 (4<<4) /* Address Space 64 */
694
695 #define TSI148_LCSR_CRGAT_SUPR (1<<3) /* Supervisor Access */
696 #define TSI148_LCSR_CRGAT_NPRIV (1<<2) /* Non-Privliged(User) Access */
697 #define TSI148_LCSR_CRGAT_PGM (1<<1) /* Program Access */
698 #define TSI148_LCSR_CRGAT_DATA (1<<0) /* Data Access */
699
700 /* CR/CSR Offset Lower Register CRG + $41C */
701 #define TSI148_LCSR_CROL_M (0x1FFF<<19) /* Mask */
702
703 /* CR/CSR Attribute register CRG + $420 */
704 #define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */
705
706 /* Location Monitor base address lower register CRG + $428 */
707 #define TSI148_LCSR_LMBAL_M (0x7FFFFFF<<5) /* Mask */
708
709 /* Location Monitor Attribute Register CRG + $42C */
710 #define TSI148_LCSR_LMAT_EN (1<<7) /* Enable Location Monitor */
711
712 #define TSI148_LCSR_LMAT_AS_M (7<<4) /* Address Space MASK */
713 #define TSI148_LCSR_LMAT_AS_16 (0<<4) /* A16 */
714 #define TSI148_LCSR_LMAT_AS_24 (1<<4) /* A24 */
715 #define TSI148_LCSR_LMAT_AS_32 (2<<4) /* A32 */
716 #define TSI148_LCSR_LMAT_AS_64 (4<<4) /* A64 */
717
718 #define TSI148_LCSR_LMAT_SUPR (1<<3) /* Supervisor Access */
719 #define TSI148_LCSR_LMAT_NPRIV (1<<2) /* Non-Priv (User) Access */
720 #define TSI148_LCSR_LMAT_PGM (1<<1) /* Program Access */
721 #define TSI148_LCSR_LMAT_DATA (1<<0) /* Data Access */
722
723 /* Broadcast Pulse Generator Timer Register CRG + $438 */
724 #define TSI148_LCSR_BPGTR_BPGT_M (0xFFFF<<0) /* Mask */
725
726 /* Broadcast Programmable Clock Timer Register CRG + $43C */
727 #define TSI148_LCSR_BPCTR_BPCT_M (0xFFFFFF<<0) /* Mask */
728
729 /* VMEbus Interrupt Control Register CRG + $440 */
730 #define TSI148_LCSR_VICR_CNTS_M (3<<30) /* Cntr Source MASK */
731 #define TSI148_LCSR_VICR_CNTS_DIS (0<<30) /* Cntr Disable */
732 #define TSI148_LCSR_VICR_CNTS_IRQ1 (1<<30) /* IRQ1 to Cntr */
733 #define TSI148_LCSR_VICR_CNTS_IRQ2 (2<<30) /* IRQ2 to Cntr */
734
735 #define TSI148_LCSR_VICR_EDGIS_M (3<<28) /* Edge interupt MASK */
736 #define TSI148_LCSR_VICR_EDGIS_DIS (0<<28) /* Edge interupt Disable */
737 #define TSI148_LCSR_VICR_EDGIS_IRQ1 (1<<28) /* IRQ1 to Edge */
738 #define TSI148_LCSR_VICR_EDGIS_IRQ2 (2<<28) /* IRQ2 to Edge */
739
740 #define TSI148_LCSR_VICR_IRQ1F_M (3<<26) /* IRQ1* Function MASK */
741 #define TSI148_LCSR_VICR_IRQ1F_NORM (1<<26) /* Normal */
742 #define TSI148_LCSR_VICR_IRQ1F_PULSE (2<<26) /* Pulse Generator */
743 #define TSI148_LCSR_VICR_IRQ1F_PROG (3<<26) /* Programmable Clock */
744 #define TSI148_LCSR_VICR_IRQ1F_1U (4<<26) /* 1.02us Clock */
745
746 #define TSI148_LCSR_VICR_IRQ2F_M (3<<24) /* IRQ2* Function MASK */
747 #define TSI148_LCSR_VICR_IRQ2F_NORM (1<<24) /* Normal */
748 #define TSI148_LCSR_VICR_IRQ2F_PULSE (2<<24) /* Pulse Generator */
749 #define TSI148_LCSR_VICR_IRQ2F_PROG (3<<24) /* Programmable Clock */
750 #define TSI148_LCSR_VICR_IRQ2F_1U (4<<24) /* 1us Clock */
751
752 #define TSI148_LCSR_VICR_BIP (1<<23) /* Broadcast Interrupt Pulse */
753 #define TSI148_LCSR_VICR_BIPS (1<<22) /* BIP status */
754
755 #define TSI148_LCSR_VICR_IRQC (1<<15) /* VMEbus IRQ Clear */
756
757 #define TSI148_LCSR_VICR_IRQLS (7<<12) /* VMEbus IRQ Level Status */
758
759
760 #define TSI148_LCSR_VICR_IRQS (1<<11) /* VMEbus IRQ Status */
761
762 #define TSI148_LCSR_VICR_IRQL_M (7<<8) /* VMEbus SW IRQ Level Mask */
763 #define TSI148_LCSR_VICR_IRQL_1 (1<<8) /* VMEbus SW IRQ Level 1 */
764 #define TSI148_LCSR_VICR_IRQL_2 (2<<8) /* VMEbus SW IRQ Level 2 */
765 #define TSI148_LCSR_VICR_IRQL_3 (3<<8) /* VMEbus SW IRQ Level 3 */
766 #define TSI148_LCSR_VICR_IRQL_4 (4<<8) /* VMEbus SW IRQ Level 4 */
767 #define TSI148_LCSR_VICR_IRQL_5 (5<<8) /* VMEbus SW IRQ Level 5 */
768 #define TSI148_LCSR_VICR_IRQL_6 (6<<8) /* VMEbus SW IRQ Level 6 */
769 #define TSI148_LCSR_VICR_IRQL_7 (7<<8) /* VMEbus SW IRQ Level 7 */
770
771 #define TSI148_LCSR_VICR_STID_M (0xFF<<0) /* Status/ID Mask */
772
773 /* Interrupt Enable Register CRG + $448 */
774 /* Interrupt Enable Out Register CRG + $44c */
775 /* Interrupt Status Register CRG + $450 */
776 /* Interrupt Clear Register CRG + $454 */
777 /* Note: IRQ1-7 bits are reserved in INTC */
778 #define TSI148_LCSR_INT_DMA_SHIFT 24
779 #define TSI148_LCSR_INT_DMA_M (3<<24) /* DMAC mask */
780 #define TSI148_LCSR_INT_DMA1 (1<<25) /* DMAC 1 */
781 #define TSI148_LCSR_INT_DMA0 (1<<24) /* DMAC 0 */
782
783 #define TSI148_LCSR_INT_LM_SHIFT 20
784 #define TSI148_LCSR_INT_LM_M (0xf<<20)
785 #define TSI148_LCSR_INT_LM3 (1<<23) /* Location Monitor 3 */
786 #define TSI148_LCSR_INT_LM2 (1<<22) /* Location Monitor 2 */
787 #define TSI148_LCSR_INT_LM1 (1<<21) /* Location Monitor 1 */
788 #define TSI148_LCSR_INT_LM0 (1<<20) /* Location Monitor 0 */
789
790 #define TSI148_LCSR_INT_MB_SHIFT 16
791 #define TSI148_LCSR_INT_MB_M (0xf<<16)
792 #define TSI148_LCSR_INT_MB3 (1<<19) /* Mail Box 3 */
793 #define TSI148_LCSR_INT_MB2 (1<<18) /* Mail Box 2 */
794 #define TSI148_LCSR_INT_MB1 (1<<17) /* Mail Box 1 */
795 #define TSI148_LCSR_INT_MB0 (1<<16) /* Mail Box 0 */
796
797 #define TSI148_LCSR_INT_PERR (1<<13) /* VMEbus Error */
798 #define TSI148_LCSR_INT_VERR (1<<12) /* VMEbus Access Time-out */
799 #define TSI148_LCSR_INT_VIE (1<<11) /* VMEbus IRQ Edge */
800 #define TSI148_LCSR_INT_IACK (1<<10) /* IACK */
801 #define TSI148_LCSR_INT_SYSFL (1<<9) /* System Fail */
802 #define TSI148_LCSR_INT_ACFL (1<<8) /* AC Fail */
803
804 #define TSI148_LCSR_INT_IRQM (0x7f<<1)
805 #define TSI148_LCSR_INT_IRQ7 (1<<7) /* IRQ7 */
806 #define TSI148_LCSR_INT_IRQ6 (1<<6) /* IRQ6 */
807 #define TSI148_LCSR_INT_IRQ5 (1<<5) /* IRQ5 */
808 #define TSI148_LCSR_INT_IRQ4 (1<<4) /* IRQ4 */
809 #define TSI148_LCSR_INT_IRQ3 (1<<3) /* IRQ3 */
810 #define TSI148_LCSR_INT_IRQ2 (1<<2) /* IRQ2 */
811 #define TSI148_LCSR_INT_IRQ1 (1<<1) /* IRQ1 */
812
813 /* Interrupt Map Register 1 CRG + $458 */
814 #define TSI148_LCSR_INTM1_DMA1M_M (3<<18) /* DMA 1 */
815 #define TSI148_LCSR_INTM1_DMA0M_M (3<<16) /* DMA 0 */
816 #define TSI148_LCSR_INTM1_LM3M_M (3<<14) /* Location Monitor 3 */
817 #define TSI148_LCSR_INTM1_LM2M_M (3<<12) /* Location Monitor 2 */
818 #define TSI148_LCSR_INTM1_LM1M_M (3<<10) /* Location Monitor 1 */
819 #define TSI148_LCSR_INTM1_LM0M_M (3<<8) /* Location Monitor 0 */
820 #define TSI148_LCSR_INTM1_MB3M_M (3<<6) /* Mail Box 3 */
821 #define TSI148_LCSR_INTM1_MB2M_M (3<<4) /* Mail Box 2 */
822 #define TSI148_LCSR_INTM1_MB1M_M (3<<2) /* Mail Box 1 */
823 #define TSI148_LCSR_INTM1_MB0M_M (3<<0) /* Mail Box 0 */
824
825 /* Interrupt Map Register 2 CRG + $45C */
826 #define TSI148_LCSR_INTM2_PERRM_M (3<<26) /* PCI Bus Error */
827 #define TSI148_LCSR_INTM2_VERRM_M (3<<24) /* VMEbus Error */
828 #define TSI148_LCSR_INTM2_VIEM_M (3<<22) /* VMEbus IRQ Edge */
829 #define TSI148_LCSR_INTM2_IACKM_M (3<<20) /* IACK */
830 #define TSI148_LCSR_INTM2_SYSFLM_M (3<<18) /* System Fail */
831 #define TSI148_LCSR_INTM2_ACFLM_M (3<<16) /* AC Fail */
832 #define TSI148_LCSR_INTM2_IRQ7M_M (3<<14) /* IRQ7 */
833 #define TSI148_LCSR_INTM2_IRQ6M_M (3<<12) /* IRQ6 */
834 #define TSI148_LCSR_INTM2_IRQ5M_M (3<<10) /* IRQ5 */
835 #define TSI148_LCSR_INTM2_IRQ4M_M (3<<8) /* IRQ4 */
836 #define TSI148_LCSR_INTM2_IRQ3M_M (3<<6) /* IRQ3 */
837 #define TSI148_LCSR_INTM2_IRQ2M_M (3<<4) /* IRQ2 */
838 #define TSI148_LCSR_INTM2_IRQ1M_M (3<<2) /* IRQ1 */
839
840 /* DMA Control (0-1) Registers CRG + $500 */
841 #define TSI148_LCSR_DCTL_ABT (1<<27) /* Abort */
842 #define TSI148_LCSR_DCTL_PAU (1<<26) /* Pause */
843 #define TSI148_LCSR_DCTL_DGO (1<<25) /* DMA Go */
844
845 #define TSI148_LCSR_DCTL_MOD (1<<23) /* Mode */
846 #define TSI148_LCSR_DCTL_VFAR (1<<17) /* VME Flush on Aborted Read */
847 #define TSI148_LCSR_DCTL_PFAR (1<<16) /* PCI Flush on Aborted Read */
848
849 #define TSI148_LCSR_DCTL_VBKS_SHIFT 12
850 #define TSI148_LCSR_DCTL_VBKS_M (7<<12) /* VMEbus block Size MASK */
851 #define TSI148_LCSR_DCTL_VBKS_32 (0<<12) /* VMEbus block Size 32 */
852 #define TSI148_LCSR_DCTL_VBKS_64 (1<<12) /* VMEbus block Size 64 */
853 #define TSI148_LCSR_DCTL_VBKS_128 (2<<12) /* VMEbus block Size 128 */
854 #define TSI148_LCSR_DCTL_VBKS_256 (3<<12) /* VMEbus block Size 256 */
855 #define TSI148_LCSR_DCTL_VBKS_512 (4<<12) /* VMEbus block Size 512 */
856 #define TSI148_LCSR_DCTL_VBKS_1024 (5<<12) /* VMEbus block Size 1024 */
857 #define TSI148_LCSR_DCTL_VBKS_2048 (6<<12) /* VMEbus block Size 2048 */
858 #define TSI148_LCSR_DCTL_VBKS_4096 (7<<12) /* VMEbus block Size 4096 */
859
860 #define TSI148_LCSR_DCTL_VBOT_SHIFT 8
861 #define TSI148_LCSR_DCTL_VBOT_M (7<<8) /* VMEbus back-off MASK */
862 #define TSI148_LCSR_DCTL_VBOT_0 (0<<8) /* VMEbus back-off 0us */
863 #define TSI148_LCSR_DCTL_VBOT_1 (1<<8) /* VMEbus back-off 1us */
864 #define TSI148_LCSR_DCTL_VBOT_2 (2<<8) /* VMEbus back-off 2us */
865 #define TSI148_LCSR_DCTL_VBOT_4 (3<<8) /* VMEbus back-off 4us */
866 #define TSI148_LCSR_DCTL_VBOT_8 (4<<8) /* VMEbus back-off 8us */
867 #define TSI148_LCSR_DCTL_VBOT_16 (5<<8) /* VMEbus back-off 16us */
868 #define TSI148_LCSR_DCTL_VBOT_32 (6<<8) /* VMEbus back-off 32us */
869 #define TSI148_LCSR_DCTL_VBOT_64 (7<<8) /* VMEbus back-off 64us */
870
871 #define TSI148_LCSR_DCTL_PBKS_SHIFT 4
872 #define TSI148_LCSR_DCTL_PBKS_M (7<<4) /* PCI block size MASK */
873 #define TSI148_LCSR_DCTL_PBKS_32 (0<<4) /* PCI block size 32 bytes */
874 #define TSI148_LCSR_DCTL_PBKS_64 (1<<4) /* PCI block size 64 bytes */
875 #define TSI148_LCSR_DCTL_PBKS_128 (2<<4) /* PCI block size 128 bytes */
876 #define TSI148_LCSR_DCTL_PBKS_256 (3<<4) /* PCI block size 256 bytes */
877 #define TSI148_LCSR_DCTL_PBKS_512 (4<<4) /* PCI block size 512 bytes */
878 #define TSI148_LCSR_DCTL_PBKS_1024 (5<<4) /* PCI block size 1024 bytes */
879 #define TSI148_LCSR_DCTL_PBKS_2048 (6<<4) /* PCI block size 2048 bytes */
880 #define TSI148_LCSR_DCTL_PBKS_4096 (7<<4) /* PCI block size 4096 bytes */
881
882 #define TSI148_LCSR_DCTL_PBOT_SHIFT 0
883 #define TSI148_LCSR_DCTL_PBOT_M (7<<0) /* PCI back off MASK */
884 #define TSI148_LCSR_DCTL_PBOT_0 (0<<0) /* PCI back off 0us */
885 #define TSI148_LCSR_DCTL_PBOT_1 (1<<0) /* PCI back off 1us */
886 #define TSI148_LCSR_DCTL_PBOT_2 (2<<0) /* PCI back off 2us */
887 #define TSI148_LCSR_DCTL_PBOT_4 (3<<0) /* PCI back off 3us */
888 #define TSI148_LCSR_DCTL_PBOT_8 (4<<0) /* PCI back off 4us */
889 #define TSI148_LCSR_DCTL_PBOT_16 (5<<0) /* PCI back off 8us */
890 #define TSI148_LCSR_DCTL_PBOT_32 (6<<0) /* PCI back off 16us */
891 #define TSI148_LCSR_DCTL_PBOT_64 (7<<0) /* PCI back off 32us */
892
893 /* DMA Status Registers (0-1) CRG + $504 */
894 #define TSI148_LCSR_DSTA_VBE (1<<28) /* Error */
895 #define TSI148_LCSR_DSTA_ABT (1<<27) /* Abort */
896 #define TSI148_LCSR_DSTA_PAU (1<<26) /* Pause */
897 #define TSI148_LCSR_DSTA_DON (1<<25) /* Done */
898 #define TSI148_LCSR_DSTA_BSY (1<<24) /* Busy */
899 #define TSI148_LCSR_DSTA_ERRS (1<<20) /* Error Source */
900 #define TSI148_LCSR_DSTA_ERT (3<<16) /* Error Type */
901
902 /* DMA Current Link Address Lower (0-1) */
903 #define TSI148_LCSR_DCLAL_M (0x3FFFFFF<<6) /* Mask */
904
905 /* DMA Source Attribute (0-1) Reg */
906 #define TSI148_LCSR_DSAT_TYP_SHIFT 28
907 #define TSI148_LCSR_DSAT_TYP_M (3<<28) /* Source Bus Type */
908 #define TSI148_LCSR_DSAT_TYP_PCI (0<<28) /* PCI Bus */
909 #define TSI148_LCSR_DSAT_TYP_VME (1<<28) /* VMEbus */
910 #define TSI148_LCSR_DSAT_TYP_PAT (2<<28) /* Data Pattern */
911
912 #define TSI148_LCSR_DSAT_PSZ (1<<25) /* Pattern Size */
913 #define TSI148_LCSR_DSAT_NIP (1<<24) /* No Increment */
914
915 #define TSI148_LCSR_DSAT_2eSSTM_SHIFT 11
916 #define TSI148_LCSR_DSAT_2eSSTM_M (3<<11) /* 2eSST Trans Rate Mask */
917 #define TSI148_LCSR_DSAT_2eSSTM_160 (0<<11) /* 160 MB/s */
918 #define TSI148_LCSR_DSAT_2eSSTM_267 (1<<11) /* 267 MB/s */
919 #define TSI148_LCSR_DSAT_2eSSTM_320 (2<<11) /* 320 MB/s */
920
921 #define TSI148_LCSR_DSAT_TM_SHIFT 8
922 #define TSI148_LCSR_DSAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
923 #define TSI148_LCSR_DSAT_TM_SCT (0<<8) /* SCT */
924 #define TSI148_LCSR_DSAT_TM_BLT (1<<8) /* BLT */
925 #define TSI148_LCSR_DSAT_TM_MBLT (2<<8) /* MBLT */
926 #define TSI148_LCSR_DSAT_TM_2eVME (3<<8) /* 2eVME */
927 #define TSI148_LCSR_DSAT_TM_2eSST (4<<8) /* 2eSST */
928 #define TSI148_LCSR_DSAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
929
930 #define TSI148_LCSR_DSAT_DBW_SHIFT 6
931 #define TSI148_LCSR_DSAT_DBW_M (3<<6) /* Max Data Width MASK */
932 #define TSI148_LCSR_DSAT_DBW_16 (0<<6) /* 16 Bits */
933 #define TSI148_LCSR_DSAT_DBW_32 (1<<6) /* 32 Bits */
934
935 #define TSI148_LCSR_DSAT_SUP (1<<5) /* Supervisory Mode */
936 #define TSI148_LCSR_DSAT_PGM (1<<4) /* Program Mode */
937
938 #define TSI148_LCSR_DSAT_AMODE_SHIFT 0
939 #define TSI148_LCSR_DSAT_AMODE_M (0xf<<0) /* Address Space Mask */
940 #define TSI148_LCSR_DSAT_AMODE_16 (0<<0) /* A16 */
941 #define TSI148_LCSR_DSAT_AMODE_24 (1<<0) /* A24 */
942 #define TSI148_LCSR_DSAT_AMODE_32 (2<<0) /* A32 */
943 #define TSI148_LCSR_DSAT_AMODE_64 (4<<0) /* A64 */
944 #define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */
945 #define TSI148_LCSR_DSAT_AMODE_USER1 (8<<0) /* User1 */
946 #define TSI148_LCSR_DSAT_AMODE_USER2 (9<<0) /* User2 */
947 #define TSI148_LCSR_DSAT_AMODE_USER3 (0xa<<0) /* User3 */
948 #define TSI148_LCSR_DSAT_AMODE_USER4 (0xb<<0) /* User4 */
949
950 /* DMA Destination Attribute Registers (0-1) */
951 #define TSI148_LCSR_DDAT_TYP_SHIFT 28
952 #define TSI148_LCSR_DDAT_TYP_M (1<<28) /* Destination Bus Type */
953 #define TSI148_LCSR_DDAT_TYP_PCI (0<<28) /* Destination PCI Bus */
954 #define TSI148_LCSR_DDAT_TYP_VME (1<<28) /* Destination VMEbus */
955
956 #define TSI148_LCSR_DDAT_2eSSTM_M (3<<11) /* 2eSST Transfer Rate Mask */
957 #define TSI148_LCSR_DDAT_2eSSTM_160 (0<<11) /* 160 MB/s */
958 #define TSI148_LCSR_DDAT_2eSSTM_267 (1<<11) /* 267 MB/s */
959 #define TSI148_LCSR_DDAT_2eSSTM_320 (2<<11) /* 320 MB/s */
960
961 #define TSI148_LCSR_DDAT_TM_M (7<<8) /* Bus Transfer Protocol Mask */
962 #define TSI148_LCSR_DDAT_TM_SCT (0<<8) /* SCT */
963 #define TSI148_LCSR_DDAT_TM_BLT (1<<8) /* BLT */
964 #define TSI148_LCSR_DDAT_TM_MBLT (2<<8) /* MBLT */
965 #define TSI148_LCSR_DDAT_TM_2eVME (3<<8) /* 2eVME */
966 #define TSI148_LCSR_DDAT_TM_2eSST (4<<8) /* 2eSST */
967 #define TSI148_LCSR_DDAT_TM_2eSSTB (5<<8) /* 2eSST Broadcast */
968
969 #define TSI148_LCSR_DDAT_DBW_M (3<<6) /* Max Data Width MASK */
970 #define TSI148_LCSR_DDAT_DBW_16 (0<<6) /* 16 Bits */
971 #define TSI148_LCSR_DDAT_DBW_32 (1<<6) /* 32 Bits */
972
973 #define TSI148_LCSR_DDAT_SUP (1<<5) /* Supervisory/User Access */
974 #define TSI148_LCSR_DDAT_PGM (1<<4) /* Program/Data Access */
975
976 #define TSI148_LCSR_DDAT_AMODE_M (0xf<<0) /* Address Space Mask */
977 #define TSI148_LCSR_DDAT_AMODE_16 (0<<0) /* A16 */
978 #define TSI148_LCSR_DDAT_AMODE_24 (1<<0) /* A24 */
979 #define TSI148_LCSR_DDAT_AMODE_32 (2<<0) /* A32 */
980 #define TSI148_LCSR_DDAT_AMODE_64 (4<<0) /* A64 */
981 #define TSI148_LCSR_DDAT_AMODE_CRCSR (5<<0) /* CRC/SR */
982 #define TSI148_LCSR_DDAT_AMODE_USER1 (8<<0) /* User1 */
983 #define TSI148_LCSR_DDAT_AMODE_USER2 (9<<0) /* User2 */
984 #define TSI148_LCSR_DDAT_AMODE_USER3 (0xa<<0) /* User3 */
985 #define TSI148_LCSR_DDAT_AMODE_USER4 (0xb<<0) /* User4 */
986
987 /* DMA Next Link Address Lower */
988 #define TSI148_LCSR_DNLAL_DNLAL_M (0x1FFFFFFF<<3) /* Address Mask */
989 #define TSI148_LCSR_DNLAL_LLA (1<<0) /* Last Link Address Indicator */
990
991 /* DMA 2eSST Broadcast Select */
992 #define TSI148_LCSR_DBS_M (0x1FFFFF<<0) /* Mask */
993
994 /*
995 * GCSR Register Group
996 */
997
998 /* GCSR Control and Status Register CRG + $604 */
999 #define TSI148_GCSR_GCTRL_LRST (1<<15) /* Local Reset */
1000 #define TSI148_GCSR_GCTRL_SFAILEN (1<<14) /* System Fail enable */
1001 #define TSI148_GCSR_GCTRL_BDFAILS (1<<13) /* Board Fail Status */
1002 #define TSI148_GCSR_GCTRL_SCON (1<<12) /* System Copntroller */
1003 #define TSI148_GCSR_GCTRL_MEN (1<<11) /* Module Enable (READY) */
1004
1005 #define TSI148_GCSR_GCTRL_LMI3S (1<<7) /* Loc Monitor 3 Int Status */
1006 #define TSI148_GCSR_GCTRL_LMI2S (1<<6) /* Loc Monitor 2 Int Status */
1007 #define TSI148_GCSR_GCTRL_LMI1S (1<<5) /* Loc Monitor 1 Int Status */
1008 #define TSI148_GCSR_GCTRL_LMI0S (1<<4) /* Loc Monitor 0 Int Status */
1009 #define TSI148_GCSR_GCTRL_MBI3S (1<<3) /* Mail box 3 Int Status */
1010 #define TSI148_GCSR_GCTRL_MBI2S (1<<2) /* Mail box 2 Int Status */
1011 #define TSI148_GCSR_GCTRL_MBI1S (1<<1) /* Mail box 1 Int Status */
1012 #define TSI148_GCSR_GCTRL_MBI0S (1<<0) /* Mail box 0 Int Status */
1013
1014 #define TSI148_GCSR_GAP (1<<5) /* Geographic Addr Parity */
1015 #define TSI148_GCSR_GA_M (0x1F<<0) /* Geographic Address Mask */
1016
1017 /*
1018 * CR/CSR Register Group
1019 */
1020
1021 /* CR/CSR Bit Clear Register CRG + $FF4 */
1022 #define TSI148_CRCSR_CSRBCR_LRSTC (1<<7) /* Local Reset Clear */
1023 #define TSI148_CRCSR_CSRBCR_SFAILC (1<<6) /* System Fail Enable Clear */
1024 #define TSI148_CRCSR_CSRBCR_BDFAILS (1<<5) /* Board Fail Status */
1025 #define TSI148_CRCSR_CSRBCR_MENC (1<<4) /* Module Enable Clear */
1026 #define TSI148_CRCSR_CSRBCR_BERRSC (1<<3) /* Bus Error Status Clear */
1027
1028 /* CR/CSR Bit Set Register CRG+$FF8 */
1029 #define TSI148_CRCSR_CSRBSR_LRSTS (1<<7) /* Local Reset Set */
1030 #define TSI148_CRCSR_CSRBSR_SFAILS (1<<6) /* System Fail Enable Set */
1031 #define TSI148_CRCSR_CSRBSR_BDFAILS (1<<5) /* Board Fail Status */
1032 #define TSI148_CRCSR_CSRBSR_MENS (1<<4) /* Module Enable Set */
1033 #define TSI148_CRCSR_CSRBSR_BERRS (1<<3) /* Bus Error Status Set */
1034
1035 /* CR/CSR Base Address Register CRG + FFC */
1036 #define TSI148_CRCSR_CBAR_M (0x1F<<3) /* Mask */
1037
1038
1039 /* Low level misc inline stuff */
1040 static inline int tsi148_get_slotnum(struct tsi148_chip *regs)
1041 {
1042 return ioread32be(&regs->lcsr.vstat) & 0x1f;
1043 }
1044
1045 static inline int tsi148_get_syscon(struct tsi148_chip *regs)
1046 {
1047 int syscon = 0;
1048
1049 if (ioread32be(&regs->lcsr.vstat) & 0x100)
1050 syscon = 1;
1051
1052 return syscon;
1053 }
1054
1055 static inline int tsi148_set_interrupts(struct tsi148_chip *regs,
1056 unsigned int mask)
1057 {
1058 iowrite32be(mask, &regs->lcsr.inteo);
1059 iowrite32be(mask, &regs->lcsr.inten);
1060
1061 /* Quick sanity check */
1062 if ((ioread32be(&regs->lcsr.inteo) != mask) ||
1063 (ioread32be(&regs->lcsr.inten) != mask))
1064 return -1;
1065
1066 return 0;
1067 }
1068
1069 static inline unsigned int tsi148_get_int_enabled(struct tsi148_chip *regs)
1070 {
1071 return ioread32be(&regs->lcsr.inteo);
1072 }
1073
1074 static inline unsigned int tsi148_get_int_status(struct tsi148_chip *regs)
1075 {
1076 return ioread32be(&regs->lcsr.ints);
1077 }
1078
1079 static inline void tsi148_clear_int(struct tsi148_chip *regs, unsigned int mask)
1080 {
1081 iowrite32be(mask, &regs->lcsr.intc);
1082 }
1083
1084 static inline int tsi148_iack8(struct tsi148_chip *regs, int irq)
1085 {
1086 int vec = ioread8(&regs->lcsr.viack[(irq * 4) + 3]);
1087
1088 return vec & 0xff;
1089 }
1090
1091 static inline int tsi148_bus_error_chk(struct tsi148_chip *regs, int clear)
1092 {
1093 unsigned int veat = ioread32be(&regs->lcsr.veat);
1094
1095 if (veat & TSI148_LCSR_VEAT_VES) {
1096 if (clear)
1097 iowrite32be(TSI148_LCSR_VEAT_VESCL, &regs->lcsr.veat);
1098 return 1;
1099 }
1100
1101 return 0;
1102 }
1103
1104
1105 extern void tsi148_handle_pci_error(void);
1106 extern void tsi148_handle_vme_error(struct vme_bus_error *);
1107 extern int tsi148_generate_interrupt(int, int, signed long);
1108
1109 extern int tsi148_dma_get_status(struct dma_channel *);
1110 extern int tsi148_dma_busy(struct dma_channel *);
1111 extern int tsi148_dma_done(struct dma_channel *);
1112 extern int tsi148_dma_setup(struct dma_channel *);
1113 extern void tsi148_dma_start(struct dma_channel *);
1114 extern void tsi148_dma_abort(struct dma_channel *);
1115 extern void tsi148_dma_release(struct dma_channel *);
1116 extern void __devexit tsi148_dma_exit(void);
1117 extern int __devinit tsi148_dma_init(void);
1118
1119 extern void tsi148_get_window_attr(struct vme_mapping *);
1120 extern int tsi148_create_window(struct vme_mapping *);
1121 extern void tsi148_remove_window(struct vme_mapping *);
1122
1123 extern int __devinit tsi148_setup_crg(unsigned int, enum vme_address_modifier);
1124 extern void __devexit tsi148_disable_crg(struct tsi148_chip *);
1125
1126 #ifdef CONFIG_PROC_FS
1127 extern void tsi148_procfs_register(struct proc_dir_entry *);
1128 extern void tsi148_procfs_unregister(struct proc_dir_entry *);
1129 #endif /* CONFIG_PROC_FS */
1130 extern void tsi148_quiesce(struct tsi148_chip *);
1131 extern void tsi148_init(struct tsi148_chip *);
1132
1133 #endif /* _TSI148_H */
1134
Drivers, Libraries and test programs for Linux and LynxOS