vmod/driver/cio8536.h

   1 /*****************************************************************************/
   2 /*                                                                           */
   3 /*     CIO8536.H                                                             */
   4 /*    ===========                                                            */
   5 /*                                                                           */
   6 /*     The includefile contains all necessary defines for the                */
   7 /*     ZILOG 8536-CIO interface chip.                                        */
   8 /*                                                                           */
   9 /*                                                                           */
  10 /*****************************************************************************/
  11
  12 #ifndef __INCcio8536h
  13 #define __INCcio8536h
  14
  15 #ifdef __cplusplus
  16 extern "C" {
  17 #endif
  18
  19 /*------------------------------*/
  20 /* Master Control Registers     */
  21 /*------------------------------*/
  22 #define MICR    0x00    /* Master Interrupt Control Register            */
  23 #define MCCR    0x01    /* Master Configuration Control Register        */
  24
  25 /* Bitdefinition MICR */
  26 #define RESET   0x01    /* d0: reset cio                                */
  27 #define RJA     0x02    /* d1: right justified address                  */
  28 #define CTVIS   0x04    /* d2: c/t vector includes status               */
  29 #define PBVIS   0x08    /* d3: port b vector includes status            */
  30 #define PAVIS   0x10    /* d4: port a vector includes status            */
  31 #define NV      0x20    /* d5: no vector                                */
  32 #define DLC     0x40    /* d6: disable lower chain                      */
  33 #define MIE     0x80    /* d7: master interrupt enable                  */
  34
  35 /* Bitdefinition MCCR */
  36                         /* Counter/Timer Link Control                   */
  37                         /* d0, d1:                                      */
  38 #define T1GT2   0x01    /*         T1's output gates T2                 */
  39 #define T1TT2   0x02    /*         T1's output triggers T2              */
  40 #define T1T2    0x03    /*         T1's output is T2's count input      */
  41 #define CTLMASK 0x03    /* Counter/Timer Link Mask                      */
  42 #define PAE     0x04    /* d2: port a enable                            */
  43 #define PLC     0x08    /* d3: port link control                        */
  44 #define PCE     0x10    /* d4: port c enable                            */
  45 #define CT3E    0x10    /* d4: c/t 3 enable                             */
  46 #define CT2E    0x20    /* d5: c/t 2 enable                             */
  47 #define CT1E    0x40    /* d6: c/t 1 enable                             */
  48 #define PBE     0x80    /* d7: port b enable                            */
  49
  50 /*------------------------------*/
  51 /* Port Specification Registers */
  52 /*------------------------------*/
  53 #define PMSR_A  0x20    /* (A) Port Mode Specification Register         */
  54 #define PMSR_B  0x28    /* (B)                                          */
  55 #define PHSR_A  0x21    /* (A) Port Handshake Specification Register    */
  56 #define PHSR_B  0x29    /* (B)                                          */
  57
  58 #define PCSR_A  0x08    /* (A) Port Command and Status Register         */
  59 #define PCSR_B  0x09    /* (B)                                          */
  60 /* Bitdefinition PCSR */
  61 #define IUS     0x80    /* d7: Interrupt under service                  */
  62 #define IE      0x40    /* d6: Interrupt enable                         */
  63 #define IP      0x20    /* d5: Interrupt pending                        */
  64 #define IERR    0x10    /* d4: Interrupt error                          */
  65 #define ORE     0x08    /* d3: output register empty                    */
  66 #define IRF     0x04    /* d2: input register full                      */
  67 #define PMF     0x02    /* d1: pattern match flag                       */
  68 #define IOE     0x01    /* d0: interrupt on error                       */
  69 #define CLEAR_IP_IUS    0x20
  70 #define CLEAR_IP        0xa0
  71 #define CLEAR_IUS       0x60
  72 #define CLEAR_IE        0xe0
  73 #define SET_IE          0xc0
  74
  75
  76 /*--------------------------------------*/
  77 /* Bit Path Definition Registers        */
  78 /*--------------------------------------*/
  79 #define DPPR_A  0x22    /* (A) Data Path Polarity Register              */
  80 #define DPPR_B  0x2a    /* (B)                                          */
  81 #define DPPR_C  0x05    /* (C)                                          */
  82 #define DDR_A   0x23    /* (A) Data Direction Register                  */
  83 #define DDR_B   0x2b    /* (B)                                          */
  84 #define DDR_C   0x06    /* (C)                                          */
  85 #define SIOCR_A 0x24    /* (A) Special I/O Control Register             */
  86 #define SIOCR_B 0x2c    /* (B)                                          */
  87 #define SIOCR_C 0x07    /* (C)                                          */
  88
  89 /*---------------------*/
  90 /* Port Data Registers */
  91 /*---------------------*/
  92 #define PDR_A   0x0d    /* (A) Port Data Register                       */
  93 #define PDR_B   0x0e    /* (B)                                          */
  94 #define PDR_C   0x0f    /* (C)                                          */
  95
  96 /*------------------------------*/
  97 /* Pattern Definition Registers */
  98 /*------------------------------*/
  99 #define PPR_A   0x25    /* (A) Pattern Polarity Register                */
 100 #define PPR_B   0x2d    /* (B)                                          */
 101 #define PTR_A   0x26    /* (A) Pattern Transition Register              */
 102 #define PTR_B   0x2e    /* (B)                                          */
 103 #define PMR_A   0x27    /* (A) Pattern Mask Register                    */
 104 #define PMR_B   0x2f    /* (B)                                          */
 105
 106 /*-------------------------*/
 107 /* Counter/Timer Registers */
 108 /*-------------------------*/
 109 #define CTCSR_1 0x0a    /* (1) C/T Command and Status Register          */
 110 #define CTCSR_2 0x0b    /* (2)                                          */
 111 #define CTCSR_3 0x0c    /* (3)                                          */
 112 /* Bitdefinition CTCSR */
 113 /*      IUS     0x80       d7: Interrupt under service                  */
 114 /*      IE      0x40       d6: Interrupt enable                         */
 115 /*      IP      0x20       d5: Interrupt pending                        */
 116 /*      IERR    0x10       d4: Interrupt error                          */
 117 #define RCC     0x08    /* d3: read counter control                     */
 118 #define GCB     0x04    /* d2: gate command bit                         */
 119 #define TCB     0x02    /* d1: trigger command bit                      */
 120 #define CIP     0x01    /* d0: count in progress                        */
 121
 122 #define CTMSR_1 0x1c    /* (1) C/T Mode Specification Register          */
 123 #define CTMSR_2 0x1d    /* (2)                                          */
 124 #define CTMSR_3 0x1e    /* (3)                                          */
 125 #define CTCCRH_1 0x10   /* (1) C/T Current Count Register high byte     */
 126 #define CTCCRL_1 0x11   /* (1)                            low  byte     */
 127 #define CTCCRH_2 0x12   /* (2)                            high byte     */
 128 #define CTCCRL_2 0x13   /* (2)                            low  byte     */
 129 #define CTCCRH_3 0x14   /* (3)                            high byte     */
 130 #define CTCCRL_3 0x15   /* (3)                            low  byte     */
 131 #define CTTCRH_1 0x16   /* (1) C/T Time Constant Register high byte     */
 132 #define CTTCRL_1 0x17   /* (1)                            low  byte     */
 133 #define CTTCRH_2 0x18   /* (1) C/T Time Constant Register high byte     */
 134 #define CTTCRL_2 0x19   /* (1)                            low  byte     */
 135 #define CTTCRH_3 0x1a   /* (1) C/T Time Constant Register high byte     */
 136 #define CTTCRL_3 0x1b   /* (1)                            low  byte     */
 137
 138 /*----------------------------*/
 139 /* Interrupt Vector Registers */
 140 /*----------------------------*/
 141 #define ICR_A   0x02    /* (A) Interrupt Vector Register                */
 142 #define ICR_B   0x03    /* (B)                                          */
 143 #define ICR_CT  0x04    /* (C/T)                                        */
 144 #define CVR     0x1f    /* Current Vector Register                      */
 145
 146 #ifdef __cplusplus
 147 }
 148 #endif
 149
 150 #endif /* __INCcio8536h */
 151