drivers/video/msm/mdp_hw.h

   1 /* drivers/video/msm_fb/mdp_hw.h
   2  *
   3  * Copyright (C) 2007 QUALCOMM Incorporated
   4  * Copyright (C) 2007 Google Incorporated
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #ifndef _MDP_HW_H_
  16 #define _MDP_HW_H_
  17
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <mach/msm_iomap.h>
  21 #include <mach/msm_fb.h>
  22
  23 typedef void (*mdp_dma_start_func_t)(void *private_data, uint32_t addr,
  24                                      uint32_t stride, uint32_t width,
  25                                      uint32_t height, uint32_t x, uint32_t y);
  26
  27 struct mdp_out_interface {
  28         uint32_t                registered:1;
  29         void                    *priv;
  30
  31         /* If the interface client wants to get DMA_DONE events */
  32         uint32_t                dma_mask;
  33         mdp_dma_start_func_t    dma_start;
  34
  35         struct msmfb_callback   *dma_cb;
  36         wait_queue_head_t       dma_waitqueue;
  37
  38         /* If the interface client wants to be notified of non-DMA irqs,
  39          * e.g. LCDC/TV-out frame start */
  40         uint32_t                irq_mask;
  41         struct msmfb_callback   *irq_cb;
  42 };
  43
  44 struct mdp_info {
  45         spinlock_t lock;
  46         struct mdp_device mdp_dev;
  47         char * __iomem base;
  48         int irq;
  49         struct clk *clk;
  50         struct clk *ebi1_clk;
  51         struct mdp_out_interface out_if[MSM_MDP_NUM_INTERFACES];
  52         int format;
  53         int pack_pattern;
  54         bool dma_config_dirty;
  55         struct mdp_blit_req *req;
  56 };
  57
  58 extern int mdp_out_if_register(struct mdp_device *mdp_dev, int interface,
  59                                void *private_data, uint32_t dma_mask,
  60                                mdp_dma_start_func_t dma_start);
  61
  62 extern int mdp_out_if_req_irq(struct mdp_device *mdp_dev, int interface,
  63                               uint32_t mask, struct msmfb_callback *cb);
  64
  65 struct mdp_blit_req;
  66 struct mdp_device;
  67 int mdp_ppp_blit(const struct mdp_info *mdp, struct mdp_blit_req *req,
  68                  struct file *src_file, unsigned long src_start,
  69                  unsigned long src_len, struct file *dst_file,
  70                  unsigned long dst_start, unsigned long dst_len);
  71
  72 void mdp_ppp_dump_debug(const struct mdp_info *mdp);
  73
  74 #define mdp_writel(mdp, value, offset) writel(value, mdp->base + offset)
  75 #define mdp_readl(mdp, offset) readl(mdp->base + offset)
  76
  77 #ifdef CONFIG_MSM_MDP302
  78 #define MDP_SYNC_CONFIG_0                ( 0x00300)
  79 #define MDP_SYNC_CONFIG_1                ( 0x00304)
  80 #define MDP_SYNC_CONFIG_2                ( 0x00308)
  81 #else
  82 #define MDP_SYNC_CONFIG_0                ( 0x00000)
  83 #define MDP_SYNC_CONFIG_1                ( 0x00004)
  84 #define MDP_SYNC_CONFIG_2                ( 0x00008)
  85 #endif
  86
  87 #define MDP_SYNC_STATUS_0                ( 0x0000c)
  88 #define MDP_SYNC_STATUS_1                ( 0x00010)
  89 #define MDP_SYNC_STATUS_2                ( 0x00014)
  90
  91 #ifdef CONFIG_MSM_MDP302
  92 #define MDP_SYNC_THRESH_0                ( 0x00200)
  93 #define MDP_SYNC_THRESH_1                ( 0x00204)
  94 #else
  95 #define MDP_SYNC_THRESH_0                ( 0x00018)
  96 #define MDP_SYNC_THRESH_1                ( 0x0001c)
  97 #endif
  98 #ifdef CONFIG_MSM_MDP40
  99 #define MDP_INTR_ENABLE                  ( 0x0050)
 100 #define MDP_INTR_STATUS                  ( 0x0054)
 101 #define MDP_INTR_CLEAR                   ( 0x0058)
 102 #define MDP_EBI2_LCD0                    ( 0x0060)
 103 #define MDP_EBI2_LCD1                    ( 0x0064)
 104 #define MDP_EBI2_PORTMAP_MODE            ( 0x0070)
 105
 106 #define MDP_DMA_P_HIST_INTR_STATUS      ( 0x95014)
 107 #define MDP_DMA_P_HIST_INTR_CLEAR       ( 0x95018)
 108 #define MDP_DMA_P_HIST_INTR_ENABLE      ( 0x9501C)
 109 #else
 110 #define MDP_INTR_ENABLE                  ( 0x00020)
 111 #define MDP_INTR_STATUS                  ( 0x00024)
 112 #define MDP_INTR_CLEAR                   ( 0x00028)
 113 #define MDP_EBI2_LCD0                    ( 0x0003c)
 114 #define MDP_EBI2_LCD1                    ( 0x00040)
 115 #define MDP_EBI2_PORTMAP_MODE            ( 0x0005c)
 116 #endif
 117 #define MDP_DISPLAY0_START               ( 0x00030)
 118 #define MDP_DISPLAY1_START               ( 0x00034)
 119 #define MDP_DISPLAY_STATUS               ( 0x00038)
 120 /* CONFIG_MSM_MDP302 */
 121 #define MDP_TEAR_CHECK_EN                ( 0x0020c)
 122 #define MDP_PRIM_START_POS               ( 0x00210)
 123
 124 #ifndef CONFIG_MSM_MDP31
 125 #define MDP_DISPLAY0_ADDR                (0x00054)
 126 #define MDP_DISPLAY1_ADDR                (0x00058)
 127 #define MDP_PPP_CMD_MODE                 (0x00060)
 128 #else
 129 #define MDP_DISPLAY0_ADDR                (0x10000)
 130 #define MDP_DISPLAY1_ADDR                (0x10004)
 131 #define MDP_PPP_CMD_MODE                 (0x10060)
 132 #endif
 133
 134 #define MDP_TV_OUT_STATUS                (0x00064)
 135 #define MDP_HW_VERSION                   (0x00070)
 136 #define MDP_SW_RESET                     (0x00074)
 137 #define MDP_AXI_ERROR_MASTER_STOP        (0x00078)
 138 #define MDP_SEL_CLK_OR_HCLK_TEST_BUS     (0x0007c)
 139 #define MDP_PRIMARY_VSYNC_OUT_CTRL       (0x00080)
 140 #define MDP_SECONDARY_VSYNC_OUT_CTRL     (0x00084)
 141 #define MDP_EXTERNAL_VSYNC_OUT_CTRL      (0x00088)
 142 #define MDP_VSYNC_CTRL                   (0x0008c)
 143 #define MDP_MDDI_PARAM_WR_SEL            (0x00090)
 144 #define MDP_MDDI_PARAM                   (0x00094)
 145 #define MDP_CGC_EN                       (0x00100)
 146 #define MDP_CMD_STATUS                   (0x10008)
 147 #define MDP_PROFILE_EN                   (0x10010)
 148 #define MDP_PROFILE_COUNT                (0x10014)
 149 #define MDP_DMA_START                    (0x10044)
 150 #define MDP_FULL_BYPASS_WORD0            (0x10100)
 151 #define MDP_FULL_BYPASS_WORD1            (0x10104)
 152 #define MDP_COMMAND_CONFIG               (0x10104)
 153 #define MDP_FULL_BYPASS_WORD2            (0x10108)
 154 #define MDP_FULL_BYPASS_WORD3            (0x1010c)
 155 #define MDP_FULL_BYPASS_WORD4            (0x10110)
 156 #define MDP_FULL_BYPASS_WORD6            (0x10118)
 157 #define MDP_FULL_BYPASS_WORD7            (0x1011c)
 158 #define MDP_FULL_BYPASS_WORD8            (0x10120)
 159 #define MDP_FULL_BYPASS_WORD9            (0x10124)
 160 #define MDP_PPP_SOURCE_CONFIG            (0x10124)
 161 #define MDP_FULL_BYPASS_WORD10           (0x10128)
 162 #define MDP_FULL_BYPASS_WORD11           (0x1012c)
 163 #define MDP_FULL_BYPASS_WORD12           (0x10130)
 164 #define MDP_FULL_BYPASS_WORD13           (0x10134)
 165 #define MDP_FULL_BYPASS_WORD14           (0x10138)
 166 #define MDP_PPP_OPERATION_CONFIG         (0x10138)
 167 #define MDP_FULL_BYPASS_WORD15           (0x1013c)
 168 #define MDP_FULL_BYPASS_WORD16           (0x10140)
 169 #define MDP_FULL_BYPASS_WORD17           (0x10144)
 170 #define MDP_FULL_BYPASS_WORD18           (0x10148)
 171 #define MDP_FULL_BYPASS_WORD19           (0x1014c)
 172 #define MDP_FULL_BYPASS_WORD20           (0x10150)
 173 #define MDP_PPP_DESTINATION_CONFIG       (0x10150)
 174 #define MDP_FULL_BYPASS_WORD21           (0x10154)
 175 #define MDP_FULL_BYPASS_WORD22           (0x10158)
 176 #define MDP_FULL_BYPASS_WORD23           (0x1015c)
 177 #define MDP_FULL_BYPASS_WORD24           (0x10160)
 178 #define MDP_FULL_BYPASS_WORD25           (0x10164)
 179 #define MDP_FULL_BYPASS_WORD26           (0x10168)
 180 #define MDP_FULL_BYPASS_WORD27           (0x1016c)
 181 #define MDP_FULL_BYPASS_WORD29           (0x10174)
 182 #define MDP_FULL_BYPASS_WORD30           (0x10178)
 183 #define MDP_FULL_BYPASS_WORD31           (0x1017c)
 184 #define MDP_FULL_BYPASS_WORD32           (0x10180)
 185 #define MDP_DMA_CONFIG                   (0x10180)
 186 #define MDP_FULL_BYPASS_WORD33           (0x10184)
 187 #define MDP_FULL_BYPASS_WORD34           (0x10188)
 188 #define MDP_FULL_BYPASS_WORD35           (0x1018c)
 189 #define MDP_FULL_BYPASS_WORD37           (0x10194)
 190 #define MDP_FULL_BYPASS_WORD39           (0x1019c)
 191 #define MDP_PPP_OUT_XY                   (0x1019c)
 192 #define MDP_FULL_BYPASS_WORD40           (0x101a0)
 193 #define MDP_FULL_BYPASS_WORD41           (0x101a4)
 194 #define MDP_FULL_BYPASS_WORD43           (0x101ac)
 195 #define MDP_FULL_BYPASS_WORD46           (0x101b8)
 196 #define MDP_FULL_BYPASS_WORD47           (0x101bc)
 197 #define MDP_FULL_BYPASS_WORD48           (0x101c0)
 198 #define MDP_FULL_BYPASS_WORD49           (0x101c4)
 199 #define MDP_FULL_BYPASS_WORD50           (0x101c8)
 200 #define MDP_FULL_BYPASS_WORD51           (0x101cc)
 201 #define MDP_FULL_BYPASS_WORD52           (0x101d0)
 202 #define MDP_FULL_BYPASS_WORD53           (0x101d4)
 203 #define MDP_FULL_BYPASS_WORD54           (0x101d8)
 204 #define MDP_FULL_BYPASS_WORD55           (0x101dc)
 205 #define MDP_FULL_BYPASS_WORD56           (0x101e0)
 206 #define MDP_FULL_BYPASS_WORD57           (0x101e4)
 207 #define MDP_FULL_BYPASS_WORD58           (0x101e8)
 208 #define MDP_FULL_BYPASS_WORD59           (0x101ec)
 209 #define MDP_FULL_BYPASS_WORD60           (0x101f0)
 210 #define MDP_VSYNC_THRESHOLD              (0x101f0)
 211 #define MDP_FULL_BYPASS_WORD61           (0x101f4)
 212 #define MDP_FULL_BYPASS_WORD62           (0x101f8)
 213 #define MDP_FULL_BYPASS_WORD63           (0x101fc)
 214
 215 #ifdef CONFIG_MSM_MDP31
 216 #define MDP_PPP_SRC_XY                   (0x10200)
 217 #define MDP_PPP_BG_XY                    (0x10204)
 218 #define MDP_PPP_SRC_IMAGE_SIZE           (0x10208)
 219 #define MDP_PPP_BG_IMAGE_SIZE            (0x1020c)
 220 #define MDP_PPP_SCALE_CONFIG             (0x10230)
 221 #define MDP_PPP_CSC_CONFIG               (0x10240)
 222 #define MDP_PPP_BLEND_BG_ALPHA_SEL       (0x70010)
 223 #endif
 224
 225 #define MDP_TFETCH_TEST_MODE             (0x20004)
 226 #define MDP_TFETCH_STATUS                (0x20008)
 227 #define MDP_TFETCH_TILE_COUNT            (0x20010)
 228 #define MDP_TFETCH_FETCH_COUNT           (0x20014)
 229 #define MDP_TFETCH_CONSTANT_COLOR        (0x20040)
 230 #define MDP_BGTFETCH_TEST_MODE           (0x28004)
 231 #define MDP_BGTFETCH_STATUS              (0x28008)
 232 #define MDP_BGTFETCH_TILE_COUNT          (0x28010)
 233 #define MDP_BGTFETCH_FETCH_COUNT         (0x28014)
 234 #define MDP_BGTFETCH_CONSTANT_COLOR      (0x28040)
 235 #define MDP_CSC_BYPASS                   (0x40004)
 236 #define MDP_SCALE_COEFF_LSB              (0x5fffc)
 237 #define MDP_TV_OUT_CTL                   (0xc0000)
 238 #define MDP_TV_OUT_FIR_COEFF             (0xc0004)
 239 #define MDP_TV_OUT_BUF_ADDR              (0xc0008)
 240 #define MDP_TV_OUT_CC_DATA               (0xc000c)
 241 #define MDP_TV_OUT_SOBEL                 (0xc0010)
 242 #define MDP_TV_OUT_Y_CLAMP               (0xc0018)
 243 #define MDP_TV_OUT_CB_CLAMP              (0xc001c)
 244 #define MDP_TV_OUT_CR_CLAMP              (0xc0020)
 245 #define MDP_TEST_MODE_CLK                (0xd0000)
 246 #define MDP_TEST_MISR_RESET_CLK          (0xd0004)
 247 #define MDP_TEST_EXPORT_MISR_CLK         (0xd0008)
 248 #define MDP_TEST_MISR_CURR_VAL_CLK       (0xd000c)
 249 #define MDP_TEST_MODE_HCLK               (0xd0100)
 250 #define MDP_TEST_MISR_RESET_HCLK         (0xd0104)
 251 #define MDP_TEST_EXPORT_MISR_HCLK        (0xd0108)
 252 #define MDP_TEST_MISR_CURR_VAL_HCLK      (0xd010c)
 253 #define MDP_TEST_MODE_DCLK               (0xd0200)
 254 #define MDP_TEST_MISR_RESET_DCLK         (0xd0204)
 255 #define MDP_TEST_EXPORT_MISR_DCLK        (0xd0208)
 256 #define MDP_TEST_MISR_CURR_VAL_DCLK      (0xd020c)
 257 #define MDP_TEST_CAPTURED_DCLK           (0xd0210)
 258 #define MDP_TEST_MISR_CAPT_VAL_DCLK      (0xd0214)
 259
 260 #ifdef CONFIG_MSM_MDP40
 261 #define MDP_DMA_P_START                  (0x000c)
 262 #else
 263 #define MDP_DMA_P_START                  (0x00044)
 264 #endif
 265 #define MDP_DMA_P_CONFIG                 (0x90000)
 266 #define MDP_DMA_P_SIZE                   (0x90004)
 267 #define MDP_DMA_P_IBUF_ADDR              (0x90008)
 268 #define MDP_DMA_P_IBUF_Y_STRIDE          (0x9000c)
 269 #define MDP_DMA_P_OUT_XY                 (0x90010)
 270 #define MDP_DMA_P_COLOR_CORRECT_CONFIG   (0x90070)
 271
 272 #define MDP_DMA_S_START                  (0x00048)
 273 #define MDP_DMA_S_CONFIG                 (0xa0000)
 274 #define MDP_DMA_S_SIZE                   (0xa0004)
 275 #define MDP_DMA_S_IBUF_ADDR              (0xa0008)
 276 #define MDP_DMA_S_IBUF_Y_STRIDE          (0xa000c)
 277 #define MDP_DMA_S_OUT_XY                 (0xa0010)
 278
 279 #ifdef CONFIG_MSM_MDP40
 280 #define MDP_LCDC_EN                      (0xc0000)
 281 #define MDP_LCDC_HSYNC_CTL               (0xc0004)
 282 #define MDP_LCDC_VSYNC_PERIOD            (0xc0008)
 283 #define MDP_LCDC_VSYNC_PULSE_WIDTH       (0xc000c)
 284 #define MDP_LCDC_DISPLAY_HCTL            (0xc0010)
 285 #define MDP_LCDC_DISPLAY_V_START         (0xc0014)
 286 #define MDP_LCDC_DISPLAY_V_END           (0xc0018)
 287 #define MDP_LCDC_ACTIVE_HCTL             (0xc001c)
 288 #define MDP_LCDC_ACTIVE_V_START          (0xc0020)
 289 #define MDP_LCDC_ACTIVE_V_END            (0xc0024)
 290 #define MDP_LCDC_BORDER_CLR              (0xc0028)
 291 #define MDP_LCDC_UNDERFLOW_CTL           (0xc002c)
 292 #define MDP_LCDC_HSYNC_SKEW              (0xc0030)
 293 #define MDP_LCDC_TEST_CTL                (0xc0034)
 294 #define MDP_LCDC_CTL_POLARITY            (0xc0038)
 295 #else
 296 #define MDP_LCDC_EN                      (0xe0000)
 297 #define MDP_LCDC_HSYNC_CTL               (0xe0004)
 298 #define MDP_LCDC_VSYNC_PERIOD            (0xe0008)
 299 #define MDP_LCDC_VSYNC_PULSE_WIDTH       (0xe000c)
 300 #define MDP_LCDC_DISPLAY_HCTL            (0xe0010)
 301 #define MDP_LCDC_DISPLAY_V_START         (0xe0014)
 302 #define MDP_LCDC_DISPLAY_V_END           (0xe0018)
 303 #define MDP_LCDC_ACTIVE_HCTL             (0xe001c)
 304 #define MDP_LCDC_ACTIVE_V_START          (0xe0020)
 305 #define MDP_LCDC_ACTIVE_V_END            (0xe0024)
 306 #define MDP_LCDC_BORDER_CLR              (0xe0028)
 307 #define MDP_LCDC_UNDERFLOW_CTL           (0xe002c)
 308 #define MDP_LCDC_HSYNC_SKEW              (0xe0030)
 309 #define MDP_LCDC_TEST_CTL                (0xe0034)
 310 #define MDP_LCDC_CTL_POLARITY            (0xe0038)
 311 #endif
 312
 313 #define MDP_PPP_SCALE_STATUS             (0x50000)
 314 #define MDP_PPP_BLEND_STATUS             (0x70000)
 315
 316 /* MDP_SW_RESET */
 317 #define MDP_PPP_SW_RESET                (1<<4)
 318
 319 /* MDP_INTR_ENABLE */
 320 #define DL0_ROI_DONE                    (1<<0)
 321 #define TV_OUT_DMA3_DONE                (1<<6)
 322 #define TV_ENC_UNDERRUN                 (1<<7)
 323 #define TV_OUT_FRAME_START              (1<<13)
 324
 325 #ifdef CONFIG_MSM_MDP22
 326 #define MDP_DMA_P_DONE                  (1 << 2)
 327 #define MDP_DMA_S_DONE                  (1 << 3)
 328 #else /* CONFIG_MSM_MDP31 */
 329
 330 #ifdef CONFIG_MSM_MDP40
 331 #define MDP_DMA_P_DONE                  (1 << 4)
 332 #else
 333 #define MDP_DMA_P_DONE                  (1 << 14)
 334 #endif
 335
 336 #define MDP_DMA_S_DONE                  (1 << 2)
 337 #define MDP_LCDC_UNDERFLOW              (1 << 16)
 338
 339 #ifdef CONFIG_MSM_MDP40
 340 #define MDP_LCDC_FRAME_START            (1 << 7)
 341 #else
 342 #define MDP_LCDC_FRAME_START            (1 << 15)
 343 #endif
 344
 345 #endif
 346
 347 #define MDP_TOP_LUMA       16
 348 #define MDP_TOP_CHROMA     0
 349 #define MDP_BOTTOM_LUMA    19
 350 #define MDP_BOTTOM_CHROMA  3
 351 #define MDP_LEFT_LUMA      22
 352 #define MDP_LEFT_CHROMA    6
 353 #define MDP_RIGHT_LUMA     25
 354 #define MDP_RIGHT_CHROMA   9
 355
 356 #define CLR_G 0x0
 357 #define CLR_B 0x1
 358 #define CLR_R 0x2
 359 #define CLR_ALPHA 0x3
 360
 361 #define CLR_Y  CLR_G
 362 #define CLR_CB CLR_B
 363 #define CLR_CR CLR_R
 364
 365 /* from lsb to msb */
 366 #define MDP_GET_PACK_PATTERN(a, x, y, z, bit) \
 367         (((a)<<(bit*3))|((x)<<(bit*2))|((y)<<bit)|(z))
 368
 369 /* MDP_SYNC_CONFIG_0/1/2 */
 370 #if defined(CONFIG_MSM_MDP30)
 371 #define MDP_SYNCFG_HGT_LOC 21
 372 #define MDP_SYNCFG_VSYNC_EXT_EN (1<<20)
 373 #define MDP_SYNCFG_VSYNC_INT_EN (1<<19)
 374 #else
 375 #define MDP_SYNCFG_HGT_LOC 22
 376 #define MDP_SYNCFG_VSYNC_EXT_EN (1<<21)
 377 #define MDP_SYNCFG_VSYNC_INT_EN (1<<20)
 378 #endif
 379
 380 /* MDP_SYNC_THRESH_0 */
 381 #define MDP_PRIM_BELOW_LOC 0
 382 #define MDP_PRIM_ABOVE_LOC 8
 383
 384 /* MDP_{PRIMARY,SECONDARY,EXTERNAL}_VSYNC_OUT_CRL */
 385 #define VSYNC_PULSE_EN (1<<31)
 386 #define VSYNC_PULSE_INV (1<<30)
 387
 388 /* MDP_VSYNC_CTRL */
 389 #define DISP0_VSYNC_MAP_VSYNC0 0
 390 #define DISP0_VSYNC_MAP_VSYNC1 (1<<0)
 391 #define DISP0_VSYNC_MAP_VSYNC2 (1<<0)|(1<<1)
 392
 393 #define DISP1_VSYNC_MAP_VSYNC0 0
 394 #define DISP1_VSYNC_MAP_VSYNC1 (1<<2)
 395 #define DISP1_VSYNC_MAP_VSYNC2 (1<<2)|(1<<3)
 396
 397 #define PRIMARY_LCD_SYNC_EN (1<<4)
 398 #define PRIMARY_LCD_SYNC_DISABLE 0
 399
 400 #define SECONDARY_LCD_SYNC_EN (1<<5)
 401 #define SECONDARY_LCD_SYNC_DISABLE 0
 402
 403 #define EXTERNAL_LCD_SYNC_EN (1<<6)
 404 #define EXTERNAL_LCD_SYNC_DISABLE 0
 405
 406 /* MDP_VSYNC_THRESHOLD / MDP_FULL_BYPASS_WORD60 */
 407 #define VSYNC_THRESHOLD_ABOVE_LOC 0
 408 #define VSYNC_THRESHOLD_BELOW_LOC 16
 409 #define VSYNC_ANTI_TEAR_EN (1<<31)
 410
 411 /* MDP_COMMAND_CONFIG / MDP_FULL_BYPASS_WORD1 */
 412 #define MDP_CMD_DBGBUS_EN (1<<0)
 413
 414 /* MDP_PPP_SOURCE_CONFIG / MDP_FULL_BYPASS_WORD9&53 */
 415 #define PPP_SRC_C0G_8BIT ((1<<1)|(1<<0))
 416 #define PPP_SRC_C1B_8BIT ((1<<3)|(1<<2))
 417 #define PPP_SRC_C2R_8BIT ((1<<5)|(1<<4))
 418 #define PPP_SRC_C3A_8BIT ((1<<7)|(1<<6))
 419
 420 #define PPP_SRC_C0G_6BIT (1<<1)
 421 #define PPP_SRC_C1B_6BIT (1<<3)
 422 #define PPP_SRC_C2R_6BIT (1<<5)
 423
 424 #define PPP_SRC_C0G_5BIT (1<<0)
 425 #define PPP_SRC_C1B_5BIT (1<<2)
 426 #define PPP_SRC_C2R_5BIT (1<<4)
 427
 428 #define PPP_SRC_C3ALPHA_EN (1<<8)
 429
 430 #define PPP_SRC_BPP_1BYTES 0
 431 #define PPP_SRC_BPP_2BYTES (1<<9)
 432 #define PPP_SRC_BPP_3BYTES (1<<10)
 433 #define PPP_SRC_BPP_4BYTES ((1<<10)|(1<<9))
 434
 435 #define PPP_SRC_BPP_ROI_ODD_X (1<<11)
 436 #define PPP_SRC_BPP_ROI_ODD_Y (1<<12)
 437 #define PPP_SRC_INTERLVD_2COMPONENTS (1<<13)
 438 #define PPP_SRC_INTERLVD_3COMPONENTS (1<<14)
 439 #define PPP_SRC_INTERLVD_4COMPONENTS ((1<<14)|(1<<13))
 440
 441
 442 /* RGB666 unpack format
 443 ** TIGHT means R6+G6+B6 together
 444 ** LOOSE means R6+2 +G6+2+ B6+2 (with MSB)
 445 **          or 2+R6 +2+G6 +2+B6 (with LSB)
 446 */
 447 #define PPP_SRC_PACK_TIGHT (1<<17)
 448 #define PPP_SRC_PACK_LOOSE 0
 449 #define PPP_SRC_PACK_ALIGN_LSB 0
 450 #define PPP_SRC_PACK_ALIGN_MSB (1<<18)
 451
 452 #define PPP_SRC_PLANE_INTERLVD 0
 453 #define PPP_SRC_PLANE_PSEUDOPLNR (1<<20)
 454
 455 #define PPP_SRC_WMV9_MODE (1<<21)
 456
 457 /* MDP_PPP_OPERATION_CONFIG / MDP_FULL_BYPASS_WORD14 */
 458 #define PPP_OP_SCALE_X_ON (1<<0)
 459 #define PPP_OP_SCALE_Y_ON (1<<1)
 460
 461 #ifndef CONFIG_MSM_MDP31
 462 #define PPP_OP_CONVERT_RGB2YCBCR 0
 463 #else
 464 #define PPP_OP_CONVERT_RGB2YCBCR (1<<30)
 465 #endif
 466
 467 #define PPP_OP_CONVERT_YCBCR2RGB (1<<2)
 468 #define PPP_OP_CONVERT_ON (1<<3)
 469
 470 #define PPP_OP_CONVERT_MATRIX_PRIMARY 0
 471 #define PPP_OP_CONVERT_MATRIX_SECONDARY (1<<4)
 472
 473 #define PPP_OP_LUT_C0_ON (1<<5)
 474 #define PPP_OP_LUT_C1_ON (1<<6)
 475 #define PPP_OP_LUT_C2_ON (1<<7)
 476
 477 /* rotate or blend enable */
 478 #define PPP_OP_ROT_ON (1<<8)
 479
 480 #define PPP_OP_ROT_90 (1<<9)
 481 #define PPP_OP_FLIP_LR (1<<10)
 482 #define PPP_OP_FLIP_UD (1<<11)
 483
 484 #define PPP_OP_BLEND_ON (1<<12)
 485
 486 #define PPP_OP_BLEND_SRCPIXEL_ALPHA 0
 487 #define PPP_OP_BLEND_DSTPIXEL_ALPHA (1<<13)
 488 #define PPP_OP_BLEND_CONSTANT_ALPHA (1<<14)
 489 #define PPP_OP_BLEND_SRCPIXEL_TRANSP ((1<<13)|(1<<14))
 490
 491 #define PPP_OP_BLEND_ALPHA_BLEND_NORMAL 0
 492 #define PPP_OP_BLEND_ALPHA_BLEND_REVERSE (1<<15)
 493
 494 #define PPP_OP_DITHER_EN (1<<16)
 495
 496 #define PPP_OP_COLOR_SPACE_RGB 0
 497 #define PPP_OP_COLOR_SPACE_YCBCR (1<<17)
 498
 499 #define PPP_OP_SRC_CHROMA_RGB 0
 500 #define PPP_OP_SRC_CHROMA_H2V1 (1<<18)
 501 #define PPP_OP_SRC_CHROMA_H1V2 (1<<19)
 502 #define PPP_OP_SRC_CHROMA_420 ((1<<18)|(1<<19))
 503 #define PPP_OP_SRC_CHROMA_COSITE 0
 504 #define PPP_OP_SRC_CHROMA_OFFSITE (1<<20)
 505
 506 #define PPP_OP_DST_CHROMA_RGB 0
 507 #define PPP_OP_DST_CHROMA_H2V1 (1<<21)
 508 #define PPP_OP_DST_CHROMA_H1V2 (1<<22)
 509 #define PPP_OP_DST_CHROMA_420 ((1<<21)|(1<<22))
 510 #define PPP_OP_DST_CHROMA_COSITE 0
 511 #define PPP_OP_DST_CHROMA_OFFSITE (1<<23)
 512
 513 #define PPP_BLEND_ALPHA_TRANSP (1<<24)
 514
 515 #define PPP_OP_BG_CHROMA_RGB 0
 516 #define PPP_OP_BG_CHROMA_H2V1 (1<<25)
 517 #define PPP_OP_BG_CHROMA_H1V2 (1<<26)
 518 #define PPP_OP_BG_CHROMA_420 ((1<<25)|(1<<26))
 519 #define PPP_OP_BG_CHROMA_SITE_COSITE 0
 520 #define PPP_OP_BG_CHROMA_SITE_OFFSITE (1<<27)
 521
 522 #define PPP_BLEND_BG_USE_ALPHA_SEL      (1 << 0)
 523 #define PPP_BLEND_BG_ALPHA_REVERSE      (1 << 3)
 524 #define PPP_BLEND_BG_SRCPIXEL_ALPHA     (0 << 1)
 525 #define PPP_BLEND_BG_DSTPIXEL_ALPHA     (1 << 1)
 526 #define PPP_BLEND_BG_CONSTANT_ALPHA     (2 << 1)
 527 #define PPP_BLEND_BG_CONST_ALPHA_VAL(x) ((x) << 24)
 528
 529 /* MDP_PPP_DESTINATION_CONFIG / MDP_FULL_BYPASS_WORD20 */
 530 #define PPP_DST_C0G_8BIT ((1<<0)|(1<<1))
 531 #define PPP_DST_C1B_8BIT ((1<<3)|(1<<2))
 532 #define PPP_DST_C2R_8BIT ((1<<5)|(1<<4))
 533 #define PPP_DST_C3A_8BIT ((1<<7)|(1<<6))
 534
 535 #define PPP_DST_C0G_6BIT (1<<1)
 536 #define PPP_DST_C1B_6BIT (1<<3)
 537 #define PPP_DST_C2R_6BIT (1<<5)
 538
 539 #define PPP_DST_C0G_5BIT (1<<0)
 540 #define PPP_DST_C1B_5BIT (1<<2)
 541 #define PPP_DST_C2R_5BIT (1<<4)
 542
 543 #define PPP_DST_C3A_8BIT ((1<<7)|(1<<6))
 544 #define PPP_DST_C3ALPHA_EN (1<<8)
 545
 546 #define PPP_DST_INTERLVD_2COMPONENTS (1<<9)
 547 #define PPP_DST_INTERLVD_3COMPONENTS (1<<10)
 548 #define PPP_DST_INTERLVD_4COMPONENTS ((1<<10)|(1<<9))
 549 #define PPP_DST_INTERLVD_6COMPONENTS ((1<<11)|(1<<9))
 550
 551 #define PPP_DST_PACK_LOOSE 0
 552 #define PPP_DST_PACK_TIGHT (1<<13)
 553 #define PPP_DST_PACK_ALIGN_LSB 0
 554 #define PPP_DST_PACK_ALIGN_MSB (1<<14)
 555
 556 #define PPP_DST_OUT_SEL_AXI 0
 557 #define PPP_DST_OUT_SEL_MDDI (1<<15)
 558
 559 #define PPP_DST_BPP_2BYTES (1<<16)
 560 #define PPP_DST_BPP_3BYTES (1<<17)
 561 #define PPP_DST_BPP_4BYTES ((1<<17)|(1<<16))
 562
 563 #define PPP_DST_PLANE_INTERLVD 0
 564 #define PPP_DST_PLANE_PLANAR (1<<18)
 565 #define PPP_DST_PLANE_PSEUDOPLNR (1<<19)
 566
 567 #define PPP_DST_TO_TV (1<<20)
 568
 569 #define PPP_DST_MDDI_PRIMARY 0
 570 #define PPP_DST_MDDI_SECONDARY (1<<21)
 571 #define PPP_DST_MDDI_EXTERNAL (1<<22)
 572
 573 /* image configurations by image type */
 574 #define PPP_CFG_MDP_RGB_565(dir)       (PPP_##dir##_C2R_5BIT | \
 575                                         PPP_##dir##_C0G_6BIT | \
 576                                         PPP_##dir##_C1B_5BIT | \
 577                                         PPP_##dir##_BPP_2BYTES | \
 578                                         PPP_##dir##_INTERLVD_3COMPONENTS | \
 579                                         PPP_##dir##_PACK_TIGHT | \
 580                                         PPP_##dir##_PACK_ALIGN_LSB | \
 581                                         PPP_##dir##_PLANE_INTERLVD)
 582
 583 #define PPP_CFG_MDP_RGB_888(dir)       (PPP_##dir##_C2R_8BIT | \
 584                                         PPP_##dir##_C0G_8BIT | \
 585                                         PPP_##dir##_C1B_8BIT | \
 586                                         PPP_##dir##_BPP_3BYTES | \
 587                                         PPP_##dir##_INTERLVD_3COMPONENTS | \
 588                                         PPP_##dir##_PACK_TIGHT | \
 589                                         PPP_##dir##_PACK_ALIGN_LSB | \
 590                                         PPP_##dir##_PLANE_INTERLVD)
 591
 592 #define PPP_CFG_MDP_ARGB_8888(dir)     (PPP_##dir##_C2R_8BIT | \
 593                                         PPP_##dir##_C0G_8BIT | \
 594                                         PPP_##dir##_C1B_8BIT | \
 595                                         PPP_##dir##_C3A_8BIT | \
 596                                         PPP_##dir##_C3ALPHA_EN | \
 597                                         PPP_##dir##_BPP_4BYTES | \
 598                                         PPP_##dir##_INTERLVD_4COMPONENTS | \
 599                                         PPP_##dir##_PACK_TIGHT | \
 600                                         PPP_##dir##_PACK_ALIGN_LSB | \
 601                                         PPP_##dir##_PLANE_INTERLVD)
 602
 603 #define PPP_CFG_MDP_XRGB_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 604 #define PPP_CFG_MDP_RGBA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 605 #define PPP_CFG_MDP_BGRA_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 606 #define PPP_CFG_MDP_RGBX_8888(dir) PPP_CFG_MDP_ARGB_8888(dir)
 607
 608 #define PPP_CFG_MDP_Y_CBCR_H2V2(dir)   (PPP_##dir##_C2R_8BIT | \
 609                                         PPP_##dir##_C0G_8BIT | \
 610                                         PPP_##dir##_C1B_8BIT | \
 611                                         PPP_##dir##_C3A_8BIT | \
 612                                         PPP_##dir##_BPP_2BYTES | \
 613                                         PPP_##dir##_INTERLVD_2COMPONENTS | \
 614                                         PPP_##dir##_PACK_TIGHT | \
 615                                         PPP_##dir##_PACK_ALIGN_LSB | \
 616                                         PPP_##dir##_PLANE_PSEUDOPLNR)
 617
 618 #define PPP_CFG_MDP_Y_CRCB_H2V2(dir)    PPP_CFG_MDP_Y_CBCR_H2V2(dir)
 619
 620 #define PPP_CFG_MDP_YCRYCB_H2V1(dir)   (PPP_##dir##_C2R_8BIT | \
 621                                         PPP_##dir##_C0G_8BIT | \
 622                                         PPP_##dir##_C1B_8BIT | \
 623                                         PPP_##dir##_C3A_8BIT | \
 624                                         PPP_##dir##_BPP_2BYTES | \
 625                                         PPP_##dir##_INTERLVD_4COMPONENTS | \
 626                                         PPP_##dir##_PACK_TIGHT | \
 627                                         PPP_##dir##_PACK_ALIGN_LSB |\
 628                                         PPP_##dir##_PLANE_INTERLVD)
 629
 630 #define PPP_CFG_MDP_Y_CBCR_H2V1(dir)   (PPP_##dir##_C2R_8BIT | \
 631                                         PPP_##dir##_C0G_8BIT | \
 632                                         PPP_##dir##_C1B_8BIT | \
 633                                         PPP_##dir##_C3A_8BIT | \
 634                                         PPP_##dir##_BPP_2BYTES |   \
 635                                         PPP_##dir##_INTERLVD_2COMPONENTS |  \
 636                                         PPP_##dir##_PACK_TIGHT | \
 637                                         PPP_##dir##_PACK_ALIGN_LSB | \
 638                                         PPP_##dir##_PLANE_PSEUDOPLNR)
 639
 640 #define PPP_CFG_MDP_Y_CRCB_H2V1(dir)    PPP_CFG_MDP_Y_CBCR_H2V1(dir)
 641
 642 #define PPP_PACK_PATTERN_MDP_RGB_565 \
 643         MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 8)
 644 #define PPP_PACK_PATTERN_MDP_RGB_888 PPP_PACK_PATTERN_MDP_RGB_565
 645 #define PPP_PACK_PATTERN_MDP_XRGB_8888 \
 646         MDP_GET_PACK_PATTERN(CLR_B, CLR_G, CLR_R, CLR_ALPHA, 8)
 647 #define PPP_PACK_PATTERN_MDP_ARGB_8888 PPP_PACK_PATTERN_MDP_XRGB_8888
 648 #define PPP_PACK_PATTERN_MDP_RGBA_8888 \
 649         MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8)
 650 #define PPP_PACK_PATTERN_MDP_BGRA_8888 \
 651         MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_R, CLR_G, CLR_B, 8)
 652 #define PPP_PACK_PATTERN_MDP_RGBX_8888 \
 653         MDP_GET_PACK_PATTERN(CLR_ALPHA, CLR_B, CLR_G, CLR_R, 8)
 654 #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1 \
 655         MDP_GET_PACK_PATTERN(0, 0, CLR_CB, CLR_CR, 8)
 656 #define PPP_PACK_PATTERN_MDP_Y_CBCR_H2V2 PPP_PACK_PATTERN_MDP_Y_CBCR_H2V1
 657 #define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1 \
 658         MDP_GET_PACK_PATTERN(0, 0, CLR_CR, CLR_CB, 8)
 659 #define PPP_PACK_PATTERN_MDP_Y_CRCB_H2V2 PPP_PACK_PATTERN_MDP_Y_CRCB_H2V1
 660 #define PPP_PACK_PATTERN_MDP_YCRYCB_H2V1 \
 661         MDP_GET_PACK_PATTERN(CLR_Y, CLR_R, CLR_Y, CLR_B, 8)
 662
 663 #define PPP_CHROMA_SAMP_MDP_RGB_565(dir) PPP_OP_##dir##_CHROMA_RGB
 664 #define PPP_CHROMA_SAMP_MDP_RGB_888(dir) PPP_OP_##dir##_CHROMA_RGB
 665 #define PPP_CHROMA_SAMP_MDP_XRGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 666 #define PPP_CHROMA_SAMP_MDP_ARGB_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 667 #define PPP_CHROMA_SAMP_MDP_RGBA_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 668 #define PPP_CHROMA_SAMP_MDP_BGRA_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 669 #define PPP_CHROMA_SAMP_MDP_RGBX_8888(dir) PPP_OP_##dir##_CHROMA_RGB
 670 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
 671 #define PPP_CHROMA_SAMP_MDP_Y_CBCR_H2V2(dir) PPP_OP_##dir##_CHROMA_420
 672 #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
 673 #define PPP_CHROMA_SAMP_MDP_Y_CRCB_H2V2(dir) PPP_OP_##dir##_CHROMA_420
 674 #define PPP_CHROMA_SAMP_MDP_YCRYCB_H2V1(dir) PPP_OP_##dir##_CHROMA_H2V1
 675
 676 /* Helpful array generation macros */
 677 #define PPP_ARRAY0(name) \
 678         [MDP_RGB_565] = PPP_##name##_MDP_RGB_565,\
 679         [MDP_RGB_888] = PPP_##name##_MDP_RGB_888,\
 680         [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888,\
 681         [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888,\
 682         [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888,\
 683         [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888,\
 684         [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888,\
 685         [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1,\
 686         [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2,\
 687         [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1,\
 688         [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2,\
 689         [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1
 690
 691 #define PPP_ARRAY1(name, dir) \
 692         [MDP_RGB_565] = PPP_##name##_MDP_RGB_565(dir),\
 693         [MDP_RGB_888] = PPP_##name##_MDP_RGB_888(dir),\
 694         [MDP_XRGB_8888] = PPP_##name##_MDP_XRGB_8888(dir),\
 695         [MDP_ARGB_8888] = PPP_##name##_MDP_ARGB_8888(dir),\
 696         [MDP_RGBA_8888] = PPP_##name##_MDP_RGBA_8888(dir),\
 697         [MDP_BGRA_8888] = PPP_##name##_MDP_BGRA_8888(dir),\
 698         [MDP_RGBX_8888] = PPP_##name##_MDP_RGBX_8888(dir),\
 699         [MDP_Y_CBCR_H2V1] = PPP_##name##_MDP_Y_CBCR_H2V1(dir),\
 700         [MDP_Y_CBCR_H2V2] = PPP_##name##_MDP_Y_CBCR_H2V2(dir),\
 701         [MDP_Y_CRCB_H2V1] = PPP_##name##_MDP_Y_CRCB_H2V1(dir),\
 702         [MDP_Y_CRCB_H2V2] = PPP_##name##_MDP_Y_CRCB_H2V2(dir),\
 703         [MDP_YCRYCB_H2V1] = PPP_##name##_MDP_YCRYCB_H2V1(dir)
 704
 705 #define IS_YCRCB(img) ((img == MDP_Y_CRCB_H2V2) | (img == MDP_Y_CBCR_H2V2) | \
 706                        (img == MDP_Y_CRCB_H2V1) | (img == MDP_Y_CBCR_H2V1) | \
 707                        (img == MDP_YCRYCB_H2V1))
 708 #define IS_RGB(img) ((img == MDP_RGB_565) | (img == MDP_RGB_888) | \
 709                      (img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
 710                      (img == MDP_XRGB_8888) | (img == MDP_BGRA_8888) | \
 711                      (img == MDP_RGBX_8888))
 712 #define HAS_ALPHA(img) ((img == MDP_ARGB_8888) | (img == MDP_RGBA_8888) | \
 713                         (img == MDP_BGRA_8888))
 714
 715 #define IS_PSEUDOPLNR(img) ((img == MDP_Y_CRCB_H2V2) | \
 716                             (img == MDP_Y_CBCR_H2V2) | \
 717                             (img == MDP_Y_CRCB_H2V1) | \
 718                             (img == MDP_Y_CBCR_H2V1))
 719
 720 /* Mappings from addr to purpose */
 721 #define PPP_ADDR_SRC_ROI                MDP_FULL_BYPASS_WORD2
 722 #define PPP_ADDR_SRC0                   MDP_FULL_BYPASS_WORD3
 723 #define PPP_ADDR_SRC1                   MDP_FULL_BYPASS_WORD4
 724 #define PPP_ADDR_SRC_YSTRIDE            MDP_FULL_BYPASS_WORD7
 725 #define PPP_ADDR_SRC_CFG                MDP_FULL_BYPASS_WORD9
 726 #define PPP_ADDR_SRC_PACK_PATTERN       MDP_FULL_BYPASS_WORD10
 727 #define PPP_ADDR_OPERATION              MDP_FULL_BYPASS_WORD14
 728 #define PPP_ADDR_PHASEX_INIT            MDP_FULL_BYPASS_WORD15
 729 #define PPP_ADDR_PHASEY_INIT            MDP_FULL_BYPASS_WORD16
 730 #define PPP_ADDR_PHASEX_STEP            MDP_FULL_BYPASS_WORD17
 731 #define PPP_ADDR_PHASEY_STEP            MDP_FULL_BYPASS_WORD18
 732 #define PPP_ADDR_ALPHA_TRANSP           MDP_FULL_BYPASS_WORD19
 733 #define PPP_ADDR_DST_CFG                MDP_FULL_BYPASS_WORD20
 734 #define PPP_ADDR_DST_PACK_PATTERN       MDP_FULL_BYPASS_WORD21
 735 #define PPP_ADDR_DST_ROI                MDP_FULL_BYPASS_WORD25
 736 #define PPP_ADDR_DST0                   MDP_FULL_BYPASS_WORD26
 737 #define PPP_ADDR_DST1                   MDP_FULL_BYPASS_WORD27
 738 #define PPP_ADDR_DST_YSTRIDE            MDP_FULL_BYPASS_WORD30
 739 #define PPP_ADDR_EDGE                   MDP_FULL_BYPASS_WORD46
 740 #define PPP_ADDR_BG0                    MDP_FULL_BYPASS_WORD48
 741 #define PPP_ADDR_BG1                    MDP_FULL_BYPASS_WORD49
 742 #define PPP_ADDR_BG_YSTRIDE             MDP_FULL_BYPASS_WORD51
 743 #define PPP_ADDR_BG_CFG                 MDP_FULL_BYPASS_WORD53
 744 #define PPP_ADDR_BG_PACK_PATTERN        MDP_FULL_BYPASS_WORD54
 745
 746 /* color conversion matrix configuration registers */
 747 /* pfmv is mv1, prmv is mv2 */
 748 #define MDP_CSC_PFMVn(n)                (0x40400 + (4 * (n)))
 749 #define MDP_CSC_PRMVn(n)                (0x40440 + (4 * (n)))
 750
 751 #ifdef CONFIG_MSM_MDP31
 752 #define MDP_PPP_CSC_PRE_BV1n(n)         (0x40500 + (4 * (n)))
 753 #define MDP_PPP_CSC_PRE_BV2n(n)         (0x40540 + (4 * (n)))
 754 #define MDP_PPP_CSC_POST_BV1n(n)        (0x40580 + (4 * (n)))
 755 #define MDP_PPP_CSC_POST_BV2n(n)        (0x405c0 + (4 * (n)))
 756
 757 #define MDP_PPP_CSC_PRE_LV1n(n)         (0x40600 + (4 * (n)))
 758 #define MDP_PPP_CSC_PRE_LV2n(n)         (0x40640 + (4 * (n)))
 759 #define MDP_PPP_CSC_POST_LV1n(n)        (0x40680 + (4 * (n)))
 760 #define MDP_PPP_CSC_POST_LV2n(n)        (0x406c0 + (4 * (n)))
 761
 762 #define MDP_PPP_SCALE_COEFF_D0_SET      (0)
 763 #define MDP_PPP_SCALE_COEFF_D1_SET      (1)
 764 #define MDP_PPP_SCALE_COEFF_D2_SET      (2)
 765 #define MDP_PPP_SCALE_COEFF_U1_SET      (3)
 766 #define MDP_PPP_SCALE_COEFF_LSBn(n)     (0x50400 + (8 * (n)))
 767 #define MDP_PPP_SCALE_COEFF_MSBn(n)     (0x50404 + (8 * (n)))
 768
 769 #define MDP_PPP_DEINT_COEFFn(n)         (0x30010 + (4 * (n)))
 770
 771 #define MDP_PPP_SCALER_FIR              (0)
 772 #define MDP_PPP_SCALER_MN               (1)
 773
 774 #else /* !defined(CONFIG_MSM_MDP31) */
 775
 776 #define MDP_CSC_PBVn(n)                 (0x40500 + (4 * (n)))
 777 #define MDP_CSC_SBVn(n)                 (0x40540 + (4 * (n)))
 778 #define MDP_CSC_PLVn(n)                 (0x40580 + (4 * (n)))
 779 #define MDP_CSC_SLVn(n)                 (0x405c0 + (4 * (n)))
 780
 781 #endif
 782
 783
 784 /* MDP_DMA_CONFIG / MDP_FULL_BYPASS_WORD32 */
 785 #define DMA_DSTC0G_5BITS (1<<0)
 786 #define DMA_DSTC1B_5BITS (1<<2)
 787 #define DMA_DSTC2R_5BITS (1<<4)
 788
 789 #define DMA_DSTC0G_6BITS (2<<0)
 790 #define DMA_DSTC1B_6BITS (2<<2)
 791 #define DMA_DSTC2R_6BITS (2<<4)
 792
 793 #define DMA_DSTC0G_8BITS (3<<0)
 794 #define DMA_DSTC1B_8BITS (3<<2)
 795 #define DMA_DSTC2R_8BITS (3<<4)
 796
 797 #define DMA_DST_BITS_MASK 0x3F
 798
 799 #define DMA_PACK_TIGHT (1<<6)
 800 #define DMA_PACK_LOOSE 0
 801 #define DMA_PACK_ALIGN_LSB 0
 802 #define DMA_PACK_ALIGN_MSB (1<<7)
 803 #define DMA_PACK_PATTERN_MASK (0x3f<<8)
 804 #define DMA_PACK_PATTERN_RGB \
 805         (MDP_GET_PACK_PATTERN(0, CLR_R, CLR_G, CLR_B, 2)<<8)
 806 #define DMA_PACK_PATTERN_BGR \
 807         (MDP_GET_PACK_PATTERN(0, CLR_B, CLR_G, CLR_R, 2)<<8)
 808
 809
 810 #ifdef CONFIG_MSM_MDP22
 811
 812 #define DMA_OUT_SEL_AHB  0
 813 #define DMA_OUT_SEL_MDDI (1<<14)
 814 #define DMA_AHBM_LCD_SEL_PRIMARY 0
 815 #define DMA_AHBM_LCD_SEL_SECONDARY (1<<15)
 816 #define DMA_IBUF_C3ALPHA_EN (1<<16)
 817 #define DMA_DITHER_EN (1<<17)
 818 #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0
 819 #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY (1<<18)
 820 #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL (1<<19)
 821 #define DMA_IBUF_FORMAT_RGB565 (1<<20)
 822 #define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 0
 823 #define DMA_IBUF_FORMAT_MASK (1 << 20)
 824 #define DMA_IBUF_NONCONTIGUOUS (1<<21)
 825
 826 #elif defined(CONFIG_MSM_MDP30)
 827
 828 #define DMA_OUT_SEL_AHB  0
 829 #define DMA_OUT_SEL_MDDI (1<<19)
 830 #define DMA_AHBM_LCD_SEL_PRIMARY 0
 831 #define DMA_AHBM_LCD_SEL_SECONDARY (0)
 832 #define DMA_IBUF_C3ALPHA_EN (0)
 833 #define DMA_DITHER_EN (1<<24)
 834
 835 #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY 0
 836 #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY (0)
 837 #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL (0)
 838
 839 #define DMA_IBUF_FORMAT_MASK (1 << 20)
 840 #define DMA_IBUF_FORMAT_RGB565 (1<<25)
 841 #define DMA_IBUF_FORMAT_RGB888_OR_ARGB8888 (1<<26)
 842 #define DMA_IBUF_NONCONTIGUOUS (0)
 843
 844 #else /* CONFIG_MSM_MDP31 | CONFIG_MSM_MDP302 */
 845
 846 #define DMA_OUT_SEL_AHB                         (0 << 19)
 847 #define DMA_OUT_SEL_MDDI                        (1 << 19)
 848 #define DMA_OUT_SEL_LCDC                        (2 << 19)
 849 #define DMA_OUT_SEL_LCDC_MDDI                   (3 << 19)
 850 #define DMA_DITHER_EN                           (1 << 24)
 851 #define DMA_IBUF_FORMAT_RGB888                  (0 << 25)
 852 #define DMA_IBUF_FORMAT_RGB565                  (1 << 25)
 853 #define DMA_IBUF_FORMAT_XRGB8888                (2 << 25)
 854 #define DMA_IBUF_FORMAT_MASK                    (3 << 25)
 855 #define DMA_IBUF_NONCONTIGUOUS                  (0)
 856
 857 #define DMA_MDDI_DMAOUT_LCD_SEL_PRIMARY         (0)
 858 #define DMA_MDDI_DMAOUT_LCD_SEL_SECONDARY       (0)
 859 #define DMA_MDDI_DMAOUT_LCD_SEL_EXTERNAL        (0)
 860 #endif
 861
 862 /* MDDI REGISTER ? */
 863 #define MDDI_VDO_PACKET_DESC_RGB565  0x5565
 864 #define MDDI_VDO_PACKET_DESC_RGB666  0x5666
 865 #define MDDI_VDO_PACKET_PRIM  0xC3
 866 #define MDDI_VDO_PACKET_SECD  0xC0
 867
 868 #endif