drivers/video/msm/mddi_hw.h

   1 /* drivers/video/msm_fb/mddi_hw.h
   2  *
   3  * MSM MDDI Hardware Registers and Structures
   4  *
   5  * Copyright (C) 2007 QUALCOMM Incorporated
   6  * Copyright (C) 2007 Google Incorporated
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #ifndef _MDDI_HW_H_
  19 #define _MDDI_HW_H_
  20
  21 #include <linux/types.h>
  22
  23 #define MDDI_CMD                0x0000
  24 #define MDDI_VERSION            0x0004
  25 #define MDDI_PRI_PTR            0x0008
  26 #define MDDI_SEC_PTR            0x000c
  27 #define MDDI_BPS                0x0010
  28 #define MDDI_SPM                0x0014
  29 #define MDDI_INT                0x0018
  30 #define MDDI_INTEN              0x001c
  31 #define MDDI_REV_PTR            0x0020
  32 #define MDDI_REV_SIZE           0x0024
  33 #define MDDI_STAT               0x0028
  34 #define MDDI_REV_RATE_DIV       0x002c
  35 #define MDDI_REV_CRC_ERR        0x0030
  36 #define MDDI_TA1_LEN            0x0034
  37 #define MDDI_TA2_LEN            0x0038
  38 #define MDDI_TEST_BUS           0x003c
  39 #define MDDI_TEST               0x0040
  40 #define MDDI_REV_PKT_CNT        0x0044
  41 #define MDDI_DRIVE_HI           0x0048
  42 #define MDDI_DRIVE_LO           0x004c
  43 #define MDDI_DISP_WAKE          0x0050
  44 #define MDDI_REV_ENCAP_SZ       0x0054
  45 #define MDDI_RTD_VAL            0x0058
  46 #define MDDI_PAD_CTL            0x0068
  47 #define MDDI_DRIVER_START_CNT   0x006c
  48 #define MDDI_NEXT_PRI_PTR       0x0070
  49 #define MDDI_NEXT_SEC_PTR       0x0074
  50 #define MDDI_MISR_CTL           0x0078
  51 #define MDDI_MISR_DATA          0x007c
  52 #define MDDI_SF_CNT             0x0080
  53 #define MDDI_MF_CNT             0x0084
  54 #define MDDI_CURR_REV_PTR       0x0088
  55 #define MDDI_CORE_VER           0x008c
  56 #define MDDI_PAD_IO_CTL         0x00a0
  57 #define MDDI_PAD_CAL            0x00a4
  58
  59 #define MDDI_INT_PRI_PTR_READ       0x0001
  60 #define MDDI_INT_SEC_PTR_READ       0x0002
  61 #define MDDI_INT_REV_DATA_AVAIL     0x0004
  62 #define MDDI_INT_DISP_REQ           0x0008
  63 #define MDDI_INT_PRI_UNDERFLOW      0x0010
  64 #define MDDI_INT_SEC_UNDERFLOW      0x0020
  65 #define MDDI_INT_REV_OVERFLOW       0x0040
  66 #define MDDI_INT_CRC_ERROR          0x0080
  67 #define MDDI_INT_MDDI_IN            0x0100
  68 #define MDDI_INT_PRI_OVERWRITE      0x0200
  69 #define MDDI_INT_SEC_OVERWRITE      0x0400
  70 #define MDDI_INT_REV_OVERWRITE      0x0800
  71 #define MDDI_INT_DMA_FAILURE        0x1000
  72 #define MDDI_INT_LINK_ACTIVE        0x2000
  73 #define MDDI_INT_IN_HIBERNATION     0x4000
  74 #define MDDI_INT_PRI_LINK_LIST_DONE 0x8000
  75 #define MDDI_INT_SEC_LINK_LIST_DONE 0x10000
  76 #define MDDI_INT_NO_CMD_PKTS_PEND   0x20000
  77 #define MDDI_INT_RTD_FAILURE        0x40000
  78 #define MDDI_INT_REV_PKT_RECEIVED   0x80000
  79 #define MDDI_INT_REV_PKTS_AVAIL     0x100000
  80
  81 #define MDDI_INT_NEED_CLEAR ( \
  82         MDDI_INT_REV_DATA_AVAIL | \
  83         MDDI_INT_PRI_UNDERFLOW | \
  84         MDDI_INT_SEC_UNDERFLOW | \
  85         MDDI_INT_REV_OVERFLOW | \
  86         MDDI_INT_CRC_ERROR | \
  87         MDDI_INT_REV_PKT_RECEIVED)
  88
  89
  90 #define MDDI_STAT_LINK_ACTIVE        0x0001
  91 #define MDDI_STAT_NEW_REV_PTR        0x0002
  92 #define MDDI_STAT_NEW_PRI_PTR        0x0004
  93 #define MDDI_STAT_NEW_SEC_PTR        0x0008
  94 #define MDDI_STAT_IN_HIBERNATION     0x0010
  95 #define MDDI_STAT_PRI_LINK_LIST_DONE 0x0020
  96 #define MDDI_STAT_SEC_LINK_LIST_DONE 0x0040
  97 #define MDDI_STAT_PENDING_TIMING_PKT 0x0080
  98 #define MDDI_STAT_PENDING_REV_ENCAP  0x0100
  99 #define MDDI_STAT_PENDING_POWERDOWN  0x0200
 100 #define MDDI_STAT_RTD_MEAS_FAIL      0x0800
 101 #define MDDI_STAT_CLIENT_WAKEUP_REQ  0x1000
 102
 103
 104 #define MDDI_CMD_POWERDOWN           0x0100
 105 #define MDDI_CMD_POWERUP             0x0200
 106 #define MDDI_CMD_HIBERNATE           0x0300
 107 #define MDDI_CMD_RESET               0x0400
 108 #define MDDI_CMD_DISP_IGNORE         0x0501
 109 #define MDDI_CMD_DISP_LISTEN         0x0500
 110 #define MDDI_CMD_SEND_REV_ENCAP      0x0600
 111 #define MDDI_CMD_GET_CLIENT_CAP      0x0601
 112 #define MDDI_CMD_GET_CLIENT_STATUS   0x0602
 113 #define MDDI_CMD_SEND_RTD            0x0700
 114 #define MDDI_CMD_LINK_ACTIVE         0x0900
 115 #define MDDI_CMD_PERIODIC_REV_ENCAP  0x0A00
 116 #define MDDI_CMD_FORCE_NEW_REV_PTR   0x0C00
 117 #define MDDI_CMD_SKEW_CALIBRATION    0x0D00
 118 #define MDDI_VIDEO_REV_PKT_SIZE              0x40
 119 #define MDDI_CLIENT_CAPABILITY_REV_PKT_SIZE  0x60
 120 #define MDDI_MAX_REV_PKT_SIZE                0x60
 121
 122 /* #define MDDI_REV_BUFFER_SIZE 128 */
 123 #define MDDI_REV_BUFFER_SIZE (MDDI_MAX_REV_PKT_SIZE * 4)
 124
 125 /* MDP sends 256 pixel packets, so lower value hibernates more without
 126  * significantly increasing latency of waiting for next subframe */
 127 #define MDDI_HOST_BYTES_PER_SUBFRAME  0x3C00
 128 #if defined (CONFIG_ARCH_QSD8X50) || defined (CONFIG_ARCH_MSM7X30)
 129 #define MDDI_HOST_TA2_LEN       0x001a
 130 #else
 131 #define MDDI_HOST_TA2_LEN       0x000c
 132 #endif
 133
 134 #if defined (CONFIG_ARCH_QSD8X50) || defined (CONFIG_ARCH_MSM7X30)
 135 #define MDDI_HOST_REV_RATE_DIV  0x0004
 136 #else
 137 #define MDDI_HOST_REV_RATE_DIV  0x0002
 138 #endif
 139
 140 struct __attribute__((packed)) mddi_rev_packet {
 141         uint16_t length;
 142         uint16_t type;
 143         uint16_t client_id;
 144 };
 145
 146 struct __attribute__((packed)) mddi_client_status {
 147         uint16_t length;
 148         uint16_t type;
 149         uint16_t client_id;
 150         uint16_t reverse_link_request;  /* bytes needed in rev encap message */
 151         uint8_t  crc_error_count;
 152         uint8_t  capability_change;
 153         uint16_t graphics_busy_flags;
 154         uint16_t crc16;
 155 };
 156
 157 struct __attribute__((packed)) mddi_client_caps {
 158         uint16_t length; /* length, exclusive of this field */
 159         uint16_t type; /* 66 */
 160         uint16_t client_id;
 161
 162         uint16_t Protocol_Version;
 163         uint16_t Minimum_Protocol_Version;
 164         uint16_t Data_Rate_Capability;
 165         uint8_t  Interface_Type_Capability;
 166         uint8_t  Number_of_Alt_Displays;
 167         uint16_t PostCal_Data_Rate;
 168         uint16_t Bitmap_Width;
 169         uint16_t Bitmap_Height;
 170         uint16_t Display_Window_Width;
 171         uint16_t Display_Window_Height;
 172         uint32_t Color_Map_Size;
 173         uint16_t Color_Map_RGB_Width;
 174         uint16_t RGB_Capability;
 175         uint8_t  Monochrome_Capability;
 176         uint8_t  Reserved_1;
 177         uint16_t Y_Cb_Cr_Capability;
 178         uint16_t Bayer_Capability;
 179         uint16_t Alpha_Cursor_Image_Planes;
 180         uint32_t Client_Feature_Capability_Indicators;
 181         uint8_t  Maximum_Video_Frame_Rate_Capability;
 182         uint8_t  Minimum_Video_Frame_Rate_Capability;
 183         uint16_t Minimum_Sub_frame_Rate;
 184         uint16_t Audio_Buffer_Depth;
 185         uint16_t Audio_Channel_Capability;
 186         uint16_t Audio_Sample_Rate_Capability;
 187         uint8_t  Audio_Sample_Resolution;
 188         uint8_t  Mic_Audio_Sample_Resolution;
 189         uint16_t Mic_Sample_Rate_Capability;
 190         uint8_t  Keyboard_Data_Format;
 191         uint8_t  pointing_device_data_format;
 192         uint16_t content_protection_type;
 193         uint16_t Mfr_Name;
 194         uint16_t Product_Code;
 195         uint16_t Reserved_3;
 196         uint32_t Serial_Number;
 197         uint8_t  Week_of_Manufacture;
 198         uint8_t  Year_of_Manufacture;
 199
 200         uint16_t crc16;
 201 } mddi_client_capability_type;
 202
 203
 204 struct __attribute__((packed)) mddi_video_stream {
 205         uint16_t length;
 206         uint16_t type; /* 16 */
 207         uint16_t client_id; /* 0 */
 208
 209         uint16_t video_data_format_descriptor;
 210 /* format of each pixel in the Pixel Data in the present stream in the
 211  * present packet.
 212  * If bits [15:13] = 000 monochrome
 213  * If bits [15:13] = 001 color pixels (palette).
 214  * If bits [15:13] = 010 color pixels in raw RGB
 215  * If bits [15:13] = 011 data in 4:2:2 Y Cb Cr format
 216  * If bits [15:13] = 100 Bayer pixels
 217  */
 218
 219         uint16_t pixel_data_attributes;
 220 /* interpreted as follows:
 221  * Bits [1:0] = 11  pixel data is displayed to both eyes
 222  * Bits [1:0] = 10  pixel data is routed to the left eye only.
 223  * Bits [1:0] = 01  pixel data is routed to the right eye only.
 224  * Bits [1:0] = 00  pixel data is routed to the alternate display.
 225  * Bit 2 is 0  Pixel Data is in the standard progressive format.
 226  * Bit 2 is 1  Pixel Data is in interlace format.
 227  * Bit 3 is 0  Pixel Data is in the standard progressive format.
 228  * Bit 3 is 1  Pixel Data is in alternate pixel format.
 229  * Bit 4 is 0  Pixel Data is to or from the display frame buffer.
 230  * Bit 4 is 1  Pixel Data is to or from the camera.
 231  * Bit 5 is 0  pixel data contains the next consecutive row of pixels.
 232  * Bit 5 is 1  X Left Edge, Y Top Edge, X Right Edge, Y Bottom Edge,
 233  *             X Start, and Y Start parameters are not defined and
 234  *             shall be ignored by the client.
 235  * Bits [7:6] = 01  Pixel data is written to the offline image buffer.
 236  * Bits [7:6] = 00  Pixel data is written to the buffer to refresh display.
 237  * Bits [7:6] = 11  Pixel data is written to all image buffers.
 238  * Bits [7:6] = 10  Invalid. Reserved for future use.
 239  * Bits 8 through 11 alternate display number.
 240  * Bits 12 through 14 are reserved for future use and shall be set to zero.
 241  * Bit 15 is 1 the row of pixels is the last row of pixels in a frame.
 242  */
 243
 244         uint16_t x_left_edge;
 245         uint16_t y_top_edge;
 246         /* X,Y coordinate of the top left edge of the screen window */
 247
 248         uint16_t x_right_edge;
 249         uint16_t y_bottom_edge;
 250         /* X,Y coordinate of the bottom right edge of the window being
 251          * updated. */
 252
 253         uint16_t x_start;
 254         uint16_t y_start;
 255         /* (X Start, Y Start) is the first pixel in the Pixel Data field
 256          * below. */
 257
 258         uint16_t pixel_count;
 259         /* number of pixels in the Pixel Data field below. */
 260
 261         uint16_t parameter_CRC;
 262         /* 16-bit CRC of all bytes from the Packet Length to the Pixel Count. */
 263
 264         uint16_t reserved;
 265         /* 16-bit variable to make structure align on 4 byte boundary */
 266 };
 267
 268 #define TYPE_VIDEO_STREAM      16
 269 #define TYPE_CLIENT_CAPS       66
 270 #define TYPE_REGISTER_ACCESS   146
 271 #define TYPE_CLIENT_STATUS     70
 272
 273 struct __attribute__((packed)) mddi_register_access {
 274         uint16_t length;
 275         uint16_t type; /* 146 */
 276         uint16_t client_id;
 277
 278         uint16_t read_write_info;
 279         /* Bits 13:0  a 14-bit unsigned integer that specifies the number of
 280          *            32-bit Register Data List items to be transferred in the
 281          *            Register Data List field.
 282          * Bits[15:14] = 00  Write to register(s);
 283          * Bits[15:14] = 10  Read from register(s);
 284          * Bits[15:14] = 11  Response to a Read.
 285          * Bits[15:14] = 01  this value is reserved for future use. */
 286 #define MDDI_WRITE     (0 << 14)
 287 #define MDDI_READ      (2 << 14)
 288 #define MDDI_READ_RESP (3 << 14)
 289
 290         uint32_t register_address;
 291         /* the register address that is to be written to or read from. */
 292
 293         uint16_t crc16;
 294
 295         union {
 296                 uint32_t reg_data;
 297                 uint32_t *reg_data_list;
 298         } u;
 299
 300         uint16_t crc_data;
 301 };
 302
 303 struct __attribute__((packed)) mddi_llentry {
 304         uint16_t flags;
 305         uint16_t header_count;
 306         uint16_t data_count;
 307         dma_addr_t data; /* 32 bit */
 308         struct mddi_llentry *next;
 309         uint16_t reserved;
 310         union {
 311                 struct mddi_video_stream v;
 312                 struct mddi_register_access r;
 313                 uint32_t _[12];
 314         } u;
 315 };
 316
 317 #endif