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htcleo: This adds an SMD channel on /dev/smd1 which can be used with pppd.
[htc-linux.git] / arch / arm / mach-msm / gpio.c
blob345e9a39eedb8292dcc7a5a6bf1ea7043fec5824
1 /* linux/arch/arm/mach-msm/gpio.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <asm/io.h>
17 #include <asm/gpio.h>
18 #include <linux/irq.h>
19 #include <linux/module.h>
20 #include "gpio_chip.h"
21 #include "gpio_hw.h"
22
23 #include "proc_comm.h"
24 #include "smd_private.h"
25
26 #ifdef CONFIG_HTC_SLEEP_MODE_GPIO_DUMP
27 #include "gpio_dump.h"
28 #endif
29
30 enum {
31 GPIO_DEBUG_SLEEP = 1U << 0,
32 };
33 static int msm_gpio_debug_mask = 0;
34 module_param_named(debug_mask, msm_gpio_debug_mask, int, S_IRUGO | S_IWUSR | S_IWGRP);
35
36
37 /* private gpio_configure flags */
38 #define MSM_GPIOF_ENABLE_INTERRUPT 0x10000000
39 #define MSM_GPIOF_DISABLE_INTERRUPT 0x20000000
40 #define MSM_GPIOF_ENABLE_WAKE 0x40000000
41 #define MSM_GPIOF_DISABLE_WAKE 0x80000000
42
43 static int msm_gpio_configure(struct gpio_chip *chip, unsigned int gpio, unsigned long flags);
44 static int msm_gpio_get_irq_num(struct gpio_chip *chip, unsigned int gpio, unsigned int *irqp, unsigned long *irqnumflagsp);
45 static int msm_gpio_read(struct gpio_chip *chip, unsigned n);
46 static int msm_gpio_write(struct gpio_chip *chip, unsigned n, unsigned on);
47 static int msm_gpio_read_detect_status(struct gpio_chip *chip, unsigned int gpio);
48 static int msm_gpio_clear_detect_status(struct gpio_chip *chip, unsigned int gpio);
49
50 struct msm_gpio_chip msm_gpio_chips[] = {
51 {
52 .regs = {
53 .out = GPIO_OUT_0,
54 .in = GPIO_IN_0,
55 .int_status = GPIO_INT_STATUS_0,
56 .int_clear = GPIO_INT_CLEAR_0,
57 .int_en = GPIO_INT_EN_0,
58 .int_edge = GPIO_INT_EDGE_0,
59 .int_pos = GPIO_INT_POS_0,
60 .oe = GPIO_OE_0,
61 },
62 .chip = {
63 .start = 0,
64 .end = 15,
65 .configure = msm_gpio_configure,
66 .get_irq_num = msm_gpio_get_irq_num,
67 .read = msm_gpio_read,
68 .write = msm_gpio_write,
69 .read_detect_status = msm_gpio_read_detect_status,
70 .clear_detect_status = msm_gpio_clear_detect_status
71 }
72 },
73 {
74 .regs = {
75 .out = GPIO_OUT_1,
76 .in = GPIO_IN_1,
77 .int_status = GPIO_INT_STATUS_1,
78 .int_clear = GPIO_INT_CLEAR_1,
79 .int_en = GPIO_INT_EN_1,
80 .int_edge = GPIO_INT_EDGE_1,
81 .int_pos = GPIO_INT_POS_1,
82 .oe = GPIO_OE_1,
83 },
84 .chip = {
85 .start = 16,
86 #if defined(CONFIG_ARCH_MSM7X30)
87 .end = 43,
88 #else
89 .end = 42,
90 #endif
91 .configure = msm_gpio_configure,
92 .get_irq_num = msm_gpio_get_irq_num,
93 .read = msm_gpio_read,
94 .write = msm_gpio_write,
95 .read_detect_status = msm_gpio_read_detect_status,
96 .clear_detect_status = msm_gpio_clear_detect_status
97 }
98 },
99 {
100 .regs = {
101 .out = GPIO_OUT_2,
102 .in = GPIO_IN_2,
103 .int_status = GPIO_INT_STATUS_2,
104 .int_clear = GPIO_INT_CLEAR_2,
105 .int_en = GPIO_INT_EN_2,
106 .int_edge = GPIO_INT_EDGE_2,
107 .int_pos = GPIO_INT_POS_2,
108 .oe = GPIO_OE_2,
109 },
110 .chip = {
111 #if defined(CONFIG_ARCH_MSM7X30)
112 .start = 44,
113 #else
114 .start = 43,
115 #endif
116 .end = 67,
117 .configure = msm_gpio_configure,
118 .get_irq_num = msm_gpio_get_irq_num,
119 .read = msm_gpio_read,
120 .write = msm_gpio_write,
121 .read_detect_status = msm_gpio_read_detect_status,
122 .clear_detect_status = msm_gpio_clear_detect_status
123 }
124 },
125 {
126 .regs = {
127 .out = GPIO_OUT_3,
128 .in = GPIO_IN_3,
129 .int_status = GPIO_INT_STATUS_3,
130 .int_clear = GPIO_INT_CLEAR_3,
131 .int_en = GPIO_INT_EN_3,
132 .int_edge = GPIO_INT_EDGE_3,
133 .int_pos = GPIO_INT_POS_3,
134 .oe = GPIO_OE_3,
135 },
136 .chip = {
137 .start = 68,
138 .end = 94,
139 .configure = msm_gpio_configure,
140 .get_irq_num = msm_gpio_get_irq_num,
141 .read = msm_gpio_read,
142 .write = msm_gpio_write,
143 .read_detect_status = msm_gpio_read_detect_status,
144 .clear_detect_status = msm_gpio_clear_detect_status
145 }
146 },
147 {
148 .regs = {
149 .out = GPIO_OUT_4,
150 .in = GPIO_IN_4,
151 .int_status = GPIO_INT_STATUS_4,
152 .int_clear = GPIO_INT_CLEAR_4,
153 .int_en = GPIO_INT_EN_4,
154 .int_edge = GPIO_INT_EDGE_4,
155 .int_pos = GPIO_INT_POS_4,
156 .oe = GPIO_OE_4,
157 },
158 .chip = {
159 .start = 95,
160 #if defined(CONFIG_ARCH_QSD8X50)
161 .end = 103,
162 #else
163 .end = 106,
164 #endif
165 .configure = msm_gpio_configure,
166 .get_irq_num = msm_gpio_get_irq_num,
167 .read = msm_gpio_read,
168 .write = msm_gpio_write,
169 .read_detect_status = msm_gpio_read_detect_status,
170 .clear_detect_status = msm_gpio_clear_detect_status
171 }
172 },
173 {
174 .regs = {
175 .out = GPIO_OUT_5,
176 .in = GPIO_IN_5,
177 .int_status = GPIO_INT_STATUS_5,
178 .int_clear = GPIO_INT_CLEAR_5,
179 .int_en = GPIO_INT_EN_5,
180 .int_edge = GPIO_INT_EDGE_5,
181 .int_pos = GPIO_INT_POS_5,
182 .oe = GPIO_OE_5,
183 },
184 .chip = {
185 #if defined(CONFIG_ARCH_QSD8X50)
186 .start = 104,
187 #else
188 .start = 107,
189 #endif
190 #if defined(CONFIG_ARCH_MSM7225) || defined(CONFIG_ARCH_MSM7227)
191 .end = 132,
192 #elif defined(CONFIG_ARCH_MSM7X30)
193 .end = 133,
194 #else
195 .end = 121,
196 #endif
197 .configure = msm_gpio_configure,
198 .get_irq_num = msm_gpio_get_irq_num,
199 .read = msm_gpio_read,
200 .write = msm_gpio_write,
201 .read_detect_status = msm_gpio_read_detect_status,
202 .clear_detect_status = msm_gpio_clear_detect_status
203 }
204 },
205 #if defined(CONFIG_ARCH_MSM_SCORPION)
206 {
207 .regs = {
208 .out = GPIO_OUT_6,
209 .in = GPIO_IN_6,
210 .int_status = GPIO_INT_STATUS_6,
211 .int_clear = GPIO_INT_CLEAR_6,
212 .int_en = GPIO_INT_EN_6,
213 .int_edge = GPIO_INT_EDGE_6,
214 .int_pos = GPIO_INT_POS_6,
215 .oe = GPIO_OE_6,
216 },
217 .chip = {
218 #if defined(CONFIG_ARCH_MSM7X30)
219 .start = 134,
220 .end = 150,
221 #else
222 .start = 122,
223 .end = 152,
224 #endif
225 .configure = msm_gpio_configure,
226 .get_irq_num = msm_gpio_get_irq_num,
227 .read = msm_gpio_read,
228 .write = msm_gpio_write,
229 .read_detect_status = msm_gpio_read_detect_status,
230 .clear_detect_status = msm_gpio_clear_detect_status
231 }
232 },
233 {
234 .regs = {
235 .out = GPIO_OUT_7,
236 .in = GPIO_IN_7,
237 .int_status = GPIO_INT_STATUS_7,
238 .int_clear = GPIO_INT_CLEAR_7,
239 .int_en = GPIO_INT_EN_7,
240 .int_edge = GPIO_INT_EDGE_7,
241 .int_pos = GPIO_INT_POS_7,
242 .oe = GPIO_OE_7,
243 },
244 .chip = {
245 #if defined(CONFIG_ARCH_MSM7X30)
246 .start = 151,
247 .end = 181,
248 #else
249 .start = 153,
250 .end = 164,
251 #endif
252 .configure = msm_gpio_configure,
253 .get_irq_num = msm_gpio_get_irq_num,
254 .read = msm_gpio_read,
255 .write = msm_gpio_write,
256 .read_detect_status = msm_gpio_read_detect_status,
257 .clear_detect_status = msm_gpio_clear_detect_status
258 }
259 },
260 #endif
261 };
262
263 static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
264 {
265 int loop_limit = 100;
266 unsigned pol, val, val2, intstat;
267 do {
268 val = readl(msm_chip->regs.in);
269 pol = readl(msm_chip->regs.int_pos);
270 pol = (pol & ~msm_chip->both_edge_detect) | (~val & msm_chip->both_edge_detect);
271 writel(pol, msm_chip->regs.int_pos);
272 intstat = readl(msm_chip->regs.int_status);
273 val2 = readl(msm_chip->regs.in);
274 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
275 return;
276 } while (loop_limit-- > 0);
277 printk(KERN_ERR "msm_gpio_update_both_edge_detect, failed to reach stable state %x != %x\n", val, val2);
278 }
279
280 static int msm_gpio_write(struct gpio_chip *chip, unsigned n, unsigned on)
281 {
282 struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
283 unsigned b = 1U << (n - chip->start);
284 unsigned v;
285
286 v = readl(msm_chip->regs.out);
287 if (on) {
288 writel(v | b, msm_chip->regs.out);
289 } else {
290 writel(v & (~b), msm_chip->regs.out);
291 }
292 return 0;
293 }
294
295 static int msm_gpio_read(struct gpio_chip *chip, unsigned n)
296 {
297 struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
298 unsigned b = 1U << (n - chip->start);
299
300 return (readl(msm_chip->regs.in) & b) ? 1 : 0;
301 }
302
303 static int msm_gpio_read_detect_status(struct gpio_chip *chip, unsigned int gpio)
304 {
305 struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
306 unsigned b = 1U << (gpio - chip->start);
307 unsigned v;
308
309 v = readl(msm_chip->regs.int_status);
310 #if MSM_GPIO_BROKEN_INT_CLEAR
311 v |= msm_chip->int_status_copy;
312 #endif
313 return (v & b) ? 1 : 0;
314 }
315
316 static int msm_gpio_clear_detect_status(struct gpio_chip *chip, unsigned int gpio)
317 {
318 struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
319 unsigned b = 1U << (gpio - chip->start);
320
321 #if MSM_GPIO_BROKEN_INT_CLEAR
322 /* Save interrupts that already triggered before we loose them. */
323 /* Any interrupt that triggers between the read of int_status */
324 /* and the write to int_clear will still be lost though. */
325 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
326 msm_chip->int_status_copy &= ~b;
327 #endif
328 writel(b, msm_chip->regs.int_clear);
329 msm_gpio_update_both_edge_detect(msm_chip);
330 return 0;
331 }
332
333 int msm_gpio_configure(struct gpio_chip *chip, unsigned int gpio, unsigned long flags)
334 {
335 struct msm_gpio_chip *msm_chip = container_of(chip, struct msm_gpio_chip, chip);
336 unsigned b = 1U << (gpio - chip->start);
337 unsigned v;
338
339 #ifdef CONFIG_HTC_SLEEP_MODE_GPIO_DUMP
340 unsigned int gpio_pull = 0, gpio_direction = 0, gpio_owner;
341
342 gpio_owner = readl(htc_smem_gpio_cfg(gpio, 0));
343 gpio_owner = gpio_owner & (0x1 << GPIO_CFG_OWNER);
344
345 if (flags & (GPIOF_INPUT | GPIOF_DRIVE_OUTPUT)) {
346 if (flags & GPIOF_INPUT)
347 gpio_direction = 0;
348 else if (flags & GPIOF_DRIVE_OUTPUT)
349 gpio_direction = 1;
350
351 if (flags & GPIOF_OUTPUT_LOW)
352 gpio_pull = 1;
353 else if (flags & GPIOF_OUTPUT_HIGH)
354 gpio_pull = 3;
355
356 v = (0 << GPIO_CFG_INVALID) | gpio_owner |
357 (0 << GPIO_CFG_DRVSTR) | (gpio_pull << GPIO_CFG_PULL) |
358 (gpio_direction << GPIO_CFG_DIR) |
359 (1 << GPIO_CFG_RMT) | 0;
360
361 writel(v, htc_smem_gpio_cfg(gpio, 0));
362 }
363 #endif
364
365 if (flags & (GPIOF_OUTPUT_LOW | GPIOF_OUTPUT_HIGH))
366 msm_gpio_write(chip, gpio, flags & GPIOF_OUTPUT_HIGH);
367
368 if (flags & (GPIOF_INPUT | GPIOF_DRIVE_OUTPUT)) {
369 v = readl(msm_chip->regs.oe);
370 if (flags & GPIOF_DRIVE_OUTPUT) {
371 writel(v | b, msm_chip->regs.oe);
372 } else {
373 writel(v & (~b), msm_chip->regs.oe);
374 }
375 }
376
377 if (flags & (IRQF_TRIGGER_MASK | GPIOF_IRQF_TRIGGER_NONE)) {
378 v = readl(msm_chip->regs.int_edge);
379 if (flags & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) {
380 writel(v | b, msm_chip->regs.int_edge);
381 irq_desc[MSM_GPIO_TO_INT(gpio)].handle_irq = handle_edge_irq;
382 } else {
383 writel(v & (~b), msm_chip->regs.int_edge);
384 irq_desc[MSM_GPIO_TO_INT(gpio)].handle_irq = handle_level_irq;
385 }
386 if ((flags & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) == (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)) {
387 msm_chip->both_edge_detect |= b;
388 msm_gpio_update_both_edge_detect(msm_chip);
389 } else {
390 msm_chip->both_edge_detect &= ~b;
391 v = readl(msm_chip->regs.int_pos);
392 if (flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH)) {
393 writel(v | b, msm_chip->regs.int_pos);
394 } else {
395 writel(v & (~b), msm_chip->regs.int_pos);
396 }
397 }
398 }
399
400 /* used by msm_gpio_irq_mask and msm_gpio_irq_unmask */
401 if (flags & (MSM_GPIOF_ENABLE_INTERRUPT | MSM_GPIOF_DISABLE_INTERRUPT)) {
402 v = readl(msm_chip->regs.int_edge);
403 /* level triggered interrupts are also latched */
404 if (!(v & b))
405 msm_gpio_clear_detect_status(chip, gpio);
406 if (flags & MSM_GPIOF_ENABLE_INTERRUPT) {
407 msm_chip->int_enable[0] |= b;
408 } else {
409 msm_chip->int_enable[0] &= ~b;
410 }
411 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
412 }
413
414 if (flags & (MSM_GPIOF_ENABLE_WAKE | MSM_GPIOF_DISABLE_WAKE)) {
415 if (flags & MSM_GPIOF_ENABLE_WAKE)
416 msm_chip->int_enable[1] |= b;
417 else
418 msm_chip->int_enable[1] &= ~b;
419 }
420
421 return 0;
422 }
423
424 static int msm_gpio_get_irq_num(struct gpio_chip *chip, unsigned int gpio, unsigned int *irqp, unsigned long *irqnumflagsp)
425 {
426 *irqp = MSM_GPIO_TO_INT(gpio);
427 if (irqnumflagsp)
428 *irqnumflagsp = 0;
429 return 0;
430 }
431
432
433 static void msm_gpio_irq_ack(unsigned int irq)
434 {
435 unsigned long irq_flags;
436 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
437 spin_lock_irqsave(&msm_chip->chip.lock, irq_flags);
438 msm_gpio_clear_detect_status(&msm_chip->chip, irq - FIRST_GPIO_IRQ);
439 spin_unlock_irqrestore(&msm_chip->chip.lock, irq_flags);
440 }
441
442 static void msm_gpio_irq_mask(unsigned int irq)
443 {
444 unsigned long irq_flags;
445 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
446 spin_lock_irqsave(&msm_chip->chip.lock, irq_flags);
447 msm_gpio_configure(&msm_chip->chip, irq - FIRST_GPIO_IRQ, MSM_GPIOF_DISABLE_INTERRUPT);
448 spin_unlock_irqrestore(&msm_chip->chip.lock, irq_flags);
449 }
450
451 static void msm_gpio_irq_unmask(unsigned int irq)
452 {
453 unsigned long irq_flags;
454 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
455 spin_lock_irqsave(&msm_chip->chip.lock, irq_flags);
456 msm_gpio_configure(&msm_chip->chip, irq - FIRST_GPIO_IRQ, MSM_GPIOF_ENABLE_INTERRUPT);
457 spin_unlock_irqrestore(&msm_chip->chip.lock, irq_flags);
458 }
459
460 static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
461 {
462 int ret;
463 unsigned long irq_flags;
464 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
465 spin_lock_irqsave(&msm_chip->chip.lock, irq_flags);
466 ret = msm_gpio_configure(&msm_chip->chip, irq - FIRST_GPIO_IRQ, on ? MSM_GPIOF_ENABLE_WAKE : MSM_GPIOF_DISABLE_WAKE);
467 spin_unlock_irqrestore(&msm_chip->chip.lock, irq_flags);
468 return ret;
469 }
470
471
472 static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
473 {
474 int ret;
475 unsigned long irq_flags;
476 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
477 spin_lock_irqsave(&msm_chip->chip.lock, irq_flags);
478 ret = msm_gpio_configure(&msm_chip->chip, irq - FIRST_GPIO_IRQ, flow_type);
479 spin_unlock_irqrestore(&msm_chip->chip.lock, irq_flags);
480 return ret;
481 }
482
483 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
484 {
485 int i, j, m;
486 unsigned v;
487
488 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
489 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
490 v = readl(msm_chip->regs.int_status);
491 v &= msm_chip->int_enable[0];
492 while (v) {
493 m = v & -v;
494 j = fls(m) - 1;
495 /* printk("msm_gpio_irq_handler %08x %08x bit %d gpio %d irq %d\n", v, m, j, msm_chip->chip.start + j, FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
496 v &= ~m;
497 generic_handle_irq(FIRST_GPIO_IRQ + msm_chip->chip.start + j);
498 }
499 }
500 desc->chip->ack(irq);
501 }
502
503 static struct irq_chip msm_gpio_irq_chip = {
504 .name = "msmgpio",
505 .ack = msm_gpio_irq_ack,
506 .mask = msm_gpio_irq_mask,
507 .unmask = msm_gpio_irq_unmask,
508 .set_wake = msm_gpio_irq_set_wake,
509 .set_type = msm_gpio_irq_set_type,
510 };
511
512 #define NUM_GPIO_SMEM_BANKS 6
513 #define GPIO_SMEM_NUM_GROUPS 2
514 #define GPIO_SMEM_MAX_PC_INTERRUPTS 8
515 struct tramp_gpio_smem
516 {
517 uint16_t num_fired[GPIO_SMEM_NUM_GROUPS];
518 uint16_t fired[GPIO_SMEM_NUM_GROUPS][GPIO_SMEM_MAX_PC_INTERRUPTS];
519 uint32_t enabled[NUM_GPIO_SMEM_BANKS];
520 uint32_t detection[NUM_GPIO_SMEM_BANKS];
521 uint32_t polarity[NUM_GPIO_SMEM_BANKS];
522 };
523
524 static void msm_gpio_sleep_int(unsigned long arg)
525 {
526 int i, j;
527 struct tramp_gpio_smem *smem_gpio;
528
529 BUILD_BUG_ON(NR_GPIO_IRQS > NUM_GPIO_SMEM_BANKS * 32);
530
531 smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio));
532 if (smem_gpio == NULL)
533 return;
534
535 local_irq_disable();
536 for(i = 0; i < GPIO_SMEM_NUM_GROUPS; i++) {
537 int count = smem_gpio->num_fired[i];
538 for(j = 0; j < count; j++) {
539 /* TODO: Check mask */
540 generic_handle_irq(MSM_GPIO_TO_INT(smem_gpio->fired[i][j]));
541 }
542 }
543 local_irq_enable();
544 }
545
546 static DECLARE_TASKLET(msm_gpio_sleep_int_tasklet, msm_gpio_sleep_int, 0);
547
548 #ifdef CONFIG_HTC_SLEEP_MODE_GPIO_DUMP
549 unsigned int htc_smem_gpio_cfg(unsigned int num, unsigned int mode)
550 {
551 return (unsigned int)(HTC_GPIO_CFG_ADDR(mode) + (num * 0x04));
552 }
553 #endif
554
555 void msm_gpio_enter_sleep(int from_idle)
556 {
557 int i;
558 struct tramp_gpio_smem *smem_gpio;
559
560 smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio));
561
562 if (smem_gpio) {
563 for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) {
564 smem_gpio->enabled[i] = 0;
565 smem_gpio->detection[i] = 0;
566 smem_gpio->polarity[i] = 0;
567 }
568 }
569
570 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
571 writel(msm_gpio_chips[i].int_enable[!from_idle], msm_gpio_chips[i].regs.int_en);
572 if ((msm_gpio_debug_mask & GPIO_DEBUG_SLEEP) && !from_idle)
573 printk("gpio[%3d,%3d]: int_enable=0x%08x int_edge=0x%8p int_pos=0x%8p\n",
574 msm_gpio_chips[i].chip.start,
575 msm_gpio_chips[i].chip.end,
576 msm_gpio_chips[i].int_enable[!from_idle],
577 msm_gpio_chips[i].regs.int_edge,
578 msm_gpio_chips[i].regs.int_pos);
579 if (smem_gpio) {
580 uint32_t tmp;
581 int start, index, shiftl, shiftr;
582 start = msm_gpio_chips[i].chip.start;
583 index = start / 32;
584 shiftl = start % 32;
585 shiftr = 32 - shiftl;
586 tmp = msm_gpio_chips[i].int_enable[!from_idle];
587 smem_gpio->enabled[index] |= tmp << shiftl;
588 smem_gpio->enabled[index+1] |= tmp >> shiftr;
589 smem_gpio->detection[index] |= readl(msm_gpio_chips[i].regs.int_edge) << shiftl;
590 smem_gpio->detection[index+1] |= readl(msm_gpio_chips[i].regs.int_edge) >> shiftr;
591 smem_gpio->polarity[index] |= readl(msm_gpio_chips[i].regs.int_pos) << shiftl;
592 smem_gpio->polarity[index+1] |= readl(msm_gpio_chips[i].regs.int_pos) >> shiftr;
593 }
594 }
595
596 if (smem_gpio) {
597 if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP)
598 for (i = 0; i < ARRAY_SIZE(smem_gpio->enabled); i++) {
599 printk("msm_gpio_enter_sleep gpio %d-%d: enable"
600 " %08x, edge %08x, polarity %08x\n",
601 i * 32, i * 32 + 31,
602 smem_gpio->enabled[i],
603 smem_gpio->detection[i],
604 smem_gpio->polarity[i]);
605 }
606 for(i = 0; i < GPIO_SMEM_NUM_GROUPS; i++)
607 smem_gpio->num_fired[i] = 0;
608 }
609 }
610
611 void msm_gpio_exit_sleep(void)
612 {
613 int i;
614 struct tramp_gpio_smem *smem_gpio;
615
616 smem_gpio = smem_alloc(SMEM_GPIO_INT, sizeof(*smem_gpio));
617
618 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
619 writel(msm_gpio_chips[i].int_enable[0], msm_gpio_chips[i].regs.int_en);
620 }
621
622 if (smem_gpio && (smem_gpio->num_fired[0] || smem_gpio->num_fired[1])) {
623 if (msm_gpio_debug_mask & GPIO_DEBUG_SLEEP)
624 printk(KERN_INFO "gpio: fired %x %x\n",
625 smem_gpio->num_fired[0], smem_gpio->num_fired[1]);
626 tasklet_schedule(&msm_gpio_sleep_int_tasklet);
627 }
628 }
629
630 static int __init msm_init_gpio(void)
631 {
632 int i, j = 0;
633
634 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
635 if (i - FIRST_GPIO_IRQ > msm_gpio_chips[j].chip.end)
636 j++;
637 set_irq_chip_data(i, &msm_gpio_chips[j]);
638 set_irq_chip(i, &msm_gpio_irq_chip);
639 set_irq_handler(i, handle_edge_irq);
640 set_irq_flags(i, IRQF_VALID);
641 }
642
643 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
644 writel(0, msm_gpio_chips[i].regs.int_en);
645 register_gpio_chip(&msm_gpio_chips[i].chip);
646 }
647
648 set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
649 set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
650 set_irq_wake(INT_GPIO_GROUP1, 1);
651 set_irq_wake(INT_GPIO_GROUP2, 2);
652 return 0;
653 }
654
655 int gpio_configure(unsigned int gpio, unsigned long flags)
656 {
657 unsigned long irq_flags;
658 struct msm_gpio_chip *msm_chip = get_irq_chip_data((gpio + FIRST_GPIO_IRQ));
659 spin_lock_irqsave(&msm_chip->chip.lock, irq_flags);
660 msm_gpio_configure(&msm_chip->chip, gpio, flags);
661 spin_unlock_irqrestore(&msm_chip->chip.lock, irq_flags);
662 return 0;
663 }
664 EXPORT_SYMBOL(gpio_configure);
665
666 void config_gpio_table(uint32_t *table, int len)
667 {
668 int n;
669 unsigned id;
670 for (n = 0; n < len; n++) {
671 id = table[n];
672 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &id, 0);
673 }
674 }
675 EXPORT_SYMBOL(config_gpio_table);
676
677 int gpio_tlmm_config(unsigned config, unsigned disable)
678 {
679 return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable);
680 }
681 EXPORT_SYMBOL(gpio_tlmm_config);
682
683 postcore_initcall(msm_init_gpio);
kernels