include/arch.h

   1 /*
   2  * Copyright (c) 2007-2019 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  17  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  */
  22
  23 #ifndef __ARCH_H
  24 #define __ARCH_H
  25
  26 /*
  27  * PSW and PSW handling
  28  */
  29 struct psw {
  30         u8 _zero0:1,
  31            r:1,                 /* PER Mask (R)                 */
  32            _zero1:3,
  33            t:1,                 /* DAT Mode (T)                 */
  34            io:1,                /* I/O Mask (IO)                */
  35            ex:1;                /* External Mask (EX)           */
  36
  37         u8 key:4,               /* Key                          */
  38            fmt:1,               /* 1 on 390, 0 on z             */
  39            m:1,                 /* Machine-Check Mask (M)       */
  40            w:1,                 /* Wait State (W)               */
  41            p:1;                 /* Problem State (P)            */
  42
  43         u8 as:2,                /* Address-Space Control (AS)   */
  44            cc:2,                /* Condition Code (CC)          */
  45            prog_mask:4;         /* Program Mask                 */
  46
  47         u8 _zero2:7,
  48            ea:1;                /* Extended Addressing (EA)     */
  49
  50         u32 ba:1,               /* Basic Addressing (BA)        */
  51             ptr31:31;
  52
  53         u64 ptr;
  54 } __attribute__((packed,aligned(8)));
  55
  56 static inline void lpswe(struct psw *psw)
  57 {
  58         asm volatile(
  59                 "       lpswe   %0\n"
  60         : /* output */
  61         : /* input */
  62           "m" (*psw)
  63         );
  64 }
  65
  66 /*
  67  * Stop the cpu
  68  *
  69  * NOTE: We don't care about not clobbering registers as when this
  70  * code executes, the CPU will be stopped.
  71  *
  72  * TODO: mark this with a no-return attribute
  73  */
  74 static inline void sigp_stop(void)
  75 {
  76         asm volatile(
  77                 "SR     %r1, %r1        # not used, but should be zero\n"
  78                 "SR     %r3, %r3        # CPU Address\n"
  79                 "SIGP   %r1, %r3, 0x05  # order 0x05 = stop\n"
  80         );
  81
  82         /*
  83          * Just in case SIGP fails
  84          */
  85         for (;;)
  86                 ;
  87 }
  88
  89 /*
  90  * Control Register handling
  91  */
  92 #define set_cr(cr, val)                                         \
  93         do {                                                    \
  94                 u64 lval = (val);                               \
  95                 asm volatile(                                   \
  96                         "lctlg  %1,%1,%0\n"                     \
  97                 : /* output */                                  \
  98                 : /* input */                                   \
  99                   "m" (lval),                                   \
 100                   "i" (cr)                                      \
 101                 );                                              \
 102         } while(0)
 103
 104 #define get_cr(cr)                                              \
 105         ({                                                      \
 106                 u64 reg;                                        \
 107                                                                 \
 108                 asm volatile(                                   \
 109                         "stctg  %1,%1,%0\n"                     \
 110                 : /* output */                                  \
 111                   "=m" (reg)                                    \
 112                 : /* input */                                   \
 113                   "i" (cr)                                      \
 114                 );                                              \
 115                 reg;                                            \
 116          })
 117
 118 /*
 119  * Machine Check Interrupt related structs & locations
 120  */
 121 struct mch_int_code {
 122         u8 sd:1,                /* System Damage */
 123            pd:1,                /* Instruction-processing damage */
 124            sr:1,                /* System recovery */
 125            _pad0:1,
 126            cd:1,                /* Timing-facility damage */
 127            ed:1,                /* External damage */
 128            _pad1:1,
 129            dg:1;                /* Degradation */
 130         u8 w:1,                 /* Warning */
 131            cp:1,                /* Channel report pending */
 132            sp:1,                /* Service-processor damage */
 133            ck:1,                /* Channel-subsystem damage */
 134            _pad2:2,
 135            b:1,                 /* Backed up */
 136            _pad3:1;
 137         u8 se:1,                /* Storage error uncorrected */
 138            sc:1,                /* Storage error corrected */
 139            ke:1,                /* Storage-key error uncorrected */
 140            ds:1,                /* Storage degradation */
 141            wp:1,                /* PSW-MWP validity */
 142            ms:1,                /* PSW mask and key validity */
 143            pm:1,                /* PSW program-mask and condition-code validity */
 144            ia:1;                /* PSW-instruction-address validity */
 145         u8 fa:1,                /* Failing-storage-address validity */
 146            _pad4:1,
 147            ec:1,                /* External-damage-code */
 148            fp:1,                /* Floating-point-register validity */
 149            gr:1,                /* General-register validity */
 150            cr:1,                /* Control-register validity */
 151            _pad5:1,
 152            st:1;                /* Storage logical validity */
 153         u8 ie:1,                /* Indirect storage error */
 154            ar:1,                /* Access-register validity */
 155            da:1,                /* Delayed-access exception */
 156            _pad6:5;
 157         u8 _pad7:2,
 158            pr:1,                /* TOD-programable-register validity */
 159            fc:1,                /* Floating-point-control-register validity */
 160            ap:1,                /* Ancilary report */
 161            _pad8:1,
 162            ct:1,                /* CPU-timer validity */
 163            cc:1;                /* Clock-comparator validity */
 164         u8 _pad9;
 165         u8 _pad10;
 166 } __attribute__((packed));
 167
 168 #define MCH_INT_OLD_PSW ((void*) 0x160)
 169 #define MCH_INT_NEW_PSW ((void*) 0x1e0)
 170 #define MCH_INT_CODE    ((struct mch_int_code*) 0xe8)
 171
 172 #endif