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Cleanup
[inav.git] / dev / svd / STM32F411.svd
blob585602d208c139722305ee295970e7c58ba68e50
1 <?xml version="1.0" encoding="utf-8" standalone="no"?>
2 <device schemaVersion="1.1"
3 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
4 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
5 <name>STM32F411</name>
6 <version>1.1</version>
7 <description>STM32F411</description>
8 <!-- details about the cpu embedded in the device -->
9 <cpu>
10 <name>CM4</name>
11 <revision>r1p0</revision>
12 <endian>little</endian>
13 <mpuPresent>false</mpuPresent>
14 <fpuPresent>false</fpuPresent>
15 <nvicPrioBits>3</nvicPrioBits>
16 <vendorSystickConfig>false</vendorSystickConfig>
17 </cpu>
18 <!--Bus Interface Properties-->
19 <!--Cortex-M4 is byte addressable-->
20 <addressUnitBits>8</addressUnitBits>
21 <!--the maximum data bit width accessible within a single transfer-->
22 <width>32</width>
23 <!--Register Default Properties-->
24 <size>0x20</size>
25 <resetValue>0x0</resetValue>
26 <resetMask>0xFFFFFFFF</resetMask>
27 <peripherals>
28 <peripheral>
29 <name>ADC_Common</name>
30 <description>ADC common registers</description>
31 <groupName>ADC</groupName>
32 <baseAddress>0x40012300</baseAddress>
33 <addressBlock>
34 <offset>0x0</offset>
35 <size>0x9</size>
36 <usage>registers</usage>
37 </addressBlock>
38 <interrupt>
39 <name>FPU</name>
40 <description>FPU interrupt</description>
41 <value>81</value>
42 </interrupt>
43 <registers>
44 <register>
45 <name>CSR</name>
46 <displayName>CSR</displayName>
47 <description>ADC Common status register</description>
48 <addressOffset>0x0</addressOffset>
49 <size>0x20</size>
50 <access>read-only</access>
51 <resetValue>0x00000000</resetValue>
52 <fields>
53 <field>
54 <name>OVR3</name>
55 <description>Overrun flag of ADC3</description>
56 <bitOffset>21</bitOffset>
57 <bitWidth>1</bitWidth>
58 </field>
59 <field>
60 <name>STRT3</name>
61 <description>Regular channel Start flag of ADC
62 3</description>
63 <bitOffset>20</bitOffset>
64 <bitWidth>1</bitWidth>
65 </field>
66 <field>
67 <name>JSTRT3</name>
68 <description>Injected channel Start flag of ADC
69 3</description>
70 <bitOffset>19</bitOffset>
71 <bitWidth>1</bitWidth>
72 </field>
73 <field>
74 <name>JEOC3</name>
75 <description>Injected channel end of conversion of
76 ADC 3</description>
77 <bitOffset>18</bitOffset>
78 <bitWidth>1</bitWidth>
79 </field>
80 <field>
81 <name>EOC3</name>
82 <description>End of conversion of ADC 3</description>
83 <bitOffset>17</bitOffset>
84 <bitWidth>1</bitWidth>
85 </field>
86 <field>
87 <name>AWD3</name>
88 <description>Analog watchdog flag of ADC
89 3</description>
90 <bitOffset>16</bitOffset>
91 <bitWidth>1</bitWidth>
92 </field>
93 <field>
94 <name>OVR2</name>
95 <description>Overrun flag of ADC 2</description>
96 <bitOffset>13</bitOffset>
97 <bitWidth>1</bitWidth>
98 </field>
99 <field>
100 <name>STRT2</name>
101 <description>Regular channel Start flag of ADC
102 2</description>
103 <bitOffset>12</bitOffset>
104 <bitWidth>1</bitWidth>
105 </field>
106 <field>
107 <name>JSTRT2</name>
108 <description>Injected channel Start flag of ADC
109 2</description>
110 <bitOffset>11</bitOffset>
111 <bitWidth>1</bitWidth>
112 </field>
113 <field>
114 <name>JEOC2</name>
115 <description>Injected channel end of conversion of
116 ADC 2</description>
117 <bitOffset>10</bitOffset>
118 <bitWidth>1</bitWidth>
119 </field>
120 <field>
121 <name>EOC2</name>
122 <description>End of conversion of ADC 2</description>
123 <bitOffset>9</bitOffset>
124 <bitWidth>1</bitWidth>
125 </field>
126 <field>
127 <name>AWD2</name>
128 <description>Analog watchdog flag of ADC
129 2</description>
130 <bitOffset>8</bitOffset>
131 <bitWidth>1</bitWidth>
132 </field>
133 <field>
134 <name>OVR1</name>
135 <description>Overrun flag of ADC 1</description>
136 <bitOffset>5</bitOffset>
137 <bitWidth>1</bitWidth>
138 </field>
139 <field>
140 <name>STRT1</name>
141 <description>Regular channel Start flag of ADC
142 1</description>
143 <bitOffset>4</bitOffset>
144 <bitWidth>1</bitWidth>
145 </field>
146 <field>
147 <name>JSTRT1</name>
148 <description>Injected channel Start flag of ADC
149 1</description>
150 <bitOffset>3</bitOffset>
151 <bitWidth>1</bitWidth>
152 </field>
153 <field>
154 <name>JEOC1</name>
155 <description>Injected channel end of conversion of
156 ADC 1</description>
157 <bitOffset>2</bitOffset>
158 <bitWidth>1</bitWidth>
159 </field>
160 <field>
161 <name>EOC1</name>
162 <description>End of conversion of ADC 1</description>
163 <bitOffset>1</bitOffset>
164 <bitWidth>1</bitWidth>
165 </field>
166 <field>
167 <name>AWD1</name>
168 <description>Analog watchdog flag of ADC
169 1</description>
170 <bitOffset>0</bitOffset>
171 <bitWidth>1</bitWidth>
172 </field>
173 </fields>
174 </register>
175 <register>
176 <name>CCR</name>
177 <displayName>CCR</displayName>
178 <description>ADC common control register</description>
179 <addressOffset>0x4</addressOffset>
180 <size>0x20</size>
181 <access>read-write</access>
182 <resetValue>0x00000000</resetValue>
183 <fields>
184 <field>
185 <name>TSVREFE</name>
186 <description>Temperature sensor and VREFINT
187 enable</description>
188 <bitOffset>23</bitOffset>
189 <bitWidth>1</bitWidth>
190 </field>
191 <field>
192 <name>VBATE</name>
193 <description>VBAT enable</description>
194 <bitOffset>22</bitOffset>
195 <bitWidth>1</bitWidth>
196 </field>
197 <field>
198 <name>ADCPRE</name>
199 <description>ADC prescaler</description>
200 <bitOffset>16</bitOffset>
201 <bitWidth>2</bitWidth>
202 </field>
203 <field>
204 <name>DMA</name>
205 <description>Direct memory access mode for multi ADC
206 mode</description>
207 <bitOffset>14</bitOffset>
208 <bitWidth>2</bitWidth>
209 </field>
210 <field>
211 <name>DDS</name>
212 <description>DMA disable selection for multi-ADC
213 mode</description>
214 <bitOffset>13</bitOffset>
215 <bitWidth>1</bitWidth>
216 </field>
217 <field>
218 <name>DELAY</name>
219 <description>Delay between 2 sampling
220 phases</description>
221 <bitOffset>8</bitOffset>
222 <bitWidth>4</bitWidth>
223 </field>
224 </fields>
225 </register>
226 </registers>
227 </peripheral>
228 <peripheral>
229 <name>ADC1</name>
230 <description>Analog-to-digital converter</description>
231 <groupName>ADC</groupName>
232 <baseAddress>0x40012000</baseAddress>
233 <addressBlock>
234 <offset>0x0</offset>
235 <size>0x51</size>
236 <usage>registers</usage>
237 </addressBlock>
238 <interrupt>
239 <name>ADC</name>
240 <description>ADC1 global interrupt</description>
241 <value>18</value>
242 </interrupt>
243 <registers>
244 <register>
245 <name>SR</name>
246 <displayName>SR</displayName>
247 <description>status register</description>
248 <addressOffset>0x0</addressOffset>
249 <size>0x20</size>
250 <access>read-write</access>
251 <resetValue>0x00000000</resetValue>
252 <fields>
253 <field>
254 <name>OVR</name>
255 <description>Overrun</description>
256 <bitOffset>5</bitOffset>
257 <bitWidth>1</bitWidth>
258 </field>
259 <field>
260 <name>STRT</name>
261 <description>Regular channel start flag</description>
262 <bitOffset>4</bitOffset>
263 <bitWidth>1</bitWidth>
264 </field>
265 <field>
266 <name>JSTRT</name>
267 <description>Injected channel start
268 flag</description>
269 <bitOffset>3</bitOffset>
270 <bitWidth>1</bitWidth>
271 </field>
272 <field>
273 <name>JEOC</name>
274 <description>Injected channel end of
275 conversion</description>
276 <bitOffset>2</bitOffset>
277 <bitWidth>1</bitWidth>
278 </field>
279 <field>
280 <name>EOC</name>
281 <description>Regular channel end of
282 conversion</description>
283 <bitOffset>1</bitOffset>
284 <bitWidth>1</bitWidth>
285 </field>
286 <field>
287 <name>AWD</name>
288 <description>Analog watchdog flag</description>
289 <bitOffset>0</bitOffset>
290 <bitWidth>1</bitWidth>
291 </field>
292 </fields>
293 </register>
294 <register>
295 <name>CR1</name>
296 <displayName>CR1</displayName>
297 <description>control register 1</description>
298 <addressOffset>0x4</addressOffset>
299 <size>0x20</size>
300 <access>read-write</access>
301 <resetValue>0x00000000</resetValue>
302 <fields>
303 <field>
304 <name>OVRIE</name>
305 <description>Overrun interrupt enable</description>
306 <bitOffset>26</bitOffset>
307 <bitWidth>1</bitWidth>
308 </field>
309 <field>
310 <name>RES</name>
311 <description>Resolution</description>
312 <bitOffset>24</bitOffset>
313 <bitWidth>2</bitWidth>
314 </field>
315 <field>
316 <name>AWDEN</name>
317 <description>Analog watchdog enable on regular
318 channels</description>
319 <bitOffset>23</bitOffset>
320 <bitWidth>1</bitWidth>
321 </field>
322 <field>
323 <name>JAWDEN</name>
324 <description>Analog watchdog enable on injected
325 channels</description>
326 <bitOffset>22</bitOffset>
327 <bitWidth>1</bitWidth>
328 </field>
329 <field>
330 <name>DISCNUM</name>
331 <description>Discontinuous mode channel
332 count</description>
333 <bitOffset>13</bitOffset>
334 <bitWidth>3</bitWidth>
335 </field>
336 <field>
337 <name>JDISCEN</name>
338 <description>Discontinuous mode on injected
339 channels</description>
340 <bitOffset>12</bitOffset>
341 <bitWidth>1</bitWidth>
342 </field>
343 <field>
344 <name>DISCEN</name>
345 <description>Discontinuous mode on regular
346 channels</description>
347 <bitOffset>11</bitOffset>
348 <bitWidth>1</bitWidth>
349 </field>
350 <field>
351 <name>JAUTO</name>
352 <description>Automatic injected group
353 conversion</description>
354 <bitOffset>10</bitOffset>
355 <bitWidth>1</bitWidth>
356 </field>
357 <field>
358 <name>AWDSGL</name>
359 <description>Enable the watchdog on a single channel
360 in scan mode</description>
361 <bitOffset>9</bitOffset>
362 <bitWidth>1</bitWidth>
363 </field>
364 <field>
365 <name>SCAN</name>
366 <description>Scan mode</description>
367 <bitOffset>8</bitOffset>
368 <bitWidth>1</bitWidth>
369 </field>
370 <field>
371 <name>JEOCIE</name>
372 <description>Interrupt enable for injected
373 channels</description>
374 <bitOffset>7</bitOffset>
375 <bitWidth>1</bitWidth>
376 </field>
377 <field>
378 <name>AWDIE</name>
379 <description>Analog watchdog interrupt
380 enable</description>
381 <bitOffset>6</bitOffset>
382 <bitWidth>1</bitWidth>
383 </field>
384 <field>
385 <name>EOCIE</name>
386 <description>Interrupt enable for EOC</description>
387 <bitOffset>5</bitOffset>
388 <bitWidth>1</bitWidth>
389 </field>
390 <field>
391 <name>AWDCH</name>
392 <description>Analog watchdog channel select
393 bits</description>
394 <bitOffset>0</bitOffset>
395 <bitWidth>5</bitWidth>
396 </field>
397 </fields>
398 </register>
399 <register>
400 <name>CR2</name>
401 <displayName>CR2</displayName>
402 <description>control register 2</description>
403 <addressOffset>0x8</addressOffset>
404 <size>0x20</size>
405 <access>read-write</access>
406 <resetValue>0x00000000</resetValue>
407 <fields>
408 <field>
409 <name>SWSTART</name>
410 <description>Start conversion of regular
411 channels</description>
412 <bitOffset>30</bitOffset>
413 <bitWidth>1</bitWidth>
414 </field>
415 <field>
416 <name>EXTEN</name>
417 <description>External trigger enable for regular
418 channels</description>
419 <bitOffset>28</bitOffset>
420 <bitWidth>2</bitWidth>
421 </field>
422 <field>
423 <name>EXTSEL</name>
424 <description>External event select for regular
425 group</description>
426 <bitOffset>24</bitOffset>
427 <bitWidth>4</bitWidth>
428 </field>
429 <field>
430 <name>JSWSTART</name>
431 <description>Start conversion of injected
432 channels</description>
433 <bitOffset>22</bitOffset>
434 <bitWidth>1</bitWidth>
435 </field>
436 <field>
437 <name>JEXTEN</name>
438 <description>External trigger enable for injected
439 channels</description>
440 <bitOffset>20</bitOffset>
441 <bitWidth>2</bitWidth>
442 </field>
443 <field>
444 <name>JEXTSEL</name>
445 <description>External event select for injected
446 group</description>
447 <bitOffset>16</bitOffset>
448 <bitWidth>4</bitWidth>
449 </field>
450 <field>
451 <name>ALIGN</name>
452 <description>Data alignment</description>
453 <bitOffset>11</bitOffset>
454 <bitWidth>1</bitWidth>
455 </field>
456 <field>
457 <name>EOCS</name>
458 <description>End of conversion
459 selection</description>
460 <bitOffset>10</bitOffset>
461 <bitWidth>1</bitWidth>
462 </field>
463 <field>
464 <name>DDS</name>
465 <description>DMA disable selection (for single ADC
466 mode)</description>
467 <bitOffset>9</bitOffset>
468 <bitWidth>1</bitWidth>
469 </field>
470 <field>
471 <name>DMA</name>
472 <description>Direct memory access mode (for single
473 ADC mode)</description>
474 <bitOffset>8</bitOffset>
475 <bitWidth>1</bitWidth>
476 </field>
477 <field>
478 <name>CONT</name>
479 <description>Continuous conversion</description>
480 <bitOffset>1</bitOffset>
481 <bitWidth>1</bitWidth>
482 </field>
483 <field>
484 <name>ADON</name>
485 <description>A/D Converter ON / OFF</description>
486 <bitOffset>0</bitOffset>
487 <bitWidth>1</bitWidth>
488 </field>
489 </fields>
490 </register>
491 <register>
492 <name>SMPR1</name>
493 <displayName>SMPR1</displayName>
494 <description>sample time register 1</description>
495 <addressOffset>0xC</addressOffset>
496 <size>0x20</size>
497 <access>read-write</access>
498 <resetValue>0x00000000</resetValue>
499 <fields>
500 <field>
501 <name>SMPx_x</name>
502 <description>Sample time bits</description>
503 <bitOffset>0</bitOffset>
504 <bitWidth>32</bitWidth>
505 </field>
506 </fields>
507 </register>
508 <register>
509 <name>SMPR2</name>
510 <displayName>SMPR2</displayName>
511 <description>sample time register 2</description>
512 <addressOffset>0x10</addressOffset>
513 <size>0x20</size>
514 <access>read-write</access>
515 <resetValue>0x00000000</resetValue>
516 <fields>
517 <field>
518 <name>SMPx_x</name>
519 <description>Sample time bits</description>
520 <bitOffset>0</bitOffset>
521 <bitWidth>32</bitWidth>
522 </field>
523 </fields>
524 </register>
525 <register>
526 <name>JOFR1</name>
527 <displayName>JOFR1</displayName>
528 <description>injected channel data offset register
529 x</description>
530 <addressOffset>0x14</addressOffset>
531 <size>0x20</size>
532 <access>read-write</access>
533 <resetValue>0x00000000</resetValue>
534 <fields>
535 <field>
536 <name>JOFFSET1</name>
537 <description>Data offset for injected channel
538 x</description>
539 <bitOffset>0</bitOffset>
540 <bitWidth>12</bitWidth>
541 </field>
542 </fields>
543 </register>
544 <register>
545 <name>JOFR2</name>
546 <displayName>JOFR2</displayName>
547 <description>injected channel data offset register
548 x</description>
549 <addressOffset>0x18</addressOffset>
550 <size>0x20</size>
551 <access>read-write</access>
552 <resetValue>0x00000000</resetValue>
553 <fields>
554 <field>
555 <name>JOFFSET2</name>
556 <description>Data offset for injected channel
557 x</description>
558 <bitOffset>0</bitOffset>
559 <bitWidth>12</bitWidth>
560 </field>
561 </fields>
562 </register>
563 <register>
564 <name>JOFR3</name>
565 <displayName>JOFR3</displayName>
566 <description>injected channel data offset register
567 x</description>
568 <addressOffset>0x1C</addressOffset>
569 <size>0x20</size>
570 <access>read-write</access>
571 <resetValue>0x00000000</resetValue>
572 <fields>
573 <field>
574 <name>JOFFSET3</name>
575 <description>Data offset for injected channel
576 x</description>
577 <bitOffset>0</bitOffset>
578 <bitWidth>12</bitWidth>
579 </field>
580 </fields>
581 </register>
582 <register>
583 <name>JOFR4</name>
584 <displayName>JOFR4</displayName>
585 <description>injected channel data offset register
586 x</description>
587 <addressOffset>0x20</addressOffset>
588 <size>0x20</size>
589 <access>read-write</access>
590 <resetValue>0x00000000</resetValue>
591 <fields>
592 <field>
593 <name>JOFFSET4</name>
594 <description>Data offset for injected channel
595 x</description>
596 <bitOffset>0</bitOffset>
597 <bitWidth>12</bitWidth>
598 </field>
599 </fields>
600 </register>
601 <register>
602 <name>HTR</name>
603 <displayName>HTR</displayName>
604 <description>watchdog higher threshold
605 register</description>
606 <addressOffset>0x24</addressOffset>
607 <size>0x20</size>
608 <access>read-write</access>
609 <resetValue>0x00000FFF</resetValue>
610 <fields>
611 <field>
612 <name>HT</name>
613 <description>Analog watchdog higher
614 threshold</description>
615 <bitOffset>0</bitOffset>
616 <bitWidth>12</bitWidth>
617 </field>
618 </fields>
619 </register>
620 <register>
621 <name>LTR</name>
622 <displayName>LTR</displayName>
623 <description>watchdog lower threshold
624 register</description>
625 <addressOffset>0x28</addressOffset>
626 <size>0x20</size>
627 <access>read-write</access>
628 <resetValue>0x00000000</resetValue>
629 <fields>
630 <field>
631 <name>LT</name>
632 <description>Analog watchdog lower
633 threshold</description>
634 <bitOffset>0</bitOffset>
635 <bitWidth>12</bitWidth>
636 </field>
637 </fields>
638 </register>
639 <register>
640 <name>SQR1</name>
641 <displayName>SQR1</displayName>
642 <description>regular sequence register 1</description>
643 <addressOffset>0x2C</addressOffset>
644 <size>0x20</size>
645 <access>read-write</access>
646 <resetValue>0x00000000</resetValue>
647 <fields>
648 <field>
649 <name>L</name>
650 <description>Regular channel sequence
651 length</description>
652 <bitOffset>20</bitOffset>
653 <bitWidth>4</bitWidth>
654 </field>
655 <field>
656 <name>SQ16</name>
657 <description>16th conversion in regular
658 sequence</description>
659 <bitOffset>15</bitOffset>
660 <bitWidth>5</bitWidth>
661 </field>
662 <field>
663 <name>SQ15</name>
664 <description>15th conversion in regular
665 sequence</description>
666 <bitOffset>10</bitOffset>
667 <bitWidth>5</bitWidth>
668 </field>
669 <field>
670 <name>SQ14</name>
671 <description>14th conversion in regular
672 sequence</description>
673 <bitOffset>5</bitOffset>
674 <bitWidth>5</bitWidth>
675 </field>
676 <field>
677 <name>SQ13</name>
678 <description>13th conversion in regular
679 sequence</description>
680 <bitOffset>0</bitOffset>
681 <bitWidth>5</bitWidth>
682 </field>
683 </fields>
684 </register>
685 <register>
686 <name>SQR2</name>
687 <displayName>SQR2</displayName>
688 <description>regular sequence register 2</description>
689 <addressOffset>0x30</addressOffset>
690 <size>0x20</size>
691 <access>read-write</access>
692 <resetValue>0x00000000</resetValue>
693 <fields>
694 <field>
695 <name>SQ12</name>
696 <description>12th conversion in regular
697 sequence</description>
698 <bitOffset>25</bitOffset>
699 <bitWidth>5</bitWidth>
700 </field>
701 <field>
702 <name>SQ11</name>
703 <description>11th conversion in regular
704 sequence</description>
705 <bitOffset>20</bitOffset>
706 <bitWidth>5</bitWidth>
707 </field>
708 <field>
709 <name>SQ10</name>
710 <description>10th conversion in regular
711 sequence</description>
712 <bitOffset>15</bitOffset>
713 <bitWidth>5</bitWidth>
714 </field>
715 <field>
716 <name>SQ9</name>
717 <description>9th conversion in regular
718 sequence</description>
719 <bitOffset>10</bitOffset>
720 <bitWidth>5</bitWidth>
721 </field>
722 <field>
723 <name>SQ8</name>
724 <description>8th conversion in regular
725 sequence</description>
726 <bitOffset>5</bitOffset>
727 <bitWidth>5</bitWidth>
728 </field>
729 <field>
730 <name>SQ7</name>
731 <description>7th conversion in regular
732 sequence</description>
733 <bitOffset>0</bitOffset>
734 <bitWidth>5</bitWidth>
735 </field>
736 </fields>
737 </register>
738 <register>
739 <name>SQR3</name>
740 <displayName>SQR3</displayName>
741 <description>regular sequence register 3</description>
742 <addressOffset>0x34</addressOffset>
743 <size>0x20</size>
744 <access>read-write</access>
745 <resetValue>0x00000000</resetValue>
746 <fields>
747 <field>
748 <name>SQ6</name>
749 <description>6th conversion in regular
750 sequence</description>
751 <bitOffset>25</bitOffset>
752 <bitWidth>5</bitWidth>
753 </field>
754 <field>
755 <name>SQ5</name>
756 <description>5th conversion in regular
757 sequence</description>
758 <bitOffset>20</bitOffset>
759 <bitWidth>5</bitWidth>
760 </field>
761 <field>
762 <name>SQ4</name>
763 <description>4th conversion in regular
764 sequence</description>
765 <bitOffset>15</bitOffset>
766 <bitWidth>5</bitWidth>
767 </field>
768 <field>
769 <name>SQ3</name>
770 <description>3rd conversion in regular
771 sequence</description>
772 <bitOffset>10</bitOffset>
773 <bitWidth>5</bitWidth>
774 </field>
775 <field>
776 <name>SQ2</name>
777 <description>2nd conversion in regular
778 sequence</description>
779 <bitOffset>5</bitOffset>
780 <bitWidth>5</bitWidth>
781 </field>
782 <field>
783 <name>SQ1</name>
784 <description>1st conversion in regular
785 sequence</description>
786 <bitOffset>0</bitOffset>
787 <bitWidth>5</bitWidth>
788 </field>
789 </fields>
790 </register>
791 <register>
792 <name>JSQR</name>
793 <displayName>JSQR</displayName>
794 <description>injected sequence register</description>
795 <addressOffset>0x38</addressOffset>
796 <size>0x20</size>
797 <access>read-write</access>
798 <resetValue>0x00000000</resetValue>
799 <fields>
800 <field>
801 <name>JL</name>
802 <description>Injected sequence length</description>
803 <bitOffset>20</bitOffset>
804 <bitWidth>2</bitWidth>
805 </field>
806 <field>
807 <name>JSQ4</name>
808 <description>4th conversion in injected
809 sequence</description>
810 <bitOffset>15</bitOffset>
811 <bitWidth>5</bitWidth>
812 </field>
813 <field>
814 <name>JSQ3</name>
815 <description>3rd conversion in injected
816 sequence</description>
817 <bitOffset>10</bitOffset>
818 <bitWidth>5</bitWidth>
819 </field>
820 <field>
821 <name>JSQ2</name>
822 <description>2nd conversion in injected
823 sequence</description>
824 <bitOffset>5</bitOffset>
825 <bitWidth>5</bitWidth>
826 </field>
827 <field>
828 <name>JSQ1</name>
829 <description>1st conversion in injected
830 sequence</description>
831 <bitOffset>0</bitOffset>
832 <bitWidth>5</bitWidth>
833 </field>
834 </fields>
835 </register>
836 <register>
837 <name>JDR1</name>
838 <displayName>JDR1</displayName>
839 <description>injected data register x</description>
840 <addressOffset>0x3C</addressOffset>
841 <size>0x20</size>
842 <access>read-only</access>
843 <resetValue>0x00000000</resetValue>
844 <fields>
845 <field>
846 <name>JDATA</name>
847 <description>Injected data</description>
848 <bitOffset>0</bitOffset>
849 <bitWidth>16</bitWidth>
850 </field>
851 </fields>
852 </register>
853 <register>
854 <name>JDR2</name>
855 <displayName>JDR2</displayName>
856 <description>injected data register x</description>
857 <addressOffset>0x40</addressOffset>
858 <size>0x20</size>
859 <access>read-only</access>
860 <resetValue>0x00000000</resetValue>
861 <fields>
862 <field>
863 <name>JDATA</name>
864 <description>Injected data</description>
865 <bitOffset>0</bitOffset>
866 <bitWidth>16</bitWidth>
867 </field>
868 </fields>
869 </register>
870 <register>
871 <name>JDR3</name>
872 <displayName>JDR3</displayName>
873 <description>injected data register x</description>
874 <addressOffset>0x44</addressOffset>
875 <size>0x20</size>
876 <access>read-only</access>
877 <resetValue>0x00000000</resetValue>
878 <fields>
879 <field>
880 <name>JDATA</name>
881 <description>Injected data</description>
882 <bitOffset>0</bitOffset>
883 <bitWidth>16</bitWidth>
884 </field>
885 </fields>
886 </register>
887 <register>
888 <name>JDR4</name>
889 <displayName>JDR4</displayName>
890 <description>injected data register x</description>
891 <addressOffset>0x48</addressOffset>
892 <size>0x20</size>
893 <access>read-only</access>
894 <resetValue>0x00000000</resetValue>
895 <fields>
896 <field>
897 <name>JDATA</name>
898 <description>Injected data</description>
899 <bitOffset>0</bitOffset>
900 <bitWidth>16</bitWidth>
901 </field>
902 </fields>
903 </register>
904 <register>
905 <name>DR</name>
906 <displayName>DR</displayName>
907 <description>regular data register</description>
908 <addressOffset>0x4C</addressOffset>
909 <size>0x20</size>
910 <access>read-only</access>
911 <resetValue>0x00000000</resetValue>
912 <fields>
913 <field>
914 <name>DATA</name>
915 <description>Regular data</description>
916 <bitOffset>0</bitOffset>
917 <bitWidth>16</bitWidth>
918 </field>
919 </fields>
920 </register>
921 </registers>
922 </peripheral>
923 <peripheral>
924 <name>CRC</name>
925 <description>Cryptographic processor</description>
926 <groupName>CRC</groupName>
927 <baseAddress>0x40023000</baseAddress>
928 <addressBlock>
929 <offset>0x0</offset>
930 <size>0x400</size>
931 <usage>registers</usage>
932 </addressBlock>
933 <registers>
934 <register>
935 <name>DR</name>
936 <displayName>DR</displayName>
937 <description>Data register</description>
938 <addressOffset>0x0</addressOffset>
939 <size>0x20</size>
940 <access>read-write</access>
941 <resetValue>0xFFFFFFFF</resetValue>
942 <fields>
943 <field>
944 <name>DR</name>
945 <description>Data Register</description>
946 <bitOffset>0</bitOffset>
947 <bitWidth>32</bitWidth>
948 </field>
949 </fields>
950 </register>
951 <register>
952 <name>IDR</name>
953 <displayName>IDR</displayName>
954 <description>Independent Data register</description>
955 <addressOffset>0x4</addressOffset>
956 <size>0x20</size>
957 <access>read-write</access>
958 <resetValue>0x00000000</resetValue>
959 <fields>
960 <field>
961 <name>IDR</name>
962 <description>Independent Data register</description>
963 <bitOffset>0</bitOffset>
964 <bitWidth>8</bitWidth>
965 </field>
966 </fields>
967 </register>
968 <register>
969 <name>CR</name>
970 <displayName>CR</displayName>
971 <description>Control register</description>
972 <addressOffset>0x8</addressOffset>
973 <size>0x20</size>
974 <access>write-only</access>
975 <resetValue>0x00000000</resetValue>
976 <fields>
977 <field>
978 <name>CR</name>
979 <description>Control regidter</description>
980 <bitOffset>0</bitOffset>
981 <bitWidth>1</bitWidth>
982 </field>
983 </fields>
984 </register>
985 </registers>
986 </peripheral>
987 <peripheral>
988 <name>DBG</name>
989 <description>Debug support</description>
990 <groupName>DBG</groupName>
991 <baseAddress>0xE0042000</baseAddress>
992 <addressBlock>
993 <offset>0x0</offset>
994 <size>0x400</size>
995 <usage>registers</usage>
996 </addressBlock>
997 <registers>
998 <register>
999 <name>DBGMCU_IDCODE</name>
1000 <displayName>DBGMCU_IDCODE</displayName>
1001 <description>IDCODE</description>
1002 <addressOffset>0x0</addressOffset>
1003 <size>0x20</size>
1004 <access>read-only</access>
1005 <resetValue>0x10006411</resetValue>
1006 <fields>
1007 <field>
1008 <name>DEV_ID</name>
1009 <description>DEV_ID</description>
1010 <bitOffset>0</bitOffset>
1011 <bitWidth>12</bitWidth>
1012 </field>
1013 <field>
1014 <name>REV_ID</name>
1015 <description>REV_ID</description>
1016 <bitOffset>16</bitOffset>
1017 <bitWidth>16</bitWidth>
1018 </field>
1019 </fields>
1020 </register>
1021 <register>
1022 <name>DBGMCU_CR</name>
1023 <displayName>DBGMCU_CR</displayName>
1024 <description>Control Register</description>
1025 <addressOffset>0x4</addressOffset>
1026 <size>0x20</size>
1027 <access>read-write</access>
1028 <resetValue>0x00000000</resetValue>
1029 <fields>
1030 <field>
1031 <name>DBG_SLEEP</name>
1032 <description>DBG_SLEEP</description>
1033 <bitOffset>0</bitOffset>
1034 <bitWidth>1</bitWidth>
1035 </field>
1036 <field>
1037 <name>DBG_STOP</name>
1038 <description>DBG_STOP</description>
1039 <bitOffset>1</bitOffset>
1040 <bitWidth>1</bitWidth>
1041 </field>
1042 <field>
1043 <name>DBG_STANDBY</name>
1044 <description>DBG_STANDBY</description>
1045 <bitOffset>2</bitOffset>
1046 <bitWidth>1</bitWidth>
1047 </field>
1048 <field>
1049 <name>TRACE_IOEN</name>
1050 <description>TRACE_IOEN</description>
1051 <bitOffset>5</bitOffset>
1052 <bitWidth>1</bitWidth>
1053 </field>
1054 <field>
1055 <name>TRACE_MODE</name>
1056 <description>TRACE_MODE</description>
1057 <bitOffset>6</bitOffset>
1058 <bitWidth>2</bitWidth>
1059 </field>
1060 </fields>
1061 </register>
1062 <register>
1063 <name>DBGMCU_APB1_FZ</name>
1064 <displayName>DBGMCU_APB1_FZ</displayName>
1065 <description>Debug MCU APB1 Freeze registe</description>
1066 <addressOffset>0x8</addressOffset>
1067 <size>0x20</size>
1068 <access>read-write</access>
1069 <resetValue>0x00000000</resetValue>
1070 <fields>
1071 <field>
1072 <name>DBG_TIM2_STOP</name>
1073 <description>DBG_TIM2_STOP</description>
1074 <bitOffset>0</bitOffset>
1075 <bitWidth>1</bitWidth>
1076 </field>
1077 <field>
1078 <name>DBG_TIM3_STOP</name>
1079 <description>DBG_TIM3 _STOP</description>
1080 <bitOffset>1</bitOffset>
1081 <bitWidth>1</bitWidth>
1082 </field>
1083 <field>
1084 <name>DBG_TIM4_STOP</name>
1085 <description>DBG_TIM4_STOP</description>
1086 <bitOffset>2</bitOffset>
1087 <bitWidth>1</bitWidth>
1088 </field>
1089 <field>
1090 <name>DBG_TIM5_STOP</name>
1091 <description>DBG_TIM5_STOP</description>
1092 <bitOffset>3</bitOffset>
1093 <bitWidth>1</bitWidth>
1094 </field>
1095 <field>
1096 <name>DBG_RTC_Stop</name>
1097 <description>RTC stopped when Core is
1098 halted</description>
1099 <bitOffset>10</bitOffset>
1100 <bitWidth>1</bitWidth>
1101 </field>
1102 <field>
1103 <name>DBG_WWDG_STOP</name>
1104 <description>DBG_WWDG_STOP</description>
1105 <bitOffset>11</bitOffset>
1106 <bitWidth>1</bitWidth>
1107 </field>
1108 <field>
1109 <name>DBG_IWDEG_STOP</name>
1110 <description>DBG_IWDEG_STOP</description>
1111 <bitOffset>12</bitOffset>
1112 <bitWidth>1</bitWidth>
1113 </field>
1114 <field>
1115 <name>DBG_I2C1_SMBUS_TIMEOUT</name>
1116 <description>DBG_J2C1_SMBUS_TIMEOUT</description>
1117 <bitOffset>21</bitOffset>
1118 <bitWidth>1</bitWidth>
1119 </field>
1120 <field>
1121 <name>DBG_I2C2_SMBUS_TIMEOUT</name>
1122 <description>DBG_J2C2_SMBUS_TIMEOUT</description>
1123 <bitOffset>22</bitOffset>
1124 <bitWidth>1</bitWidth>
1125 </field>
1126 <field>
1127 <name>DBG_I2C3SMBUS_TIMEOUT</name>
1128 <description>DBG_J2C3SMBUS_TIMEOUT</description>
1129 <bitOffset>23</bitOffset>
1130 <bitWidth>1</bitWidth>
1131 </field>
1132 </fields>
1133 </register>
1134 <register>
1135 <name>DBGMCU_APB2_FZ</name>
1136 <displayName>DBGMCU_APB2_FZ</displayName>
1137 <description>Debug MCU APB2 Freeze registe</description>
1138 <addressOffset>0xC</addressOffset>
1139 <size>0x20</size>
1140 <access>read-write</access>
1141 <resetValue>0x00000000</resetValue>
1142 <fields>
1143 <field>
1144 <name>DBG_TIM1_STOP</name>
1145 <description>TIM1 counter stopped when core is
1146 halted</description>
1147 <bitOffset>0</bitOffset>
1148 <bitWidth>1</bitWidth>
1149 </field>
1150 <field>
1151 <name>DBG_TIM9_STOP</name>
1152 <description>TIM9 counter stopped when core is
1153 halted</description>
1154 <bitOffset>16</bitOffset>
1155 <bitWidth>1</bitWidth>
1156 </field>
1157 <field>
1158 <name>DBG_TIM10_STOP</name>
1159 <description>TIM10 counter stopped when core is
1160 halted</description>
1161 <bitOffset>17</bitOffset>
1162 <bitWidth>1</bitWidth>
1163 </field>
1164 <field>
1165 <name>DBG_TIM11_STOP</name>
1166 <description>TIM11 counter stopped when core is
1167 halted</description>
1168 <bitOffset>18</bitOffset>
1169 <bitWidth>1</bitWidth>
1170 </field>
1171 </fields>
1172 </register>
1173 </registers>
1174 </peripheral>
1175 <peripheral>
1176 <name>EXTI</name>
1177 <description>External interrupt/event
1178 controller</description>
1179 <groupName>EXTI</groupName>
1180 <baseAddress>0x40013C00</baseAddress>
1181 <addressBlock>
1182 <offset>0x0</offset>
1183 <size>0x400</size>
1184 <usage>registers</usage>
1185 </addressBlock>
1186 <interrupt>
1187 <name>TAMP_STAMP</name>
1188 <description>Tamper and TimeStamp interrupts through the
1189 EXTI line</description>
1190 <value>2</value>
1191 </interrupt>
1192 <interrupt>
1193 <name>EXTI0</name>
1194 <description>EXTI Line0 interrupt</description>
1195 <value>6</value>
1196 </interrupt>
1197 <interrupt>
1198 <name>EXTI1</name>
1199 <description>EXTI Line1 interrupt</description>
1200 <value>7</value>
1201 </interrupt>
1202 <interrupt>
1203 <name>EXTI2</name>
1204 <description>EXTI Line2 interrupt</description>
1205 <value>8</value>
1206 </interrupt>
1207 <interrupt>
1208 <name>EXTI3</name>
1209 <description>EXTI Line3 interrupt</description>
1210 <value>9</value>
1211 </interrupt>
1212 <interrupt>
1213 <name>EXTI4</name>
1214 <description>EXTI Line4 interrupt</description>
1215 <value>10</value>
1216 </interrupt>
1217 <interrupt>
1218 <name>EXTI9_5</name>
1219 <description>EXTI Line[9:5] interrupts</description>
1220 <value>23</value>
1221 </interrupt>
1222 <interrupt>
1223 <name>EXTI15_10</name>
1224 <description>EXTI Line[15:10] interrupts</description>
1225 <value>40</value>
1226 </interrupt>
1227 <registers>
1228 <register>
1229 <name>IMR</name>
1230 <displayName>IMR</displayName>
1231 <description>Interrupt mask register
1232 (EXTI_IMR)</description>
1233 <addressOffset>0x0</addressOffset>
1234 <size>0x20</size>
1235 <access>read-write</access>
1236 <resetValue>0x00000000</resetValue>
1237 <fields>
1238 <field>
1239 <name>MR0</name>
1240 <description>Interrupt Mask on line 0</description>
1241 <bitOffset>0</bitOffset>
1242 <bitWidth>1</bitWidth>
1243 </field>
1244 <field>
1245 <name>MR1</name>
1246 <description>Interrupt Mask on line 1</description>
1247 <bitOffset>1</bitOffset>
1248 <bitWidth>1</bitWidth>
1249 </field>
1250 <field>
1251 <name>MR2</name>
1252 <description>Interrupt Mask on line 2</description>
1253 <bitOffset>2</bitOffset>
1254 <bitWidth>1</bitWidth>
1255 </field>
1256 <field>
1257 <name>MR3</name>
1258 <description>Interrupt Mask on line 3</description>
1259 <bitOffset>3</bitOffset>
1260 <bitWidth>1</bitWidth>
1261 </field>
1262 <field>
1263 <name>MR4</name>
1264 <description>Interrupt Mask on line 4</description>
1265 <bitOffset>4</bitOffset>
1266 <bitWidth>1</bitWidth>
1267 </field>
1268 <field>
1269 <name>MR5</name>
1270 <description>Interrupt Mask on line 5</description>
1271 <bitOffset>5</bitOffset>
1272 <bitWidth>1</bitWidth>
1273 </field>
1274 <field>
1275 <name>MR6</name>
1276 <description>Interrupt Mask on line 6</description>
1277 <bitOffset>6</bitOffset>
1278 <bitWidth>1</bitWidth>
1279 </field>
1280 <field>
1281 <name>MR7</name>
1282 <description>Interrupt Mask on line 7</description>
1283 <bitOffset>7</bitOffset>
1284 <bitWidth>1</bitWidth>
1285 </field>
1286 <field>
1287 <name>MR8</name>
1288 <description>Interrupt Mask on line 8</description>
1289 <bitOffset>8</bitOffset>
1290 <bitWidth>1</bitWidth>
1291 </field>
1292 <field>
1293 <name>MR9</name>
1294 <description>Interrupt Mask on line 9</description>
1295 <bitOffset>9</bitOffset>
1296 <bitWidth>1</bitWidth>
1297 </field>
1298 <field>
1299 <name>MR10</name>
1300 <description>Interrupt Mask on line 10</description>
1301 <bitOffset>10</bitOffset>
1302 <bitWidth>1</bitWidth>
1303 </field>
1304 <field>
1305 <name>MR11</name>
1306 <description>Interrupt Mask on line 11</description>
1307 <bitOffset>11</bitOffset>
1308 <bitWidth>1</bitWidth>
1309 </field>
1310 <field>
1311 <name>MR12</name>
1312 <description>Interrupt Mask on line 12</description>
1313 <bitOffset>12</bitOffset>
1314 <bitWidth>1</bitWidth>
1315 </field>
1316 <field>
1317 <name>MR13</name>
1318 <description>Interrupt Mask on line 13</description>
1319 <bitOffset>13</bitOffset>
1320 <bitWidth>1</bitWidth>
1321 </field>
1322 <field>
1323 <name>MR14</name>
1324 <description>Interrupt Mask on line 14</description>
1325 <bitOffset>14</bitOffset>
1326 <bitWidth>1</bitWidth>
1327 </field>
1328 <field>
1329 <name>MR15</name>
1330 <description>Interrupt Mask on line 15</description>
1331 <bitOffset>15</bitOffset>
1332 <bitWidth>1</bitWidth>
1333 </field>
1334 <field>
1335 <name>MR16</name>
1336 <description>Interrupt Mask on line 16</description>
1337 <bitOffset>16</bitOffset>
1338 <bitWidth>1</bitWidth>
1339 </field>
1340 <field>
1341 <name>MR17</name>
1342 <description>Interrupt Mask on line 17</description>
1343 <bitOffset>17</bitOffset>
1344 <bitWidth>1</bitWidth>
1345 </field>
1346 <field>
1347 <name>MR18</name>
1348 <description>Interrupt Mask on line 18</description>
1349 <bitOffset>18</bitOffset>
1350 <bitWidth>1</bitWidth>
1351 </field>
1352 <field>
1353 <name>MR19</name>
1354 <description>Interrupt Mask on line 19</description>
1355 <bitOffset>19</bitOffset>
1356 <bitWidth>1</bitWidth>
1357 </field>
1358 <field>
1359 <name>MR20</name>
1360 <description>Interrupt Mask on line 20</description>
1361 <bitOffset>20</bitOffset>
1362 <bitWidth>1</bitWidth>
1363 </field>
1364 <field>
1365 <name>MR21</name>
1366 <description>Interrupt Mask on line 21</description>
1367 <bitOffset>21</bitOffset>
1368 <bitWidth>1</bitWidth>
1369 </field>
1370 <field>
1371 <name>MR22</name>
1372 <description>Interrupt Mask on line 22</description>
1373 <bitOffset>22</bitOffset>
1374 <bitWidth>1</bitWidth>
1375 </field>
1376 </fields>
1377 </register>
1378 <register>
1379 <name>EMR</name>
1380 <displayName>EMR</displayName>
1381 <description>Event mask register (EXTI_EMR)</description>
1382 <addressOffset>0x4</addressOffset>
1383 <size>0x20</size>
1384 <access>read-write</access>
1385 <resetValue>0x00000000</resetValue>
1386 <fields>
1387 <field>
1388 <name>MR0</name>
1389 <description>Event Mask on line 0</description>
1390 <bitOffset>0</bitOffset>
1391 <bitWidth>1</bitWidth>
1392 </field>
1393 <field>
1394 <name>MR1</name>
1395 <description>Event Mask on line 1</description>
1396 <bitOffset>1</bitOffset>
1397 <bitWidth>1</bitWidth>
1398 </field>
1399 <field>
1400 <name>MR2</name>
1401 <description>Event Mask on line 2</description>
1402 <bitOffset>2</bitOffset>
1403 <bitWidth>1</bitWidth>
1404 </field>
1405 <field>
1406 <name>MR3</name>
1407 <description>Event Mask on line 3</description>
1408 <bitOffset>3</bitOffset>
1409 <bitWidth>1</bitWidth>
1410 </field>
1411 <field>
1412 <name>MR4</name>
1413 <description>Event Mask on line 4</description>
1414 <bitOffset>4</bitOffset>
1415 <bitWidth>1</bitWidth>
1416 </field>
1417 <field>
1418 <name>MR5</name>
1419 <description>Event Mask on line 5</description>
1420 <bitOffset>5</bitOffset>
1421 <bitWidth>1</bitWidth>
1422 </field>
1423 <field>
1424 <name>MR6</name>
1425 <description>Event Mask on line 6</description>
1426 <bitOffset>6</bitOffset>
1427 <bitWidth>1</bitWidth>
1428 </field>
1429 <field>
1430 <name>MR7</name>
1431 <description>Event Mask on line 7</description>
1432 <bitOffset>7</bitOffset>
1433 <bitWidth>1</bitWidth>
1434 </field>
1435 <field>
1436 <name>MR8</name>
1437 <description>Event Mask on line 8</description>
1438 <bitOffset>8</bitOffset>
1439 <bitWidth>1</bitWidth>
1440 </field>
1441 <field>
1442 <name>MR9</name>
1443 <description>Event Mask on line 9</description>
1444 <bitOffset>9</bitOffset>
1445 <bitWidth>1</bitWidth>
1446 </field>
1447 <field>
1448 <name>MR10</name>
1449 <description>Event Mask on line 10</description>
1450 <bitOffset>10</bitOffset>
1451 <bitWidth>1</bitWidth>
1452 </field>
1453 <field>
1454 <name>MR11</name>
1455 <description>Event Mask on line 11</description>
1456 <bitOffset>11</bitOffset>
1457 <bitWidth>1</bitWidth>
1458 </field>
1459 <field>
1460 <name>MR12</name>
1461 <description>Event Mask on line 12</description>
1462 <bitOffset>12</bitOffset>
1463 <bitWidth>1</bitWidth>
1464 </field>
1465 <field>
1466 <name>MR13</name>
1467 <description>Event Mask on line 13</description>
1468 <bitOffset>13</bitOffset>
1469 <bitWidth>1</bitWidth>
1470 </field>
1471 <field>
1472 <name>MR14</name>
1473 <description>Event Mask on line 14</description>
1474 <bitOffset>14</bitOffset>
1475 <bitWidth>1</bitWidth>
1476 </field>
1477 <field>
1478 <name>MR15</name>
1479 <description>Event Mask on line 15</description>
1480 <bitOffset>15</bitOffset>
1481 <bitWidth>1</bitWidth>
1482 </field>
1483 <field>
1484 <name>MR16</name>
1485 <description>Event Mask on line 16</description>
1486 <bitOffset>16</bitOffset>
1487 <bitWidth>1</bitWidth>
1488 </field>
1489 <field>
1490 <name>MR17</name>
1491 <description>Event Mask on line 17</description>
1492 <bitOffset>17</bitOffset>
1493 <bitWidth>1</bitWidth>
1494 </field>
1495 <field>
1496 <name>MR18</name>
1497 <description>Event Mask on line 18</description>
1498 <bitOffset>18</bitOffset>
1499 <bitWidth>1</bitWidth>
1500 </field>
1501 <field>
1502 <name>MR19</name>
1503 <description>Event Mask on line 19</description>
1504 <bitOffset>19</bitOffset>
1505 <bitWidth>1</bitWidth>
1506 </field>
1507 <field>
1508 <name>MR20</name>
1509 <description>Event Mask on line 20</description>
1510 <bitOffset>20</bitOffset>
1511 <bitWidth>1</bitWidth>
1512 </field>
1513 <field>
1514 <name>MR21</name>
1515 <description>Event Mask on line 21</description>
1516 <bitOffset>21</bitOffset>
1517 <bitWidth>1</bitWidth>
1518 </field>
1519 <field>
1520 <name>MR22</name>
1521 <description>Event Mask on line 22</description>
1522 <bitOffset>22</bitOffset>
1523 <bitWidth>1</bitWidth>
1524 </field>
1525 </fields>
1526 </register>
1527 <register>
1528 <name>RTSR</name>
1529 <displayName>RTSR</displayName>
1530 <description>Rising Trigger selection register
1531 (EXTI_RTSR)</description>
1532 <addressOffset>0x8</addressOffset>
1533 <size>0x20</size>
1534 <access>read-write</access>
1535 <resetValue>0x00000000</resetValue>
1536 <fields>
1537 <field>
1538 <name>TR0</name>
1539 <description>Rising trigger event configuration of
1540 line 0</description>
1541 <bitOffset>0</bitOffset>
1542 <bitWidth>1</bitWidth>
1543 </field>
1544 <field>
1545 <name>TR1</name>
1546 <description>Rising trigger event configuration of
1547 line 1</description>
1548 <bitOffset>1</bitOffset>
1549 <bitWidth>1</bitWidth>
1550 </field>
1551 <field>
1552 <name>TR2</name>
1553 <description>Rising trigger event configuration of
1554 line 2</description>
1555 <bitOffset>2</bitOffset>
1556 <bitWidth>1</bitWidth>
1557 </field>
1558 <field>
1559 <name>TR3</name>
1560 <description>Rising trigger event configuration of
1561 line 3</description>
1562 <bitOffset>3</bitOffset>
1563 <bitWidth>1</bitWidth>
1564 </field>
1565 <field>
1566 <name>TR4</name>
1567 <description>Rising trigger event configuration of
1568 line 4</description>
1569 <bitOffset>4</bitOffset>
1570 <bitWidth>1</bitWidth>
1571 </field>
1572 <field>
1573 <name>TR5</name>
1574 <description>Rising trigger event configuration of
1575 line 5</description>
1576 <bitOffset>5</bitOffset>
1577 <bitWidth>1</bitWidth>
1578 </field>
1579 <field>
1580 <name>TR6</name>
1581 <description>Rising trigger event configuration of
1582 line 6</description>
1583 <bitOffset>6</bitOffset>
1584 <bitWidth>1</bitWidth>
1585 </field>
1586 <field>
1587 <name>TR7</name>
1588 <description>Rising trigger event configuration of
1589 line 7</description>
1590 <bitOffset>7</bitOffset>
1591 <bitWidth>1</bitWidth>
1592 </field>
1593 <field>
1594 <name>TR8</name>
1595 <description>Rising trigger event configuration of
1596 line 8</description>
1597 <bitOffset>8</bitOffset>
1598 <bitWidth>1</bitWidth>
1599 </field>
1600 <field>
1601 <name>TR9</name>
1602 <description>Rising trigger event configuration of
1603 line 9</description>
1604 <bitOffset>9</bitOffset>
1605 <bitWidth>1</bitWidth>
1606 </field>
1607 <field>
1608 <name>TR10</name>
1609 <description>Rising trigger event configuration of
1610 line 10</description>
1611 <bitOffset>10</bitOffset>
1612 <bitWidth>1</bitWidth>
1613 </field>
1614 <field>
1615 <name>TR11</name>
1616 <description>Rising trigger event configuration of
1617 line 11</description>
1618 <bitOffset>11</bitOffset>
1619 <bitWidth>1</bitWidth>
1620 </field>
1621 <field>
1622 <name>TR12</name>
1623 <description>Rising trigger event configuration of
1624 line 12</description>
1625 <bitOffset>12</bitOffset>
1626 <bitWidth>1</bitWidth>
1627 </field>
1628 <field>
1629 <name>TR13</name>
1630 <description>Rising trigger event configuration of
1631 line 13</description>
1632 <bitOffset>13</bitOffset>
1633 <bitWidth>1</bitWidth>
1634 </field>
1635 <field>
1636 <name>TR14</name>
1637 <description>Rising trigger event configuration of
1638 line 14</description>
1639 <bitOffset>14</bitOffset>
1640 <bitWidth>1</bitWidth>
1641 </field>
1642 <field>
1643 <name>TR15</name>
1644 <description>Rising trigger event configuration of
1645 line 15</description>
1646 <bitOffset>15</bitOffset>
1647 <bitWidth>1</bitWidth>
1648 </field>
1649 <field>
1650 <name>TR16</name>
1651 <description>Rising trigger event configuration of
1652 line 16</description>
1653 <bitOffset>16</bitOffset>
1654 <bitWidth>1</bitWidth>
1655 </field>
1656 <field>
1657 <name>TR17</name>
1658 <description>Rising trigger event configuration of
1659 line 17</description>
1660 <bitOffset>17</bitOffset>
1661 <bitWidth>1</bitWidth>
1662 </field>
1663 <field>
1664 <name>TR18</name>
1665 <description>Rising trigger event configuration of
1666 line 18</description>
1667 <bitOffset>18</bitOffset>
1668 <bitWidth>1</bitWidth>
1669 </field>
1670 <field>
1671 <name>TR19</name>
1672 <description>Rising trigger event configuration of
1673 line 19</description>
1674 <bitOffset>19</bitOffset>
1675 <bitWidth>1</bitWidth>
1676 </field>
1677 <field>
1678 <name>TR20</name>
1679 <description>Rising trigger event configuration of
1680 line 20</description>
1681 <bitOffset>20</bitOffset>
1682 <bitWidth>1</bitWidth>
1683 </field>
1684 <field>
1685 <name>TR21</name>
1686 <description>Rising trigger event configuration of
1687 line 21</description>
1688 <bitOffset>21</bitOffset>
1689 <bitWidth>1</bitWidth>
1690 </field>
1691 <field>
1692 <name>TR22</name>
1693 <description>Rising trigger event configuration of
1694 line 22</description>
1695 <bitOffset>22</bitOffset>
1696 <bitWidth>1</bitWidth>
1697 </field>
1698 </fields>
1699 </register>
1700 <register>
1701 <name>FTSR</name>
1702 <displayName>FTSR</displayName>
1703 <description>Falling Trigger selection register
1704 (EXTI_FTSR)</description>
1705 <addressOffset>0xC</addressOffset>
1706 <size>0x20</size>
1707 <access>read-write</access>
1708 <resetValue>0x00000000</resetValue>
1709 <fields>
1710 <field>
1711 <name>TR0</name>
1712 <description>Falling trigger event configuration of
1713 line 0</description>
1714 <bitOffset>0</bitOffset>
1715 <bitWidth>1</bitWidth>
1716 </field>
1717 <field>
1718 <name>TR1</name>
1719 <description>Falling trigger event configuration of
1720 line 1</description>
1721 <bitOffset>1</bitOffset>
1722 <bitWidth>1</bitWidth>
1723 </field>
1724 <field>
1725 <name>TR2</name>
1726 <description>Falling trigger event configuration of
1727 line 2</description>
1728 <bitOffset>2</bitOffset>
1729 <bitWidth>1</bitWidth>
1730 </field>
1731 <field>
1732 <name>TR3</name>
1733 <description>Falling trigger event configuration of
1734 line 3</description>
1735 <bitOffset>3</bitOffset>
1736 <bitWidth>1</bitWidth>
1737 </field>
1738 <field>
1739 <name>TR4</name>
1740 <description>Falling trigger event configuration of
1741 line 4</description>
1742 <bitOffset>4</bitOffset>
1743 <bitWidth>1</bitWidth>
1744 </field>
1745 <field>
1746 <name>TR5</name>
1747 <description>Falling trigger event configuration of
1748 line 5</description>
1749 <bitOffset>5</bitOffset>
1750 <bitWidth>1</bitWidth>
1751 </field>
1752 <field>
1753 <name>TR6</name>
1754 <description>Falling trigger event configuration of
1755 line 6</description>
1756 <bitOffset>6</bitOffset>
1757 <bitWidth>1</bitWidth>
1758 </field>
1759 <field>
1760 <name>TR7</name>
1761 <description>Falling trigger event configuration of
1762 line 7</description>
1763 <bitOffset>7</bitOffset>
1764 <bitWidth>1</bitWidth>
1765 </field>
1766 <field>
1767 <name>TR8</name>
1768 <description>Falling trigger event configuration of
1769 line 8</description>
1770 <bitOffset>8</bitOffset>
1771 <bitWidth>1</bitWidth>
1772 </field>
1773 <field>
1774 <name>TR9</name>
1775 <description>Falling trigger event configuration of
1776 line 9</description>
1777 <bitOffset>9</bitOffset>
1778 <bitWidth>1</bitWidth>
1779 </field>
1780 <field>
1781 <name>TR10</name>
1782 <description>Falling trigger event configuration of
1783 line 10</description>
1784 <bitOffset>10</bitOffset>
1785 <bitWidth>1</bitWidth>
1786 </field>
1787 <field>
1788 <name>TR11</name>
1789 <description>Falling trigger event configuration of
1790 line 11</description>
1791 <bitOffset>11</bitOffset>
1792 <bitWidth>1</bitWidth>
1793 </field>
1794 <field>
1795 <name>TR12</name>
1796 <description>Falling trigger event configuration of
1797 line 12</description>
1798 <bitOffset>12</bitOffset>
1799 <bitWidth>1</bitWidth>
1800 </field>
1801 <field>
1802 <name>TR13</name>
1803 <description>Falling trigger event configuration of
1804 line 13</description>
1805 <bitOffset>13</bitOffset>
1806 <bitWidth>1</bitWidth>
1807 </field>
1808 <field>
1809 <name>TR14</name>
1810 <description>Falling trigger event configuration of
1811 line 14</description>
1812 <bitOffset>14</bitOffset>
1813 <bitWidth>1</bitWidth>
1814 </field>
1815 <field>
1816 <name>TR15</name>
1817 <description>Falling trigger event configuration of
1818 line 15</description>
1819 <bitOffset>15</bitOffset>
1820 <bitWidth>1</bitWidth>
1821 </field>
1822 <field>
1823 <name>TR16</name>
1824 <description>Falling trigger event configuration of
1825 line 16</description>
1826 <bitOffset>16</bitOffset>
1827 <bitWidth>1</bitWidth>
1828 </field>
1829 <field>
1830 <name>TR17</name>
1831 <description>Falling trigger event configuration of
1832 line 17</description>
1833 <bitOffset>17</bitOffset>
1834 <bitWidth>1</bitWidth>
1835 </field>
1836 <field>
1837 <name>TR18</name>
1838 <description>Falling trigger event configuration of
1839 line 18</description>
1840 <bitOffset>18</bitOffset>
1841 <bitWidth>1</bitWidth>
1842 </field>
1843 <field>
1844 <name>TR19</name>
1845 <description>Falling trigger event configuration of
1846 line 19</description>
1847 <bitOffset>19</bitOffset>
1848 <bitWidth>1</bitWidth>
1849 </field>
1850 <field>
1851 <name>TR20</name>
1852 <description>Falling trigger event configuration of
1853 line 20</description>
1854 <bitOffset>20</bitOffset>
1855 <bitWidth>1</bitWidth>
1856 </field>
1857 <field>
1858 <name>TR21</name>
1859 <description>Falling trigger event configuration of
1860 line 21</description>
1861 <bitOffset>21</bitOffset>
1862 <bitWidth>1</bitWidth>
1863 </field>
1864 <field>
1865 <name>TR22</name>
1866 <description>Falling trigger event configuration of
1867 line 22</description>
1868 <bitOffset>22</bitOffset>
1869 <bitWidth>1</bitWidth>
1870 </field>
1871 </fields>
1872 </register>
1873 <register>
1874 <name>SWIER</name>
1875 <displayName>SWIER</displayName>
1876 <description>Software interrupt event register
1877 (EXTI_SWIER)</description>
1878 <addressOffset>0x10</addressOffset>
1879 <size>0x20</size>
1880 <access>read-write</access>
1881 <resetValue>0x00000000</resetValue>
1882 <fields>
1883 <field>
1884 <name>SWIER0</name>
1885 <description>Software Interrupt on line
1886 0</description>
1887 <bitOffset>0</bitOffset>
1888 <bitWidth>1</bitWidth>
1889 </field>
1890 <field>
1891 <name>SWIER1</name>
1892 <description>Software Interrupt on line
1893 1</description>
1894 <bitOffset>1</bitOffset>
1895 <bitWidth>1</bitWidth>
1896 </field>
1897 <field>
1898 <name>SWIER2</name>
1899 <description>Software Interrupt on line
1900 2</description>
1901 <bitOffset>2</bitOffset>
1902 <bitWidth>1</bitWidth>
1903 </field>
1904 <field>
1905 <name>SWIER3</name>
1906 <description>Software Interrupt on line
1907 3</description>
1908 <bitOffset>3</bitOffset>
1909 <bitWidth>1</bitWidth>
1910 </field>
1911 <field>
1912 <name>SWIER4</name>
1913 <description>Software Interrupt on line
1914 4</description>
1915 <bitOffset>4</bitOffset>
1916 <bitWidth>1</bitWidth>
1917 </field>
1918 <field>
1919 <name>SWIER5</name>
1920 <description>Software Interrupt on line
1921 5</description>
1922 <bitOffset>5</bitOffset>
1923 <bitWidth>1</bitWidth>
1924 </field>
1925 <field>
1926 <name>SWIER6</name>
1927 <description>Software Interrupt on line
1928 6</description>
1929 <bitOffset>6</bitOffset>
1930 <bitWidth>1</bitWidth>
1931 </field>
1932 <field>
1933 <name>SWIER7</name>
1934 <description>Software Interrupt on line
1935 7</description>
1936 <bitOffset>7</bitOffset>
1937 <bitWidth>1</bitWidth>
1938 </field>
1939 <field>
1940 <name>SWIER8</name>
1941 <description>Software Interrupt on line
1942 8</description>
1943 <bitOffset>8</bitOffset>
1944 <bitWidth>1</bitWidth>
1945 </field>
1946 <field>
1947 <name>SWIER9</name>
1948 <description>Software Interrupt on line
1949 9</description>
1950 <bitOffset>9</bitOffset>
1951 <bitWidth>1</bitWidth>
1952 </field>
1953 <field>
1954 <name>SWIER10</name>
1955 <description>Software Interrupt on line
1956 10</description>
1957 <bitOffset>10</bitOffset>
1958 <bitWidth>1</bitWidth>
1959 </field>
1960 <field>
1961 <name>SWIER11</name>
1962 <description>Software Interrupt on line
1963 11</description>
1964 <bitOffset>11</bitOffset>
1965 <bitWidth>1</bitWidth>
1966 </field>
1967 <field>
1968 <name>SWIER12</name>
1969 <description>Software Interrupt on line
1970 12</description>
1971 <bitOffset>12</bitOffset>
1972 <bitWidth>1</bitWidth>
1973 </field>
1974 <field>
1975 <name>SWIER13</name>
1976 <description>Software Interrupt on line
1977 13</description>
1978 <bitOffset>13</bitOffset>
1979 <bitWidth>1</bitWidth>
1980 </field>
1981 <field>
1982 <name>SWIER14</name>
1983 <description>Software Interrupt on line
1984 14</description>
1985 <bitOffset>14</bitOffset>
1986 <bitWidth>1</bitWidth>
1987 </field>
1988 <field>
1989 <name>SWIER15</name>
1990 <description>Software Interrupt on line
1991 15</description>
1992 <bitOffset>15</bitOffset>
1993 <bitWidth>1</bitWidth>
1994 </field>
1995 <field>
1996 <name>SWIER16</name>
1997 <description>Software Interrupt on line
1998 16</description>
1999 <bitOffset>16</bitOffset>
2000 <bitWidth>1</bitWidth>
2001 </field>
2002 <field>
2003 <name>SWIER17</name>
2004 <description>Software Interrupt on line
2005 17</description>
2006 <bitOffset>17</bitOffset>
2007 <bitWidth>1</bitWidth>
2008 </field>
2009 <field>
2010 <name>SWIER18</name>
2011 <description>Software Interrupt on line
2012 18</description>
2013 <bitOffset>18</bitOffset>
2014 <bitWidth>1</bitWidth>
2015 </field>
2016 <field>
2017 <name>SWIER19</name>
2018 <description>Software Interrupt on line
2019 19</description>
2020 <bitOffset>19</bitOffset>
2021 <bitWidth>1</bitWidth>
2022 </field>
2023 <field>
2024 <name>SWIER20</name>
2025 <description>Software Interrupt on line
2026 20</description>
2027 <bitOffset>20</bitOffset>
2028 <bitWidth>1</bitWidth>
2029 </field>
2030 <field>
2031 <name>SWIER21</name>
2032 <description>Software Interrupt on line
2033 21</description>
2034 <bitOffset>21</bitOffset>
2035 <bitWidth>1</bitWidth>
2036 </field>
2037 <field>
2038 <name>SWIER22</name>
2039 <description>Software Interrupt on line
2040 22</description>
2041 <bitOffset>22</bitOffset>
2042 <bitWidth>1</bitWidth>
2043 </field>
2044 </fields>
2045 </register>
2046 <register>
2047 <name>PR</name>
2048 <displayName>PR</displayName>
2049 <description>Pending register (EXTI_PR)</description>
2050 <addressOffset>0x14</addressOffset>
2051 <size>0x20</size>
2052 <access>read-write</access>
2053 <resetValue>0x00000000</resetValue>
2054 <fields>
2055 <field>
2056 <name>PR0</name>
2057 <description>Pending bit 0</description>
2058 <bitOffset>0</bitOffset>
2059 <bitWidth>1</bitWidth>
2060 </field>
2061 <field>
2062 <name>PR1</name>
2063 <description>Pending bit 1</description>
2064 <bitOffset>1</bitOffset>
2065 <bitWidth>1</bitWidth>
2066 </field>
2067 <field>
2068 <name>PR2</name>
2069 <description>Pending bit 2</description>
2070 <bitOffset>2</bitOffset>
2071 <bitWidth>1</bitWidth>
2072 </field>
2073 <field>
2074 <name>PR3</name>
2075 <description>Pending bit 3</description>
2076 <bitOffset>3</bitOffset>
2077 <bitWidth>1</bitWidth>
2078 </field>
2079 <field>
2080 <name>PR4</name>
2081 <description>Pending bit 4</description>
2082 <bitOffset>4</bitOffset>
2083 <bitWidth>1</bitWidth>
2084 </field>
2085 <field>
2086 <name>PR5</name>
2087 <description>Pending bit 5</description>
2088 <bitOffset>5</bitOffset>
2089 <bitWidth>1</bitWidth>
2090 </field>
2091 <field>
2092 <name>PR6</name>
2093 <description>Pending bit 6</description>
2094 <bitOffset>6</bitOffset>
2095 <bitWidth>1</bitWidth>
2096 </field>
2097 <field>
2098 <name>PR7</name>
2099 <description>Pending bit 7</description>
2100 <bitOffset>7</bitOffset>
2101 <bitWidth>1</bitWidth>
2102 </field>
2103 <field>
2104 <name>PR8</name>
2105 <description>Pending bit 8</description>
2106 <bitOffset>8</bitOffset>
2107 <bitWidth>1</bitWidth>
2108 </field>
2109 <field>
2110 <name>PR9</name>
2111 <description>Pending bit 9</description>
2112 <bitOffset>9</bitOffset>
2113 <bitWidth>1</bitWidth>
2114 </field>
2115 <field>
2116 <name>PR10</name>
2117 <description>Pending bit 10</description>
2118 <bitOffset>10</bitOffset>
2119 <bitWidth>1</bitWidth>
2120 </field>
2121 <field>
2122 <name>PR11</name>
2123 <description>Pending bit 11</description>
2124 <bitOffset>11</bitOffset>
2125 <bitWidth>1</bitWidth>
2126 </field>
2127 <field>
2128 <name>PR12</name>
2129 <description>Pending bit 12</description>
2130 <bitOffset>12</bitOffset>
2131 <bitWidth>1</bitWidth>
2132 </field>
2133 <field>
2134 <name>PR13</name>
2135 <description>Pending bit 13</description>
2136 <bitOffset>13</bitOffset>
2137 <bitWidth>1</bitWidth>
2138 </field>
2139 <field>
2140 <name>PR14</name>
2141 <description>Pending bit 14</description>
2142 <bitOffset>14</bitOffset>
2143 <bitWidth>1</bitWidth>
2144 </field>
2145 <field>
2146 <name>PR15</name>
2147 <description>Pending bit 15</description>
2148 <bitOffset>15</bitOffset>
2149 <bitWidth>1</bitWidth>
2150 </field>
2151 <field>
2152 <name>PR16</name>
2153 <description>Pending bit 16</description>
2154 <bitOffset>16</bitOffset>
2155 <bitWidth>1</bitWidth>
2156 </field>
2157 <field>
2158 <name>PR17</name>
2159 <description>Pending bit 17</description>
2160 <bitOffset>17</bitOffset>
2161 <bitWidth>1</bitWidth>
2162 </field>
2163 <field>
2164 <name>PR18</name>
2165 <description>Pending bit 18</description>
2166 <bitOffset>18</bitOffset>
2167 <bitWidth>1</bitWidth>
2168 </field>
2169 <field>
2170 <name>PR19</name>
2171 <description>Pending bit 19</description>
2172 <bitOffset>19</bitOffset>
2173 <bitWidth>1</bitWidth>
2174 </field>
2175 <field>
2176 <name>PR20</name>
2177 <description>Pending bit 20</description>
2178 <bitOffset>20</bitOffset>
2179 <bitWidth>1</bitWidth>
2180 </field>
2181 <field>
2182 <name>PR21</name>
2183 <description>Pending bit 21</description>
2184 <bitOffset>21</bitOffset>
2185 <bitWidth>1</bitWidth>
2186 </field>
2187 <field>
2188 <name>PR22</name>
2189 <description>Pending bit 22</description>
2190 <bitOffset>22</bitOffset>
2191 <bitWidth>1</bitWidth>
2192 </field>
2193 </fields>
2194 </register>
2195 </registers>
2196 </peripheral>
2197 <peripheral>
2198 <name>FLASH</name>
2199 <description>FLASH</description>
2200 <groupName>FLASH</groupName>
2201 <baseAddress>0x40023C00</baseAddress>
2202 <addressBlock>
2203 <offset>0x0</offset>
2204 <size>0x400</size>
2205 <usage>registers</usage>
2206 </addressBlock>
2207 <interrupt>
2208 <name>FLASH</name>
2209 <description>FLASH global interrupt</description>
2210 <value>4</value>
2211 </interrupt>
2212 <registers>
2213 <register>
2214 <name>ACR</name>
2215 <displayName>ACR</displayName>
2216 <description>Flash access control register</description>
2217 <addressOffset>0x0</addressOffset>
2218 <size>0x20</size>
2219 <resetValue>0x00000000</resetValue>
2220 <fields>
2221 <field>
2222 <name>LATENCY</name>
2223 <description>Latency</description>
2224 <bitOffset>0</bitOffset>
2225 <bitWidth>3</bitWidth>
2226 <access>read-write</access>
2227 </field>
2228 <field>
2229 <name>PRFTEN</name>
2230 <description>Prefetch enable</description>
2231 <bitOffset>8</bitOffset>
2232 <bitWidth>1</bitWidth>
2233 <access>read-write</access>
2234 </field>
2235 <field>
2236 <name>ICEN</name>
2237 <description>Instruction cache enable</description>
2238 <bitOffset>9</bitOffset>
2239 <bitWidth>1</bitWidth>
2240 <access>read-write</access>
2241 </field>
2242 <field>
2243 <name>DCEN</name>
2244 <description>Data cache enable</description>
2245 <bitOffset>10</bitOffset>
2246 <bitWidth>1</bitWidth>
2247 <access>read-write</access>
2248 </field>
2249 <field>
2250 <name>ICRST</name>
2251 <description>Instruction cache reset</description>
2252 <bitOffset>11</bitOffset>
2253 <bitWidth>1</bitWidth>
2254 <access>write-only</access>
2255 </field>
2256 <field>
2257 <name>DCRST</name>
2258 <description>Data cache reset</description>
2259 <bitOffset>12</bitOffset>
2260 <bitWidth>1</bitWidth>
2261 <access>read-write</access>
2262 </field>
2263 </fields>
2264 </register>
2265 <register>
2266 <name>KEYR</name>
2267 <displayName>KEYR</displayName>
2268 <description>Flash key register</description>
2269 <addressOffset>0x4</addressOffset>
2270 <size>0x20</size>
2271 <access>write-only</access>
2272 <resetValue>0x00000000</resetValue>
2273 <fields>
2274 <field>
2275 <name>KEY</name>
2276 <description>FPEC key</description>
2277 <bitOffset>0</bitOffset>
2278 <bitWidth>32</bitWidth>
2279 </field>
2280 </fields>
2281 </register>
2282 <register>
2283 <name>OPTKEYR</name>
2284 <displayName>OPTKEYR</displayName>
2285 <description>Flash option key register</description>
2286 <addressOffset>0x8</addressOffset>
2287 <size>0x20</size>
2288 <access>write-only</access>
2289 <resetValue>0x00000000</resetValue>
2290 <fields>
2291 <field>
2292 <name>OPTKEY</name>
2293 <description>Option byte key</description>
2294 <bitOffset>0</bitOffset>
2295 <bitWidth>32</bitWidth>
2296 </field>
2297 </fields>
2298 </register>
2299 <register>
2300 <name>SR</name>
2301 <displayName>SR</displayName>
2302 <description>Status register</description>
2303 <addressOffset>0xC</addressOffset>
2304 <size>0x20</size>
2305 <resetValue>0x00000000</resetValue>
2306 <fields>
2307 <field>
2308 <name>EOP</name>
2309 <description>End of operation</description>
2310 <bitOffset>0</bitOffset>
2311 <bitWidth>1</bitWidth>
2312 <access>read-write</access>
2313 </field>
2314 <field>
2315 <name>OPERR</name>
2316 <description>Operation error</description>
2317 <bitOffset>1</bitOffset>
2318 <bitWidth>1</bitWidth>
2319 <access>read-write</access>
2320 </field>
2321 <field>
2322 <name>WRPERR</name>
2323 <description>Write protection error</description>
2324 <bitOffset>4</bitOffset>
2325 <bitWidth>1</bitWidth>
2326 <access>read-write</access>
2327 </field>
2328 <field>
2329 <name>PGAERR</name>
2330 <description>Programming alignment
2331 error</description>
2332 <bitOffset>5</bitOffset>
2333 <bitWidth>1</bitWidth>
2334 <access>read-write</access>
2335 </field>
2336 <field>
2337 <name>PGPERR</name>
2338 <description>Programming parallelism
2339 error</description>
2340 <bitOffset>6</bitOffset>
2341 <bitWidth>1</bitWidth>
2342 <access>read-write</access>
2343 </field>
2344 <field>
2345 <name>PGSERR</name>
2346 <description>Programming sequence error</description>
2347 <bitOffset>7</bitOffset>
2348 <bitWidth>1</bitWidth>
2349 <access>read-write</access>
2350 </field>
2351 <field>
2352 <name>BSY</name>
2353 <description>Busy</description>
2354 <bitOffset>16</bitOffset>
2355 <bitWidth>1</bitWidth>
2356 <access>read-only</access>
2357 </field>
2358 </fields>
2359 </register>
2360 <register>
2361 <name>CR</name>
2362 <displayName>CR</displayName>
2363 <description>Control register</description>
2364 <addressOffset>0x10</addressOffset>
2365 <size>0x20</size>
2366 <access>read-write</access>
2367 <resetValue>0x80000000</resetValue>
2368 <fields>
2369 <field>
2370 <name>PG</name>
2371 <description>Programming</description>
2372 <bitOffset>0</bitOffset>
2373 <bitWidth>1</bitWidth>
2374 </field>
2375 <field>
2376 <name>SER</name>
2377 <description>Sector Erase</description>
2378 <bitOffset>1</bitOffset>
2379 <bitWidth>1</bitWidth>
2380 </field>
2381 <field>
2382 <name>MER</name>
2383 <description>Mass Erase</description>
2384 <bitOffset>2</bitOffset>
2385 <bitWidth>1</bitWidth>
2386 </field>
2387 <field>
2388 <name>SNB</name>
2389 <description>Sector number</description>
2390 <bitOffset>3</bitOffset>
2391 <bitWidth>4</bitWidth>
2392 </field>
2393 <field>
2394 <name>PSIZE</name>
2395 <description>Program size</description>
2396 <bitOffset>8</bitOffset>
2397 <bitWidth>2</bitWidth>
2398 </field>
2399 <field>
2400 <name>STRT</name>
2401 <description>Start</description>
2402 <bitOffset>16</bitOffset>
2403 <bitWidth>1</bitWidth>
2404 </field>
2405 <field>
2406 <name>EOPIE</name>
2407 <description>End of operation interrupt
2408 enable</description>
2409 <bitOffset>24</bitOffset>
2410 <bitWidth>1</bitWidth>
2411 </field>
2412 <field>
2413 <name>ERRIE</name>
2414 <description>Error interrupt enable</description>
2415 <bitOffset>25</bitOffset>
2416 <bitWidth>1</bitWidth>
2417 </field>
2418 <field>
2419 <name>LOCK</name>
2420 <description>Lock</description>
2421 <bitOffset>31</bitOffset>
2422 <bitWidth>1</bitWidth>
2423 </field>
2424 </fields>
2425 </register>
2426 <register>
2427 <name>OPTCR</name>
2428 <displayName>OPTCR</displayName>
2429 <description>Flash option control register</description>
2430 <addressOffset>0x14</addressOffset>
2431 <size>0x20</size>
2432 <access>read-write</access>
2433 <resetValue>0x00000014</resetValue>
2434 <fields>
2435 <field>
2436 <name>OPTLOCK</name>
2437 <description>Option lock</description>
2438 <bitOffset>0</bitOffset>
2439 <bitWidth>1</bitWidth>
2440 </field>
2441 <field>
2442 <name>OPTSTRT</name>
2443 <description>Option start</description>
2444 <bitOffset>1</bitOffset>
2445 <bitWidth>1</bitWidth>
2446 </field>
2447 <field>
2448 <name>BOR_LEV</name>
2449 <description>BOR reset Level</description>
2450 <bitOffset>2</bitOffset>
2451 <bitWidth>2</bitWidth>
2452 </field>
2453 <field>
2454 <name>WDG_SW</name>
2455 <description>WDG_SW User option bytes</description>
2456 <bitOffset>5</bitOffset>
2457 <bitWidth>1</bitWidth>
2458 </field>
2459 <field>
2460 <name>nRST_STOP</name>
2461 <description>nRST_STOP User option
2462 bytes</description>
2463 <bitOffset>6</bitOffset>
2464 <bitWidth>1</bitWidth>
2465 </field>
2466 <field>
2467 <name>nRST_STDBY</name>
2468 <description>nRST_STDBY User option
2469 bytes</description>
2470 <bitOffset>7</bitOffset>
2471 <bitWidth>1</bitWidth>
2472 </field>
2473 <field>
2474 <name>RDP</name>
2475 <description>Read protect</description>
2476 <bitOffset>8</bitOffset>
2477 <bitWidth>8</bitWidth>
2478 </field>
2479 <field>
2480 <name>nWRP</name>
2481 <description>Not write protect</description>
2482 <bitOffset>16</bitOffset>
2483 <bitWidth>12</bitWidth>
2484 </field>
2485 </fields>
2486 </register>
2487 </registers>
2488 </peripheral>
2489 <peripheral>
2490 <name>IWDG</name>
2491 <description>Independent watchdog</description>
2492 <groupName>IWDG</groupName>
2493 <baseAddress>0x40003000</baseAddress>
2494 <addressBlock>
2495 <offset>0x0</offset>
2496 <size>0x400</size>
2497 <usage>registers</usage>
2498 </addressBlock>
2499 <registers>
2500 <register>
2501 <name>KR</name>
2502 <displayName>KR</displayName>
2503 <description>Key register</description>
2504 <addressOffset>0x0</addressOffset>
2505 <size>0x20</size>
2506 <access>write-only</access>
2507 <resetValue>0x00000000</resetValue>
2508 <fields>
2509 <field>
2510 <name>KEY</name>
2511 <description>Key value</description>
2512 <bitOffset>0</bitOffset>
2513 <bitWidth>16</bitWidth>
2514 </field>
2515 </fields>
2516 </register>
2517 <register>
2518 <name>PR</name>
2519 <displayName>PR</displayName>
2520 <description>Prescaler register</description>
2521 <addressOffset>0x4</addressOffset>
2522 <size>0x20</size>
2523 <access>read-write</access>
2524 <resetValue>0x00000000</resetValue>
2525 <fields>
2526 <field>
2527 <name>PR</name>
2528 <description>Prescaler divider</description>
2529 <bitOffset>0</bitOffset>
2530 <bitWidth>3</bitWidth>
2531 </field>
2532 </fields>
2533 </register>
2534 <register>
2535 <name>RLR</name>
2536 <displayName>RLR</displayName>
2537 <description>Reload register</description>
2538 <addressOffset>0x8</addressOffset>
2539 <size>0x20</size>
2540 <access>read-write</access>
2541 <resetValue>0x00000FFF</resetValue>
2542 <fields>
2543 <field>
2544 <name>RL</name>
2545 <description>Watchdog counter reload
2546 value</description>
2547 <bitOffset>0</bitOffset>
2548 <bitWidth>12</bitWidth>
2549 </field>
2550 </fields>
2551 </register>
2552 <register>
2553 <name>SR</name>
2554 <displayName>SR</displayName>
2555 <description>Status register</description>
2556 <addressOffset>0xC</addressOffset>
2557 <size>0x20</size>
2558 <access>read-only</access>
2559 <resetValue>0x00000000</resetValue>
2560 <fields>
2561 <field>
2562 <name>RVU</name>
2563 <description>Watchdog counter reload value
2564 update</description>
2565 <bitOffset>1</bitOffset>
2566 <bitWidth>1</bitWidth>
2567 </field>
2568 <field>
2569 <name>PVU</name>
2570 <description>Watchdog prescaler value
2571 update</description>
2572 <bitOffset>0</bitOffset>
2573 <bitWidth>1</bitWidth>
2574 </field>
2575 </fields>
2576 </register>
2577 </registers>
2578 </peripheral>
2579 <peripheral>
2580 <name>OTG_FS_DEVICE</name>
2581 <description>USB on the go full speed</description>
2582 <groupName>USB_OTG_FS</groupName>
2583 <baseAddress>0x50000800</baseAddress>
2584 <addressBlock>
2585 <offset>0x0</offset>
2586 <size>0x400</size>
2587 <usage>registers</usage>
2588 </addressBlock>
2589 <registers>
2590 <register>
2591 <name>FS_DCFG</name>
2592 <displayName>FS_DCFG</displayName>
2593 <description>OTG_FS device configuration register
2594 (OTG_FS_DCFG)</description>
2595 <addressOffset>0x0</addressOffset>
2596 <size>0x20</size>
2597 <access>read-write</access>
2598 <resetValue>0x02200000</resetValue>
2599 <fields>
2600 <field>
2601 <name>DSPD</name>
2602 <description>Device speed</description>
2603 <bitOffset>0</bitOffset>
2604 <bitWidth>2</bitWidth>
2605 </field>
2606 <field>
2607 <name>NZLSOHSK</name>
2608 <description>Non-zero-length status OUT
2609 handshake</description>
2610 <bitOffset>2</bitOffset>
2611 <bitWidth>1</bitWidth>
2612 </field>
2613 <field>
2614 <name>DAD</name>
2615 <description>Device address</description>
2616 <bitOffset>4</bitOffset>
2617 <bitWidth>7</bitWidth>
2618 </field>
2619 <field>
2620 <name>PFIVL</name>
2621 <description>Periodic frame interval</description>
2622 <bitOffset>11</bitOffset>
2623 <bitWidth>2</bitWidth>
2624 </field>
2625 </fields>
2626 </register>
2627 <register>
2628 <name>FS_DCTL</name>
2629 <displayName>FS_DCTL</displayName>
2630 <description>OTG_FS device control register
2631 (OTG_FS_DCTL)</description>
2632 <addressOffset>0x4</addressOffset>
2633 <size>0x20</size>
2634 <resetValue>0x00000000</resetValue>
2635 <fields>
2636 <field>
2637 <name>RWUSIG</name>
2638 <description>Remote wakeup signaling</description>
2639 <bitOffset>0</bitOffset>
2640 <bitWidth>1</bitWidth>
2641 <access>read-write</access>
2642 </field>
2643 <field>
2644 <name>SDIS</name>
2645 <description>Soft disconnect</description>
2646 <bitOffset>1</bitOffset>
2647 <bitWidth>1</bitWidth>
2648 <access>read-write</access>
2649 </field>
2650 <field>
2651 <name>GINSTS</name>
2652 <description>Global IN NAK status</description>
2653 <bitOffset>2</bitOffset>
2654 <bitWidth>1</bitWidth>
2655 <access>read-only</access>
2656 </field>
2657 <field>
2658 <name>GONSTS</name>
2659 <description>Global OUT NAK status</description>
2660 <bitOffset>3</bitOffset>
2661 <bitWidth>1</bitWidth>
2662 <access>read-only</access>
2663 </field>
2664 <field>
2665 <name>TCTL</name>
2666 <description>Test control</description>
2667 <bitOffset>4</bitOffset>
2668 <bitWidth>3</bitWidth>
2669 <access>read-write</access>
2670 </field>
2671 <field>
2672 <name>SGINAK</name>
2673 <description>Set global IN NAK</description>
2674 <bitOffset>7</bitOffset>
2675 <bitWidth>1</bitWidth>
2676 <access>read-write</access>
2677 </field>
2678 <field>
2679 <name>CGINAK</name>
2680 <description>Clear global IN NAK</description>
2681 <bitOffset>8</bitOffset>
2682 <bitWidth>1</bitWidth>
2683 <access>read-write</access>
2684 </field>
2685 <field>
2686 <name>SGONAK</name>
2687 <description>Set global OUT NAK</description>
2688 <bitOffset>9</bitOffset>
2689 <bitWidth>1</bitWidth>
2690 <access>read-write</access>
2691 </field>
2692 <field>
2693 <name>CGONAK</name>
2694 <description>Clear global OUT NAK</description>
2695 <bitOffset>10</bitOffset>
2696 <bitWidth>1</bitWidth>
2697 <access>read-write</access>
2698 </field>
2699 <field>
2700 <name>POPRGDNE</name>
2701 <description>Power-on programming done</description>
2702 <bitOffset>11</bitOffset>
2703 <bitWidth>1</bitWidth>
2704 <access>read-write</access>
2705 </field>
2706 </fields>
2707 </register>
2708 <register>
2709 <name>FS_DSTS</name>
2710 <displayName>FS_DSTS</displayName>
2711 <description>OTG_FS device status register
2712 (OTG_FS_DSTS)</description>
2713 <addressOffset>0x8</addressOffset>
2714 <size>0x20</size>
2715 <access>read-only</access>
2716 <resetValue>0x00000010</resetValue>
2717 <fields>
2718 <field>
2719 <name>SUSPSTS</name>
2720 <description>Suspend status</description>
2721 <bitOffset>0</bitOffset>
2722 <bitWidth>1</bitWidth>
2723 </field>
2724 <field>
2725 <name>ENUMSPD</name>
2726 <description>Enumerated speed</description>
2727 <bitOffset>1</bitOffset>
2728 <bitWidth>2</bitWidth>
2729 </field>
2730 <field>
2731 <name>EERR</name>
2732 <description>Erratic error</description>
2733 <bitOffset>3</bitOffset>
2734 <bitWidth>1</bitWidth>
2735 </field>
2736 <field>
2737 <name>FNSOF</name>
2738 <description>Frame number of the received
2739 SOF</description>
2740 <bitOffset>8</bitOffset>
2741 <bitWidth>14</bitWidth>
2742 </field>
2743 </fields>
2744 </register>
2745 <register>
2746 <name>FS_DIEPMSK</name>
2747 <displayName>FS_DIEPMSK</displayName>
2748 <description>OTG_FS device IN endpoint common interrupt
2749 mask register (OTG_FS_DIEPMSK)</description>
2750 <addressOffset>0x10</addressOffset>
2751 <size>0x20</size>
2752 <access>read-write</access>
2753 <resetValue>0x00000000</resetValue>
2754 <fields>
2755 <field>
2756 <name>XFRCM</name>
2757 <description>Transfer completed interrupt
2758 mask</description>
2759 <bitOffset>0</bitOffset>
2760 <bitWidth>1</bitWidth>
2761 </field>
2762 <field>
2763 <name>EPDM</name>
2764 <description>Endpoint disabled interrupt
2765 mask</description>
2766 <bitOffset>1</bitOffset>
2767 <bitWidth>1</bitWidth>
2768 </field>
2769 <field>
2770 <name>TOM</name>
2771 <description>Timeout condition mask (Non-isochronous
2772 endpoints)</description>
2773 <bitOffset>3</bitOffset>
2774 <bitWidth>1</bitWidth>
2775 </field>
2776 <field>
2777 <name>ITTXFEMSK</name>
2778 <description>IN token received when TxFIFO empty
2779 mask</description>
2780 <bitOffset>4</bitOffset>
2781 <bitWidth>1</bitWidth>
2782 </field>
2783 <field>
2784 <name>INEPNMM</name>
2785 <description>IN token received with EP mismatch
2786 mask</description>
2787 <bitOffset>5</bitOffset>
2788 <bitWidth>1</bitWidth>
2789 </field>
2790 <field>
2791 <name>INEPNEM</name>
2792 <description>IN endpoint NAK effective
2793 mask</description>
2794 <bitOffset>6</bitOffset>
2795 <bitWidth>1</bitWidth>
2796 </field>
2797 </fields>
2798 </register>
2799 <register>
2800 <name>FS_DOEPMSK</name>
2801 <displayName>FS_DOEPMSK</displayName>
2802 <description>OTG_FS device OUT endpoint common interrupt
2803 mask register (OTG_FS_DOEPMSK)</description>
2804 <addressOffset>0x14</addressOffset>
2805 <size>0x20</size>
2806 <access>read-write</access>
2807 <resetValue>0x00000000</resetValue>
2808 <fields>
2809 <field>
2810 <name>XFRCM</name>
2811 <description>Transfer completed interrupt
2812 mask</description>
2813 <bitOffset>0</bitOffset>
2814 <bitWidth>1</bitWidth>
2815 </field>
2816 <field>
2817 <name>EPDM</name>
2818 <description>Endpoint disabled interrupt
2819 mask</description>
2820 <bitOffset>1</bitOffset>
2821 <bitWidth>1</bitWidth>
2822 </field>
2823 <field>
2824 <name>STUPM</name>
2825 <description>SETUP phase done mask</description>
2826 <bitOffset>3</bitOffset>
2827 <bitWidth>1</bitWidth>
2828 </field>
2829 <field>
2830 <name>OTEPDM</name>
2831 <description>OUT token received when endpoint
2832 disabled mask</description>
2833 <bitOffset>4</bitOffset>
2834 <bitWidth>1</bitWidth>
2835 </field>
2836 </fields>
2837 </register>
2838 <register>
2839 <name>FS_DAINT</name>
2840 <displayName>FS_DAINT</displayName>
2841 <description>OTG_FS device all endpoints interrupt
2842 register (OTG_FS_DAINT)</description>
2843 <addressOffset>0x18</addressOffset>
2844 <size>0x20</size>
2845 <access>read-only</access>
2846 <resetValue>0x00000000</resetValue>
2847 <fields>
2848 <field>
2849 <name>IEPINT</name>
2850 <description>IN endpoint interrupt bits</description>
2851 <bitOffset>0</bitOffset>
2852 <bitWidth>16</bitWidth>
2853 </field>
2854 <field>
2855 <name>OEPINT</name>
2856 <description>OUT endpoint interrupt
2857 bits</description>
2858 <bitOffset>16</bitOffset>
2859 <bitWidth>16</bitWidth>
2860 </field>
2861 </fields>
2862 </register>
2863 <register>
2864 <name>FS_DAINTMSK</name>
2865 <displayName>FS_DAINTMSK</displayName>
2866 <description>OTG_FS all endpoints interrupt mask register
2867 (OTG_FS_DAINTMSK)</description>
2868 <addressOffset>0x1C</addressOffset>
2869 <size>0x20</size>
2870 <access>read-write</access>
2871 <resetValue>0x00000000</resetValue>
2872 <fields>
2873 <field>
2874 <name>IEPM</name>
2875 <description>IN EP interrupt mask bits</description>
2876 <bitOffset>0</bitOffset>
2877 <bitWidth>16</bitWidth>
2878 </field>
2879 <field>
2880 <name>OEPINT</name>
2881 <description>OUT endpoint interrupt
2882 bits</description>
2883 <bitOffset>16</bitOffset>
2884 <bitWidth>16</bitWidth>
2885 </field>
2886 </fields>
2887 </register>
2888 <register>
2889 <name>DVBUSDIS</name>
2890 <displayName>DVBUSDIS</displayName>
2891 <description>OTG_FS device VBUS discharge time
2892 register</description>
2893 <addressOffset>0x28</addressOffset>
2894 <size>0x20</size>
2895 <access>read-write</access>
2896 <resetValue>0x000017D7</resetValue>
2897 <fields>
2898 <field>
2899 <name>VBUSDT</name>
2900 <description>Device VBUS discharge time</description>
2901 <bitOffset>0</bitOffset>
2902 <bitWidth>16</bitWidth>
2903 </field>
2904 </fields>
2905 </register>
2906 <register>
2907 <name>DVBUSPULSE</name>
2908 <displayName>DVBUSPULSE</displayName>
2909 <description>OTG_FS device VBUS pulsing time
2910 register</description>
2911 <addressOffset>0x2C</addressOffset>
2912 <size>0x20</size>
2913 <access>read-write</access>
2914 <resetValue>0x000005B8</resetValue>
2915 <fields>
2916 <field>
2917 <name>DVBUSP</name>
2918 <description>Device VBUS pulsing time</description>
2919 <bitOffset>0</bitOffset>
2920 <bitWidth>12</bitWidth>
2921 </field>
2922 </fields>
2923 </register>
2924 <register>
2925 <name>DIEPEMPMSK</name>
2926 <displayName>DIEPEMPMSK</displayName>
2927 <description>OTG_FS device IN endpoint FIFO empty
2928 interrupt mask register</description>
2929 <addressOffset>0x34</addressOffset>
2930 <size>0x20</size>
2931 <access>read-write</access>
2932 <resetValue>0x00000000</resetValue>
2933 <fields>
2934 <field>
2935 <name>INEPTXFEM</name>
2936 <description>IN EP Tx FIFO empty interrupt mask
2937 bits</description>
2938 <bitOffset>0</bitOffset>
2939 <bitWidth>16</bitWidth>
2940 </field>
2941 </fields>
2942 </register>
2943 <register>
2944 <name>FS_DIEPCTL0</name>
2945 <displayName>FS_DIEPCTL0</displayName>
2946 <description>OTG_FS device control IN endpoint 0 control
2947 register (OTG_FS_DIEPCTL0)</description>
2948 <addressOffset>0x100</addressOffset>
2949 <size>0x20</size>
2950 <resetValue>0x00000000</resetValue>
2951 <fields>
2952 <field>
2953 <name>MPSIZ</name>
2954 <description>Maximum packet size</description>
2955 <bitOffset>0</bitOffset>
2956 <bitWidth>2</bitWidth>
2957 <access>read-write</access>
2958 </field>
2959 <field>
2960 <name>USBAEP</name>
2961 <description>USB active endpoint</description>
2962 <bitOffset>15</bitOffset>
2963 <bitWidth>1</bitWidth>
2964 <access>read-only</access>
2965 </field>
2966 <field>
2967 <name>NAKSTS</name>
2968 <description>NAK status</description>
2969 <bitOffset>17</bitOffset>
2970 <bitWidth>1</bitWidth>
2971 <access>read-only</access>
2972 </field>
2973 <field>
2974 <name>EPTYP</name>
2975 <description>Endpoint type</description>
2976 <bitOffset>18</bitOffset>
2977 <bitWidth>2</bitWidth>
2978 <access>read-only</access>
2979 </field>
2980 <field>
2981 <name>STALL</name>
2982 <description>STALL handshake</description>
2983 <bitOffset>21</bitOffset>
2984 <bitWidth>1</bitWidth>
2985 <access>read-write</access>
2986 </field>
2987 <field>
2988 <name>TXFNUM</name>
2989 <description>TxFIFO number</description>
2990 <bitOffset>22</bitOffset>
2991 <bitWidth>4</bitWidth>
2992 <access>read-write</access>
2993 </field>
2994 <field>
2995 <name>CNAK</name>
2996 <description>Clear NAK</description>
2997 <bitOffset>26</bitOffset>
2998 <bitWidth>1</bitWidth>
2999 <access>write-only</access>
3000 </field>
3001 <field>
3002 <name>SNAK</name>
3003 <description>Set NAK</description>
3004 <bitOffset>27</bitOffset>
3005 <bitWidth>1</bitWidth>
3006 <access>write-only</access>
3007 </field>
3008 <field>
3009 <name>EPDIS</name>
3010 <description>Endpoint disable</description>
3011 <bitOffset>30</bitOffset>
3012 <bitWidth>1</bitWidth>
3013 <access>read-only</access>
3014 </field>
3015 <field>
3016 <name>EPENA</name>
3017 <description>Endpoint enable</description>
3018 <bitOffset>31</bitOffset>
3019 <bitWidth>1</bitWidth>
3020 <access>read-only</access>
3021 </field>
3022 </fields>
3023 </register>
3024 <register>
3025 <name>DIEPCTL1</name>
3026 <displayName>DIEPCTL1</displayName>
3027 <description>OTG device endpoint-1 control
3028 register</description>
3029 <addressOffset>0x120</addressOffset>
3030 <size>0x20</size>
3031 <resetValue>0x00000000</resetValue>
3032 <fields>
3033 <field>
3034 <name>EPENA</name>
3035 <description>EPENA</description>
3036 <bitOffset>31</bitOffset>
3037 <bitWidth>1</bitWidth>
3038 <access>read-write</access>
3039 </field>
3040 <field>
3041 <name>EPDIS</name>
3042 <description>EPDIS</description>
3043 <bitOffset>30</bitOffset>
3044 <bitWidth>1</bitWidth>
3045 <access>read-write</access>
3046 </field>
3047 <field>
3048 <name>SODDFRM_SD1PID</name>
3049 <description>SODDFRM/SD1PID</description>
3050 <bitOffset>29</bitOffset>
3051 <bitWidth>1</bitWidth>
3052 <access>write-only</access>
3053 </field>
3054 <field>
3055 <name>SD0PID_SEVNFRM</name>
3056 <description>SD0PID/SEVNFRM</description>
3057 <bitOffset>28</bitOffset>
3058 <bitWidth>1</bitWidth>
3059 <access>write-only</access>
3060 </field>
3061 <field>
3062 <name>SNAK</name>
3063 <description>SNAK</description>
3064 <bitOffset>27</bitOffset>
3065 <bitWidth>1</bitWidth>
3066 <access>write-only</access>
3067 </field>
3068 <field>
3069 <name>CNAK</name>
3070 <description>CNAK</description>
3071 <bitOffset>26</bitOffset>
3072 <bitWidth>1</bitWidth>
3073 <access>write-only</access>
3074 </field>
3075 <field>
3076 <name>TXFNUM</name>
3077 <description>TXFNUM</description>
3078 <bitOffset>22</bitOffset>
3079 <bitWidth>4</bitWidth>
3080 <access>read-write</access>
3081 </field>
3082 <field>
3083 <name>Stall</name>
3084 <description>Stall</description>
3085 <bitOffset>21</bitOffset>
3086 <bitWidth>1</bitWidth>
3087 <access>read-write</access>
3088 </field>
3089 <field>
3090 <name>EPTYP</name>
3091 <description>EPTYP</description>
3092 <bitOffset>18</bitOffset>
3093 <bitWidth>2</bitWidth>
3094 <access>read-write</access>
3095 </field>
3096 <field>
3097 <name>NAKSTS</name>
3098 <description>NAKSTS</description>
3099 <bitOffset>17</bitOffset>
3100 <bitWidth>1</bitWidth>
3101 <access>read-only</access>
3102 </field>
3103 <field>
3104 <name>EONUM_DPID</name>
3105 <description>EONUM/DPID</description>
3106 <bitOffset>16</bitOffset>
3107 <bitWidth>1</bitWidth>
3108 <access>read-only</access>
3109 </field>
3110 <field>
3111 <name>USBAEP</name>
3112 <description>USBAEP</description>
3113 <bitOffset>15</bitOffset>
3114 <bitWidth>1</bitWidth>
3115 <access>read-write</access>
3116 </field>
3117 <field>
3118 <name>MPSIZ</name>
3119 <description>MPSIZ</description>
3120 <bitOffset>0</bitOffset>
3121 <bitWidth>11</bitWidth>
3122 <access>read-write</access>
3123 </field>
3124 </fields>
3125 </register>
3126 <register>
3127 <name>DIEPCTL2</name>
3128 <displayName>DIEPCTL2</displayName>
3129 <description>OTG device endpoint-2 control
3130 register</description>
3131 <addressOffset>0x140</addressOffset>
3132 <size>0x20</size>
3133 <resetValue>0x00000000</resetValue>
3134 <fields>
3135 <field>
3136 <name>EPENA</name>
3137 <description>EPENA</description>
3138 <bitOffset>31</bitOffset>
3139 <bitWidth>1</bitWidth>
3140 <access>read-write</access>
3141 </field>
3142 <field>
3143 <name>EPDIS</name>
3144 <description>EPDIS</description>
3145 <bitOffset>30</bitOffset>
3146 <bitWidth>1</bitWidth>
3147 <access>read-write</access>
3148 </field>
3149 <field>
3150 <name>SODDFRM</name>
3151 <description>SODDFRM</description>
3152 <bitOffset>29</bitOffset>
3153 <bitWidth>1</bitWidth>
3154 <access>write-only</access>
3155 </field>
3156 <field>
3157 <name>SD0PID_SEVNFRM</name>
3158 <description>SD0PID/SEVNFRM</description>
3159 <bitOffset>28</bitOffset>
3160 <bitWidth>1</bitWidth>
3161 <access>write-only</access>
3162 </field>
3163 <field>
3164 <name>SNAK</name>
3165 <description>SNAK</description>
3166 <bitOffset>27</bitOffset>
3167 <bitWidth>1</bitWidth>
3168 <access>write-only</access>
3169 </field>
3170 <field>
3171 <name>CNAK</name>
3172 <description>CNAK</description>
3173 <bitOffset>26</bitOffset>
3174 <bitWidth>1</bitWidth>
3175 <access>write-only</access>
3176 </field>
3177 <field>
3178 <name>TXFNUM</name>
3179 <description>TXFNUM</description>
3180 <bitOffset>22</bitOffset>
3181 <bitWidth>4</bitWidth>
3182 <access>read-write</access>
3183 </field>
3184 <field>
3185 <name>Stall</name>
3186 <description>Stall</description>
3187 <bitOffset>21</bitOffset>
3188 <bitWidth>1</bitWidth>
3189 <access>read-write</access>
3190 </field>
3191 <field>
3192 <name>EPTYP</name>
3193 <description>EPTYP</description>
3194 <bitOffset>18</bitOffset>
3195 <bitWidth>2</bitWidth>
3196 <access>read-write</access>
3197 </field>
3198 <field>
3199 <name>NAKSTS</name>
3200 <description>NAKSTS</description>
3201 <bitOffset>17</bitOffset>
3202 <bitWidth>1</bitWidth>
3203 <access>read-only</access>
3204 </field>
3205 <field>
3206 <name>EONUM_DPID</name>
3207 <description>EONUM/DPID</description>
3208 <bitOffset>16</bitOffset>
3209 <bitWidth>1</bitWidth>
3210 <access>read-only</access>
3211 </field>
3212 <field>
3213 <name>USBAEP</name>
3214 <description>USBAEP</description>
3215 <bitOffset>15</bitOffset>
3216 <bitWidth>1</bitWidth>
3217 <access>read-write</access>
3218 </field>
3219 <field>
3220 <name>MPSIZ</name>
3221 <description>MPSIZ</description>
3222 <bitOffset>0</bitOffset>
3223 <bitWidth>11</bitWidth>
3224 <access>read-write</access>
3225 </field>
3226 </fields>
3227 </register>
3228 <register>
3229 <name>DIEPCTL3</name>
3230 <displayName>DIEPCTL3</displayName>
3231 <description>OTG device endpoint-3 control
3232 register</description>
3233 <addressOffset>0x160</addressOffset>
3234 <size>0x20</size>
3235 <resetValue>0x00000000</resetValue>
3236 <fields>
3237 <field>
3238 <name>EPENA</name>
3239 <description>EPENA</description>
3240 <bitOffset>31</bitOffset>
3241 <bitWidth>1</bitWidth>
3242 <access>read-write</access>
3243 </field>
3244 <field>
3245 <name>EPDIS</name>
3246 <description>EPDIS</description>
3247 <bitOffset>30</bitOffset>
3248 <bitWidth>1</bitWidth>
3249 <access>read-write</access>
3250 </field>
3251 <field>
3252 <name>SODDFRM</name>
3253 <description>SODDFRM</description>
3254 <bitOffset>29</bitOffset>
3255 <bitWidth>1</bitWidth>
3256 <access>write-only</access>
3257 </field>
3258 <field>
3259 <name>SD0PID_SEVNFRM</name>
3260 <description>SD0PID/SEVNFRM</description>
3261 <bitOffset>28</bitOffset>
3262 <bitWidth>1</bitWidth>
3263 <access>write-only</access>
3264 </field>
3265 <field>
3266 <name>SNAK</name>
3267 <description>SNAK</description>
3268 <bitOffset>27</bitOffset>
3269 <bitWidth>1</bitWidth>
3270 <access>write-only</access>
3271 </field>
3272 <field>
3273 <name>CNAK</name>
3274 <description>CNAK</description>
3275 <bitOffset>26</bitOffset>
3276 <bitWidth>1</bitWidth>
3277 <access>write-only</access>
3278 </field>
3279 <field>
3280 <name>TXFNUM</name>
3281 <description>TXFNUM</description>
3282 <bitOffset>22</bitOffset>
3283 <bitWidth>4</bitWidth>
3284 <access>read-write</access>
3285 </field>
3286 <field>
3287 <name>Stall</name>
3288 <description>Stall</description>
3289 <bitOffset>21</bitOffset>
3290 <bitWidth>1</bitWidth>
3291 <access>read-write</access>
3292 </field>
3293 <field>
3294 <name>EPTYP</name>
3295 <description>EPTYP</description>
3296 <bitOffset>18</bitOffset>
3297 <bitWidth>2</bitWidth>
3298 <access>read-write</access>
3299 </field>
3300 <field>
3301 <name>NAKSTS</name>
3302 <description>NAKSTS</description>
3303 <bitOffset>17</bitOffset>
3304 <bitWidth>1</bitWidth>
3305 <access>read-only</access>
3306 </field>
3307 <field>
3308 <name>EONUM_DPID</name>
3309 <description>EONUM/DPID</description>
3310 <bitOffset>16</bitOffset>
3311 <bitWidth>1</bitWidth>
3312 <access>read-only</access>
3313 </field>
3314 <field>
3315 <name>USBAEP</name>
3316 <description>USBAEP</description>
3317 <bitOffset>15</bitOffset>
3318 <bitWidth>1</bitWidth>
3319 <access>read-write</access>
3320 </field>
3321 <field>
3322 <name>MPSIZ</name>
3323 <description>MPSIZ</description>
3324 <bitOffset>0</bitOffset>
3325 <bitWidth>11</bitWidth>
3326 <access>read-write</access>
3327 </field>
3328 </fields>
3329 </register>
3330 <register>
3331 <name>DOEPCTL0</name>
3332 <displayName>DOEPCTL0</displayName>
3333 <description>device endpoint-0 control
3334 register</description>
3335 <addressOffset>0x300</addressOffset>
3336 <size>0x20</size>
3337 <resetValue>0x00008000</resetValue>
3338 <fields>
3339 <field>
3340 <name>EPENA</name>
3341 <description>EPENA</description>
3342 <bitOffset>31</bitOffset>
3343 <bitWidth>1</bitWidth>
3344 <access>write-only</access>
3345 </field>
3346 <field>
3347 <name>EPDIS</name>
3348 <description>EPDIS</description>
3349 <bitOffset>30</bitOffset>
3350 <bitWidth>1</bitWidth>
3351 <access>read-only</access>
3352 </field>
3353 <field>
3354 <name>SNAK</name>
3355 <description>SNAK</description>
3356 <bitOffset>27</bitOffset>
3357 <bitWidth>1</bitWidth>
3358 <access>write-only</access>
3359 </field>
3360 <field>
3361 <name>CNAK</name>
3362 <description>CNAK</description>
3363 <bitOffset>26</bitOffset>
3364 <bitWidth>1</bitWidth>
3365 <access>write-only</access>
3366 </field>
3367 <field>
3368 <name>Stall</name>
3369 <description>Stall</description>
3370 <bitOffset>21</bitOffset>
3371 <bitWidth>1</bitWidth>
3372 <access>read-write</access>
3373 </field>
3374 <field>
3375 <name>SNPM</name>
3376 <description>SNPM</description>
3377 <bitOffset>20</bitOffset>
3378 <bitWidth>1</bitWidth>
3379 <access>read-write</access>
3380 </field>
3381 <field>
3382 <name>EPTYP</name>
3383 <description>EPTYP</description>
3384 <bitOffset>18</bitOffset>
3385 <bitWidth>2</bitWidth>
3386 <access>read-only</access>
3387 </field>
3388 <field>
3389 <name>NAKSTS</name>
3390 <description>NAKSTS</description>
3391 <bitOffset>17</bitOffset>
3392 <bitWidth>1</bitWidth>
3393 <access>read-only</access>
3394 </field>
3395 <field>
3396 <name>USBAEP</name>
3397 <description>USBAEP</description>
3398 <bitOffset>15</bitOffset>
3399 <bitWidth>1</bitWidth>
3400 <access>read-only</access>
3401 </field>
3402 <field>
3403 <name>MPSIZ</name>
3404 <description>MPSIZ</description>
3405 <bitOffset>0</bitOffset>
3406 <bitWidth>2</bitWidth>
3407 <access>read-only</access>
3408 </field>
3409 </fields>
3410 </register>
3411 <register>
3412 <name>DOEPCTL1</name>
3413 <displayName>DOEPCTL1</displayName>
3414 <description>device endpoint-1 control
3415 register</description>
3416 <addressOffset>0x320</addressOffset>
3417 <size>0x20</size>
3418 <resetValue>0x00000000</resetValue>
3419 <fields>
3420 <field>
3421 <name>EPENA</name>
3422 <description>EPENA</description>
3423 <bitOffset>31</bitOffset>
3424 <bitWidth>1</bitWidth>
3425 <access>read-write</access>
3426 </field>
3427 <field>
3428 <name>EPDIS</name>
3429 <description>EPDIS</description>
3430 <bitOffset>30</bitOffset>
3431 <bitWidth>1</bitWidth>
3432 <access>read-write</access>
3433 </field>
3434 <field>
3435 <name>SODDFRM</name>
3436 <description>SODDFRM</description>
3437 <bitOffset>29</bitOffset>
3438 <bitWidth>1</bitWidth>
3439 <access>write-only</access>
3440 </field>
3441 <field>
3442 <name>SD0PID_SEVNFRM</name>
3443 <description>SD0PID/SEVNFRM</description>
3444 <bitOffset>28</bitOffset>
3445 <bitWidth>1</bitWidth>
3446 <access>write-only</access>
3447 </field>
3448 <field>
3449 <name>SNAK</name>
3450 <description>SNAK</description>
3451 <bitOffset>27</bitOffset>
3452 <bitWidth>1</bitWidth>
3453 <access>write-only</access>
3454 </field>
3455 <field>
3456 <name>CNAK</name>
3457 <description>CNAK</description>
3458 <bitOffset>26</bitOffset>
3459 <bitWidth>1</bitWidth>
3460 <access>write-only</access>
3461 </field>
3462 <field>
3463 <name>Stall</name>
3464 <description>Stall</description>
3465 <bitOffset>21</bitOffset>
3466 <bitWidth>1</bitWidth>
3467 <access>read-write</access>
3468 </field>
3469 <field>
3470 <name>SNPM</name>
3471 <description>SNPM</description>
3472 <bitOffset>20</bitOffset>
3473 <bitWidth>1</bitWidth>
3474 <access>read-write</access>
3475 </field>
3476 <field>
3477 <name>EPTYP</name>
3478 <description>EPTYP</description>
3479 <bitOffset>18</bitOffset>
3480 <bitWidth>2</bitWidth>
3481 <access>read-write</access>
3482 </field>
3483 <field>
3484 <name>NAKSTS</name>
3485 <description>NAKSTS</description>
3486 <bitOffset>17</bitOffset>
3487 <bitWidth>1</bitWidth>
3488 <access>read-only</access>
3489 </field>
3490 <field>
3491 <name>EONUM_DPID</name>
3492 <description>EONUM/DPID</description>
3493 <bitOffset>16</bitOffset>
3494 <bitWidth>1</bitWidth>
3495 <access>read-only</access>
3496 </field>
3497 <field>
3498 <name>USBAEP</name>
3499 <description>USBAEP</description>
3500 <bitOffset>15</bitOffset>
3501 <bitWidth>1</bitWidth>
3502 <access>read-write</access>
3503 </field>
3504 <field>
3505 <name>MPSIZ</name>
3506 <description>MPSIZ</description>
3507 <bitOffset>0</bitOffset>
3508 <bitWidth>11</bitWidth>
3509 <access>read-write</access>
3510 </field>
3511 </fields>
3512 </register>
3513 <register>
3514 <name>DOEPCTL2</name>
3515 <displayName>DOEPCTL2</displayName>
3516 <description>device endpoint-2 control
3517 register</description>
3518 <addressOffset>0x340</addressOffset>
3519 <size>0x20</size>
3520 <resetValue>0x00000000</resetValue>
3521 <fields>
3522 <field>
3523 <name>EPENA</name>
3524 <description>EPENA</description>
3525 <bitOffset>31</bitOffset>
3526 <bitWidth>1</bitWidth>
3527 <access>read-write</access>
3528 </field>
3529 <field>
3530 <name>EPDIS</name>
3531 <description>EPDIS</description>
3532 <bitOffset>30</bitOffset>
3533 <bitWidth>1</bitWidth>
3534 <access>read-write</access>
3535 </field>
3536 <field>
3537 <name>SODDFRM</name>
3538 <description>SODDFRM</description>
3539 <bitOffset>29</bitOffset>
3540 <bitWidth>1</bitWidth>
3541 <access>write-only</access>
3542 </field>
3543 <field>
3544 <name>SD0PID_SEVNFRM</name>
3545 <description>SD0PID/SEVNFRM</description>
3546 <bitOffset>28</bitOffset>
3547 <bitWidth>1</bitWidth>
3548 <access>write-only</access>
3549 </field>
3550 <field>
3551 <name>SNAK</name>
3552 <description>SNAK</description>
3553 <bitOffset>27</bitOffset>
3554 <bitWidth>1</bitWidth>
3555 <access>write-only</access>
3556 </field>
3557 <field>
3558 <name>CNAK</name>
3559 <description>CNAK</description>
3560 <bitOffset>26</bitOffset>
3561 <bitWidth>1</bitWidth>
3562 <access>write-only</access>
3563 </field>
3564 <field>
3565 <name>Stall</name>
3566 <description>Stall</description>
3567 <bitOffset>21</bitOffset>
3568 <bitWidth>1</bitWidth>
3569 <access>read-write</access>
3570 </field>
3571 <field>
3572 <name>SNPM</name>
3573 <description>SNPM</description>
3574 <bitOffset>20</bitOffset>
3575 <bitWidth>1</bitWidth>
3576 <access>read-write</access>
3577 </field>
3578 <field>
3579 <name>EPTYP</name>
3580 <description>EPTYP</description>
3581 <bitOffset>18</bitOffset>
3582 <bitWidth>2</bitWidth>
3583 <access>read-write</access>
3584 </field>
3585 <field>
3586 <name>NAKSTS</name>
3587 <description>NAKSTS</description>
3588 <bitOffset>17</bitOffset>
3589 <bitWidth>1</bitWidth>
3590 <access>read-only</access>
3591 </field>
3592 <field>
3593 <name>EONUM_DPID</name>
3594 <description>EONUM/DPID</description>
3595 <bitOffset>16</bitOffset>
3596 <bitWidth>1</bitWidth>
3597 <access>read-only</access>
3598 </field>
3599 <field>
3600 <name>USBAEP</name>
3601 <description>USBAEP</description>
3602 <bitOffset>15</bitOffset>
3603 <bitWidth>1</bitWidth>
3604 <access>read-write</access>
3605 </field>
3606 <field>
3607 <name>MPSIZ</name>
3608 <description>MPSIZ</description>
3609 <bitOffset>0</bitOffset>
3610 <bitWidth>11</bitWidth>
3611 <access>read-write</access>
3612 </field>
3613 </fields>
3614 </register>
3615 <register>
3616 <name>DOEPCTL3</name>
3617 <displayName>DOEPCTL3</displayName>
3618 <description>device endpoint-3 control
3619 register</description>
3620 <addressOffset>0x360</addressOffset>
3621 <size>0x20</size>
3622 <resetValue>0x00000000</resetValue>
3623 <fields>
3624 <field>
3625 <name>EPENA</name>
3626 <description>EPENA</description>
3627 <bitOffset>31</bitOffset>
3628 <bitWidth>1</bitWidth>
3629 <access>read-write</access>
3630 </field>
3631 <field>
3632 <name>EPDIS</name>
3633 <description>EPDIS</description>
3634 <bitOffset>30</bitOffset>
3635 <bitWidth>1</bitWidth>
3636 <access>read-write</access>
3637 </field>
3638 <field>
3639 <name>SODDFRM</name>
3640 <description>SODDFRM</description>
3641 <bitOffset>29</bitOffset>
3642 <bitWidth>1</bitWidth>
3643 <access>write-only</access>
3644 </field>
3645 <field>
3646 <name>SD0PID_SEVNFRM</name>
3647 <description>SD0PID/SEVNFRM</description>
3648 <bitOffset>28</bitOffset>
3649 <bitWidth>1</bitWidth>
3650 <access>write-only</access>
3651 </field>
3652 <field>
3653 <name>SNAK</name>
3654 <description>SNAK</description>
3655 <bitOffset>27</bitOffset>
3656 <bitWidth>1</bitWidth>
3657 <access>write-only</access>
3658 </field>
3659 <field>
3660 <name>CNAK</name>
3661 <description>CNAK</description>
3662 <bitOffset>26</bitOffset>
3663 <bitWidth>1</bitWidth>
3664 <access>write-only</access>
3665 </field>
3666 <field>
3667 <name>Stall</name>
3668 <description>Stall</description>
3669 <bitOffset>21</bitOffset>
3670 <bitWidth>1</bitWidth>
3671 <access>read-write</access>
3672 </field>
3673 <field>
3674 <name>SNPM</name>
3675 <description>SNPM</description>
3676 <bitOffset>20</bitOffset>
3677 <bitWidth>1</bitWidth>
3678 <access>read-write</access>
3679 </field>
3680 <field>
3681 <name>EPTYP</name>
3682 <description>EPTYP</description>
3683 <bitOffset>18</bitOffset>
3684 <bitWidth>2</bitWidth>
3685 <access>read-write</access>
3686 </field>
3687 <field>
3688 <name>NAKSTS</name>
3689 <description>NAKSTS</description>
3690 <bitOffset>17</bitOffset>
3691 <bitWidth>1</bitWidth>
3692 <access>read-only</access>
3693 </field>
3694 <field>
3695 <name>EONUM_DPID</name>
3696 <description>EONUM/DPID</description>
3697 <bitOffset>16</bitOffset>
3698 <bitWidth>1</bitWidth>
3699 <access>read-only</access>
3700 </field>
3701 <field>
3702 <name>USBAEP</name>
3703 <description>USBAEP</description>
3704 <bitOffset>15</bitOffset>
3705 <bitWidth>1</bitWidth>
3706 <access>read-write</access>
3707 </field>
3708 <field>
3709 <name>MPSIZ</name>
3710 <description>MPSIZ</description>
3711 <bitOffset>0</bitOffset>
3712 <bitWidth>11</bitWidth>
3713 <access>read-write</access>
3714 </field>
3715 </fields>
3716 </register>
3717 <register>
3718 <name>DIEPINT0</name>
3719 <displayName>DIEPINT0</displayName>
3720 <description>device endpoint-x interrupt
3721 register</description>
3722 <addressOffset>0x108</addressOffset>
3723 <size>0x20</size>
3724 <resetValue>0x00000080</resetValue>
3725 <fields>
3726 <field>
3727 <name>TXFE</name>
3728 <description>TXFE</description>
3729 <bitOffset>7</bitOffset>
3730 <bitWidth>1</bitWidth>
3731 <access>read-only</access>
3732 </field>
3733 <field>
3734 <name>INEPNE</name>
3735 <description>INEPNE</description>
3736 <bitOffset>6</bitOffset>
3737 <bitWidth>1</bitWidth>
3738 <access>read-write</access>
3739 </field>
3740 <field>
3741 <name>ITTXFE</name>
3742 <description>ITTXFE</description>
3743 <bitOffset>4</bitOffset>
3744 <bitWidth>1</bitWidth>
3745 <access>read-write</access>
3746 </field>
3747 <field>
3748 <name>TOC</name>
3749 <description>TOC</description>
3750 <bitOffset>3</bitOffset>
3751 <bitWidth>1</bitWidth>
3752 <access>read-write</access>
3753 </field>
3754 <field>
3755 <name>EPDISD</name>
3756 <description>EPDISD</description>
3757 <bitOffset>1</bitOffset>
3758 <bitWidth>1</bitWidth>
3759 <access>read-write</access>
3760 </field>
3761 <field>
3762 <name>XFRC</name>
3763 <description>XFRC</description>
3764 <bitOffset>0</bitOffset>
3765 <bitWidth>1</bitWidth>
3766 <access>read-write</access>
3767 </field>
3768 </fields>
3769 </register>
3770 <register>
3771 <name>DIEPINT1</name>
3772 <displayName>DIEPINT1</displayName>
3773 <description>device endpoint-1 interrupt
3774 register</description>
3775 <addressOffset>0x128</addressOffset>
3776 <size>0x20</size>
3777 <resetValue>0x00000080</resetValue>
3778 <fields>
3779 <field>
3780 <name>TXFE</name>
3781 <description>TXFE</description>
3782 <bitOffset>7</bitOffset>
3783 <bitWidth>1</bitWidth>
3784 <access>read-only</access>
3785 </field>
3786 <field>
3787 <name>INEPNE</name>
3788 <description>INEPNE</description>
3789 <bitOffset>6</bitOffset>
3790 <bitWidth>1</bitWidth>
3791 <access>read-write</access>
3792 </field>
3793 <field>
3794 <name>ITTXFE</name>
3795 <description>ITTXFE</description>
3796 <bitOffset>4</bitOffset>
3797 <bitWidth>1</bitWidth>
3798 <access>read-write</access>
3799 </field>
3800 <field>
3801 <name>TOC</name>
3802 <description>TOC</description>
3803 <bitOffset>3</bitOffset>
3804 <bitWidth>1</bitWidth>
3805 <access>read-write</access>
3806 </field>
3807 <field>
3808 <name>EPDISD</name>
3809 <description>EPDISD</description>
3810 <bitOffset>1</bitOffset>
3811 <bitWidth>1</bitWidth>
3812 <access>read-write</access>
3813 </field>
3814 <field>
3815 <name>XFRC</name>
3816 <description>XFRC</description>
3817 <bitOffset>0</bitOffset>
3818 <bitWidth>1</bitWidth>
3819 <access>read-write</access>
3820 </field>
3821 </fields>
3822 </register>
3823 <register>
3824 <name>DIEPINT2</name>
3825 <displayName>DIEPINT2</displayName>
3826 <description>device endpoint-2 interrupt
3827 register</description>
3828 <addressOffset>0x148</addressOffset>
3829 <size>0x20</size>
3830 <resetValue>0x00000080</resetValue>
3831 <fields>
3832 <field>
3833 <name>TXFE</name>
3834 <description>TXFE</description>
3835 <bitOffset>7</bitOffset>
3836 <bitWidth>1</bitWidth>
3837 <access>read-only</access>
3838 </field>
3839 <field>
3840 <name>INEPNE</name>
3841 <description>INEPNE</description>
3842 <bitOffset>6</bitOffset>
3843 <bitWidth>1</bitWidth>
3844 <access>read-write</access>
3845 </field>
3846 <field>
3847 <name>ITTXFE</name>
3848 <description>ITTXFE</description>
3849 <bitOffset>4</bitOffset>
3850 <bitWidth>1</bitWidth>
3851 <access>read-write</access>
3852 </field>
3853 <field>
3854 <name>TOC</name>
3855 <description>TOC</description>
3856 <bitOffset>3</bitOffset>
3857 <bitWidth>1</bitWidth>
3858 <access>read-write</access>
3859 </field>
3860 <field>
3861 <name>EPDISD</name>
3862 <description>EPDISD</description>
3863 <bitOffset>1</bitOffset>
3864 <bitWidth>1</bitWidth>
3865 <access>read-write</access>
3866 </field>
3867 <field>
3868 <name>XFRC</name>
3869 <description>XFRC</description>
3870 <bitOffset>0</bitOffset>
3871 <bitWidth>1</bitWidth>
3872 <access>read-write</access>
3873 </field>
3874 </fields>
3875 </register>
3876 <register>
3877 <name>DIEPINT3</name>
3878 <displayName>DIEPINT3</displayName>
3879 <description>device endpoint-3 interrupt
3880 register</description>
3881 <addressOffset>0x168</addressOffset>
3882 <size>0x20</size>
3883 <resetValue>0x00000080</resetValue>
3884 <fields>
3885 <field>
3886 <name>TXFE</name>
3887 <description>TXFE</description>
3888 <bitOffset>7</bitOffset>
3889 <bitWidth>1</bitWidth>
3890 <access>read-only</access>
3891 </field>
3892 <field>
3893 <name>INEPNE</name>
3894 <description>INEPNE</description>
3895 <bitOffset>6</bitOffset>
3896 <bitWidth>1</bitWidth>
3897 <access>read-write</access>
3898 </field>
3899 <field>
3900 <name>ITTXFE</name>
3901 <description>ITTXFE</description>
3902 <bitOffset>4</bitOffset>
3903 <bitWidth>1</bitWidth>
3904 <access>read-write</access>
3905 </field>
3906 <field>
3907 <name>TOC</name>
3908 <description>TOC</description>
3909 <bitOffset>3</bitOffset>
3910 <bitWidth>1</bitWidth>
3911 <access>read-write</access>
3912 </field>
3913 <field>
3914 <name>EPDISD</name>
3915 <description>EPDISD</description>
3916 <bitOffset>1</bitOffset>
3917 <bitWidth>1</bitWidth>
3918 <access>read-write</access>
3919 </field>
3920 <field>
3921 <name>XFRC</name>
3922 <description>XFRC</description>
3923 <bitOffset>0</bitOffset>
3924 <bitWidth>1</bitWidth>
3925 <access>read-write</access>
3926 </field>
3927 </fields>
3928 </register>
3929 <register>
3930 <name>DOEPINT0</name>
3931 <displayName>DOEPINT0</displayName>
3932 <description>device endpoint-0 interrupt
3933 register</description>
3934 <addressOffset>0x308</addressOffset>
3935 <size>0x20</size>
3936 <access>read-write</access>
3937 <resetValue>0x00000080</resetValue>
3938 <fields>
3939 <field>
3940 <name>B2BSTUP</name>
3941 <description>B2BSTUP</description>
3942 <bitOffset>6</bitOffset>
3943 <bitWidth>1</bitWidth>
3944 </field>
3945 <field>
3946 <name>OTEPDIS</name>
3947 <description>OTEPDIS</description>
3948 <bitOffset>4</bitOffset>
3949 <bitWidth>1</bitWidth>
3950 </field>
3951 <field>
3952 <name>STUP</name>
3953 <description>STUP</description>
3954 <bitOffset>3</bitOffset>
3955 <bitWidth>1</bitWidth>
3956 </field>
3957 <field>
3958 <name>EPDISD</name>
3959 <description>EPDISD</description>
3960 <bitOffset>1</bitOffset>
3961 <bitWidth>1</bitWidth>
3962 </field>
3963 <field>
3964 <name>XFRC</name>
3965 <description>XFRC</description>
3966 <bitOffset>0</bitOffset>
3967 <bitWidth>1</bitWidth>
3968 </field>
3969 </fields>
3970 </register>
3971 <register>
3972 <name>DOEPINT1</name>
3973 <displayName>DOEPINT1</displayName>
3974 <description>device endpoint-1 interrupt
3975 register</description>
3976 <addressOffset>0x328</addressOffset>
3977 <size>0x20</size>
3978 <access>read-write</access>
3979 <resetValue>0x00000080</resetValue>
3980 <fields>
3981 <field>
3982 <name>B2BSTUP</name>
3983 <description>B2BSTUP</description>
3984 <bitOffset>6</bitOffset>
3985 <bitWidth>1</bitWidth>
3986 </field>
3987 <field>
3988 <name>OTEPDIS</name>
3989 <description>OTEPDIS</description>
3990 <bitOffset>4</bitOffset>
3991 <bitWidth>1</bitWidth>
3992 </field>
3993 <field>
3994 <name>STUP</name>
3995 <description>STUP</description>
3996 <bitOffset>3</bitOffset>
3997 <bitWidth>1</bitWidth>
3998 </field>
3999 <field>
4000 <name>EPDISD</name>
4001 <description>EPDISD</description>
4002 <bitOffset>1</bitOffset>
4003 <bitWidth>1</bitWidth>
4004 </field>
4005 <field>
4006 <name>XFRC</name>
4007 <description>XFRC</description>
4008 <bitOffset>0</bitOffset>
4009 <bitWidth>1</bitWidth>
4010 </field>
4011 </fields>
4012 </register>
4013 <register>
4014 <name>DOEPINT2</name>
4015 <displayName>DOEPINT2</displayName>
4016 <description>device endpoint-2 interrupt
4017 register</description>
4018 <addressOffset>0x348</addressOffset>
4019 <size>0x20</size>
4020 <access>read-write</access>
4021 <resetValue>0x00000080</resetValue>
4022 <fields>
4023 <field>
4024 <name>B2BSTUP</name>
4025 <description>B2BSTUP</description>
4026 <bitOffset>6</bitOffset>
4027 <bitWidth>1</bitWidth>
4028 </field>
4029 <field>
4030 <name>OTEPDIS</name>
4031 <description>OTEPDIS</description>
4032 <bitOffset>4</bitOffset>
4033 <bitWidth>1</bitWidth>
4034 </field>
4035 <field>
4036 <name>STUP</name>
4037 <description>STUP</description>
4038 <bitOffset>3</bitOffset>
4039 <bitWidth>1</bitWidth>
4040 </field>
4041 <field>
4042 <name>EPDISD</name>
4043 <description>EPDISD</description>
4044 <bitOffset>1</bitOffset>
4045 <bitWidth>1</bitWidth>
4046 </field>
4047 <field>
4048 <name>XFRC</name>
4049 <description>XFRC</description>
4050 <bitOffset>0</bitOffset>
4051 <bitWidth>1</bitWidth>
4052 </field>
4053 </fields>
4054 </register>
4055 <register>
4056 <name>DOEPINT3</name>
4057 <displayName>DOEPINT3</displayName>
4058 <description>device endpoint-3 interrupt
4059 register</description>
4060 <addressOffset>0x368</addressOffset>
4061 <size>0x20</size>
4062 <access>read-write</access>
4063 <resetValue>0x00000080</resetValue>
4064 <fields>
4065 <field>
4066 <name>B2BSTUP</name>
4067 <description>B2BSTUP</description>
4068 <bitOffset>6</bitOffset>
4069 <bitWidth>1</bitWidth>
4070 </field>
4071 <field>
4072 <name>OTEPDIS</name>
4073 <description>OTEPDIS</description>
4074 <bitOffset>4</bitOffset>
4075 <bitWidth>1</bitWidth>
4076 </field>
4077 <field>
4078 <name>STUP</name>
4079 <description>STUP</description>
4080 <bitOffset>3</bitOffset>
4081 <bitWidth>1</bitWidth>
4082 </field>
4083 <field>
4084 <name>EPDISD</name>
4085 <description>EPDISD</description>
4086 <bitOffset>1</bitOffset>
4087 <bitWidth>1</bitWidth>
4088 </field>
4089 <field>
4090 <name>XFRC</name>
4091 <description>XFRC</description>
4092 <bitOffset>0</bitOffset>
4093 <bitWidth>1</bitWidth>
4094 </field>
4095 </fields>
4096 </register>
4097 <register>
4098 <name>DIEPTSIZ0</name>
4099 <displayName>DIEPTSIZ0</displayName>
4100 <description>device endpoint-0 transfer size
4101 register</description>
4102 <addressOffset>0x110</addressOffset>
4103 <size>0x20</size>
4104 <access>read-write</access>
4105 <resetValue>0x00000000</resetValue>
4106 <fields>
4107 <field>
4108 <name>PKTCNT</name>
4109 <description>Packet count</description>
4110 <bitOffset>19</bitOffset>
4111 <bitWidth>2</bitWidth>
4112 </field>
4113 <field>
4114 <name>XFRSIZ</name>
4115 <description>Transfer size</description>
4116 <bitOffset>0</bitOffset>
4117 <bitWidth>7</bitWidth>
4118 </field>
4119 </fields>
4120 </register>
4121 <register>
4122 <name>DOEPTSIZ0</name>
4123 <displayName>DOEPTSIZ0</displayName>
4124 <description>device OUT endpoint-0 transfer size
4125 register</description>
4126 <addressOffset>0x310</addressOffset>
4127 <size>0x20</size>
4128 <access>read-write</access>
4129 <resetValue>0x00000000</resetValue>
4130 <fields>
4131 <field>
4132 <name>STUPCNT</name>
4133 <description>SETUP packet count</description>
4134 <bitOffset>29</bitOffset>
4135 <bitWidth>2</bitWidth>
4136 </field>
4137 <field>
4138 <name>PKTCNT</name>
4139 <description>Packet count</description>
4140 <bitOffset>19</bitOffset>
4141 <bitWidth>1</bitWidth>
4142 </field>
4143 <field>
4144 <name>XFRSIZ</name>
4145 <description>Transfer size</description>
4146 <bitOffset>0</bitOffset>
4147 <bitWidth>7</bitWidth>
4148 </field>
4149 </fields>
4150 </register>
4151 <register>
4152 <name>DIEPTSIZ1</name>
4153 <displayName>DIEPTSIZ1</displayName>
4154 <description>device endpoint-1 transfer size
4155 register</description>
4156 <addressOffset>0x130</addressOffset>
4157 <size>0x20</size>
4158 <access>read-write</access>
4159 <resetValue>0x00000000</resetValue>
4160 <fields>
4161 <field>
4162 <name>MCNT</name>
4163 <description>Multi count</description>
4164 <bitOffset>29</bitOffset>
4165 <bitWidth>2</bitWidth>
4166 </field>
4167 <field>
4168 <name>PKTCNT</name>
4169 <description>Packet count</description>
4170 <bitOffset>19</bitOffset>
4171 <bitWidth>10</bitWidth>
4172 </field>
4173 <field>
4174 <name>XFRSIZ</name>
4175 <description>Transfer size</description>
4176 <bitOffset>0</bitOffset>
4177 <bitWidth>19</bitWidth>
4178 </field>
4179 </fields>
4180 </register>
4181 <register>
4182 <name>DIEPTSIZ2</name>
4183 <displayName>DIEPTSIZ2</displayName>
4184 <description>device endpoint-2 transfer size
4185 register</description>
4186 <addressOffset>0x150</addressOffset>
4187 <size>0x20</size>
4188 <access>read-write</access>
4189 <resetValue>0x00000000</resetValue>
4190 <fields>
4191 <field>
4192 <name>MCNT</name>
4193 <description>Multi count</description>
4194 <bitOffset>29</bitOffset>
4195 <bitWidth>2</bitWidth>
4196 </field>
4197 <field>
4198 <name>PKTCNT</name>
4199 <description>Packet count</description>
4200 <bitOffset>19</bitOffset>
4201 <bitWidth>10</bitWidth>
4202 </field>
4203 <field>
4204 <name>XFRSIZ</name>
4205 <description>Transfer size</description>
4206 <bitOffset>0</bitOffset>
4207 <bitWidth>19</bitWidth>
4208 </field>
4209 </fields>
4210 </register>
4211 <register>
4212 <name>DIEPTSIZ3</name>
4213 <displayName>DIEPTSIZ3</displayName>
4214 <description>device endpoint-3 transfer size
4215 register</description>
4216 <addressOffset>0x170</addressOffset>
4217 <size>0x20</size>
4218 <access>read-write</access>
4219 <resetValue>0x00000000</resetValue>
4220 <fields>
4221 <field>
4222 <name>MCNT</name>
4223 <description>Multi count</description>
4224 <bitOffset>29</bitOffset>
4225 <bitWidth>2</bitWidth>
4226 </field>
4227 <field>
4228 <name>PKTCNT</name>
4229 <description>Packet count</description>
4230 <bitOffset>19</bitOffset>
4231 <bitWidth>10</bitWidth>
4232 </field>
4233 <field>
4234 <name>XFRSIZ</name>
4235 <description>Transfer size</description>
4236 <bitOffset>0</bitOffset>
4237 <bitWidth>19</bitWidth>
4238 </field>
4239 </fields>
4240 </register>
4241 <register>
4242 <name>DTXFSTS0</name>
4243 <displayName>DTXFSTS0</displayName>
4244 <description>OTG_FS device IN endpoint transmit FIFO
4245 status register</description>
4246 <addressOffset>0x118</addressOffset>
4247 <size>0x20</size>
4248 <access>read-only</access>
4249 <resetValue>0x00000000</resetValue>
4250 <fields>
4251 <field>
4252 <name>INEPTFSAV</name>
4253 <description>IN endpoint TxFIFO space
4254 available</description>
4255 <bitOffset>0</bitOffset>
4256 <bitWidth>16</bitWidth>
4257 </field>
4258 </fields>
4259 </register>
4260 <register>
4261 <name>DTXFSTS1</name>
4262 <displayName>DTXFSTS1</displayName>
4263 <description>OTG_FS device IN endpoint transmit FIFO
4264 status register</description>
4265 <addressOffset>0x138</addressOffset>
4266 <size>0x20</size>
4267 <access>read-only</access>
4268 <resetValue>0x00000000</resetValue>
4269 <fields>
4270 <field>
4271 <name>INEPTFSAV</name>
4272 <description>IN endpoint TxFIFO space
4273 available</description>
4274 <bitOffset>0</bitOffset>
4275 <bitWidth>16</bitWidth>
4276 </field>
4277 </fields>
4278 </register>
4279 <register>
4280 <name>DTXFSTS2</name>
4281 <displayName>DTXFSTS2</displayName>
4282 <description>OTG_FS device IN endpoint transmit FIFO
4283 status register</description>
4284 <addressOffset>0x158</addressOffset>
4285 <size>0x20</size>
4286 <access>read-only</access>
4287 <resetValue>0x00000000</resetValue>
4288 <fields>
4289 <field>
4290 <name>INEPTFSAV</name>
4291 <description>IN endpoint TxFIFO space
4292 available</description>
4293 <bitOffset>0</bitOffset>
4294 <bitWidth>16</bitWidth>
4295 </field>
4296 </fields>
4297 </register>
4298 <register>
4299 <name>DTXFSTS3</name>
4300 <displayName>DTXFSTS3</displayName>
4301 <description>OTG_FS device IN endpoint transmit FIFO
4302 status register</description>
4303 <addressOffset>0x178</addressOffset>
4304 <size>0x20</size>
4305 <access>read-only</access>
4306 <resetValue>0x00000000</resetValue>
4307 <fields>
4308 <field>
4309 <name>INEPTFSAV</name>
4310 <description>IN endpoint TxFIFO space
4311 available</description>
4312 <bitOffset>0</bitOffset>
4313 <bitWidth>16</bitWidth>
4314 </field>
4315 </fields>
4316 </register>
4317 <register>
4318 <name>DOEPTSIZ1</name>
4319 <displayName>DOEPTSIZ1</displayName>
4320 <description>device OUT endpoint-1 transfer size
4321 register</description>
4322 <addressOffset>0x330</addressOffset>
4323 <size>0x20</size>
4324 <access>read-write</access>
4325 <resetValue>0x00000000</resetValue>
4326 <fields>
4327 <field>
4328 <name>RXDPID_STUPCNT</name>
4329 <description>Received data PID/SETUP packet
4330 count</description>
4331 <bitOffset>29</bitOffset>
4332 <bitWidth>2</bitWidth>
4333 </field>
4334 <field>
4335 <name>PKTCNT</name>
4336 <description>Packet count</description>
4337 <bitOffset>19</bitOffset>
4338 <bitWidth>10</bitWidth>
4339 </field>
4340 <field>
4341 <name>XFRSIZ</name>
4342 <description>Transfer size</description>
4343 <bitOffset>0</bitOffset>
4344 <bitWidth>19</bitWidth>
4345 </field>
4346 </fields>
4347 </register>
4348 <register>
4349 <name>DOEPTSIZ2</name>
4350 <displayName>DOEPTSIZ2</displayName>
4351 <description>device OUT endpoint-2 transfer size
4352 register</description>
4353 <addressOffset>0x350</addressOffset>
4354 <size>0x20</size>
4355 <access>read-write</access>
4356 <resetValue>0x00000000</resetValue>
4357 <fields>
4358 <field>
4359 <name>RXDPID_STUPCNT</name>
4360 <description>Received data PID/SETUP packet
4361 count</description>
4362 <bitOffset>29</bitOffset>
4363 <bitWidth>2</bitWidth>
4364 </field>
4365 <field>
4366 <name>PKTCNT</name>
4367 <description>Packet count</description>
4368 <bitOffset>19</bitOffset>
4369 <bitWidth>10</bitWidth>
4370 </field>
4371 <field>
4372 <name>XFRSIZ</name>
4373 <description>Transfer size</description>
4374 <bitOffset>0</bitOffset>
4375 <bitWidth>19</bitWidth>
4376 </field>
4377 </fields>
4378 </register>
4379 <register>
4380 <name>DOEPTSIZ3</name>
4381 <displayName>DOEPTSIZ3</displayName>
4382 <description>device OUT endpoint-3 transfer size
4383 register</description>
4384 <addressOffset>0x370</addressOffset>
4385 <size>0x20</size>
4386 <access>read-write</access>
4387 <resetValue>0x00000000</resetValue>
4388 <fields>
4389 <field>
4390 <name>RXDPID_STUPCNT</name>
4391 <description>Received data PID/SETUP packet
4392 count</description>
4393 <bitOffset>29</bitOffset>
4394 <bitWidth>2</bitWidth>
4395 </field>
4396 <field>
4397 <name>PKTCNT</name>
4398 <description>Packet count</description>
4399 <bitOffset>19</bitOffset>
4400 <bitWidth>10</bitWidth>
4401 </field>
4402 <field>
4403 <name>XFRSIZ</name>
4404 <description>Transfer size</description>
4405 <bitOffset>0</bitOffset>
4406 <bitWidth>19</bitWidth>
4407 </field>
4408 </fields>
4409 </register>
4410 </registers>
4411 </peripheral>
4412 <peripheral>
4413 <name>OTG_FS_GLOBAL</name>
4414 <description>USB on the go full speed</description>
4415 <groupName>USB_OTG_FS</groupName>
4416 <baseAddress>0x50000000</baseAddress>
4417 <addressBlock>
4418 <offset>0x0</offset>
4419 <size>0x400</size>
4420 <usage>registers</usage>
4421 </addressBlock>
4422 <registers>
4423 <register>
4424 <name>FS_GOTGCTL</name>
4425 <displayName>FS_GOTGCTL</displayName>
4426 <description>OTG_FS control and status register
4427 (OTG_FS_GOTGCTL)</description>
4428 <addressOffset>0x0</addressOffset>
4429 <size>0x20</size>
4430 <resetValue>0x00000800</resetValue>
4431 <fields>
4432 <field>
4433 <name>SRQSCS</name>
4434 <description>Session request success</description>
4435 <bitOffset>0</bitOffset>
4436 <bitWidth>1</bitWidth>
4437 <access>read-only</access>
4438 </field>
4439 <field>
4440 <name>SRQ</name>
4441 <description>Session request</description>
4442 <bitOffset>1</bitOffset>
4443 <bitWidth>1</bitWidth>
4444 <access>read-write</access>
4445 </field>
4446 <field>
4447 <name>HNGSCS</name>
4448 <description>Host negotiation success</description>
4449 <bitOffset>8</bitOffset>
4450 <bitWidth>1</bitWidth>
4451 <access>read-only</access>
4452 </field>
4453 <field>
4454 <name>HNPRQ</name>
4455 <description>HNP request</description>
4456 <bitOffset>9</bitOffset>
4457 <bitWidth>1</bitWidth>
4458 <access>read-write</access>
4459 </field>
4460 <field>
4461 <name>HSHNPEN</name>
4462 <description>Host set HNP enable</description>
4463 <bitOffset>10</bitOffset>
4464 <bitWidth>1</bitWidth>
4465 <access>read-write</access>
4466 </field>
4467 <field>
4468 <name>DHNPEN</name>
4469 <description>Device HNP enabled</description>
4470 <bitOffset>11</bitOffset>
4471 <bitWidth>1</bitWidth>
4472 <access>read-write</access>
4473 </field>
4474 <field>
4475 <name>CIDSTS</name>
4476 <description>Connector ID status</description>
4477 <bitOffset>16</bitOffset>
4478 <bitWidth>1</bitWidth>
4479 <access>read-only</access>
4480 </field>
4481 <field>
4482 <name>DBCT</name>
4483 <description>Long/short debounce time</description>
4484 <bitOffset>17</bitOffset>
4485 <bitWidth>1</bitWidth>
4486 <access>read-only</access>
4487 </field>
4488 <field>
4489 <name>ASVLD</name>
4490 <description>A-session valid</description>
4491 <bitOffset>18</bitOffset>
4492 <bitWidth>1</bitWidth>
4493 <access>read-only</access>
4494 </field>
4495 <field>
4496 <name>BSVLD</name>
4497 <description>B-session valid</description>
4498 <bitOffset>19</bitOffset>
4499 <bitWidth>1</bitWidth>
4500 <access>read-only</access>
4501 </field>
4502 </fields>
4503 </register>
4504 <register>
4505 <name>FS_GOTGINT</name>
4506 <displayName>FS_GOTGINT</displayName>
4507 <description>OTG_FS interrupt register
4508 (OTG_FS_GOTGINT)</description>
4509 <addressOffset>0x4</addressOffset>
4510 <size>0x20</size>
4511 <access>read-write</access>
4512 <resetValue>0x00000000</resetValue>
4513 <fields>
4514 <field>
4515 <name>SEDET</name>
4516 <description>Session end detected</description>
4517 <bitOffset>2</bitOffset>
4518 <bitWidth>1</bitWidth>
4519 </field>
4520 <field>
4521 <name>SRSSCHG</name>
4522 <description>Session request success status
4523 change</description>
4524 <bitOffset>8</bitOffset>
4525 <bitWidth>1</bitWidth>
4526 </field>
4527 <field>
4528 <name>HNSSCHG</name>
4529 <description>Host negotiation success status
4530 change</description>
4531 <bitOffset>9</bitOffset>
4532 <bitWidth>1</bitWidth>
4533 </field>
4534 <field>
4535 <name>HNGDET</name>
4536 <description>Host negotiation detected</description>
4537 <bitOffset>17</bitOffset>
4538 <bitWidth>1</bitWidth>
4539 </field>
4540 <field>
4541 <name>ADTOCHG</name>
4542 <description>A-device timeout change</description>
4543 <bitOffset>18</bitOffset>
4544 <bitWidth>1</bitWidth>
4545 </field>
4546 <field>
4547 <name>DBCDNE</name>
4548 <description>Debounce done</description>
4549 <bitOffset>19</bitOffset>
4550 <bitWidth>1</bitWidth>
4551 </field>
4552 </fields>
4553 </register>
4554 <register>
4555 <name>FS_GAHBCFG</name>
4556 <displayName>FS_GAHBCFG</displayName>
4557 <description>OTG_FS AHB configuration register
4558 (OTG_FS_GAHBCFG)</description>
4559 <addressOffset>0x8</addressOffset>
4560 <size>0x20</size>
4561 <access>read-write</access>
4562 <resetValue>0x00000000</resetValue>
4563 <fields>
4564 <field>
4565 <name>GINT</name>
4566 <description>Global interrupt mask</description>
4567 <bitOffset>0</bitOffset>
4568 <bitWidth>1</bitWidth>
4569 </field>
4570 <field>
4571 <name>TXFELVL</name>
4572 <description>TxFIFO empty level</description>
4573 <bitOffset>7</bitOffset>
4574 <bitWidth>1</bitWidth>
4575 </field>
4576 <field>
4577 <name>PTXFELVL</name>
4578 <description>Periodic TxFIFO empty
4579 level</description>
4580 <bitOffset>8</bitOffset>
4581 <bitWidth>1</bitWidth>
4582 </field>
4583 </fields>
4584 </register>
4585 <register>
4586 <name>FS_GUSBCFG</name>
4587 <displayName>FS_GUSBCFG</displayName>
4588 <description>OTG_FS USB configuration register
4589 (OTG_FS_GUSBCFG)</description>
4590 <addressOffset>0xC</addressOffset>
4591 <size>0x20</size>
4592 <resetValue>0x00000A00</resetValue>
4593 <fields>
4594 <field>
4595 <name>TOCAL</name>
4596 <description>FS timeout calibration</description>
4597 <bitOffset>0</bitOffset>
4598 <bitWidth>3</bitWidth>
4599 <access>read-write</access>
4600 </field>
4601 <field>
4602 <name>PHYSEL</name>
4603 <description>Full Speed serial transceiver
4604 select</description>
4605 <bitOffset>6</bitOffset>
4606 <bitWidth>1</bitWidth>
4607 <access>write-only</access>
4608 </field>
4609 <field>
4610 <name>SRPCAP</name>
4611 <description>SRP-capable</description>
4612 <bitOffset>8</bitOffset>
4613 <bitWidth>1</bitWidth>
4614 <access>read-write</access>
4615 </field>
4616 <field>
4617 <name>HNPCAP</name>
4618 <description>HNP-capable</description>
4619 <bitOffset>9</bitOffset>
4620 <bitWidth>1</bitWidth>
4621 <access>read-write</access>
4622 </field>
4623 <field>
4624 <name>TRDT</name>
4625 <description>USB turnaround time</description>
4626 <bitOffset>10</bitOffset>
4627 <bitWidth>4</bitWidth>
4628 <access>read-write</access>
4629 </field>
4630 <field>
4631 <name>FHMOD</name>
4632 <description>Force host mode</description>
4633 <bitOffset>29</bitOffset>
4634 <bitWidth>1</bitWidth>
4635 <access>read-write</access>
4636 </field>
4637 <field>
4638 <name>FDMOD</name>
4639 <description>Force device mode</description>
4640 <bitOffset>30</bitOffset>
4641 <bitWidth>1</bitWidth>
4642 <access>read-write</access>
4643 </field>
4644 <field>
4645 <name>CTXPKT</name>
4646 <description>Corrupt Tx packet</description>
4647 <bitOffset>31</bitOffset>
4648 <bitWidth>1</bitWidth>
4649 <access>read-write</access>
4650 </field>
4651 </fields>
4652 </register>
4653 <register>
4654 <name>FS_GRSTCTL</name>
4655 <displayName>FS_GRSTCTL</displayName>
4656 <description>OTG_FS reset register
4657 (OTG_FS_GRSTCTL)</description>
4658 <addressOffset>0x10</addressOffset>
4659 <size>0x20</size>
4660 <resetValue>0x20000000</resetValue>
4661 <fields>
4662 <field>
4663 <name>CSRST</name>
4664 <description>Core soft reset</description>
4665 <bitOffset>0</bitOffset>
4666 <bitWidth>1</bitWidth>
4667 <access>read-write</access>
4668 </field>
4669 <field>
4670 <name>HSRST</name>
4671 <description>HCLK soft reset</description>
4672 <bitOffset>1</bitOffset>
4673 <bitWidth>1</bitWidth>
4674 <access>read-write</access>
4675 </field>
4676 <field>
4677 <name>FCRST</name>
4678 <description>Host frame counter reset</description>
4679 <bitOffset>2</bitOffset>
4680 <bitWidth>1</bitWidth>
4681 <access>read-write</access>
4682 </field>
4683 <field>
4684 <name>RXFFLSH</name>
4685 <description>RxFIFO flush</description>
4686 <bitOffset>4</bitOffset>
4687 <bitWidth>1</bitWidth>
4688 <access>read-write</access>
4689 </field>
4690 <field>
4691 <name>TXFFLSH</name>
4692 <description>TxFIFO flush</description>
4693 <bitOffset>5</bitOffset>
4694 <bitWidth>1</bitWidth>
4695 <access>read-write</access>
4696 </field>
4697 <field>
4698 <name>TXFNUM</name>
4699 <description>TxFIFO number</description>
4700 <bitOffset>6</bitOffset>
4701 <bitWidth>5</bitWidth>
4702 <access>read-write</access>
4703 </field>
4704 <field>
4705 <name>AHBIDL</name>
4706 <description>AHB master idle</description>
4707 <bitOffset>31</bitOffset>
4708 <bitWidth>1</bitWidth>
4709 <access>read-only</access>
4710 </field>
4711 </fields>
4712 </register>
4713 <register>
4714 <name>FS_GINTSTS</name>
4715 <displayName>FS_GINTSTS</displayName>
4716 <description>OTG_FS core interrupt register
4717 (OTG_FS_GINTSTS)</description>
4718 <addressOffset>0x14</addressOffset>
4719 <size>0x20</size>
4720 <resetValue>0x04000020</resetValue>
4721 <fields>
4722 <field>
4723 <name>CMOD</name>
4724 <description>Current mode of operation</description>
4725 <bitOffset>0</bitOffset>
4726 <bitWidth>1</bitWidth>
4727 <access>read-only</access>
4728 </field>
4729 <field>
4730 <name>MMIS</name>
4731 <description>Mode mismatch interrupt</description>
4732 <bitOffset>1</bitOffset>
4733 <bitWidth>1</bitWidth>
4734 <access>read-write</access>
4735 </field>
4736 <field>
4737 <name>OTGINT</name>
4738 <description>OTG interrupt</description>
4739 <bitOffset>2</bitOffset>
4740 <bitWidth>1</bitWidth>
4741 <access>read-only</access>
4742 </field>
4743 <field>
4744 <name>SOF</name>
4745 <description>Start of frame</description>
4746 <bitOffset>3</bitOffset>
4747 <bitWidth>1</bitWidth>
4748 <access>read-write</access>
4749 </field>
4750 <field>
4751 <name>RXFLVL</name>
4752 <description>RxFIFO non-empty</description>
4753 <bitOffset>4</bitOffset>
4754 <bitWidth>1</bitWidth>
4755 <access>read-only</access>
4756 </field>
4757 <field>
4758 <name>NPTXFE</name>
4759 <description>Non-periodic TxFIFO empty</description>
4760 <bitOffset>5</bitOffset>
4761 <bitWidth>1</bitWidth>
4762 <access>read-only</access>
4763 </field>
4764 <field>
4765 <name>GINAKEFF</name>
4766 <description>Global IN non-periodic NAK
4767 effective</description>
4768 <bitOffset>6</bitOffset>
4769 <bitWidth>1</bitWidth>
4770 <access>read-only</access>
4771 </field>
4772 <field>
4773 <name>GOUTNAKEFF</name>
4774 <description>Global OUT NAK effective</description>
4775 <bitOffset>7</bitOffset>
4776 <bitWidth>1</bitWidth>
4777 <access>read-only</access>
4778 </field>
4779 <field>
4780 <name>ESUSP</name>
4781 <description>Early suspend</description>
4782 <bitOffset>10</bitOffset>
4783 <bitWidth>1</bitWidth>
4784 <access>read-write</access>
4785 </field>
4786 <field>
4787 <name>USBSUSP</name>
4788 <description>USB suspend</description>
4789 <bitOffset>11</bitOffset>
4790 <bitWidth>1</bitWidth>
4791 <access>read-write</access>
4792 </field>
4793 <field>
4794 <name>USBRST</name>
4795 <description>USB reset</description>
4796 <bitOffset>12</bitOffset>
4797 <bitWidth>1</bitWidth>
4798 <access>read-write</access>
4799 </field>
4800 <field>
4801 <name>ENUMDNE</name>
4802 <description>Enumeration done</description>
4803 <bitOffset>13</bitOffset>
4804 <bitWidth>1</bitWidth>
4805 <access>read-write</access>
4806 </field>
4807 <field>
4808 <name>ISOODRP</name>
4809 <description>Isochronous OUT packet dropped
4810 interrupt</description>
4811 <bitOffset>14</bitOffset>
4812 <bitWidth>1</bitWidth>
4813 <access>read-write</access>
4814 </field>
4815 <field>
4816 <name>EOPF</name>
4817 <description>End of periodic frame
4818 interrupt</description>
4819 <bitOffset>15</bitOffset>
4820 <bitWidth>1</bitWidth>
4821 <access>read-write</access>
4822 </field>
4823 <field>
4824 <name>IEPINT</name>
4825 <description>IN endpoint interrupt</description>
4826 <bitOffset>18</bitOffset>
4827 <bitWidth>1</bitWidth>
4828 <access>read-only</access>
4829 </field>
4830 <field>
4831 <name>OEPINT</name>
4832 <description>OUT endpoint interrupt</description>
4833 <bitOffset>19</bitOffset>
4834 <bitWidth>1</bitWidth>
4835 <access>read-only</access>
4836 </field>
4837 <field>
4838 <name>IISOIXFR</name>
4839 <description>Incomplete isochronous IN
4840 transfer</description>
4841 <bitOffset>20</bitOffset>
4842 <bitWidth>1</bitWidth>
4843 <access>read-write</access>
4844 </field>
4845 <field>
4846 <name>IPXFR_INCOMPISOOUT</name>
4847 <description>Incomplete periodic transfer(Host
4848 mode)/Incomplete isochronous OUT transfer(Device
4849 mode)</description>
4850 <bitOffset>21</bitOffset>
4851 <bitWidth>1</bitWidth>
4852 <access>read-write</access>
4853 </field>
4854 <field>
4855 <name>HPRTINT</name>
4856 <description>Host port interrupt</description>
4857 <bitOffset>24</bitOffset>
4858 <bitWidth>1</bitWidth>
4859 <access>read-only</access>
4860 </field>
4861 <field>
4862 <name>HCINT</name>
4863 <description>Host channels interrupt</description>
4864 <bitOffset>25</bitOffset>
4865 <bitWidth>1</bitWidth>
4866 <access>read-only</access>
4867 </field>
4868 <field>
4869 <name>PTXFE</name>
4870 <description>Periodic TxFIFO empty</description>
4871 <bitOffset>26</bitOffset>
4872 <bitWidth>1</bitWidth>
4873 <access>read-only</access>
4874 </field>
4875 <field>
4876 <name>CIDSCHG</name>
4877 <description>Connector ID status change</description>
4878 <bitOffset>28</bitOffset>
4879 <bitWidth>1</bitWidth>
4880 <access>read-write</access>
4881 </field>
4882 <field>
4883 <name>DISCINT</name>
4884 <description>Disconnect detected
4885 interrupt</description>
4886 <bitOffset>29</bitOffset>
4887 <bitWidth>1</bitWidth>
4888 <access>read-write</access>
4889 </field>
4890 <field>
4891 <name>SRQINT</name>
4892 <description>Session request/new session detected
4893 interrupt</description>
4894 <bitOffset>30</bitOffset>
4895 <bitWidth>1</bitWidth>
4896 <access>read-write</access>
4897 </field>
4898 <field>
4899 <name>WKUPINT</name>
4900 <description>Resume/remote wakeup detected
4901 interrupt</description>
4902 <bitOffset>31</bitOffset>
4903 <bitWidth>1</bitWidth>
4904 <access>read-write</access>
4905 </field>
4906 </fields>
4907 </register>
4908 <register>
4909 <name>FS_GINTMSK</name>
4910 <displayName>FS_GINTMSK</displayName>
4911 <description>OTG_FS interrupt mask register
4912 (OTG_FS_GINTMSK)</description>
4913 <addressOffset>0x18</addressOffset>
4914 <size>0x20</size>
4915 <resetValue>0x00000000</resetValue>
4916 <fields>
4917 <field>
4918 <name>MMISM</name>
4919 <description>Mode mismatch interrupt
4920 mask</description>
4921 <bitOffset>1</bitOffset>
4922 <bitWidth>1</bitWidth>
4923 <access>read-write</access>
4924 </field>
4925 <field>
4926 <name>OTGINT</name>
4927 <description>OTG interrupt mask</description>
4928 <bitOffset>2</bitOffset>
4929 <bitWidth>1</bitWidth>
4930 <access>read-write</access>
4931 </field>
4932 <field>
4933 <name>SOFM</name>
4934 <description>Start of frame mask</description>
4935 <bitOffset>3</bitOffset>
4936 <bitWidth>1</bitWidth>
4937 <access>read-write</access>
4938 </field>
4939 <field>
4940 <name>RXFLVLM</name>
4941 <description>Receive FIFO non-empty
4942 mask</description>
4943 <bitOffset>4</bitOffset>
4944 <bitWidth>1</bitWidth>
4945 <access>read-write</access>
4946 </field>
4947 <field>
4948 <name>NPTXFEM</name>
4949 <description>Non-periodic TxFIFO empty
4950 mask</description>
4951 <bitOffset>5</bitOffset>
4952 <bitWidth>1</bitWidth>
4953 <access>read-write</access>
4954 </field>
4955 <field>
4956 <name>GINAKEFFM</name>
4957 <description>Global non-periodic IN NAK effective
4958 mask</description>
4959 <bitOffset>6</bitOffset>
4960 <bitWidth>1</bitWidth>
4961 <access>read-write</access>
4962 </field>
4963 <field>
4964 <name>GONAKEFFM</name>
4965 <description>Global OUT NAK effective
4966 mask</description>
4967 <bitOffset>7</bitOffset>
4968 <bitWidth>1</bitWidth>
4969 <access>read-write</access>
4970 </field>
4971 <field>
4972 <name>ESUSPM</name>
4973 <description>Early suspend mask</description>
4974 <bitOffset>10</bitOffset>
4975 <bitWidth>1</bitWidth>
4976 <access>read-write</access>
4977 </field>
4978 <field>
4979 <name>USBSUSPM</name>
4980 <description>USB suspend mask</description>
4981 <bitOffset>11</bitOffset>
4982 <bitWidth>1</bitWidth>
4983 <access>read-write</access>
4984 </field>
4985 <field>
4986 <name>USBRST</name>
4987 <description>USB reset mask</description>
4988 <bitOffset>12</bitOffset>
4989 <bitWidth>1</bitWidth>
4990 <access>read-write</access>
4991 </field>
4992 <field>
4993 <name>ENUMDNEM</name>
4994 <description>Enumeration done mask</description>
4995 <bitOffset>13</bitOffset>
4996 <bitWidth>1</bitWidth>
4997 <access>read-write</access>
4998 </field>
4999 <field>
5000 <name>ISOODRPM</name>
5001 <description>Isochronous OUT packet dropped interrupt
5002 mask</description>
5003 <bitOffset>14</bitOffset>
5004 <bitWidth>1</bitWidth>
5005 <access>read-write</access>
5006 </field>
5007 <field>
5008 <name>EOPFM</name>
5009 <description>End of periodic frame interrupt
5010 mask</description>
5011 <bitOffset>15</bitOffset>
5012 <bitWidth>1</bitWidth>
5013 <access>read-write</access>
5014 </field>
5015 <field>
5016 <name>EPMISM</name>
5017 <description>Endpoint mismatch interrupt
5018 mask</description>
5019 <bitOffset>17</bitOffset>
5020 <bitWidth>1</bitWidth>
5021 <access>read-write</access>
5022 </field>
5023 <field>
5024 <name>IEPINT</name>
5025 <description>IN endpoints interrupt
5026 mask</description>
5027 <bitOffset>18</bitOffset>
5028 <bitWidth>1</bitWidth>
5029 <access>read-write</access>
5030 </field>
5031 <field>
5032 <name>OEPINT</name>
5033 <description>OUT endpoints interrupt
5034 mask</description>
5035 <bitOffset>19</bitOffset>
5036 <bitWidth>1</bitWidth>
5037 <access>read-write</access>
5038 </field>
5039 <field>
5040 <name>IISOIXFRM</name>
5041 <description>Incomplete isochronous IN transfer
5042 mask</description>
5043 <bitOffset>20</bitOffset>
5044 <bitWidth>1</bitWidth>
5045 <access>read-write</access>
5046 </field>
5047 <field>
5048 <name>IPXFRM_IISOOXFRM</name>
5049 <description>Incomplete periodic transfer mask(Host
5050 mode)/Incomplete isochronous OUT transfer mask(Device
5051 mode)</description>
5052 <bitOffset>21</bitOffset>
5053 <bitWidth>1</bitWidth>
5054 <access>read-write</access>
5055 </field>
5056 <field>
5057 <name>PRTIM</name>
5058 <description>Host port interrupt mask</description>
5059 <bitOffset>24</bitOffset>
5060 <bitWidth>1</bitWidth>
5061 <access>read-only</access>
5062 </field>
5063 <field>
5064 <name>HCIM</name>
5065 <description>Host channels interrupt
5066 mask</description>
5067 <bitOffset>25</bitOffset>
5068 <bitWidth>1</bitWidth>
5069 <access>read-write</access>
5070 </field>
5071 <field>
5072 <name>PTXFEM</name>
5073 <description>Periodic TxFIFO empty mask</description>
5074 <bitOffset>26</bitOffset>
5075 <bitWidth>1</bitWidth>
5076 <access>read-write</access>
5077 </field>
5078 <field>
5079 <name>CIDSCHGM</name>
5080 <description>Connector ID status change
5081 mask</description>
5082 <bitOffset>28</bitOffset>
5083 <bitWidth>1</bitWidth>
5084 <access>read-write</access>
5085 </field>
5086 <field>
5087 <name>DISCINT</name>
5088 <description>Disconnect detected interrupt
5089 mask</description>
5090 <bitOffset>29</bitOffset>
5091 <bitWidth>1</bitWidth>
5092 <access>read-write</access>
5093 </field>
5094 <field>
5095 <name>SRQIM</name>
5096 <description>Session request/new session detected
5097 interrupt mask</description>
5098 <bitOffset>30</bitOffset>
5099 <bitWidth>1</bitWidth>
5100 <access>read-write</access>
5101 </field>
5102 <field>
5103 <name>WUIM</name>
5104 <description>Resume/remote wakeup detected interrupt
5105 mask</description>
5106 <bitOffset>31</bitOffset>
5107 <bitWidth>1</bitWidth>
5108 <access>read-write</access>
5109 </field>
5110 </fields>
5111 </register>
5112 <register>
5113 <name>FS_GRXSTSR_Device</name>
5114 <displayName>FS_GRXSTSR_Device</displayName>
5115 <description>OTG_FS Receive status debug read(Device
5116 mode)</description>
5117 <addressOffset>0x1C</addressOffset>
5118 <size>0x20</size>
5119 <access>read-only</access>
5120 <resetValue>0x00000000</resetValue>
5121 <fields>
5122 <field>
5123 <name>EPNUM</name>
5124 <description>Endpoint number</description>
5125 <bitOffset>0</bitOffset>
5126 <bitWidth>4</bitWidth>
5127 </field>
5128 <field>
5129 <name>BCNT</name>
5130 <description>Byte count</description>
5131 <bitOffset>4</bitOffset>
5132 <bitWidth>11</bitWidth>
5133 </field>
5134 <field>
5135 <name>DPID</name>
5136 <description>Data PID</description>
5137 <bitOffset>15</bitOffset>
5138 <bitWidth>2</bitWidth>
5139 </field>
5140 <field>
5141 <name>PKTSTS</name>
5142 <description>Packet status</description>
5143 <bitOffset>17</bitOffset>
5144 <bitWidth>4</bitWidth>
5145 </field>
5146 <field>
5147 <name>FRMNUM</name>
5148 <description>Frame number</description>
5149 <bitOffset>21</bitOffset>
5150 <bitWidth>4</bitWidth>
5151 </field>
5152 </fields>
5153 </register>
5154 <register>
5155 <name>FS_GRXSTSR_Host</name>
5156 <displayName>FS_GRXSTSR_Host</displayName>
5157 <description>OTG_FS Receive status debug read(Host
5158 mode)</description>
5159 <alternateRegister>FS_GRXSTSR_Device</alternateRegister>
5160 <addressOffset>0x1C</addressOffset>
5161 <size>0x20</size>
5162 <access>read-only</access>
5163 <resetValue>0x00000000</resetValue>
5164 <fields>
5165 <field>
5166 <name>EPNUM</name>
5167 <description>Endpoint number</description>
5168 <bitOffset>0</bitOffset>
5169 <bitWidth>4</bitWidth>
5170 </field>
5171 <field>
5172 <name>BCNT</name>
5173 <description>Byte count</description>
5174 <bitOffset>4</bitOffset>
5175 <bitWidth>11</bitWidth>
5176 </field>
5177 <field>
5178 <name>DPID</name>
5179 <description>Data PID</description>
5180 <bitOffset>15</bitOffset>
5181 <bitWidth>2</bitWidth>
5182 </field>
5183 <field>
5184 <name>PKTSTS</name>
5185 <description>Packet status</description>
5186 <bitOffset>17</bitOffset>
5187 <bitWidth>4</bitWidth>
5188 </field>
5189 <field>
5190 <name>FRMNUM</name>
5191 <description>Frame number</description>
5192 <bitOffset>21</bitOffset>
5193 <bitWidth>4</bitWidth>
5194 </field>
5195 </fields>
5196 </register>
5197 <register>
5198 <name>FS_GRXFSIZ</name>
5199 <displayName>FS_GRXFSIZ</displayName>
5200 <description>OTG_FS Receive FIFO size register
5201 (OTG_FS_GRXFSIZ)</description>
5202 <addressOffset>0x24</addressOffset>
5203 <size>0x20</size>
5204 <access>read-write</access>
5205 <resetValue>0x00000200</resetValue>
5206 <fields>
5207 <field>
5208 <name>RXFD</name>
5209 <description>RxFIFO depth</description>
5210 <bitOffset>0</bitOffset>
5211 <bitWidth>16</bitWidth>
5212 </field>
5213 </fields>
5214 </register>
5215 <register>
5216 <name>FS_GNPTXFSIZ_Device</name>
5217 <displayName>FS_GNPTXFSIZ_Device</displayName>
5218 <description>OTG_FS non-periodic transmit FIFO size
5219 register (Device mode)</description>
5220 <addressOffset>0x28</addressOffset>
5221 <size>0x20</size>
5222 <access>read-write</access>
5223 <resetValue>0x00000200</resetValue>
5224 <fields>
5225 <field>
5226 <name>TX0FSA</name>
5227 <description>Endpoint 0 transmit RAM start
5228 address</description>
5229 <bitOffset>0</bitOffset>
5230 <bitWidth>16</bitWidth>
5231 </field>
5232 <field>
5233 <name>TX0FD</name>
5234 <description>Endpoint 0 TxFIFO depth</description>
5235 <bitOffset>16</bitOffset>
5236 <bitWidth>16</bitWidth>
5237 </field>
5238 </fields>
5239 </register>
5240 <register>
5241 <name>FS_GNPTXFSIZ_Host</name>
5242 <displayName>FS_GNPTXFSIZ_Host</displayName>
5243 <description>OTG_FS non-periodic transmit FIFO size
5244 register (Host mode)</description>
5245 <alternateRegister>FS_GNPTXFSIZ_Device</alternateRegister>
5246 <addressOffset>0x28</addressOffset>
5247 <size>0x20</size>
5248 <access>read-write</access>
5249 <resetValue>0x00000200</resetValue>
5250 <fields>
5251 <field>
5252 <name>NPTXFSA</name>
5253 <description>Non-periodic transmit RAM start
5254 address</description>
5255 <bitOffset>0</bitOffset>
5256 <bitWidth>16</bitWidth>
5257 </field>
5258 <field>
5259 <name>NPTXFD</name>
5260 <description>Non-periodic TxFIFO depth</description>
5261 <bitOffset>16</bitOffset>
5262 <bitWidth>16</bitWidth>
5263 </field>
5264 </fields>
5265 </register>
5266 <register>
5267 <name>FS_GNPTXSTS</name>
5268 <displayName>FS_GNPTXSTS</displayName>
5269 <description>OTG_FS non-periodic transmit FIFO/queue
5270 status register (OTG_FS_GNPTXSTS)</description>
5271 <addressOffset>0x2C</addressOffset>
5272 <size>0x20</size>
5273 <access>read-only</access>
5274 <resetValue>0x00080200</resetValue>
5275 <fields>
5276 <field>
5277 <name>NPTXFSAV</name>
5278 <description>Non-periodic TxFIFO space
5279 available</description>
5280 <bitOffset>0</bitOffset>
5281 <bitWidth>16</bitWidth>
5282 </field>
5283 <field>
5284 <name>NPTQXSAV</name>
5285 <description>Non-periodic transmit request queue
5286 space available</description>
5287 <bitOffset>16</bitOffset>
5288 <bitWidth>8</bitWidth>
5289 </field>
5290 <field>
5291 <name>NPTXQTOP</name>
5292 <description>Top of the non-periodic transmit request
5293 queue</description>
5294 <bitOffset>24</bitOffset>
5295 <bitWidth>7</bitWidth>
5296 </field>
5297 </fields>
5298 </register>
5299 <register>
5300 <name>FS_GCCFG</name>
5301 <displayName>FS_GCCFG</displayName>
5302 <description>OTG_FS general core configuration register
5303 (OTG_FS_GCCFG)</description>
5304 <addressOffset>0x38</addressOffset>
5305 <size>0x20</size>
5306 <access>read-write</access>
5307 <resetValue>0x00000000</resetValue>
5308 <fields>
5309 <field>
5310 <name>PWRDWN</name>
5311 <description>Power down</description>
5312 <bitOffset>16</bitOffset>
5313 <bitWidth>1</bitWidth>
5314 </field>
5315 <field>
5316 <name>VBUSASEN</name>
5317 <description>Enable the VBUS sensing
5318 device</description>
5319 <bitOffset>18</bitOffset>
5320 <bitWidth>1</bitWidth>
5321 </field>
5322 <field>
5323 <name>VBUSBSEN</name>
5324 <description>Enable the VBUS sensing
5325 device</description>
5326 <bitOffset>19</bitOffset>
5327 <bitWidth>1</bitWidth>
5328 </field>
5329 <field>
5330 <name>SOFOUTEN</name>
5331 <description>SOF output enable</description>
5332 <bitOffset>20</bitOffset>
5333 <bitWidth>1</bitWidth>
5334 </field>
5335 </fields>
5336 </register>
5337 <register>
5338 <name>FS_CID</name>
5339 <displayName>FS_CID</displayName>
5340 <description>core ID register</description>
5341 <addressOffset>0x3C</addressOffset>
5342 <size>0x20</size>
5343 <access>read-write</access>
5344 <resetValue>0x00001000</resetValue>
5345 <fields>
5346 <field>
5347 <name>PRODUCT_ID</name>
5348 <description>Product ID field</description>
5349 <bitOffset>0</bitOffset>
5350 <bitWidth>32</bitWidth>
5351 </field>
5352 </fields>
5353 </register>
5354 <register>
5355 <name>FS_HPTXFSIZ</name>
5356 <displayName>FS_HPTXFSIZ</displayName>
5357 <description>OTG_FS Host periodic transmit FIFO size
5358 register (OTG_FS_HPTXFSIZ)</description>
5359 <addressOffset>0x100</addressOffset>
5360 <size>0x20</size>
5361 <access>read-write</access>
5362 <resetValue>0x02000600</resetValue>
5363 <fields>
5364 <field>
5365 <name>PTXSA</name>
5366 <description>Host periodic TxFIFO start
5367 address</description>
5368 <bitOffset>0</bitOffset>
5369 <bitWidth>16</bitWidth>
5370 </field>
5371 <field>
5372 <name>PTXFSIZ</name>
5373 <description>Host periodic TxFIFO depth</description>
5374 <bitOffset>16</bitOffset>
5375 <bitWidth>16</bitWidth>
5376 </field>
5377 </fields>
5378 </register>
5379 <register>
5380 <name>FS_DIEPTXF1</name>
5381 <displayName>FS_DIEPTXF1</displayName>
5382 <description>OTG_FS device IN endpoint transmit FIFO size
5383 register (OTG_FS_DIEPTXF2)</description>
5384 <addressOffset>0x104</addressOffset>
5385 <size>0x20</size>
5386 <access>read-write</access>
5387 <resetValue>0x02000400</resetValue>
5388 <fields>
5389 <field>
5390 <name>INEPTXSA</name>
5391 <description>IN endpoint FIFO2 transmit RAM start
5392 address</description>
5393 <bitOffset>0</bitOffset>
5394 <bitWidth>16</bitWidth>
5395 </field>
5396 <field>
5397 <name>INEPTXFD</name>
5398 <description>IN endpoint TxFIFO depth</description>
5399 <bitOffset>16</bitOffset>
5400 <bitWidth>16</bitWidth>
5401 </field>
5402 </fields>
5403 </register>
5404 <register>
5405 <name>FS_DIEPTXF2</name>
5406 <displayName>FS_DIEPTXF2</displayName>
5407 <description>OTG_FS device IN endpoint transmit FIFO size
5408 register (OTG_FS_DIEPTXF3)</description>
5409 <addressOffset>0x108</addressOffset>
5410 <size>0x20</size>
5411 <access>read-write</access>
5412 <resetValue>0x02000400</resetValue>
5413 <fields>
5414 <field>
5415 <name>INEPTXSA</name>
5416 <description>IN endpoint FIFO3 transmit RAM start
5417 address</description>
5418 <bitOffset>0</bitOffset>
5419 <bitWidth>16</bitWidth>
5420 </field>
5421 <field>
5422 <name>INEPTXFD</name>
5423 <description>IN endpoint TxFIFO depth</description>
5424 <bitOffset>16</bitOffset>
5425 <bitWidth>16</bitWidth>
5426 </field>
5427 </fields>
5428 </register>
5429 <register>
5430 <name>FS_DIEPTXF3</name>
5431 <displayName>FS_DIEPTXF3</displayName>
5432 <description>OTG_FS device IN endpoint transmit FIFO size
5433 register (OTG_FS_DIEPTXF4)</description>
5434 <addressOffset>0x10C</addressOffset>
5435 <size>0x20</size>
5436 <access>read-write</access>
5437 <resetValue>0x02000400</resetValue>
5438 <fields>
5439 <field>
5440 <name>INEPTXSA</name>
5441 <description>IN endpoint FIFO4 transmit RAM start
5442 address</description>
5443 <bitOffset>0</bitOffset>
5444 <bitWidth>16</bitWidth>
5445 </field>
5446 <field>
5447 <name>INEPTXFD</name>
5448 <description>IN endpoint TxFIFO depth</description>
5449 <bitOffset>16</bitOffset>
5450 <bitWidth>16</bitWidth>
5451 </field>
5452 </fields>
5453 </register>
5454 </registers>
5455 </peripheral>
5456 <peripheral>
5457 <name>OTG_FS_HOST</name>
5458 <description>USB on the go full speed</description>
5459 <groupName>USB_OTG_FS</groupName>
5460 <baseAddress>0x50000400</baseAddress>
5461 <addressBlock>
5462 <offset>0x0</offset>
5463 <size>0x400</size>
5464 <usage>registers</usage>
5465 </addressBlock>
5466 <registers>
5467 <register>
5468 <name>FS_HCFG</name>
5469 <displayName>FS_HCFG</displayName>
5470 <description>OTG_FS host configuration register
5471 (OTG_FS_HCFG)</description>
5472 <addressOffset>0x0</addressOffset>
5473 <size>0x20</size>
5474 <resetValue>0x00000000</resetValue>
5475 <fields>
5476 <field>
5477 <name>FSLSPCS</name>
5478 <description>FS/LS PHY clock select</description>
5479 <bitOffset>0</bitOffset>
5480 <bitWidth>2</bitWidth>
5481 <access>read-write</access>
5482 </field>
5483 <field>
5484 <name>FSLSS</name>
5485 <description>FS- and LS-only support</description>
5486 <bitOffset>2</bitOffset>
5487 <bitWidth>1</bitWidth>
5488 <access>read-only</access>
5489 </field>
5490 </fields>
5491 </register>
5492 <register>
5493 <name>HFIR</name>
5494 <displayName>HFIR</displayName>
5495 <description>OTG_FS Host frame interval
5496 register</description>
5497 <addressOffset>0x4</addressOffset>
5498 <size>0x20</size>
5499 <access>read-write</access>
5500 <resetValue>0x0000EA60</resetValue>
5501 <fields>
5502 <field>
5503 <name>FRIVL</name>
5504 <description>Frame interval</description>
5505 <bitOffset>0</bitOffset>
5506 <bitWidth>16</bitWidth>
5507 </field>
5508 </fields>
5509 </register>
5510 <register>
5511 <name>FS_HFNUM</name>
5512 <displayName>FS_HFNUM</displayName>
5513 <description>OTG_FS host frame number/frame time
5514 remaining register (OTG_FS_HFNUM)</description>
5515 <addressOffset>0x8</addressOffset>
5516 <size>0x20</size>
5517 <access>read-only</access>
5518 <resetValue>0x00003FFF</resetValue>
5519 <fields>
5520 <field>
5521 <name>FRNUM</name>
5522 <description>Frame number</description>
5523 <bitOffset>0</bitOffset>
5524 <bitWidth>16</bitWidth>
5525 </field>
5526 <field>
5527 <name>FTREM</name>
5528 <description>Frame time remaining</description>
5529 <bitOffset>16</bitOffset>
5530 <bitWidth>16</bitWidth>
5531 </field>
5532 </fields>
5533 </register>
5534 <register>
5535 <name>FS_HPTXSTS</name>
5536 <displayName>FS_HPTXSTS</displayName>
5537 <description>OTG_FS_Host periodic transmit FIFO/queue
5538 status register (OTG_FS_HPTXSTS)</description>
5539 <addressOffset>0x10</addressOffset>
5540 <size>0x20</size>
5541 <resetValue>0x00080100</resetValue>
5542 <fields>
5543 <field>
5544 <name>PTXFSAVL</name>
5545 <description>Periodic transmit data FIFO space
5546 available</description>
5547 <bitOffset>0</bitOffset>
5548 <bitWidth>16</bitWidth>
5549 <access>read-write</access>
5550 </field>
5551 <field>
5552 <name>PTXQSAV</name>
5553 <description>Periodic transmit request queue space
5554 available</description>
5555 <bitOffset>16</bitOffset>
5556 <bitWidth>8</bitWidth>
5557 <access>read-only</access>
5558 </field>
5559 <field>
5560 <name>PTXQTOP</name>
5561 <description>Top of the periodic transmit request
5562 queue</description>
5563 <bitOffset>24</bitOffset>
5564 <bitWidth>8</bitWidth>
5565 <access>read-only</access>
5566 </field>
5567 </fields>
5568 </register>
5569 <register>
5570 <name>HAINT</name>
5571 <displayName>HAINT</displayName>
5572 <description>OTG_FS Host all channels interrupt
5573 register</description>
5574 <addressOffset>0x14</addressOffset>
5575 <size>0x20</size>
5576 <access>read-only</access>
5577 <resetValue>0x00000000</resetValue>
5578 <fields>
5579 <field>
5580 <name>HAINT</name>
5581 <description>Channel interrupts</description>
5582 <bitOffset>0</bitOffset>
5583 <bitWidth>16</bitWidth>
5584 </field>
5585 </fields>
5586 </register>
5587 <register>
5588 <name>HAINTMSK</name>
5589 <displayName>HAINTMSK</displayName>
5590 <description>OTG_FS host all channels interrupt mask
5591 register</description>
5592 <addressOffset>0x18</addressOffset>
5593 <size>0x20</size>
5594 <access>read-write</access>
5595 <resetValue>0x00000000</resetValue>
5596 <fields>
5597 <field>
5598 <name>HAINTM</name>
5599 <description>Channel interrupt mask</description>
5600 <bitOffset>0</bitOffset>
5601 <bitWidth>16</bitWidth>
5602 </field>
5603 </fields>
5604 </register>
5605 <register>
5606 <name>FS_HPRT</name>
5607 <displayName>FS_HPRT</displayName>
5608 <description>OTG_FS host port control and status register
5609 (OTG_FS_HPRT)</description>
5610 <addressOffset>0x40</addressOffset>
5611 <size>0x20</size>
5612 <resetValue>0x00000000</resetValue>
5613 <fields>
5614 <field>
5615 <name>PCSTS</name>
5616 <description>Port connect status</description>
5617 <bitOffset>0</bitOffset>
5618 <bitWidth>1</bitWidth>
5619 <access>read-only</access>
5620 </field>
5621 <field>
5622 <name>PCDET</name>
5623 <description>Port connect detected</description>
5624 <bitOffset>1</bitOffset>
5625 <bitWidth>1</bitWidth>
5626 <access>read-write</access>
5627 </field>
5628 <field>
5629 <name>PENA</name>
5630 <description>Port enable</description>
5631 <bitOffset>2</bitOffset>
5632 <bitWidth>1</bitWidth>
5633 <access>read-write</access>
5634 </field>
5635 <field>
5636 <name>PENCHNG</name>
5637 <description>Port enable/disable change</description>
5638 <bitOffset>3</bitOffset>
5639 <bitWidth>1</bitWidth>
5640 <access>read-write</access>
5641 </field>
5642 <field>
5643 <name>POCA</name>
5644 <description>Port overcurrent active</description>
5645 <bitOffset>4</bitOffset>
5646 <bitWidth>1</bitWidth>
5647 <access>read-only</access>
5648 </field>
5649 <field>
5650 <name>POCCHNG</name>
5651 <description>Port overcurrent change</description>
5652 <bitOffset>5</bitOffset>
5653 <bitWidth>1</bitWidth>
5654 <access>read-write</access>
5655 </field>
5656 <field>
5657 <name>PRES</name>
5658 <description>Port resume</description>
5659 <bitOffset>6</bitOffset>
5660 <bitWidth>1</bitWidth>
5661 <access>read-write</access>
5662 </field>
5663 <field>
5664 <name>PSUSP</name>
5665 <description>Port suspend</description>
5666 <bitOffset>7</bitOffset>
5667 <bitWidth>1</bitWidth>
5668 <access>read-write</access>
5669 </field>
5670 <field>
5671 <name>PRST</name>
5672 <description>Port reset</description>
5673 <bitOffset>8</bitOffset>
5674 <bitWidth>1</bitWidth>
5675 <access>read-write</access>
5676 </field>
5677 <field>
5678 <name>PLSTS</name>
5679 <description>Port line status</description>
5680 <bitOffset>10</bitOffset>
5681 <bitWidth>2</bitWidth>
5682 <access>read-only</access>
5683 </field>
5684 <field>
5685 <name>PPWR</name>
5686 <description>Port power</description>
5687 <bitOffset>12</bitOffset>
5688 <bitWidth>1</bitWidth>
5689 <access>read-write</access>
5690 </field>
5691 <field>
5692 <name>PTCTL</name>
5693 <description>Port test control</description>
5694 <bitOffset>13</bitOffset>
5695 <bitWidth>4</bitWidth>
5696 <access>read-write</access>
5697 </field>
5698 <field>
5699 <name>PSPD</name>
5700 <description>Port speed</description>
5701 <bitOffset>17</bitOffset>
5702 <bitWidth>2</bitWidth>
5703 <access>read-only</access>
5704 </field>
5705 </fields>
5706 </register>
5707 <register>
5708 <name>FS_HCCHAR0</name>
5709 <displayName>FS_HCCHAR0</displayName>
5710 <description>OTG_FS host channel-0 characteristics
5711 register (OTG_FS_HCCHAR0)</description>
5712 <addressOffset>0x100</addressOffset>
5713 <size>0x20</size>
5714 <access>read-write</access>
5715 <resetValue>0x00000000</resetValue>
5716 <fields>
5717 <field>
5718 <name>MPSIZ</name>
5719 <description>Maximum packet size</description>
5720 <bitOffset>0</bitOffset>
5721 <bitWidth>11</bitWidth>
5722 </field>
5723 <field>
5724 <name>EPNUM</name>
5725 <description>Endpoint number</description>
5726 <bitOffset>11</bitOffset>
5727 <bitWidth>4</bitWidth>
5728 </field>
5729 <field>
5730 <name>EPDIR</name>
5731 <description>Endpoint direction</description>
5732 <bitOffset>15</bitOffset>
5733 <bitWidth>1</bitWidth>
5734 </field>
5735 <field>
5736 <name>LSDEV</name>
5737 <description>Low-speed device</description>
5738 <bitOffset>17</bitOffset>
5739 <bitWidth>1</bitWidth>
5740 </field>
5741 <field>
5742 <name>EPTYP</name>
5743 <description>Endpoint type</description>
5744 <bitOffset>18</bitOffset>
5745 <bitWidth>2</bitWidth>
5746 </field>
5747 <field>
5748 <name>MCNT</name>
5749 <description>Multicount</description>
5750 <bitOffset>20</bitOffset>
5751 <bitWidth>2</bitWidth>
5752 </field>
5753 <field>
5754 <name>DAD</name>
5755 <description>Device address</description>
5756 <bitOffset>22</bitOffset>
5757 <bitWidth>7</bitWidth>
5758 </field>
5759 <field>
5760 <name>ODDFRM</name>
5761 <description>Odd frame</description>
5762 <bitOffset>29</bitOffset>
5763 <bitWidth>1</bitWidth>
5764 </field>
5765 <field>
5766 <name>CHDIS</name>
5767 <description>Channel disable</description>
5768 <bitOffset>30</bitOffset>
5769 <bitWidth>1</bitWidth>
5770 </field>
5771 <field>
5772 <name>CHENA</name>
5773 <description>Channel enable</description>
5774 <bitOffset>31</bitOffset>
5775 <bitWidth>1</bitWidth>
5776 </field>
5777 </fields>
5778 </register>
5779 <register>
5780 <name>FS_HCCHAR1</name>
5781 <displayName>FS_HCCHAR1</displayName>
5782 <description>OTG_FS host channel-1 characteristics
5783 register (OTG_FS_HCCHAR1)</description>
5784 <addressOffset>0x120</addressOffset>
5785 <size>0x20</size>
5786 <access>read-write</access>
5787 <resetValue>0x00000000</resetValue>
5788 <fields>
5789 <field>
5790 <name>MPSIZ</name>
5791 <description>Maximum packet size</description>
5792 <bitOffset>0</bitOffset>
5793 <bitWidth>11</bitWidth>
5794 </field>
5795 <field>
5796 <name>EPNUM</name>
5797 <description>Endpoint number</description>
5798 <bitOffset>11</bitOffset>
5799 <bitWidth>4</bitWidth>
5800 </field>
5801 <field>
5802 <name>EPDIR</name>
5803 <description>Endpoint direction</description>
5804 <bitOffset>15</bitOffset>
5805 <bitWidth>1</bitWidth>
5806 </field>
5807 <field>
5808 <name>LSDEV</name>
5809 <description>Low-speed device</description>
5810 <bitOffset>17</bitOffset>
5811 <bitWidth>1</bitWidth>
5812 </field>
5813 <field>
5814 <name>EPTYP</name>
5815 <description>Endpoint type</description>
5816 <bitOffset>18</bitOffset>
5817 <bitWidth>2</bitWidth>
5818 </field>
5819 <field>
5820 <name>MCNT</name>
5821 <description>Multicount</description>
5822 <bitOffset>20</bitOffset>
5823 <bitWidth>2</bitWidth>
5824 </field>
5825 <field>
5826 <name>DAD</name>
5827 <description>Device address</description>
5828 <bitOffset>22</bitOffset>
5829 <bitWidth>7</bitWidth>
5830 </field>
5831 <field>
5832 <name>ODDFRM</name>
5833 <description>Odd frame</description>
5834 <bitOffset>29</bitOffset>
5835 <bitWidth>1</bitWidth>
5836 </field>
5837 <field>
5838 <name>CHDIS</name>
5839 <description>Channel disable</description>
5840 <bitOffset>30</bitOffset>
5841 <bitWidth>1</bitWidth>
5842 </field>
5843 <field>
5844 <name>CHENA</name>
5845 <description>Channel enable</description>
5846 <bitOffset>31</bitOffset>
5847 <bitWidth>1</bitWidth>
5848 </field>
5849 </fields>
5850 </register>
5851 <register>
5852 <name>FS_HCCHAR2</name>
5853 <displayName>FS_HCCHAR2</displayName>
5854 <description>OTG_FS host channel-2 characteristics
5855 register (OTG_FS_HCCHAR2)</description>
5856 <addressOffset>0x140</addressOffset>
5857 <size>0x20</size>
5858 <access>read-write</access>
5859 <resetValue>0x00000000</resetValue>
5860 <fields>
5861 <field>
5862 <name>MPSIZ</name>
5863 <description>Maximum packet size</description>
5864 <bitOffset>0</bitOffset>
5865 <bitWidth>11</bitWidth>
5866 </field>
5867 <field>
5868 <name>EPNUM</name>
5869 <description>Endpoint number</description>
5870 <bitOffset>11</bitOffset>
5871 <bitWidth>4</bitWidth>
5872 </field>
5873 <field>
5874 <name>EPDIR</name>
5875 <description>Endpoint direction</description>
5876 <bitOffset>15</bitOffset>
5877 <bitWidth>1</bitWidth>
5878 </field>
5879 <field>
5880 <name>LSDEV</name>
5881 <description>Low-speed device</description>
5882 <bitOffset>17</bitOffset>
5883 <bitWidth>1</bitWidth>
5884 </field>
5885 <field>
5886 <name>EPTYP</name>
5887 <description>Endpoint type</description>
5888 <bitOffset>18</bitOffset>
5889 <bitWidth>2</bitWidth>
5890 </field>
5891 <field>
5892 <name>MCNT</name>
5893 <description>Multicount</description>
5894 <bitOffset>20</bitOffset>
5895 <bitWidth>2</bitWidth>
5896 </field>
5897 <field>
5898 <name>DAD</name>
5899 <description>Device address</description>
5900 <bitOffset>22</bitOffset>
5901 <bitWidth>7</bitWidth>
5902 </field>
5903 <field>
5904 <name>ODDFRM</name>
5905 <description>Odd frame</description>
5906 <bitOffset>29</bitOffset>
5907 <bitWidth>1</bitWidth>
5908 </field>
5909 <field>
5910 <name>CHDIS</name>
5911 <description>Channel disable</description>
5912 <bitOffset>30</bitOffset>
5913 <bitWidth>1</bitWidth>
5914 </field>
5915 <field>
5916 <name>CHENA</name>
5917 <description>Channel enable</description>
5918 <bitOffset>31</bitOffset>
5919 <bitWidth>1</bitWidth>
5920 </field>
5921 </fields>
5922 </register>
5923 <register>
5924 <name>FS_HCCHAR3</name>
5925 <displayName>FS_HCCHAR3</displayName>
5926 <description>OTG_FS host channel-3 characteristics
5927 register (OTG_FS_HCCHAR3)</description>
5928 <addressOffset>0x160</addressOffset>
5929 <size>0x20</size>
5930 <access>read-write</access>
5931 <resetValue>0x00000000</resetValue>
5932 <fields>
5933 <field>
5934 <name>MPSIZ</name>
5935 <description>Maximum packet size</description>
5936 <bitOffset>0</bitOffset>
5937 <bitWidth>11</bitWidth>
5938 </field>
5939 <field>
5940 <name>EPNUM</name>
5941 <description>Endpoint number</description>
5942 <bitOffset>11</bitOffset>
5943 <bitWidth>4</bitWidth>
5944 </field>
5945 <field>
5946 <name>EPDIR</name>
5947 <description>Endpoint direction</description>
5948 <bitOffset>15</bitOffset>
5949 <bitWidth>1</bitWidth>
5950 </field>
5951 <field>
5952 <name>LSDEV</name>
5953 <description>Low-speed device</description>
5954 <bitOffset>17</bitOffset>
5955 <bitWidth>1</bitWidth>
5956 </field>
5957 <field>
5958 <name>EPTYP</name>
5959 <description>Endpoint type</description>
5960 <bitOffset>18</bitOffset>
5961 <bitWidth>2</bitWidth>
5962 </field>
5963 <field>
5964 <name>MCNT</name>
5965 <description>Multicount</description>
5966 <bitOffset>20</bitOffset>
5967 <bitWidth>2</bitWidth>
5968 </field>
5969 <field>
5970 <name>DAD</name>
5971 <description>Device address</description>
5972 <bitOffset>22</bitOffset>
5973 <bitWidth>7</bitWidth>
5974 </field>
5975 <field>
5976 <name>ODDFRM</name>
5977 <description>Odd frame</description>
5978 <bitOffset>29</bitOffset>
5979 <bitWidth>1</bitWidth>
5980 </field>
5981 <field>
5982 <name>CHDIS</name>
5983 <description>Channel disable</description>
5984 <bitOffset>30</bitOffset>
5985 <bitWidth>1</bitWidth>
5986 </field>
5987 <field>
5988 <name>CHENA</name>
5989 <description>Channel enable</description>
5990 <bitOffset>31</bitOffset>
5991 <bitWidth>1</bitWidth>
5992 </field>
5993 </fields>
5994 </register>
5995 <register>
5996 <name>FS_HCCHAR4</name>
5997 <displayName>FS_HCCHAR4</displayName>
5998 <description>OTG_FS host channel-4 characteristics
5999 register (OTG_FS_HCCHAR4)</description>
6000 <addressOffset>0x180</addressOffset>
6001 <size>0x20</size>
6002 <access>read-write</access>
6003 <resetValue>0x00000000</resetValue>
6004 <fields>
6005 <field>
6006 <name>MPSIZ</name>
6007 <description>Maximum packet size</description>
6008 <bitOffset>0</bitOffset>
6009 <bitWidth>11</bitWidth>
6010 </field>
6011 <field>
6012 <name>EPNUM</name>
6013 <description>Endpoint number</description>
6014 <bitOffset>11</bitOffset>
6015 <bitWidth>4</bitWidth>
6016 </field>
6017 <field>
6018 <name>EPDIR</name>
6019 <description>Endpoint direction</description>
6020 <bitOffset>15</bitOffset>
6021 <bitWidth>1</bitWidth>
6022 </field>
6023 <field>
6024 <name>LSDEV</name>
6025 <description>Low-speed device</description>
6026 <bitOffset>17</bitOffset>
6027 <bitWidth>1</bitWidth>
6028 </field>
6029 <field>
6030 <name>EPTYP</name>
6031 <description>Endpoint type</description>
6032 <bitOffset>18</bitOffset>
6033 <bitWidth>2</bitWidth>
6034 </field>
6035 <field>
6036 <name>MCNT</name>
6037 <description>Multicount</description>
6038 <bitOffset>20</bitOffset>
6039 <bitWidth>2</bitWidth>
6040 </field>
6041 <field>
6042 <name>DAD</name>
6043 <description>Device address</description>
6044 <bitOffset>22</bitOffset>
6045 <bitWidth>7</bitWidth>
6046 </field>
6047 <field>
6048 <name>ODDFRM</name>
6049 <description>Odd frame</description>
6050 <bitOffset>29</bitOffset>
6051 <bitWidth>1</bitWidth>
6052 </field>
6053 <field>
6054 <name>CHDIS</name>
6055 <description>Channel disable</description>
6056 <bitOffset>30</bitOffset>
6057 <bitWidth>1</bitWidth>
6058 </field>
6059 <field>
6060 <name>CHENA</name>
6061 <description>Channel enable</description>
6062 <bitOffset>31</bitOffset>
6063 <bitWidth>1</bitWidth>
6064 </field>
6065 </fields>
6066 </register>
6067 <register>
6068 <name>FS_HCCHAR5</name>
6069 <displayName>FS_HCCHAR5</displayName>
6070 <description>OTG_FS host channel-5 characteristics
6071 register (OTG_FS_HCCHAR5)</description>
6072 <addressOffset>0x1A0</addressOffset>
6073 <size>0x20</size>
6074 <access>read-write</access>
6075 <resetValue>0x00000000</resetValue>
6076 <fields>
6077 <field>
6078 <name>MPSIZ</name>
6079 <description>Maximum packet size</description>
6080 <bitOffset>0</bitOffset>
6081 <bitWidth>11</bitWidth>
6082 </field>
6083 <field>
6084 <name>EPNUM</name>
6085 <description>Endpoint number</description>
6086 <bitOffset>11</bitOffset>
6087 <bitWidth>4</bitWidth>
6088 </field>
6089 <field>
6090 <name>EPDIR</name>
6091 <description>Endpoint direction</description>
6092 <bitOffset>15</bitOffset>
6093 <bitWidth>1</bitWidth>
6094 </field>
6095 <field>
6096 <name>LSDEV</name>
6097 <description>Low-speed device</description>
6098 <bitOffset>17</bitOffset>
6099 <bitWidth>1</bitWidth>
6100 </field>
6101 <field>
6102 <name>EPTYP</name>
6103 <description>Endpoint type</description>
6104 <bitOffset>18</bitOffset>
6105 <bitWidth>2</bitWidth>
6106 </field>
6107 <field>
6108 <name>MCNT</name>
6109 <description>Multicount</description>
6110 <bitOffset>20</bitOffset>
6111 <bitWidth>2</bitWidth>
6112 </field>
6113 <field>
6114 <name>DAD</name>
6115 <description>Device address</description>
6116 <bitOffset>22</bitOffset>
6117 <bitWidth>7</bitWidth>
6118 </field>
6119 <field>
6120 <name>ODDFRM</name>
6121 <description>Odd frame</description>
6122 <bitOffset>29</bitOffset>
6123 <bitWidth>1</bitWidth>
6124 </field>
6125 <field>
6126 <name>CHDIS</name>
6127 <description>Channel disable</description>
6128 <bitOffset>30</bitOffset>
6129 <bitWidth>1</bitWidth>
6130 </field>
6131 <field>
6132 <name>CHENA</name>
6133 <description>Channel enable</description>
6134 <bitOffset>31</bitOffset>
6135 <bitWidth>1</bitWidth>
6136 </field>
6137 </fields>
6138 </register>
6139 <register>
6140 <name>FS_HCCHAR6</name>
6141 <displayName>FS_HCCHAR6</displayName>
6142 <description>OTG_FS host channel-6 characteristics
6143 register (OTG_FS_HCCHAR6)</description>
6144 <addressOffset>0x1C0</addressOffset>
6145 <size>0x20</size>
6146 <access>read-write</access>
6147 <resetValue>0x00000000</resetValue>
6148 <fields>
6149 <field>
6150 <name>MPSIZ</name>
6151 <description>Maximum packet size</description>
6152 <bitOffset>0</bitOffset>
6153 <bitWidth>11</bitWidth>
6154 </field>
6155 <field>
6156 <name>EPNUM</name>
6157 <description>Endpoint number</description>
6158 <bitOffset>11</bitOffset>
6159 <bitWidth>4</bitWidth>
6160 </field>
6161 <field>
6162 <name>EPDIR</name>
6163 <description>Endpoint direction</description>
6164 <bitOffset>15</bitOffset>
6165 <bitWidth>1</bitWidth>
6166 </field>
6167 <field>
6168 <name>LSDEV</name>
6169 <description>Low-speed device</description>
6170 <bitOffset>17</bitOffset>
6171 <bitWidth>1</bitWidth>
6172 </field>
6173 <field>
6174 <name>EPTYP</name>
6175 <description>Endpoint type</description>
6176 <bitOffset>18</bitOffset>
6177 <bitWidth>2</bitWidth>
6178 </field>
6179 <field>
6180 <name>MCNT</name>
6181 <description>Multicount</description>
6182 <bitOffset>20</bitOffset>
6183 <bitWidth>2</bitWidth>
6184 </field>
6185 <field>
6186 <name>DAD</name>
6187 <description>Device address</description>
6188 <bitOffset>22</bitOffset>
6189 <bitWidth>7</bitWidth>
6190 </field>
6191 <field>
6192 <name>ODDFRM</name>
6193 <description>Odd frame</description>
6194 <bitOffset>29</bitOffset>
6195 <bitWidth>1</bitWidth>
6196 </field>
6197 <field>
6198 <name>CHDIS</name>
6199 <description>Channel disable</description>
6200 <bitOffset>30</bitOffset>
6201 <bitWidth>1</bitWidth>
6202 </field>
6203 <field>
6204 <name>CHENA</name>
6205 <description>Channel enable</description>
6206 <bitOffset>31</bitOffset>
6207 <bitWidth>1</bitWidth>
6208 </field>
6209 </fields>
6210 </register>
6211 <register>
6212 <name>FS_HCCHAR7</name>
6213 <displayName>FS_HCCHAR7</displayName>
6214 <description>OTG_FS host channel-7 characteristics
6215 register (OTG_FS_HCCHAR7)</description>
6216 <addressOffset>0x1E0</addressOffset>
6217 <size>0x20</size>
6218 <access>read-write</access>
6219 <resetValue>0x00000000</resetValue>
6220 <fields>
6221 <field>
6222 <name>MPSIZ</name>
6223 <description>Maximum packet size</description>
6224 <bitOffset>0</bitOffset>
6225 <bitWidth>11</bitWidth>
6226 </field>
6227 <field>
6228 <name>EPNUM</name>
6229 <description>Endpoint number</description>
6230 <bitOffset>11</bitOffset>
6231 <bitWidth>4</bitWidth>
6232 </field>
6233 <field>
6234 <name>EPDIR</name>
6235 <description>Endpoint direction</description>
6236 <bitOffset>15</bitOffset>
6237 <bitWidth>1</bitWidth>
6238 </field>
6239 <field>
6240 <name>LSDEV</name>
6241 <description>Low-speed device</description>
6242 <bitOffset>17</bitOffset>
6243 <bitWidth>1</bitWidth>
6244 </field>
6245 <field>
6246 <name>EPTYP</name>
6247 <description>Endpoint type</description>
6248 <bitOffset>18</bitOffset>
6249 <bitWidth>2</bitWidth>
6250 </field>
6251 <field>
6252 <name>MCNT</name>
6253 <description>Multicount</description>
6254 <bitOffset>20</bitOffset>
6255 <bitWidth>2</bitWidth>
6256 </field>
6257 <field>
6258 <name>DAD</name>
6259 <description>Device address</description>
6260 <bitOffset>22</bitOffset>
6261 <bitWidth>7</bitWidth>
6262 </field>
6263 <field>
6264 <name>ODDFRM</name>
6265 <description>Odd frame</description>
6266 <bitOffset>29</bitOffset>
6267 <bitWidth>1</bitWidth>
6268 </field>
6269 <field>
6270 <name>CHDIS</name>
6271 <description>Channel disable</description>
6272 <bitOffset>30</bitOffset>
6273 <bitWidth>1</bitWidth>
6274 </field>
6275 <field>
6276 <name>CHENA</name>
6277 <description>Channel enable</description>
6278 <bitOffset>31</bitOffset>
6279 <bitWidth>1</bitWidth>
6280 </field>
6281 </fields>
6282 </register>
6283 <register>
6284 <name>FS_HCINT0</name>
6285 <displayName>FS_HCINT0</displayName>
6286 <description>OTG_FS host channel-0 interrupt register
6287 (OTG_FS_HCINT0)</description>
6288 <addressOffset>0x108</addressOffset>
6289 <size>0x20</size>
6290 <access>read-write</access>
6291 <resetValue>0x00000000</resetValue>
6292 <fields>
6293 <field>
6294 <name>XFRC</name>
6295 <description>Transfer completed</description>
6296 <bitOffset>0</bitOffset>
6297 <bitWidth>1</bitWidth>
6298 </field>
6299 <field>
6300 <name>CHH</name>
6301 <description>Channel halted</description>
6302 <bitOffset>1</bitOffset>
6303 <bitWidth>1</bitWidth>
6304 </field>
6305 <field>
6306 <name>STALL</name>
6307 <description>STALL response received
6308 interrupt</description>
6309 <bitOffset>3</bitOffset>
6310 <bitWidth>1</bitWidth>
6311 </field>
6312 <field>
6313 <name>NAK</name>
6314 <description>NAK response received
6315 interrupt</description>
6316 <bitOffset>4</bitOffset>
6317 <bitWidth>1</bitWidth>
6318 </field>
6319 <field>
6320 <name>ACK</name>
6321 <description>ACK response received/transmitted
6322 interrupt</description>
6323 <bitOffset>5</bitOffset>
6324 <bitWidth>1</bitWidth>
6325 </field>
6326 <field>
6327 <name>TXERR</name>
6328 <description>Transaction error</description>
6329 <bitOffset>7</bitOffset>
6330 <bitWidth>1</bitWidth>
6331 </field>
6332 <field>
6333 <name>BBERR</name>
6334 <description>Babble error</description>
6335 <bitOffset>8</bitOffset>
6336 <bitWidth>1</bitWidth>
6337 </field>
6338 <field>
6339 <name>FRMOR</name>
6340 <description>Frame overrun</description>
6341 <bitOffset>9</bitOffset>
6342 <bitWidth>1</bitWidth>
6343 </field>
6344 <field>
6345 <name>DTERR</name>
6346 <description>Data toggle error</description>
6347 <bitOffset>10</bitOffset>
6348 <bitWidth>1</bitWidth>
6349 </field>
6350 </fields>
6351 </register>
6352 <register>
6353 <name>FS_HCINT1</name>
6354 <displayName>FS_HCINT1</displayName>
6355 <description>OTG_FS host channel-1 interrupt register
6356 (OTG_FS_HCINT1)</description>
6357 <addressOffset>0x128</addressOffset>
6358 <size>0x20</size>
6359 <access>read-write</access>
6360 <resetValue>0x00000000</resetValue>
6361 <fields>
6362 <field>
6363 <name>XFRC</name>
6364 <description>Transfer completed</description>
6365 <bitOffset>0</bitOffset>
6366 <bitWidth>1</bitWidth>
6367 </field>
6368 <field>
6369 <name>CHH</name>
6370 <description>Channel halted</description>
6371 <bitOffset>1</bitOffset>
6372 <bitWidth>1</bitWidth>
6373 </field>
6374 <field>
6375 <name>STALL</name>
6376 <description>STALL response received
6377 interrupt</description>
6378 <bitOffset>3</bitOffset>
6379 <bitWidth>1</bitWidth>
6380 </field>
6381 <field>
6382 <name>NAK</name>
6383 <description>NAK response received
6384 interrupt</description>
6385 <bitOffset>4</bitOffset>
6386 <bitWidth>1</bitWidth>
6387 </field>
6388 <field>
6389 <name>ACK</name>
6390 <description>ACK response received/transmitted
6391 interrupt</description>
6392 <bitOffset>5</bitOffset>
6393 <bitWidth>1</bitWidth>
6394 </field>
6395 <field>
6396 <name>TXERR</name>
6397 <description>Transaction error</description>
6398 <bitOffset>7</bitOffset>
6399 <bitWidth>1</bitWidth>
6400 </field>
6401 <field>
6402 <name>BBERR</name>
6403 <description>Babble error</description>
6404 <bitOffset>8</bitOffset>
6405 <bitWidth>1</bitWidth>
6406 </field>
6407 <field>
6408 <name>FRMOR</name>
6409 <description>Frame overrun</description>
6410 <bitOffset>9</bitOffset>
6411 <bitWidth>1</bitWidth>
6412 </field>
6413 <field>
6414 <name>DTERR</name>
6415 <description>Data toggle error</description>
6416 <bitOffset>10</bitOffset>
6417 <bitWidth>1</bitWidth>
6418 </field>
6419 </fields>
6420 </register>
6421 <register>
6422 <name>FS_HCINT2</name>
6423 <displayName>FS_HCINT2</displayName>
6424 <description>OTG_FS host channel-2 interrupt register
6425 (OTG_FS_HCINT2)</description>
6426 <addressOffset>0x148</addressOffset>
6427 <size>0x20</size>
6428 <access>read-write</access>
6429 <resetValue>0x00000000</resetValue>
6430 <fields>
6431 <field>
6432 <name>XFRC</name>
6433 <description>Transfer completed</description>
6434 <bitOffset>0</bitOffset>
6435 <bitWidth>1</bitWidth>
6436 </field>
6437 <field>
6438 <name>CHH</name>
6439 <description>Channel halted</description>
6440 <bitOffset>1</bitOffset>
6441 <bitWidth>1</bitWidth>
6442 </field>
6443 <field>
6444 <name>STALL</name>
6445 <description>STALL response received
6446 interrupt</description>
6447 <bitOffset>3</bitOffset>
6448 <bitWidth>1</bitWidth>
6449 </field>
6450 <field>
6451 <name>NAK</name>
6452 <description>NAK response received
6453 interrupt</description>
6454 <bitOffset>4</bitOffset>
6455 <bitWidth>1</bitWidth>
6456 </field>
6457 <field>
6458 <name>ACK</name>
6459 <description>ACK response received/transmitted
6460 interrupt</description>
6461 <bitOffset>5</bitOffset>
6462 <bitWidth>1</bitWidth>
6463 </field>
6464 <field>
6465 <name>TXERR</name>
6466 <description>Transaction error</description>
6467 <bitOffset>7</bitOffset>
6468 <bitWidth>1</bitWidth>
6469 </field>
6470 <field>
6471 <name>BBERR</name>
6472 <description>Babble error</description>
6473 <bitOffset>8</bitOffset>
6474 <bitWidth>1</bitWidth>
6475 </field>
6476 <field>
6477 <name>FRMOR</name>
6478 <description>Frame overrun</description>
6479 <bitOffset>9</bitOffset>
6480 <bitWidth>1</bitWidth>
6481 </field>
6482 <field>
6483 <name>DTERR</name>
6484 <description>Data toggle error</description>
6485 <bitOffset>10</bitOffset>
6486 <bitWidth>1</bitWidth>
6487 </field>
6488 </fields>
6489 </register>
6490 <register>
6491 <name>FS_HCINT3</name>
6492 <displayName>FS_HCINT3</displayName>
6493 <description>OTG_FS host channel-3 interrupt register
6494 (OTG_FS_HCINT3)</description>
6495 <addressOffset>0x168</addressOffset>
6496 <size>0x20</size>
6497 <access>read-write</access>
6498 <resetValue>0x00000000</resetValue>
6499 <fields>
6500 <field>
6501 <name>XFRC</name>
6502 <description>Transfer completed</description>
6503 <bitOffset>0</bitOffset>
6504 <bitWidth>1</bitWidth>
6505 </field>
6506 <field>
6507 <name>CHH</name>
6508 <description>Channel halted</description>
6509 <bitOffset>1</bitOffset>
6510 <bitWidth>1</bitWidth>
6511 </field>
6512 <field>
6513 <name>STALL</name>
6514 <description>STALL response received
6515 interrupt</description>
6516 <bitOffset>3</bitOffset>
6517 <bitWidth>1</bitWidth>
6518 </field>
6519 <field>
6520 <name>NAK</name>
6521 <description>NAK response received
6522 interrupt</description>
6523 <bitOffset>4</bitOffset>
6524 <bitWidth>1</bitWidth>
6525 </field>
6526 <field>
6527 <name>ACK</name>
6528 <description>ACK response received/transmitted
6529 interrupt</description>
6530 <bitOffset>5</bitOffset>
6531 <bitWidth>1</bitWidth>
6532 </field>
6533 <field>
6534 <name>TXERR</name>
6535 <description>Transaction error</description>
6536 <bitOffset>7</bitOffset>
6537 <bitWidth>1</bitWidth>
6538 </field>
6539 <field>
6540 <name>BBERR</name>
6541 <description>Babble error</description>
6542 <bitOffset>8</bitOffset>
6543 <bitWidth>1</bitWidth>
6544 </field>
6545 <field>
6546 <name>FRMOR</name>
6547 <description>Frame overrun</description>
6548 <bitOffset>9</bitOffset>
6549 <bitWidth>1</bitWidth>
6550 </field>
6551 <field>
6552 <name>DTERR</name>
6553 <description>Data toggle error</description>
6554 <bitOffset>10</bitOffset>
6555 <bitWidth>1</bitWidth>
6556 </field>
6557 </fields>
6558 </register>
6559 <register>
6560 <name>FS_HCINT4</name>
6561 <displayName>FS_HCINT4</displayName>
6562 <description>OTG_FS host channel-4 interrupt register
6563 (OTG_FS_HCINT4)</description>
6564 <addressOffset>0x188</addressOffset>
6565 <size>0x20</size>
6566 <access>read-write</access>
6567 <resetValue>0x00000000</resetValue>
6568 <fields>
6569 <field>
6570 <name>XFRC</name>
6571 <description>Transfer completed</description>
6572 <bitOffset>0</bitOffset>
6573 <bitWidth>1</bitWidth>
6574 </field>
6575 <field>
6576 <name>CHH</name>
6577 <description>Channel halted</description>
6578 <bitOffset>1</bitOffset>
6579 <bitWidth>1</bitWidth>
6580 </field>
6581 <field>
6582 <name>STALL</name>
6583 <description>STALL response received
6584 interrupt</description>
6585 <bitOffset>3</bitOffset>
6586 <bitWidth>1</bitWidth>
6587 </field>
6588 <field>
6589 <name>NAK</name>
6590 <description>NAK response received
6591 interrupt</description>
6592 <bitOffset>4</bitOffset>
6593 <bitWidth>1</bitWidth>
6594 </field>
6595 <field>
6596 <name>ACK</name>
6597 <description>ACK response received/transmitted
6598 interrupt</description>
6599 <bitOffset>5</bitOffset>
6600 <bitWidth>1</bitWidth>
6601 </field>
6602 <field>
6603 <name>TXERR</name>
6604 <description>Transaction error</description>
6605 <bitOffset>7</bitOffset>
6606 <bitWidth>1</bitWidth>
6607 </field>
6608 <field>
6609 <name>BBERR</name>
6610 <description>Babble error</description>
6611 <bitOffset>8</bitOffset>
6612 <bitWidth>1</bitWidth>
6613 </field>
6614 <field>
6615 <name>FRMOR</name>
6616 <description>Frame overrun</description>
6617 <bitOffset>9</bitOffset>
6618 <bitWidth>1</bitWidth>
6619 </field>
6620 <field>
6621 <name>DTERR</name>
6622 <description>Data toggle error</description>
6623 <bitOffset>10</bitOffset>
6624 <bitWidth>1</bitWidth>
6625 </field>
6626 </fields>
6627 </register>
6628 <register>
6629 <name>FS_HCINT5</name>
6630 <displayName>FS_HCINT5</displayName>
6631 <description>OTG_FS host channel-5 interrupt register
6632 (OTG_FS_HCINT5)</description>
6633 <addressOffset>0x1A8</addressOffset>
6634 <size>0x20</size>
6635 <access>read-write</access>
6636 <resetValue>0x00000000</resetValue>
6637 <fields>
6638 <field>
6639 <name>XFRC</name>
6640 <description>Transfer completed</description>
6641 <bitOffset>0</bitOffset>
6642 <bitWidth>1</bitWidth>
6643 </field>
6644 <field>
6645 <name>CHH</name>
6646 <description>Channel halted</description>
6647 <bitOffset>1</bitOffset>
6648 <bitWidth>1</bitWidth>
6649 </field>
6650 <field>
6651 <name>STALL</name>
6652 <description>STALL response received
6653 interrupt</description>
6654 <bitOffset>3</bitOffset>
6655 <bitWidth>1</bitWidth>
6656 </field>
6657 <field>
6658 <name>NAK</name>
6659 <description>NAK response received
6660 interrupt</description>
6661 <bitOffset>4</bitOffset>
6662 <bitWidth>1</bitWidth>
6663 </field>
6664 <field>
6665 <name>ACK</name>
6666 <description>ACK response received/transmitted
6667 interrupt</description>
6668 <bitOffset>5</bitOffset>
6669 <bitWidth>1</bitWidth>
6670 </field>
6671 <field>
6672 <name>TXERR</name>
6673 <description>Transaction error</description>
6674 <bitOffset>7</bitOffset>
6675 <bitWidth>1</bitWidth>
6676 </field>
6677 <field>
6678 <name>BBERR</name>
6679 <description>Babble error</description>
6680 <bitOffset>8</bitOffset>
6681 <bitWidth>1</bitWidth>
6682 </field>
6683 <field>
6684 <name>FRMOR</name>
6685 <description>Frame overrun</description>
6686 <bitOffset>9</bitOffset>
6687 <bitWidth>1</bitWidth>
6688 </field>
6689 <field>
6690 <name>DTERR</name>
6691 <description>Data toggle error</description>
6692 <bitOffset>10</bitOffset>
6693 <bitWidth>1</bitWidth>
6694 </field>
6695 </fields>
6696 </register>
6697 <register>
6698 <name>FS_HCINT6</name>
6699 <displayName>FS_HCINT6</displayName>
6700 <description>OTG_FS host channel-6 interrupt register
6701 (OTG_FS_HCINT6)</description>
6702 <addressOffset>0x1C8</addressOffset>
6703 <size>0x20</size>
6704 <access>read-write</access>
6705 <resetValue>0x00000000</resetValue>
6706 <fields>
6707 <field>
6708 <name>XFRC</name>
6709 <description>Transfer completed</description>
6710 <bitOffset>0</bitOffset>
6711 <bitWidth>1</bitWidth>
6712 </field>
6713 <field>
6714 <name>CHH</name>
6715 <description>Channel halted</description>
6716 <bitOffset>1</bitOffset>
6717 <bitWidth>1</bitWidth>
6718 </field>
6719 <field>
6720 <name>STALL</name>
6721 <description>STALL response received
6722 interrupt</description>
6723 <bitOffset>3</bitOffset>
6724 <bitWidth>1</bitWidth>
6725 </field>
6726 <field>
6727 <name>NAK</name>
6728 <description>NAK response received
6729 interrupt</description>
6730 <bitOffset>4</bitOffset>
6731 <bitWidth>1</bitWidth>
6732 </field>
6733 <field>
6734 <name>ACK</name>
6735 <description>ACK response received/transmitted
6736 interrupt</description>
6737 <bitOffset>5</bitOffset>
6738 <bitWidth>1</bitWidth>
6739 </field>
6740 <field>
6741 <name>TXERR</name>
6742 <description>Transaction error</description>
6743 <bitOffset>7</bitOffset>
6744 <bitWidth>1</bitWidth>
6745 </field>
6746 <field>
6747 <name>BBERR</name>
6748 <description>Babble error</description>
6749 <bitOffset>8</bitOffset>
6750 <bitWidth>1</bitWidth>
6751 </field>
6752 <field>
6753 <name>FRMOR</name>
6754 <description>Frame overrun</description>
6755 <bitOffset>9</bitOffset>
6756 <bitWidth>1</bitWidth>
6757 </field>
6758 <field>
6759 <name>DTERR</name>
6760 <description>Data toggle error</description>
6761 <bitOffset>10</bitOffset>
6762 <bitWidth>1</bitWidth>
6763 </field>
6764 </fields>
6765 </register>
6766 <register>
6767 <name>FS_HCINT7</name>
6768 <displayName>FS_HCINT7</displayName>
6769 <description>OTG_FS host channel-7 interrupt register
6770 (OTG_FS_HCINT7)</description>
6771 <addressOffset>0x1E8</addressOffset>
6772 <size>0x20</size>
6773 <access>read-write</access>
6774 <resetValue>0x00000000</resetValue>
6775 <fields>
6776 <field>
6777 <name>XFRC</name>
6778 <description>Transfer completed</description>
6779 <bitOffset>0</bitOffset>
6780 <bitWidth>1</bitWidth>
6781 </field>
6782 <field>
6783 <name>CHH</name>
6784 <description>Channel halted</description>
6785 <bitOffset>1</bitOffset>
6786 <bitWidth>1</bitWidth>
6787 </field>
6788 <field>
6789 <name>STALL</name>
6790 <description>STALL response received
6791 interrupt</description>
6792 <bitOffset>3</bitOffset>
6793 <bitWidth>1</bitWidth>
6794 </field>
6795 <field>
6796 <name>NAK</name>
6797 <description>NAK response received
6798 interrupt</description>
6799 <bitOffset>4</bitOffset>
6800 <bitWidth>1</bitWidth>
6801 </field>
6802 <field>
6803 <name>ACK</name>
6804 <description>ACK response received/transmitted
6805 interrupt</description>
6806 <bitOffset>5</bitOffset>
6807 <bitWidth>1</bitWidth>
6808 </field>
6809 <field>
6810 <name>TXERR</name>
6811 <description>Transaction error</description>
6812 <bitOffset>7</bitOffset>
6813 <bitWidth>1</bitWidth>
6814 </field>
6815 <field>
6816 <name>BBERR</name>
6817 <description>Babble error</description>
6818 <bitOffset>8</bitOffset>
6819 <bitWidth>1</bitWidth>
6820 </field>
6821 <field>
6822 <name>FRMOR</name>
6823 <description>Frame overrun</description>
6824 <bitOffset>9</bitOffset>
6825 <bitWidth>1</bitWidth>
6826 </field>
6827 <field>
6828 <name>DTERR</name>
6829 <description>Data toggle error</description>
6830 <bitOffset>10</bitOffset>
6831 <bitWidth>1</bitWidth>
6832 </field>
6833 </fields>
6834 </register>
6835 <register>
6836 <name>FS_HCINTMSK0</name>
6837 <displayName>FS_HCINTMSK0</displayName>
6838 <description>OTG_FS host channel-0 mask register
6839 (OTG_FS_HCINTMSK0)</description>
6840 <addressOffset>0x10C</addressOffset>
6841 <size>0x20</size>
6842 <access>read-write</access>
6843 <resetValue>0x00000000</resetValue>
6844 <fields>
6845 <field>
6846 <name>XFRCM</name>
6847 <description>Transfer completed mask</description>
6848 <bitOffset>0</bitOffset>
6849 <bitWidth>1</bitWidth>
6850 </field>
6851 <field>
6852 <name>CHHM</name>
6853 <description>Channel halted mask</description>
6854 <bitOffset>1</bitOffset>
6855 <bitWidth>1</bitWidth>
6856 </field>
6857 <field>
6858 <name>STALLM</name>
6859 <description>STALL response received interrupt
6860 mask</description>
6861 <bitOffset>3</bitOffset>
6862 <bitWidth>1</bitWidth>
6863 </field>
6864 <field>
6865 <name>NAKM</name>
6866 <description>NAK response received interrupt
6867 mask</description>
6868 <bitOffset>4</bitOffset>
6869 <bitWidth>1</bitWidth>
6870 </field>
6871 <field>
6872 <name>ACKM</name>
6873 <description>ACK response received/transmitted
6874 interrupt mask</description>
6875 <bitOffset>5</bitOffset>
6876 <bitWidth>1</bitWidth>
6877 </field>
6878 <field>
6879 <name>NYET</name>
6880 <description>response received interrupt
6881 mask</description>
6882 <bitOffset>6</bitOffset>
6883 <bitWidth>1</bitWidth>
6884 </field>
6885 <field>
6886 <name>TXERRM</name>
6887 <description>Transaction error mask</description>
6888 <bitOffset>7</bitOffset>
6889 <bitWidth>1</bitWidth>
6890 </field>
6891 <field>
6892 <name>BBERRM</name>
6893 <description>Babble error mask</description>
6894 <bitOffset>8</bitOffset>
6895 <bitWidth>1</bitWidth>
6896 </field>
6897 <field>
6898 <name>FRMORM</name>
6899 <description>Frame overrun mask</description>
6900 <bitOffset>9</bitOffset>
6901 <bitWidth>1</bitWidth>
6902 </field>
6903 <field>
6904 <name>DTERRM</name>
6905 <description>Data toggle error mask</description>
6906 <bitOffset>10</bitOffset>
6907 <bitWidth>1</bitWidth>
6908 </field>
6909 </fields>
6910 </register>
6911 <register>
6912 <name>FS_HCINTMSK1</name>
6913 <displayName>FS_HCINTMSK1</displayName>
6914 <description>OTG_FS host channel-1 mask register
6915 (OTG_FS_HCINTMSK1)</description>
6916 <addressOffset>0x12C</addressOffset>
6917 <size>0x20</size>
6918 <access>read-write</access>
6919 <resetValue>0x00000000</resetValue>
6920 <fields>
6921 <field>
6922 <name>XFRCM</name>
6923 <description>Transfer completed mask</description>
6924 <bitOffset>0</bitOffset>
6925 <bitWidth>1</bitWidth>
6926 </field>
6927 <field>
6928 <name>CHHM</name>
6929 <description>Channel halted mask</description>
6930 <bitOffset>1</bitOffset>
6931 <bitWidth>1</bitWidth>
6932 </field>
6933 <field>
6934 <name>STALLM</name>
6935 <description>STALL response received interrupt
6936 mask</description>
6937 <bitOffset>3</bitOffset>
6938 <bitWidth>1</bitWidth>
6939 </field>
6940 <field>
6941 <name>NAKM</name>
6942 <description>NAK response received interrupt
6943 mask</description>
6944 <bitOffset>4</bitOffset>
6945 <bitWidth>1</bitWidth>
6946 </field>
6947 <field>
6948 <name>ACKM</name>
6949 <description>ACK response received/transmitted
6950 interrupt mask</description>
6951 <bitOffset>5</bitOffset>
6952 <bitWidth>1</bitWidth>
6953 </field>
6954 <field>
6955 <name>NYET</name>
6956 <description>response received interrupt
6957 mask</description>
6958 <bitOffset>6</bitOffset>
6959 <bitWidth>1</bitWidth>
6960 </field>
6961 <field>
6962 <name>TXERRM</name>
6963 <description>Transaction error mask</description>
6964 <bitOffset>7</bitOffset>
6965 <bitWidth>1</bitWidth>
6966 </field>
6967 <field>
6968 <name>BBERRM</name>
6969 <description>Babble error mask</description>
6970 <bitOffset>8</bitOffset>
6971 <bitWidth>1</bitWidth>
6972 </field>
6973 <field>
6974 <name>FRMORM</name>
6975 <description>Frame overrun mask</description>
6976 <bitOffset>9</bitOffset>
6977 <bitWidth>1</bitWidth>
6978 </field>
6979 <field>
6980 <name>DTERRM</name>
6981 <description>Data toggle error mask</description>
6982 <bitOffset>10</bitOffset>
6983 <bitWidth>1</bitWidth>
6984 </field>
6985 </fields>
6986 </register>
6987 <register>
6988 <name>FS_HCINTMSK2</name>
6989 <displayName>FS_HCINTMSK2</displayName>
6990 <description>OTG_FS host channel-2 mask register
6991 (OTG_FS_HCINTMSK2)</description>
6992 <addressOffset>0x14C</addressOffset>
6993 <size>0x20</size>
6994 <access>read-write</access>
6995 <resetValue>0x00000000</resetValue>
6996 <fields>
6997 <field>
6998 <name>XFRCM</name>
6999 <description>Transfer completed mask</description>
7000 <bitOffset>0</bitOffset>
7001 <bitWidth>1</bitWidth>
7002 </field>
7003 <field>
7004 <name>CHHM</name>
7005 <description>Channel halted mask</description>
7006 <bitOffset>1</bitOffset>
7007 <bitWidth>1</bitWidth>
7008 </field>
7009 <field>
7010 <name>STALLM</name>
7011 <description>STALL response received interrupt
7012 mask</description>
7013 <bitOffset>3</bitOffset>
7014 <bitWidth>1</bitWidth>
7015 </field>
7016 <field>
7017 <name>NAKM</name>
7018 <description>NAK response received interrupt
7019 mask</description>
7020 <bitOffset>4</bitOffset>
7021 <bitWidth>1</bitWidth>
7022 </field>
7023 <field>
7024 <name>ACKM</name>
7025 <description>ACK response received/transmitted
7026 interrupt mask</description>
7027 <bitOffset>5</bitOffset>
7028 <bitWidth>1</bitWidth>
7029 </field>
7030 <field>
7031 <name>NYET</name>
7032 <description>response received interrupt
7033 mask</description>
7034 <bitOffset>6</bitOffset>
7035 <bitWidth>1</bitWidth>
7036 </field>
7037 <field>
7038 <name>TXERRM</name>
7039 <description>Transaction error mask</description>
7040 <bitOffset>7</bitOffset>
7041 <bitWidth>1</bitWidth>
7042 </field>
7043 <field>
7044 <name>BBERRM</name>
7045 <description>Babble error mask</description>
7046 <bitOffset>8</bitOffset>
7047 <bitWidth>1</bitWidth>
7048 </field>
7049 <field>
7050 <name>FRMORM</name>
7051 <description>Frame overrun mask</description>
7052 <bitOffset>9</bitOffset>
7053 <bitWidth>1</bitWidth>
7054 </field>
7055 <field>
7056 <name>DTERRM</name>
7057 <description>Data toggle error mask</description>
7058 <bitOffset>10</bitOffset>
7059 <bitWidth>1</bitWidth>
7060 </field>
7061 </fields>
7062 </register>
7063 <register>
7064 <name>FS_HCINTMSK3</name>
7065 <displayName>FS_HCINTMSK3</displayName>
7066 <description>OTG_FS host channel-3 mask register
7067 (OTG_FS_HCINTMSK3)</description>
7068 <addressOffset>0x16C</addressOffset>
7069 <size>0x20</size>
7070 <access>read-write</access>
7071 <resetValue>0x00000000</resetValue>
7072 <fields>
7073 <field>
7074 <name>XFRCM</name>
7075 <description>Transfer completed mask</description>
7076 <bitOffset>0</bitOffset>
7077 <bitWidth>1</bitWidth>
7078 </field>
7079 <field>
7080 <name>CHHM</name>
7081 <description>Channel halted mask</description>
7082 <bitOffset>1</bitOffset>
7083 <bitWidth>1</bitWidth>
7084 </field>
7085 <field>
7086 <name>STALLM</name>
7087 <description>STALL response received interrupt
7088 mask</description>
7089 <bitOffset>3</bitOffset>
7090 <bitWidth>1</bitWidth>
7091 </field>
7092 <field>
7093 <name>NAKM</name>
7094 <description>NAK response received interrupt
7095 mask</description>
7096 <bitOffset>4</bitOffset>
7097 <bitWidth>1</bitWidth>
7098 </field>
7099 <field>
7100 <name>ACKM</name>
7101 <description>ACK response received/transmitted
7102 interrupt mask</description>
7103 <bitOffset>5</bitOffset>
7104 <bitWidth>1</bitWidth>
7105 </field>
7106 <field>
7107 <name>NYET</name>
7108 <description>response received interrupt
7109 mask</description>
7110 <bitOffset>6</bitOffset>
7111 <bitWidth>1</bitWidth>
7112 </field>
7113 <field>
7114 <name>TXERRM</name>
7115 <description>Transaction error mask</description>
7116 <bitOffset>7</bitOffset>
7117 <bitWidth>1</bitWidth>
7118 </field>
7119 <field>
7120 <name>BBERRM</name>
7121 <description>Babble error mask</description>
7122 <bitOffset>8</bitOffset>
7123 <bitWidth>1</bitWidth>
7124 </field>
7125 <field>
7126 <name>FRMORM</name>
7127 <description>Frame overrun mask</description>
7128 <bitOffset>9</bitOffset>
7129 <bitWidth>1</bitWidth>
7130 </field>
7131 <field>
7132 <name>DTERRM</name>
7133 <description>Data toggle error mask</description>
7134 <bitOffset>10</bitOffset>
7135 <bitWidth>1</bitWidth>
7136 </field>
7137 </fields>
7138 </register>
7139 <register>
7140 <name>FS_HCINTMSK4</name>
7141 <displayName>FS_HCINTMSK4</displayName>
7142 <description>OTG_FS host channel-4 mask register
7143 (OTG_FS_HCINTMSK4)</description>
7144 <addressOffset>0x18C</addressOffset>
7145 <size>0x20</size>
7146 <access>read-write</access>
7147 <resetValue>0x00000000</resetValue>
7148 <fields>
7149 <field>
7150 <name>XFRCM</name>
7151 <description>Transfer completed mask</description>
7152 <bitOffset>0</bitOffset>
7153 <bitWidth>1</bitWidth>
7154 </field>
7155 <field>
7156 <name>CHHM</name>
7157 <description>Channel halted mask</description>
7158 <bitOffset>1</bitOffset>
7159 <bitWidth>1</bitWidth>
7160 </field>
7161 <field>
7162 <name>STALLM</name>
7163 <description>STALL response received interrupt
7164 mask</description>
7165 <bitOffset>3</bitOffset>
7166 <bitWidth>1</bitWidth>
7167 </field>
7168 <field>
7169 <name>NAKM</name>
7170 <description>NAK response received interrupt
7171 mask</description>
7172 <bitOffset>4</bitOffset>
7173 <bitWidth>1</bitWidth>
7174 </field>
7175 <field>
7176 <name>ACKM</name>
7177 <description>ACK response received/transmitted
7178 interrupt mask</description>
7179 <bitOffset>5</bitOffset>
7180 <bitWidth>1</bitWidth>
7181 </field>
7182 <field>
7183 <name>NYET</name>
7184 <description>response received interrupt
7185 mask</description>
7186 <bitOffset>6</bitOffset>
7187 <bitWidth>1</bitWidth>
7188 </field>
7189 <field>
7190 <name>TXERRM</name>
7191 <description>Transaction error mask</description>
7192 <bitOffset>7</bitOffset>
7193 <bitWidth>1</bitWidth>
7194 </field>
7195 <field>
7196 <name>BBERRM</name>
7197 <description>Babble error mask</description>
7198 <bitOffset>8</bitOffset>
7199 <bitWidth>1</bitWidth>
7200 </field>
7201 <field>
7202 <name>FRMORM</name>
7203 <description>Frame overrun mask</description>
7204 <bitOffset>9</bitOffset>
7205 <bitWidth>1</bitWidth>
7206 </field>
7207 <field>
7208 <name>DTERRM</name>
7209 <description>Data toggle error mask</description>
7210 <bitOffset>10</bitOffset>
7211 <bitWidth>1</bitWidth>
7212 </field>
7213 </fields>
7214 </register>
7215 <register>
7216 <name>FS_HCINTMSK5</name>
7217 <displayName>FS_HCINTMSK5</displayName>
7218 <description>OTG_FS host channel-5 mask register
7219 (OTG_FS_HCINTMSK5)</description>
7220 <addressOffset>0x1AC</addressOffset>
7221 <size>0x20</size>
7222 <access>read-write</access>
7223 <resetValue>0x00000000</resetValue>
7224 <fields>
7225 <field>
7226 <name>XFRCM</name>
7227 <description>Transfer completed mask</description>
7228 <bitOffset>0</bitOffset>
7229 <bitWidth>1</bitWidth>
7230 </field>
7231 <field>
7232 <name>CHHM</name>
7233 <description>Channel halted mask</description>
7234 <bitOffset>1</bitOffset>
7235 <bitWidth>1</bitWidth>
7236 </field>
7237 <field>
7238 <name>STALLM</name>
7239 <description>STALL response received interrupt
7240 mask</description>
7241 <bitOffset>3</bitOffset>
7242 <bitWidth>1</bitWidth>
7243 </field>
7244 <field>
7245 <name>NAKM</name>
7246 <description>NAK response received interrupt
7247 mask</description>
7248 <bitOffset>4</bitOffset>
7249 <bitWidth>1</bitWidth>
7250 </field>
7251 <field>
7252 <name>ACKM</name>
7253 <description>ACK response received/transmitted
7254 interrupt mask</description>
7255 <bitOffset>5</bitOffset>
7256 <bitWidth>1</bitWidth>
7257 </field>
7258 <field>
7259 <name>NYET</name>
7260 <description>response received interrupt
7261 mask</description>
7262 <bitOffset>6</bitOffset>
7263 <bitWidth>1</bitWidth>
7264 </field>
7265 <field>
7266 <name>TXERRM</name>
7267 <description>Transaction error mask</description>
7268 <bitOffset>7</bitOffset>
7269 <bitWidth>1</bitWidth>
7270 </field>
7271 <field>
7272 <name>BBERRM</name>
7273 <description>Babble error mask</description>
7274 <bitOffset>8</bitOffset>
7275 <bitWidth>1</bitWidth>
7276 </field>
7277 <field>
7278 <name>FRMORM</name>
7279 <description>Frame overrun mask</description>
7280 <bitOffset>9</bitOffset>
7281 <bitWidth>1</bitWidth>
7282 </field>
7283 <field>
7284 <name>DTERRM</name>
7285 <description>Data toggle error mask</description>
7286 <bitOffset>10</bitOffset>
7287 <bitWidth>1</bitWidth>
7288 </field>
7289 </fields>
7290 </register>
7291 <register>
7292 <name>FS_HCINTMSK6</name>
7293 <displayName>FS_HCINTMSK6</displayName>
7294 <description>OTG_FS host channel-6 mask register
7295 (OTG_FS_HCINTMSK6)</description>
7296 <addressOffset>0x1CC</addressOffset>
7297 <size>0x20</size>
7298 <access>read-write</access>
7299 <resetValue>0x00000000</resetValue>
7300 <fields>
7301 <field>
7302 <name>XFRCM</name>
7303 <description>Transfer completed mask</description>
7304 <bitOffset>0</bitOffset>
7305 <bitWidth>1</bitWidth>
7306 </field>
7307 <field>
7308 <name>CHHM</name>
7309 <description>Channel halted mask</description>
7310 <bitOffset>1</bitOffset>
7311 <bitWidth>1</bitWidth>
7312 </field>
7313 <field>
7314 <name>STALLM</name>
7315 <description>STALL response received interrupt
7316 mask</description>
7317 <bitOffset>3</bitOffset>
7318 <bitWidth>1</bitWidth>
7319 </field>
7320 <field>
7321 <name>NAKM</name>
7322 <description>NAK response received interrupt
7323 mask</description>
7324 <bitOffset>4</bitOffset>
7325 <bitWidth>1</bitWidth>
7326 </field>
7327 <field>
7328 <name>ACKM</name>
7329 <description>ACK response received/transmitted
7330 interrupt mask</description>
7331 <bitOffset>5</bitOffset>
7332 <bitWidth>1</bitWidth>
7333 </field>
7334 <field>
7335 <name>NYET</name>
7336 <description>response received interrupt
7337 mask</description>
7338 <bitOffset>6</bitOffset>
7339 <bitWidth>1</bitWidth>
7340 </field>
7341 <field>
7342 <name>TXERRM</name>
7343 <description>Transaction error mask</description>
7344 <bitOffset>7</bitOffset>
7345 <bitWidth>1</bitWidth>
7346 </field>
7347 <field>
7348 <name>BBERRM</name>
7349 <description>Babble error mask</description>
7350 <bitOffset>8</bitOffset>
7351 <bitWidth>1</bitWidth>
7352 </field>
7353 <field>
7354 <name>FRMORM</name>
7355 <description>Frame overrun mask</description>
7356 <bitOffset>9</bitOffset>
7357 <bitWidth>1</bitWidth>
7358 </field>
7359 <field>
7360 <name>DTERRM</name>
7361 <description>Data toggle error mask</description>
7362 <bitOffset>10</bitOffset>
7363 <bitWidth>1</bitWidth>
7364 </field>
7365 </fields>
7366 </register>
7367 <register>
7368 <name>FS_HCINTMSK7</name>
7369 <displayName>FS_HCINTMSK7</displayName>
7370 <description>OTG_FS host channel-7 mask register
7371 (OTG_FS_HCINTMSK7)</description>
7372 <addressOffset>0x1EC</addressOffset>
7373 <size>0x20</size>
7374 <access>read-write</access>
7375 <resetValue>0x00000000</resetValue>
7376 <fields>
7377 <field>
7378 <name>XFRCM</name>
7379 <description>Transfer completed mask</description>
7380 <bitOffset>0</bitOffset>
7381 <bitWidth>1</bitWidth>
7382 </field>
7383 <field>
7384 <name>CHHM</name>
7385 <description>Channel halted mask</description>
7386 <bitOffset>1</bitOffset>
7387 <bitWidth>1</bitWidth>
7388 </field>
7389 <field>
7390 <name>STALLM</name>
7391 <description>STALL response received interrupt
7392 mask</description>
7393 <bitOffset>3</bitOffset>
7394 <bitWidth>1</bitWidth>
7395 </field>
7396 <field>
7397 <name>NAKM</name>
7398 <description>NAK response received interrupt
7399 mask</description>
7400 <bitOffset>4</bitOffset>
7401 <bitWidth>1</bitWidth>
7402 </field>
7403 <field>
7404 <name>ACKM</name>
7405 <description>ACK response received/transmitted
7406 interrupt mask</description>
7407 <bitOffset>5</bitOffset>
7408 <bitWidth>1</bitWidth>
7409 </field>
7410 <field>
7411 <name>NYET</name>
7412 <description>response received interrupt
7413 mask</description>
7414 <bitOffset>6</bitOffset>
7415 <bitWidth>1</bitWidth>
7416 </field>
7417 <field>
7418 <name>TXERRM</name>
7419 <description>Transaction error mask</description>
7420 <bitOffset>7</bitOffset>
7421 <bitWidth>1</bitWidth>
7422 </field>
7423 <field>
7424 <name>BBERRM</name>
7425 <description>Babble error mask</description>
7426 <bitOffset>8</bitOffset>
7427 <bitWidth>1</bitWidth>
7428 </field>
7429 <field>
7430 <name>FRMORM</name>
7431 <description>Frame overrun mask</description>
7432 <bitOffset>9</bitOffset>
7433 <bitWidth>1</bitWidth>
7434 </field>
7435 <field>
7436 <name>DTERRM</name>
7437 <description>Data toggle error mask</description>
7438 <bitOffset>10</bitOffset>
7439 <bitWidth>1</bitWidth>
7440 </field>
7441 </fields>
7442 </register>
7443 <register>
7444 <name>FS_HCTSIZ0</name>
7445 <displayName>FS_HCTSIZ0</displayName>
7446 <description>OTG_FS host channel-0 transfer size
7447 register</description>
7448 <addressOffset>0x110</addressOffset>
7449 <size>0x20</size>
7450 <access>read-write</access>
7451 <resetValue>0x00000000</resetValue>
7452 <fields>
7453 <field>
7454 <name>XFRSIZ</name>
7455 <description>Transfer size</description>
7456 <bitOffset>0</bitOffset>
7457 <bitWidth>19</bitWidth>
7458 </field>
7459 <field>
7460 <name>PKTCNT</name>
7461 <description>Packet count</description>
7462 <bitOffset>19</bitOffset>
7463 <bitWidth>10</bitWidth>
7464 </field>
7465 <field>
7466 <name>DPID</name>
7467 <description>Data PID</description>
7468 <bitOffset>29</bitOffset>
7469 <bitWidth>2</bitWidth>
7470 </field>
7471 </fields>
7472 </register>
7473 <register>
7474 <name>FS_HCTSIZ1</name>
7475 <displayName>FS_HCTSIZ1</displayName>
7476 <description>OTG_FS host channel-1 transfer size
7477 register</description>
7478 <addressOffset>0x130</addressOffset>
7479 <size>0x20</size>
7480 <access>read-write</access>
7481 <resetValue>0x00000000</resetValue>
7482 <fields>
7483 <field>
7484 <name>XFRSIZ</name>
7485 <description>Transfer size</description>
7486 <bitOffset>0</bitOffset>
7487 <bitWidth>19</bitWidth>
7488 </field>
7489 <field>
7490 <name>PKTCNT</name>
7491 <description>Packet count</description>
7492 <bitOffset>19</bitOffset>
7493 <bitWidth>10</bitWidth>
7494 </field>
7495 <field>
7496 <name>DPID</name>
7497 <description>Data PID</description>
7498 <bitOffset>29</bitOffset>
7499 <bitWidth>2</bitWidth>
7500 </field>
7501 </fields>
7502 </register>
7503 <register>
7504 <name>FS_HCTSIZ2</name>
7505 <displayName>FS_HCTSIZ2</displayName>
7506 <description>OTG_FS host channel-2 transfer size
7507 register</description>
7508 <addressOffset>0x150</addressOffset>
7509 <size>0x20</size>
7510 <access>read-write</access>
7511 <resetValue>0x00000000</resetValue>
7512 <fields>
7513 <field>
7514 <name>XFRSIZ</name>
7515 <description>Transfer size</description>
7516 <bitOffset>0</bitOffset>
7517 <bitWidth>19</bitWidth>
7518 </field>
7519 <field>
7520 <name>PKTCNT</name>
7521 <description>Packet count</description>
7522 <bitOffset>19</bitOffset>
7523 <bitWidth>10</bitWidth>
7524 </field>
7525 <field>
7526 <name>DPID</name>
7527 <description>Data PID</description>
7528 <bitOffset>29</bitOffset>
7529 <bitWidth>2</bitWidth>
7530 </field>
7531 </fields>
7532 </register>
7533 <register>
7534 <name>FS_HCTSIZ3</name>
7535 <displayName>FS_HCTSIZ3</displayName>
7536 <description>OTG_FS host channel-3 transfer size
7537 register</description>
7538 <addressOffset>0x170</addressOffset>
7539 <size>0x20</size>
7540 <access>read-write</access>
7541 <resetValue>0x00000000</resetValue>
7542 <fields>
7543 <field>
7544 <name>XFRSIZ</name>
7545 <description>Transfer size</description>
7546 <bitOffset>0</bitOffset>
7547 <bitWidth>19</bitWidth>
7548 </field>
7549 <field>
7550 <name>PKTCNT</name>
7551 <description>Packet count</description>
7552 <bitOffset>19</bitOffset>
7553 <bitWidth>10</bitWidth>
7554 </field>
7555 <field>
7556 <name>DPID</name>
7557 <description>Data PID</description>
7558 <bitOffset>29</bitOffset>
7559 <bitWidth>2</bitWidth>
7560 </field>
7561 </fields>
7562 </register>
7563 <register>
7564 <name>FS_HCTSIZ4</name>
7565 <displayName>FS_HCTSIZ4</displayName>
7566 <description>OTG_FS host channel-x transfer size
7567 register</description>
7568 <addressOffset>0x190</addressOffset>
7569 <size>0x20</size>
7570 <access>read-write</access>
7571 <resetValue>0x00000000</resetValue>
7572 <fields>
7573 <field>
7574 <name>XFRSIZ</name>
7575 <description>Transfer size</description>
7576 <bitOffset>0</bitOffset>
7577 <bitWidth>19</bitWidth>
7578 </field>
7579 <field>
7580 <name>PKTCNT</name>
7581 <description>Packet count</description>
7582 <bitOffset>19</bitOffset>
7583 <bitWidth>10</bitWidth>
7584 </field>
7585 <field>
7586 <name>DPID</name>
7587 <description>Data PID</description>
7588 <bitOffset>29</bitOffset>
7589 <bitWidth>2</bitWidth>
7590 </field>
7591 </fields>
7592 </register>
7593 <register>
7594 <name>FS_HCTSIZ5</name>
7595 <displayName>FS_HCTSIZ5</displayName>
7596 <description>OTG_FS host channel-5 transfer size
7597 register</description>
7598 <addressOffset>0x1B0</addressOffset>
7599 <size>0x20</size>
7600 <access>read-write</access>
7601 <resetValue>0x00000000</resetValue>
7602 <fields>
7603 <field>
7604 <name>XFRSIZ</name>
7605 <description>Transfer size</description>
7606 <bitOffset>0</bitOffset>
7607 <bitWidth>19</bitWidth>
7608 </field>
7609 <field>
7610 <name>PKTCNT</name>
7611 <description>Packet count</description>
7612 <bitOffset>19</bitOffset>
7613 <bitWidth>10</bitWidth>
7614 </field>
7615 <field>
7616 <name>DPID</name>
7617 <description>Data PID</description>
7618 <bitOffset>29</bitOffset>
7619 <bitWidth>2</bitWidth>
7620 </field>
7621 </fields>
7622 </register>
7623 <register>
7624 <name>FS_HCTSIZ6</name>
7625 <displayName>FS_HCTSIZ6</displayName>
7626 <description>OTG_FS host channel-6 transfer size
7627 register</description>
7628 <addressOffset>0x1D0</addressOffset>
7629 <size>0x20</size>
7630 <access>read-write</access>
7631 <resetValue>0x00000000</resetValue>
7632 <fields>
7633 <field>
7634 <name>XFRSIZ</name>
7635 <description>Transfer size</description>
7636 <bitOffset>0</bitOffset>
7637 <bitWidth>19</bitWidth>
7638 </field>
7639 <field>
7640 <name>PKTCNT</name>
7641 <description>Packet count</description>
7642 <bitOffset>19</bitOffset>
7643 <bitWidth>10</bitWidth>
7644 </field>
7645 <field>
7646 <name>DPID</name>
7647 <description>Data PID</description>
7648 <bitOffset>29</bitOffset>
7649 <bitWidth>2</bitWidth>
7650 </field>
7651 </fields>
7652 </register>
7653 <register>
7654 <name>FS_HCTSIZ7</name>
7655 <displayName>FS_HCTSIZ7</displayName>
7656 <description>OTG_FS host channel-7 transfer size
7657 register</description>
7658 <addressOffset>0x1F0</addressOffset>
7659 <size>0x20</size>
7660 <access>read-write</access>
7661 <resetValue>0x00000000</resetValue>
7662 <fields>
7663 <field>
7664 <name>XFRSIZ</name>
7665 <description>Transfer size</description>
7666 <bitOffset>0</bitOffset>
7667 <bitWidth>19</bitWidth>
7668 </field>
7669 <field>
7670 <name>PKTCNT</name>
7671 <description>Packet count</description>
7672 <bitOffset>19</bitOffset>
7673 <bitWidth>10</bitWidth>
7674 </field>
7675 <field>
7676 <name>DPID</name>
7677 <description>Data PID</description>
7678 <bitOffset>29</bitOffset>
7679 <bitWidth>2</bitWidth>
7680 </field>
7681 </fields>
7682 </register>
7683 </registers>
7684 </peripheral>
7685 <peripheral>
7686 <name>OTG_FS_PWRCLK</name>
7687 <description>USB on the go full speed</description>
7688 <groupName>USB_OTG_FS</groupName>
7689 <baseAddress>0x50000E00</baseAddress>
7690 <addressBlock>
7691 <offset>0x0</offset>
7692 <size>0x400</size>
7693 <usage>registers</usage>
7694 </addressBlock>
7695 <registers>
7696 <register>
7697 <name>FS_PCGCCTL</name>
7698 <displayName>FS_PCGCCTL</displayName>
7699 <description>OTG_FS power and clock gating control
7700 register</description>
7701 <addressOffset>0x0</addressOffset>
7702 <size>0x20</size>
7703 <access>read-write</access>
7704 <resetValue>0x00000000</resetValue>
7705 <fields>
7706 <field>
7707 <name>STPPCLK</name>
7708 <description>Stop PHY clock</description>
7709 <bitOffset>0</bitOffset>
7710 <bitWidth>1</bitWidth>
7711 </field>
7712 <field>
7713 <name>GATEHCLK</name>
7714 <description>Gate HCLK</description>
7715 <bitOffset>1</bitOffset>
7716 <bitWidth>1</bitWidth>
7717 </field>
7718 <field>
7719 <name>PHYSUSP</name>
7720 <description>PHY Suspended</description>
7721 <bitOffset>4</bitOffset>
7722 <bitWidth>1</bitWidth>
7723 </field>
7724 </fields>
7725 </register>
7726 </registers>
7727 </peripheral>
7728 <peripheral>
7729 <name>PWR</name>
7730 <description>Power control</description>
7731 <groupName>PWR</groupName>
7732 <baseAddress>0x40007000</baseAddress>
7733 <addressBlock>
7734 <offset>0x0</offset>
7735 <size>0x400</size>
7736 <usage>registers</usage>
7737 </addressBlock>
7738 <registers>
7739 <register>
7740 <name>CR</name>
7741 <displayName>CR</displayName>
7742 <description>power control register</description>
7743 <addressOffset>0x0</addressOffset>
7744 <size>0x20</size>
7745 <access>read-write</access>
7746 <resetValue>0x00000000</resetValue>
7747 <fields>
7748 <field>
7749 <name>VOS</name>
7750 <description>Regulator voltage scaling output
7751 selection</description>
7752 <bitOffset>14</bitOffset>
7753 <bitWidth>2</bitWidth>
7754 </field>
7755 <field>
7756 <name>ADCDC1</name>
7757 <description>ADCDC1</description>
7758 <bitOffset>13</bitOffset>
7759 <bitWidth>1</bitWidth>
7760 </field>
7761 <field>
7762 <name>FPDS</name>
7763 <description>Flash power down in Stop
7764 mode</description>
7765 <bitOffset>9</bitOffset>
7766 <bitWidth>1</bitWidth>
7767 </field>
7768 <field>
7769 <name>DBP</name>
7770 <description>Disable backup domain write
7771 protection</description>
7772 <bitOffset>8</bitOffset>
7773 <bitWidth>1</bitWidth>
7774 </field>
7775 <field>
7776 <name>PLS</name>
7777 <description>PVD level selection</description>
7778 <bitOffset>5</bitOffset>
7779 <bitWidth>3</bitWidth>
7780 </field>
7781 <field>
7782 <name>PVDE</name>
7783 <description>Power voltage detector
7784 enable</description>
7785 <bitOffset>4</bitOffset>
7786 <bitWidth>1</bitWidth>
7787 </field>
7788 <field>
7789 <name>CSBF</name>
7790 <description>Clear standby flag</description>
7791 <bitOffset>3</bitOffset>
7792 <bitWidth>1</bitWidth>
7793 </field>
7794 <field>
7795 <name>CWUF</name>
7796 <description>Clear wakeup flag</description>
7797 <bitOffset>2</bitOffset>
7798 <bitWidth>1</bitWidth>
7799 </field>
7800 <field>
7801 <name>PDDS</name>
7802 <description>Power down deepsleep</description>
7803 <bitOffset>1</bitOffset>
7804 <bitWidth>1</bitWidth>
7805 </field>
7806 <field>
7807 <name>LPDS</name>
7808 <description>Low-power deep sleep</description>
7809 <bitOffset>0</bitOffset>
7810 <bitWidth>1</bitWidth>
7811 </field>
7812 </fields>
7813 </register>
7814 <register>
7815 <name>CSR</name>
7816 <displayName>CSR</displayName>
7817 <description>power control/status register</description>
7818 <addressOffset>0x4</addressOffset>
7819 <size>0x20</size>
7820 <resetValue>0x00000000</resetValue>
7821 <fields>
7822 <field>
7823 <name>WUF</name>
7824 <description>Wakeup flag</description>
7825 <bitOffset>0</bitOffset>
7826 <bitWidth>1</bitWidth>
7827 <access>read-only</access>
7828 </field>
7829 <field>
7830 <name>SBF</name>
7831 <description>Standby flag</description>
7832 <bitOffset>1</bitOffset>
7833 <bitWidth>1</bitWidth>
7834 <access>read-only</access>
7835 </field>
7836 <field>
7837 <name>PVDO</name>
7838 <description>PVD output</description>
7839 <bitOffset>2</bitOffset>
7840 <bitWidth>1</bitWidth>
7841 <access>read-only</access>
7842 </field>
7843 <field>
7844 <name>BRR</name>
7845 <description>Backup regulator ready</description>
7846 <bitOffset>3</bitOffset>
7847 <bitWidth>1</bitWidth>
7848 <access>read-only</access>
7849 </field>
7850 <field>
7851 <name>EWUP</name>
7852 <description>Enable WKUP pin</description>
7853 <bitOffset>8</bitOffset>
7854 <bitWidth>1</bitWidth>
7855 <access>read-write</access>
7856 </field>
7857 <field>
7858 <name>BRE</name>
7859 <description>Backup regulator enable</description>
7860 <bitOffset>9</bitOffset>
7861 <bitWidth>1</bitWidth>
7862 <access>read-write</access>
7863 </field>
7864 <field>
7865 <name>VOSRDY</name>
7866 <description>Regulator voltage scaling output
7867 selection ready bit</description>
7868 <bitOffset>14</bitOffset>
7869 <bitWidth>1</bitWidth>
7870 <access>read-write</access>
7871 </field>
7872 </fields>
7873 </register>
7874 </registers>
7875 </peripheral>
7876 <peripheral>
7877 <name>RCC</name>
7878 <description>Reset and clock control</description>
7879 <groupName>RCC</groupName>
7880 <baseAddress>0x40023800</baseAddress>
7881 <addressBlock>
7882 <offset>0x0</offset>
7883 <size>0x400</size>
7884 <usage>registers</usage>
7885 </addressBlock>
7886 <interrupt>
7887 <name>I2C1_EV</name>
7888 <description>I2C1 event interrupt</description>
7889 <value>31</value>
7890 </interrupt>
7891 <interrupt>
7892 <name>I2C1_ER</name>
7893 <description>I2C1 error interrupt</description>
7894 <value>32</value>
7895 </interrupt>
7896 <registers>
7897 <register>
7898 <name>CR</name>
7899 <displayName>CR</displayName>
7900 <description>clock control register</description>
7901 <addressOffset>0x0</addressOffset>
7902 <size>0x20</size>
7903 <resetValue>0x00000083</resetValue>
7904 <fields>
7905 <field>
7906 <name>PLLI2SRDY</name>
7907 <description>PLLI2S clock ready flag</description>
7908 <bitOffset>27</bitOffset>
7909 <bitWidth>1</bitWidth>
7910 <access>read-only</access>
7911 </field>
7912 <field>
7913 <name>PLLI2SON</name>
7914 <description>PLLI2S enable</description>
7915 <bitOffset>26</bitOffset>
7916 <bitWidth>1</bitWidth>
7917 <access>read-write</access>
7918 </field>
7919 <field>
7920 <name>PLLRDY</name>
7921 <description>Main PLL (PLL) clock ready
7922 flag</description>
7923 <bitOffset>25</bitOffset>
7924 <bitWidth>1</bitWidth>
7925 <access>read-only</access>
7926 </field>
7927 <field>
7928 <name>PLLON</name>
7929 <description>Main PLL (PLL) enable</description>
7930 <bitOffset>24</bitOffset>
7931 <bitWidth>1</bitWidth>
7932 <access>read-write</access>
7933 </field>
7934 <field>
7935 <name>CSSON</name>
7936 <description>Clock security system
7937 enable</description>
7938 <bitOffset>19</bitOffset>
7939 <bitWidth>1</bitWidth>
7940 <access>read-write</access>
7941 </field>
7942 <field>
7943 <name>HSEBYP</name>
7944 <description>HSE clock bypass</description>
7945 <bitOffset>18</bitOffset>
7946 <bitWidth>1</bitWidth>
7947 <access>read-write</access>
7948 </field>
7949 <field>
7950 <name>HSERDY</name>
7951 <description>HSE clock ready flag</description>
7952 <bitOffset>17</bitOffset>
7953 <bitWidth>1</bitWidth>
7954 <access>read-only</access>
7955 </field>
7956 <field>
7957 <name>HSEON</name>
7958 <description>HSE clock enable</description>
7959 <bitOffset>16</bitOffset>
7960 <bitWidth>1</bitWidth>
7961 <access>read-write</access>
7962 </field>
7963 <field>
7964 <name>HSICAL</name>
7965 <description>Internal high-speed clock
7966 calibration</description>
7967 <bitOffset>8</bitOffset>
7968 <bitWidth>8</bitWidth>
7969 <access>read-only</access>
7970 </field>
7971 <field>
7972 <name>HSITRIM</name>
7973 <description>Internal high-speed clock
7974 trimming</description>
7975 <bitOffset>3</bitOffset>
7976 <bitWidth>5</bitWidth>
7977 <access>read-write</access>
7978 </field>
7979 <field>
7980 <name>HSIRDY</name>
7981 <description>Internal high-speed clock ready
7982 flag</description>
7983 <bitOffset>1</bitOffset>
7984 <bitWidth>1</bitWidth>
7985 <access>read-only</access>
7986 </field>
7987 <field>
7988 <name>HSION</name>
7989 <description>Internal high-speed clock
7990 enable</description>
7991 <bitOffset>0</bitOffset>
7992 <bitWidth>1</bitWidth>
7993 <access>read-write</access>
7994 </field>
7995 </fields>
7996 </register>
7997 <register>
7998 <name>PLLCFGR</name>
7999 <displayName>PLLCFGR</displayName>
8000 <description>PLL configuration register</description>
8001 <addressOffset>0x4</addressOffset>
8002 <size>0x20</size>
8003 <access>read-write</access>
8004 <resetValue>0x24003010</resetValue>
8005 <fields>
8006 <field>
8007 <name>PLLQ3</name>
8008 <description>Main PLL (PLL) division factor for USB
8009 OTG FS, SDIO and random number generator
8010 clocks</description>
8011 <bitOffset>27</bitOffset>
8012 <bitWidth>1</bitWidth>
8013 </field>
8014 <field>
8015 <name>PLLQ2</name>
8016 <description>Main PLL (PLL) division factor for USB
8017 OTG FS, SDIO and random number generator
8018 clocks</description>
8019 <bitOffset>26</bitOffset>
8020 <bitWidth>1</bitWidth>
8021 </field>
8022 <field>
8023 <name>PLLQ1</name>
8024 <description>Main PLL (PLL) division factor for USB
8025 OTG FS, SDIO and random number generator
8026 clocks</description>
8027 <bitOffset>25</bitOffset>
8028 <bitWidth>1</bitWidth>
8029 </field>
8030 <field>
8031 <name>PLLQ0</name>
8032 <description>Main PLL (PLL) division factor for USB
8033 OTG FS, SDIO and random number generator
8034 clocks</description>
8035 <bitOffset>24</bitOffset>
8036 <bitWidth>1</bitWidth>
8037 </field>
8038 <field>
8039 <name>PLLSRC</name>
8040 <description>Main PLL(PLL) and audio PLL (PLLI2S)
8041 entry clock source</description>
8042 <bitOffset>22</bitOffset>
8043 <bitWidth>1</bitWidth>
8044 </field>
8045 <field>
8046 <name>PLLP1</name>
8047 <description>Main PLL (PLL) division factor for main
8048 system clock</description>
8049 <bitOffset>17</bitOffset>
8050 <bitWidth>1</bitWidth>
8051 </field>
8052 <field>
8053 <name>PLLP0</name>
8054 <description>Main PLL (PLL) division factor for main
8055 system clock</description>
8056 <bitOffset>16</bitOffset>
8057 <bitWidth>1</bitWidth>
8058 </field>
8059 <field>
8060 <name>PLLN8</name>
8061 <description>Main PLL (PLL) multiplication factor for
8062 VCO</description>
8063 <bitOffset>14</bitOffset>
8064 <bitWidth>1</bitWidth>
8065 </field>
8066 <field>
8067 <name>PLLN7</name>
8068 <description>Main PLL (PLL) multiplication factor for
8069 VCO</description>
8070 <bitOffset>13</bitOffset>
8071 <bitWidth>1</bitWidth>
8072 </field>
8073 <field>
8074 <name>PLLN6</name>
8075 <description>Main PLL (PLL) multiplication factor for
8076 VCO</description>
8077 <bitOffset>12</bitOffset>
8078 <bitWidth>1</bitWidth>
8079 </field>
8080 <field>
8081 <name>PLLN5</name>
8082 <description>Main PLL (PLL) multiplication factor for
8083 VCO</description>
8084 <bitOffset>11</bitOffset>
8085 <bitWidth>1</bitWidth>
8086 </field>
8087 <field>
8088 <name>PLLN4</name>
8089 <description>Main PLL (PLL) multiplication factor for
8090 VCO</description>
8091 <bitOffset>10</bitOffset>
8092 <bitWidth>1</bitWidth>
8093 </field>
8094 <field>
8095 <name>PLLN3</name>
8096 <description>Main PLL (PLL) multiplication factor for
8097 VCO</description>
8098 <bitOffset>9</bitOffset>
8099 <bitWidth>1</bitWidth>
8100 </field>
8101 <field>
8102 <name>PLLN2</name>
8103 <description>Main PLL (PLL) multiplication factor for
8104 VCO</description>
8105 <bitOffset>8</bitOffset>
8106 <bitWidth>1</bitWidth>
8107 </field>
8108 <field>
8109 <name>PLLN1</name>
8110 <description>Main PLL (PLL) multiplication factor for
8111 VCO</description>
8112 <bitOffset>7</bitOffset>
8113 <bitWidth>1</bitWidth>
8114 </field>
8115 <field>
8116 <name>PLLN0</name>
8117 <description>Main PLL (PLL) multiplication factor for
8118 VCO</description>
8119 <bitOffset>6</bitOffset>
8120 <bitWidth>1</bitWidth>
8121 </field>
8122 <field>
8123 <name>PLLM5</name>
8124 <description>Division factor for the main PLL (PLL)
8125 and audio PLL (PLLI2S) input clock</description>
8126 <bitOffset>5</bitOffset>
8127 <bitWidth>1</bitWidth>
8128 </field>
8129 <field>
8130 <name>PLLM4</name>
8131 <description>Division factor for the main PLL (PLL)
8132 and audio PLL (PLLI2S) input clock</description>
8133 <bitOffset>4</bitOffset>
8134 <bitWidth>1</bitWidth>
8135 </field>
8136 <field>
8137 <name>PLLM3</name>
8138 <description>Division factor for the main PLL (PLL)
8139 and audio PLL (PLLI2S) input clock</description>
8140 <bitOffset>3</bitOffset>
8141 <bitWidth>1</bitWidth>
8142 </field>
8143 <field>
8144 <name>PLLM2</name>
8145 <description>Division factor for the main PLL (PLL)
8146 and audio PLL (PLLI2S) input clock</description>
8147 <bitOffset>2</bitOffset>
8148 <bitWidth>1</bitWidth>
8149 </field>
8150 <field>
8151 <name>PLLM1</name>
8152 <description>Division factor for the main PLL (PLL)
8153 and audio PLL (PLLI2S) input clock</description>
8154 <bitOffset>1</bitOffset>
8155 <bitWidth>1</bitWidth>
8156 </field>
8157 <field>
8158 <name>PLLM0</name>
8159 <description>Division factor for the main PLL (PLL)
8160 and audio PLL (PLLI2S) input clock</description>
8161 <bitOffset>0</bitOffset>
8162 <bitWidth>1</bitWidth>
8163 </field>
8164 </fields>
8165 </register>
8166 <register>
8167 <name>CFGR</name>
8168 <displayName>CFGR</displayName>
8169 <description>clock configuration register</description>
8170 <addressOffset>0x8</addressOffset>
8171 <size>0x20</size>
8172 <resetValue>0x00000000</resetValue>
8173 <fields>
8174 <field>
8175 <name>MCO2</name>
8176 <description>Microcontroller clock output
8177 2</description>
8178 <bitOffset>30</bitOffset>
8179 <bitWidth>2</bitWidth>
8180 <access>read-write</access>
8181 </field>
8182 <field>
8183 <name>MCO2PRE</name>
8184 <description>MCO2 prescaler</description>
8185 <bitOffset>27</bitOffset>
8186 <bitWidth>3</bitWidth>
8187 <access>read-write</access>
8188 </field>
8189 <field>
8190 <name>MCO1PRE</name>
8191 <description>MCO1 prescaler</description>
8192 <bitOffset>24</bitOffset>
8193 <bitWidth>3</bitWidth>
8194 <access>read-write</access>
8195 </field>
8196 <field>
8197 <name>I2SSRC</name>
8198 <description>I2S clock selection</description>
8199 <bitOffset>23</bitOffset>
8200 <bitWidth>1</bitWidth>
8201 <access>read-write</access>
8202 </field>
8203 <field>
8204 <name>MCO1</name>
8205 <description>Microcontroller clock output
8206 1</description>
8207 <bitOffset>21</bitOffset>
8208 <bitWidth>2</bitWidth>
8209 <access>read-write</access>
8210 </field>
8211 <field>
8212 <name>RTCPRE</name>
8213 <description>HSE division factor for RTC
8214 clock</description>
8215 <bitOffset>16</bitOffset>
8216 <bitWidth>5</bitWidth>
8217 <access>read-write</access>
8218 </field>
8219 <field>
8220 <name>PPRE2</name>
8221 <description>APB high-speed prescaler
8222 (APB2)</description>
8223 <bitOffset>13</bitOffset>
8224 <bitWidth>3</bitWidth>
8225 <access>read-write</access>
8226 </field>
8227 <field>
8228 <name>PPRE1</name>
8229 <description>APB Low speed prescaler
8230 (APB1)</description>
8231 <bitOffset>10</bitOffset>
8232 <bitWidth>3</bitWidth>
8233 <access>read-write</access>
8234 </field>
8235 <field>
8236 <name>HPRE</name>
8237 <description>AHB prescaler</description>
8238 <bitOffset>4</bitOffset>
8239 <bitWidth>4</bitWidth>
8240 <access>read-write</access>
8241 </field>
8242 <field>
8243 <name>SWS1</name>
8244 <description>System clock switch status</description>
8245 <bitOffset>3</bitOffset>
8246 <bitWidth>1</bitWidth>
8247 <access>read-only</access>
8248 </field>
8249 <field>
8250 <name>SWS0</name>
8251 <description>System clock switch status</description>
8252 <bitOffset>2</bitOffset>
8253 <bitWidth>1</bitWidth>
8254 <access>read-only</access>
8255 </field>
8256 <field>
8257 <name>SW1</name>
8258 <description>System clock switch</description>
8259 <bitOffset>1</bitOffset>
8260 <bitWidth>1</bitWidth>
8261 <access>read-write</access>
8262 </field>
8263 <field>
8264 <name>SW0</name>
8265 <description>System clock switch</description>
8266 <bitOffset>0</bitOffset>
8267 <bitWidth>1</bitWidth>
8268 <access>read-write</access>
8269 </field>
8270 </fields>
8271 </register>
8272 <register>
8273 <name>CIR</name>
8274 <displayName>CIR</displayName>
8275 <description>clock interrupt register</description>
8276 <addressOffset>0xC</addressOffset>
8277 <size>0x20</size>
8278 <resetValue>0x00000000</resetValue>
8279 <fields>
8280 <field>
8281 <name>CSSC</name>
8282 <description>Clock security system interrupt
8283 clear</description>
8284 <bitOffset>23</bitOffset>
8285 <bitWidth>1</bitWidth>
8286 <access>write-only</access>
8287 </field>
8288 <field>
8289 <name>PLLI2SRDYC</name>
8290 <description>PLLI2S ready interrupt
8291 clear</description>
8292 <bitOffset>21</bitOffset>
8293 <bitWidth>1</bitWidth>
8294 <access>write-only</access>
8295 </field>
8296 <field>
8297 <name>PLLRDYC</name>
8298 <description>Main PLL(PLL) ready interrupt
8299 clear</description>
8300 <bitOffset>20</bitOffset>
8301 <bitWidth>1</bitWidth>
8302 <access>write-only</access>
8303 </field>
8304 <field>
8305 <name>HSERDYC</name>
8306 <description>HSE ready interrupt clear</description>
8307 <bitOffset>19</bitOffset>
8308 <bitWidth>1</bitWidth>
8309 <access>write-only</access>
8310 </field>
8311 <field>
8312 <name>HSIRDYC</name>
8313 <description>HSI ready interrupt clear</description>
8314 <bitOffset>18</bitOffset>
8315 <bitWidth>1</bitWidth>
8316 <access>write-only</access>
8317 </field>
8318 <field>
8319 <name>LSERDYC</name>
8320 <description>LSE ready interrupt clear</description>
8321 <bitOffset>17</bitOffset>
8322 <bitWidth>1</bitWidth>
8323 <access>write-only</access>
8324 </field>
8325 <field>
8326 <name>LSIRDYC</name>
8327 <description>LSI ready interrupt clear</description>
8328 <bitOffset>16</bitOffset>
8329 <bitWidth>1</bitWidth>
8330 <access>write-only</access>
8331 </field>
8332 <field>
8333 <name>PLLI2SRDYIE</name>
8334 <description>PLLI2S ready interrupt
8335 enable</description>
8336 <bitOffset>13</bitOffset>
8337 <bitWidth>1</bitWidth>
8338 <access>read-write</access>
8339 </field>
8340 <field>
8341 <name>PLLRDYIE</name>
8342 <description>Main PLL (PLL) ready interrupt
8343 enable</description>
8344 <bitOffset>12</bitOffset>
8345 <bitWidth>1</bitWidth>
8346 <access>read-write</access>
8347 </field>
8348 <field>
8349 <name>HSERDYIE</name>
8350 <description>HSE ready interrupt enable</description>
8351 <bitOffset>11</bitOffset>
8352 <bitWidth>1</bitWidth>
8353 <access>read-write</access>
8354 </field>
8355 <field>
8356 <name>HSIRDYIE</name>
8357 <description>HSI ready interrupt enable</description>
8358 <bitOffset>10</bitOffset>
8359 <bitWidth>1</bitWidth>
8360 <access>read-write</access>
8361 </field>
8362 <field>
8363 <name>LSERDYIE</name>
8364 <description>LSE ready interrupt enable</description>
8365 <bitOffset>9</bitOffset>
8366 <bitWidth>1</bitWidth>
8367 <access>read-write</access>
8368 </field>
8369 <field>
8370 <name>LSIRDYIE</name>
8371 <description>LSI ready interrupt enable</description>
8372 <bitOffset>8</bitOffset>
8373 <bitWidth>1</bitWidth>
8374 <access>read-write</access>
8375 </field>
8376 <field>
8377 <name>CSSF</name>
8378 <description>Clock security system interrupt
8379 flag</description>
8380 <bitOffset>7</bitOffset>
8381 <bitWidth>1</bitWidth>
8382 <access>read-only</access>
8383 </field>
8384 <field>
8385 <name>PLLI2SRDYF</name>
8386 <description>PLLI2S ready interrupt
8387 flag</description>
8388 <bitOffset>5</bitOffset>
8389 <bitWidth>1</bitWidth>
8390 <access>read-only</access>
8391 </field>
8392 <field>
8393 <name>PLLRDYF</name>
8394 <description>Main PLL (PLL) ready interrupt
8395 flag</description>
8396 <bitOffset>4</bitOffset>
8397 <bitWidth>1</bitWidth>
8398 <access>read-only</access>
8399 </field>
8400 <field>
8401 <name>HSERDYF</name>
8402 <description>HSE ready interrupt flag</description>
8403 <bitOffset>3</bitOffset>
8404 <bitWidth>1</bitWidth>
8405 <access>read-only</access>
8406 </field>
8407 <field>
8408 <name>HSIRDYF</name>
8409 <description>HSI ready interrupt flag</description>
8410 <bitOffset>2</bitOffset>
8411 <bitWidth>1</bitWidth>
8412 <access>read-only</access>
8413 </field>
8414 <field>
8415 <name>LSERDYF</name>
8416 <description>LSE ready interrupt flag</description>
8417 <bitOffset>1</bitOffset>
8418 <bitWidth>1</bitWidth>
8419 <access>read-only</access>
8420 </field>
8421 <field>
8422 <name>LSIRDYF</name>
8423 <description>LSI ready interrupt flag</description>
8424 <bitOffset>0</bitOffset>
8425 <bitWidth>1</bitWidth>
8426 <access>read-only</access>
8427 </field>
8428 </fields>
8429 </register>
8430 <register>
8431 <name>AHB1RSTR</name>
8432 <displayName>AHB1RSTR</displayName>
8433 <description>AHB1 peripheral reset register</description>
8434 <addressOffset>0x10</addressOffset>
8435 <size>0x20</size>
8436 <access>read-write</access>
8437 <resetValue>0x00000000</resetValue>
8438 <fields>
8439 <field>
8440 <name>DMA2RST</name>
8441 <description>DMA2 reset</description>
8442 <bitOffset>22</bitOffset>
8443 <bitWidth>1</bitWidth>
8444 </field>
8445 <field>
8446 <name>DMA1RST</name>
8447 <description>DMA2 reset</description>
8448 <bitOffset>21</bitOffset>
8449 <bitWidth>1</bitWidth>
8450 </field>
8451 <field>
8452 <name>CRCRST</name>
8453 <description>CRC reset</description>
8454 <bitOffset>12</bitOffset>
8455 <bitWidth>1</bitWidth>
8456 </field>
8457 <field>
8458 <name>GPIOHRST</name>
8459 <description>IO port H reset</description>
8460 <bitOffset>7</bitOffset>
8461 <bitWidth>1</bitWidth>
8462 </field>
8463 <field>
8464 <name>GPIOERST</name>
8465 <description>IO port E reset</description>
8466 <bitOffset>4</bitOffset>
8467 <bitWidth>1</bitWidth>
8468 </field>
8469 <field>
8470 <name>GPIODRST</name>
8471 <description>IO port D reset</description>
8472 <bitOffset>3</bitOffset>
8473 <bitWidth>1</bitWidth>
8474 </field>
8475 <field>
8476 <name>GPIOCRST</name>
8477 <description>IO port C reset</description>
8478 <bitOffset>2</bitOffset>
8479 <bitWidth>1</bitWidth>
8480 </field>
8481 <field>
8482 <name>GPIOBRST</name>
8483 <description>IO port B reset</description>
8484 <bitOffset>1</bitOffset>
8485 <bitWidth>1</bitWidth>
8486 </field>
8487 <field>
8488 <name>GPIOARST</name>
8489 <description>IO port A reset</description>
8490 <bitOffset>0</bitOffset>
8491 <bitWidth>1</bitWidth>
8492 </field>
8493 </fields>
8494 </register>
8495 <register>
8496 <name>AHB2RSTR</name>
8497 <displayName>AHB2RSTR</displayName>
8498 <description>AHB2 peripheral reset register</description>
8499 <addressOffset>0x14</addressOffset>
8500 <size>0x20</size>
8501 <access>read-write</access>
8502 <resetValue>0x00000000</resetValue>
8503 <fields>
8504 <field>
8505 <name>OTGFSRST</name>
8506 <description>USB OTG FS module reset</description>
8507 <bitOffset>7</bitOffset>
8508 <bitWidth>1</bitWidth>
8509 </field>
8510 </fields>
8511 </register>
8512 <register>
8513 <name>APB1RSTR</name>
8514 <displayName>APB1RSTR</displayName>
8515 <description>APB1 peripheral reset register</description>
8516 <addressOffset>0x20</addressOffset>
8517 <size>0x20</size>
8518 <access>read-write</access>
8519 <resetValue>0x00000000</resetValue>
8520 <fields>
8521 <field>
8522 <name>PWRRST</name>
8523 <description>Power interface reset</description>
8524 <bitOffset>28</bitOffset>
8525 <bitWidth>1</bitWidth>
8526 </field>
8527 <field>
8528 <name>I2C3RST</name>
8529 <description>I2C3 reset</description>
8530 <bitOffset>23</bitOffset>
8531 <bitWidth>1</bitWidth>
8532 </field>
8533 <field>
8534 <name>I2C2RST</name>
8535 <description>I2C 2 reset</description>
8536 <bitOffset>22</bitOffset>
8537 <bitWidth>1</bitWidth>
8538 </field>
8539 <field>
8540 <name>I2C1RST</name>
8541 <description>I2C 1 reset</description>
8542 <bitOffset>21</bitOffset>
8543 <bitWidth>1</bitWidth>
8544 </field>
8545 <field>
8546 <name>UART2RST</name>
8547 <description>USART 2 reset</description>
8548 <bitOffset>17</bitOffset>
8549 <bitWidth>1</bitWidth>
8550 </field>
8551 <field>
8552 <name>SPI3RST</name>
8553 <description>SPI 3 reset</description>
8554 <bitOffset>15</bitOffset>
8555 <bitWidth>1</bitWidth>
8556 </field>
8557 <field>
8558 <name>SPI2RST</name>
8559 <description>SPI 2 reset</description>
8560 <bitOffset>14</bitOffset>
8561 <bitWidth>1</bitWidth>
8562 </field>
8563 <field>
8564 <name>WWDGRST</name>
8565 <description>Window watchdog reset</description>
8566 <bitOffset>11</bitOffset>
8567 <bitWidth>1</bitWidth>
8568 </field>
8569 <field>
8570 <name>TIM5RST</name>
8571 <description>TIM5 reset</description>
8572 <bitOffset>3</bitOffset>
8573 <bitWidth>1</bitWidth>
8574 </field>
8575 <field>
8576 <name>TIM4RST</name>
8577 <description>TIM4 reset</description>
8578 <bitOffset>2</bitOffset>
8579 <bitWidth>1</bitWidth>
8580 </field>
8581 <field>
8582 <name>TIM3RST</name>
8583 <description>TIM3 reset</description>
8584 <bitOffset>1</bitOffset>
8585 <bitWidth>1</bitWidth>
8586 </field>
8587 <field>
8588 <name>TIM2RST</name>
8589 <description>TIM2 reset</description>
8590 <bitOffset>0</bitOffset>
8591 <bitWidth>1</bitWidth>
8592 </field>
8593 </fields>
8594 </register>
8595 <register>
8596 <name>APB2RSTR</name>
8597 <displayName>APB2RSTR</displayName>
8598 <description>APB2 peripheral reset register</description>
8599 <addressOffset>0x24</addressOffset>
8600 <size>0x20</size>
8601 <access>read-write</access>
8602 <resetValue>0x00000000</resetValue>
8603 <fields>
8604 <field>
8605 <name>TIM11RST</name>
8606 <description>TIM11 reset</description>
8607 <bitOffset>18</bitOffset>
8608 <bitWidth>1</bitWidth>
8609 </field>
8610 <field>
8611 <name>TIM10RST</name>
8612 <description>TIM10 reset</description>
8613 <bitOffset>17</bitOffset>
8614 <bitWidth>1</bitWidth>
8615 </field>
8616 <field>
8617 <name>TIM9RST</name>
8618 <description>TIM9 reset</description>
8619 <bitOffset>16</bitOffset>
8620 <bitWidth>1</bitWidth>
8621 </field>
8622 <field>
8623 <name>SYSCFGRST</name>
8624 <description>System configuration controller
8625 reset</description>
8626 <bitOffset>14</bitOffset>
8627 <bitWidth>1</bitWidth>
8628 </field>
8629 <field>
8630 <name>SPI1RST</name>
8631 <description>SPI 1 reset</description>
8632 <bitOffset>12</bitOffset>
8633 <bitWidth>1</bitWidth>
8634 </field>
8635 <field>
8636 <name>SDIORST</name>
8637 <description>SDIO reset</description>
8638 <bitOffset>11</bitOffset>
8639 <bitWidth>1</bitWidth>
8640 </field>
8641 <field>
8642 <name>ADCRST</name>
8643 <description>ADC interface reset (common to all
8644 ADCs)</description>
8645 <bitOffset>8</bitOffset>
8646 <bitWidth>1</bitWidth>
8647 </field>
8648 <field>
8649 <name>USART6RST</name>
8650 <description>USART6 reset</description>
8651 <bitOffset>5</bitOffset>
8652 <bitWidth>1</bitWidth>
8653 </field>
8654 <field>
8655 <name>USART1RST</name>
8656 <description>USART1 reset</description>
8657 <bitOffset>4</bitOffset>
8658 <bitWidth>1</bitWidth>
8659 </field>
8660 <field>
8661 <name>TIM1RST</name>
8662 <description>TIM1 reset</description>
8663 <bitOffset>0</bitOffset>
8664 <bitWidth>1</bitWidth>
8665 </field>
8666 </fields>
8667 </register>
8668 <register>
8669 <name>AHB1ENR</name>
8670 <displayName>AHB1ENR</displayName>
8671 <description>AHB1 peripheral clock register</description>
8672 <addressOffset>0x30</addressOffset>
8673 <size>0x20</size>
8674 <access>read-write</access>
8675 <resetValue>0x00100000</resetValue>
8676 <fields>
8677 <field>
8678 <name>DMA2EN</name>
8679 <description>DMA2 clock enable</description>
8680 <bitOffset>22</bitOffset>
8681 <bitWidth>1</bitWidth>
8682 </field>
8683 <field>
8684 <name>DMA1EN</name>
8685 <description>DMA1 clock enable</description>
8686 <bitOffset>21</bitOffset>
8687 <bitWidth>1</bitWidth>
8688 </field>
8689 <field>
8690 <name>CRCEN</name>
8691 <description>CRC clock enable</description>
8692 <bitOffset>12</bitOffset>
8693 <bitWidth>1</bitWidth>
8694 </field>
8695 <field>
8696 <name>GPIOHEN</name>
8697 <description>IO port H clock enable</description>
8698 <bitOffset>7</bitOffset>
8699 <bitWidth>1</bitWidth>
8700 </field>
8701 <field>
8702 <name>GPIOEEN</name>
8703 <description>IO port E clock enable</description>
8704 <bitOffset>4</bitOffset>
8705 <bitWidth>1</bitWidth>
8706 </field>
8707 <field>
8708 <name>GPIODEN</name>
8709 <description>IO port D clock enable</description>
8710 <bitOffset>3</bitOffset>
8711 <bitWidth>1</bitWidth>
8712 </field>
8713 <field>
8714 <name>GPIOCEN</name>
8715 <description>IO port C clock enable</description>
8716 <bitOffset>2</bitOffset>
8717 <bitWidth>1</bitWidth>
8718 </field>
8719 <field>
8720 <name>GPIOBEN</name>
8721 <description>IO port B clock enable</description>
8722 <bitOffset>1</bitOffset>
8723 <bitWidth>1</bitWidth>
8724 </field>
8725 <field>
8726 <name>GPIOAEN</name>
8727 <description>IO port A clock enable</description>
8728 <bitOffset>0</bitOffset>
8729 <bitWidth>1</bitWidth>
8730 </field>
8731 </fields>
8732 </register>
8733 <register>
8734 <name>AHB2ENR</name>
8735 <displayName>AHB2ENR</displayName>
8736 <description>AHB2 peripheral clock enable
8737 register</description>
8738 <addressOffset>0x34</addressOffset>
8739 <size>0x20</size>
8740 <access>read-write</access>
8741 <resetValue>0x00000000</resetValue>
8742 <fields>
8743 <field>
8744 <name>OTGFSEN</name>
8745 <description>USB OTG FS clock enable</description>
8746 <bitOffset>7</bitOffset>
8747 <bitWidth>1</bitWidth>
8748 </field>
8749 </fields>
8750 </register>
8751 <register>
8752 <name>APB1ENR</name>
8753 <displayName>APB1ENR</displayName>
8754 <description>APB1 peripheral clock enable
8755 register</description>
8756 <addressOffset>0x40</addressOffset>
8757 <size>0x20</size>
8758 <access>read-write</access>
8759 <resetValue>0x00000000</resetValue>
8760 <fields>
8761 <field>
8762 <name>PWREN</name>
8763 <description>Power interface clock
8764 enable</description>
8765 <bitOffset>28</bitOffset>
8766 <bitWidth>1</bitWidth>
8767 </field>
8768 <field>
8769 <name>I2C3EN</name>
8770 <description>I2C3 clock enable</description>
8771 <bitOffset>23</bitOffset>
8772 <bitWidth>1</bitWidth>
8773 </field>
8774 <field>
8775 <name>I2C2EN</name>
8776 <description>I2C2 clock enable</description>
8777 <bitOffset>22</bitOffset>
8778 <bitWidth>1</bitWidth>
8779 </field>
8780 <field>
8781 <name>I2C1EN</name>
8782 <description>I2C1 clock enable</description>
8783 <bitOffset>21</bitOffset>
8784 <bitWidth>1</bitWidth>
8785 </field>
8786 <field>
8787 <name>USART2EN</name>
8788 <description>USART 2 clock enable</description>
8789 <bitOffset>17</bitOffset>
8790 <bitWidth>1</bitWidth>
8791 </field>
8792 <field>
8793 <name>SPI3EN</name>
8794 <description>SPI3 clock enable</description>
8795 <bitOffset>15</bitOffset>
8796 <bitWidth>1</bitWidth>
8797 </field>
8798 <field>
8799 <name>SPI2EN</name>
8800 <description>SPI2 clock enable</description>
8801 <bitOffset>14</bitOffset>
8802 <bitWidth>1</bitWidth>
8803 </field>
8804 <field>
8805 <name>WWDGEN</name>
8806 <description>Window watchdog clock
8807 enable</description>
8808 <bitOffset>11</bitOffset>
8809 <bitWidth>1</bitWidth>
8810 </field>
8811 <field>
8812 <name>TIM5EN</name>
8813 <description>TIM5 clock enable</description>
8814 <bitOffset>3</bitOffset>
8815 <bitWidth>1</bitWidth>
8816 </field>
8817 <field>
8818 <name>TIM4EN</name>
8819 <description>TIM4 clock enable</description>
8820 <bitOffset>2</bitOffset>
8821 <bitWidth>1</bitWidth>
8822 </field>
8823 <field>
8824 <name>TIM3EN</name>
8825 <description>TIM3 clock enable</description>
8826 <bitOffset>1</bitOffset>
8827 <bitWidth>1</bitWidth>
8828 </field>
8829 <field>
8830 <name>TIM2EN</name>
8831 <description>TIM2 clock enable</description>
8832 <bitOffset>0</bitOffset>
8833 <bitWidth>1</bitWidth>
8834 </field>
8835 </fields>
8836 </register>
8837 <register>
8838 <name>APB2ENR</name>
8839 <displayName>APB2ENR</displayName>
8840 <description>APB2 peripheral clock enable
8841 register</description>
8842 <addressOffset>0x44</addressOffset>
8843 <size>0x20</size>
8844 <access>read-write</access>
8845 <resetValue>0x00000000</resetValue>
8846 <fields>
8847 <field>
8848 <name>TIM1EN</name>
8849 <description>TIM1 clock enable</description>
8850 <bitOffset>0</bitOffset>
8851 <bitWidth>1</bitWidth>
8852 </field>
8853 <field>
8854 <name>USART1EN</name>
8855 <description>USART1 clock enable</description>
8856 <bitOffset>4</bitOffset>
8857 <bitWidth>1</bitWidth>
8858 </field>
8859 <field>
8860 <name>USART6EN</name>
8861 <description>USART6 clock enable</description>
8862 <bitOffset>5</bitOffset>
8863 <bitWidth>1</bitWidth>
8864 </field>
8865 <field>
8866 <name>ADC1EN</name>
8867 <description>ADC1 clock enable</description>
8868 <bitOffset>8</bitOffset>
8869 <bitWidth>1</bitWidth>
8870 </field>
8871 <field>
8872 <name>SDIOEN</name>
8873 <description>SDIO clock enable</description>
8874 <bitOffset>11</bitOffset>
8875 <bitWidth>1</bitWidth>
8876 </field>
8877 <field>
8878 <name>SPI1EN</name>
8879 <description>SPI1 clock enable</description>
8880 <bitOffset>12</bitOffset>
8881 <bitWidth>1</bitWidth>
8882 </field>
8883 <field>
8884 <name>SPI4EN</name>
8885 <description>SPI4 clock enable</description>
8886 <bitOffset>13</bitOffset>
8887 <bitWidth>1</bitWidth>
8888 </field>
8889 <field>
8890 <name>SYSCFGEN</name>
8891 <description>System configuration controller clock
8892 enable</description>
8893 <bitOffset>14</bitOffset>
8894 <bitWidth>1</bitWidth>
8895 </field>
8896 <field>
8897 <name>TIM9EN</name>
8898 <description>TIM9 clock enable</description>
8899 <bitOffset>16</bitOffset>
8900 <bitWidth>1</bitWidth>
8901 </field>
8902 <field>
8903 <name>TIM10EN</name>
8904 <description>TIM10 clock enable</description>
8905 <bitOffset>17</bitOffset>
8906 <bitWidth>1</bitWidth>
8907 </field>
8908 <field>
8909 <name>TIM11EN</name>
8910 <description>TIM11 clock enable</description>
8911 <bitOffset>18</bitOffset>
8912 <bitWidth>1</bitWidth>
8913 </field>
8914 </fields>
8915 </register>
8916 <register>
8917 <name>AHB1LPENR</name>
8918 <displayName>AHB1LPENR</displayName>
8919 <description>AHB1 peripheral clock enable in low power
8920 mode register</description>
8921 <addressOffset>0x50</addressOffset>
8922 <size>0x20</size>
8923 <access>read-write</access>
8924 <resetValue>0x7E6791FF</resetValue>
8925 <fields>
8926 <field>
8927 <name>DMA2LPEN</name>
8928 <description>DMA2 clock enable during Sleep
8929 mode</description>
8930 <bitOffset>22</bitOffset>
8931 <bitWidth>1</bitWidth>
8932 </field>
8933 <field>
8934 <name>DMA1LPEN</name>
8935 <description>DMA1 clock enable during Sleep
8936 mode</description>
8937 <bitOffset>21</bitOffset>
8938 <bitWidth>1</bitWidth>
8939 </field>
8940 <field>
8941 <name>SRAM1LPEN</name>
8942 <description>SRAM 1interface clock enable during
8943 Sleep mode</description>
8944 <bitOffset>16</bitOffset>
8945 <bitWidth>1</bitWidth>
8946 </field>
8947 <field>
8948 <name>FLITFLPEN</name>
8949 <description>Flash interface clock enable during
8950 Sleep mode</description>
8951 <bitOffset>15</bitOffset>
8952 <bitWidth>1</bitWidth>
8953 </field>
8954 <field>
8955 <name>CRCLPEN</name>
8956 <description>CRC clock enable during Sleep
8957 mode</description>
8958 <bitOffset>12</bitOffset>
8959 <bitWidth>1</bitWidth>
8960 </field>
8961 <field>
8962 <name>GPIOHLPEN</name>
8963 <description>IO port H clock enable during Sleep
8964 mode</description>
8965 <bitOffset>7</bitOffset>
8966 <bitWidth>1</bitWidth>
8967 </field>
8968 <field>
8969 <name>GPIOELPEN</name>
8970 <description>IO port E clock enable during Sleep
8971 mode</description>
8972 <bitOffset>4</bitOffset>
8973 <bitWidth>1</bitWidth>
8974 </field>
8975 <field>
8976 <name>GPIODLPEN</name>
8977 <description>IO port D clock enable during Sleep
8978 mode</description>
8979 <bitOffset>3</bitOffset>
8980 <bitWidth>1</bitWidth>
8981 </field>
8982 <field>
8983 <name>GPIOCLPEN</name>
8984 <description>IO port C clock enable during Sleep
8985 mode</description>
8986 <bitOffset>2</bitOffset>
8987 <bitWidth>1</bitWidth>
8988 </field>
8989 <field>
8990 <name>GPIOBLPEN</name>
8991 <description>IO port B clock enable during Sleep
8992 mode</description>
8993 <bitOffset>1</bitOffset>
8994 <bitWidth>1</bitWidth>
8995 </field>
8996 <field>
8997 <name>GPIOALPEN</name>
8998 <description>IO port A clock enable during sleep
8999 mode</description>
9000 <bitOffset>0</bitOffset>
9001 <bitWidth>1</bitWidth>
9002 </field>
9003 </fields>
9004 </register>
9005 <register>
9006 <name>AHB2LPENR</name>
9007 <displayName>AHB2LPENR</displayName>
9008 <description>AHB2 peripheral clock enable in low power
9009 mode register</description>
9010 <addressOffset>0x54</addressOffset>
9011 <size>0x20</size>
9012 <access>read-write</access>
9013 <resetValue>0x000000F1</resetValue>
9014 <fields>
9015 <field>
9016 <name>OTGFSLPEN</name>
9017 <description>USB OTG FS clock enable during Sleep
9018 mode</description>
9019 <bitOffset>7</bitOffset>
9020 <bitWidth>1</bitWidth>
9021 </field>
9022 </fields>
9023 </register>
9024 <register>
9025 <name>APB1LPENR</name>
9026 <displayName>APB1LPENR</displayName>
9027 <description>APB1 peripheral clock enable in low power
9028 mode register</description>
9029 <addressOffset>0x60</addressOffset>
9030 <size>0x20</size>
9031 <access>read-write</access>
9032 <resetValue>0x36FEC9FF</resetValue>
9033 <fields>
9034 <field>
9035 <name>PWRLPEN</name>
9036 <description>Power interface clock enable during
9037 Sleep mode</description>
9038 <bitOffset>28</bitOffset>
9039 <bitWidth>1</bitWidth>
9040 </field>
9041 <field>
9042 <name>I2C3LPEN</name>
9043 <description>I2C3 clock enable during Sleep
9044 mode</description>
9045 <bitOffset>23</bitOffset>
9046 <bitWidth>1</bitWidth>
9047 </field>
9048 <field>
9049 <name>I2C2LPEN</name>
9050 <description>I2C2 clock enable during Sleep
9051 mode</description>
9052 <bitOffset>22</bitOffset>
9053 <bitWidth>1</bitWidth>
9054 </field>
9055 <field>
9056 <name>I2C1LPEN</name>
9057 <description>I2C1 clock enable during Sleep
9058 mode</description>
9059 <bitOffset>21</bitOffset>
9060 <bitWidth>1</bitWidth>
9061 </field>
9062 <field>
9063 <name>USART2LPEN</name>
9064 <description>USART2 clock enable during Sleep
9065 mode</description>
9066 <bitOffset>17</bitOffset>
9067 <bitWidth>1</bitWidth>
9068 </field>
9069 <field>
9070 <name>SPI3LPEN</name>
9071 <description>SPI3 clock enable during Sleep
9072 mode</description>
9073 <bitOffset>15</bitOffset>
9074 <bitWidth>1</bitWidth>
9075 </field>
9076 <field>
9077 <name>SPI2LPEN</name>
9078 <description>SPI2 clock enable during Sleep
9079 mode</description>
9080 <bitOffset>14</bitOffset>
9081 <bitWidth>1</bitWidth>
9082 </field>
9083 <field>
9084 <name>WWDGLPEN</name>
9085 <description>Window watchdog clock enable during
9086 Sleep mode</description>
9087 <bitOffset>11</bitOffset>
9088 <bitWidth>1</bitWidth>
9089 </field>
9090 <field>
9091 <name>TIM5LPEN</name>
9092 <description>TIM5 clock enable during Sleep
9093 mode</description>
9094 <bitOffset>3</bitOffset>
9095 <bitWidth>1</bitWidth>
9096 </field>
9097 <field>
9098 <name>TIM4LPEN</name>
9099 <description>TIM4 clock enable during Sleep
9100 mode</description>
9101 <bitOffset>2</bitOffset>
9102 <bitWidth>1</bitWidth>
9103 </field>
9104 <field>
9105 <name>TIM3LPEN</name>
9106 <description>TIM3 clock enable during Sleep
9107 mode</description>
9108 <bitOffset>1</bitOffset>
9109 <bitWidth>1</bitWidth>
9110 </field>
9111 <field>
9112 <name>TIM2LPEN</name>
9113 <description>TIM2 clock enable during Sleep
9114 mode</description>
9115 <bitOffset>0</bitOffset>
9116 <bitWidth>1</bitWidth>
9117 </field>
9118 </fields>
9119 </register>
9120 <register>
9121 <name>APB2LPENR</name>
9122 <displayName>APB2LPENR</displayName>
9123 <description>APB2 peripheral clock enabled in low power
9124 mode register</description>
9125 <addressOffset>0x64</addressOffset>
9126 <size>0x20</size>
9127 <access>read-write</access>
9128 <resetValue>0x00075F33</resetValue>
9129 <fields>
9130 <field>
9131 <name>TIM1LPEN</name>
9132 <description>TIM1 clock enable during Sleep
9133 mode</description>
9134 <bitOffset>0</bitOffset>
9135 <bitWidth>1</bitWidth>
9136 </field>
9137 <field>
9138 <name>USART1LPEN</name>
9139 <description>USART1 clock enable during Sleep
9140 mode</description>
9141 <bitOffset>4</bitOffset>
9142 <bitWidth>1</bitWidth>
9143 </field>
9144 <field>
9145 <name>USART6LPEN</name>
9146 <description>USART6 clock enable during Sleep
9147 mode</description>
9148 <bitOffset>5</bitOffset>
9149 <bitWidth>1</bitWidth>
9150 </field>
9151 <field>
9152 <name>ADC1LPEN</name>
9153 <description>ADC1 clock enable during Sleep
9154 mode</description>
9155 <bitOffset>8</bitOffset>
9156 <bitWidth>1</bitWidth>
9157 </field>
9158 <field>
9159 <name>SDIOLPEN</name>
9160 <description>SDIO clock enable during Sleep
9161 mode</description>
9162 <bitOffset>11</bitOffset>
9163 <bitWidth>1</bitWidth>
9164 </field>
9165 <field>
9166 <name>SPI1LPEN</name>
9167 <description>SPI 1 clock enable during Sleep
9168 mode</description>
9169 <bitOffset>12</bitOffset>
9170 <bitWidth>1</bitWidth>
9171 </field>
9172 <field>
9173 <name>SPI4LPEN</name>
9174 <description>SPI4 clock enable during Sleep
9175 mode</description>
9176 <bitOffset>13</bitOffset>
9177 <bitWidth>1</bitWidth>
9178 </field>
9179 <field>
9180 <name>SYSCFGLPEN</name>
9181 <description>System configuration controller clock
9182 enable during Sleep mode</description>
9183 <bitOffset>14</bitOffset>
9184 <bitWidth>1</bitWidth>
9185 </field>
9186 <field>
9187 <name>TIM9LPEN</name>
9188 <description>TIM9 clock enable during sleep
9189 mode</description>
9190 <bitOffset>16</bitOffset>
9191 <bitWidth>1</bitWidth>
9192 </field>
9193 <field>
9194 <name>TIM10LPEN</name>
9195 <description>TIM10 clock enable during Sleep
9196 mode</description>
9197 <bitOffset>17</bitOffset>
9198 <bitWidth>1</bitWidth>
9199 </field>
9200 <field>
9201 <name>TIM11LPEN</name>
9202 <description>TIM11 clock enable during Sleep
9203 mode</description>
9204 <bitOffset>18</bitOffset>
9205 <bitWidth>1</bitWidth>
9206 </field>
9207 </fields>
9208 </register>
9209 <register>
9210 <name>BDCR</name>
9211 <displayName>BDCR</displayName>
9212 <description>Backup domain control register</description>
9213 <addressOffset>0x70</addressOffset>
9214 <size>0x20</size>
9215 <resetValue>0x00000000</resetValue>
9216 <fields>
9217 <field>
9218 <name>BDRST</name>
9219 <description>Backup domain software
9220 reset</description>
9221 <bitOffset>16</bitOffset>
9222 <bitWidth>1</bitWidth>
9223 <access>read-write</access>
9224 </field>
9225 <field>
9226 <name>RTCEN</name>
9227 <description>RTC clock enable</description>
9228 <bitOffset>15</bitOffset>
9229 <bitWidth>1</bitWidth>
9230 <access>read-write</access>
9231 </field>
9232 <field>
9233 <name>RTCSEL1</name>
9234 <description>RTC clock source selection</description>
9235 <bitOffset>9</bitOffset>
9236 <bitWidth>1</bitWidth>
9237 <access>read-write</access>
9238 </field>
9239 <field>
9240 <name>RTCSEL0</name>
9241 <description>RTC clock source selection</description>
9242 <bitOffset>8</bitOffset>
9243 <bitWidth>1</bitWidth>
9244 <access>read-write</access>
9245 </field>
9246 <field>
9247 <name>LSEBYP</name>
9248 <description>External low-speed oscillator
9249 bypass</description>
9250 <bitOffset>2</bitOffset>
9251 <bitWidth>1</bitWidth>
9252 <access>read-write</access>
9253 </field>
9254 <field>
9255 <name>LSERDY</name>
9256 <description>External low-speed oscillator
9257 ready</description>
9258 <bitOffset>1</bitOffset>
9259 <bitWidth>1</bitWidth>
9260 <access>read-only</access>
9261 </field>
9262 <field>
9263 <name>LSEON</name>
9264 <description>External low-speed oscillator
9265 enable</description>
9266 <bitOffset>0</bitOffset>
9267 <bitWidth>1</bitWidth>
9268 <access>read-write</access>
9269 </field>
9270 </fields>
9271 </register>
9272 <register>
9273 <name>CSR</name>
9274 <displayName>CSR</displayName>
9275 <description>clock control &amp; status
9276 register</description>
9277 <addressOffset>0x74</addressOffset>
9278 <size>0x20</size>
9279 <resetValue>0x0E000000</resetValue>
9280 <fields>
9281 <field>
9282 <name>LPWRRSTF</name>
9283 <description>Low-power reset flag</description>
9284 <bitOffset>31</bitOffset>
9285 <bitWidth>1</bitWidth>
9286 <access>read-write</access>
9287 </field>
9288 <field>
9289 <name>WWDGRSTF</name>
9290 <description>Window watchdog reset flag</description>
9291 <bitOffset>30</bitOffset>
9292 <bitWidth>1</bitWidth>
9293 <access>read-write</access>
9294 </field>
9295 <field>
9296 <name>WDGRSTF</name>
9297 <description>Independent watchdog reset
9298 flag</description>
9299 <bitOffset>29</bitOffset>
9300 <bitWidth>1</bitWidth>
9301 <access>read-write</access>
9302 </field>
9303 <field>
9304 <name>SFTRSTF</name>
9305 <description>Software reset flag</description>
9306 <bitOffset>28</bitOffset>
9307 <bitWidth>1</bitWidth>
9308 <access>read-write</access>
9309 </field>
9310 <field>
9311 <name>PORRSTF</name>
9312 <description>POR/PDR reset flag</description>
9313 <bitOffset>27</bitOffset>
9314 <bitWidth>1</bitWidth>
9315 <access>read-write</access>
9316 </field>
9317 <field>
9318 <name>PADRSTF</name>
9319 <description>PIN reset flag</description>
9320 <bitOffset>26</bitOffset>
9321 <bitWidth>1</bitWidth>
9322 <access>read-write</access>
9323 </field>
9324 <field>
9325 <name>BORRSTF</name>
9326 <description>BOR reset flag</description>
9327 <bitOffset>25</bitOffset>
9328 <bitWidth>1</bitWidth>
9329 <access>read-write</access>
9330 </field>
9331 <field>
9332 <name>RMVF</name>
9333 <description>Remove reset flag</description>
9334 <bitOffset>24</bitOffset>
9335 <bitWidth>1</bitWidth>
9336 <access>read-write</access>
9337 </field>
9338 <field>
9339 <name>LSIRDY</name>
9340 <description>Internal low-speed oscillator
9341 ready</description>
9342 <bitOffset>1</bitOffset>
9343 <bitWidth>1</bitWidth>
9344 <access>read-only</access>
9345 </field>
9346 <field>
9347 <name>LSION</name>
9348 <description>Internal low-speed oscillator
9349 enable</description>
9350 <bitOffset>0</bitOffset>
9351 <bitWidth>1</bitWidth>
9352 <access>read-write</access>
9353 </field>
9354 </fields>
9355 </register>
9356 <register>
9357 <name>SSCGR</name>
9358 <displayName>SSCGR</displayName>
9359 <description>spread spectrum clock generation
9360 register</description>
9361 <addressOffset>0x80</addressOffset>
9362 <size>0x20</size>
9363 <access>read-write</access>
9364 <resetValue>0x00000000</resetValue>
9365 <fields>
9366 <field>
9367 <name>SSCGEN</name>
9368 <description>Spread spectrum modulation
9369 enable</description>
9370 <bitOffset>31</bitOffset>
9371 <bitWidth>1</bitWidth>
9372 </field>
9373 <field>
9374 <name>SPREADSEL</name>
9375 <description>Spread Select</description>
9376 <bitOffset>30</bitOffset>
9377 <bitWidth>1</bitWidth>
9378 </field>
9379 <field>
9380 <name>INCSTEP</name>
9381 <description>Incrementation step</description>
9382 <bitOffset>13</bitOffset>
9383 <bitWidth>15</bitWidth>
9384 </field>
9385 <field>
9386 <name>MODPER</name>
9387 <description>Modulation period</description>
9388 <bitOffset>0</bitOffset>
9389 <bitWidth>13</bitWidth>
9390 </field>
9391 </fields>
9392 </register>
9393 <register>
9394 <name>PLLI2SCFGR</name>
9395 <displayName>PLLI2SCFGR</displayName>
9396 <description>PLLI2S configuration register</description>
9397 <addressOffset>0x84</addressOffset>
9398 <size>0x20</size>
9399 <access>read-write</access>
9400 <resetValue>0x20003000</resetValue>
9401 <fields>
9402 <field>
9403 <name>PLLI2SRx</name>
9404 <description>PLLI2S division factor for I2S
9405 clocks</description>
9406 <bitOffset>28</bitOffset>
9407 <bitWidth>3</bitWidth>
9408 </field>
9409 <field>
9410 <name>PLLI2SNx</name>
9411 <description>PLLI2S multiplication factor for
9412 VCO</description>
9413 <bitOffset>6</bitOffset>
9414 <bitWidth>9</bitWidth>
9415 </field>
9416 </fields>
9417 </register>
9418 </registers>
9419 </peripheral>
9420 <peripheral>
9421 <name>RTC</name>
9422 <description>Real-time clock</description>
9423 <groupName>RTC</groupName>
9424 <baseAddress>0x40002800</baseAddress>
9425 <addressBlock>
9426 <offset>0x0</offset>
9427 <size>0x400</size>
9428 <usage>registers</usage>
9429 </addressBlock>
9430 <interrupt>
9431 <name>I2C2_EV</name>
9432 <description>I2C2 event interrupt</description>
9433 <value>33</value>
9434 </interrupt>
9435 <interrupt>
9436 <name>I2C2_ER</name>
9437 <description>I2C2 error interrupt</description>
9438 <value>34</value>
9439 </interrupt>
9440 <registers>
9441 <register>
9442 <name>TR</name>
9443 <displayName>TR</displayName>
9444 <description>time register</description>
9445 <addressOffset>0x0</addressOffset>
9446 <size>0x20</size>
9447 <access>read-write</access>
9448 <resetValue>0x00000000</resetValue>
9449 <fields>
9450 <field>
9451 <name>PM</name>
9452 <description>AM/PM notation</description>
9453 <bitOffset>22</bitOffset>
9454 <bitWidth>1</bitWidth>
9455 </field>
9456 <field>
9457 <name>HT</name>
9458 <description>Hour tens in BCD format</description>
9459 <bitOffset>20</bitOffset>
9460 <bitWidth>2</bitWidth>
9461 </field>
9462 <field>
9463 <name>HU</name>
9464 <description>Hour units in BCD format</description>
9465 <bitOffset>16</bitOffset>
9466 <bitWidth>4</bitWidth>
9467 </field>
9468 <field>
9469 <name>MNT</name>
9470 <description>Minute tens in BCD format</description>
9471 <bitOffset>12</bitOffset>
9472 <bitWidth>3</bitWidth>
9473 </field>
9474 <field>
9475 <name>MNU</name>
9476 <description>Minute units in BCD format</description>
9477 <bitOffset>8</bitOffset>
9478 <bitWidth>4</bitWidth>
9479 </field>
9480 <field>
9481 <name>ST</name>
9482 <description>Second tens in BCD format</description>
9483 <bitOffset>4</bitOffset>
9484 <bitWidth>3</bitWidth>
9485 </field>
9486 <field>
9487 <name>SU</name>
9488 <description>Second units in BCD format</description>
9489 <bitOffset>0</bitOffset>
9490 <bitWidth>4</bitWidth>
9491 </field>
9492 </fields>
9493 </register>
9494 <register>
9495 <name>DR</name>
9496 <displayName>DR</displayName>
9497 <description>date register</description>
9498 <addressOffset>0x4</addressOffset>
9499 <size>0x20</size>
9500 <access>read-write</access>
9501 <resetValue>0x00002101</resetValue>
9502 <fields>
9503 <field>
9504 <name>YT</name>
9505 <description>Year tens in BCD format</description>
9506 <bitOffset>20</bitOffset>
9507 <bitWidth>4</bitWidth>
9508 </field>
9509 <field>
9510 <name>YU</name>
9511 <description>Year units in BCD format</description>
9512 <bitOffset>16</bitOffset>
9513 <bitWidth>4</bitWidth>
9514 </field>
9515 <field>
9516 <name>WDU</name>
9517 <description>Week day units</description>
9518 <bitOffset>13</bitOffset>
9519 <bitWidth>3</bitWidth>
9520 </field>
9521 <field>
9522 <name>MT</name>
9523 <description>Month tens in BCD format</description>
9524 <bitOffset>12</bitOffset>
9525 <bitWidth>1</bitWidth>
9526 </field>
9527 <field>
9528 <name>MU</name>
9529 <description>Month units in BCD format</description>
9530 <bitOffset>8</bitOffset>
9531 <bitWidth>4</bitWidth>
9532 </field>
9533 <field>
9534 <name>DT</name>
9535 <description>Date tens in BCD format</description>
9536 <bitOffset>4</bitOffset>
9537 <bitWidth>2</bitWidth>
9538 </field>
9539 <field>
9540 <name>DU</name>
9541 <description>Date units in BCD format</description>
9542 <bitOffset>0</bitOffset>
9543 <bitWidth>4</bitWidth>
9544 </field>
9545 </fields>
9546 </register>
9547 <register>
9548 <name>CR</name>
9549 <displayName>CR</displayName>
9550 <description>control register</description>
9551 <addressOffset>0x8</addressOffset>
9552 <size>0x20</size>
9553 <access>read-write</access>
9554 <resetValue>0x00000000</resetValue>
9555 <fields>
9556 <field>
9557 <name>COE</name>
9558 <description>Calibration output enable</description>
9559 <bitOffset>23</bitOffset>
9560 <bitWidth>1</bitWidth>
9561 </field>
9562 <field>
9563 <name>OSEL</name>
9564 <description>Output selection</description>
9565 <bitOffset>21</bitOffset>
9566 <bitWidth>2</bitWidth>
9567 </field>
9568 <field>
9569 <name>POL</name>
9570 <description>Output polarity</description>
9571 <bitOffset>20</bitOffset>
9572 <bitWidth>1</bitWidth>
9573 </field>
9574 <field>
9575 <name>COSEL</name>
9576 <description>Calibration Output
9577 selection</description>
9578 <bitOffset>19</bitOffset>
9579 <bitWidth>1</bitWidth>
9580 </field>
9581 <field>
9582 <name>BKP</name>
9583 <description>Backup</description>
9584 <bitOffset>18</bitOffset>
9585 <bitWidth>1</bitWidth>
9586 </field>
9587 <field>
9588 <name>SUB1H</name>
9589 <description>Subtract 1 hour (winter time
9590 change)</description>
9591 <bitOffset>17</bitOffset>
9592 <bitWidth>1</bitWidth>
9593 </field>
9594 <field>
9595 <name>ADD1H</name>
9596 <description>Add 1 hour (summer time
9597 change)</description>
9598 <bitOffset>16</bitOffset>
9599 <bitWidth>1</bitWidth>
9600 </field>
9601 <field>
9602 <name>TSIE</name>
9603 <description>Time-stamp interrupt
9604 enable</description>
9605 <bitOffset>15</bitOffset>
9606 <bitWidth>1</bitWidth>
9607 </field>
9608 <field>
9609 <name>WUTIE</name>
9610 <description>Wakeup timer interrupt
9611 enable</description>
9612 <bitOffset>14</bitOffset>
9613 <bitWidth>1</bitWidth>
9614 </field>
9615 <field>
9616 <name>ALRBIE</name>
9617 <description>Alarm B interrupt enable</description>
9618 <bitOffset>13</bitOffset>
9619 <bitWidth>1</bitWidth>
9620 </field>
9621 <field>
9622 <name>ALRAIE</name>
9623 <description>Alarm A interrupt enable</description>
9624 <bitOffset>12</bitOffset>
9625 <bitWidth>1</bitWidth>
9626 </field>
9627 <field>
9628 <name>TSE</name>
9629 <description>Time stamp enable</description>
9630 <bitOffset>11</bitOffset>
9631 <bitWidth>1</bitWidth>
9632 </field>
9633 <field>
9634 <name>WUTE</name>
9635 <description>Wakeup timer enable</description>
9636 <bitOffset>10</bitOffset>
9637 <bitWidth>1</bitWidth>
9638 </field>
9639 <field>
9640 <name>ALRBE</name>
9641 <description>Alarm B enable</description>
9642 <bitOffset>9</bitOffset>
9643 <bitWidth>1</bitWidth>
9644 </field>
9645 <field>
9646 <name>ALRAE</name>
9647 <description>Alarm A enable</description>
9648 <bitOffset>8</bitOffset>
9649 <bitWidth>1</bitWidth>
9650 </field>
9651 <field>
9652 <name>DCE</name>
9653 <description>Coarse digital calibration
9654 enable</description>
9655 <bitOffset>7</bitOffset>
9656 <bitWidth>1</bitWidth>
9657 </field>
9658 <field>
9659 <name>FMT</name>
9660 <description>Hour format</description>
9661 <bitOffset>6</bitOffset>
9662 <bitWidth>1</bitWidth>
9663 </field>
9664 <field>
9665 <name>BYPSHAD</name>
9666 <description>Bypass the shadow
9667 registers</description>
9668 <bitOffset>5</bitOffset>
9669 <bitWidth>1</bitWidth>
9670 </field>
9671 <field>
9672 <name>REFCKON</name>
9673 <description>Reference clock detection enable (50 or
9674 60 Hz)</description>
9675 <bitOffset>4</bitOffset>
9676 <bitWidth>1</bitWidth>
9677 </field>
9678 <field>
9679 <name>TSEDGE</name>
9680 <description>Time-stamp event active
9681 edge</description>
9682 <bitOffset>3</bitOffset>
9683 <bitWidth>1</bitWidth>
9684 </field>
9685 <field>
9686 <name>WCKSEL</name>
9687 <description>Wakeup clock selection</description>
9688 <bitOffset>0</bitOffset>
9689 <bitWidth>3</bitWidth>
9690 </field>
9691 </fields>
9692 </register>
9693 <register>
9694 <name>ISR</name>
9695 <displayName>ISR</displayName>
9696 <description>initialization and status
9697 register</description>
9698 <addressOffset>0xC</addressOffset>
9699 <size>0x20</size>
9700 <resetValue>0x00000007</resetValue>
9701 <fields>
9702 <field>
9703 <name>ALRAWF</name>
9704 <description>Alarm A write flag</description>
9705 <bitOffset>0</bitOffset>
9706 <bitWidth>1</bitWidth>
9707 <access>read-only</access>
9708 </field>
9709 <field>
9710 <name>ALRBWF</name>
9711 <description>Alarm B write flag</description>
9712 <bitOffset>1</bitOffset>
9713 <bitWidth>1</bitWidth>
9714 <access>read-only</access>
9715 </field>
9716 <field>
9717 <name>WUTWF</name>
9718 <description>Wakeup timer write flag</description>
9719 <bitOffset>2</bitOffset>
9720 <bitWidth>1</bitWidth>
9721 <access>read-only</access>
9722 </field>
9723 <field>
9724 <name>SHPF</name>
9725 <description>Shift operation pending</description>
9726 <bitOffset>3</bitOffset>
9727 <bitWidth>1</bitWidth>
9728 <access>read-write</access>
9729 </field>
9730 <field>
9731 <name>INITS</name>
9732 <description>Initialization status flag</description>
9733 <bitOffset>4</bitOffset>
9734 <bitWidth>1</bitWidth>
9735 <access>read-only</access>
9736 </field>
9737 <field>
9738 <name>RSF</name>
9739 <description>Registers synchronization
9740 flag</description>
9741 <bitOffset>5</bitOffset>
9742 <bitWidth>1</bitWidth>
9743 <access>read-write</access>
9744 </field>
9745 <field>
9746 <name>INITF</name>
9747 <description>Initialization flag</description>
9748 <bitOffset>6</bitOffset>
9749 <bitWidth>1</bitWidth>
9750 <access>read-only</access>
9751 </field>
9752 <field>
9753 <name>INIT</name>
9754 <description>Initialization mode</description>
9755 <bitOffset>7</bitOffset>
9756 <bitWidth>1</bitWidth>
9757 <access>read-write</access>
9758 </field>
9759 <field>
9760 <name>ALRAF</name>
9761 <description>Alarm A flag</description>
9762 <bitOffset>8</bitOffset>
9763 <bitWidth>1</bitWidth>
9764 <access>read-write</access>
9765 </field>
9766 <field>
9767 <name>ALRBF</name>
9768 <description>Alarm B flag</description>
9769 <bitOffset>9</bitOffset>
9770 <bitWidth>1</bitWidth>
9771 <access>read-write</access>
9772 </field>
9773 <field>
9774 <name>WUTF</name>
9775 <description>Wakeup timer flag</description>
9776 <bitOffset>10</bitOffset>
9777 <bitWidth>1</bitWidth>
9778 <access>read-write</access>
9779 </field>
9780 <field>
9781 <name>TSF</name>
9782 <description>Time-stamp flag</description>
9783 <bitOffset>11</bitOffset>
9784 <bitWidth>1</bitWidth>
9785 <access>read-write</access>
9786 </field>
9787 <field>
9788 <name>TSOVF</name>
9789 <description>Time-stamp overflow flag</description>
9790 <bitOffset>12</bitOffset>
9791 <bitWidth>1</bitWidth>
9792 <access>read-write</access>
9793 </field>
9794 <field>
9795 <name>TAMP1F</name>
9796 <description>Tamper detection flag</description>
9797 <bitOffset>13</bitOffset>
9798 <bitWidth>1</bitWidth>
9799 <access>read-write</access>
9800 </field>
9801 <field>
9802 <name>TAMP2F</name>
9803 <description>TAMPER2 detection flag</description>
9804 <bitOffset>14</bitOffset>
9805 <bitWidth>1</bitWidth>
9806 <access>read-write</access>
9807 </field>
9808 <field>
9809 <name>RECALPF</name>
9810 <description>Recalibration pending Flag</description>
9811 <bitOffset>16</bitOffset>
9812 <bitWidth>1</bitWidth>
9813 <access>read-only</access>
9814 </field>
9815 </fields>
9816 </register>
9817 <register>
9818 <name>PRER</name>
9819 <displayName>PRER</displayName>
9820 <description>prescaler register</description>
9821 <addressOffset>0x10</addressOffset>
9822 <size>0x20</size>
9823 <access>read-write</access>
9824 <resetValue>0x007F00FF</resetValue>
9825 <fields>
9826 <field>
9827 <name>PREDIV_A</name>
9828 <description>Asynchronous prescaler
9829 factor</description>
9830 <bitOffset>16</bitOffset>
9831 <bitWidth>7</bitWidth>
9832 </field>
9833 <field>
9834 <name>PREDIV_S</name>
9835 <description>Synchronous prescaler
9836 factor</description>
9837 <bitOffset>0</bitOffset>
9838 <bitWidth>15</bitWidth>
9839 </field>
9840 </fields>
9841 </register>
9842 <register>
9843 <name>WUTR</name>
9844 <displayName>WUTR</displayName>
9845 <description>wakeup timer register</description>
9846 <addressOffset>0x14</addressOffset>
9847 <size>0x20</size>
9848 <access>read-write</access>
9849 <resetValue>0x0000FFFF</resetValue>
9850 <fields>
9851 <field>
9852 <name>WUT</name>
9853 <description>Wakeup auto-reload value
9854 bits</description>
9855 <bitOffset>0</bitOffset>
9856 <bitWidth>16</bitWidth>
9857 </field>
9858 </fields>
9859 </register>
9860 <register>
9861 <name>CALIBR</name>
9862 <displayName>CALIBR</displayName>
9863 <description>calibration register</description>
9864 <addressOffset>0x18</addressOffset>
9865 <size>0x20</size>
9866 <access>read-write</access>
9867 <resetValue>0x00000000</resetValue>
9868 <fields>
9869 <field>
9870 <name>DCS</name>
9871 <description>Digital calibration sign</description>
9872 <bitOffset>7</bitOffset>
9873 <bitWidth>1</bitWidth>
9874 </field>
9875 <field>
9876 <name>DC</name>
9877 <description>Digital calibration</description>
9878 <bitOffset>0</bitOffset>
9879 <bitWidth>5</bitWidth>
9880 </field>
9881 </fields>
9882 </register>
9883 <register>
9884 <name>ALRMAR</name>
9885 <displayName>ALRMAR</displayName>
9886 <description>alarm A register</description>
9887 <addressOffset>0x1C</addressOffset>
9888 <size>0x20</size>
9889 <access>read-write</access>
9890 <resetValue>0x00000000</resetValue>
9891 <fields>
9892 <field>
9893 <name>MSK4</name>
9894 <description>Alarm A date mask</description>
9895 <bitOffset>31</bitOffset>
9896 <bitWidth>1</bitWidth>
9897 </field>
9898 <field>
9899 <name>WDSEL</name>
9900 <description>Week day selection</description>
9901 <bitOffset>30</bitOffset>
9902 <bitWidth>1</bitWidth>
9903 </field>
9904 <field>
9905 <name>DT</name>
9906 <description>Date tens in BCD format</description>
9907 <bitOffset>28</bitOffset>
9908 <bitWidth>2</bitWidth>
9909 </field>
9910 <field>
9911 <name>DU</name>
9912 <description>Date units or day in BCD
9913 format</description>
9914 <bitOffset>24</bitOffset>
9915 <bitWidth>4</bitWidth>
9916 </field>
9917 <field>
9918 <name>MSK3</name>
9919 <description>Alarm A hours mask</description>
9920 <bitOffset>23</bitOffset>
9921 <bitWidth>1</bitWidth>
9922 </field>
9923 <field>
9924 <name>PM</name>
9925 <description>AM/PM notation</description>
9926 <bitOffset>22</bitOffset>
9927 <bitWidth>1</bitWidth>
9928 </field>
9929 <field>
9930 <name>HT</name>
9931 <description>Hour tens in BCD format</description>
9932 <bitOffset>20</bitOffset>
9933 <bitWidth>2</bitWidth>
9934 </field>
9935 <field>
9936 <name>HU</name>
9937 <description>Hour units in BCD format</description>
9938 <bitOffset>16</bitOffset>
9939 <bitWidth>4</bitWidth>
9940 </field>
9941 <field>
9942 <name>MSK2</name>
9943 <description>Alarm A minutes mask</description>
9944 <bitOffset>15</bitOffset>
9945 <bitWidth>1</bitWidth>
9946 </field>
9947 <field>
9948 <name>MNT</name>
9949 <description>Minute tens in BCD format</description>
9950 <bitOffset>12</bitOffset>
9951 <bitWidth>3</bitWidth>
9952 </field>
9953 <field>
9954 <name>MNU</name>
9955 <description>Minute units in BCD format</description>
9956 <bitOffset>8</bitOffset>
9957 <bitWidth>4</bitWidth>
9958 </field>
9959 <field>
9960 <name>MSK1</name>
9961 <description>Alarm A seconds mask</description>
9962 <bitOffset>7</bitOffset>
9963 <bitWidth>1</bitWidth>
9964 </field>
9965 <field>
9966 <name>ST</name>
9967 <description>Second tens in BCD format</description>
9968 <bitOffset>4</bitOffset>
9969 <bitWidth>3</bitWidth>
9970 </field>
9971 <field>
9972 <name>SU</name>
9973 <description>Second units in BCD format</description>
9974 <bitOffset>0</bitOffset>
9975 <bitWidth>4</bitWidth>
9976 </field>
9977 </fields>
9978 </register>
9979 <register>
9980 <name>ALRMBR</name>
9981 <displayName>ALRMBR</displayName>
9982 <description>alarm B register</description>
9983 <addressOffset>0x20</addressOffset>
9984 <size>0x20</size>
9985 <access>read-write</access>
9986 <resetValue>0x00000000</resetValue>
9987 <fields>
9988 <field>
9989 <name>MSK4</name>
9990 <description>Alarm B date mask</description>
9991 <bitOffset>31</bitOffset>
9992 <bitWidth>1</bitWidth>
9993 </field>
9994 <field>
9995 <name>WDSEL</name>
9996 <description>Week day selection</description>
9997 <bitOffset>30</bitOffset>
9998 <bitWidth>1</bitWidth>
9999 </field>
10000 <field>
10001 <name>DT</name>
10002 <description>Date tens in BCD format</description>
10003 <bitOffset>28</bitOffset>
10004 <bitWidth>2</bitWidth>
10005 </field>
10006 <field>
10007 <name>DU</name>
10008 <description>Date units or day in BCD
10009 format</description>
10010 <bitOffset>24</bitOffset>
10011 <bitWidth>4</bitWidth>
10012 </field>
10013 <field>
10014 <name>MSK3</name>
10015 <description>Alarm B hours mask</description>
10016 <bitOffset>23</bitOffset>
10017 <bitWidth>1</bitWidth>
10018 </field>
10019 <field>
10020 <name>PM</name>
10021 <description>AM/PM notation</description>
10022 <bitOffset>22</bitOffset>
10023 <bitWidth>1</bitWidth>
10024 </field>
10025 <field>
10026 <name>HT</name>
10027 <description>Hour tens in BCD format</description>
10028 <bitOffset>20</bitOffset>
10029 <bitWidth>2</bitWidth>
10030 </field>
10031 <field>
10032 <name>HU</name>
10033 <description>Hour units in BCD format</description>
10034 <bitOffset>16</bitOffset>
10035 <bitWidth>4</bitWidth>
10036 </field>
10037 <field>
10038 <name>MSK2</name>
10039 <description>Alarm B minutes mask</description>
10040 <bitOffset>15</bitOffset>
10041 <bitWidth>1</bitWidth>
10042 </field>
10043 <field>
10044 <name>MNT</name>
10045 <description>Minute tens in BCD format</description>
10046 <bitOffset>12</bitOffset>
10047 <bitWidth>3</bitWidth>
10048 </field>
10049 <field>
10050 <name>MNU</name>
10051 <description>Minute units in BCD format</description>
10052 <bitOffset>8</bitOffset>
10053 <bitWidth>4</bitWidth>
10054 </field>
10055 <field>
10056 <name>MSK1</name>
10057 <description>Alarm B seconds mask</description>
10058 <bitOffset>7</bitOffset>
10059 <bitWidth>1</bitWidth>
10060 </field>
10061 <field>
10062 <name>ST</name>
10063 <description>Second tens in BCD format</description>
10064 <bitOffset>4</bitOffset>
10065 <bitWidth>3</bitWidth>
10066 </field>
10067 <field>
10068 <name>SU</name>
10069 <description>Second units in BCD format</description>
10070 <bitOffset>0</bitOffset>
10071 <bitWidth>4</bitWidth>
10072 </field>
10073 </fields>
10074 </register>
10075 <register>
10076 <name>WPR</name>
10077 <displayName>WPR</displayName>
10078 <description>write protection register</description>
10079 <addressOffset>0x24</addressOffset>
10080 <size>0x20</size>
10081 <access>write-only</access>
10082 <resetValue>0x00000000</resetValue>
10083 <fields>
10084 <field>
10085 <name>KEY</name>
10086 <description>Write protection key</description>
10087 <bitOffset>0</bitOffset>
10088 <bitWidth>8</bitWidth>
10089 </field>
10090 </fields>
10091 </register>
10092 <register>
10093 <name>SSR</name>
10094 <displayName>SSR</displayName>
10095 <description>sub second register</description>
10096 <addressOffset>0x28</addressOffset>
10097 <size>0x20</size>
10098 <access>read-only</access>
10099 <resetValue>0x00000000</resetValue>
10100 <fields>
10101 <field>
10102 <name>SS</name>
10103 <description>Sub second value</description>
10104 <bitOffset>0</bitOffset>
10105 <bitWidth>16</bitWidth>
10106 </field>
10107 </fields>
10108 </register>
10109 <register>
10110 <name>SHIFTR</name>
10111 <displayName>SHIFTR</displayName>
10112 <description>shift control register</description>
10113 <addressOffset>0x2C</addressOffset>
10114 <size>0x20</size>
10115 <access>write-only</access>
10116 <resetValue>0x00000000</resetValue>
10117 <fields>
10118 <field>
10119 <name>ADD1S</name>
10120 <description>Add one second</description>
10121 <bitOffset>31</bitOffset>
10122 <bitWidth>1</bitWidth>
10123 </field>
10124 <field>
10125 <name>SUBFS</name>
10126 <description>Subtract a fraction of a
10127 second</description>
10128 <bitOffset>0</bitOffset>
10129 <bitWidth>15</bitWidth>
10130 </field>
10131 </fields>
10132 </register>
10133 <register>
10134 <name>TSTR</name>
10135 <displayName>TSTR</displayName>
10136 <description>time stamp time register</description>
10137 <addressOffset>0x30</addressOffset>
10138 <size>0x20</size>
10139 <access>read-only</access>
10140 <resetValue>0x00000000</resetValue>
10141 <fields>
10142 <field>
10143 <name>PM</name>
10144 <description>AM/PM notation</description>
10145 <bitOffset>22</bitOffset>
10146 <bitWidth>1</bitWidth>
10147 </field>
10148 <field>
10149 <name>HT</name>
10150 <description>Hour tens in BCD format</description>
10151 <bitOffset>20</bitOffset>
10152 <bitWidth>2</bitWidth>
10153 </field>
10154 <field>
10155 <name>HU</name>
10156 <description>Hour units in BCD format</description>
10157 <bitOffset>16</bitOffset>
10158 <bitWidth>4</bitWidth>
10159 </field>
10160 <field>
10161 <name>MNT</name>
10162 <description>Minute tens in BCD format</description>
10163 <bitOffset>12</bitOffset>
10164 <bitWidth>3</bitWidth>
10165 </field>
10166 <field>
10167 <name>MNU</name>
10168 <description>Minute units in BCD format</description>
10169 <bitOffset>8</bitOffset>
10170 <bitWidth>4</bitWidth>
10171 </field>
10172 <field>
10173 <name>ST</name>
10174 <description>Second tens in BCD format</description>
10175 <bitOffset>4</bitOffset>
10176 <bitWidth>3</bitWidth>
10177 </field>
10178 <field>
10179 <name>SU</name>
10180 <description>Second units in BCD format</description>
10181 <bitOffset>0</bitOffset>
10182 <bitWidth>4</bitWidth>
10183 </field>
10184 </fields>
10185 </register>
10186 <register>
10187 <name>TSDR</name>
10188 <displayName>TSDR</displayName>
10189 <description>time stamp date register</description>
10190 <addressOffset>0x34</addressOffset>
10191 <size>0x20</size>
10192 <access>read-only</access>
10193 <resetValue>0x00000000</resetValue>
10194 <fields>
10195 <field>
10196 <name>WDU</name>
10197 <description>Week day units</description>
10198 <bitOffset>13</bitOffset>
10199 <bitWidth>3</bitWidth>
10200 </field>
10201 <field>
10202 <name>MT</name>
10203 <description>Month tens in BCD format</description>
10204 <bitOffset>12</bitOffset>
10205 <bitWidth>1</bitWidth>
10206 </field>
10207 <field>
10208 <name>MU</name>
10209 <description>Month units in BCD format</description>
10210 <bitOffset>8</bitOffset>
10211 <bitWidth>4</bitWidth>
10212 </field>
10213 <field>
10214 <name>DT</name>
10215 <description>Date tens in BCD format</description>
10216 <bitOffset>4</bitOffset>
10217 <bitWidth>2</bitWidth>
10218 </field>
10219 <field>
10220 <name>DU</name>
10221 <description>Date units in BCD format</description>
10222 <bitOffset>0</bitOffset>
10223 <bitWidth>4</bitWidth>
10224 </field>
10225 </fields>
10226 </register>
10227 <register>
10228 <name>TSSSR</name>
10229 <displayName>TSSSR</displayName>
10230 <description>timestamp sub second register</description>
10231 <addressOffset>0x38</addressOffset>
10232 <size>0x20</size>
10233 <access>read-only</access>
10234 <resetValue>0x00000000</resetValue>
10235 <fields>
10236 <field>
10237 <name>SS</name>
10238 <description>Sub second value</description>
10239 <bitOffset>0</bitOffset>
10240 <bitWidth>16</bitWidth>
10241 </field>
10242 </fields>
10243 </register>
10244 <register>
10245 <name>CALR</name>
10246 <displayName>CALR</displayName>
10247 <description>calibration register</description>
10248 <addressOffset>0x3C</addressOffset>
10249 <size>0x20</size>
10250 <access>read-write</access>
10251 <resetValue>0x00000000</resetValue>
10252 <fields>
10253 <field>
10254 <name>CALP</name>
10255 <description>Increase frequency of RTC by 488.5
10256 ppm</description>
10257 <bitOffset>15</bitOffset>
10258 <bitWidth>1</bitWidth>
10259 </field>
10260 <field>
10261 <name>CALW8</name>
10262 <description>Use an 8-second calibration cycle
10263 period</description>
10264 <bitOffset>14</bitOffset>
10265 <bitWidth>1</bitWidth>
10266 </field>
10267 <field>
10268 <name>CALW16</name>
10269 <description>Use a 16-second calibration cycle
10270 period</description>
10271 <bitOffset>13</bitOffset>
10272 <bitWidth>1</bitWidth>
10273 </field>
10274 <field>
10275 <name>CALM</name>
10276 <description>Calibration minus</description>
10277 <bitOffset>0</bitOffset>
10278 <bitWidth>9</bitWidth>
10279 </field>
10280 </fields>
10281 </register>
10282 <register>
10283 <name>TAFCR</name>
10284 <displayName>TAFCR</displayName>
10285 <description>tamper and alternate function configuration
10286 register</description>
10287 <addressOffset>0x40</addressOffset>
10288 <size>0x20</size>
10289 <access>read-write</access>
10290 <resetValue>0x00000000</resetValue>
10291 <fields>
10292 <field>
10293 <name>ALARMOUTTYPE</name>
10294 <description>AFO_ALARM output type</description>
10295 <bitOffset>18</bitOffset>
10296 <bitWidth>1</bitWidth>
10297 </field>
10298 <field>
10299 <name>TSINSEL</name>
10300 <description>TIMESTAMP mapping</description>
10301 <bitOffset>17</bitOffset>
10302 <bitWidth>1</bitWidth>
10303 </field>
10304 <field>
10305 <name>TAMP1INSEL</name>
10306 <description>TAMPER1 mapping</description>
10307 <bitOffset>16</bitOffset>
10308 <bitWidth>1</bitWidth>
10309 </field>
10310 <field>
10311 <name>TAMPPUDIS</name>
10312 <description>TAMPER pull-up disable</description>
10313 <bitOffset>15</bitOffset>
10314 <bitWidth>1</bitWidth>
10315 </field>
10316 <field>
10317 <name>TAMPPRCH</name>
10318 <description>Tamper precharge duration</description>
10319 <bitOffset>13</bitOffset>
10320 <bitWidth>2</bitWidth>
10321 </field>
10322 <field>
10323 <name>TAMPFLT</name>
10324 <description>Tamper filter count</description>
10325 <bitOffset>11</bitOffset>
10326 <bitWidth>2</bitWidth>
10327 </field>
10328 <field>
10329 <name>TAMPFREQ</name>
10330 <description>Tamper sampling frequency</description>
10331 <bitOffset>8</bitOffset>
10332 <bitWidth>3</bitWidth>
10333 </field>
10334 <field>
10335 <name>TAMPTS</name>
10336 <description>Activate timestamp on tamper detection
10337 event</description>
10338 <bitOffset>7</bitOffset>
10339 <bitWidth>1</bitWidth>
10340 </field>
10341 <field>
10342 <name>TAMP2TRG</name>
10343 <description>Active level for tamper 2</description>
10344 <bitOffset>4</bitOffset>
10345 <bitWidth>1</bitWidth>
10346 </field>
10347 <field>
10348 <name>TAMP2E</name>
10349 <description>Tamper 2 detection enable</description>
10350 <bitOffset>3</bitOffset>
10351 <bitWidth>1</bitWidth>
10352 </field>
10353 <field>
10354 <name>TAMPIE</name>
10355 <description>Tamper interrupt enable</description>
10356 <bitOffset>2</bitOffset>
10357 <bitWidth>1</bitWidth>
10358 </field>
10359 <field>
10360 <name>TAMP1TRG</name>
10361 <description>Active level for tamper 1</description>
10362 <bitOffset>1</bitOffset>
10363 <bitWidth>1</bitWidth>
10364 </field>
10365 <field>
10366 <name>TAMP1E</name>
10367 <description>Tamper 1 detection enable</description>
10368 <bitOffset>0</bitOffset>
10369 <bitWidth>1</bitWidth>
10370 </field>
10371 </fields>
10372 </register>
10373 <register>
10374 <name>ALRMASSR</name>
10375 <displayName>ALRMASSR</displayName>
10376 <description>alarm A sub second register</description>
10377 <addressOffset>0x44</addressOffset>
10378 <size>0x20</size>
10379 <access>read-write</access>
10380 <resetValue>0x00000000</resetValue>
10381 <fields>
10382 <field>
10383 <name>MASKSS</name>
10384 <description>Mask the most-significant bits starting
10385 at this bit</description>
10386 <bitOffset>24</bitOffset>
10387 <bitWidth>4</bitWidth>
10388 </field>
10389 <field>
10390 <name>SS</name>
10391 <description>Sub seconds value</description>
10392 <bitOffset>0</bitOffset>
10393 <bitWidth>15</bitWidth>
10394 </field>
10395 </fields>
10396 </register>
10397 <register>
10398 <name>ALRMBSSR</name>
10399 <displayName>ALRMBSSR</displayName>
10400 <description>alarm B sub second register</description>
10401 <addressOffset>0x48</addressOffset>
10402 <size>0x20</size>
10403 <access>read-write</access>
10404 <resetValue>0x00000000</resetValue>
10405 <fields>
10406 <field>
10407 <name>MASKSS</name>
10408 <description>Mask the most-significant bits starting
10409 at this bit</description>
10410 <bitOffset>24</bitOffset>
10411 <bitWidth>4</bitWidth>
10412 </field>
10413 <field>
10414 <name>SS</name>
10415 <description>Sub seconds value</description>
10416 <bitOffset>0</bitOffset>
10417 <bitWidth>15</bitWidth>
10418 </field>
10419 </fields>
10420 </register>
10421 <register>
10422 <name>BKP0R</name>
10423 <displayName>BKP0R</displayName>
10424 <description>backup register</description>
10425 <addressOffset>0x50</addressOffset>
10426 <size>0x20</size>
10427 <access>read-write</access>
10428 <resetValue>0x00000000</resetValue>
10429 <fields>
10430 <field>
10431 <name>BKP</name>
10432 <description>BKP</description>
10433 <bitOffset>0</bitOffset>
10434 <bitWidth>32</bitWidth>
10435 </field>
10436 </fields>
10437 </register>
10438 <register>
10439 <name>BKP1R</name>
10440 <displayName>BKP1R</displayName>
10441 <description>backup register</description>
10442 <addressOffset>0x54</addressOffset>
10443 <size>0x20</size>
10444 <access>read-write</access>
10445 <resetValue>0x00000000</resetValue>
10446 <fields>
10447 <field>
10448 <name>BKP</name>
10449 <description>BKP</description>
10450 <bitOffset>0</bitOffset>
10451 <bitWidth>32</bitWidth>
10452 </field>
10453 </fields>
10454 </register>
10455 <register>
10456 <name>BKP2R</name>
10457 <displayName>BKP2R</displayName>
10458 <description>backup register</description>
10459 <addressOffset>0x58</addressOffset>
10460 <size>0x20</size>
10461 <access>read-write</access>
10462 <resetValue>0x00000000</resetValue>
10463 <fields>
10464 <field>
10465 <name>BKP</name>
10466 <description>BKP</description>
10467 <bitOffset>0</bitOffset>
10468 <bitWidth>32</bitWidth>
10469 </field>
10470 </fields>
10471 </register>
10472 <register>
10473 <name>BKP3R</name>
10474 <displayName>BKP3R</displayName>
10475 <description>backup register</description>
10476 <addressOffset>0x5C</addressOffset>
10477 <size>0x20</size>
10478 <access>read-write</access>
10479 <resetValue>0x00000000</resetValue>
10480 <fields>
10481 <field>
10482 <name>BKP</name>
10483 <description>BKP</description>
10484 <bitOffset>0</bitOffset>
10485 <bitWidth>32</bitWidth>
10486 </field>
10487 </fields>
10488 </register>
10489 <register>
10490 <name>BKP4R</name>
10491 <displayName>BKP4R</displayName>
10492 <description>backup register</description>
10493 <addressOffset>0x60</addressOffset>
10494 <size>0x20</size>
10495 <access>read-write</access>
10496 <resetValue>0x00000000</resetValue>
10497 <fields>
10498 <field>
10499 <name>BKP</name>
10500 <description>BKP</description>
10501 <bitOffset>0</bitOffset>
10502 <bitWidth>32</bitWidth>
10503 </field>
10504 </fields>
10505 </register>
10506 <register>
10507 <name>BKP5R</name>
10508 <displayName>BKP5R</displayName>
10509 <description>backup register</description>
10510 <addressOffset>0x64</addressOffset>
10511 <size>0x20</size>
10512 <access>read-write</access>
10513 <resetValue>0x00000000</resetValue>
10514 <fields>
10515 <field>
10516 <name>BKP</name>
10517 <description>BKP</description>
10518 <bitOffset>0</bitOffset>
10519 <bitWidth>32</bitWidth>
10520 </field>
10521 </fields>
10522 </register>
10523 <register>
10524 <name>BKP6R</name>
10525 <displayName>BKP6R</displayName>
10526 <description>backup register</description>
10527 <addressOffset>0x68</addressOffset>
10528 <size>0x20</size>
10529 <access>read-write</access>
10530 <resetValue>0x00000000</resetValue>
10531 <fields>
10532 <field>
10533 <name>BKP</name>
10534 <description>BKP</description>
10535 <bitOffset>0</bitOffset>
10536 <bitWidth>32</bitWidth>
10537 </field>
10538 </fields>
10539 </register>
10540 <register>
10541 <name>BKP7R</name>
10542 <displayName>BKP7R</displayName>
10543 <description>backup register</description>
10544 <addressOffset>0x6C</addressOffset>
10545 <size>0x20</size>
10546 <access>read-write</access>
10547 <resetValue>0x00000000</resetValue>
10548 <fields>
10549 <field>
10550 <name>BKP</name>
10551 <description>BKP</description>
10552 <bitOffset>0</bitOffset>
10553 <bitWidth>32</bitWidth>
10554 </field>
10555 </fields>
10556 </register>
10557 <register>
10558 <name>BKP8R</name>
10559 <displayName>BKP8R</displayName>
10560 <description>backup register</description>
10561 <addressOffset>0x70</addressOffset>
10562 <size>0x20</size>
10563 <access>read-write</access>
10564 <resetValue>0x00000000</resetValue>
10565 <fields>
10566 <field>
10567 <name>BKP</name>
10568 <description>BKP</description>
10569 <bitOffset>0</bitOffset>
10570 <bitWidth>32</bitWidth>
10571 </field>
10572 </fields>
10573 </register>
10574 <register>
10575 <name>BKP9R</name>
10576 <displayName>BKP9R</displayName>
10577 <description>backup register</description>
10578 <addressOffset>0x74</addressOffset>
10579 <size>0x20</size>
10580 <access>read-write</access>
10581 <resetValue>0x00000000</resetValue>
10582 <fields>
10583 <field>
10584 <name>BKP</name>
10585 <description>BKP</description>
10586 <bitOffset>0</bitOffset>
10587 <bitWidth>32</bitWidth>
10588 </field>
10589 </fields>
10590 </register>
10591 <register>
10592 <name>BKP10R</name>
10593 <displayName>BKP10R</displayName>
10594 <description>backup register</description>
10595 <addressOffset>0x78</addressOffset>
10596 <size>0x20</size>
10597 <access>read-write</access>
10598 <resetValue>0x00000000</resetValue>
10599 <fields>
10600 <field>
10601 <name>BKP</name>
10602 <description>BKP</description>
10603 <bitOffset>0</bitOffset>
10604 <bitWidth>32</bitWidth>
10605 </field>
10606 </fields>
10607 </register>
10608 <register>
10609 <name>BKP11R</name>
10610 <displayName>BKP11R</displayName>
10611 <description>backup register</description>
10612 <addressOffset>0x7C</addressOffset>
10613 <size>0x20</size>
10614 <access>read-write</access>
10615 <resetValue>0x00000000</resetValue>
10616 <fields>
10617 <field>
10618 <name>BKP</name>
10619 <description>BKP</description>
10620 <bitOffset>0</bitOffset>
10621 <bitWidth>32</bitWidth>
10622 </field>
10623 </fields>
10624 </register>
10625 <register>
10626 <name>BKP12R</name>
10627 <displayName>BKP12R</displayName>
10628 <description>backup register</description>
10629 <addressOffset>0x80</addressOffset>
10630 <size>0x20</size>
10631 <access>read-write</access>
10632 <resetValue>0x00000000</resetValue>
10633 <fields>
10634 <field>
10635 <name>BKP</name>
10636 <description>BKP</description>
10637 <bitOffset>0</bitOffset>
10638 <bitWidth>32</bitWidth>
10639 </field>
10640 </fields>
10641 </register>
10642 <register>
10643 <name>BKP13R</name>
10644 <displayName>BKP13R</displayName>
10645 <description>backup register</description>
10646 <addressOffset>0x84</addressOffset>
10647 <size>0x20</size>
10648 <access>read-write</access>
10649 <resetValue>0x00000000</resetValue>
10650 <fields>
10651 <field>
10652 <name>BKP</name>
10653 <description>BKP</description>
10654 <bitOffset>0</bitOffset>
10655 <bitWidth>32</bitWidth>
10656 </field>
10657 </fields>
10658 </register>
10659 <register>
10660 <name>BKP14R</name>
10661 <displayName>BKP14R</displayName>
10662 <description>backup register</description>
10663 <addressOffset>0x88</addressOffset>
10664 <size>0x20</size>
10665 <access>read-write</access>
10666 <resetValue>0x00000000</resetValue>
10667 <fields>
10668 <field>
10669 <name>BKP</name>
10670 <description>BKP</description>
10671 <bitOffset>0</bitOffset>
10672 <bitWidth>32</bitWidth>
10673 </field>
10674 </fields>
10675 </register>
10676 <register>
10677 <name>BKP15R</name>
10678 <displayName>BKP15R</displayName>
10679 <description>backup register</description>
10680 <addressOffset>0x8C</addressOffset>
10681 <size>0x20</size>
10682 <access>read-write</access>
10683 <resetValue>0x00000000</resetValue>
10684 <fields>
10685 <field>
10686 <name>BKP</name>
10687 <description>BKP</description>
10688 <bitOffset>0</bitOffset>
10689 <bitWidth>32</bitWidth>
10690 </field>
10691 </fields>
10692 </register>
10693 <register>
10694 <name>BKP16R</name>
10695 <displayName>BKP16R</displayName>
10696 <description>backup register</description>
10697 <addressOffset>0x90</addressOffset>
10698 <size>0x20</size>
10699 <access>read-write</access>
10700 <resetValue>0x00000000</resetValue>
10701 <fields>
10702 <field>
10703 <name>BKP</name>
10704 <description>BKP</description>
10705 <bitOffset>0</bitOffset>
10706 <bitWidth>32</bitWidth>
10707 </field>
10708 </fields>
10709 </register>
10710 <register>
10711 <name>BKP17R</name>
10712 <displayName>BKP17R</displayName>
10713 <description>backup register</description>
10714 <addressOffset>0x94</addressOffset>
10715 <size>0x20</size>
10716 <access>read-write</access>
10717 <resetValue>0x00000000</resetValue>
10718 <fields>
10719 <field>
10720 <name>BKP</name>
10721 <description>BKP</description>
10722 <bitOffset>0</bitOffset>
10723 <bitWidth>32</bitWidth>
10724 </field>
10725 </fields>
10726 </register>
10727 <register>
10728 <name>BKP18R</name>
10729 <displayName>BKP18R</displayName>
10730 <description>backup register</description>
10731 <addressOffset>0x98</addressOffset>
10732 <size>0x20</size>
10733 <access>read-write</access>
10734 <resetValue>0x00000000</resetValue>
10735 <fields>
10736 <field>
10737 <name>BKP</name>
10738 <description>BKP</description>
10739 <bitOffset>0</bitOffset>
10740 <bitWidth>32</bitWidth>
10741 </field>
10742 </fields>
10743 </register>
10744 <register>
10745 <name>BKP19R</name>
10746 <displayName>BKP19R</displayName>
10747 <description>backup register</description>
10748 <addressOffset>0x9C</addressOffset>
10749 <size>0x20</size>
10750 <access>read-write</access>
10751 <resetValue>0x00000000</resetValue>
10752 <fields>
10753 <field>
10754 <name>BKP</name>
10755 <description>BKP</description>
10756 <bitOffset>0</bitOffset>
10757 <bitWidth>32</bitWidth>
10758 </field>
10759 </fields>
10760 </register>
10761 </registers>
10762 </peripheral>
10763 <peripheral>
10764 <name>SDIO</name>
10765 <description>Secure digital input/output
10766 interface</description>
10767 <groupName>SDIO</groupName>
10768 <baseAddress>0x40012C00</baseAddress>
10769 <addressBlock>
10770 <offset>0x0</offset>
10771 <size>0x400</size>
10772 <usage>registers</usage>
10773 </addressBlock>
10774 <interrupt>
10775 <name>I2C3_EV</name>
10776 <description>I2C3 event interrupt</description>
10777 <value>72</value>
10778 </interrupt>
10779 <interrupt>
10780 <name>I2C3_ER</name>
10781 <description>I2C3 error interrupt</description>
10782 <value>73</value>
10783 </interrupt>
10784 <registers>
10785 <register>
10786 <name>POWER</name>
10787 <displayName>POWER</displayName>
10788 <description>power control register</description>
10789 <addressOffset>0x0</addressOffset>
10790 <size>0x20</size>
10791 <access>read-write</access>
10792 <resetValue>0x00000000</resetValue>
10793 <fields>
10794 <field>
10795 <name>PWRCTRL</name>
10796 <description>PWRCTRL</description>
10797 <bitOffset>0</bitOffset>
10798 <bitWidth>2</bitWidth>
10799 </field>
10800 </fields>
10801 </register>
10802 <register>
10803 <name>CLKCR</name>
10804 <displayName>CLKCR</displayName>
10805 <description>SDI clock control register</description>
10806 <addressOffset>0x4</addressOffset>
10807 <size>0x20</size>
10808 <access>read-write</access>
10809 <resetValue>0x00000000</resetValue>
10810 <fields>
10811 <field>
10812 <name>HWFC_EN</name>
10813 <description>HW Flow Control enable</description>
10814 <bitOffset>14</bitOffset>
10815 <bitWidth>1</bitWidth>
10816 </field>
10817 <field>
10818 <name>NEGEDGE</name>
10819 <description>SDIO_CK dephasing selection
10820 bit</description>
10821 <bitOffset>13</bitOffset>
10822 <bitWidth>1</bitWidth>
10823 </field>
10824 <field>
10825 <name>WIDBUS</name>
10826 <description>Wide bus mode enable bit</description>
10827 <bitOffset>11</bitOffset>
10828 <bitWidth>2</bitWidth>
10829 </field>
10830 <field>
10831 <name>BYPASS</name>
10832 <description>Clock divider bypass enable
10833 bit</description>
10834 <bitOffset>10</bitOffset>
10835 <bitWidth>1</bitWidth>
10836 </field>
10837 <field>
10838 <name>PWRSAV</name>
10839 <description>Power saving configuration
10840 bit</description>
10841 <bitOffset>9</bitOffset>
10842 <bitWidth>1</bitWidth>
10843 </field>
10844 <field>
10845 <name>CLKEN</name>
10846 <description>Clock enable bit</description>
10847 <bitOffset>8</bitOffset>
10848 <bitWidth>1</bitWidth>
10849 </field>
10850 <field>
10851 <name>CLKDIV</name>
10852 <description>Clock divide factor</description>
10853 <bitOffset>0</bitOffset>
10854 <bitWidth>8</bitWidth>
10855 </field>
10856 </fields>
10857 </register>
10858 <register>
10859 <name>ARG</name>
10860 <displayName>ARG</displayName>
10861 <description>argument register</description>
10862 <addressOffset>0x8</addressOffset>
10863 <size>0x20</size>
10864 <access>read-write</access>
10865 <resetValue>0x00000000</resetValue>
10866 <fields>
10867 <field>
10868 <name>CMDARG</name>
10869 <description>Command argument</description>
10870 <bitOffset>0</bitOffset>
10871 <bitWidth>32</bitWidth>
10872 </field>
10873 </fields>
10874 </register>
10875 <register>
10876 <name>CMD</name>
10877 <displayName>CMD</displayName>
10878 <description>command register</description>
10879 <addressOffset>0xC</addressOffset>
10880 <size>0x20</size>
10881 <access>read-write</access>
10882 <resetValue>0x00000000</resetValue>
10883 <fields>
10884 <field>
10885 <name>CE_ATACMD</name>
10886 <description>CE-ATA command</description>
10887 <bitOffset>14</bitOffset>
10888 <bitWidth>1</bitWidth>
10889 </field>
10890 <field>
10891 <name>nIEN</name>
10892 <description>not Interrupt Enable</description>
10893 <bitOffset>13</bitOffset>
10894 <bitWidth>1</bitWidth>
10895 </field>
10896 <field>
10897 <name>ENCMDcompl</name>
10898 <description>Enable CMD completion</description>
10899 <bitOffset>12</bitOffset>
10900 <bitWidth>1</bitWidth>
10901 </field>
10902 <field>
10903 <name>SDIOSuspend</name>
10904 <description>SD I/O suspend command</description>
10905 <bitOffset>11</bitOffset>
10906 <bitWidth>1</bitWidth>
10907 </field>
10908 <field>
10909 <name>CPSMEN</name>
10910 <description>Command path state machine (CPSM) Enable
10911 bit</description>
10912 <bitOffset>10</bitOffset>
10913 <bitWidth>1</bitWidth>
10914 </field>
10915 <field>
10916 <name>WAITPEND</name>
10917 <description>CPSM Waits for ends of data transfer
10918 (CmdPend internal signal).</description>
10919 <bitOffset>9</bitOffset>
10920 <bitWidth>1</bitWidth>
10921 </field>
10922 <field>
10923 <name>WAITINT</name>
10924 <description>CPSM waits for interrupt
10925 request</description>
10926 <bitOffset>8</bitOffset>
10927 <bitWidth>1</bitWidth>
10928 </field>
10929 <field>
10930 <name>WAITRESP</name>
10931 <description>Wait for response bits</description>
10932 <bitOffset>6</bitOffset>
10933 <bitWidth>2</bitWidth>
10934 </field>
10935 <field>
10936 <name>CMDINDEX</name>
10937 <description>Command index</description>
10938 <bitOffset>0</bitOffset>
10939 <bitWidth>6</bitWidth>
10940 </field>
10941 </fields>
10942 </register>
10943 <register>
10944 <name>RESPCMD</name>
10945 <displayName>RESPCMD</displayName>
10946 <description>command response register</description>
10947 <addressOffset>0x10</addressOffset>
10948 <size>0x20</size>
10949 <access>read-only</access>
10950 <resetValue>0x00000000</resetValue>
10951 <fields>
10952 <field>
10953 <name>RESPCMD</name>
10954 <description>Response command index</description>
10955 <bitOffset>0</bitOffset>
10956 <bitWidth>6</bitWidth>
10957 </field>
10958 </fields>
10959 </register>
10960 <register>
10961 <name>RESP1</name>
10962 <displayName>RESP1</displayName>
10963 <description>response 1..4 register</description>
10964 <addressOffset>0x14</addressOffset>
10965 <size>0x20</size>
10966 <access>read-only</access>
10967 <resetValue>0x00000000</resetValue>
10968 <fields>
10969 <field>
10970 <name>CARDSTATUS1</name>
10971 <description>Card Status</description>
10972 <bitOffset>0</bitOffset>
10973 <bitWidth>32</bitWidth>
10974 </field>
10975 </fields>
10976 </register>
10977 <register>
10978 <name>RESP2</name>
10979 <displayName>RESP2</displayName>
10980 <description>response 1..4 register</description>
10981 <addressOffset>0x18</addressOffset>
10982 <size>0x20</size>
10983 <access>read-only</access>
10984 <resetValue>0x00000000</resetValue>
10985 <fields>
10986 <field>
10987 <name>CARDSTATUS2</name>
10988 <description>Card Status</description>
10989 <bitOffset>0</bitOffset>
10990 <bitWidth>32</bitWidth>
10991 </field>
10992 </fields>
10993 </register>
10994 <register>
10995 <name>RESP3</name>
10996 <displayName>RESP3</displayName>
10997 <description>response 1..4 register</description>
10998 <addressOffset>0x1C</addressOffset>
10999 <size>0x20</size>
11000 <access>read-only</access>
11001 <resetValue>0x00000000</resetValue>
11002 <fields>
11003 <field>
11004 <name>CARDSTATUS3</name>
11005 <description>Card Status</description>
11006 <bitOffset>0</bitOffset>
11007 <bitWidth>32</bitWidth>
11008 </field>
11009 </fields>
11010 </register>
11011 <register>
11012 <name>RESP4</name>
11013 <displayName>RESP4</displayName>
11014 <description>response 1..4 register</description>
11015 <addressOffset>0x20</addressOffset>
11016 <size>0x20</size>
11017 <access>read-only</access>
11018 <resetValue>0x00000000</resetValue>
11019 <fields>
11020 <field>
11021 <name>CARDSTATUS4</name>
11022 <description>Card Status</description>
11023 <bitOffset>0</bitOffset>
11024 <bitWidth>32</bitWidth>
11025 </field>
11026 </fields>
11027 </register>
11028 <register>
11029 <name>DTIMER</name>
11030 <displayName>DTIMER</displayName>
11031 <description>data timer register</description>
11032 <addressOffset>0x24</addressOffset>
11033 <size>0x20</size>
11034 <access>read-write</access>
11035 <resetValue>0x00000000</resetValue>
11036 <fields>
11037 <field>
11038 <name>DATATIME</name>
11039 <description>Data timeout period</description>
11040 <bitOffset>0</bitOffset>
11041 <bitWidth>32</bitWidth>
11042 </field>
11043 </fields>
11044 </register>
11045 <register>
11046 <name>DLEN</name>
11047 <displayName>DLEN</displayName>
11048 <description>data length register</description>
11049 <addressOffset>0x28</addressOffset>
11050 <size>0x20</size>
11051 <access>read-write</access>
11052 <resetValue>0x00000000</resetValue>
11053 <fields>
11054 <field>
11055 <name>DATALENGTH</name>
11056 <description>Data length value</description>
11057 <bitOffset>0</bitOffset>
11058 <bitWidth>25</bitWidth>
11059 </field>
11060 </fields>
11061 </register>
11062 <register>
11063 <name>DCTRL</name>
11064 <displayName>DCTRL</displayName>
11065 <description>data control register</description>
11066 <addressOffset>0x2C</addressOffset>
11067 <size>0x20</size>
11068 <access>read-write</access>
11069 <resetValue>0x00000000</resetValue>
11070 <fields>
11071 <field>
11072 <name>SDIOEN</name>
11073 <description>SD I/O enable functions</description>
11074 <bitOffset>11</bitOffset>
11075 <bitWidth>1</bitWidth>
11076 </field>
11077 <field>
11078 <name>RWMOD</name>
11079 <description>Read wait mode</description>
11080 <bitOffset>10</bitOffset>
11081 <bitWidth>1</bitWidth>
11082 </field>
11083 <field>
11084 <name>RWSTOP</name>
11085 <description>Read wait stop</description>
11086 <bitOffset>9</bitOffset>
11087 <bitWidth>1</bitWidth>
11088 </field>
11089 <field>
11090 <name>RWSTART</name>
11091 <description>Read wait start</description>
11092 <bitOffset>8</bitOffset>
11093 <bitWidth>1</bitWidth>
11094 </field>
11095 <field>
11096 <name>DBLOCKSIZE</name>
11097 <description>Data block size</description>
11098 <bitOffset>4</bitOffset>
11099 <bitWidth>4</bitWidth>
11100 </field>
11101 <field>
11102 <name>DMAEN</name>
11103 <description>DMA enable bit</description>
11104 <bitOffset>3</bitOffset>
11105 <bitWidth>1</bitWidth>
11106 </field>
11107 <field>
11108 <name>DTMODE</name>
11109 <description>Data transfer mode selection 1: Stream
11110 or SDIO multibyte data transfer.</description>
11111 <bitOffset>2</bitOffset>
11112 <bitWidth>1</bitWidth>
11113 </field>
11114 <field>
11115 <name>DTDIR</name>
11116 <description>Data transfer direction
11117 selection</description>
11118 <bitOffset>1</bitOffset>
11119 <bitWidth>1</bitWidth>
11120 </field>
11121 <field>
11122 <name>DTEN</name>
11123 <description>DTEN</description>
11124 <bitOffset>0</bitOffset>
11125 <bitWidth>1</bitWidth>
11126 </field>
11127 </fields>
11128 </register>
11129 <register>
11130 <name>DCOUNT</name>
11131 <displayName>DCOUNT</displayName>
11132 <description>data counter register</description>
11133 <addressOffset>0x30</addressOffset>
11134 <size>0x20</size>
11135 <access>read-only</access>
11136 <resetValue>0x00000000</resetValue>
11137 <fields>
11138 <field>
11139 <name>DATACOUNT</name>
11140 <description>Data count value</description>
11141 <bitOffset>0</bitOffset>
11142 <bitWidth>25</bitWidth>
11143 </field>
11144 </fields>
11145 </register>
11146 <register>
11147 <name>STA</name>
11148 <displayName>STA</displayName>
11149 <description>status register</description>
11150 <addressOffset>0x34</addressOffset>
11151 <size>0x20</size>
11152 <access>read-only</access>
11153 <resetValue>0x00000000</resetValue>
11154 <fields>
11155 <field>
11156 <name>CEATAEND</name>
11157 <description>CE-ATA command completion signal
11158 received for CMD61</description>
11159 <bitOffset>23</bitOffset>
11160 <bitWidth>1</bitWidth>
11161 </field>
11162 <field>
11163 <name>SDIOIT</name>
11164 <description>SDIO interrupt received</description>
11165 <bitOffset>22</bitOffset>
11166 <bitWidth>1</bitWidth>
11167 </field>
11168 <field>
11169 <name>RXDAVL</name>
11170 <description>Data available in receive
11171 FIFO</description>
11172 <bitOffset>21</bitOffset>
11173 <bitWidth>1</bitWidth>
11174 </field>
11175 <field>
11176 <name>TXDAVL</name>
11177 <description>Data available in transmit
11178 FIFO</description>
11179 <bitOffset>20</bitOffset>
11180 <bitWidth>1</bitWidth>
11181 </field>
11182 <field>
11183 <name>RXFIFOE</name>
11184 <description>Receive FIFO empty</description>
11185 <bitOffset>19</bitOffset>
11186 <bitWidth>1</bitWidth>
11187 </field>
11188 <field>
11189 <name>TXFIFOE</name>
11190 <description>Transmit FIFO empty</description>
11191 <bitOffset>18</bitOffset>
11192 <bitWidth>1</bitWidth>
11193 </field>
11194 <field>
11195 <name>RXFIFOF</name>
11196 <description>Receive FIFO full</description>
11197 <bitOffset>17</bitOffset>
11198 <bitWidth>1</bitWidth>
11199 </field>
11200 <field>
11201 <name>TXFIFOF</name>
11202 <description>Transmit FIFO full</description>
11203 <bitOffset>16</bitOffset>
11204 <bitWidth>1</bitWidth>
11205 </field>
11206 <field>
11207 <name>RXFIFOHF</name>
11208 <description>Receive FIFO half full: there are at
11209 least 8 words in the FIFO</description>
11210 <bitOffset>15</bitOffset>
11211 <bitWidth>1</bitWidth>
11212 </field>
11213 <field>
11214 <name>TXFIFOHE</name>
11215 <description>Transmit FIFO half empty: at least 8
11216 words can be written into the FIFO</description>
11217 <bitOffset>14</bitOffset>
11218 <bitWidth>1</bitWidth>
11219 </field>
11220 <field>
11221 <name>RXACT</name>
11222 <description>Data receive in progress</description>
11223 <bitOffset>13</bitOffset>
11224 <bitWidth>1</bitWidth>
11225 </field>
11226 <field>
11227 <name>TXACT</name>
11228 <description>Data transmit in progress</description>
11229 <bitOffset>12</bitOffset>
11230 <bitWidth>1</bitWidth>
11231 </field>
11232 <field>
11233 <name>CMDACT</name>
11234 <description>Command transfer in
11235 progress</description>
11236 <bitOffset>11</bitOffset>
11237 <bitWidth>1</bitWidth>
11238 </field>
11239 <field>
11240 <name>DBCKEND</name>
11241 <description>Data block sent/received (CRC check
11242 passed)</description>
11243 <bitOffset>10</bitOffset>
11244 <bitWidth>1</bitWidth>
11245 </field>
11246 <field>
11247 <name>STBITERR</name>
11248 <description>Start bit not detected on all data
11249 signals in wide bus mode</description>
11250 <bitOffset>9</bitOffset>
11251 <bitWidth>1</bitWidth>
11252 </field>
11253 <field>
11254 <name>DATAEND</name>
11255 <description>Data end (data counter, SDIDCOUNT, is
11256 zero)</description>
11257 <bitOffset>8</bitOffset>
11258 <bitWidth>1</bitWidth>
11259 </field>
11260 <field>
11261 <name>CMDSENT</name>
11262 <description>Command sent (no response
11263 required)</description>
11264 <bitOffset>7</bitOffset>
11265 <bitWidth>1</bitWidth>
11266 </field>
11267 <field>
11268 <name>CMDREND</name>
11269 <description>Command response received (CRC check
11270 passed)</description>
11271 <bitOffset>6</bitOffset>
11272 <bitWidth>1</bitWidth>
11273 </field>
11274 <field>
11275 <name>RXOVERR</name>
11276 <description>Received FIFO overrun
11277 error</description>
11278 <bitOffset>5</bitOffset>
11279 <bitWidth>1</bitWidth>
11280 </field>
11281 <field>
11282 <name>TXUNDERR</name>
11283 <description>Transmit FIFO underrun
11284 error</description>
11285 <bitOffset>4</bitOffset>
11286 <bitWidth>1</bitWidth>
11287 </field>
11288 <field>
11289 <name>DTIMEOUT</name>
11290 <description>Data timeout</description>
11291 <bitOffset>3</bitOffset>
11292 <bitWidth>1</bitWidth>
11293 </field>
11294 <field>
11295 <name>CTIMEOUT</name>
11296 <description>Command response timeout</description>
11297 <bitOffset>2</bitOffset>
11298 <bitWidth>1</bitWidth>
11299 </field>
11300 <field>
11301 <name>DCRCFAIL</name>
11302 <description>Data block sent/received (CRC check
11303 failed)</description>
11304 <bitOffset>1</bitOffset>
11305 <bitWidth>1</bitWidth>
11306 </field>
11307 <field>
11308 <name>CCRCFAIL</name>
11309 <description>Command response received (CRC check
11310 failed)</description>
11311 <bitOffset>0</bitOffset>
11312 <bitWidth>1</bitWidth>
11313 </field>
11314 </fields>
11315 </register>
11316 <register>
11317 <name>ICR</name>
11318 <displayName>ICR</displayName>
11319 <description>interrupt clear register</description>
11320 <addressOffset>0x38</addressOffset>
11321 <size>0x20</size>
11322 <access>read-write</access>
11323 <resetValue>0x00000000</resetValue>
11324 <fields>
11325 <field>
11326 <name>CEATAENDC</name>
11327 <description>CEATAEND flag clear bit</description>
11328 <bitOffset>23</bitOffset>
11329 <bitWidth>1</bitWidth>
11330 </field>
11331 <field>
11332 <name>SDIOITC</name>
11333 <description>SDIOIT flag clear bit</description>
11334 <bitOffset>22</bitOffset>
11335 <bitWidth>1</bitWidth>
11336 </field>
11337 <field>
11338 <name>DBCKENDC</name>
11339 <description>DBCKEND flag clear bit</description>
11340 <bitOffset>10</bitOffset>
11341 <bitWidth>1</bitWidth>
11342 </field>
11343 <field>
11344 <name>STBITERRC</name>
11345 <description>STBITERR flag clear bit</description>
11346 <bitOffset>9</bitOffset>
11347 <bitWidth>1</bitWidth>
11348 </field>
11349 <field>
11350 <name>DATAENDC</name>
11351 <description>DATAEND flag clear bit</description>
11352 <bitOffset>8</bitOffset>
11353 <bitWidth>1</bitWidth>
11354 </field>
11355 <field>
11356 <name>CMDSENTC</name>
11357 <description>CMDSENT flag clear bit</description>
11358 <bitOffset>7</bitOffset>
11359 <bitWidth>1</bitWidth>
11360 </field>
11361 <field>
11362 <name>CMDRENDC</name>
11363 <description>CMDREND flag clear bit</description>
11364 <bitOffset>6</bitOffset>
11365 <bitWidth>1</bitWidth>
11366 </field>
11367 <field>
11368 <name>RXOVERRC</name>
11369 <description>RXOVERR flag clear bit</description>
11370 <bitOffset>5</bitOffset>
11371 <bitWidth>1</bitWidth>
11372 </field>
11373 <field>
11374 <name>TXUNDERRC</name>
11375 <description>TXUNDERR flag clear bit</description>
11376 <bitOffset>4</bitOffset>
11377 <bitWidth>1</bitWidth>
11378 </field>
11379 <field>
11380 <name>DTIMEOUTC</name>
11381 <description>DTIMEOUT flag clear bit</description>
11382 <bitOffset>3</bitOffset>
11383 <bitWidth>1</bitWidth>
11384 </field>
11385 <field>
11386 <name>CTIMEOUTC</name>
11387 <description>CTIMEOUT flag clear bit</description>
11388 <bitOffset>2</bitOffset>
11389 <bitWidth>1</bitWidth>
11390 </field>
11391 <field>
11392 <name>DCRCFAILC</name>
11393 <description>DCRCFAIL flag clear bit</description>
11394 <bitOffset>1</bitOffset>
11395 <bitWidth>1</bitWidth>
11396 </field>
11397 <field>
11398 <name>CCRCFAILC</name>
11399 <description>CCRCFAIL flag clear bit</description>
11400 <bitOffset>0</bitOffset>
11401 <bitWidth>1</bitWidth>
11402 </field>
11403 </fields>
11404 </register>
11405 <register>
11406 <name>MASK</name>
11407 <displayName>MASK</displayName>
11408 <description>mask register</description>
11409 <addressOffset>0x3C</addressOffset>
11410 <size>0x20</size>
11411 <access>read-write</access>
11412 <resetValue>0x00000000</resetValue>
11413 <fields>
11414 <field>
11415 <name>CEATAENDIE</name>
11416 <description>CE-ATA command completion signal
11417 received interrupt enable</description>
11418 <bitOffset>23</bitOffset>
11419 <bitWidth>1</bitWidth>
11420 </field>
11421 <field>
11422 <name>SDIOITIE</name>
11423 <description>SDIO mode interrupt received interrupt
11424 enable</description>
11425 <bitOffset>22</bitOffset>
11426 <bitWidth>1</bitWidth>
11427 </field>
11428 <field>
11429 <name>RXDAVLIE</name>
11430 <description>Data available in Rx FIFO interrupt
11431 enable</description>
11432 <bitOffset>21</bitOffset>
11433 <bitWidth>1</bitWidth>
11434 </field>
11435 <field>
11436 <name>TXDAVLIE</name>
11437 <description>Data available in Tx FIFO interrupt
11438 enable</description>
11439 <bitOffset>20</bitOffset>
11440 <bitWidth>1</bitWidth>
11441 </field>
11442 <field>
11443 <name>RXFIFOEIE</name>
11444 <description>Rx FIFO empty interrupt
11445 enable</description>
11446 <bitOffset>19</bitOffset>
11447 <bitWidth>1</bitWidth>
11448 </field>
11449 <field>
11450 <name>TXFIFOEIE</name>
11451 <description>Tx FIFO empty interrupt
11452 enable</description>
11453 <bitOffset>18</bitOffset>
11454 <bitWidth>1</bitWidth>
11455 </field>
11456 <field>
11457 <name>RXFIFOFIE</name>
11458 <description>Rx FIFO full interrupt
11459 enable</description>
11460 <bitOffset>17</bitOffset>
11461 <bitWidth>1</bitWidth>
11462 </field>
11463 <field>
11464 <name>TXFIFOFIE</name>
11465 <description>Tx FIFO full interrupt
11466 enable</description>
11467 <bitOffset>16</bitOffset>
11468 <bitWidth>1</bitWidth>
11469 </field>
11470 <field>
11471 <name>RXFIFOHFIE</name>
11472 <description>Rx FIFO half full interrupt
11473 enable</description>
11474 <bitOffset>15</bitOffset>
11475 <bitWidth>1</bitWidth>
11476 </field>
11477 <field>
11478 <name>TXFIFOHEIE</name>
11479 <description>Tx FIFO half empty interrupt
11480 enable</description>
11481 <bitOffset>14</bitOffset>
11482 <bitWidth>1</bitWidth>
11483 </field>
11484 <field>
11485 <name>RXACTIE</name>
11486 <description>Data receive acting interrupt
11487 enable</description>
11488 <bitOffset>13</bitOffset>
11489 <bitWidth>1</bitWidth>
11490 </field>
11491 <field>
11492 <name>TXACTIE</name>
11493 <description>Data transmit acting interrupt
11494 enable</description>
11495 <bitOffset>12</bitOffset>
11496 <bitWidth>1</bitWidth>
11497 </field>
11498 <field>
11499 <name>CMDACTIE</name>
11500 <description>Command acting interrupt
11501 enable</description>
11502 <bitOffset>11</bitOffset>
11503 <bitWidth>1</bitWidth>
11504 </field>
11505 <field>
11506 <name>DBCKENDIE</name>
11507 <description>Data block end interrupt
11508 enable</description>
11509 <bitOffset>10</bitOffset>
11510 <bitWidth>1</bitWidth>
11511 </field>
11512 <field>
11513 <name>STBITERRIE</name>
11514 <description>Start bit error interrupt
11515 enable</description>
11516 <bitOffset>9</bitOffset>
11517 <bitWidth>1</bitWidth>
11518 </field>
11519 <field>
11520 <name>DATAENDIE</name>
11521 <description>Data end interrupt enable</description>
11522 <bitOffset>8</bitOffset>
11523 <bitWidth>1</bitWidth>
11524 </field>
11525 <field>
11526 <name>CMDSENTIE</name>
11527 <description>Command sent interrupt
11528 enable</description>
11529 <bitOffset>7</bitOffset>
11530 <bitWidth>1</bitWidth>
11531 </field>
11532 <field>
11533 <name>CMDRENDIE</name>
11534 <description>Command response received interrupt
11535 enable</description>
11536 <bitOffset>6</bitOffset>
11537 <bitWidth>1</bitWidth>
11538 </field>
11539 <field>
11540 <name>RXOVERRIE</name>
11541 <description>Rx FIFO overrun error interrupt
11542 enable</description>
11543 <bitOffset>5</bitOffset>
11544 <bitWidth>1</bitWidth>
11545 </field>
11546 <field>
11547 <name>TXUNDERRIE</name>
11548 <description>Tx FIFO underrun error interrupt
11549 enable</description>
11550 <bitOffset>4</bitOffset>
11551 <bitWidth>1</bitWidth>
11552 </field>
11553 <field>
11554 <name>DTIMEOUTIE</name>
11555 <description>Data timeout interrupt
11556 enable</description>
11557 <bitOffset>3</bitOffset>
11558 <bitWidth>1</bitWidth>
11559 </field>
11560 <field>
11561 <name>CTIMEOUTIE</name>
11562 <description>Command timeout interrupt
11563 enable</description>
11564 <bitOffset>2</bitOffset>
11565 <bitWidth>1</bitWidth>
11566 </field>
11567 <field>
11568 <name>DCRCFAILIE</name>
11569 <description>Data CRC fail interrupt
11570 enable</description>
11571 <bitOffset>1</bitOffset>
11572 <bitWidth>1</bitWidth>
11573 </field>
11574 <field>
11575 <name>CCRCFAILIE</name>
11576 <description>Command CRC fail interrupt
11577 enable</description>
11578 <bitOffset>0</bitOffset>
11579 <bitWidth>1</bitWidth>
11580 </field>
11581 </fields>
11582 </register>
11583 <register>
11584 <name>FIFOCNT</name>
11585 <displayName>FIFOCNT</displayName>
11586 <description>FIFO counter register</description>
11587 <addressOffset>0x48</addressOffset>
11588 <size>0x20</size>
11589 <access>read-only</access>
11590 <resetValue>0x00000000</resetValue>
11591 <fields>
11592 <field>
11593 <name>FIFOCOUNT</name>
11594 <description>Remaining number of words to be written
11595 to or read from the FIFO.</description>
11596 <bitOffset>0</bitOffset>
11597 <bitWidth>24</bitWidth>
11598 </field>
11599 </fields>
11600 </register>
11601 <register>
11602 <name>FIFO</name>
11603 <displayName>FIFO</displayName>
11604 <description>data FIFO register</description>
11605 <addressOffset>0x80</addressOffset>
11606 <size>0x20</size>
11607 <access>read-write</access>
11608 <resetValue>0x00000000</resetValue>
11609 <fields>
11610 <field>
11611 <name>FIFOData</name>
11612 <description>Receive and transmit FIFO
11613 data</description>
11614 <bitOffset>0</bitOffset>
11615 <bitWidth>32</bitWidth>
11616 </field>
11617 </fields>
11618 </register>
11619 </registers>
11620 </peripheral>
11621 <peripheral>
11622 <name>SYSCFG</name>
11623 <description>System configuration controller</description>
11624 <groupName>SYSCFG</groupName>
11625 <baseAddress>0x40013800</baseAddress>
11626 <addressBlock>
11627 <offset>0x0</offset>
11628 <size>0x400</size>
11629 <usage>registers</usage>
11630 </addressBlock>
11631 <registers>
11632 <register>
11633 <name>MEMRM</name>
11634 <displayName>MEMRM</displayName>
11635 <description>memory remap register</description>
11636 <addressOffset>0x0</addressOffset>
11637 <size>0x20</size>
11638 <access>read-write</access>
11639 <resetValue>0x00000000</resetValue>
11640 <fields>
11641 <field>
11642 <name>MEM_MODE</name>
11643 <description>MEM_MODE</description>
11644 <bitOffset>0</bitOffset>
11645 <bitWidth>2</bitWidth>
11646 </field>
11647 </fields>
11648 </register>
11649 <register>
11650 <name>PMC</name>
11651 <displayName>PMC</displayName>
11652 <description>peripheral mode configuration
11653 register</description>
11654 <addressOffset>0x4</addressOffset>
11655 <size>0x20</size>
11656 <access>read-write</access>
11657 <resetValue>0x00000000</resetValue>
11658 <fields>
11659 <field>
11660 <name>ADC1DC2</name>
11661 <description>ADC1DC2</description>
11662 <bitOffset>16</bitOffset>
11663 <bitWidth>1</bitWidth>
11664 </field>
11665 </fields>
11666 </register>
11667 <register>
11668 <name>EXTICR1</name>
11669 <displayName>EXTICR1</displayName>
11670 <description>external interrupt configuration register
11671 1</description>
11672 <addressOffset>0x8</addressOffset>
11673 <size>0x20</size>
11674 <access>read-write</access>
11675 <resetValue>0x0000</resetValue>
11676 <fields>
11677 <field>
11678 <name>EXTI3</name>
11679 <description>EXTI x configuration (x = 0 to
11680 3)</description>
11681 <bitOffset>12</bitOffset>
11682 <bitWidth>4</bitWidth>
11683 </field>
11684 <field>
11685 <name>EXTI2</name>
11686 <description>EXTI x configuration (x = 0 to
11687 3)</description>
11688 <bitOffset>8</bitOffset>
11689 <bitWidth>4</bitWidth>
11690 </field>
11691 <field>
11692 <name>EXTI1</name>
11693 <description>EXTI x configuration (x = 0 to
11694 3)</description>
11695 <bitOffset>4</bitOffset>
11696 <bitWidth>4</bitWidth>
11697 </field>
11698 <field>
11699 <name>EXTI0</name>
11700 <description>EXTI x configuration (x = 0 to
11701 3)</description>
11702 <bitOffset>0</bitOffset>
11703 <bitWidth>4</bitWidth>
11704 </field>
11705 </fields>
11706 </register>
11707 <register>
11708 <name>EXTICR2</name>
11709 <displayName>EXTICR2</displayName>
11710 <description>external interrupt configuration register
11711 2</description>
11712 <addressOffset>0xC</addressOffset>
11713 <size>0x20</size>
11714 <access>read-write</access>
11715 <resetValue>0x0000</resetValue>
11716 <fields>
11717 <field>
11718 <name>EXTI7</name>
11719 <description>EXTI x configuration (x = 4 to
11720 7)</description>
11721 <bitOffset>12</bitOffset>
11722 <bitWidth>4</bitWidth>
11723 </field>
11724 <field>
11725 <name>EXTI6</name>
11726 <description>EXTI x configuration (x = 4 to
11727 7)</description>
11728 <bitOffset>8</bitOffset>
11729 <bitWidth>4</bitWidth>
11730 </field>
11731 <field>
11732 <name>EXTI5</name>
11733 <description>EXTI x configuration (x = 4 to
11734 7)</description>
11735 <bitOffset>4</bitOffset>
11736 <bitWidth>4</bitWidth>
11737 </field>
11738 <field>
11739 <name>EXTI4</name>
11740 <description>EXTI x configuration (x = 4 to
11741 7)</description>
11742 <bitOffset>0</bitOffset>
11743 <bitWidth>4</bitWidth>
11744 </field>
11745 </fields>
11746 </register>
11747 <register>
11748 <name>EXTICR3</name>
11749 <displayName>EXTICR3</displayName>
11750 <description>external interrupt configuration register
11751 3</description>
11752 <addressOffset>0x10</addressOffset>
11753 <size>0x20</size>
11754 <access>read-write</access>
11755 <resetValue>0x0000</resetValue>
11756 <fields>
11757 <field>
11758 <name>EXTI11</name>
11759 <description>EXTI x configuration (x = 8 to
11760 11)</description>
11761 <bitOffset>12</bitOffset>
11762 <bitWidth>4</bitWidth>
11763 </field>
11764 <field>
11765 <name>EXTI10</name>
11766 <description>EXTI10</description>
11767 <bitOffset>8</bitOffset>
11768 <bitWidth>4</bitWidth>
11769 </field>
11770 <field>
11771 <name>EXTI9</name>
11772 <description>EXTI x configuration (x = 8 to
11773 11)</description>
11774 <bitOffset>4</bitOffset>
11775 <bitWidth>4</bitWidth>
11776 </field>
11777 <field>
11778 <name>EXTI8</name>
11779 <description>EXTI x configuration (x = 8 to
11780 11)</description>
11781 <bitOffset>0</bitOffset>
11782 <bitWidth>4</bitWidth>
11783 </field>
11784 </fields>
11785 </register>
11786 <register>
11787 <name>EXTICR4</name>
11788 <displayName>EXTICR4</displayName>
11789 <description>external interrupt configuration register
11790 4</description>
11791 <addressOffset>0x14</addressOffset>
11792 <size>0x20</size>
11793 <access>read-write</access>
11794 <resetValue>0x0000</resetValue>
11795 <fields>
11796 <field>
11797 <name>EXTI15</name>
11798 <description>EXTI x configuration (x = 12 to
11799 15)</description>
11800 <bitOffset>12</bitOffset>
11801 <bitWidth>4</bitWidth>
11802 </field>
11803 <field>
11804 <name>EXTI14</name>
11805 <description>EXTI x configuration (x = 12 to
11806 15)</description>
11807 <bitOffset>8</bitOffset>
11808 <bitWidth>4</bitWidth>
11809 </field>
11810 <field>
11811 <name>EXTI13</name>
11812 <description>EXTI x configuration (x = 12 to
11813 15)</description>
11814 <bitOffset>4</bitOffset>
11815 <bitWidth>4</bitWidth>
11816 </field>
11817 <field>
11818 <name>EXTI12</name>
11819 <description>EXTI x configuration (x = 12 to
11820 15)</description>
11821 <bitOffset>0</bitOffset>
11822 <bitWidth>4</bitWidth>
11823 </field>
11824 </fields>
11825 </register>
11826 <register>
11827 <name>CMPCR</name>
11828 <displayName>CMPCR</displayName>
11829 <description>Compensation cell control
11830 register</description>
11831 <addressOffset>0x20</addressOffset>
11832 <size>0x20</size>
11833 <access>read-only</access>
11834 <resetValue>0x00000000</resetValue>
11835 <fields>
11836 <field>
11837 <name>READY</name>
11838 <description>READY</description>
11839 <bitOffset>8</bitOffset>
11840 <bitWidth>1</bitWidth>
11841 </field>
11842 <field>
11843 <name>CMP_PD</name>
11844 <description>Compensation cell
11845 power-down</description>
11846 <bitOffset>0</bitOffset>
11847 <bitWidth>1</bitWidth>
11848 </field>
11849 </fields>
11850 </register>
11851 </registers>
11852 </peripheral>
11853 <peripheral>
11854 <name>TIM1</name>
11855 <description>Advanced-timers</description>
11856 <groupName>TIM</groupName>
11857 <baseAddress>0x40010000</baseAddress>
11858 <addressBlock>
11859 <offset>0x0</offset>
11860 <size>0x400</size>
11861 <usage>registers</usage>
11862 </addressBlock>
11863 <registers>
11864 <register>
11865 <name>CR1</name>
11866 <displayName>CR1</displayName>
11867 <description>control register 1</description>
11868 <addressOffset>0x0</addressOffset>
11869 <size>0x20</size>
11870 <access>read-write</access>
11871 <resetValue>0x0000</resetValue>
11872 <fields>
11873 <field>
11874 <name>CKD</name>
11875 <description>Clock division</description>
11876 <bitOffset>8</bitOffset>
11877 <bitWidth>2</bitWidth>
11878 </field>
11879 <field>
11880 <name>ARPE</name>
11881 <description>Auto-reload preload enable</description>
11882 <bitOffset>7</bitOffset>
11883 <bitWidth>1</bitWidth>
11884 </field>
11885 <field>
11886 <name>CMS</name>
11887 <description>Center-aligned mode
11888 selection</description>
11889 <bitOffset>5</bitOffset>
11890 <bitWidth>2</bitWidth>
11891 </field>
11892 <field>
11893 <name>DIR</name>
11894 <description>Direction</description>
11895 <bitOffset>4</bitOffset>
11896 <bitWidth>1</bitWidth>
11897 </field>
11898 <field>
11899 <name>OPM</name>
11900 <description>One-pulse mode</description>
11901 <bitOffset>3</bitOffset>
11902 <bitWidth>1</bitWidth>
11903 </field>
11904 <field>
11905 <name>URS</name>
11906 <description>Update request source</description>
11907 <bitOffset>2</bitOffset>
11908 <bitWidth>1</bitWidth>
11909 </field>
11910 <field>
11911 <name>UDIS</name>
11912 <description>Update disable</description>
11913 <bitOffset>1</bitOffset>
11914 <bitWidth>1</bitWidth>
11915 </field>
11916 <field>
11917 <name>CEN</name>
11918 <description>Counter enable</description>
11919 <bitOffset>0</bitOffset>
11920 <bitWidth>1</bitWidth>
11921 </field>
11922 </fields>
11923 </register>
11924 <register>
11925 <name>CR2</name>
11926 <displayName>CR2</displayName>
11927 <description>control register 2</description>
11928 <addressOffset>0x4</addressOffset>
11929 <size>0x20</size>
11930 <access>read-write</access>
11931 <resetValue>0x0000</resetValue>
11932 <fields>
11933 <field>
11934 <name>OIS4</name>
11935 <description>Output Idle state 4</description>
11936 <bitOffset>14</bitOffset>
11937 <bitWidth>1</bitWidth>
11938 </field>
11939 <field>
11940 <name>OIS3N</name>
11941 <description>Output Idle state 3</description>
11942 <bitOffset>13</bitOffset>
11943 <bitWidth>1</bitWidth>
11944 </field>
11945 <field>
11946 <name>OIS3</name>
11947 <description>Output Idle state 3</description>
11948 <bitOffset>12</bitOffset>
11949 <bitWidth>1</bitWidth>
11950 </field>
11951 <field>
11952 <name>OIS2N</name>
11953 <description>Output Idle state 2</description>
11954 <bitOffset>11</bitOffset>
11955 <bitWidth>1</bitWidth>
11956 </field>
11957 <field>
11958 <name>OIS2</name>
11959 <description>Output Idle state 2</description>
11960 <bitOffset>10</bitOffset>
11961 <bitWidth>1</bitWidth>
11962 </field>
11963 <field>
11964 <name>OIS1N</name>
11965 <description>Output Idle state 1</description>
11966 <bitOffset>9</bitOffset>
11967 <bitWidth>1</bitWidth>
11968 </field>
11969 <field>
11970 <name>OIS1</name>
11971 <description>Output Idle state 1</description>
11972 <bitOffset>8</bitOffset>
11973 <bitWidth>1</bitWidth>
11974 </field>
11975 <field>
11976 <name>TI1S</name>
11977 <description>TI1 selection</description>
11978 <bitOffset>7</bitOffset>
11979 <bitWidth>1</bitWidth>
11980 </field>
11981 <field>
11982 <name>MMS</name>
11983 <description>Master mode selection</description>
11984 <bitOffset>4</bitOffset>
11985 <bitWidth>3</bitWidth>
11986 </field>
11987 <field>
11988 <name>CCDS</name>
11989 <description>Capture/compare DMA
11990 selection</description>
11991 <bitOffset>3</bitOffset>
11992 <bitWidth>1</bitWidth>
11993 </field>
11994 <field>
11995 <name>CCUS</name>
11996 <description>Capture/compare control update
11997 selection</description>
11998 <bitOffset>2</bitOffset>
11999 <bitWidth>1</bitWidth>
12000 </field>
12001 <field>
12002 <name>CCPC</name>
12003 <description>Capture/compare preloaded
12004 control</description>
12005 <bitOffset>0</bitOffset>
12006 <bitWidth>1</bitWidth>
12007 </field>
12008 </fields>
12009 </register>
12010 <register>
12011 <name>SMCR</name>
12012 <displayName>SMCR</displayName>
12013 <description>slave mode control register</description>
12014 <addressOffset>0x8</addressOffset>
12015 <size>0x20</size>
12016 <access>read-write</access>
12017 <resetValue>0x0000</resetValue>
12018 <fields>
12019 <field>
12020 <name>ETP</name>
12021 <description>External trigger polarity</description>
12022 <bitOffset>15</bitOffset>
12023 <bitWidth>1</bitWidth>
12024 </field>
12025 <field>
12026 <name>ECE</name>
12027 <description>External clock enable</description>
12028 <bitOffset>14</bitOffset>
12029 <bitWidth>1</bitWidth>
12030 </field>
12031 <field>
12032 <name>ETPS</name>
12033 <description>External trigger prescaler</description>
12034 <bitOffset>12</bitOffset>
12035 <bitWidth>2</bitWidth>
12036 </field>
12037 <field>
12038 <name>ETF</name>
12039 <description>External trigger filter</description>
12040 <bitOffset>8</bitOffset>
12041 <bitWidth>4</bitWidth>
12042 </field>
12043 <field>
12044 <name>MSM</name>
12045 <description>Master/Slave mode</description>
12046 <bitOffset>7</bitOffset>
12047 <bitWidth>1</bitWidth>
12048 </field>
12049 <field>
12050 <name>TS</name>
12051 <description>Trigger selection</description>
12052 <bitOffset>4</bitOffset>
12053 <bitWidth>3</bitWidth>
12054 </field>
12055 <field>
12056 <name>SMS</name>
12057 <description>Slave mode selection</description>
12058 <bitOffset>0</bitOffset>
12059 <bitWidth>3</bitWidth>
12060 </field>
12061 </fields>
12062 </register>
12063 <register>
12064 <name>DIER</name>
12065 <displayName>DIER</displayName>
12066 <description>DMA/Interrupt enable register</description>
12067 <addressOffset>0xC</addressOffset>
12068 <size>0x20</size>
12069 <access>read-write</access>
12070 <resetValue>0x0000</resetValue>
12071 <fields>
12072 <field>
12073 <name>TDE</name>
12074 <description>Trigger DMA request enable</description>
12075 <bitOffset>14</bitOffset>
12076 <bitWidth>1</bitWidth>
12077 </field>
12078 <field>
12079 <name>COMDE</name>
12080 <description>COM DMA request enable</description>
12081 <bitOffset>13</bitOffset>
12082 <bitWidth>1</bitWidth>
12083 </field>
12084 <field>
12085 <name>CC4DE</name>
12086 <description>Capture/Compare 4 DMA request
12087 enable</description>
12088 <bitOffset>12</bitOffset>
12089 <bitWidth>1</bitWidth>
12090 </field>
12091 <field>
12092 <name>CC3DE</name>
12093 <description>Capture/Compare 3 DMA request
12094 enable</description>
12095 <bitOffset>11</bitOffset>
12096 <bitWidth>1</bitWidth>
12097 </field>
12098 <field>
12099 <name>CC2DE</name>
12100 <description>Capture/Compare 2 DMA request
12101 enable</description>
12102 <bitOffset>10</bitOffset>
12103 <bitWidth>1</bitWidth>
12104 </field>
12105 <field>
12106 <name>CC1DE</name>
12107 <description>Capture/Compare 1 DMA request
12108 enable</description>
12109 <bitOffset>9</bitOffset>
12110 <bitWidth>1</bitWidth>
12111 </field>
12112 <field>
12113 <name>UDE</name>
12114 <description>Update DMA request enable</description>
12115 <bitOffset>8</bitOffset>
12116 <bitWidth>1</bitWidth>
12117 </field>
12118 <field>
12119 <name>BIE</name>
12120 <description>Break interrupt enable</description>
12121 <bitOffset>7</bitOffset>
12122 <bitWidth>1</bitWidth>
12123 </field>
12124 <field>
12125 <name>TIE</name>
12126 <description>Trigger interrupt enable</description>
12127 <bitOffset>6</bitOffset>
12128 <bitWidth>1</bitWidth>
12129 </field>
12130 <field>
12131 <name>COMIE</name>
12132 <description>COM interrupt enable</description>
12133 <bitOffset>5</bitOffset>
12134 <bitWidth>1</bitWidth>
12135 </field>
12136 <field>
12137 <name>CC4IE</name>
12138 <description>Capture/Compare 4 interrupt
12139 enable</description>
12140 <bitOffset>4</bitOffset>
12141 <bitWidth>1</bitWidth>
12142 </field>
12143 <field>
12144 <name>CC3IE</name>
12145 <description>Capture/Compare 3 interrupt
12146 enable</description>
12147 <bitOffset>3</bitOffset>
12148 <bitWidth>1</bitWidth>
12149 </field>
12150 <field>
12151 <name>CC2IE</name>
12152 <description>Capture/Compare 2 interrupt
12153 enable</description>
12154 <bitOffset>2</bitOffset>
12155 <bitWidth>1</bitWidth>
12156 </field>
12157 <field>
12158 <name>CC1IE</name>
12159 <description>Capture/Compare 1 interrupt
12160 enable</description>
12161 <bitOffset>1</bitOffset>
12162 <bitWidth>1</bitWidth>
12163 </field>
12164 <field>
12165 <name>UIE</name>
12166 <description>Update interrupt enable</description>
12167 <bitOffset>0</bitOffset>
12168 <bitWidth>1</bitWidth>
12169 </field>
12170 </fields>
12171 </register>
12172 <register>
12173 <name>SR</name>
12174 <displayName>SR</displayName>
12175 <description>status register</description>
12176 <addressOffset>0x10</addressOffset>
12177 <size>0x20</size>
12178 <access>read-write</access>
12179 <resetValue>0x0000</resetValue>
12180 <fields>
12181 <field>
12182 <name>CC4OF</name>
12183 <description>Capture/Compare 4 overcapture
12184 flag</description>
12185 <bitOffset>12</bitOffset>
12186 <bitWidth>1</bitWidth>
12187 </field>
12188 <field>
12189 <name>CC3OF</name>
12190 <description>Capture/Compare 3 overcapture
12191 flag</description>
12192 <bitOffset>11</bitOffset>
12193 <bitWidth>1</bitWidth>
12194 </field>
12195 <field>
12196 <name>CC2OF</name>
12197 <description>Capture/compare 2 overcapture
12198 flag</description>
12199 <bitOffset>10</bitOffset>
12200 <bitWidth>1</bitWidth>
12201 </field>
12202 <field>
12203 <name>CC1OF</name>
12204 <description>Capture/Compare 1 overcapture
12205 flag</description>
12206 <bitOffset>9</bitOffset>
12207 <bitWidth>1</bitWidth>
12208 </field>
12209 <field>
12210 <name>BIF</name>
12211 <description>Break interrupt flag</description>
12212 <bitOffset>7</bitOffset>
12213 <bitWidth>1</bitWidth>
12214 </field>
12215 <field>
12216 <name>TIF</name>
12217 <description>Trigger interrupt flag</description>
12218 <bitOffset>6</bitOffset>
12219 <bitWidth>1</bitWidth>
12220 </field>
12221 <field>
12222 <name>COMIF</name>
12223 <description>COM interrupt flag</description>
12224 <bitOffset>5</bitOffset>
12225 <bitWidth>1</bitWidth>
12226 </field>
12227 <field>
12228 <name>CC4IF</name>
12229 <description>Capture/Compare 4 interrupt
12230 flag</description>
12231 <bitOffset>4</bitOffset>
12232 <bitWidth>1</bitWidth>
12233 </field>
12234 <field>
12235 <name>CC3IF</name>
12236 <description>Capture/Compare 3 interrupt
12237 flag</description>
12238 <bitOffset>3</bitOffset>
12239 <bitWidth>1</bitWidth>
12240 </field>
12241 <field>
12242 <name>CC2IF</name>
12243 <description>Capture/Compare 2 interrupt
12244 flag</description>
12245 <bitOffset>2</bitOffset>
12246 <bitWidth>1</bitWidth>
12247 </field>
12248 <field>
12249 <name>CC1IF</name>
12250 <description>Capture/compare 1 interrupt
12251 flag</description>
12252 <bitOffset>1</bitOffset>
12253 <bitWidth>1</bitWidth>
12254 </field>
12255 <field>
12256 <name>UIF</name>
12257 <description>Update interrupt flag</description>
12258 <bitOffset>0</bitOffset>
12259 <bitWidth>1</bitWidth>
12260 </field>
12261 </fields>
12262 </register>
12263 <register>
12264 <name>EGR</name>
12265 <displayName>EGR</displayName>
12266 <description>event generation register</description>
12267 <addressOffset>0x14</addressOffset>
12268 <size>0x20</size>
12269 <access>write-only</access>
12270 <resetValue>0x0000</resetValue>
12271 <fields>
12272 <field>
12273 <name>BG</name>
12274 <description>Break generation</description>
12275 <bitOffset>7</bitOffset>
12276 <bitWidth>1</bitWidth>
12277 </field>
12278 <field>
12279 <name>TG</name>
12280 <description>Trigger generation</description>
12281 <bitOffset>6</bitOffset>
12282 <bitWidth>1</bitWidth>
12283 </field>
12284 <field>
12285 <name>COMG</name>
12286 <description>Capture/Compare control update
12287 generation</description>
12288 <bitOffset>5</bitOffset>
12289 <bitWidth>1</bitWidth>
12290 </field>
12291 <field>
12292 <name>CC4G</name>
12293 <description>Capture/compare 4
12294 generation</description>
12295 <bitOffset>4</bitOffset>
12296 <bitWidth>1</bitWidth>
12297 </field>
12298 <field>
12299 <name>CC3G</name>
12300 <description>Capture/compare 3
12301 generation</description>
12302 <bitOffset>3</bitOffset>
12303 <bitWidth>1</bitWidth>
12304 </field>
12305 <field>
12306 <name>CC2G</name>
12307 <description>Capture/compare 2
12308 generation</description>
12309 <bitOffset>2</bitOffset>
12310 <bitWidth>1</bitWidth>
12311 </field>
12312 <field>
12313 <name>CC1G</name>
12314 <description>Capture/compare 1
12315 generation</description>
12316 <bitOffset>1</bitOffset>
12317 <bitWidth>1</bitWidth>
12318 </field>
12319 <field>
12320 <name>UG</name>
12321 <description>Update generation</description>
12322 <bitOffset>0</bitOffset>
12323 <bitWidth>1</bitWidth>
12324 </field>
12325 </fields>
12326 </register>
12327 <register>
12328 <name>CCMR1_Output</name>
12329 <displayName>CCMR1_Output</displayName>
12330 <description>capture/compare mode register 1 (output
12331 mode)</description>
12332 <addressOffset>0x18</addressOffset>
12333 <size>0x20</size>
12334 <access>read-write</access>
12335 <resetValue>0x00000000</resetValue>
12336 <fields>
12337 <field>
12338 <name>OC2CE</name>
12339 <description>Output Compare 2 clear
12340 enable</description>
12341 <bitOffset>15</bitOffset>
12342 <bitWidth>1</bitWidth>
12343 </field>
12344 <field>
12345 <name>OC2M</name>
12346 <description>Output Compare 2 mode</description>
12347 <bitOffset>12</bitOffset>
12348 <bitWidth>3</bitWidth>
12349 </field>
12350 <field>
12351 <name>OC2PE</name>
12352 <description>Output Compare 2 preload
12353 enable</description>
12354 <bitOffset>11</bitOffset>
12355 <bitWidth>1</bitWidth>
12356 </field>
12357 <field>
12358 <name>OC2FE</name>
12359 <description>Output Compare 2 fast
12360 enable</description>
12361 <bitOffset>10</bitOffset>
12362 <bitWidth>1</bitWidth>
12363 </field>
12364 <field>
12365 <name>CC2S</name>
12366 <description>Capture/Compare 2
12367 selection</description>
12368 <bitOffset>8</bitOffset>
12369 <bitWidth>2</bitWidth>
12370 </field>
12371 <field>
12372 <name>OC1CE</name>
12373 <description>Output Compare 1 clear
12374 enable</description>
12375 <bitOffset>7</bitOffset>
12376 <bitWidth>1</bitWidth>
12377 </field>
12378 <field>
12379 <name>OC1M</name>
12380 <description>Output Compare 1 mode</description>
12381 <bitOffset>4</bitOffset>
12382 <bitWidth>3</bitWidth>
12383 </field>
12384 <field>
12385 <name>OC1PE</name>
12386 <description>Output Compare 1 preload
12387 enable</description>
12388 <bitOffset>3</bitOffset>
12389 <bitWidth>1</bitWidth>
12390 </field>
12391 <field>
12392 <name>OC1FE</name>
12393 <description>Output Compare 1 fast
12394 enable</description>
12395 <bitOffset>2</bitOffset>
12396 <bitWidth>1</bitWidth>
12397 </field>
12398 <field>
12399 <name>CC1S</name>
12400 <description>Capture/Compare 1
12401 selection</description>
12402 <bitOffset>0</bitOffset>
12403 <bitWidth>2</bitWidth>
12404 </field>
12405 </fields>
12406 </register>
12407 <register>
12408 <name>CCMR1_Input</name>
12409 <displayName>CCMR1_Input</displayName>
12410 <description>capture/compare mode register 1 (input
12411 mode)</description>
12412 <alternateRegister>CCMR1_Output</alternateRegister>
12413 <addressOffset>0x18</addressOffset>
12414 <size>0x20</size>
12415 <access>read-write</access>
12416 <resetValue>0x00000000</resetValue>
12417 <fields>
12418 <field>
12419 <name>IC2F</name>
12420 <description>Input capture 2 filter</description>
12421 <bitOffset>12</bitOffset>
12422 <bitWidth>4</bitWidth>
12423 </field>
12424 <field>
12425 <name>IC2PCS</name>
12426 <description>Input capture 2 prescaler</description>
12427 <bitOffset>10</bitOffset>
12428 <bitWidth>2</bitWidth>
12429 </field>
12430 <field>
12431 <name>CC2S</name>
12432 <description>Capture/Compare 2
12433 selection</description>
12434 <bitOffset>8</bitOffset>
12435 <bitWidth>2</bitWidth>
12436 </field>
12437 <field>
12438 <name>IC1F</name>
12439 <description>Input capture 1 filter</description>
12440 <bitOffset>4</bitOffset>
12441 <bitWidth>4</bitWidth>
12442 </field>
12443 <field>
12444 <name>ICPCS</name>
12445 <description>Input capture 1 prescaler</description>
12446 <bitOffset>2</bitOffset>
12447 <bitWidth>2</bitWidth>
12448 </field>
12449 <field>
12450 <name>CC1S</name>
12451 <description>Capture/Compare 1
12452 selection</description>
12453 <bitOffset>0</bitOffset>
12454 <bitWidth>2</bitWidth>
12455 </field>
12456 </fields>
12457 </register>
12458 <register>
12459 <name>CCMR2_Output</name>
12460 <displayName>CCMR2_Output</displayName>
12461 <description>capture/compare mode register 2 (output
12462 mode)</description>
12463 <addressOffset>0x1C</addressOffset>
12464 <size>0x20</size>
12465 <access>read-write</access>
12466 <resetValue>0x00000000</resetValue>
12467 <fields>
12468 <field>
12469 <name>OC4CE</name>
12470 <description>Output compare 4 clear
12471 enable</description>
12472 <bitOffset>15</bitOffset>
12473 <bitWidth>1</bitWidth>
12474 </field>
12475 <field>
12476 <name>OC4M</name>
12477 <description>Output compare 4 mode</description>
12478 <bitOffset>12</bitOffset>
12479 <bitWidth>3</bitWidth>
12480 </field>
12481 <field>
12482 <name>OC4PE</name>
12483 <description>Output compare 4 preload
12484 enable</description>
12485 <bitOffset>11</bitOffset>
12486 <bitWidth>1</bitWidth>
12487 </field>
12488 <field>
12489 <name>OC4FE</name>
12490 <description>Output compare 4 fast
12491 enable</description>
12492 <bitOffset>10</bitOffset>
12493 <bitWidth>1</bitWidth>
12494 </field>
12495 <field>
12496 <name>CC4S</name>
12497 <description>Capture/Compare 4
12498 selection</description>
12499 <bitOffset>8</bitOffset>
12500 <bitWidth>2</bitWidth>
12501 </field>
12502 <field>
12503 <name>OC3CE</name>
12504 <description>Output compare 3 clear
12505 enable</description>
12506 <bitOffset>7</bitOffset>
12507 <bitWidth>1</bitWidth>
12508 </field>
12509 <field>
12510 <name>OC3M</name>
12511 <description>Output compare 3 mode</description>
12512 <bitOffset>4</bitOffset>
12513 <bitWidth>3</bitWidth>
12514 </field>
12515 <field>
12516 <name>OC3PE</name>
12517 <description>Output compare 3 preload
12518 enable</description>
12519 <bitOffset>3</bitOffset>
12520 <bitWidth>1</bitWidth>
12521 </field>
12522 <field>
12523 <name>OC3FE</name>
12524 <description>Output compare 3 fast
12525 enable</description>
12526 <bitOffset>2</bitOffset>
12527 <bitWidth>1</bitWidth>
12528 </field>
12529 <field>
12530 <name>CC3S</name>
12531 <description>Capture/Compare 3
12532 selection</description>
12533 <bitOffset>0</bitOffset>
12534 <bitWidth>2</bitWidth>
12535 </field>
12536 </fields>
12537 </register>
12538 <register>
12539 <name>CCMR2_Input</name>
12540 <displayName>CCMR2_Input</displayName>
12541 <description>capture/compare mode register 2 (input
12542 mode)</description>
12543 <alternateRegister>CCMR2_Output</alternateRegister>
12544 <addressOffset>0x1C</addressOffset>
12545 <size>0x20</size>
12546 <access>read-write</access>
12547 <resetValue>0x00000000</resetValue>
12548 <fields>
12549 <field>
12550 <name>IC4F</name>
12551 <description>Input capture 4 filter</description>
12552 <bitOffset>12</bitOffset>
12553 <bitWidth>4</bitWidth>
12554 </field>
12555 <field>
12556 <name>IC4PSC</name>
12557 <description>Input capture 4 prescaler</description>
12558 <bitOffset>10</bitOffset>
12559 <bitWidth>2</bitWidth>
12560 </field>
12561 <field>
12562 <name>CC4S</name>
12563 <description>Capture/Compare 4
12564 selection</description>
12565 <bitOffset>8</bitOffset>
12566 <bitWidth>2</bitWidth>
12567 </field>
12568 <field>
12569 <name>IC3F</name>
12570 <description>Input capture 3 filter</description>
12571 <bitOffset>4</bitOffset>
12572 <bitWidth>4</bitWidth>
12573 </field>
12574 <field>
12575 <name>IC3PSC</name>
12576 <description>Input capture 3 prescaler</description>
12577 <bitOffset>2</bitOffset>
12578 <bitWidth>2</bitWidth>
12579 </field>
12580 <field>
12581 <name>CC3S</name>
12582 <description>Capture/compare 3
12583 selection</description>
12584 <bitOffset>0</bitOffset>
12585 <bitWidth>2</bitWidth>
12586 </field>
12587 </fields>
12588 </register>
12589 <register>
12590 <name>CCER</name>
12591 <displayName>CCER</displayName>
12592 <description>capture/compare enable
12593 register</description>
12594 <addressOffset>0x20</addressOffset>
12595 <size>0x20</size>
12596 <access>read-write</access>
12597 <resetValue>0x0000</resetValue>
12598 <fields>
12599 <field>
12600 <name>CC4P</name>
12601 <description>Capture/Compare 3 output
12602 Polarity</description>
12603 <bitOffset>13</bitOffset>
12604 <bitWidth>1</bitWidth>
12605 </field>
12606 <field>
12607 <name>CC4E</name>
12608 <description>Capture/Compare 4 output
12609 enable</description>
12610 <bitOffset>12</bitOffset>
12611 <bitWidth>1</bitWidth>
12612 </field>
12613 <field>
12614 <name>CC3NP</name>
12615 <description>Capture/Compare 3 output
12616 Polarity</description>
12617 <bitOffset>11</bitOffset>
12618 <bitWidth>1</bitWidth>
12619 </field>
12620 <field>
12621 <name>CC3NE</name>
12622 <description>Capture/Compare 3 complementary output
12623 enable</description>
12624 <bitOffset>10</bitOffset>
12625 <bitWidth>1</bitWidth>
12626 </field>
12627 <field>
12628 <name>CC3P</name>
12629 <description>Capture/Compare 3 output
12630 Polarity</description>
12631 <bitOffset>9</bitOffset>
12632 <bitWidth>1</bitWidth>
12633 </field>
12634 <field>
12635 <name>CC3E</name>
12636 <description>Capture/Compare 3 output
12637 enable</description>
12638 <bitOffset>8</bitOffset>
12639 <bitWidth>1</bitWidth>
12640 </field>
12641 <field>
12642 <name>CC2NP</name>
12643 <description>Capture/Compare 2 output
12644 Polarity</description>
12645 <bitOffset>7</bitOffset>
12646 <bitWidth>1</bitWidth>
12647 </field>
12648 <field>
12649 <name>CC2NE</name>
12650 <description>Capture/Compare 2 complementary output
12651 enable</description>
12652 <bitOffset>6</bitOffset>
12653 <bitWidth>1</bitWidth>
12654 </field>
12655 <field>
12656 <name>CC2P</name>
12657 <description>Capture/Compare 2 output
12658 Polarity</description>
12659 <bitOffset>5</bitOffset>
12660 <bitWidth>1</bitWidth>
12661 </field>
12662 <field>
12663 <name>CC2E</name>
12664 <description>Capture/Compare 2 output
12665 enable</description>
12666 <bitOffset>4</bitOffset>
12667 <bitWidth>1</bitWidth>
12668 </field>
12669 <field>
12670 <name>CC1NP</name>
12671 <description>Capture/Compare 1 output
12672 Polarity</description>
12673 <bitOffset>3</bitOffset>
12674 <bitWidth>1</bitWidth>
12675 </field>
12676 <field>
12677 <name>CC1NE</name>
12678 <description>Capture/Compare 1 complementary output
12679 enable</description>
12680 <bitOffset>2</bitOffset>
12681 <bitWidth>1</bitWidth>
12682 </field>
12683 <field>
12684 <name>CC1P</name>
12685 <description>Capture/Compare 1 output
12686 Polarity</description>
12687 <bitOffset>1</bitOffset>
12688 <bitWidth>1</bitWidth>
12689 </field>
12690 <field>
12691 <name>CC1E</name>
12692 <description>Capture/Compare 1 output
12693 enable</description>
12694 <bitOffset>0</bitOffset>
12695 <bitWidth>1</bitWidth>
12696 </field>
12697 </fields>
12698 </register>
12699 <register>
12700 <name>CNT</name>
12701 <displayName>CNT</displayName>
12702 <description>counter</description>
12703 <addressOffset>0x24</addressOffset>
12704 <size>0x20</size>
12705 <access>read-write</access>
12706 <resetValue>0x00000000</resetValue>
12707 <fields>
12708 <field>
12709 <name>CNT</name>
12710 <description>counter value</description>
12711 <bitOffset>0</bitOffset>
12712 <bitWidth>16</bitWidth>
12713 </field>
12714 </fields>
12715 </register>
12716 <register>
12717 <name>PSC</name>
12718 <displayName>PSC</displayName>
12719 <description>prescaler</description>
12720 <addressOffset>0x28</addressOffset>
12721 <size>0x20</size>
12722 <access>read-write</access>
12723 <resetValue>0x0000</resetValue>
12724 <fields>
12725 <field>
12726 <name>PSC</name>
12727 <description>Prescaler value</description>
12728 <bitOffset>0</bitOffset>
12729 <bitWidth>16</bitWidth>
12730 </field>
12731 </fields>
12732 </register>
12733 <register>
12734 <name>ARR</name>
12735 <displayName>ARR</displayName>
12736 <description>auto-reload register</description>
12737 <addressOffset>0x2C</addressOffset>
12738 <size>0x20</size>
12739 <access>read-write</access>
12740 <resetValue>0x00000000</resetValue>
12741 <fields>
12742 <field>
12743 <name>ARR</name>
12744 <description>Auto-reload value</description>
12745 <bitOffset>0</bitOffset>
12746 <bitWidth>16</bitWidth>
12747 </field>
12748 </fields>
12749 </register>
12750 <register>
12751 <name>CCR1</name>
12752 <displayName>CCR1</displayName>
12753 <description>capture/compare register 1</description>
12754 <addressOffset>0x34</addressOffset>
12755 <size>0x20</size>
12756 <access>read-write</access>
12757 <resetValue>0x00000000</resetValue>
12758 <fields>
12759 <field>
12760 <name>CCR1</name>
12761 <description>Capture/Compare 1 value</description>
12762 <bitOffset>0</bitOffset>
12763 <bitWidth>16</bitWidth>
12764 </field>
12765 </fields>
12766 </register>
12767 <register>
12768 <name>CCR2</name>
12769 <displayName>CCR2</displayName>
12770 <description>capture/compare register 2</description>
12771 <addressOffset>0x38</addressOffset>
12772 <size>0x20</size>
12773 <access>read-write</access>
12774 <resetValue>0x00000000</resetValue>
12775 <fields>
12776 <field>
12777 <name>CCR2</name>
12778 <description>Capture/Compare 2 value</description>
12779 <bitOffset>0</bitOffset>
12780 <bitWidth>16</bitWidth>
12781 </field>
12782 </fields>
12783 </register>
12784 <register>
12785 <name>CCR3</name>
12786 <displayName>CCR3</displayName>
12787 <description>capture/compare register 3</description>
12788 <addressOffset>0x3C</addressOffset>
12789 <size>0x20</size>
12790 <access>read-write</access>
12791 <resetValue>0x00000000</resetValue>
12792 <fields>
12793 <field>
12794 <name>CCR3</name>
12795 <description>Capture/Compare value</description>
12796 <bitOffset>0</bitOffset>
12797 <bitWidth>16</bitWidth>
12798 </field>
12799 </fields>
12800 </register>
12801 <register>
12802 <name>CCR4</name>
12803 <displayName>CCR4</displayName>
12804 <description>capture/compare register 4</description>
12805 <addressOffset>0x40</addressOffset>
12806 <size>0x20</size>
12807 <access>read-write</access>
12808 <resetValue>0x00000000</resetValue>
12809 <fields>
12810 <field>
12811 <name>CCR4</name>
12812 <description>Capture/Compare value</description>
12813 <bitOffset>0</bitOffset>
12814 <bitWidth>16</bitWidth>
12815 </field>
12816 </fields>
12817 </register>
12818 <register>
12819 <name>DCR</name>
12820 <displayName>DCR</displayName>
12821 <description>DMA control register</description>
12822 <addressOffset>0x48</addressOffset>
12823 <size>0x20</size>
12824 <access>read-write</access>
12825 <resetValue>0x0000</resetValue>
12826 <fields>
12827 <field>
12828 <name>DBL</name>
12829 <description>DMA burst length</description>
12830 <bitOffset>8</bitOffset>
12831 <bitWidth>5</bitWidth>
12832 </field>
12833 <field>
12834 <name>DBA</name>
12835 <description>DMA base address</description>
12836 <bitOffset>0</bitOffset>
12837 <bitWidth>5</bitWidth>
12838 </field>
12839 </fields>
12840 </register>
12841 <register>
12842 <name>DMAR</name>
12843 <displayName>DMAR</displayName>
12844 <description>DMA address for full transfer</description>
12845 <addressOffset>0x4C</addressOffset>
12846 <size>0x20</size>
12847 <access>read-write</access>
12848 <resetValue>0x0000</resetValue>
12849 <fields>
12850 <field>
12851 <name>DMAB</name>
12852 <description>DMA register for burst
12853 accesses</description>
12854 <bitOffset>0</bitOffset>
12855 <bitWidth>16</bitWidth>
12856 </field>
12857 </fields>
12858 </register>
12859 <register>
12860 <name>RCR</name>
12861 <displayName>RCR</displayName>
12862 <description>repetition counter register</description>
12863 <addressOffset>0x30</addressOffset>
12864 <size>0x20</size>
12865 <access>read-write</access>
12866 <resetValue>0x0000</resetValue>
12867 <fields>
12868 <field>
12869 <name>REP</name>
12870 <description>Repetition counter value</description>
12871 <bitOffset>0</bitOffset>
12872 <bitWidth>8</bitWidth>
12873 </field>
12874 </fields>
12875 </register>
12876 <register>
12877 <name>BDTR</name>
12878 <displayName>BDTR</displayName>
12879 <description>break and dead-time register</description>
12880 <addressOffset>0x44</addressOffset>
12881 <size>0x20</size>
12882 <access>read-write</access>
12883 <resetValue>0x0000</resetValue>
12884 <fields>
12885 <field>
12886 <name>MOE</name>
12887 <description>Main output enable</description>
12888 <bitOffset>15</bitOffset>
12889 <bitWidth>1</bitWidth>
12890 </field>
12891 <field>
12892 <name>AOE</name>
12893 <description>Automatic output enable</description>
12894 <bitOffset>14</bitOffset>
12895 <bitWidth>1</bitWidth>
12896 </field>
12897 <field>
12898 <name>BKP</name>
12899 <description>Break polarity</description>
12900 <bitOffset>13</bitOffset>
12901 <bitWidth>1</bitWidth>
12902 </field>
12903 <field>
12904 <name>BKE</name>
12905 <description>Break enable</description>
12906 <bitOffset>12</bitOffset>
12907 <bitWidth>1</bitWidth>
12908 </field>
12909 <field>
12910 <name>OSSR</name>
12911 <description>Off-state selection for Run
12912 mode</description>
12913 <bitOffset>11</bitOffset>
12914 <bitWidth>1</bitWidth>
12915 </field>
12916 <field>
12917 <name>OSSI</name>
12918 <description>Off-state selection for Idle
12919 mode</description>
12920 <bitOffset>10</bitOffset>
12921 <bitWidth>1</bitWidth>
12922 </field>
12923 <field>
12924 <name>LOCK</name>
12925 <description>Lock configuration</description>
12926 <bitOffset>8</bitOffset>
12927 <bitWidth>2</bitWidth>
12928 </field>
12929 <field>
12930 <name>DTG</name>
12931 <description>Dead-time generator setup</description>
12932 <bitOffset>0</bitOffset>
12933 <bitWidth>8</bitWidth>
12934 </field>
12935 </fields>
12936 </register>
12937 </registers>
12938 </peripheral>
12939 <peripheral derivedFrom="TIM1">
12940 <name>TIM8</name>
12941 <baseAddress>0x40010400</baseAddress>
12942 </peripheral>
12943 <peripheral>
12944 <name>TIM10</name>
12945 <description>General-purpose-timers</description>
12946 <groupName>TIM</groupName>
12947 <baseAddress>0x40014400</baseAddress>
12948 <addressBlock>
12949 <offset>0x0</offset>
12950 <size>0x400</size>
12951 <usage>registers</usage>
12952 </addressBlock>
12953 <interrupt>
12954 <name>SPI1</name>
12955 <description>SPI1 global interrupt</description>
12956 <value>35</value>
12957 </interrupt>
12958 <registers>
12959 <register>
12960 <name>CR1</name>
12961 <displayName>CR1</displayName>
12962 <description>control register 1</description>
12963 <addressOffset>0x0</addressOffset>
12964 <size>0x20</size>
12965 <access>read-write</access>
12966 <resetValue>0x0000</resetValue>
12967 <fields>
12968 <field>
12969 <name>CKD</name>
12970 <description>Clock division</description>
12971 <bitOffset>8</bitOffset>
12972 <bitWidth>2</bitWidth>
12973 </field>
12974 <field>
12975 <name>ARPE</name>
12976 <description>Auto-reload preload enable</description>
12977 <bitOffset>7</bitOffset>
12978 <bitWidth>1</bitWidth>
12979 </field>
12980 <field>
12981 <name>URS</name>
12982 <description>Update request source</description>
12983 <bitOffset>2</bitOffset>
12984 <bitWidth>1</bitWidth>
12985 </field>
12986 <field>
12987 <name>UDIS</name>
12988 <description>Update disable</description>
12989 <bitOffset>1</bitOffset>
12990 <bitWidth>1</bitWidth>
12991 </field>
12992 <field>
12993 <name>CEN</name>
12994 <description>Counter enable</description>
12995 <bitOffset>0</bitOffset>
12996 <bitWidth>1</bitWidth>
12997 </field>
12998 </fields>
12999 </register>
13000 <register>
13001 <name>DIER</name>
13002 <displayName>DIER</displayName>
13003 <description>DMA/Interrupt enable register</description>
13004 <addressOffset>0xC</addressOffset>
13005 <size>0x20</size>
13006 <access>read-write</access>
13007 <resetValue>0x0000</resetValue>
13008 <fields>
13009 <field>
13010 <name>CC1IE</name>
13011 <description>Capture/Compare 1 interrupt
13012 enable</description>
13013 <bitOffset>1</bitOffset>
13014 <bitWidth>1</bitWidth>
13015 </field>
13016 <field>
13017 <name>UIE</name>
13018 <description>Update interrupt enable</description>
13019 <bitOffset>0</bitOffset>
13020 <bitWidth>1</bitWidth>
13021 </field>
13022 </fields>
13023 </register>
13024 <register>
13025 <name>SR</name>
13026 <displayName>SR</displayName>
13027 <description>status register</description>
13028 <addressOffset>0x10</addressOffset>
13029 <size>0x20</size>
13030 <access>read-write</access>
13031 <resetValue>0x0000</resetValue>
13032 <fields>
13033 <field>
13034 <name>CC1OF</name>
13035 <description>Capture/Compare 1 overcapture
13036 flag</description>
13037 <bitOffset>9</bitOffset>
13038 <bitWidth>1</bitWidth>
13039 </field>
13040 <field>
13041 <name>CC1IF</name>
13042 <description>Capture/compare 1 interrupt
13043 flag</description>
13044 <bitOffset>1</bitOffset>
13045 <bitWidth>1</bitWidth>
13046 </field>
13047 <field>
13048 <name>UIF</name>
13049 <description>Update interrupt flag</description>
13050 <bitOffset>0</bitOffset>
13051 <bitWidth>1</bitWidth>
13052 </field>
13053 </fields>
13054 </register>
13055 <register>
13056 <name>EGR</name>
13057 <displayName>EGR</displayName>
13058 <description>event generation register</description>
13059 <addressOffset>0x14</addressOffset>
13060 <size>0x20</size>
13061 <access>write-only</access>
13062 <resetValue>0x0000</resetValue>
13063 <fields>
13064 <field>
13065 <name>CC1G</name>
13066 <description>Capture/compare 1
13067 generation</description>
13068 <bitOffset>1</bitOffset>
13069 <bitWidth>1</bitWidth>
13070 </field>
13071 <field>
13072 <name>UG</name>
13073 <description>Update generation</description>
13074 <bitOffset>0</bitOffset>
13075 <bitWidth>1</bitWidth>
13076 </field>
13077 </fields>
13078 </register>
13079 <register>
13080 <name>CCMR1_Output</name>
13081 <displayName>CCMR1_Output</displayName>
13082 <description>capture/compare mode register 1 (output
13083 mode)</description>
13084 <addressOffset>0x18</addressOffset>
13085 <size>0x20</size>
13086 <access>read-write</access>
13087 <resetValue>0x00000000</resetValue>
13088 <fields>
13089 <field>
13090 <name>OC1M</name>
13091 <description>Output Compare 1 mode</description>
13092 <bitOffset>4</bitOffset>
13093 <bitWidth>3</bitWidth>
13094 </field>
13095 <field>
13096 <name>OC1PE</name>
13097 <description>Output Compare 1 preload
13098 enable</description>
13099 <bitOffset>3</bitOffset>
13100 <bitWidth>1</bitWidth>
13101 </field>
13102 <field>
13103 <name>OC1FE</name>
13104 <description>Output Compare 1 fast
13105 enable</description>
13106 <bitOffset>2</bitOffset>
13107 <bitWidth>1</bitWidth>
13108 </field>
13109 <field>
13110 <name>CC1S</name>
13111 <description>Capture/Compare 1
13112 selection</description>
13113 <bitOffset>0</bitOffset>
13114 <bitWidth>2</bitWidth>
13115 </field>
13116 </fields>
13117 </register>
13118 <register>
13119 <name>CCMR1_Input</name>
13120 <displayName>CCMR1_Input</displayName>
13121 <description>capture/compare mode register 1 (input
13122 mode)</description>
13123 <alternateRegister>CCMR1_Output</alternateRegister>
13124 <addressOffset>0x18</addressOffset>
13125 <size>0x20</size>
13126 <access>read-write</access>
13127 <resetValue>0x00000000</resetValue>
13128 <fields>
13129 <field>
13130 <name>IC1F</name>
13131 <description>Input capture 1 filter</description>
13132 <bitOffset>4</bitOffset>
13133 <bitWidth>4</bitWidth>
13134 </field>
13135 <field>
13136 <name>ICPCS</name>
13137 <description>Input capture 1 prescaler</description>
13138 <bitOffset>2</bitOffset>
13139 <bitWidth>2</bitWidth>
13140 </field>
13141 <field>
13142 <name>CC1S</name>
13143 <description>Capture/Compare 1
13144 selection</description>
13145 <bitOffset>0</bitOffset>
13146 <bitWidth>2</bitWidth>
13147 </field>
13148 </fields>
13149 </register>
13150 <register>
13151 <name>CCER</name>
13152 <displayName>CCER</displayName>
13153 <description>capture/compare enable
13154 register</description>
13155 <addressOffset>0x20</addressOffset>
13156 <size>0x20</size>
13157 <access>read-write</access>
13158 <resetValue>0x0000</resetValue>
13159 <fields>
13160 <field>
13161 <name>CC1NP</name>
13162 <description>Capture/Compare 1 output
13163 Polarity</description>
13164 <bitOffset>3</bitOffset>
13165 <bitWidth>1</bitWidth>
13166 </field>
13167 <field>
13168 <name>CC1P</name>
13169 <description>Capture/Compare 1 output
13170 Polarity</description>
13171 <bitOffset>1</bitOffset>
13172 <bitWidth>1</bitWidth>
13173 </field>
13174 <field>
13175 <name>CC1E</name>
13176 <description>Capture/Compare 1 output
13177 enable</description>
13178 <bitOffset>0</bitOffset>
13179 <bitWidth>1</bitWidth>
13180 </field>
13181 </fields>
13182 </register>
13183 <register>
13184 <name>CNT</name>
13185 <displayName>CNT</displayName>
13186 <description>counter</description>
13187 <addressOffset>0x24</addressOffset>
13188 <size>0x20</size>
13189 <access>read-write</access>
13190 <resetValue>0x00000000</resetValue>
13191 <fields>
13192 <field>
13193 <name>CNT</name>
13194 <description>counter value</description>
13195 <bitOffset>0</bitOffset>
13196 <bitWidth>16</bitWidth>
13197 </field>
13198 </fields>
13199 </register>
13200 <register>
13201 <name>PSC</name>
13202 <displayName>PSC</displayName>
13203 <description>prescaler</description>
13204 <addressOffset>0x28</addressOffset>
13205 <size>0x20</size>
13206 <access>read-write</access>
13207 <resetValue>0x0000</resetValue>
13208 <fields>
13209 <field>
13210 <name>PSC</name>
13211 <description>Prescaler value</description>
13212 <bitOffset>0</bitOffset>
13213 <bitWidth>16</bitWidth>
13214 </field>
13215 </fields>
13216 </register>
13217 <register>
13218 <name>ARR</name>
13219 <displayName>ARR</displayName>
13220 <description>auto-reload register</description>
13221 <addressOffset>0x2C</addressOffset>
13222 <size>0x20</size>
13223 <access>read-write</access>
13224 <resetValue>0x00000000</resetValue>
13225 <fields>
13226 <field>
13227 <name>ARR</name>
13228 <description>Auto-reload value</description>
13229 <bitOffset>0</bitOffset>
13230 <bitWidth>16</bitWidth>
13231 </field>
13232 </fields>
13233 </register>
13234 <register>
13235 <name>CCR1</name>
13236 <displayName>CCR1</displayName>
13237 <description>capture/compare register 1</description>
13238 <addressOffset>0x34</addressOffset>
13239 <size>0x20</size>
13240 <access>read-write</access>
13241 <resetValue>0x00000000</resetValue>
13242 <fields>
13243 <field>
13244 <name>CCR1</name>
13245 <description>Capture/Compare 1 value</description>
13246 <bitOffset>0</bitOffset>
13247 <bitWidth>16</bitWidth>
13248 </field>
13249 </fields>
13250 </register>
13251 </registers>
13252 </peripheral>
13253 <peripheral>
13254 <name>TIM11</name>
13255 <description>General-purpose-timers</description>
13256 <groupName>TIM</groupName>
13257 <baseAddress>0x40014800</baseAddress>
13258 <addressBlock>
13259 <offset>0x0</offset>
13260 <size>0x400</size>
13261 <usage>registers</usage>
13262 </addressBlock>
13263 <interrupt>
13264 <name>SPI2</name>
13265 <description>SPI2 global interrupt</description>
13266 <value>36</value>
13267 </interrupt>
13268 <registers>
13269 <register>
13270 <name>CR1</name>
13271 <displayName>CR1</displayName>
13272 <description>control register 1</description>
13273 <addressOffset>0x0</addressOffset>
13274 <size>0x20</size>
13275 <access>read-write</access>
13276 <resetValue>0x0000</resetValue>
13277 <fields>
13278 <field>
13279 <name>CKD</name>
13280 <description>Clock division</description>
13281 <bitOffset>8</bitOffset>
13282 <bitWidth>2</bitWidth>
13283 </field>
13284 <field>
13285 <name>ARPE</name>
13286 <description>Auto-reload preload enable</description>
13287 <bitOffset>7</bitOffset>
13288 <bitWidth>1</bitWidth>
13289 </field>
13290 <field>
13291 <name>URS</name>
13292 <description>Update request source</description>
13293 <bitOffset>2</bitOffset>
13294 <bitWidth>1</bitWidth>
13295 </field>
13296 <field>
13297 <name>UDIS</name>
13298 <description>Update disable</description>
13299 <bitOffset>1</bitOffset>
13300 <bitWidth>1</bitWidth>
13301 </field>
13302 <field>
13303 <name>CEN</name>
13304 <description>Counter enable</description>
13305 <bitOffset>0</bitOffset>
13306 <bitWidth>1</bitWidth>
13307 </field>
13308 </fields>
13309 </register>
13310 <register>
13311 <name>DIER</name>
13312 <displayName>DIER</displayName>
13313 <description>DMA/Interrupt enable register</description>
13314 <addressOffset>0xC</addressOffset>
13315 <size>0x20</size>
13316 <access>read-write</access>
13317 <resetValue>0x0000</resetValue>
13318 <fields>
13319 <field>
13320 <name>CC1IE</name>
13321 <description>Capture/Compare 1 interrupt
13322 enable</description>
13323 <bitOffset>1</bitOffset>
13324 <bitWidth>1</bitWidth>
13325 </field>
13326 <field>
13327 <name>UIE</name>
13328 <description>Update interrupt enable</description>
13329 <bitOffset>0</bitOffset>
13330 <bitWidth>1</bitWidth>
13331 </field>
13332 </fields>
13333 </register>
13334 <register>
13335 <name>SR</name>
13336 <displayName>SR</displayName>
13337 <description>status register</description>
13338 <addressOffset>0x10</addressOffset>
13339 <size>0x20</size>
13340 <access>read-write</access>
13341 <resetValue>0x0000</resetValue>
13342 <fields>
13343 <field>
13344 <name>CC1OF</name>
13345 <description>Capture/Compare 1 overcapture
13346 flag</description>
13347 <bitOffset>9</bitOffset>
13348 <bitWidth>1</bitWidth>
13349 </field>
13350 <field>
13351 <name>CC1IF</name>
13352 <description>Capture/compare 1 interrupt
13353 flag</description>
13354 <bitOffset>1</bitOffset>
13355 <bitWidth>1</bitWidth>
13356 </field>
13357 <field>
13358 <name>UIF</name>
13359 <description>Update interrupt flag</description>
13360 <bitOffset>0</bitOffset>
13361 <bitWidth>1</bitWidth>
13362 </field>
13363 </fields>
13364 </register>
13365 <register>
13366 <name>EGR</name>
13367 <displayName>EGR</displayName>
13368 <description>event generation register</description>
13369 <addressOffset>0x14</addressOffset>
13370 <size>0x20</size>
13371 <access>write-only</access>
13372 <resetValue>0x0000</resetValue>
13373 <fields>
13374 <field>
13375 <name>CC1G</name>
13376 <description>Capture/compare 1
13377 generation</description>
13378 <bitOffset>1</bitOffset>
13379 <bitWidth>1</bitWidth>
13380 </field>
13381 <field>
13382 <name>UG</name>
13383 <description>Update generation</description>
13384 <bitOffset>0</bitOffset>
13385 <bitWidth>1</bitWidth>
13386 </field>
13387 </fields>
13388 </register>
13389 <register>
13390 <name>CCMR1_Output</name>
13391 <displayName>CCMR1_Output</displayName>
13392 <description>capture/compare mode register 1 (output
13393 mode)</description>
13394 <addressOffset>0x18</addressOffset>
13395 <size>0x20</size>
13396 <access>read-write</access>
13397 <resetValue>0x00000000</resetValue>
13398 <fields>
13399 <field>
13400 <name>OC1M</name>
13401 <description>Output Compare 1 mode</description>
13402 <bitOffset>4</bitOffset>
13403 <bitWidth>3</bitWidth>
13404 </field>
13405 <field>
13406 <name>OC1PE</name>
13407 <description>Output Compare 1 preload
13408 enable</description>
13409 <bitOffset>3</bitOffset>
13410 <bitWidth>1</bitWidth>
13411 </field>
13412 <field>
13413 <name>OC1FE</name>
13414 <description>Output Compare 1 fast
13415 enable</description>
13416 <bitOffset>2</bitOffset>
13417 <bitWidth>1</bitWidth>
13418 </field>
13419 <field>
13420 <name>CC1S</name>
13421 <description>Capture/Compare 1
13422 selection</description>
13423 <bitOffset>0</bitOffset>
13424 <bitWidth>2</bitWidth>
13425 </field>
13426 </fields>
13427 </register>
13428 <register>
13429 <name>CCMR1_Input</name>
13430 <displayName>CCMR1_Input</displayName>
13431 <description>capture/compare mode register 1 (input
13432 mode)</description>
13433 <alternateRegister>CCMR1_Output</alternateRegister>
13434 <addressOffset>0x18</addressOffset>
13435 <size>0x20</size>
13436 <access>read-write</access>
13437 <resetValue>0x00000000</resetValue>
13438 <fields>
13439 <field>
13440 <name>IC1F</name>
13441 <description>Input capture 1 filter</description>
13442 <bitOffset>4</bitOffset>
13443 <bitWidth>4</bitWidth>
13444 </field>
13445 <field>
13446 <name>ICPCS</name>
13447 <description>Input capture 1 prescaler</description>
13448 <bitOffset>2</bitOffset>
13449 <bitWidth>2</bitWidth>
13450 </field>
13451 <field>
13452 <name>CC1S</name>
13453 <description>Capture/Compare 1
13454 selection</description>
13455 <bitOffset>0</bitOffset>
13456 <bitWidth>2</bitWidth>
13457 </field>
13458 </fields>
13459 </register>
13460 <register>
13461 <name>CCER</name>
13462 <displayName>CCER</displayName>
13463 <description>capture/compare enable
13464 register</description>
13465 <addressOffset>0x20</addressOffset>
13466 <size>0x20</size>
13467 <access>read-write</access>
13468 <resetValue>0x0000</resetValue>
13469 <fields>
13470 <field>
13471 <name>CC1NP</name>
13472 <description>Capture/Compare 1 output
13473 Polarity</description>
13474 <bitOffset>3</bitOffset>
13475 <bitWidth>1</bitWidth>
13476 </field>
13477 <field>
13478 <name>CC1P</name>
13479 <description>Capture/Compare 1 output
13480 Polarity</description>
13481 <bitOffset>1</bitOffset>
13482 <bitWidth>1</bitWidth>
13483 </field>
13484 <field>
13485 <name>CC1E</name>
13486 <description>Capture/Compare 1 output
13487 enable</description>
13488 <bitOffset>0</bitOffset>
13489 <bitWidth>1</bitWidth>
13490 </field>
13491 </fields>
13492 </register>
13493 <register>
13494 <name>CNT</name>
13495 <displayName>CNT</displayName>
13496 <description>counter</description>
13497 <addressOffset>0x24</addressOffset>
13498 <size>0x20</size>
13499 <access>read-write</access>
13500 <resetValue>0x00000000</resetValue>
13501 <fields>
13502 <field>
13503 <name>CNT</name>
13504 <description>counter value</description>
13505 <bitOffset>0</bitOffset>
13506 <bitWidth>16</bitWidth>
13507 </field>
13508 </fields>
13509 </register>
13510 <register>
13511 <name>PSC</name>
13512 <displayName>PSC</displayName>
13513 <description>prescaler</description>
13514 <addressOffset>0x28</addressOffset>
13515 <size>0x20</size>
13516 <access>read-write</access>
13517 <resetValue>0x0000</resetValue>
13518 <fields>
13519 <field>
13520 <name>PSC</name>
13521 <description>Prescaler value</description>
13522 <bitOffset>0</bitOffset>
13523 <bitWidth>16</bitWidth>
13524 </field>
13525 </fields>
13526 </register>
13527 <register>
13528 <name>ARR</name>
13529 <displayName>ARR</displayName>
13530 <description>auto-reload register</description>
13531 <addressOffset>0x2C</addressOffset>
13532 <size>0x20</size>
13533 <access>read-write</access>
13534 <resetValue>0x00000000</resetValue>
13535 <fields>
13536 <field>
13537 <name>ARR</name>
13538 <description>Auto-reload value</description>
13539 <bitOffset>0</bitOffset>
13540 <bitWidth>16</bitWidth>
13541 </field>
13542 </fields>
13543 </register>
13544 <register>
13545 <name>CCR1</name>
13546 <displayName>CCR1</displayName>
13547 <description>capture/compare register 1</description>
13548 <addressOffset>0x34</addressOffset>
13549 <size>0x20</size>
13550 <access>read-write</access>
13551 <resetValue>0x00000000</resetValue>
13552 <fields>
13553 <field>
13554 <name>CCR1</name>
13555 <description>Capture/Compare 1 value</description>
13556 <bitOffset>0</bitOffset>
13557 <bitWidth>16</bitWidth>
13558 </field>
13559 </fields>
13560 </register>
13561 <register>
13562 <name>OR</name>
13563 <displayName>OR</displayName>
13564 <description>option register</description>
13565 <addressOffset>0x50</addressOffset>
13566 <size>0x20</size>
13567 <access>read-write</access>
13568 <resetValue>0x00000000</resetValue>
13569 <fields>
13570 <field>
13571 <name>RMP</name>
13572 <description>Input 1 remapping
13573 capability</description>
13574 <bitOffset>0</bitOffset>
13575 <bitWidth>2</bitWidth>
13576 </field>
13577 </fields>
13578 </register>
13579 </registers>
13580 </peripheral>
13581 <peripheral>
13582 <name>TIM2</name>
13583 <description>General purpose timers</description>
13584 <groupName>TIM</groupName>
13585 <baseAddress>0x40000000</baseAddress>
13586 <addressBlock>
13587 <offset>0x0</offset>
13588 <size>0x400</size>
13589 <usage>registers</usage>
13590 </addressBlock>
13591 <interrupt>
13592 <name>SPI3</name>
13593 <description>SPI3 global interrupt</description>
13594 <value>51</value>
13595 </interrupt>
13596 <registers>
13597 <register>
13598 <name>CR1</name>
13599 <displayName>CR1</displayName>
13600 <description>control register 1</description>
13601 <addressOffset>0x0</addressOffset>
13602 <size>0x20</size>
13603 <access>read-write</access>
13604 <resetValue>0x0000</resetValue>
13605 <fields>
13606 <field>
13607 <name>CKD</name>
13608 <description>Clock division</description>
13609 <bitOffset>8</bitOffset>
13610 <bitWidth>2</bitWidth>
13611 </field>
13612 <field>
13613 <name>ARPE</name>
13614 <description>Auto-reload preload enable</description>
13615 <bitOffset>7</bitOffset>
13616 <bitWidth>1</bitWidth>
13617 </field>
13618 <field>
13619 <name>CMS</name>
13620 <description>Center-aligned mode
13621 selection</description>
13622 <bitOffset>5</bitOffset>
13623 <bitWidth>2</bitWidth>
13624 </field>
13625 <field>
13626 <name>DIR</name>
13627 <description>Direction</description>
13628 <bitOffset>4</bitOffset>
13629 <bitWidth>1</bitWidth>
13630 </field>
13631 <field>
13632 <name>OPM</name>
13633 <description>One-pulse mode</description>
13634 <bitOffset>3</bitOffset>
13635 <bitWidth>1</bitWidth>
13636 </field>
13637 <field>
13638 <name>URS</name>
13639 <description>Update request source</description>
13640 <bitOffset>2</bitOffset>
13641 <bitWidth>1</bitWidth>
13642 </field>
13643 <field>
13644 <name>UDIS</name>
13645 <description>Update disable</description>
13646 <bitOffset>1</bitOffset>
13647 <bitWidth>1</bitWidth>
13648 </field>
13649 <field>
13650 <name>CEN</name>
13651 <description>Counter enable</description>
13652 <bitOffset>0</bitOffset>
13653 <bitWidth>1</bitWidth>
13654 </field>
13655 </fields>
13656 </register>
13657 <register>
13658 <name>CR2</name>
13659 <displayName>CR2</displayName>
13660 <description>control register 2</description>
13661 <addressOffset>0x4</addressOffset>
13662 <size>0x20</size>
13663 <access>read-write</access>
13664 <resetValue>0x0000</resetValue>
13665 <fields>
13666 <field>
13667 <name>TI1S</name>
13668 <description>TI1 selection</description>
13669 <bitOffset>7</bitOffset>
13670 <bitWidth>1</bitWidth>
13671 </field>
13672 <field>
13673 <name>MMS</name>
13674 <description>Master mode selection</description>
13675 <bitOffset>4</bitOffset>
13676 <bitWidth>3</bitWidth>
13677 </field>
13678 <field>
13679 <name>CCDS</name>
13680 <description>Capture/compare DMA
13681 selection</description>
13682 <bitOffset>3</bitOffset>
13683 <bitWidth>1</bitWidth>
13684 </field>
13685 </fields>
13686 </register>
13687 <register>
13688 <name>SMCR</name>
13689 <displayName>SMCR</displayName>
13690 <description>slave mode control register</description>
13691 <addressOffset>0x8</addressOffset>
13692 <size>0x20</size>
13693 <access>read-write</access>
13694 <resetValue>0x0000</resetValue>
13695 <fields>
13696 <field>
13697 <name>ETP</name>
13698 <description>External trigger polarity</description>
13699 <bitOffset>15</bitOffset>
13700 <bitWidth>1</bitWidth>
13701 </field>
13702 <field>
13703 <name>ECE</name>
13704 <description>External clock enable</description>
13705 <bitOffset>14</bitOffset>
13706 <bitWidth>1</bitWidth>
13707 </field>
13708 <field>
13709 <name>ETPS</name>
13710 <description>External trigger prescaler</description>
13711 <bitOffset>12</bitOffset>
13712 <bitWidth>2</bitWidth>
13713 </field>
13714 <field>
13715 <name>ETF</name>
13716 <description>External trigger filter</description>
13717 <bitOffset>8</bitOffset>
13718 <bitWidth>4</bitWidth>
13719 </field>
13720 <field>
13721 <name>MSM</name>
13722 <description>Master/Slave mode</description>
13723 <bitOffset>7</bitOffset>
13724 <bitWidth>1</bitWidth>
13725 </field>
13726 <field>
13727 <name>TS</name>
13728 <description>Trigger selection</description>
13729 <bitOffset>4</bitOffset>
13730 <bitWidth>3</bitWidth>
13731 </field>
13732 <field>
13733 <name>SMS</name>
13734 <description>Slave mode selection</description>
13735 <bitOffset>0</bitOffset>
13736 <bitWidth>3</bitWidth>
13737 </field>
13738 </fields>
13739 </register>
13740 <register>
13741 <name>DIER</name>
13742 <displayName>DIER</displayName>
13743 <description>DMA/Interrupt enable register</description>
13744 <addressOffset>0xC</addressOffset>
13745 <size>0x20</size>
13746 <access>read-write</access>
13747 <resetValue>0x0000</resetValue>
13748 <fields>
13749 <field>
13750 <name>TDE</name>
13751 <description>Trigger DMA request enable</description>
13752 <bitOffset>14</bitOffset>
13753 <bitWidth>1</bitWidth>
13754 </field>
13755 <field>
13756 <name>CC4DE</name>
13757 <description>Capture/Compare 4 DMA request
13758 enable</description>
13759 <bitOffset>12</bitOffset>
13760 <bitWidth>1</bitWidth>
13761 </field>
13762 <field>
13763 <name>CC3DE</name>
13764 <description>Capture/Compare 3 DMA request
13765 enable</description>
13766 <bitOffset>11</bitOffset>
13767 <bitWidth>1</bitWidth>
13768 </field>
13769 <field>
13770 <name>CC2DE</name>
13771 <description>Capture/Compare 2 DMA request
13772 enable</description>
13773 <bitOffset>10</bitOffset>
13774 <bitWidth>1</bitWidth>
13775 </field>
13776 <field>
13777 <name>CC1DE</name>
13778 <description>Capture/Compare 1 DMA request
13779 enable</description>
13780 <bitOffset>9</bitOffset>
13781 <bitWidth>1</bitWidth>
13782 </field>
13783 <field>
13784 <name>UDE</name>
13785 <description>Update DMA request enable</description>
13786 <bitOffset>8</bitOffset>
13787 <bitWidth>1</bitWidth>
13788 </field>
13789 <field>
13790 <name>TIE</name>
13791 <description>Trigger interrupt enable</description>
13792 <bitOffset>6</bitOffset>
13793 <bitWidth>1</bitWidth>
13794 </field>
13795 <field>
13796 <name>CC4IE</name>
13797 <description>Capture/Compare 4 interrupt
13798 enable</description>
13799 <bitOffset>4</bitOffset>
13800 <bitWidth>1</bitWidth>
13801 </field>
13802 <field>
13803 <name>CC3IE</name>
13804 <description>Capture/Compare 3 interrupt
13805 enable</description>
13806 <bitOffset>3</bitOffset>
13807 <bitWidth>1</bitWidth>
13808 </field>
13809 <field>
13810 <name>CC2IE</name>
13811 <description>Capture/Compare 2 interrupt
13812 enable</description>
13813 <bitOffset>2</bitOffset>
13814 <bitWidth>1</bitWidth>
13815 </field>
13816 <field>
13817 <name>CC1IE</name>
13818 <description>Capture/Compare 1 interrupt
13819 enable</description>
13820 <bitOffset>1</bitOffset>
13821 <bitWidth>1</bitWidth>
13822 </field>
13823 <field>
13824 <name>UIE</name>
13825 <description>Update interrupt enable</description>
13826 <bitOffset>0</bitOffset>
13827 <bitWidth>1</bitWidth>
13828 </field>
13829 </fields>
13830 </register>
13831 <register>
13832 <name>SR</name>
13833 <displayName>SR</displayName>
13834 <description>status register</description>
13835 <addressOffset>0x10</addressOffset>
13836 <size>0x20</size>
13837 <access>read-write</access>
13838 <resetValue>0x0000</resetValue>
13839 <fields>
13840 <field>
13841 <name>CC4OF</name>
13842 <description>Capture/Compare 4 overcapture
13843 flag</description>
13844 <bitOffset>12</bitOffset>
13845 <bitWidth>1</bitWidth>
13846 </field>
13847 <field>
13848 <name>CC3OF</name>
13849 <description>Capture/Compare 3 overcapture
13850 flag</description>
13851 <bitOffset>11</bitOffset>
13852 <bitWidth>1</bitWidth>
13853 </field>
13854 <field>
13855 <name>CC2OF</name>
13856 <description>Capture/compare 2 overcapture
13857 flag</description>
13858 <bitOffset>10</bitOffset>
13859 <bitWidth>1</bitWidth>
13860 </field>
13861 <field>
13862 <name>CC1OF</name>
13863 <description>Capture/Compare 1 overcapture
13864 flag</description>
13865 <bitOffset>9</bitOffset>
13866 <bitWidth>1</bitWidth>
13867 </field>
13868 <field>
13869 <name>TIF</name>
13870 <description>Trigger interrupt flag</description>
13871 <bitOffset>6</bitOffset>
13872 <bitWidth>1</bitWidth>
13873 </field>
13874 <field>
13875 <name>CC4IF</name>
13876 <description>Capture/Compare 4 interrupt
13877 flag</description>
13878 <bitOffset>4</bitOffset>
13879 <bitWidth>1</bitWidth>
13880 </field>
13881 <field>
13882 <name>CC3IF</name>
13883 <description>Capture/Compare 3 interrupt
13884 flag</description>
13885 <bitOffset>3</bitOffset>
13886 <bitWidth>1</bitWidth>
13887 </field>
13888 <field>
13889 <name>CC2IF</name>
13890 <description>Capture/Compare 2 interrupt
13891 flag</description>
13892 <bitOffset>2</bitOffset>
13893 <bitWidth>1</bitWidth>
13894 </field>
13895 <field>
13896 <name>CC1IF</name>
13897 <description>Capture/compare 1 interrupt
13898 flag</description>
13899 <bitOffset>1</bitOffset>
13900 <bitWidth>1</bitWidth>
13901 </field>
13902 <field>
13903 <name>UIF</name>
13904 <description>Update interrupt flag</description>
13905 <bitOffset>0</bitOffset>
13906 <bitWidth>1</bitWidth>
13907 </field>
13908 </fields>
13909 </register>
13910 <register>
13911 <name>EGR</name>
13912 <displayName>EGR</displayName>
13913 <description>event generation register</description>
13914 <addressOffset>0x14</addressOffset>
13915 <size>0x20</size>
13916 <access>write-only</access>
13917 <resetValue>0x0000</resetValue>
13918 <fields>
13919 <field>
13920 <name>TG</name>
13921 <description>Trigger generation</description>
13922 <bitOffset>6</bitOffset>
13923 <bitWidth>1</bitWidth>
13924 </field>
13925 <field>
13926 <name>CC4G</name>
13927 <description>Capture/compare 4
13928 generation</description>
13929 <bitOffset>4</bitOffset>
13930 <bitWidth>1</bitWidth>
13931 </field>
13932 <field>
13933 <name>CC3G</name>
13934 <description>Capture/compare 3
13935 generation</description>
13936 <bitOffset>3</bitOffset>
13937 <bitWidth>1</bitWidth>
13938 </field>
13939 <field>
13940 <name>CC2G</name>
13941 <description>Capture/compare 2
13942 generation</description>
13943 <bitOffset>2</bitOffset>
13944 <bitWidth>1</bitWidth>
13945 </field>
13946 <field>
13947 <name>CC1G</name>
13948 <description>Capture/compare 1
13949 generation</description>
13950 <bitOffset>1</bitOffset>
13951 <bitWidth>1</bitWidth>
13952 </field>
13953 <field>
13954 <name>UG</name>
13955 <description>Update generation</description>
13956 <bitOffset>0</bitOffset>
13957 <bitWidth>1</bitWidth>
13958 </field>
13959 </fields>
13960 </register>
13961 <register>
13962 <name>CCMR1_Output</name>
13963 <displayName>CCMR1_Output</displayName>
13964 <description>capture/compare mode register 1 (output
13965 mode)</description>
13966 <addressOffset>0x18</addressOffset>
13967 <size>0x20</size>
13968 <access>read-write</access>
13969 <resetValue>0x00000000</resetValue>
13970 <fields>
13971 <field>
13972 <name>OC2CE</name>
13973 <description>OC2CE</description>
13974 <bitOffset>15</bitOffset>
13975 <bitWidth>1</bitWidth>
13976 </field>
13977 <field>
13978 <name>OC2M</name>
13979 <description>OC2M</description>
13980 <bitOffset>12</bitOffset>
13981 <bitWidth>3</bitWidth>
13982 </field>
13983 <field>
13984 <name>OC2PE</name>
13985 <description>OC2PE</description>
13986 <bitOffset>11</bitOffset>
13987 <bitWidth>1</bitWidth>
13988 </field>
13989 <field>
13990 <name>OC2FE</name>
13991 <description>OC2FE</description>
13992 <bitOffset>10</bitOffset>
13993 <bitWidth>1</bitWidth>
13994 </field>
13995 <field>
13996 <name>CC2S</name>
13997 <description>CC2S</description>
13998 <bitOffset>8</bitOffset>
13999 <bitWidth>2</bitWidth>
14000 </field>
14001 <field>
14002 <name>OC1CE</name>
14003 <description>OC1CE</description>
14004 <bitOffset>7</bitOffset>
14005 <bitWidth>1</bitWidth>
14006 </field>
14007 <field>
14008 <name>OC1M</name>
14009 <description>OC1M</description>
14010 <bitOffset>4</bitOffset>
14011 <bitWidth>3</bitWidth>
14012 </field>
14013 <field>
14014 <name>OC1PE</name>
14015 <description>OC1PE</description>
14016 <bitOffset>3</bitOffset>
14017 <bitWidth>1</bitWidth>
14018 </field>
14019 <field>
14020 <name>OC1FE</name>
14021 <description>OC1FE</description>
14022 <bitOffset>2</bitOffset>
14023 <bitWidth>1</bitWidth>
14024 </field>
14025 <field>
14026 <name>CC1S</name>
14027 <description>CC1S</description>
14028 <bitOffset>0</bitOffset>
14029 <bitWidth>2</bitWidth>
14030 </field>
14031 </fields>
14032 </register>
14033 <register>
14034 <name>CCMR1_Input</name>
14035 <displayName>CCMR1_Input</displayName>
14036 <description>capture/compare mode register 1 (input
14037 mode)</description>
14038 <alternateRegister>CCMR1_Output</alternateRegister>
14039 <addressOffset>0x18</addressOffset>
14040 <size>0x20</size>
14041 <access>read-write</access>
14042 <resetValue>0x00000000</resetValue>
14043 <fields>
14044 <field>
14045 <name>IC2F</name>
14046 <description>Input capture 2 filter</description>
14047 <bitOffset>12</bitOffset>
14048 <bitWidth>4</bitWidth>
14049 </field>
14050 <field>
14051 <name>IC2PCS</name>
14052 <description>Input capture 2 prescaler</description>
14053 <bitOffset>10</bitOffset>
14054 <bitWidth>2</bitWidth>
14055 </field>
14056 <field>
14057 <name>CC2S</name>
14058 <description>Capture/Compare 2
14059 selection</description>
14060 <bitOffset>8</bitOffset>
14061 <bitWidth>2</bitWidth>
14062 </field>
14063 <field>
14064 <name>IC1F</name>
14065 <description>Input capture 1 filter</description>
14066 <bitOffset>4</bitOffset>
14067 <bitWidth>4</bitWidth>
14068 </field>
14069 <field>
14070 <name>ICPCS</name>
14071 <description>Input capture 1 prescaler</description>
14072 <bitOffset>2</bitOffset>
14073 <bitWidth>2</bitWidth>
14074 </field>
14075 <field>
14076 <name>CC1S</name>
14077 <description>Capture/Compare 1
14078 selection</description>
14079 <bitOffset>0</bitOffset>
14080 <bitWidth>2</bitWidth>
14081 </field>
14082 </fields>
14083 </register>
14084 <register>
14085 <name>CCMR2_Output</name>
14086 <displayName>CCMR2_Output</displayName>
14087 <description>capture/compare mode register 2 (output
14088 mode)</description>
14089 <addressOffset>0x1C</addressOffset>
14090 <size>0x20</size>
14091 <access>read-write</access>
14092 <resetValue>0x00000000</resetValue>
14093 <fields>
14094 <field>
14095 <name>O24CE</name>
14096 <description>O24CE</description>
14097 <bitOffset>15</bitOffset>
14098 <bitWidth>1</bitWidth>
14099 </field>
14100 <field>
14101 <name>OC4M</name>
14102 <description>OC4M</description>
14103 <bitOffset>12</bitOffset>
14104 <bitWidth>3</bitWidth>
14105 </field>
14106 <field>
14107 <name>OC4PE</name>
14108 <description>OC4PE</description>
14109 <bitOffset>11</bitOffset>
14110 <bitWidth>1</bitWidth>
14111 </field>
14112 <field>
14113 <name>OC4FE</name>
14114 <description>OC4FE</description>
14115 <bitOffset>10</bitOffset>
14116 <bitWidth>1</bitWidth>
14117 </field>
14118 <field>
14119 <name>CC4S</name>
14120 <description>CC4S</description>
14121 <bitOffset>8</bitOffset>
14122 <bitWidth>2</bitWidth>
14123 </field>
14124 <field>
14125 <name>OC3CE</name>
14126 <description>OC3CE</description>
14127 <bitOffset>7</bitOffset>
14128 <bitWidth>1</bitWidth>
14129 </field>
14130 <field>
14131 <name>OC3M</name>
14132 <description>OC3M</description>
14133 <bitOffset>4</bitOffset>
14134 <bitWidth>3</bitWidth>
14135 </field>
14136 <field>
14137 <name>OC3PE</name>
14138 <description>OC3PE</description>
14139 <bitOffset>3</bitOffset>
14140 <bitWidth>1</bitWidth>
14141 </field>
14142 <field>
14143 <name>OC3FE</name>
14144 <description>OC3FE</description>
14145 <bitOffset>2</bitOffset>
14146 <bitWidth>1</bitWidth>
14147 </field>
14148 <field>
14149 <name>CC3S</name>
14150 <description>CC3S</description>
14151 <bitOffset>0</bitOffset>
14152 <bitWidth>2</bitWidth>
14153 </field>
14154 </fields>
14155 </register>
14156 <register>
14157 <name>CCMR2_Input</name>
14158 <displayName>CCMR2_Input</displayName>
14159 <description>capture/compare mode register 2 (input
14160 mode)</description>
14161 <alternateRegister>CCMR2_Output</alternateRegister>
14162 <addressOffset>0x1C</addressOffset>
14163 <size>0x20</size>
14164 <access>read-write</access>
14165 <resetValue>0x00000000</resetValue>
14166 <fields>
14167 <field>
14168 <name>IC4F</name>
14169 <description>Input capture 4 filter</description>
14170 <bitOffset>12</bitOffset>
14171 <bitWidth>4</bitWidth>
14172 </field>
14173 <field>
14174 <name>IC4PSC</name>
14175 <description>Input capture 4 prescaler</description>
14176 <bitOffset>10</bitOffset>
14177 <bitWidth>2</bitWidth>
14178 </field>
14179 <field>
14180 <name>CC4S</name>
14181 <description>Capture/Compare 4
14182 selection</description>
14183 <bitOffset>8</bitOffset>
14184 <bitWidth>2</bitWidth>
14185 </field>
14186 <field>
14187 <name>IC3F</name>
14188 <description>Input capture 3 filter</description>
14189 <bitOffset>4</bitOffset>
14190 <bitWidth>4</bitWidth>
14191 </field>
14192 <field>
14193 <name>IC3PSC</name>
14194 <description>Input capture 3 prescaler</description>
14195 <bitOffset>2</bitOffset>
14196 <bitWidth>2</bitWidth>
14197 </field>
14198 <field>
14199 <name>CC3S</name>
14200 <description>Capture/compare 3
14201 selection</description>
14202 <bitOffset>0</bitOffset>
14203 <bitWidth>2</bitWidth>
14204 </field>
14205 </fields>
14206 </register>
14207 <register>
14208 <name>CCER</name>
14209 <displayName>CCER</displayName>
14210 <description>capture/compare enable
14211 register</description>
14212 <addressOffset>0x20</addressOffset>
14213 <size>0x20</size>
14214 <access>read-write</access>
14215 <resetValue>0x0000</resetValue>
14216 <fields>
14217 <field>
14218 <name>CC4NP</name>
14219 <description>Capture/Compare 4 output
14220 Polarity</description>
14221 <bitOffset>15</bitOffset>
14222 <bitWidth>1</bitWidth>
14223 </field>
14224 <field>
14225 <name>CC4P</name>
14226 <description>Capture/Compare 3 output
14227 Polarity</description>
14228 <bitOffset>13</bitOffset>
14229 <bitWidth>1</bitWidth>
14230 </field>
14231 <field>
14232 <name>CC4E</name>
14233 <description>Capture/Compare 4 output
14234 enable</description>
14235 <bitOffset>12</bitOffset>
14236 <bitWidth>1</bitWidth>
14237 </field>
14238 <field>
14239 <name>CC3NP</name>
14240 <description>Capture/Compare 3 output
14241 Polarity</description>
14242 <bitOffset>11</bitOffset>
14243 <bitWidth>1</bitWidth>
14244 </field>
14245 <field>
14246 <name>CC3P</name>
14247 <description>Capture/Compare 3 output
14248 Polarity</description>
14249 <bitOffset>9</bitOffset>
14250 <bitWidth>1</bitWidth>
14251 </field>
14252 <field>
14253 <name>CC3E</name>
14254 <description>Capture/Compare 3 output
14255 enable</description>
14256 <bitOffset>8</bitOffset>
14257 <bitWidth>1</bitWidth>
14258 </field>
14259 <field>
14260 <name>CC2NP</name>
14261 <description>Capture/Compare 2 output
14262 Polarity</description>
14263 <bitOffset>7</bitOffset>
14264 <bitWidth>1</bitWidth>
14265 </field>
14266 <field>
14267 <name>CC2P</name>
14268 <description>Capture/Compare 2 output
14269 Polarity</description>
14270 <bitOffset>5</bitOffset>
14271 <bitWidth>1</bitWidth>
14272 </field>
14273 <field>
14274 <name>CC2E</name>
14275 <description>Capture/Compare 2 output
14276 enable</description>
14277 <bitOffset>4</bitOffset>
14278 <bitWidth>1</bitWidth>
14279 </field>
14280 <field>
14281 <name>CC1NP</name>
14282 <description>Capture/Compare 1 output
14283 Polarity</description>
14284 <bitOffset>3</bitOffset>
14285 <bitWidth>1</bitWidth>
14286 </field>
14287 <field>
14288 <name>CC1P</name>
14289 <description>Capture/Compare 1 output
14290 Polarity</description>
14291 <bitOffset>1</bitOffset>
14292 <bitWidth>1</bitWidth>
14293 </field>
14294 <field>
14295 <name>CC1E</name>
14296 <description>Capture/Compare 1 output
14297 enable</description>
14298 <bitOffset>0</bitOffset>
14299 <bitWidth>1</bitWidth>
14300 </field>
14301 </fields>
14302 </register>
14303 <register>
14304 <name>CNT</name>
14305 <displayName>CNT</displayName>
14306 <description>counter</description>
14307 <addressOffset>0x24</addressOffset>
14308 <size>0x20</size>
14309 <access>read-write</access>
14310 <resetValue>0x00000000</resetValue>
14311 <fields>
14312 <field>
14313 <name>CNT_H</name>
14314 <description>High counter value</description>
14315 <bitOffset>16</bitOffset>
14316 <bitWidth>16</bitWidth>
14317 </field>
14318 <field>
14319 <name>CNT_L</name>
14320 <description>Low counter value</description>
14321 <bitOffset>0</bitOffset>
14322 <bitWidth>16</bitWidth>
14323 </field>
14324 </fields>
14325 </register>
14326 <register>
14327 <name>PSC</name>
14328 <displayName>PSC</displayName>
14329 <description>prescaler</description>
14330 <addressOffset>0x28</addressOffset>
14331 <size>0x20</size>
14332 <access>read-write</access>
14333 <resetValue>0x0000</resetValue>
14334 <fields>
14335 <field>
14336 <name>PSC</name>
14337 <description>Prescaler value</description>
14338 <bitOffset>0</bitOffset>
14339 <bitWidth>16</bitWidth>
14340 </field>
14341 </fields>
14342 </register>
14343 <register>
14344 <name>ARR</name>
14345 <displayName>ARR</displayName>
14346 <description>auto-reload register</description>
14347 <addressOffset>0x2C</addressOffset>
14348 <size>0x20</size>
14349 <access>read-write</access>
14350 <resetValue>0x00000000</resetValue>
14351 <fields>
14352 <field>
14353 <name>ARR_H</name>
14354 <description>High Auto-reload value</description>
14355 <bitOffset>16</bitOffset>
14356 <bitWidth>16</bitWidth>
14357 </field>
14358 <field>
14359 <name>ARR_L</name>
14360 <description>Low Auto-reload value</description>
14361 <bitOffset>0</bitOffset>
14362 <bitWidth>16</bitWidth>
14363 </field>
14364 </fields>
14365 </register>
14366 <register>
14367 <name>CCR1</name>
14368 <displayName>CCR1</displayName>
14369 <description>capture/compare register 1</description>
14370 <addressOffset>0x34</addressOffset>
14371 <size>0x20</size>
14372 <access>read-write</access>
14373 <resetValue>0x00000000</resetValue>
14374 <fields>
14375 <field>
14376 <name>CCR1_H</name>
14377 <description>High Capture/Compare 1
14378 value</description>
14379 <bitOffset>16</bitOffset>
14380 <bitWidth>16</bitWidth>
14381 </field>
14382 <field>
14383 <name>CCR1_L</name>
14384 <description>Low Capture/Compare 1
14385 value</description>
14386 <bitOffset>0</bitOffset>
14387 <bitWidth>16</bitWidth>
14388 </field>
14389 </fields>
14390 </register>
14391 <register>
14392 <name>CCR2</name>
14393 <displayName>CCR2</displayName>
14394 <description>capture/compare register 2</description>
14395 <addressOffset>0x38</addressOffset>
14396 <size>0x20</size>
14397 <access>read-write</access>
14398 <resetValue>0x00000000</resetValue>
14399 <fields>
14400 <field>
14401 <name>CCR2_H</name>
14402 <description>High Capture/Compare 2
14403 value</description>
14404 <bitOffset>16</bitOffset>
14405 <bitWidth>16</bitWidth>
14406 </field>
14407 <field>
14408 <name>CCR2_L</name>
14409 <description>Low Capture/Compare 2
14410 value</description>
14411 <bitOffset>0</bitOffset>
14412 <bitWidth>16</bitWidth>
14413 </field>
14414 </fields>
14415 </register>
14416 <register>
14417 <name>CCR3</name>
14418 <displayName>CCR3</displayName>
14419 <description>capture/compare register 3</description>
14420 <addressOffset>0x3C</addressOffset>
14421 <size>0x20</size>
14422 <access>read-write</access>
14423 <resetValue>0x00000000</resetValue>
14424 <fields>
14425 <field>
14426 <name>CCR3_H</name>
14427 <description>High Capture/Compare value</description>
14428 <bitOffset>16</bitOffset>
14429 <bitWidth>16</bitWidth>
14430 </field>
14431 <field>
14432 <name>CCR3_L</name>
14433 <description>Low Capture/Compare value</description>
14434 <bitOffset>0</bitOffset>
14435 <bitWidth>16</bitWidth>
14436 </field>
14437 </fields>
14438 </register>
14439 <register>
14440 <name>CCR4</name>
14441 <displayName>CCR4</displayName>
14442 <description>capture/compare register 4</description>
14443 <addressOffset>0x40</addressOffset>
14444 <size>0x20</size>
14445 <access>read-write</access>
14446 <resetValue>0x00000000</resetValue>
14447 <fields>
14448 <field>
14449 <name>CCR4_H</name>
14450 <description>High Capture/Compare value</description>
14451 <bitOffset>16</bitOffset>
14452 <bitWidth>16</bitWidth>
14453 </field>
14454 <field>
14455 <name>CCR4_L</name>
14456 <description>Low Capture/Compare value</description>
14457 <bitOffset>0</bitOffset>
14458 <bitWidth>16</bitWidth>
14459 </field>
14460 </fields>
14461 </register>
14462 <register>
14463 <name>DCR</name>
14464 <displayName>DCR</displayName>
14465 <description>DMA control register</description>
14466 <addressOffset>0x48</addressOffset>
14467 <size>0x20</size>
14468 <access>read-write</access>
14469 <resetValue>0x0000</resetValue>
14470 <fields>
14471 <field>
14472 <name>DBL</name>
14473 <description>DMA burst length</description>
14474 <bitOffset>8</bitOffset>
14475 <bitWidth>5</bitWidth>
14476 </field>
14477 <field>
14478 <name>DBA</name>
14479 <description>DMA base address</description>
14480 <bitOffset>0</bitOffset>
14481 <bitWidth>5</bitWidth>
14482 </field>
14483 </fields>
14484 </register>
14485 <register>
14486 <name>DMAR</name>
14487 <displayName>DMAR</displayName>
14488 <description>DMA address for full transfer</description>
14489 <addressOffset>0x4C</addressOffset>
14490 <size>0x20</size>
14491 <access>read-write</access>
14492 <resetValue>0x0000</resetValue>
14493 <fields>
14494 <field>
14495 <name>DMAB</name>
14496 <description>DMA register for burst
14497 accesses</description>
14498 <bitOffset>0</bitOffset>
14499 <bitWidth>16</bitWidth>
14500 </field>
14501 </fields>
14502 </register>
14503 <register>
14504 <name>OR</name>
14505 <displayName>OR</displayName>
14506 <description>TIM5 option register</description>
14507 <addressOffset>0x50</addressOffset>
14508 <size>0x20</size>
14509 <access>read-write</access>
14510 <resetValue>0x0000</resetValue>
14511 <fields>
14512 <field>
14513 <name>ITR1_RMP</name>
14514 <description>Timer Input 4 remap</description>
14515 <bitOffset>10</bitOffset>
14516 <bitWidth>2</bitWidth>
14517 </field>
14518 </fields>
14519 </register>
14520 </registers>
14521 </peripheral>
14522 <peripheral>
14523 <name>TIM3</name>
14524 <description>General purpose timers</description>
14525 <groupName>TIM</groupName>
14526 <baseAddress>0x40000400</baseAddress>
14527 <addressBlock>
14528 <offset>0x0</offset>
14529 <size>0x400</size>
14530 <usage>registers</usage>
14531 </addressBlock>
14532 <interrupt>
14533 <name>SPI4</name>
14534 <description>SPI4 global interrupt</description>
14535 <value>84</value>
14536 </interrupt>
14537 <registers>
14538 <register>
14539 <name>CR1</name>
14540 <displayName>CR1</displayName>
14541 <description>control register 1</description>
14542 <addressOffset>0x0</addressOffset>
14543 <size>0x20</size>
14544 <access>read-write</access>
14545 <resetValue>0x0000</resetValue>
14546 <fields>
14547 <field>
14548 <name>CKD</name>
14549 <description>Clock division</description>
14550 <bitOffset>8</bitOffset>
14551 <bitWidth>2</bitWidth>
14552 </field>
14553 <field>
14554 <name>ARPE</name>
14555 <description>Auto-reload preload enable</description>
14556 <bitOffset>7</bitOffset>
14557 <bitWidth>1</bitWidth>
14558 </field>
14559 <field>
14560 <name>CMS</name>
14561 <description>Center-aligned mode
14562 selection</description>
14563 <bitOffset>5</bitOffset>
14564 <bitWidth>2</bitWidth>
14565 </field>
14566 <field>
14567 <name>DIR</name>
14568 <description>Direction</description>
14569 <bitOffset>4</bitOffset>
14570 <bitWidth>1</bitWidth>
14571 </field>
14572 <field>
14573 <name>OPM</name>
14574 <description>One-pulse mode</description>
14575 <bitOffset>3</bitOffset>
14576 <bitWidth>1</bitWidth>
14577 </field>
14578 <field>
14579 <name>URS</name>
14580 <description>Update request source</description>
14581 <bitOffset>2</bitOffset>
14582 <bitWidth>1</bitWidth>
14583 </field>
14584 <field>
14585 <name>UDIS</name>
14586 <description>Update disable</description>
14587 <bitOffset>1</bitOffset>
14588 <bitWidth>1</bitWidth>
14589 </field>
14590 <field>
14591 <name>CEN</name>
14592 <description>Counter enable</description>
14593 <bitOffset>0</bitOffset>
14594 <bitWidth>1</bitWidth>
14595 </field>
14596 </fields>
14597 </register>
14598 <register>
14599 <name>CR2</name>
14600 <displayName>CR2</displayName>
14601 <description>control register 2</description>
14602 <addressOffset>0x4</addressOffset>
14603 <size>0x20</size>
14604 <access>read-write</access>
14605 <resetValue>0x0000</resetValue>
14606 <fields>
14607 <field>
14608 <name>TI1S</name>
14609 <description>TI1 selection</description>
14610 <bitOffset>7</bitOffset>
14611 <bitWidth>1</bitWidth>
14612 </field>
14613 <field>
14614 <name>MMS</name>
14615 <description>Master mode selection</description>
14616 <bitOffset>4</bitOffset>
14617 <bitWidth>3</bitWidth>
14618 </field>
14619 <field>
14620 <name>CCDS</name>
14621 <description>Capture/compare DMA
14622 selection</description>
14623 <bitOffset>3</bitOffset>
14624 <bitWidth>1</bitWidth>
14625 </field>
14626 </fields>
14627 </register>
14628 <register>
14629 <name>SMCR</name>
14630 <displayName>SMCR</displayName>
14631 <description>slave mode control register</description>
14632 <addressOffset>0x8</addressOffset>
14633 <size>0x20</size>
14634 <access>read-write</access>
14635 <resetValue>0x0000</resetValue>
14636 <fields>
14637 <field>
14638 <name>ETP</name>
14639 <description>External trigger polarity</description>
14640 <bitOffset>15</bitOffset>
14641 <bitWidth>1</bitWidth>
14642 </field>
14643 <field>
14644 <name>ECE</name>
14645 <description>External clock enable</description>
14646 <bitOffset>14</bitOffset>
14647 <bitWidth>1</bitWidth>
14648 </field>
14649 <field>
14650 <name>ETPS</name>
14651 <description>External trigger prescaler</description>
14652 <bitOffset>12</bitOffset>
14653 <bitWidth>2</bitWidth>
14654 </field>
14655 <field>
14656 <name>ETF</name>
14657 <description>External trigger filter</description>
14658 <bitOffset>8</bitOffset>
14659 <bitWidth>4</bitWidth>
14660 </field>
14661 <field>
14662 <name>MSM</name>
14663 <description>Master/Slave mode</description>
14664 <bitOffset>7</bitOffset>
14665 <bitWidth>1</bitWidth>
14666 </field>
14667 <field>
14668 <name>TS</name>
14669 <description>Trigger selection</description>
14670 <bitOffset>4</bitOffset>
14671 <bitWidth>3</bitWidth>
14672 </field>
14673 <field>
14674 <name>SMS</name>
14675 <description>Slave mode selection</description>
14676 <bitOffset>0</bitOffset>
14677 <bitWidth>3</bitWidth>
14678 </field>
14679 </fields>
14680 </register>
14681 <register>
14682 <name>DIER</name>
14683 <displayName>DIER</displayName>
14684 <description>DMA/Interrupt enable register</description>
14685 <addressOffset>0xC</addressOffset>
14686 <size>0x20</size>
14687 <access>read-write</access>
14688 <resetValue>0x0000</resetValue>
14689 <fields>
14690 <field>
14691 <name>TDE</name>
14692 <description>Trigger DMA request enable</description>
14693 <bitOffset>14</bitOffset>
14694 <bitWidth>1</bitWidth>
14695 </field>
14696 <field>
14697 <name>CC4DE</name>
14698 <description>Capture/Compare 4 DMA request
14699 enable</description>
14700 <bitOffset>12</bitOffset>
14701 <bitWidth>1</bitWidth>
14702 </field>
14703 <field>
14704 <name>CC3DE</name>
14705 <description>Capture/Compare 3 DMA request
14706 enable</description>
14707 <bitOffset>11</bitOffset>
14708 <bitWidth>1</bitWidth>
14709 </field>
14710 <field>
14711 <name>CC2DE</name>
14712 <description>Capture/Compare 2 DMA request
14713 enable</description>
14714 <bitOffset>10</bitOffset>
14715 <bitWidth>1</bitWidth>
14716 </field>
14717 <field>
14718 <name>CC1DE</name>
14719 <description>Capture/Compare 1 DMA request
14720 enable</description>
14721 <bitOffset>9</bitOffset>
14722 <bitWidth>1</bitWidth>
14723 </field>
14724 <field>
14725 <name>UDE</name>
14726 <description>Update DMA request enable</description>
14727 <bitOffset>8</bitOffset>
14728 <bitWidth>1</bitWidth>
14729 </field>
14730 <field>
14731 <name>TIE</name>
14732 <description>Trigger interrupt enable</description>
14733 <bitOffset>6</bitOffset>
14734 <bitWidth>1</bitWidth>
14735 </field>
14736 <field>
14737 <name>CC4IE</name>
14738 <description>Capture/Compare 4 interrupt
14739 enable</description>
14740 <bitOffset>4</bitOffset>
14741 <bitWidth>1</bitWidth>
14742 </field>
14743 <field>
14744 <name>CC3IE</name>
14745 <description>Capture/Compare 3 interrupt
14746 enable</description>
14747 <bitOffset>3</bitOffset>
14748 <bitWidth>1</bitWidth>
14749 </field>
14750 <field>
14751 <name>CC2IE</name>
14752 <description>Capture/Compare 2 interrupt
14753 enable</description>
14754 <bitOffset>2</bitOffset>
14755 <bitWidth>1</bitWidth>
14756 </field>
14757 <field>
14758 <name>CC1IE</name>
14759 <description>Capture/Compare 1 interrupt
14760 enable</description>
14761 <bitOffset>1</bitOffset>
14762 <bitWidth>1</bitWidth>
14763 </field>
14764 <field>
14765 <name>UIE</name>
14766 <description>Update interrupt enable</description>
14767 <bitOffset>0</bitOffset>
14768 <bitWidth>1</bitWidth>
14769 </field>
14770 </fields>
14771 </register>
14772 <register>
14773 <name>SR</name>
14774 <displayName>SR</displayName>
14775 <description>status register</description>
14776 <addressOffset>0x10</addressOffset>
14777 <size>0x20</size>
14778 <access>read-write</access>
14779 <resetValue>0x0000</resetValue>
14780 <fields>
14781 <field>
14782 <name>CC4OF</name>
14783 <description>Capture/Compare 4 overcapture
14784 flag</description>
14785 <bitOffset>12</bitOffset>
14786 <bitWidth>1</bitWidth>
14787 </field>
14788 <field>
14789 <name>CC3OF</name>
14790 <description>Capture/Compare 3 overcapture
14791 flag</description>
14792 <bitOffset>11</bitOffset>
14793 <bitWidth>1</bitWidth>
14794 </field>
14795 <field>
14796 <name>CC2OF</name>
14797 <description>Capture/compare 2 overcapture
14798 flag</description>
14799 <bitOffset>10</bitOffset>
14800 <bitWidth>1</bitWidth>
14801 </field>
14802 <field>
14803 <name>CC1OF</name>
14804 <description>Capture/Compare 1 overcapture
14805 flag</description>
14806 <bitOffset>9</bitOffset>
14807 <bitWidth>1</bitWidth>
14808 </field>
14809 <field>
14810 <name>TIF</name>
14811 <description>Trigger interrupt flag</description>
14812 <bitOffset>6</bitOffset>
14813 <bitWidth>1</bitWidth>
14814 </field>
14815 <field>
14816 <name>CC4IF</name>
14817 <description>Capture/Compare 4 interrupt
14818 flag</description>
14819 <bitOffset>4</bitOffset>
14820 <bitWidth>1</bitWidth>
14821 </field>
14822 <field>
14823 <name>CC3IF</name>
14824 <description>Capture/Compare 3 interrupt
14825 flag</description>
14826 <bitOffset>3</bitOffset>
14827 <bitWidth>1</bitWidth>
14828 </field>
14829 <field>
14830 <name>CC2IF</name>
14831 <description>Capture/Compare 2 interrupt
14832 flag</description>
14833 <bitOffset>2</bitOffset>
14834 <bitWidth>1</bitWidth>
14835 </field>
14836 <field>
14837 <name>CC1IF</name>
14838 <description>Capture/compare 1 interrupt
14839 flag</description>
14840 <bitOffset>1</bitOffset>
14841 <bitWidth>1</bitWidth>
14842 </field>
14843 <field>
14844 <name>UIF</name>
14845 <description>Update interrupt flag</description>
14846 <bitOffset>0</bitOffset>
14847 <bitWidth>1</bitWidth>
14848 </field>
14849 </fields>
14850 </register>
14851 <register>
14852 <name>EGR</name>
14853 <displayName>EGR</displayName>
14854 <description>event generation register</description>
14855 <addressOffset>0x14</addressOffset>
14856 <size>0x20</size>
14857 <access>write-only</access>
14858 <resetValue>0x0000</resetValue>
14859 <fields>
14860 <field>
14861 <name>TG</name>
14862 <description>Trigger generation</description>
14863 <bitOffset>6</bitOffset>
14864 <bitWidth>1</bitWidth>
14865 </field>
14866 <field>
14867 <name>CC4G</name>
14868 <description>Capture/compare 4
14869 generation</description>
14870 <bitOffset>4</bitOffset>
14871 <bitWidth>1</bitWidth>
14872 </field>
14873 <field>
14874 <name>CC3G</name>
14875 <description>Capture/compare 3
14876 generation</description>
14877 <bitOffset>3</bitOffset>
14878 <bitWidth>1</bitWidth>
14879 </field>
14880 <field>
14881 <name>CC2G</name>
14882 <description>Capture/compare 2
14883 generation</description>
14884 <bitOffset>2</bitOffset>
14885 <bitWidth>1</bitWidth>
14886 </field>
14887 <field>
14888 <name>CC1G</name>
14889 <description>Capture/compare 1
14890 generation</description>
14891 <bitOffset>1</bitOffset>
14892 <bitWidth>1</bitWidth>
14893 </field>
14894 <field>
14895 <name>UG</name>
14896 <description>Update generation</description>
14897 <bitOffset>0</bitOffset>
14898 <bitWidth>1</bitWidth>
14899 </field>
14900 </fields>
14901 </register>
14902 <register>
14903 <name>CCMR1_Output</name>
14904 <displayName>CCMR1_Output</displayName>
14905 <description>capture/compare mode register 1 (output
14906 mode)</description>
14907 <addressOffset>0x18</addressOffset>
14908 <size>0x20</size>
14909 <access>read-write</access>
14910 <resetValue>0x00000000</resetValue>
14911 <fields>
14912 <field>
14913 <name>OC2CE</name>
14914 <description>OC2CE</description>
14915 <bitOffset>15</bitOffset>
14916 <bitWidth>1</bitWidth>
14917 </field>
14918 <field>
14919 <name>OC2M</name>
14920 <description>OC2M</description>
14921 <bitOffset>12</bitOffset>
14922 <bitWidth>3</bitWidth>
14923 </field>
14924 <field>
14925 <name>OC2PE</name>
14926 <description>OC2PE</description>
14927 <bitOffset>11</bitOffset>
14928 <bitWidth>1</bitWidth>
14929 </field>
14930 <field>
14931 <name>OC2FE</name>
14932 <description>OC2FE</description>
14933 <bitOffset>10</bitOffset>
14934 <bitWidth>1</bitWidth>
14935 </field>
14936 <field>
14937 <name>CC2S</name>
14938 <description>CC2S</description>
14939 <bitOffset>8</bitOffset>
14940 <bitWidth>2</bitWidth>
14941 </field>
14942 <field>
14943 <name>OC1CE</name>
14944 <description>OC1CE</description>
14945 <bitOffset>7</bitOffset>
14946 <bitWidth>1</bitWidth>
14947 </field>
14948 <field>
14949 <name>OC1M</name>
14950 <description>OC1M</description>
14951 <bitOffset>4</bitOffset>
14952 <bitWidth>3</bitWidth>
14953 </field>
14954 <field>
14955 <name>OC1PE</name>
14956 <description>OC1PE</description>
14957 <bitOffset>3</bitOffset>
14958 <bitWidth>1</bitWidth>
14959 </field>
14960 <field>
14961 <name>OC1FE</name>
14962 <description>OC1FE</description>
14963 <bitOffset>2</bitOffset>
14964 <bitWidth>1</bitWidth>
14965 </field>
14966 <field>
14967 <name>CC1S</name>
14968 <description>CC1S</description>
14969 <bitOffset>0</bitOffset>
14970 <bitWidth>2</bitWidth>
14971 </field>
14972 </fields>
14973 </register>
14974 <register>
14975 <name>CCMR1_Input</name>
14976 <displayName>CCMR1_Input</displayName>
14977 <description>capture/compare mode register 1 (input
14978 mode)</description>
14979 <alternateRegister>CCMR1_Output</alternateRegister>
14980 <addressOffset>0x18</addressOffset>
14981 <size>0x20</size>
14982 <access>read-write</access>
14983 <resetValue>0x00000000</resetValue>
14984 <fields>
14985 <field>
14986 <name>IC2F</name>
14987 <description>Input capture 2 filter</description>
14988 <bitOffset>12</bitOffset>
14989 <bitWidth>4</bitWidth>
14990 </field>
14991 <field>
14992 <name>IC2PCS</name>
14993 <description>Input capture 2 prescaler</description>
14994 <bitOffset>10</bitOffset>
14995 <bitWidth>2</bitWidth>
14996 </field>
14997 <field>
14998 <name>CC2S</name>
14999 <description>Capture/Compare 2
15000 selection</description>
15001 <bitOffset>8</bitOffset>
15002 <bitWidth>2</bitWidth>
15003 </field>
15004 <field>
15005 <name>IC1F</name>
15006 <description>Input capture 1 filter</description>
15007 <bitOffset>4</bitOffset>
15008 <bitWidth>4</bitWidth>
15009 </field>
15010 <field>
15011 <name>ICPCS</name>
15012 <description>Input capture 1 prescaler</description>
15013 <bitOffset>2</bitOffset>
15014 <bitWidth>2</bitWidth>
15015 </field>
15016 <field>
15017 <name>CC1S</name>
15018 <description>Capture/Compare 1
15019 selection</description>
15020 <bitOffset>0</bitOffset>
15021 <bitWidth>2</bitWidth>
15022 </field>
15023 </fields>
15024 </register>
15025 <register>
15026 <name>CCMR2_Output</name>
15027 <displayName>CCMR2_Output</displayName>
15028 <description>capture/compare mode register 2 (output
15029 mode)</description>
15030 <addressOffset>0x1C</addressOffset>
15031 <size>0x20</size>
15032 <access>read-write</access>
15033 <resetValue>0x00000000</resetValue>
15034 <fields>
15035 <field>
15036 <name>O24CE</name>
15037 <description>O24CE</description>
15038 <bitOffset>15</bitOffset>
15039 <bitWidth>1</bitWidth>
15040 </field>
15041 <field>
15042 <name>OC4M</name>
15043 <description>OC4M</description>
15044 <bitOffset>12</bitOffset>
15045 <bitWidth>3</bitWidth>
15046 </field>
15047 <field>
15048 <name>OC4PE</name>
15049 <description>OC4PE</description>
15050 <bitOffset>11</bitOffset>
15051 <bitWidth>1</bitWidth>
15052 </field>
15053 <field>
15054 <name>OC4FE</name>
15055 <description>OC4FE</description>
15056 <bitOffset>10</bitOffset>
15057 <bitWidth>1</bitWidth>
15058 </field>
15059 <field>
15060 <name>CC4S</name>
15061 <description>CC4S</description>
15062 <bitOffset>8</bitOffset>
15063 <bitWidth>2</bitWidth>
15064 </field>
15065 <field>
15066 <name>OC3CE</name>
15067 <description>OC3CE</description>
15068 <bitOffset>7</bitOffset>
15069 <bitWidth>1</bitWidth>
15070 </field>
15071 <field>
15072 <name>OC3M</name>
15073 <description>OC3M</description>
15074 <bitOffset>4</bitOffset>
15075 <bitWidth>3</bitWidth>
15076 </field>
15077 <field>
15078 <name>OC3PE</name>
15079 <description>OC3PE</description>
15080 <bitOffset>3</bitOffset>
15081 <bitWidth>1</bitWidth>
15082 </field>
15083 <field>
15084 <name>OC3FE</name>
15085 <description>OC3FE</description>
15086 <bitOffset>2</bitOffset>
15087 <bitWidth>1</bitWidth>
15088 </field>
15089 <field>
15090 <name>CC3S</name>
15091 <description>CC3S</description>
15092 <bitOffset>0</bitOffset>
15093 <bitWidth>2</bitWidth>
15094 </field>
15095 </fields>
15096 </register>
15097 <register>
15098 <name>CCMR2_Input</name>
15099 <displayName>CCMR2_Input</displayName>
15100 <description>capture/compare mode register 2 (input
15101 mode)</description>
15102 <alternateRegister>CCMR2_Output</alternateRegister>
15103 <addressOffset>0x1C</addressOffset>
15104 <size>0x20</size>
15105 <access>read-write</access>
15106 <resetValue>0x00000000</resetValue>
15107 <fields>
15108 <field>
15109 <name>IC4F</name>
15110 <description>Input capture 4 filter</description>
15111 <bitOffset>12</bitOffset>
15112 <bitWidth>4</bitWidth>
15113 </field>
15114 <field>
15115 <name>IC4PSC</name>
15116 <description>Input capture 4 prescaler</description>
15117 <bitOffset>10</bitOffset>
15118 <bitWidth>2</bitWidth>
15119 </field>
15120 <field>
15121 <name>CC4S</name>
15122 <description>Capture/Compare 4
15123 selection</description>
15124 <bitOffset>8</bitOffset>
15125 <bitWidth>2</bitWidth>
15126 </field>
15127 <field>
15128 <name>IC3F</name>
15129 <description>Input capture 3 filter</description>
15130 <bitOffset>4</bitOffset>
15131 <bitWidth>4</bitWidth>
15132 </field>
15133 <field>
15134 <name>IC3PSC</name>
15135 <description>Input capture 3 prescaler</description>
15136 <bitOffset>2</bitOffset>
15137 <bitWidth>2</bitWidth>
15138 </field>
15139 <field>
15140 <name>CC3S</name>
15141 <description>Capture/compare 3
15142 selection</description>
15143 <bitOffset>0</bitOffset>
15144 <bitWidth>2</bitWidth>
15145 </field>
15146 </fields>
15147 </register>
15148 <register>
15149 <name>CCER</name>
15150 <displayName>CCER</displayName>
15151 <description>capture/compare enable
15152 register</description>
15153 <addressOffset>0x20</addressOffset>
15154 <size>0x20</size>
15155 <access>read-write</access>
15156 <resetValue>0x0000</resetValue>
15157 <fields>
15158 <field>
15159 <name>CC4NP</name>
15160 <description>Capture/Compare 4 output
15161 Polarity</description>
15162 <bitOffset>15</bitOffset>
15163 <bitWidth>1</bitWidth>
15164 </field>
15165 <field>
15166 <name>CC4P</name>
15167 <description>Capture/Compare 3 output
15168 Polarity</description>
15169 <bitOffset>13</bitOffset>
15170 <bitWidth>1</bitWidth>
15171 </field>
15172 <field>
15173 <name>CC4E</name>
15174 <description>Capture/Compare 4 output
15175 enable</description>
15176 <bitOffset>12</bitOffset>
15177 <bitWidth>1</bitWidth>
15178 </field>
15179 <field>
15180 <name>CC3NP</name>
15181 <description>Capture/Compare 3 output
15182 Polarity</description>
15183 <bitOffset>11</bitOffset>
15184 <bitWidth>1</bitWidth>
15185 </field>
15186 <field>
15187 <name>CC3P</name>
15188 <description>Capture/Compare 3 output
15189 Polarity</description>
15190 <bitOffset>9</bitOffset>
15191 <bitWidth>1</bitWidth>
15192 </field>
15193 <field>
15194 <name>CC3E</name>
15195 <description>Capture/Compare 3 output
15196 enable</description>
15197 <bitOffset>8</bitOffset>
15198 <bitWidth>1</bitWidth>
15199 </field>
15200 <field>
15201 <name>CC2NP</name>
15202 <description>Capture/Compare 2 output
15203 Polarity</description>
15204 <bitOffset>7</bitOffset>
15205 <bitWidth>1</bitWidth>
15206 </field>
15207 <field>
15208 <name>CC2P</name>
15209 <description>Capture/Compare 2 output
15210 Polarity</description>
15211 <bitOffset>5</bitOffset>
15212 <bitWidth>1</bitWidth>
15213 </field>
15214 <field>
15215 <name>CC2E</name>
15216 <description>Capture/Compare 2 output
15217 enable</description>
15218 <bitOffset>4</bitOffset>
15219 <bitWidth>1</bitWidth>
15220 </field>
15221 <field>
15222 <name>CC1NP</name>
15223 <description>Capture/Compare 1 output
15224 Polarity</description>
15225 <bitOffset>3</bitOffset>
15226 <bitWidth>1</bitWidth>
15227 </field>
15228 <field>
15229 <name>CC1P</name>
15230 <description>Capture/Compare 1 output
15231 Polarity</description>
15232 <bitOffset>1</bitOffset>
15233 <bitWidth>1</bitWidth>
15234 </field>
15235 <field>
15236 <name>CC1E</name>
15237 <description>Capture/Compare 1 output
15238 enable</description>
15239 <bitOffset>0</bitOffset>
15240 <bitWidth>1</bitWidth>
15241 </field>
15242 </fields>
15243 </register>
15244 <register>
15245 <name>CNT</name>
15246 <displayName>CNT</displayName>
15247 <description>counter</description>
15248 <addressOffset>0x24</addressOffset>
15249 <size>0x20</size>
15250 <access>read-write</access>
15251 <resetValue>0x00000000</resetValue>
15252 <fields>
15253 <field>
15254 <name>CNT_H</name>
15255 <description>High counter value</description>
15256 <bitOffset>16</bitOffset>
15257 <bitWidth>16</bitWidth>
15258 </field>
15259 <field>
15260 <name>CNT_L</name>
15261 <description>Low counter value</description>
15262 <bitOffset>0</bitOffset>
15263 <bitWidth>16</bitWidth>
15264 </field>
15265 </fields>
15266 </register>
15267 <register>
15268 <name>PSC</name>
15269 <displayName>PSC</displayName>
15270 <description>prescaler</description>
15271 <addressOffset>0x28</addressOffset>
15272 <size>0x20</size>
15273 <access>read-write</access>
15274 <resetValue>0x0000</resetValue>
15275 <fields>
15276 <field>
15277 <name>PSC</name>
15278 <description>Prescaler value</description>
15279 <bitOffset>0</bitOffset>
15280 <bitWidth>16</bitWidth>
15281 </field>
15282 </fields>
15283 </register>
15284 <register>
15285 <name>ARR</name>
15286 <displayName>ARR</displayName>
15287 <description>auto-reload register</description>
15288 <addressOffset>0x2C</addressOffset>
15289 <size>0x20</size>
15290 <access>read-write</access>
15291 <resetValue>0x00000000</resetValue>
15292 <fields>
15293 <field>
15294 <name>ARR_H</name>
15295 <description>High Auto-reload value</description>
15296 <bitOffset>16</bitOffset>
15297 <bitWidth>16</bitWidth>
15298 </field>
15299 <field>
15300 <name>ARR_L</name>
15301 <description>Low Auto-reload value</description>
15302 <bitOffset>0</bitOffset>
15303 <bitWidth>16</bitWidth>
15304 </field>
15305 </fields>
15306 </register>
15307 <register>
15308 <name>CCR1</name>
15309 <displayName>CCR1</displayName>
15310 <description>capture/compare register 1</description>
15311 <addressOffset>0x34</addressOffset>
15312 <size>0x20</size>
15313 <access>read-write</access>
15314 <resetValue>0x00000000</resetValue>
15315 <fields>
15316 <field>
15317 <name>CCR1_H</name>
15318 <description>High Capture/Compare 1
15319 value</description>
15320 <bitOffset>16</bitOffset>
15321 <bitWidth>16</bitWidth>
15322 </field>
15323 <field>
15324 <name>CCR1_L</name>
15325 <description>Low Capture/Compare 1
15326 value</description>
15327 <bitOffset>0</bitOffset>
15328 <bitWidth>16</bitWidth>
15329 </field>
15330 </fields>
15331 </register>
15332 <register>
15333 <name>CCR2</name>
15334 <displayName>CCR2</displayName>
15335 <description>capture/compare register 2</description>
15336 <addressOffset>0x38</addressOffset>
15337 <size>0x20</size>
15338 <access>read-write</access>
15339 <resetValue>0x00000000</resetValue>
15340 <fields>
15341 <field>
15342 <name>CCR2_H</name>
15343 <description>High Capture/Compare 2
15344 value</description>
15345 <bitOffset>16</bitOffset>
15346 <bitWidth>16</bitWidth>
15347 </field>
15348 <field>
15349 <name>CCR2_L</name>
15350 <description>Low Capture/Compare 2
15351 value</description>
15352 <bitOffset>0</bitOffset>
15353 <bitWidth>16</bitWidth>
15354 </field>
15355 </fields>
15356 </register>
15357 <register>
15358 <name>CCR3</name>
15359 <displayName>CCR3</displayName>
15360 <description>capture/compare register 3</description>
15361 <addressOffset>0x3C</addressOffset>
15362 <size>0x20</size>
15363 <access>read-write</access>
15364 <resetValue>0x00000000</resetValue>
15365 <fields>
15366 <field>
15367 <name>CCR3_H</name>
15368 <description>High Capture/Compare value</description>
15369 <bitOffset>16</bitOffset>
15370 <bitWidth>16</bitWidth>
15371 </field>
15372 <field>
15373 <name>CCR3_L</name>
15374 <description>Low Capture/Compare value</description>
15375 <bitOffset>0</bitOffset>
15376 <bitWidth>16</bitWidth>
15377 </field>
15378 </fields>
15379 </register>
15380 <register>
15381 <name>CCR4</name>
15382 <displayName>CCR4</displayName>
15383 <description>capture/compare register 4</description>
15384 <addressOffset>0x40</addressOffset>
15385 <size>0x20</size>
15386 <access>read-write</access>
15387 <resetValue>0x00000000</resetValue>
15388 <fields>
15389 <field>
15390 <name>CCR4_H</name>
15391 <description>High Capture/Compare value</description>
15392 <bitOffset>16</bitOffset>
15393 <bitWidth>16</bitWidth>
15394 </field>
15395 <field>
15396 <name>CCR4_L</name>
15397 <description>Low Capture/Compare value</description>
15398 <bitOffset>0</bitOffset>
15399 <bitWidth>16</bitWidth>
15400 </field>
15401 </fields>
15402 </register>
15403 <register>
15404 <name>DCR</name>
15405 <displayName>DCR</displayName>
15406 <description>DMA control register</description>
15407 <addressOffset>0x48</addressOffset>
15408 <size>0x20</size>
15409 <access>read-write</access>
15410 <resetValue>0x0000</resetValue>
15411 <fields>
15412 <field>
15413 <name>DBL</name>
15414 <description>DMA burst length</description>
15415 <bitOffset>8</bitOffset>
15416 <bitWidth>5</bitWidth>
15417 </field>
15418 <field>
15419 <name>DBA</name>
15420 <description>DMA base address</description>
15421 <bitOffset>0</bitOffset>
15422 <bitWidth>5</bitWidth>
15423 </field>
15424 </fields>
15425 </register>
15426 <register>
15427 <name>DMAR</name>
15428 <displayName>DMAR</displayName>
15429 <description>DMA address for full transfer</description>
15430 <addressOffset>0x4C</addressOffset>
15431 <size>0x20</size>
15432 <access>read-write</access>
15433 <resetValue>0x0000</resetValue>
15434 <fields>
15435 <field>
15436 <name>DMAB</name>
15437 <description>DMA register for burst
15438 accesses</description>
15439 <bitOffset>0</bitOffset>
15440 <bitWidth>16</bitWidth>
15441 </field>
15442 </fields>
15443 </register>
15444 </registers>
15445 </peripheral>
15446 <peripheral derivedFrom="TIM3">
15447 <name>TIM4</name>
15448 <baseAddress>0x40000800</baseAddress>
15449 </peripheral>
15450 <peripheral>
15451 <name>TIM5</name>
15452 <description>General-purpose-timers</description>
15453 <groupName>TIM</groupName>
15454 <baseAddress>0x40000C00</baseAddress>
15455 <addressBlock>
15456 <offset>0x0</offset>
15457 <size>0x400</size>
15458 <usage>registers</usage>
15459 </addressBlock>
15460 <registers>
15461 <register>
15462 <name>CR1</name>
15463 <displayName>CR1</displayName>
15464 <description>control register 1</description>
15465 <addressOffset>0x0</addressOffset>
15466 <size>0x20</size>
15467 <access>read-write</access>
15468 <resetValue>0x0000</resetValue>
15469 <fields>
15470 <field>
15471 <name>CKD</name>
15472 <description>Clock division</description>
15473 <bitOffset>8</bitOffset>
15474 <bitWidth>2</bitWidth>
15475 </field>
15476 <field>
15477 <name>ARPE</name>
15478 <description>Auto-reload preload enable</description>
15479 <bitOffset>7</bitOffset>
15480 <bitWidth>1</bitWidth>
15481 </field>
15482 <field>
15483 <name>CMS</name>
15484 <description>Center-aligned mode
15485 selection</description>
15486 <bitOffset>5</bitOffset>
15487 <bitWidth>2</bitWidth>
15488 </field>
15489 <field>
15490 <name>DIR</name>
15491 <description>Direction</description>
15492 <bitOffset>4</bitOffset>
15493 <bitWidth>1</bitWidth>
15494 </field>
15495 <field>
15496 <name>OPM</name>
15497 <description>One-pulse mode</description>
15498 <bitOffset>3</bitOffset>
15499 <bitWidth>1</bitWidth>
15500 </field>
15501 <field>
15502 <name>URS</name>
15503 <description>Update request source</description>
15504 <bitOffset>2</bitOffset>
15505 <bitWidth>1</bitWidth>
15506 </field>
15507 <field>
15508 <name>UDIS</name>
15509 <description>Update disable</description>
15510 <bitOffset>1</bitOffset>
15511 <bitWidth>1</bitWidth>
15512 </field>
15513 <field>
15514 <name>CEN</name>
15515 <description>Counter enable</description>
15516 <bitOffset>0</bitOffset>
15517 <bitWidth>1</bitWidth>
15518 </field>
15519 </fields>
15520 </register>
15521 <register>
15522 <name>CR2</name>
15523 <displayName>CR2</displayName>
15524 <description>control register 2</description>
15525 <addressOffset>0x4</addressOffset>
15526 <size>0x20</size>
15527 <access>read-write</access>
15528 <resetValue>0x0000</resetValue>
15529 <fields>
15530 <field>
15531 <name>TI1S</name>
15532 <description>TI1 selection</description>
15533 <bitOffset>7</bitOffset>
15534 <bitWidth>1</bitWidth>
15535 </field>
15536 <field>
15537 <name>MMS</name>
15538 <description>Master mode selection</description>
15539 <bitOffset>4</bitOffset>
15540 <bitWidth>3</bitWidth>
15541 </field>
15542 <field>
15543 <name>CCDS</name>
15544 <description>Capture/compare DMA
15545 selection</description>
15546 <bitOffset>3</bitOffset>
15547 <bitWidth>1</bitWidth>
15548 </field>
15549 </fields>
15550 </register>
15551 <register>
15552 <name>SMCR</name>
15553 <displayName>SMCR</displayName>
15554 <description>slave mode control register</description>
15555 <addressOffset>0x8</addressOffset>
15556 <size>0x20</size>
15557 <access>read-write</access>
15558 <resetValue>0x0000</resetValue>
15559 <fields>
15560 <field>
15561 <name>ETP</name>
15562 <description>External trigger polarity</description>
15563 <bitOffset>15</bitOffset>
15564 <bitWidth>1</bitWidth>
15565 </field>
15566 <field>
15567 <name>ECE</name>
15568 <description>External clock enable</description>
15569 <bitOffset>14</bitOffset>
15570 <bitWidth>1</bitWidth>
15571 </field>
15572 <field>
15573 <name>ETPS</name>
15574 <description>External trigger prescaler</description>
15575 <bitOffset>12</bitOffset>
15576 <bitWidth>2</bitWidth>
15577 </field>
15578 <field>
15579 <name>ETF</name>
15580 <description>External trigger filter</description>
15581 <bitOffset>8</bitOffset>
15582 <bitWidth>4</bitWidth>
15583 </field>
15584 <field>
15585 <name>MSM</name>
15586 <description>Master/Slave mode</description>
15587 <bitOffset>7</bitOffset>
15588 <bitWidth>1</bitWidth>
15589 </field>
15590 <field>
15591 <name>TS</name>
15592 <description>Trigger selection</description>
15593 <bitOffset>4</bitOffset>
15594 <bitWidth>3</bitWidth>
15595 </field>
15596 <field>
15597 <name>SMS</name>
15598 <description>Slave mode selection</description>
15599 <bitOffset>0</bitOffset>
15600 <bitWidth>3</bitWidth>
15601 </field>
15602 </fields>
15603 </register>
15604 <register>
15605 <name>DIER</name>
15606 <displayName>DIER</displayName>
15607 <description>DMA/Interrupt enable register</description>
15608 <addressOffset>0xC</addressOffset>
15609 <size>0x20</size>
15610 <access>read-write</access>
15611 <resetValue>0x0000</resetValue>
15612 <fields>
15613 <field>
15614 <name>TDE</name>
15615 <description>Trigger DMA request enable</description>
15616 <bitOffset>14</bitOffset>
15617 <bitWidth>1</bitWidth>
15618 </field>
15619 <field>
15620 <name>CC4DE</name>
15621 <description>Capture/Compare 4 DMA request
15622 enable</description>
15623 <bitOffset>12</bitOffset>
15624 <bitWidth>1</bitWidth>
15625 </field>
15626 <field>
15627 <name>CC3DE</name>
15628 <description>Capture/Compare 3 DMA request
15629 enable</description>
15630 <bitOffset>11</bitOffset>
15631 <bitWidth>1</bitWidth>
15632 </field>
15633 <field>
15634 <name>CC2DE</name>
15635 <description>Capture/Compare 2 DMA request
15636 enable</description>
15637 <bitOffset>10</bitOffset>
15638 <bitWidth>1</bitWidth>
15639 </field>
15640 <field>
15641 <name>CC1DE</name>
15642 <description>Capture/Compare 1 DMA request
15643 enable</description>
15644 <bitOffset>9</bitOffset>
15645 <bitWidth>1</bitWidth>
15646 </field>
15647 <field>
15648 <name>UDE</name>
15649 <description>Update DMA request enable</description>
15650 <bitOffset>8</bitOffset>
15651 <bitWidth>1</bitWidth>
15652 </field>
15653 <field>
15654 <name>TIE</name>
15655 <description>Trigger interrupt enable</description>
15656 <bitOffset>6</bitOffset>
15657 <bitWidth>1</bitWidth>
15658 </field>
15659 <field>
15660 <name>CC4IE</name>
15661 <description>Capture/Compare 4 interrupt
15662 enable</description>
15663 <bitOffset>4</bitOffset>
15664 <bitWidth>1</bitWidth>
15665 </field>
15666 <field>
15667 <name>CC3IE</name>
15668 <description>Capture/Compare 3 interrupt
15669 enable</description>
15670 <bitOffset>3</bitOffset>
15671 <bitWidth>1</bitWidth>
15672 </field>
15673 <field>
15674 <name>CC2IE</name>
15675 <description>Capture/Compare 2 interrupt
15676 enable</description>
15677 <bitOffset>2</bitOffset>
15678 <bitWidth>1</bitWidth>
15679 </field>
15680 <field>
15681 <name>CC1IE</name>
15682 <description>Capture/Compare 1 interrupt
15683 enable</description>
15684 <bitOffset>1</bitOffset>
15685 <bitWidth>1</bitWidth>
15686 </field>
15687 <field>
15688 <name>UIE</name>
15689 <description>Update interrupt enable</description>
15690 <bitOffset>0</bitOffset>
15691 <bitWidth>1</bitWidth>
15692 </field>
15693 </fields>
15694 </register>
15695 <register>
15696 <name>SR</name>
15697 <displayName>SR</displayName>
15698 <description>status register</description>
15699 <addressOffset>0x10</addressOffset>
15700 <size>0x20</size>
15701 <access>read-write</access>
15702 <resetValue>0x0000</resetValue>
15703 <fields>
15704 <field>
15705 <name>CC4OF</name>
15706 <description>Capture/Compare 4 overcapture
15707 flag</description>
15708 <bitOffset>12</bitOffset>
15709 <bitWidth>1</bitWidth>
15710 </field>
15711 <field>
15712 <name>CC3OF</name>
15713 <description>Capture/Compare 3 overcapture
15714 flag</description>
15715 <bitOffset>11</bitOffset>
15716 <bitWidth>1</bitWidth>
15717 </field>
15718 <field>
15719 <name>CC2OF</name>
15720 <description>Capture/compare 2 overcapture
15721 flag</description>
15722 <bitOffset>10</bitOffset>
15723 <bitWidth>1</bitWidth>
15724 </field>
15725 <field>
15726 <name>CC1OF</name>
15727 <description>Capture/Compare 1 overcapture
15728 flag</description>
15729 <bitOffset>9</bitOffset>
15730 <bitWidth>1</bitWidth>
15731 </field>
15732 <field>
15733 <name>TIF</name>
15734 <description>Trigger interrupt flag</description>
15735 <bitOffset>6</bitOffset>
15736 <bitWidth>1</bitWidth>
15737 </field>
15738 <field>
15739 <name>CC4IF</name>
15740 <description>Capture/Compare 4 interrupt
15741 flag</description>
15742 <bitOffset>4</bitOffset>
15743 <bitWidth>1</bitWidth>
15744 </field>
15745 <field>
15746 <name>CC3IF</name>
15747 <description>Capture/Compare 3 interrupt
15748 flag</description>
15749 <bitOffset>3</bitOffset>
15750 <bitWidth>1</bitWidth>
15751 </field>
15752 <field>
15753 <name>CC2IF</name>
15754 <description>Capture/Compare 2 interrupt
15755 flag</description>
15756 <bitOffset>2</bitOffset>
15757 <bitWidth>1</bitWidth>
15758 </field>
15759 <field>
15760 <name>CC1IF</name>
15761 <description>Capture/compare 1 interrupt
15762 flag</description>
15763 <bitOffset>1</bitOffset>
15764 <bitWidth>1</bitWidth>
15765 </field>
15766 <field>
15767 <name>UIF</name>
15768 <description>Update interrupt flag</description>
15769 <bitOffset>0</bitOffset>
15770 <bitWidth>1</bitWidth>
15771 </field>
15772 </fields>
15773 </register>
15774 <register>
15775 <name>EGR</name>
15776 <displayName>EGR</displayName>
15777 <description>event generation register</description>
15778 <addressOffset>0x14</addressOffset>
15779 <size>0x20</size>
15780 <access>write-only</access>
15781 <resetValue>0x0000</resetValue>
15782 <fields>
15783 <field>
15784 <name>TG</name>
15785 <description>Trigger generation</description>
15786 <bitOffset>6</bitOffset>
15787 <bitWidth>1</bitWidth>
15788 </field>
15789 <field>
15790 <name>CC4G</name>
15791 <description>Capture/compare 4
15792 generation</description>
15793 <bitOffset>4</bitOffset>
15794 <bitWidth>1</bitWidth>
15795 </field>
15796 <field>
15797 <name>CC3G</name>
15798 <description>Capture/compare 3
15799 generation</description>
15800 <bitOffset>3</bitOffset>
15801 <bitWidth>1</bitWidth>
15802 </field>
15803 <field>
15804 <name>CC2G</name>
15805 <description>Capture/compare 2
15806 generation</description>
15807 <bitOffset>2</bitOffset>
15808 <bitWidth>1</bitWidth>
15809 </field>
15810 <field>
15811 <name>CC1G</name>
15812 <description>Capture/compare 1
15813 generation</description>
15814 <bitOffset>1</bitOffset>
15815 <bitWidth>1</bitWidth>
15816 </field>
15817 <field>
15818 <name>UG</name>
15819 <description>Update generation</description>
15820 <bitOffset>0</bitOffset>
15821 <bitWidth>1</bitWidth>
15822 </field>
15823 </fields>
15824 </register>
15825 <register>
15826 <name>CCMR1_Output</name>
15827 <displayName>CCMR1_Output</displayName>
15828 <description>capture/compare mode register 1 (output
15829 mode)</description>
15830 <addressOffset>0x18</addressOffset>
15831 <size>0x20</size>
15832 <access>read-write</access>
15833 <resetValue>0x00000000</resetValue>
15834 <fields>
15835 <field>
15836 <name>OC2CE</name>
15837 <description>OC2CE</description>
15838 <bitOffset>15</bitOffset>
15839 <bitWidth>1</bitWidth>
15840 </field>
15841 <field>
15842 <name>OC2M</name>
15843 <description>OC2M</description>
15844 <bitOffset>12</bitOffset>
15845 <bitWidth>3</bitWidth>
15846 </field>
15847 <field>
15848 <name>OC2PE</name>
15849 <description>OC2PE</description>
15850 <bitOffset>11</bitOffset>
15851 <bitWidth>1</bitWidth>
15852 </field>
15853 <field>
15854 <name>OC2FE</name>
15855 <description>OC2FE</description>
15856 <bitOffset>10</bitOffset>
15857 <bitWidth>1</bitWidth>
15858 </field>
15859 <field>
15860 <name>CC2S</name>
15861 <description>CC2S</description>
15862 <bitOffset>8</bitOffset>
15863 <bitWidth>2</bitWidth>
15864 </field>
15865 <field>
15866 <name>OC1CE</name>
15867 <description>OC1CE</description>
15868 <bitOffset>7</bitOffset>
15869 <bitWidth>1</bitWidth>
15870 </field>
15871 <field>
15872 <name>OC1M</name>
15873 <description>OC1M</description>
15874 <bitOffset>4</bitOffset>
15875 <bitWidth>3</bitWidth>
15876 </field>
15877 <field>
15878 <name>OC1PE</name>
15879 <description>OC1PE</description>
15880 <bitOffset>3</bitOffset>
15881 <bitWidth>1</bitWidth>
15882 </field>
15883 <field>
15884 <name>OC1FE</name>
15885 <description>OC1FE</description>
15886 <bitOffset>2</bitOffset>
15887 <bitWidth>1</bitWidth>
15888 </field>
15889 <field>
15890 <name>CC1S</name>
15891 <description>CC1S</description>
15892 <bitOffset>0</bitOffset>
15893 <bitWidth>2</bitWidth>
15894 </field>
15895 </fields>
15896 </register>
15897 <register>
15898 <name>CCMR1_Input</name>
15899 <displayName>CCMR1_Input</displayName>
15900 <description>capture/compare mode register 1 (input
15901 mode)</description>
15902 <alternateRegister>CCMR1_Output</alternateRegister>
15903 <addressOffset>0x18</addressOffset>
15904 <size>0x20</size>
15905 <access>read-write</access>
15906 <resetValue>0x00000000</resetValue>
15907 <fields>
15908 <field>
15909 <name>IC2F</name>
15910 <description>Input capture 2 filter</description>
15911 <bitOffset>12</bitOffset>
15912 <bitWidth>4</bitWidth>
15913 </field>
15914 <field>
15915 <name>IC2PCS</name>
15916 <description>Input capture 2 prescaler</description>
15917 <bitOffset>10</bitOffset>
15918 <bitWidth>2</bitWidth>
15919 </field>
15920 <field>
15921 <name>CC2S</name>
15922 <description>Capture/Compare 2
15923 selection</description>
15924 <bitOffset>8</bitOffset>
15925 <bitWidth>2</bitWidth>
15926 </field>
15927 <field>
15928 <name>IC1F</name>
15929 <description>Input capture 1 filter</description>
15930 <bitOffset>4</bitOffset>
15931 <bitWidth>4</bitWidth>
15932 </field>
15933 <field>
15934 <name>ICPCS</name>
15935 <description>Input capture 1 prescaler</description>
15936 <bitOffset>2</bitOffset>
15937 <bitWidth>2</bitWidth>
15938 </field>
15939 <field>
15940 <name>CC1S</name>
15941 <description>Capture/Compare 1
15942 selection</description>
15943 <bitOffset>0</bitOffset>
15944 <bitWidth>2</bitWidth>
15945 </field>
15946 </fields>
15947 </register>
15948 <register>
15949 <name>CCMR2_Output</name>
15950 <displayName>CCMR2_Output</displayName>
15951 <description>capture/compare mode register 2 (output
15952 mode)</description>
15953 <addressOffset>0x1C</addressOffset>
15954 <size>0x20</size>
15955 <access>read-write</access>
15956 <resetValue>0x00000000</resetValue>
15957 <fields>
15958 <field>
15959 <name>O24CE</name>
15960 <description>O24CE</description>
15961 <bitOffset>15</bitOffset>
15962 <bitWidth>1</bitWidth>
15963 </field>
15964 <field>
15965 <name>OC4M</name>
15966 <description>OC4M</description>
15967 <bitOffset>12</bitOffset>
15968 <bitWidth>3</bitWidth>
15969 </field>
15970 <field>
15971 <name>OC4PE</name>
15972 <description>OC4PE</description>
15973 <bitOffset>11</bitOffset>
15974 <bitWidth>1</bitWidth>
15975 </field>
15976 <field>
15977 <name>OC4FE</name>
15978 <description>OC4FE</description>
15979 <bitOffset>10</bitOffset>
15980 <bitWidth>1</bitWidth>
15981 </field>
15982 <field>
15983 <name>CC4S</name>
15984 <description>CC4S</description>
15985 <bitOffset>8</bitOffset>
15986 <bitWidth>2</bitWidth>
15987 </field>
15988 <field>
15989 <name>OC3CE</name>
15990 <description>OC3CE</description>
15991 <bitOffset>7</bitOffset>
15992 <bitWidth>1</bitWidth>
15993 </field>
15994 <field>
15995 <name>OC3M</name>
15996 <description>OC3M</description>
15997 <bitOffset>4</bitOffset>
15998 <bitWidth>3</bitWidth>
15999 </field>
16000 <field>
16001 <name>OC3PE</name>
16002 <description>OC3PE</description>
16003 <bitOffset>3</bitOffset>
16004 <bitWidth>1</bitWidth>
16005 </field>
16006 <field>
16007 <name>OC3FE</name>
16008 <description>OC3FE</description>
16009 <bitOffset>2</bitOffset>
16010 <bitWidth>1</bitWidth>
16011 </field>
16012 <field>
16013 <name>CC3S</name>
16014 <description>CC3S</description>
16015 <bitOffset>0</bitOffset>
16016 <bitWidth>2</bitWidth>
16017 </field>
16018 </fields>
16019 </register>
16020 <register>
16021 <name>CCMR2_Input</name>
16022 <displayName>CCMR2_Input</displayName>
16023 <description>capture/compare mode register 2 (input
16024 mode)</description>
16025 <alternateRegister>CCMR2_Output</alternateRegister>
16026 <addressOffset>0x1C</addressOffset>
16027 <size>0x20</size>
16028 <access>read-write</access>
16029 <resetValue>0x00000000</resetValue>
16030 <fields>
16031 <field>
16032 <name>IC4F</name>
16033 <description>Input capture 4 filter</description>
16034 <bitOffset>12</bitOffset>
16035 <bitWidth>4</bitWidth>
16036 </field>
16037 <field>
16038 <name>IC4PSC</name>
16039 <description>Input capture 4 prescaler</description>
16040 <bitOffset>10</bitOffset>
16041 <bitWidth>2</bitWidth>
16042 </field>
16043 <field>
16044 <name>CC4S</name>
16045 <description>Capture/Compare 4
16046 selection</description>
16047 <bitOffset>8</bitOffset>
16048 <bitWidth>2</bitWidth>
16049 </field>
16050 <field>
16051 <name>IC3F</name>
16052 <description>Input capture 3 filter</description>
16053 <bitOffset>4</bitOffset>
16054 <bitWidth>4</bitWidth>
16055 </field>
16056 <field>
16057 <name>IC3PSC</name>
16058 <description>Input capture 3 prescaler</description>
16059 <bitOffset>2</bitOffset>
16060 <bitWidth>2</bitWidth>
16061 </field>
16062 <field>
16063 <name>CC3S</name>
16064 <description>Capture/compare 3
16065 selection</description>
16066 <bitOffset>0</bitOffset>
16067 <bitWidth>2</bitWidth>
16068 </field>
16069 </fields>
16070 </register>
16071 <register>
16072 <name>CCER</name>
16073 <displayName>CCER</displayName>
16074 <description>capture/compare enable
16075 register</description>
16076 <addressOffset>0x20</addressOffset>
16077 <size>0x20</size>
16078 <access>read-write</access>
16079 <resetValue>0x0000</resetValue>
16080 <fields>
16081 <field>
16082 <name>CC4NP</name>
16083 <description>Capture/Compare 4 output
16084 Polarity</description>
16085 <bitOffset>15</bitOffset>
16086 <bitWidth>1</bitWidth>
16087 </field>
16088 <field>
16089 <name>CC4P</name>
16090 <description>Capture/Compare 3 output
16091 Polarity</description>
16092 <bitOffset>13</bitOffset>
16093 <bitWidth>1</bitWidth>
16094 </field>
16095 <field>
16096 <name>CC4E</name>
16097 <description>Capture/Compare 4 output
16098 enable</description>
16099 <bitOffset>12</bitOffset>
16100 <bitWidth>1</bitWidth>
16101 </field>
16102 <field>
16103 <name>CC3NP</name>
16104 <description>Capture/Compare 3 output
16105 Polarity</description>
16106 <bitOffset>11</bitOffset>
16107 <bitWidth>1</bitWidth>
16108 </field>
16109 <field>
16110 <name>CC3P</name>
16111 <description>Capture/Compare 3 output
16112 Polarity</description>
16113 <bitOffset>9</bitOffset>
16114 <bitWidth>1</bitWidth>
16115 </field>
16116 <field>
16117 <name>CC3E</name>
16118 <description>Capture/Compare 3 output
16119 enable</description>
16120 <bitOffset>8</bitOffset>
16121 <bitWidth>1</bitWidth>
16122 </field>
16123 <field>
16124 <name>CC2NP</name>
16125 <description>Capture/Compare 2 output
16126 Polarity</description>
16127 <bitOffset>7</bitOffset>
16128 <bitWidth>1</bitWidth>
16129 </field>
16130 <field>
16131 <name>CC2P</name>
16132 <description>Capture/Compare 2 output
16133 Polarity</description>
16134 <bitOffset>5</bitOffset>
16135 <bitWidth>1</bitWidth>
16136 </field>
16137 <field>
16138 <name>CC2E</name>
16139 <description>Capture/Compare 2 output
16140 enable</description>
16141 <bitOffset>4</bitOffset>
16142 <bitWidth>1</bitWidth>
16143 </field>
16144 <field>
16145 <name>CC1NP</name>
16146 <description>Capture/Compare 1 output
16147 Polarity</description>
16148 <bitOffset>3</bitOffset>
16149 <bitWidth>1</bitWidth>
16150 </field>
16151 <field>
16152 <name>CC1P</name>
16153 <description>Capture/Compare 1 output
16154 Polarity</description>
16155 <bitOffset>1</bitOffset>
16156 <bitWidth>1</bitWidth>
16157 </field>
16158 <field>
16159 <name>CC1E</name>
16160 <description>Capture/Compare 1 output
16161 enable</description>
16162 <bitOffset>0</bitOffset>
16163 <bitWidth>1</bitWidth>
16164 </field>
16165 </fields>
16166 </register>
16167 <register>
16168 <name>CNT</name>
16169 <displayName>CNT</displayName>
16170 <description>counter</description>
16171 <addressOffset>0x24</addressOffset>
16172 <size>0x20</size>
16173 <access>read-write</access>
16174 <resetValue>0x00000000</resetValue>
16175 <fields>
16176 <field>
16177 <name>CNT_H</name>
16178 <description>High counter value</description>
16179 <bitOffset>16</bitOffset>
16180 <bitWidth>16</bitWidth>
16181 </field>
16182 <field>
16183 <name>CNT_L</name>
16184 <description>Low counter value</description>
16185 <bitOffset>0</bitOffset>
16186 <bitWidth>16</bitWidth>
16187 </field>
16188 </fields>
16189 </register>
16190 <register>
16191 <name>PSC</name>
16192 <displayName>PSC</displayName>
16193 <description>prescaler</description>
16194 <addressOffset>0x28</addressOffset>
16195 <size>0x20</size>
16196 <access>read-write</access>
16197 <resetValue>0x0000</resetValue>
16198 <fields>
16199 <field>
16200 <name>PSC</name>
16201 <description>Prescaler value</description>
16202 <bitOffset>0</bitOffset>
16203 <bitWidth>16</bitWidth>
16204 </field>
16205 </fields>
16206 </register>
16207 <register>
16208 <name>ARR</name>
16209 <displayName>ARR</displayName>
16210 <description>auto-reload register</description>
16211 <addressOffset>0x2C</addressOffset>
16212 <size>0x20</size>
16213 <access>read-write</access>
16214 <resetValue>0x00000000</resetValue>
16215 <fields>
16216 <field>
16217 <name>ARR_H</name>
16218 <description>High Auto-reload value</description>
16219 <bitOffset>16</bitOffset>
16220 <bitWidth>16</bitWidth>
16221 </field>
16222 <field>
16223 <name>ARR_L</name>
16224 <description>Low Auto-reload value</description>
16225 <bitOffset>0</bitOffset>
16226 <bitWidth>16</bitWidth>
16227 </field>
16228 </fields>
16229 </register>
16230 <register>
16231 <name>CCR1</name>
16232 <displayName>CCR1</displayName>
16233 <description>capture/compare register 1</description>
16234 <addressOffset>0x34</addressOffset>
16235 <size>0x20</size>
16236 <access>read-write</access>
16237 <resetValue>0x00000000</resetValue>
16238 <fields>
16239 <field>
16240 <name>CCR1_H</name>
16241 <description>High Capture/Compare 1
16242 value</description>
16243 <bitOffset>16</bitOffset>
16244 <bitWidth>16</bitWidth>
16245 </field>
16246 <field>
16247 <name>CCR1_L</name>
16248 <description>Low Capture/Compare 1
16249 value</description>
16250 <bitOffset>0</bitOffset>
16251 <bitWidth>16</bitWidth>
16252 </field>
16253 </fields>
16254 </register>
16255 <register>
16256 <name>CCR2</name>
16257 <displayName>CCR2</displayName>
16258 <description>capture/compare register 2</description>
16259 <addressOffset>0x38</addressOffset>
16260 <size>0x20</size>
16261 <access>read-write</access>
16262 <resetValue>0x00000000</resetValue>
16263 <fields>
16264 <field>
16265 <name>CCR2_H</name>
16266 <description>High Capture/Compare 2
16267 value</description>
16268 <bitOffset>16</bitOffset>
16269 <bitWidth>16</bitWidth>
16270 </field>
16271 <field>
16272 <name>CCR2_L</name>
16273 <description>Low Capture/Compare 2
16274 value</description>
16275 <bitOffset>0</bitOffset>
16276 <bitWidth>16</bitWidth>
16277 </field>
16278 </fields>
16279 </register>
16280 <register>
16281 <name>CCR3</name>
16282 <displayName>CCR3</displayName>
16283 <description>capture/compare register 3</description>
16284 <addressOffset>0x3C</addressOffset>
16285 <size>0x20</size>
16286 <access>read-write</access>
16287 <resetValue>0x00000000</resetValue>
16288 <fields>
16289 <field>
16290 <name>CCR3_H</name>
16291 <description>High Capture/Compare value</description>
16292 <bitOffset>16</bitOffset>
16293 <bitWidth>16</bitWidth>
16294 </field>
16295 <field>
16296 <name>CCR3_L</name>
16297 <description>Low Capture/Compare value</description>
16298 <bitOffset>0</bitOffset>
16299 <bitWidth>16</bitWidth>
16300 </field>
16301 </fields>
16302 </register>
16303 <register>
16304 <name>CCR4</name>
16305 <displayName>CCR4</displayName>
16306 <description>capture/compare register 4</description>
16307 <addressOffset>0x40</addressOffset>
16308 <size>0x20</size>
16309 <access>read-write</access>
16310 <resetValue>0x00000000</resetValue>
16311 <fields>
16312 <field>
16313 <name>CCR4_H</name>
16314 <description>High Capture/Compare value</description>
16315 <bitOffset>16</bitOffset>
16316 <bitWidth>16</bitWidth>
16317 </field>
16318 <field>
16319 <name>CCR4_L</name>
16320 <description>Low Capture/Compare value</description>
16321 <bitOffset>0</bitOffset>
16322 <bitWidth>16</bitWidth>
16323 </field>
16324 </fields>
16325 </register>
16326 <register>
16327 <name>DCR</name>
16328 <displayName>DCR</displayName>
16329 <description>DMA control register</description>
16330 <addressOffset>0x48</addressOffset>
16331 <size>0x20</size>
16332 <access>read-write</access>
16333 <resetValue>0x0000</resetValue>
16334 <fields>
16335 <field>
16336 <name>DBL</name>
16337 <description>DMA burst length</description>
16338 <bitOffset>8</bitOffset>
16339 <bitWidth>5</bitWidth>
16340 </field>
16341 <field>
16342 <name>DBA</name>
16343 <description>DMA base address</description>
16344 <bitOffset>0</bitOffset>
16345 <bitWidth>5</bitWidth>
16346 </field>
16347 </fields>
16348 </register>
16349 <register>
16350 <name>DMAR</name>
16351 <displayName>DMAR</displayName>
16352 <description>DMA address for full transfer</description>
16353 <addressOffset>0x4C</addressOffset>
16354 <size>0x20</size>
16355 <access>read-write</access>
16356 <resetValue>0x0000</resetValue>
16357 <fields>
16358 <field>
16359 <name>DMAB</name>
16360 <description>DMA register for burst
16361 accesses</description>
16362 <bitOffset>0</bitOffset>
16363 <bitWidth>16</bitWidth>
16364 </field>
16365 </fields>
16366 </register>
16367 <register>
16368 <name>OR</name>
16369 <displayName>OR</displayName>
16370 <description>TIM5 option register</description>
16371 <addressOffset>0x50</addressOffset>
16372 <size>0x20</size>
16373 <access>read-write</access>
16374 <resetValue>0x0000</resetValue>
16375 <fields>
16376 <field>
16377 <name>IT4_RMP</name>
16378 <description>Timer Input 4 remap</description>
16379 <bitOffset>6</bitOffset>
16380 <bitWidth>2</bitWidth>
16381 </field>
16382 </fields>
16383 </register>
16384 </registers>
16385 </peripheral>
16386 <peripheral>
16387 <name>TIM9</name>
16388 <description>General purpose timers</description>
16389 <groupName>TIM</groupName>
16390 <baseAddress>0x40014000</baseAddress>
16391 <addressBlock>
16392 <offset>0x0</offset>
16393 <size>0x400</size>
16394 <usage>registers</usage>
16395 </addressBlock>
16396 <registers>
16397 <register>
16398 <name>CR1</name>
16399 <displayName>CR1</displayName>
16400 <description>control register 1</description>
16401 <addressOffset>0x0</addressOffset>
16402 <size>0x20</size>
16403 <access>read-write</access>
16404 <resetValue>0x0000</resetValue>
16405 <fields>
16406 <field>
16407 <name>CKD</name>
16408 <description>Clock division</description>
16409 <bitOffset>8</bitOffset>
16410 <bitWidth>2</bitWidth>
16411 </field>
16412 <field>
16413 <name>ARPE</name>
16414 <description>Auto-reload preload enable</description>
16415 <bitOffset>7</bitOffset>
16416 <bitWidth>1</bitWidth>
16417 </field>
16418 <field>
16419 <name>OPM</name>
16420 <description>One-pulse mode</description>
16421 <bitOffset>3</bitOffset>
16422 <bitWidth>1</bitWidth>
16423 </field>
16424 <field>
16425 <name>URS</name>
16426 <description>Update request source</description>
16427 <bitOffset>2</bitOffset>
16428 <bitWidth>1</bitWidth>
16429 </field>
16430 <field>
16431 <name>UDIS</name>
16432 <description>Update disable</description>
16433 <bitOffset>1</bitOffset>
16434 <bitWidth>1</bitWidth>
16435 </field>
16436 <field>
16437 <name>CEN</name>
16438 <description>Counter enable</description>
16439 <bitOffset>0</bitOffset>
16440 <bitWidth>1</bitWidth>
16441 </field>
16442 </fields>
16443 </register>
16444 <register>
16445 <name>CR2</name>
16446 <displayName>CR2</displayName>
16447 <description>control register 2</description>
16448 <addressOffset>0x4</addressOffset>
16449 <size>0x20</size>
16450 <access>read-write</access>
16451 <resetValue>0x0000</resetValue>
16452 <fields>
16453 <field>
16454 <name>MMS</name>
16455 <description>Master mode selection</description>
16456 <bitOffset>4</bitOffset>
16457 <bitWidth>3</bitWidth>
16458 </field>
16459 </fields>
16460 </register>
16461 <register>
16462 <name>SMCR</name>
16463 <displayName>SMCR</displayName>
16464 <description>slave mode control register</description>
16465 <addressOffset>0x8</addressOffset>
16466 <size>0x20</size>
16467 <access>read-write</access>
16468 <resetValue>0x0000</resetValue>
16469 <fields>
16470 <field>
16471 <name>MSM</name>
16472 <description>Master/Slave mode</description>
16473 <bitOffset>7</bitOffset>
16474 <bitWidth>1</bitWidth>
16475 </field>
16476 <field>
16477 <name>TS</name>
16478 <description>Trigger selection</description>
16479 <bitOffset>4</bitOffset>
16480 <bitWidth>3</bitWidth>
16481 </field>
16482 <field>
16483 <name>SMS</name>
16484 <description>Slave mode selection</description>
16485 <bitOffset>0</bitOffset>
16486 <bitWidth>3</bitWidth>
16487 </field>
16488 </fields>
16489 </register>
16490 <register>
16491 <name>DIER</name>
16492 <displayName>DIER</displayName>
16493 <description>DMA/Interrupt enable register</description>
16494 <addressOffset>0xC</addressOffset>
16495 <size>0x20</size>
16496 <access>read-write</access>
16497 <resetValue>0x0000</resetValue>
16498 <fields>
16499 <field>
16500 <name>TIE</name>
16501 <description>Trigger interrupt enable</description>
16502 <bitOffset>6</bitOffset>
16503 <bitWidth>1</bitWidth>
16504 </field>
16505 <field>
16506 <name>CC2IE</name>
16507 <description>Capture/Compare 2 interrupt
16508 enable</description>
16509 <bitOffset>2</bitOffset>
16510 <bitWidth>1</bitWidth>
16511 </field>
16512 <field>
16513 <name>CC1IE</name>
16514 <description>Capture/Compare 1 interrupt
16515 enable</description>
16516 <bitOffset>1</bitOffset>
16517 <bitWidth>1</bitWidth>
16518 </field>
16519 <field>
16520 <name>UIE</name>
16521 <description>Update interrupt enable</description>
16522 <bitOffset>0</bitOffset>
16523 <bitWidth>1</bitWidth>
16524 </field>
16525 </fields>
16526 </register>
16527 <register>
16528 <name>SR</name>
16529 <displayName>SR</displayName>
16530 <description>status register</description>
16531 <addressOffset>0x10</addressOffset>
16532 <size>0x20</size>
16533 <access>read-write</access>
16534 <resetValue>0x0000</resetValue>
16535 <fields>
16536 <field>
16537 <name>CC2OF</name>
16538 <description>Capture/compare 2 overcapture
16539 flag</description>
16540 <bitOffset>10</bitOffset>
16541 <bitWidth>1</bitWidth>
16542 </field>
16543 <field>
16544 <name>CC1OF</name>
16545 <description>Capture/Compare 1 overcapture
16546 flag</description>
16547 <bitOffset>9</bitOffset>
16548 <bitWidth>1</bitWidth>
16549 </field>
16550 <field>
16551 <name>TIF</name>
16552 <description>Trigger interrupt flag</description>
16553 <bitOffset>6</bitOffset>
16554 <bitWidth>1</bitWidth>
16555 </field>
16556 <field>
16557 <name>CC2IF</name>
16558 <description>Capture/Compare 2 interrupt
16559 flag</description>
16560 <bitOffset>2</bitOffset>
16561 <bitWidth>1</bitWidth>
16562 </field>
16563 <field>
16564 <name>CC1IF</name>
16565 <description>Capture/compare 1 interrupt
16566 flag</description>
16567 <bitOffset>1</bitOffset>
16568 <bitWidth>1</bitWidth>
16569 </field>
16570 <field>
16571 <name>UIF</name>
16572 <description>Update interrupt flag</description>
16573 <bitOffset>0</bitOffset>
16574 <bitWidth>1</bitWidth>
16575 </field>
16576 </fields>
16577 </register>
16578 <register>
16579 <name>EGR</name>
16580 <displayName>EGR</displayName>
16581 <description>event generation register</description>
16582 <addressOffset>0x14</addressOffset>
16583 <size>0x20</size>
16584 <access>write-only</access>
16585 <resetValue>0x0000</resetValue>
16586 <fields>
16587 <field>
16588 <name>TG</name>
16589 <description>Trigger generation</description>
16590 <bitOffset>6</bitOffset>
16591 <bitWidth>1</bitWidth>
16592 </field>
16593 <field>
16594 <name>CC2G</name>
16595 <description>Capture/compare 2
16596 generation</description>
16597 <bitOffset>2</bitOffset>
16598 <bitWidth>1</bitWidth>
16599 </field>
16600 <field>
16601 <name>CC1G</name>
16602 <description>Capture/compare 1
16603 generation</description>
16604 <bitOffset>1</bitOffset>
16605 <bitWidth>1</bitWidth>
16606 </field>
16607 <field>
16608 <name>UG</name>
16609 <description>Update generation</description>
16610 <bitOffset>0</bitOffset>
16611 <bitWidth>1</bitWidth>
16612 </field>
16613 </fields>
16614 </register>
16615 <register>
16616 <name>CCMR1_Output</name>
16617 <displayName>CCMR1_Output</displayName>
16618 <description>capture/compare mode register 1 (output
16619 mode)</description>
16620 <addressOffset>0x18</addressOffset>
16621 <size>0x20</size>
16622 <access>read-write</access>
16623 <resetValue>0x00000000</resetValue>
16624 <fields>
16625 <field>
16626 <name>OC2M</name>
16627 <description>Output Compare 2 mode</description>
16628 <bitOffset>12</bitOffset>
16629 <bitWidth>3</bitWidth>
16630 </field>
16631 <field>
16632 <name>OC2PE</name>
16633 <description>Output Compare 2 preload
16634 enable</description>
16635 <bitOffset>11</bitOffset>
16636 <bitWidth>1</bitWidth>
16637 </field>
16638 <field>
16639 <name>OC2FE</name>
16640 <description>Output Compare 2 fast
16641 enable</description>
16642 <bitOffset>10</bitOffset>
16643 <bitWidth>1</bitWidth>
16644 </field>
16645 <field>
16646 <name>CC2S</name>
16647 <description>Capture/Compare 2
16648 selection</description>
16649 <bitOffset>8</bitOffset>
16650 <bitWidth>2</bitWidth>
16651 </field>
16652 <field>
16653 <name>OC1M</name>
16654 <description>Output Compare 1 mode</description>
16655 <bitOffset>4</bitOffset>
16656 <bitWidth>3</bitWidth>
16657 </field>
16658 <field>
16659 <name>OC1PE</name>
16660 <description>Output Compare 1 preload
16661 enable</description>
16662 <bitOffset>3</bitOffset>
16663 <bitWidth>1</bitWidth>
16664 </field>
16665 <field>
16666 <name>OC1FE</name>
16667 <description>Output Compare 1 fast
16668 enable</description>
16669 <bitOffset>2</bitOffset>
16670 <bitWidth>1</bitWidth>
16671 </field>
16672 <field>
16673 <name>CC1S</name>
16674 <description>Capture/Compare 1
16675 selection</description>
16676 <bitOffset>0</bitOffset>
16677 <bitWidth>2</bitWidth>
16678 </field>
16679 </fields>
16680 </register>
16681 <register>
16682 <name>CCMR1_Input</name>
16683 <displayName>CCMR1_Input</displayName>
16684 <description>capture/compare mode register 1 (input
16685 mode)</description>
16686 <alternateRegister>CCMR1_Output</alternateRegister>
16687 <addressOffset>0x18</addressOffset>
16688 <size>0x20</size>
16689 <access>read-write</access>
16690 <resetValue>0x00000000</resetValue>
16691 <fields>
16692 <field>
16693 <name>IC2F</name>
16694 <description>Input capture 2 filter</description>
16695 <bitOffset>12</bitOffset>
16696 <bitWidth>3</bitWidth>
16697 </field>
16698 <field>
16699 <name>IC2PCS</name>
16700 <description>Input capture 2 prescaler</description>
16701 <bitOffset>10</bitOffset>
16702 <bitWidth>2</bitWidth>
16703 </field>
16704 <field>
16705 <name>CC2S</name>
16706 <description>Capture/Compare 2
16707 selection</description>
16708 <bitOffset>8</bitOffset>
16709 <bitWidth>2</bitWidth>
16710 </field>
16711 <field>
16712 <name>IC1F</name>
16713 <description>Input capture 1 filter</description>
16714 <bitOffset>4</bitOffset>
16715 <bitWidth>3</bitWidth>
16716 </field>
16717 <field>
16718 <name>ICPCS</name>
16719 <description>Input capture 1 prescaler</description>
16720 <bitOffset>2</bitOffset>
16721 <bitWidth>2</bitWidth>
16722 </field>
16723 <field>
16724 <name>CC1S</name>
16725 <description>Capture/Compare 1
16726 selection</description>
16727 <bitOffset>0</bitOffset>
16728 <bitWidth>2</bitWidth>
16729 </field>
16730 </fields>
16731 </register>
16732 <register>
16733 <name>CCER</name>
16734 <displayName>CCER</displayName>
16735 <description>capture/compare enable
16736 register</description>
16737 <addressOffset>0x20</addressOffset>
16738 <size>0x20</size>
16739 <access>read-write</access>
16740 <resetValue>0x0000</resetValue>
16741 <fields>
16742 <field>
16743 <name>CC2NP</name>
16744 <description>Capture/Compare 2 output
16745 Polarity</description>
16746 <bitOffset>7</bitOffset>
16747 <bitWidth>1</bitWidth>
16748 </field>
16749 <field>
16750 <name>CC2P</name>
16751 <description>Capture/Compare 2 output
16752 Polarity</description>
16753 <bitOffset>5</bitOffset>
16754 <bitWidth>1</bitWidth>
16755 </field>
16756 <field>
16757 <name>CC2E</name>
16758 <description>Capture/Compare 2 output
16759 enable</description>
16760 <bitOffset>4</bitOffset>
16761 <bitWidth>1</bitWidth>
16762 </field>
16763 <field>
16764 <name>CC1NP</name>
16765 <description>Capture/Compare 1 output
16766 Polarity</description>
16767 <bitOffset>3</bitOffset>
16768 <bitWidth>1</bitWidth>
16769 </field>
16770 <field>
16771 <name>CC1P</name>
16772 <description>Capture/Compare 1 output
16773 Polarity</description>
16774 <bitOffset>1</bitOffset>
16775 <bitWidth>1</bitWidth>
16776 </field>
16777 <field>
16778 <name>CC1E</name>
16779 <description>Capture/Compare 1 output
16780 enable</description>
16781 <bitOffset>0</bitOffset>
16782 <bitWidth>1</bitWidth>
16783 </field>
16784 </fields>
16785 </register>
16786 <register>
16787 <name>CNT</name>
16788 <displayName>CNT</displayName>
16789 <description>counter</description>
16790 <addressOffset>0x24</addressOffset>
16791 <size>0x20</size>
16792 <access>read-write</access>
16793 <resetValue>0x00000000</resetValue>
16794 <fields>
16795 <field>
16796 <name>CNT</name>
16797 <description>counter value</description>
16798 <bitOffset>0</bitOffset>
16799 <bitWidth>16</bitWidth>
16800 </field>
16801 </fields>
16802 </register>
16803 <register>
16804 <name>PSC</name>
16805 <displayName>PSC</displayName>
16806 <description>prescaler</description>
16807 <addressOffset>0x28</addressOffset>
16808 <size>0x20</size>
16809 <access>read-write</access>
16810 <resetValue>0x0000</resetValue>
16811 <fields>
16812 <field>
16813 <name>PSC</name>
16814 <description>Prescaler value</description>
16815 <bitOffset>0</bitOffset>
16816 <bitWidth>16</bitWidth>
16817 </field>
16818 </fields>
16819 </register>
16820 <register>
16821 <name>ARR</name>
16822 <displayName>ARR</displayName>
16823 <description>auto-reload register</description>
16824 <addressOffset>0x2C</addressOffset>
16825 <size>0x20</size>
16826 <access>read-write</access>
16827 <resetValue>0x00000000</resetValue>
16828 <fields>
16829 <field>
16830 <name>ARR</name>
16831 <description>Auto-reload value</description>
16832 <bitOffset>0</bitOffset>
16833 <bitWidth>16</bitWidth>
16834 </field>
16835 </fields>
16836 </register>
16837 <register>
16838 <name>CCR1</name>
16839 <displayName>CCR1</displayName>
16840 <description>capture/compare register 1</description>
16841 <addressOffset>0x34</addressOffset>
16842 <size>0x20</size>
16843 <access>read-write</access>
16844 <resetValue>0x00000000</resetValue>
16845 <fields>
16846 <field>
16847 <name>CCR1</name>
16848 <description>Capture/Compare 1 value</description>
16849 <bitOffset>0</bitOffset>
16850 <bitWidth>16</bitWidth>
16851 </field>
16852 </fields>
16853 </register>
16854 <register>
16855 <name>CCR2</name>
16856 <displayName>CCR2</displayName>
16857 <description>capture/compare register 2</description>
16858 <addressOffset>0x38</addressOffset>
16859 <size>0x20</size>
16860 <access>read-write</access>
16861 <resetValue>0x00000000</resetValue>
16862 <fields>
16863 <field>
16864 <name>CCR2</name>
16865 <description>Capture/Compare 2 value</description>
16866 <bitOffset>0</bitOffset>
16867 <bitWidth>16</bitWidth>
16868 </field>
16869 </fields>
16870 </register>
16871 </registers>
16872 </peripheral>
16873 <peripheral>
16874 <name>USART1</name>
16875 <description>Universal synchronous asynchronous receiver
16876 transmitter</description>
16877 <groupName>USART</groupName>
16878 <baseAddress>0x40011000</baseAddress>
16879 <addressBlock>
16880 <offset>0x0</offset>
16881 <size>0x400</size>
16882 <usage>registers</usage>
16883 </addressBlock>
16884 <interrupt>
16885 <name>OTG_FS_WKUP</name>
16886 <description>USB On-The-Go FS Wakeup through EXTI line
16887 interrupt</description>
16888 <value>42</value>
16889 </interrupt>
16890 <interrupt>
16891 <name>OTG_FS</name>
16892 <description>USB On The Go FS global
16893 interrupt</description>
16894 <value>67</value>
16895 </interrupt>
16896 <registers>
16897 <register>
16898 <name>SR</name>
16899 <displayName>SR</displayName>
16900 <description>Status register</description>
16901 <addressOffset>0x0</addressOffset>
16902 <size>0x20</size>
16903 <resetValue>0x00C00000</resetValue>
16904 <fields>
16905 <field>
16906 <name>CTS</name>
16907 <description>CTS flag</description>
16908 <bitOffset>9</bitOffset>
16909 <bitWidth>1</bitWidth>
16910 <access>read-write</access>
16911 </field>
16912 <field>
16913 <name>LBD</name>
16914 <description>LIN break detection flag</description>
16915 <bitOffset>8</bitOffset>
16916 <bitWidth>1</bitWidth>
16917 <access>read-write</access>
16918 </field>
16919 <field>
16920 <name>TXE</name>
16921 <description>Transmit data register
16922 empty</description>
16923 <bitOffset>7</bitOffset>
16924 <bitWidth>1</bitWidth>
16925 <access>read-only</access>
16926 </field>
16927 <field>
16928 <name>TC</name>
16929 <description>Transmission complete</description>
16930 <bitOffset>6</bitOffset>
16931 <bitWidth>1</bitWidth>
16932 <access>read-write</access>
16933 </field>
16934 <field>
16935 <name>RXNE</name>
16936 <description>Read data register not
16937 empty</description>
16938 <bitOffset>5</bitOffset>
16939 <bitWidth>1</bitWidth>
16940 <access>read-write</access>
16941 </field>
16942 <field>
16943 <name>IDLE</name>
16944 <description>IDLE line detected</description>
16945 <bitOffset>4</bitOffset>
16946 <bitWidth>1</bitWidth>
16947 <access>read-only</access>
16948 </field>
16949 <field>
16950 <name>ORE</name>
16951 <description>Overrun error</description>
16952 <bitOffset>3</bitOffset>
16953 <bitWidth>1</bitWidth>
16954 <access>read-only</access>
16955 </field>
16956 <field>
16957 <name>NF</name>
16958 <description>Noise detected flag</description>
16959 <bitOffset>2</bitOffset>
16960 <bitWidth>1</bitWidth>
16961 <access>read-only</access>
16962 </field>
16963 <field>
16964 <name>FE</name>
16965 <description>Framing error</description>
16966 <bitOffset>1</bitOffset>
16967 <bitWidth>1</bitWidth>
16968 <access>read-only</access>
16969 </field>
16970 <field>
16971 <name>PE</name>
16972 <description>Parity error</description>
16973 <bitOffset>0</bitOffset>
16974 <bitWidth>1</bitWidth>
16975 <access>read-only</access>
16976 </field>
16977 </fields>
16978 </register>
16979 <register>
16980 <name>DR</name>
16981 <displayName>DR</displayName>
16982 <description>Data register</description>
16983 <addressOffset>0x4</addressOffset>
16984 <size>0x20</size>
16985 <access>read-write</access>
16986 <resetValue>0x00000000</resetValue>
16987 <fields>
16988 <field>
16989 <name>DR</name>
16990 <description>Data value</description>
16991 <bitOffset>0</bitOffset>
16992 <bitWidth>9</bitWidth>
16993 </field>
16994 </fields>
16995 </register>
16996 <register>
16997 <name>BRR</name>
16998 <displayName>BRR</displayName>
16999 <description>Baud rate register</description>
17000 <addressOffset>0x8</addressOffset>
17001 <size>0x20</size>
17002 <access>read-write</access>
17003 <resetValue>0x0000</resetValue>
17004 <fields>
17005 <field>
17006 <name>DIV_Mantissa</name>
17007 <description>mantissa of USARTDIV</description>
17008 <bitOffset>4</bitOffset>
17009 <bitWidth>12</bitWidth>
17010 </field>
17011 <field>
17012 <name>DIV_Fraction</name>
17013 <description>fraction of USARTDIV</description>
17014 <bitOffset>0</bitOffset>
17015 <bitWidth>4</bitWidth>
17016 </field>
17017 </fields>
17018 </register>
17019 <register>
17020 <name>CR1</name>
17021 <displayName>CR1</displayName>
17022 <description>Control register 1</description>
17023 <addressOffset>0xC</addressOffset>
17024 <size>0x20</size>
17025 <access>read-write</access>
17026 <resetValue>0x0000</resetValue>
17027 <fields>
17028 <field>
17029 <name>OVER8</name>
17030 <description>Oversampling mode</description>
17031 <bitOffset>15</bitOffset>
17032 <bitWidth>1</bitWidth>
17033 </field>
17034 <field>
17035 <name>UE</name>
17036 <description>USART enable</description>
17037 <bitOffset>13</bitOffset>
17038 <bitWidth>1</bitWidth>
17039 </field>
17040 <field>
17041 <name>M</name>
17042 <description>Word length</description>
17043 <bitOffset>12</bitOffset>
17044 <bitWidth>1</bitWidth>
17045 </field>
17046 <field>
17047 <name>WAKE</name>
17048 <description>Wakeup method</description>
17049 <bitOffset>11</bitOffset>
17050 <bitWidth>1</bitWidth>
17051 </field>
17052 <field>
17053 <name>PCE</name>
17054 <description>Parity control enable</description>
17055 <bitOffset>10</bitOffset>
17056 <bitWidth>1</bitWidth>
17057 </field>
17058 <field>
17059 <name>PS</name>
17060 <description>Parity selection</description>
17061 <bitOffset>9</bitOffset>
17062 <bitWidth>1</bitWidth>
17063 </field>
17064 <field>
17065 <name>PEIE</name>
17066 <description>PE interrupt enable</description>
17067 <bitOffset>8</bitOffset>
17068 <bitWidth>1</bitWidth>
17069 </field>
17070 <field>
17071 <name>TXEIE</name>
17072 <description>TXE interrupt enable</description>
17073 <bitOffset>7</bitOffset>
17074 <bitWidth>1</bitWidth>
17075 </field>
17076 <field>
17077 <name>TCIE</name>
17078 <description>Transmission complete interrupt
17079 enable</description>
17080 <bitOffset>6</bitOffset>
17081 <bitWidth>1</bitWidth>
17082 </field>
17083 <field>
17084 <name>RXNEIE</name>
17085 <description>RXNE interrupt enable</description>
17086 <bitOffset>5</bitOffset>
17087 <bitWidth>1</bitWidth>
17088 </field>
17089 <field>
17090 <name>IDLEIE</name>
17091 <description>IDLE interrupt enable</description>
17092 <bitOffset>4</bitOffset>
17093 <bitWidth>1</bitWidth>
17094 </field>
17095 <field>
17096 <name>TE</name>
17097 <description>Transmitter enable</description>
17098 <bitOffset>3</bitOffset>
17099 <bitWidth>1</bitWidth>
17100 </field>
17101 <field>
17102 <name>RE</name>
17103 <description>Receiver enable</description>
17104 <bitOffset>2</bitOffset>
17105 <bitWidth>1</bitWidth>
17106 </field>
17107 <field>
17108 <name>RWU</name>
17109 <description>Receiver wakeup</description>
17110 <bitOffset>1</bitOffset>
17111 <bitWidth>1</bitWidth>
17112 </field>
17113 <field>
17114 <name>SBK</name>
17115 <description>Send break</description>
17116 <bitOffset>0</bitOffset>
17117 <bitWidth>1</bitWidth>
17118 </field>
17119 </fields>
17120 </register>
17121 <register>
17122 <name>CR2</name>
17123 <displayName>CR2</displayName>
17124 <description>Control register 2</description>
17125 <addressOffset>0x10</addressOffset>
17126 <size>0x20</size>
17127 <access>read-write</access>
17128 <resetValue>0x0000</resetValue>
17129 <fields>
17130 <field>
17131 <name>LINEN</name>
17132 <description>LIN mode enable</description>
17133 <bitOffset>14</bitOffset>
17134 <bitWidth>1</bitWidth>
17135 </field>
17136 <field>
17137 <name>STOP</name>
17138 <description>STOP bits</description>
17139 <bitOffset>12</bitOffset>
17140 <bitWidth>2</bitWidth>
17141 </field>
17142 <field>
17143 <name>CLKEN</name>
17144 <description>Clock enable</description>
17145 <bitOffset>11</bitOffset>
17146 <bitWidth>1</bitWidth>
17147 </field>
17148 <field>
17149 <name>CPOL</name>
17150 <description>Clock polarity</description>
17151 <bitOffset>10</bitOffset>
17152 <bitWidth>1</bitWidth>
17153 </field>
17154 <field>
17155 <name>CPHA</name>
17156 <description>Clock phase</description>
17157 <bitOffset>9</bitOffset>
17158 <bitWidth>1</bitWidth>
17159 </field>
17160 <field>
17161 <name>LBCL</name>
17162 <description>Last bit clock pulse</description>
17163 <bitOffset>8</bitOffset>
17164 <bitWidth>1</bitWidth>
17165 </field>
17166 <field>
17167 <name>LBDIE</name>
17168 <description>LIN break detection interrupt
17169 enable</description>
17170 <bitOffset>6</bitOffset>
17171 <bitWidth>1</bitWidth>
17172 </field>
17173 <field>
17174 <name>LBDL</name>
17175 <description>lin break detection length</description>
17176 <bitOffset>5</bitOffset>
17177 <bitWidth>1</bitWidth>
17178 </field>
17179 <field>
17180 <name>ADD</name>
17181 <description>Address of the USART node</description>
17182 <bitOffset>0</bitOffset>
17183 <bitWidth>4</bitWidth>
17184 </field>
17185 </fields>
17186 </register>
17187 <register>
17188 <name>CR3</name>
17189 <displayName>CR3</displayName>
17190 <description>Control register 3</description>
17191 <addressOffset>0x14</addressOffset>
17192 <size>0x20</size>
17193 <access>read-write</access>
17194 <resetValue>0x0000</resetValue>
17195 <fields>
17196 <field>
17197 <name>ONEBIT</name>
17198 <description>One sample bit method
17199 enable</description>
17200 <bitOffset>11</bitOffset>
17201 <bitWidth>1</bitWidth>
17202 </field>
17203 <field>
17204 <name>CTSIE</name>
17205 <description>CTS interrupt enable</description>
17206 <bitOffset>10</bitOffset>
17207 <bitWidth>1</bitWidth>
17208 </field>
17209 <field>
17210 <name>CTSE</name>
17211 <description>CTS enable</description>
17212 <bitOffset>9</bitOffset>
17213 <bitWidth>1</bitWidth>
17214 </field>
17215 <field>
17216 <name>RTSE</name>
17217 <description>RTS enable</description>
17218 <bitOffset>8</bitOffset>
17219 <bitWidth>1</bitWidth>
17220 </field>
17221 <field>
17222 <name>DMAT</name>
17223 <description>DMA enable transmitter</description>
17224 <bitOffset>7</bitOffset>
17225 <bitWidth>1</bitWidth>
17226 </field>
17227 <field>
17228 <name>DMAR</name>
17229 <description>DMA enable receiver</description>
17230 <bitOffset>6</bitOffset>
17231 <bitWidth>1</bitWidth>
17232 </field>
17233 <field>
17234 <name>SCEN</name>
17235 <description>Smartcard mode enable</description>
17236 <bitOffset>5</bitOffset>
17237 <bitWidth>1</bitWidth>
17238 </field>
17239 <field>
17240 <name>NACK</name>
17241 <description>Smartcard NACK enable</description>
17242 <bitOffset>4</bitOffset>
17243 <bitWidth>1</bitWidth>
17244 </field>
17245 <field>
17246 <name>HDSEL</name>
17247 <description>Half-duplex selection</description>
17248 <bitOffset>3</bitOffset>
17249 <bitWidth>1</bitWidth>
17250 </field>
17251 <field>
17252 <name>IRLP</name>
17253 <description>IrDA low-power</description>
17254 <bitOffset>2</bitOffset>
17255 <bitWidth>1</bitWidth>
17256 </field>
17257 <field>
17258 <name>IREN</name>
17259 <description>IrDA mode enable</description>
17260 <bitOffset>1</bitOffset>
17261 <bitWidth>1</bitWidth>
17262 </field>
17263 <field>
17264 <name>EIE</name>
17265 <description>Error interrupt enable</description>
17266 <bitOffset>0</bitOffset>
17267 <bitWidth>1</bitWidth>
17268 </field>
17269 </fields>
17270 </register>
17271 <register>
17272 <name>GTPR</name>
17273 <displayName>GTPR</displayName>
17274 <description>Guard time and prescaler
17275 register</description>
17276 <addressOffset>0x18</addressOffset>
17277 <size>0x20</size>
17278 <access>read-write</access>
17279 <resetValue>0x0000</resetValue>
17280 <fields>
17281 <field>
17282 <name>GT</name>
17283 <description>Guard time value</description>
17284 <bitOffset>8</bitOffset>
17285 <bitWidth>8</bitWidth>
17286 </field>
17287 <field>
17288 <name>PSC</name>
17289 <description>Prescaler value</description>
17290 <bitOffset>0</bitOffset>
17291 <bitWidth>8</bitWidth>
17292 </field>
17293 </fields>
17294 </register>
17295 </registers>
17296 </peripheral>
17297 <peripheral derivedFrom="USART1">
17298 <name>USART2</name>
17299 <baseAddress>0x40004400</baseAddress>
17300 </peripheral>
17301 <peripheral derivedFrom="USART1">
17302 <name>USART6</name>
17303 <baseAddress>0x40011400</baseAddress>
17304 </peripheral>
17305 <peripheral>
17306 <name>WWDG</name>
17307 <description>Window watchdog</description>
17308 <groupName>WWDG</groupName>
17309 <baseAddress>0x40002C00</baseAddress>
17310 <addressBlock>
17311 <offset>0x0</offset>
17312 <size>0x400</size>
17313 <usage>registers</usage>
17314 </addressBlock>
17315 <interrupt>
17316 <name>PVD</name>
17317 <description>PVD through EXTI line detection
17318 interrupt</description>
17319 <value>1</value>
17320 </interrupt>
17321 <registers>
17322 <register>
17323 <name>CR</name>
17324 <displayName>CR</displayName>
17325 <description>Control register</description>
17326 <addressOffset>0x0</addressOffset>
17327 <size>0x20</size>
17328 <access>read-write</access>
17329 <resetValue>0x7F</resetValue>
17330 <fields>
17331 <field>
17332 <name>WDGA</name>
17333 <description>Activation bit</description>
17334 <bitOffset>7</bitOffset>
17335 <bitWidth>1</bitWidth>
17336 </field>
17337 <field>
17338 <name>T</name>
17339 <description>7-bit counter (MSB to LSB)</description>
17340 <bitOffset>0</bitOffset>
17341 <bitWidth>7</bitWidth>
17342 </field>
17343 </fields>
17344 </register>
17345 <register>
17346 <name>CFR</name>
17347 <displayName>CFR</displayName>
17348 <description>Configuration register</description>
17349 <addressOffset>0x4</addressOffset>
17350 <size>0x20</size>
17351 <access>read-write</access>
17352 <resetValue>0x7F</resetValue>
17353 <fields>
17354 <field>
17355 <name>EWI</name>
17356 <description>Early wakeup interrupt</description>
17357 <bitOffset>9</bitOffset>
17358 <bitWidth>1</bitWidth>
17359 </field>
17360 <field>
17361 <name>WDGTB1</name>
17362 <description>Timer base</description>
17363 <bitOffset>8</bitOffset>
17364 <bitWidth>1</bitWidth>
17365 </field>
17366 <field>
17367 <name>WDGTB0</name>
17368 <description>Timer base</description>
17369 <bitOffset>7</bitOffset>
17370 <bitWidth>1</bitWidth>
17371 </field>
17372 <field>
17373 <name>W</name>
17374 <description>7-bit window value</description>
17375 <bitOffset>0</bitOffset>
17376 <bitWidth>7</bitWidth>
17377 </field>
17378 </fields>
17379 </register>
17380 <register>
17381 <name>SR</name>
17382 <displayName>SR</displayName>
17383 <description>Status register</description>
17384 <addressOffset>0x8</addressOffset>
17385 <size>0x20</size>
17386 <access>read-write</access>
17387 <resetValue>0x00</resetValue>
17388 <fields>
17389 <field>
17390 <name>EWIF</name>
17391 <description>Early wakeup interrupt
17392 flag</description>
17393 <bitOffset>0</bitOffset>
17394 <bitWidth>1</bitWidth>
17395 </field>
17396 </fields>
17397 </register>
17398 </registers>
17399 </peripheral>
17400 <peripheral>
17401 <name>DMA2</name>
17402 <description>DMA controller</description>
17403 <groupName>DMA</groupName>
17404 <baseAddress>0x40026400</baseAddress>
17405 <addressBlock>
17406 <offset>0x0</offset>
17407 <size>0x400</size>
17408 <usage>registers</usage>
17409 </addressBlock>
17410 <interrupt>
17411 <name>RCC</name>
17412 <description>RCC global interrupt</description>
17413 <value>5</value>
17414 </interrupt>
17415 <registers>
17416 <register>
17417 <name>LISR</name>
17418 <displayName>LISR</displayName>
17419 <description>low interrupt status register</description>
17420 <addressOffset>0x0</addressOffset>
17421 <size>0x20</size>
17422 <access>read-only</access>
17423 <resetValue>0x00000000</resetValue>
17424 <fields>
17425 <field>
17426 <name>TCIF3</name>
17427 <description>Stream x transfer complete interrupt
17428 flag (x = 3..0)</description>
17429 <bitOffset>27</bitOffset>
17430 <bitWidth>1</bitWidth>
17431 </field>
17432 <field>
17433 <name>HTIF3</name>
17434 <description>Stream x half transfer interrupt flag
17435 (x=3..0)</description>
17436 <bitOffset>26</bitOffset>
17437 <bitWidth>1</bitWidth>
17438 </field>
17439 <field>
17440 <name>TEIF3</name>
17441 <description>Stream x transfer error interrupt flag
17442 (x=3..0)</description>
17443 <bitOffset>25</bitOffset>
17444 <bitWidth>1</bitWidth>
17445 </field>
17446 <field>
17447 <name>DMEIF3</name>
17448 <description>Stream x direct mode error interrupt
17449 flag (x=3..0)</description>
17450 <bitOffset>24</bitOffset>
17451 <bitWidth>1</bitWidth>
17452 </field>
17453 <field>
17454 <name>FEIF3</name>
17455 <description>Stream x FIFO error interrupt flag
17456 (x=3..0)</description>
17457 <bitOffset>22</bitOffset>
17458 <bitWidth>1</bitWidth>
17459 </field>
17460 <field>
17461 <name>TCIF2</name>
17462 <description>Stream x transfer complete interrupt
17463 flag (x = 3..0)</description>
17464 <bitOffset>21</bitOffset>
17465 <bitWidth>1</bitWidth>
17466 </field>
17467 <field>
17468 <name>HTIF2</name>
17469 <description>Stream x half transfer interrupt flag
17470 (x=3..0)</description>
17471 <bitOffset>20</bitOffset>
17472 <bitWidth>1</bitWidth>
17473 </field>
17474 <field>
17475 <name>TEIF2</name>
17476 <description>Stream x transfer error interrupt flag
17477 (x=3..0)</description>
17478 <bitOffset>19</bitOffset>
17479 <bitWidth>1</bitWidth>
17480 </field>
17481 <field>
17482 <name>DMEIF2</name>
17483 <description>Stream x direct mode error interrupt
17484 flag (x=3..0)</description>
17485 <bitOffset>18</bitOffset>
17486 <bitWidth>1</bitWidth>
17487 </field>
17488 <field>
17489 <name>FEIF2</name>
17490 <description>Stream x FIFO error interrupt flag
17491 (x=3..0)</description>
17492 <bitOffset>16</bitOffset>
17493 <bitWidth>1</bitWidth>
17494 </field>
17495 <field>
17496 <name>TCIF1</name>
17497 <description>Stream x transfer complete interrupt
17498 flag (x = 3..0)</description>
17499 <bitOffset>11</bitOffset>
17500 <bitWidth>1</bitWidth>
17501 </field>
17502 <field>
17503 <name>HTIF1</name>
17504 <description>Stream x half transfer interrupt flag
17505 (x=3..0)</description>
17506 <bitOffset>10</bitOffset>
17507 <bitWidth>1</bitWidth>
17508 </field>
17509 <field>
17510 <name>TEIF1</name>
17511 <description>Stream x transfer error interrupt flag
17512 (x=3..0)</description>
17513 <bitOffset>9</bitOffset>
17514 <bitWidth>1</bitWidth>
17515 </field>
17516 <field>
17517 <name>DMEIF1</name>
17518 <description>Stream x direct mode error interrupt
17519 flag (x=3..0)</description>
17520 <bitOffset>8</bitOffset>
17521 <bitWidth>1</bitWidth>
17522 </field>
17523 <field>
17524 <name>FEIF1</name>
17525 <description>Stream x FIFO error interrupt flag
17526 (x=3..0)</description>
17527 <bitOffset>6</bitOffset>
17528 <bitWidth>1</bitWidth>
17529 </field>
17530 <field>
17531 <name>TCIF0</name>
17532 <description>Stream x transfer complete interrupt
17533 flag (x = 3..0)</description>
17534 <bitOffset>5</bitOffset>
17535 <bitWidth>1</bitWidth>
17536 </field>
17537 <field>
17538 <name>HTIF0</name>
17539 <description>Stream x half transfer interrupt flag
17540 (x=3..0)</description>
17541 <bitOffset>4</bitOffset>
17542 <bitWidth>1</bitWidth>
17543 </field>
17544 <field>
17545 <name>TEIF0</name>
17546 <description>Stream x transfer error interrupt flag
17547 (x=3..0)</description>
17548 <bitOffset>3</bitOffset>
17549 <bitWidth>1</bitWidth>
17550 </field>
17551 <field>
17552 <name>DMEIF0</name>
17553 <description>Stream x direct mode error interrupt
17554 flag (x=3..0)</description>
17555 <bitOffset>2</bitOffset>
17556 <bitWidth>1</bitWidth>
17557 </field>
17558 <field>
17559 <name>FEIF0</name>
17560 <description>Stream x FIFO error interrupt flag
17561 (x=3..0)</description>
17562 <bitOffset>0</bitOffset>
17563 <bitWidth>1</bitWidth>
17564 </field>
17565 </fields>
17566 </register>
17567 <register>
17568 <name>HISR</name>
17569 <displayName>HISR</displayName>
17570 <description>high interrupt status register</description>
17571 <addressOffset>0x4</addressOffset>
17572 <size>0x20</size>
17573 <access>read-only</access>
17574 <resetValue>0x00000000</resetValue>
17575 <fields>
17576 <field>
17577 <name>TCIF7</name>
17578 <description>Stream x transfer complete interrupt
17579 flag (x=7..4)</description>
17580 <bitOffset>27</bitOffset>
17581 <bitWidth>1</bitWidth>
17582 </field>
17583 <field>
17584 <name>HTIF7</name>
17585 <description>Stream x half transfer interrupt flag
17586 (x=7..4)</description>
17587 <bitOffset>26</bitOffset>
17588 <bitWidth>1</bitWidth>
17589 </field>
17590 <field>
17591 <name>TEIF7</name>
17592 <description>Stream x transfer error interrupt flag
17593 (x=7..4)</description>
17594 <bitOffset>25</bitOffset>
17595 <bitWidth>1</bitWidth>
17596 </field>
17597 <field>
17598 <name>DMEIF7</name>
17599 <description>Stream x direct mode error interrupt
17600 flag (x=7..4)</description>
17601 <bitOffset>24</bitOffset>
17602 <bitWidth>1</bitWidth>
17603 </field>
17604 <field>
17605 <name>FEIF7</name>
17606 <description>Stream x FIFO error interrupt flag
17607 (x=7..4)</description>
17608 <bitOffset>22</bitOffset>
17609 <bitWidth>1</bitWidth>
17610 </field>
17611 <field>
17612 <name>TCIF6</name>
17613 <description>Stream x transfer complete interrupt
17614 flag (x=7..4)</description>
17615 <bitOffset>21</bitOffset>
17616 <bitWidth>1</bitWidth>
17617 </field>
17618 <field>
17619 <name>HTIF6</name>
17620 <description>Stream x half transfer interrupt flag
17621 (x=7..4)</description>
17622 <bitOffset>20</bitOffset>
17623 <bitWidth>1</bitWidth>
17624 </field>
17625 <field>
17626 <name>TEIF6</name>
17627 <description>Stream x transfer error interrupt flag
17628 (x=7..4)</description>
17629 <bitOffset>19</bitOffset>
17630 <bitWidth>1</bitWidth>
17631 </field>
17632 <field>
17633 <name>DMEIF6</name>
17634 <description>Stream x direct mode error interrupt
17635 flag (x=7..4)</description>
17636 <bitOffset>18</bitOffset>
17637 <bitWidth>1</bitWidth>
17638 </field>
17639 <field>
17640 <name>FEIF6</name>
17641 <description>Stream x FIFO error interrupt flag
17642 (x=7..4)</description>
17643 <bitOffset>16</bitOffset>
17644 <bitWidth>1</bitWidth>
17645 </field>
17646 <field>
17647 <name>TCIF5</name>
17648 <description>Stream x transfer complete interrupt
17649 flag (x=7..4)</description>
17650 <bitOffset>11</bitOffset>
17651 <bitWidth>1</bitWidth>
17652 </field>
17653 <field>
17654 <name>HTIF5</name>
17655 <description>Stream x half transfer interrupt flag
17656 (x=7..4)</description>
17657 <bitOffset>10</bitOffset>
17658 <bitWidth>1</bitWidth>
17659 </field>
17660 <field>
17661 <name>TEIF5</name>
17662 <description>Stream x transfer error interrupt flag
17663 (x=7..4)</description>
17664 <bitOffset>9</bitOffset>
17665 <bitWidth>1</bitWidth>
17666 </field>
17667 <field>
17668 <name>DMEIF5</name>
17669 <description>Stream x direct mode error interrupt
17670 flag (x=7..4)</description>
17671 <bitOffset>8</bitOffset>
17672 <bitWidth>1</bitWidth>
17673 </field>
17674 <field>
17675 <name>FEIF5</name>
17676 <description>Stream x FIFO error interrupt flag
17677 (x=7..4)</description>
17678 <bitOffset>6</bitOffset>
17679 <bitWidth>1</bitWidth>
17680 </field>
17681 <field>
17682 <name>TCIF4</name>
17683 <description>Stream x transfer complete interrupt
17684 flag (x=7..4)</description>
17685 <bitOffset>5</bitOffset>
17686 <bitWidth>1</bitWidth>
17687 </field>
17688 <field>
17689 <name>HTIF4</name>
17690 <description>Stream x half transfer interrupt flag
17691 (x=7..4)</description>
17692 <bitOffset>4</bitOffset>
17693 <bitWidth>1</bitWidth>
17694 </field>
17695 <field>
17696 <name>TEIF4</name>
17697 <description>Stream x transfer error interrupt flag
17698 (x=7..4)</description>
17699 <bitOffset>3</bitOffset>
17700 <bitWidth>1</bitWidth>
17701 </field>
17702 <field>
17703 <name>DMEIF4</name>
17704 <description>Stream x direct mode error interrupt
17705 flag (x=7..4)</description>
17706 <bitOffset>2</bitOffset>
17707 <bitWidth>1</bitWidth>
17708 </field>
17709 <field>
17710 <name>FEIF4</name>
17711 <description>Stream x FIFO error interrupt flag
17712 (x=7..4)</description>
17713 <bitOffset>0</bitOffset>
17714 <bitWidth>1</bitWidth>
17715 </field>
17716 </fields>
17717 </register>
17718 <register>
17719 <name>LIFCR</name>
17720 <displayName>LIFCR</displayName>
17721 <description>low interrupt flag clear
17722 register</description>
17723 <addressOffset>0x8</addressOffset>
17724 <size>0x20</size>
17725 <access>write-only</access>
17726 <resetValue>0x00000000</resetValue>
17727 <fields>
17728 <field>
17729 <name>CTCIF3</name>
17730 <description>Stream x clear transfer complete
17731 interrupt flag (x = 3..0)</description>
17732 <bitOffset>27</bitOffset>
17733 <bitWidth>1</bitWidth>
17734 </field>
17735 <field>
17736 <name>CHTIF3</name>
17737 <description>Stream x clear half transfer interrupt
17738 flag (x = 3..0)</description>
17739 <bitOffset>26</bitOffset>
17740 <bitWidth>1</bitWidth>
17741 </field>
17742 <field>
17743 <name>CTEIF3</name>
17744 <description>Stream x clear transfer error interrupt
17745 flag (x = 3..0)</description>
17746 <bitOffset>25</bitOffset>
17747 <bitWidth>1</bitWidth>
17748 </field>
17749 <field>
17750 <name>CDMEIF3</name>
17751 <description>Stream x clear direct mode error
17752 interrupt flag (x = 3..0)</description>
17753 <bitOffset>24</bitOffset>
17754 <bitWidth>1</bitWidth>
17755 </field>
17756 <field>
17757 <name>CFEIF3</name>
17758 <description>Stream x clear FIFO error interrupt flag
17759 (x = 3..0)</description>
17760 <bitOffset>22</bitOffset>
17761 <bitWidth>1</bitWidth>
17762 </field>
17763 <field>
17764 <name>CTCIF2</name>
17765 <description>Stream x clear transfer complete
17766 interrupt flag (x = 3..0)</description>
17767 <bitOffset>21</bitOffset>
17768 <bitWidth>1</bitWidth>
17769 </field>
17770 <field>
17771 <name>CHTIF2</name>
17772 <description>Stream x clear half transfer interrupt
17773 flag (x = 3..0)</description>
17774 <bitOffset>20</bitOffset>
17775 <bitWidth>1</bitWidth>
17776 </field>
17777 <field>
17778 <name>CTEIF2</name>
17779 <description>Stream x clear transfer error interrupt
17780 flag (x = 3..0)</description>
17781 <bitOffset>19</bitOffset>
17782 <bitWidth>1</bitWidth>
17783 </field>
17784 <field>
17785 <name>CDMEIF2</name>
17786 <description>Stream x clear direct mode error
17787 interrupt flag (x = 3..0)</description>
17788 <bitOffset>18</bitOffset>
17789 <bitWidth>1</bitWidth>
17790 </field>
17791 <field>
17792 <name>CFEIF2</name>
17793 <description>Stream x clear FIFO error interrupt flag
17794 (x = 3..0)</description>
17795 <bitOffset>16</bitOffset>
17796 <bitWidth>1</bitWidth>
17797 </field>
17798 <field>
17799 <name>CTCIF1</name>
17800 <description>Stream x clear transfer complete
17801 interrupt flag (x = 3..0)</description>
17802 <bitOffset>11</bitOffset>
17803 <bitWidth>1</bitWidth>
17804 </field>
17805 <field>
17806 <name>CHTIF1</name>
17807 <description>Stream x clear half transfer interrupt
17808 flag (x = 3..0)</description>
17809 <bitOffset>10</bitOffset>
17810 <bitWidth>1</bitWidth>
17811 </field>
17812 <field>
17813 <name>CTEIF1</name>
17814 <description>Stream x clear transfer error interrupt
17815 flag (x = 3..0)</description>
17816 <bitOffset>9</bitOffset>
17817 <bitWidth>1</bitWidth>
17818 </field>
17819 <field>
17820 <name>CDMEIF1</name>
17821 <description>Stream x clear direct mode error
17822 interrupt flag (x = 3..0)</description>
17823 <bitOffset>8</bitOffset>
17824 <bitWidth>1</bitWidth>
17825 </field>
17826 <field>
17827 <name>CFEIF1</name>
17828 <description>Stream x clear FIFO error interrupt flag
17829 (x = 3..0)</description>
17830 <bitOffset>6</bitOffset>
17831 <bitWidth>1</bitWidth>
17832 </field>
17833 <field>
17834 <name>CTCIF0</name>
17835 <description>Stream x clear transfer complete
17836 interrupt flag (x = 3..0)</description>
17837 <bitOffset>5</bitOffset>
17838 <bitWidth>1</bitWidth>
17839 </field>
17840 <field>
17841 <name>CHTIF0</name>
17842 <description>Stream x clear half transfer interrupt
17843 flag (x = 3..0)</description>
17844 <bitOffset>4</bitOffset>
17845 <bitWidth>1</bitWidth>
17846 </field>
17847 <field>
17848 <name>CTEIF0</name>
17849 <description>Stream x clear transfer error interrupt
17850 flag (x = 3..0)</description>
17851 <bitOffset>3</bitOffset>
17852 <bitWidth>1</bitWidth>
17853 </field>
17854 <field>
17855 <name>CDMEIF0</name>
17856 <description>Stream x clear direct mode error
17857 interrupt flag (x = 3..0)</description>
17858 <bitOffset>2</bitOffset>
17859 <bitWidth>1</bitWidth>
17860 </field>
17861 <field>
17862 <name>CFEIF0</name>
17863 <description>Stream x clear FIFO error interrupt flag
17864 (x = 3..0)</description>
17865 <bitOffset>0</bitOffset>
17866 <bitWidth>1</bitWidth>
17867 </field>
17868 </fields>
17869 </register>
17870 <register>
17871 <name>HIFCR</name>
17872 <displayName>HIFCR</displayName>
17873 <description>high interrupt flag clear
17874 register</description>
17875 <addressOffset>0xC</addressOffset>
17876 <size>0x20</size>
17877 <access>write-only</access>
17878 <resetValue>0x00000000</resetValue>
17879 <fields>
17880 <field>
17881 <name>CTCIF7</name>
17882 <description>Stream x clear transfer complete
17883 interrupt flag (x = 7..4)</description>
17884 <bitOffset>27</bitOffset>
17885 <bitWidth>1</bitWidth>
17886 </field>
17887 <field>
17888 <name>CHTIF7</name>
17889 <description>Stream x clear half transfer interrupt
17890 flag (x = 7..4)</description>
17891 <bitOffset>26</bitOffset>
17892 <bitWidth>1</bitWidth>
17893 </field>
17894 <field>
17895 <name>CTEIF7</name>
17896 <description>Stream x clear transfer error interrupt
17897 flag (x = 7..4)</description>
17898 <bitOffset>25</bitOffset>
17899 <bitWidth>1</bitWidth>
17900 </field>
17901 <field>
17902 <name>CDMEIF7</name>
17903 <description>Stream x clear direct mode error
17904 interrupt flag (x = 7..4)</description>
17905 <bitOffset>24</bitOffset>
17906 <bitWidth>1</bitWidth>
17907 </field>
17908 <field>
17909 <name>CFEIF7</name>
17910 <description>Stream x clear FIFO error interrupt flag
17911 (x = 7..4)</description>
17912 <bitOffset>22</bitOffset>
17913 <bitWidth>1</bitWidth>
17914 </field>
17915 <field>
17916 <name>CTCIF6</name>
17917 <description>Stream x clear transfer complete
17918 interrupt flag (x = 7..4)</description>
17919 <bitOffset>21</bitOffset>
17920 <bitWidth>1</bitWidth>
17921 </field>
17922 <field>
17923 <name>CHTIF6</name>
17924 <description>Stream x clear half transfer interrupt
17925 flag (x = 7..4)</description>
17926 <bitOffset>20</bitOffset>
17927 <bitWidth>1</bitWidth>
17928 </field>
17929 <field>
17930 <name>CTEIF6</name>
17931 <description>Stream x clear transfer error interrupt
17932 flag (x = 7..4)</description>
17933 <bitOffset>19</bitOffset>
17934 <bitWidth>1</bitWidth>
17935 </field>
17936 <field>
17937 <name>CDMEIF6</name>
17938 <description>Stream x clear direct mode error
17939 interrupt flag (x = 7..4)</description>
17940 <bitOffset>18</bitOffset>
17941 <bitWidth>1</bitWidth>
17942 </field>
17943 <field>
17944 <name>CFEIF6</name>
17945 <description>Stream x clear FIFO error interrupt flag
17946 (x = 7..4)</description>
17947 <bitOffset>16</bitOffset>
17948 <bitWidth>1</bitWidth>
17949 </field>
17950 <field>
17951 <name>CTCIF5</name>
17952 <description>Stream x clear transfer complete
17953 interrupt flag (x = 7..4)</description>
17954 <bitOffset>11</bitOffset>
17955 <bitWidth>1</bitWidth>
17956 </field>
17957 <field>
17958 <name>CHTIF5</name>
17959 <description>Stream x clear half transfer interrupt
17960 flag (x = 7..4)</description>
17961 <bitOffset>10</bitOffset>
17962 <bitWidth>1</bitWidth>
17963 </field>
17964 <field>
17965 <name>CTEIF5</name>
17966 <description>Stream x clear transfer error interrupt
17967 flag (x = 7..4)</description>
17968 <bitOffset>9</bitOffset>
17969 <bitWidth>1</bitWidth>
17970 </field>
17971 <field>
17972 <name>CDMEIF5</name>
17973 <description>Stream x clear direct mode error
17974 interrupt flag (x = 7..4)</description>
17975 <bitOffset>8</bitOffset>
17976 <bitWidth>1</bitWidth>
17977 </field>
17978 <field>
17979 <name>CFEIF5</name>
17980 <description>Stream x clear FIFO error interrupt flag
17981 (x = 7..4)</description>
17982 <bitOffset>6</bitOffset>
17983 <bitWidth>1</bitWidth>
17984 </field>
17985 <field>
17986 <name>CTCIF4</name>
17987 <description>Stream x clear transfer complete
17988 interrupt flag (x = 7..4)</description>
17989 <bitOffset>5</bitOffset>
17990 <bitWidth>1</bitWidth>
17991 </field>
17992 <field>
17993 <name>CHTIF4</name>
17994 <description>Stream x clear half transfer interrupt
17995 flag (x = 7..4)</description>
17996 <bitOffset>4</bitOffset>
17997 <bitWidth>1</bitWidth>
17998 </field>
17999 <field>
18000 <name>CTEIF4</name>
18001 <description>Stream x clear transfer error interrupt
18002 flag (x = 7..4)</description>
18003 <bitOffset>3</bitOffset>
18004 <bitWidth>1</bitWidth>
18005 </field>
18006 <field>
18007 <name>CDMEIF4</name>
18008 <description>Stream x clear direct mode error
18009 interrupt flag (x = 7..4)</description>
18010 <bitOffset>2</bitOffset>
18011 <bitWidth>1</bitWidth>
18012 </field>
18013 <field>
18014 <name>CFEIF4</name>
18015 <description>Stream x clear FIFO error interrupt flag
18016 (x = 7..4)</description>
18017 <bitOffset>0</bitOffset>
18018 <bitWidth>1</bitWidth>
18019 </field>
18020 </fields>
18021 </register>
18022 <register>
18023 <name>S0CR</name>
18024 <displayName>S0CR</displayName>
18025 <description>stream x configuration
18026 register</description>
18027 <addressOffset>0x10</addressOffset>
18028 <size>0x20</size>
18029 <access>read-write</access>
18030 <resetValue>0x00000000</resetValue>
18031 <fields>
18032 <field>
18033 <name>CHSEL</name>
18034 <description>Channel selection</description>
18035 <bitOffset>25</bitOffset>
18036 <bitWidth>3</bitWidth>
18037 </field>
18038 <field>
18039 <name>MBURST</name>
18040 <description>Memory burst transfer
18041 configuration</description>
18042 <bitOffset>23</bitOffset>
18043 <bitWidth>2</bitWidth>
18044 </field>
18045 <field>
18046 <name>PBURST</name>
18047 <description>Peripheral burst transfer
18048 configuration</description>
18049 <bitOffset>21</bitOffset>
18050 <bitWidth>2</bitWidth>
18051 </field>
18052 <field>
18053 <name>CT</name>
18054 <description>Current target (only in double buffer
18055 mode)</description>
18056 <bitOffset>19</bitOffset>
18057 <bitWidth>1</bitWidth>
18058 </field>
18059 <field>
18060 <name>DBM</name>
18061 <description>Double buffer mode</description>
18062 <bitOffset>18</bitOffset>
18063 <bitWidth>1</bitWidth>
18064 </field>
18065 <field>
18066 <name>PL</name>
18067 <description>Priority level</description>
18068 <bitOffset>16</bitOffset>
18069 <bitWidth>2</bitWidth>
18070 </field>
18071 <field>
18072 <name>PINCOS</name>
18073 <description>Peripheral increment offset
18074 size</description>
18075 <bitOffset>15</bitOffset>
18076 <bitWidth>1</bitWidth>
18077 </field>
18078 <field>
18079 <name>MSIZE</name>
18080 <description>Memory data size</description>
18081 <bitOffset>13</bitOffset>
18082 <bitWidth>2</bitWidth>
18083 </field>
18084 <field>
18085 <name>PSIZE</name>
18086 <description>Peripheral data size</description>
18087 <bitOffset>11</bitOffset>
18088 <bitWidth>2</bitWidth>
18089 </field>
18090 <field>
18091 <name>MINC</name>
18092 <description>Memory increment mode</description>
18093 <bitOffset>10</bitOffset>
18094 <bitWidth>1</bitWidth>
18095 </field>
18096 <field>
18097 <name>PINC</name>
18098 <description>Peripheral increment mode</description>
18099 <bitOffset>9</bitOffset>
18100 <bitWidth>1</bitWidth>
18101 </field>
18102 <field>
18103 <name>CIRC</name>
18104 <description>Circular mode</description>
18105 <bitOffset>8</bitOffset>
18106 <bitWidth>1</bitWidth>
18107 </field>
18108 <field>
18109 <name>DIR</name>
18110 <description>Data transfer direction</description>
18111 <bitOffset>6</bitOffset>
18112 <bitWidth>2</bitWidth>
18113 </field>
18114 <field>
18115 <name>PFCTRL</name>
18116 <description>Peripheral flow controller</description>
18117 <bitOffset>5</bitOffset>
18118 <bitWidth>1</bitWidth>
18119 </field>
18120 <field>
18121 <name>TCIE</name>
18122 <description>Transfer complete interrupt
18123 enable</description>
18124 <bitOffset>4</bitOffset>
18125 <bitWidth>1</bitWidth>
18126 </field>
18127 <field>
18128 <name>HTIE</name>
18129 <description>Half transfer interrupt
18130 enable</description>
18131 <bitOffset>3</bitOffset>
18132 <bitWidth>1</bitWidth>
18133 </field>
18134 <field>
18135 <name>TEIE</name>
18136 <description>Transfer error interrupt
18137 enable</description>
18138 <bitOffset>2</bitOffset>
18139 <bitWidth>1</bitWidth>
18140 </field>
18141 <field>
18142 <name>DMEIE</name>
18143 <description>Direct mode error interrupt
18144 enable</description>
18145 <bitOffset>1</bitOffset>
18146 <bitWidth>1</bitWidth>
18147 </field>
18148 <field>
18149 <name>EN</name>
18150 <description>Stream enable / flag stream ready when
18151 read low</description>
18152 <bitOffset>0</bitOffset>
18153 <bitWidth>1</bitWidth>
18154 </field>
18155 </fields>
18156 </register>
18157 <register>
18158 <name>S0NDTR</name>
18159 <displayName>S0NDTR</displayName>
18160 <description>stream x number of data
18161 register</description>
18162 <addressOffset>0x14</addressOffset>
18163 <size>0x20</size>
18164 <access>read-write</access>
18165 <resetValue>0x00000000</resetValue>
18166 <fields>
18167 <field>
18168 <name>NDT</name>
18169 <description>Number of data items to
18170 transfer</description>
18171 <bitOffset>0</bitOffset>
18172 <bitWidth>16</bitWidth>
18173 </field>
18174 </fields>
18175 </register>
18176 <register>
18177 <name>S0PAR</name>
18178 <displayName>S0PAR</displayName>
18179 <description>stream x peripheral address
18180 register</description>
18181 <addressOffset>0x18</addressOffset>
18182 <size>0x20</size>
18183 <access>read-write</access>
18184 <resetValue>0x00000000</resetValue>
18185 <fields>
18186 <field>
18187 <name>PA</name>
18188 <description>Peripheral address</description>
18189 <bitOffset>0</bitOffset>
18190 <bitWidth>32</bitWidth>
18191 </field>
18192 </fields>
18193 </register>
18194 <register>
18195 <name>S0M0AR</name>
18196 <displayName>S0M0AR</displayName>
18197 <description>stream x memory 0 address
18198 register</description>
18199 <addressOffset>0x1C</addressOffset>
18200 <size>0x20</size>
18201 <access>read-write</access>
18202 <resetValue>0x00000000</resetValue>
18203 <fields>
18204 <field>
18205 <name>M0A</name>
18206 <description>Memory 0 address</description>
18207 <bitOffset>0</bitOffset>
18208 <bitWidth>32</bitWidth>
18209 </field>
18210 </fields>
18211 </register>
18212 <register>
18213 <name>S0M1AR</name>
18214 <displayName>S0M1AR</displayName>
18215 <description>stream x memory 1 address
18216 register</description>
18217 <addressOffset>0x20</addressOffset>
18218 <size>0x20</size>
18219 <access>read-write</access>
18220 <resetValue>0x00000000</resetValue>
18221 <fields>
18222 <field>
18223 <name>M1A</name>
18224 <description>Memory 1 address (used in case of Double
18225 buffer mode)</description>
18226 <bitOffset>0</bitOffset>
18227 <bitWidth>32</bitWidth>
18228 </field>
18229 </fields>
18230 </register>
18231 <register>
18232 <name>S0FCR</name>
18233 <displayName>S0FCR</displayName>
18234 <description>stream x FIFO control register</description>
18235 <addressOffset>0x24</addressOffset>
18236 <size>0x20</size>
18237 <resetValue>0x00000021</resetValue>
18238 <fields>
18239 <field>
18240 <name>FEIE</name>
18241 <description>FIFO error interrupt
18242 enable</description>
18243 <bitOffset>7</bitOffset>
18244 <bitWidth>1</bitWidth>
18245 <access>read-write</access>
18246 </field>
18247 <field>
18248 <name>FS</name>
18249 <description>FIFO status</description>
18250 <bitOffset>3</bitOffset>
18251 <bitWidth>3</bitWidth>
18252 <access>read-only</access>
18253 </field>
18254 <field>
18255 <name>DMDIS</name>
18256 <description>Direct mode disable</description>
18257 <bitOffset>2</bitOffset>
18258 <bitWidth>1</bitWidth>
18259 <access>read-write</access>
18260 </field>
18261 <field>
18262 <name>FTH</name>
18263 <description>FIFO threshold selection</description>
18264 <bitOffset>0</bitOffset>
18265 <bitWidth>2</bitWidth>
18266 <access>read-write</access>
18267 </field>
18268 </fields>
18269 </register>
18270 <register>
18271 <name>S1CR</name>
18272 <displayName>S1CR</displayName>
18273 <description>stream x configuration
18274 register</description>
18275 <addressOffset>0x28</addressOffset>
18276 <size>0x20</size>
18277 <access>read-write</access>
18278 <resetValue>0x00000000</resetValue>
18279 <fields>
18280 <field>
18281 <name>CHSEL</name>
18282 <description>Channel selection</description>
18283 <bitOffset>25</bitOffset>
18284 <bitWidth>3</bitWidth>
18285 </field>
18286 <field>
18287 <name>MBURST</name>
18288 <description>Memory burst transfer
18289 configuration</description>
18290 <bitOffset>23</bitOffset>
18291 <bitWidth>2</bitWidth>
18292 </field>
18293 <field>
18294 <name>PBURST</name>
18295 <description>Peripheral burst transfer
18296 configuration</description>
18297 <bitOffset>21</bitOffset>
18298 <bitWidth>2</bitWidth>
18299 </field>
18300 <field>
18301 <name>ACK</name>
18302 <description>ACK</description>
18303 <bitOffset>20</bitOffset>
18304 <bitWidth>1</bitWidth>
18305 </field>
18306 <field>
18307 <name>CT</name>
18308 <description>Current target (only in double buffer
18309 mode)</description>
18310 <bitOffset>19</bitOffset>
18311 <bitWidth>1</bitWidth>
18312 </field>
18313 <field>
18314 <name>DBM</name>
18315 <description>Double buffer mode</description>
18316 <bitOffset>18</bitOffset>
18317 <bitWidth>1</bitWidth>
18318 </field>
18319 <field>
18320 <name>PL</name>
18321 <description>Priority level</description>
18322 <bitOffset>16</bitOffset>
18323 <bitWidth>2</bitWidth>
18324 </field>
18325 <field>
18326 <name>PINCOS</name>
18327 <description>Peripheral increment offset
18328 size</description>
18329 <bitOffset>15</bitOffset>
18330 <bitWidth>1</bitWidth>
18331 </field>
18332 <field>
18333 <name>MSIZE</name>
18334 <description>Memory data size</description>
18335 <bitOffset>13</bitOffset>
18336 <bitWidth>2</bitWidth>
18337 </field>
18338 <field>
18339 <name>PSIZE</name>
18340 <description>Peripheral data size</description>
18341 <bitOffset>11</bitOffset>
18342 <bitWidth>2</bitWidth>
18343 </field>
18344 <field>
18345 <name>MINC</name>
18346 <description>Memory increment mode</description>
18347 <bitOffset>10</bitOffset>
18348 <bitWidth>1</bitWidth>
18349 </field>
18350 <field>
18351 <name>PINC</name>
18352 <description>Peripheral increment mode</description>
18353 <bitOffset>9</bitOffset>
18354 <bitWidth>1</bitWidth>
18355 </field>
18356 <field>
18357 <name>CIRC</name>
18358 <description>Circular mode</description>
18359 <bitOffset>8</bitOffset>
18360 <bitWidth>1</bitWidth>
18361 </field>
18362 <field>
18363 <name>DIR</name>
18364 <description>Data transfer direction</description>
18365 <bitOffset>6</bitOffset>
18366 <bitWidth>2</bitWidth>
18367 </field>
18368 <field>
18369 <name>PFCTRL</name>
18370 <description>Peripheral flow controller</description>
18371 <bitOffset>5</bitOffset>
18372 <bitWidth>1</bitWidth>
18373 </field>
18374 <field>
18375 <name>TCIE</name>
18376 <description>Transfer complete interrupt
18377 enable</description>
18378 <bitOffset>4</bitOffset>
18379 <bitWidth>1</bitWidth>
18380 </field>
18381 <field>
18382 <name>HTIE</name>
18383 <description>Half transfer interrupt
18384 enable</description>
18385 <bitOffset>3</bitOffset>
18386 <bitWidth>1</bitWidth>
18387 </field>
18388 <field>
18389 <name>TEIE</name>
18390 <description>Transfer error interrupt
18391 enable</description>
18392 <bitOffset>2</bitOffset>
18393 <bitWidth>1</bitWidth>
18394 </field>
18395 <field>
18396 <name>DMEIE</name>
18397 <description>Direct mode error interrupt
18398 enable</description>
18399 <bitOffset>1</bitOffset>
18400 <bitWidth>1</bitWidth>
18401 </field>
18402 <field>
18403 <name>EN</name>
18404 <description>Stream enable / flag stream ready when
18405 read low</description>
18406 <bitOffset>0</bitOffset>
18407 <bitWidth>1</bitWidth>
18408 </field>
18409 </fields>
18410 </register>
18411 <register>
18412 <name>S1NDTR</name>
18413 <displayName>S1NDTR</displayName>
18414 <description>stream x number of data
18415 register</description>
18416 <addressOffset>0x2C</addressOffset>
18417 <size>0x20</size>
18418 <access>read-write</access>
18419 <resetValue>0x00000000</resetValue>
18420 <fields>
18421 <field>
18422 <name>NDT</name>
18423 <description>Number of data items to
18424 transfer</description>
18425 <bitOffset>0</bitOffset>
18426 <bitWidth>16</bitWidth>
18427 </field>
18428 </fields>
18429 </register>
18430 <register>
18431 <name>S1PAR</name>
18432 <displayName>S1PAR</displayName>
18433 <description>stream x peripheral address
18434 register</description>
18435 <addressOffset>0x30</addressOffset>
18436 <size>0x20</size>
18437 <access>read-write</access>
18438 <resetValue>0x00000000</resetValue>
18439 <fields>
18440 <field>
18441 <name>PA</name>
18442 <description>Peripheral address</description>
18443 <bitOffset>0</bitOffset>
18444 <bitWidth>32</bitWidth>
18445 </field>
18446 </fields>
18447 </register>
18448 <register>
18449 <name>S1M0AR</name>
18450 <displayName>S1M0AR</displayName>
18451 <description>stream x memory 0 address
18452 register</description>
18453 <addressOffset>0x34</addressOffset>
18454 <size>0x20</size>
18455 <access>read-write</access>
18456 <resetValue>0x00000000</resetValue>
18457 <fields>
18458 <field>
18459 <name>M0A</name>
18460 <description>Memory 0 address</description>
18461 <bitOffset>0</bitOffset>
18462 <bitWidth>32</bitWidth>
18463 </field>
18464 </fields>
18465 </register>
18466 <register>
18467 <name>S1M1AR</name>
18468 <displayName>S1M1AR</displayName>
18469 <description>stream x memory 1 address
18470 register</description>
18471 <addressOffset>0x38</addressOffset>
18472 <size>0x20</size>
18473 <access>read-write</access>
18474 <resetValue>0x00000000</resetValue>
18475 <fields>
18476 <field>
18477 <name>M1A</name>
18478 <description>Memory 1 address (used in case of Double
18479 buffer mode)</description>
18480 <bitOffset>0</bitOffset>
18481 <bitWidth>32</bitWidth>
18482 </field>
18483 </fields>
18484 </register>
18485 <register>
18486 <name>S1FCR</name>
18487 <displayName>S1FCR</displayName>
18488 <description>stream x FIFO control register</description>
18489 <addressOffset>0x3C</addressOffset>
18490 <size>0x20</size>
18491 <resetValue>0x00000021</resetValue>
18492 <fields>
18493 <field>
18494 <name>FEIE</name>
18495 <description>FIFO error interrupt
18496 enable</description>
18497 <bitOffset>7</bitOffset>
18498 <bitWidth>1</bitWidth>
18499 <access>read-write</access>
18500 </field>
18501 <field>
18502 <name>FS</name>
18503 <description>FIFO status</description>
18504 <bitOffset>3</bitOffset>
18505 <bitWidth>3</bitWidth>
18506 <access>read-only</access>
18507 </field>
18508 <field>
18509 <name>DMDIS</name>
18510 <description>Direct mode disable</description>
18511 <bitOffset>2</bitOffset>
18512 <bitWidth>1</bitWidth>
18513 <access>read-write</access>
18514 </field>
18515 <field>
18516 <name>FTH</name>
18517 <description>FIFO threshold selection</description>
18518 <bitOffset>0</bitOffset>
18519 <bitWidth>2</bitWidth>
18520 <access>read-write</access>
18521 </field>
18522 </fields>
18523 </register>
18524 <register>
18525 <name>S2CR</name>
18526 <displayName>S2CR</displayName>
18527 <description>stream x configuration
18528 register</description>
18529 <addressOffset>0x40</addressOffset>
18530 <size>0x20</size>
18531 <access>read-write</access>
18532 <resetValue>0x00000000</resetValue>
18533 <fields>
18534 <field>
18535 <name>CHSEL</name>
18536 <description>Channel selection</description>
18537 <bitOffset>25</bitOffset>
18538 <bitWidth>3</bitWidth>
18539 </field>
18540 <field>
18541 <name>MBURST</name>
18542 <description>Memory burst transfer
18543 configuration</description>
18544 <bitOffset>23</bitOffset>
18545 <bitWidth>2</bitWidth>
18546 </field>
18547 <field>
18548 <name>PBURST</name>
18549 <description>Peripheral burst transfer
18550 configuration</description>
18551 <bitOffset>21</bitOffset>
18552 <bitWidth>2</bitWidth>
18553 </field>
18554 <field>
18555 <name>ACK</name>
18556 <description>ACK</description>
18557 <bitOffset>20</bitOffset>
18558 <bitWidth>1</bitWidth>
18559 </field>
18560 <field>
18561 <name>CT</name>
18562 <description>Current target (only in double buffer
18563 mode)</description>
18564 <bitOffset>19</bitOffset>
18565 <bitWidth>1</bitWidth>
18566 </field>
18567 <field>
18568 <name>DBM</name>
18569 <description>Double buffer mode</description>
18570 <bitOffset>18</bitOffset>
18571 <bitWidth>1</bitWidth>
18572 </field>
18573 <field>
18574 <name>PL</name>
18575 <description>Priority level</description>
18576 <bitOffset>16</bitOffset>
18577 <bitWidth>2</bitWidth>
18578 </field>
18579 <field>
18580 <name>PINCOS</name>
18581 <description>Peripheral increment offset
18582 size</description>
18583 <bitOffset>15</bitOffset>
18584 <bitWidth>1</bitWidth>
18585 </field>
18586 <field>
18587 <name>MSIZE</name>
18588 <description>Memory data size</description>
18589 <bitOffset>13</bitOffset>
18590 <bitWidth>2</bitWidth>
18591 </field>
18592 <field>
18593 <name>PSIZE</name>
18594 <description>Peripheral data size</description>
18595 <bitOffset>11</bitOffset>
18596 <bitWidth>2</bitWidth>
18597 </field>
18598 <field>
18599 <name>MINC</name>
18600 <description>Memory increment mode</description>
18601 <bitOffset>10</bitOffset>
18602 <bitWidth>1</bitWidth>
18603 </field>
18604 <field>
18605 <name>PINC</name>
18606 <description>Peripheral increment mode</description>
18607 <bitOffset>9</bitOffset>
18608 <bitWidth>1</bitWidth>
18609 </field>
18610 <field>
18611 <name>CIRC</name>
18612 <description>Circular mode</description>
18613 <bitOffset>8</bitOffset>
18614 <bitWidth>1</bitWidth>
18615 </field>
18616 <field>
18617 <name>DIR</name>
18618 <description>Data transfer direction</description>
18619 <bitOffset>6</bitOffset>
18620 <bitWidth>2</bitWidth>
18621 </field>
18622 <field>
18623 <name>PFCTRL</name>
18624 <description>Peripheral flow controller</description>
18625 <bitOffset>5</bitOffset>
18626 <bitWidth>1</bitWidth>
18627 </field>
18628 <field>
18629 <name>TCIE</name>
18630 <description>Transfer complete interrupt
18631 enable</description>
18632 <bitOffset>4</bitOffset>
18633 <bitWidth>1</bitWidth>
18634 </field>
18635 <field>
18636 <name>HTIE</name>
18637 <description>Half transfer interrupt
18638 enable</description>
18639 <bitOffset>3</bitOffset>
18640 <bitWidth>1</bitWidth>
18641 </field>
18642 <field>
18643 <name>TEIE</name>
18644 <description>Transfer error interrupt
18645 enable</description>
18646 <bitOffset>2</bitOffset>
18647 <bitWidth>1</bitWidth>
18648 </field>
18649 <field>
18650 <name>DMEIE</name>
18651 <description>Direct mode error interrupt
18652 enable</description>
18653 <bitOffset>1</bitOffset>
18654 <bitWidth>1</bitWidth>
18655 </field>
18656 <field>
18657 <name>EN</name>
18658 <description>Stream enable / flag stream ready when
18659 read low</description>
18660 <bitOffset>0</bitOffset>
18661 <bitWidth>1</bitWidth>
18662 </field>
18663 </fields>
18664 </register>
18665 <register>
18666 <name>S2NDTR</name>
18667 <displayName>S2NDTR</displayName>
18668 <description>stream x number of data
18669 register</description>
18670 <addressOffset>0x44</addressOffset>
18671 <size>0x20</size>
18672 <access>read-write</access>
18673 <resetValue>0x00000000</resetValue>
18674 <fields>
18675 <field>
18676 <name>NDT</name>
18677 <description>Number of data items to
18678 transfer</description>
18679 <bitOffset>0</bitOffset>
18680 <bitWidth>16</bitWidth>
18681 </field>
18682 </fields>
18683 </register>
18684 <register>
18685 <name>S2PAR</name>
18686 <displayName>S2PAR</displayName>
18687 <description>stream x peripheral address
18688 register</description>
18689 <addressOffset>0x48</addressOffset>
18690 <size>0x20</size>
18691 <access>read-write</access>
18692 <resetValue>0x00000000</resetValue>
18693 <fields>
18694 <field>
18695 <name>PA</name>
18696 <description>Peripheral address</description>
18697 <bitOffset>0</bitOffset>
18698 <bitWidth>32</bitWidth>
18699 </field>
18700 </fields>
18701 </register>
18702 <register>
18703 <name>S2M0AR</name>
18704 <displayName>S2M0AR</displayName>
18705 <description>stream x memory 0 address
18706 register</description>
18707 <addressOffset>0x4C</addressOffset>
18708 <size>0x20</size>
18709 <access>read-write</access>
18710 <resetValue>0x00000000</resetValue>
18711 <fields>
18712 <field>
18713 <name>M0A</name>
18714 <description>Memory 0 address</description>
18715 <bitOffset>0</bitOffset>
18716 <bitWidth>32</bitWidth>
18717 </field>
18718 </fields>
18719 </register>
18720 <register>
18721 <name>S2M1AR</name>
18722 <displayName>S2M1AR</displayName>
18723 <description>stream x memory 1 address
18724 register</description>
18725 <addressOffset>0x50</addressOffset>
18726 <size>0x20</size>
18727 <access>read-write</access>
18728 <resetValue>0x00000000</resetValue>
18729 <fields>
18730 <field>
18731 <name>M1A</name>
18732 <description>Memory 1 address (used in case of Double
18733 buffer mode)</description>
18734 <bitOffset>0</bitOffset>
18735 <bitWidth>32</bitWidth>
18736 </field>
18737 </fields>
18738 </register>
18739 <register>
18740 <name>S2FCR</name>
18741 <displayName>S2FCR</displayName>
18742 <description>stream x FIFO control register</description>
18743 <addressOffset>0x54</addressOffset>
18744 <size>0x20</size>
18745 <resetValue>0x00000021</resetValue>
18746 <fields>
18747 <field>
18748 <name>FEIE</name>
18749 <description>FIFO error interrupt
18750 enable</description>
18751 <bitOffset>7</bitOffset>
18752 <bitWidth>1</bitWidth>
18753 <access>read-write</access>
18754 </field>
18755 <field>
18756 <name>FS</name>
18757 <description>FIFO status</description>
18758 <bitOffset>3</bitOffset>
18759 <bitWidth>3</bitWidth>
18760 <access>read-only</access>
18761 </field>
18762 <field>
18763 <name>DMDIS</name>
18764 <description>Direct mode disable</description>
18765 <bitOffset>2</bitOffset>
18766 <bitWidth>1</bitWidth>
18767 <access>read-write</access>
18768 </field>
18769 <field>
18770 <name>FTH</name>
18771 <description>FIFO threshold selection</description>
18772 <bitOffset>0</bitOffset>
18773 <bitWidth>2</bitWidth>
18774 <access>read-write</access>
18775 </field>
18776 </fields>
18777 </register>
18778 <register>
18779 <name>S3CR</name>
18780 <displayName>S3CR</displayName>
18781 <description>stream x configuration
18782 register</description>
18783 <addressOffset>0x58</addressOffset>
18784 <size>0x20</size>
18785 <access>read-write</access>
18786 <resetValue>0x00000000</resetValue>
18787 <fields>
18788 <field>
18789 <name>CHSEL</name>
18790 <description>Channel selection</description>
18791 <bitOffset>25</bitOffset>
18792 <bitWidth>3</bitWidth>
18793 </field>
18794 <field>
18795 <name>MBURST</name>
18796 <description>Memory burst transfer
18797 configuration</description>
18798 <bitOffset>23</bitOffset>
18799 <bitWidth>2</bitWidth>
18800 </field>
18801 <field>
18802 <name>PBURST</name>
18803 <description>Peripheral burst transfer
18804 configuration</description>
18805 <bitOffset>21</bitOffset>
18806 <bitWidth>2</bitWidth>
18807 </field>
18808 <field>
18809 <name>ACK</name>
18810 <description>ACK</description>
18811 <bitOffset>20</bitOffset>
18812 <bitWidth>1</bitWidth>
18813 </field>
18814 <field>
18815 <name>CT</name>
18816 <description>Current target (only in double buffer
18817 mode)</description>
18818 <bitOffset>19</bitOffset>
18819 <bitWidth>1</bitWidth>
18820 </field>
18821 <field>
18822 <name>DBM</name>
18823 <description>Double buffer mode</description>
18824 <bitOffset>18</bitOffset>
18825 <bitWidth>1</bitWidth>
18826 </field>
18827 <field>
18828 <name>PL</name>
18829 <description>Priority level</description>
18830 <bitOffset>16</bitOffset>
18831 <bitWidth>2</bitWidth>
18832 </field>
18833 <field>
18834 <name>PINCOS</name>
18835 <description>Peripheral increment offset
18836 size</description>
18837 <bitOffset>15</bitOffset>
18838 <bitWidth>1</bitWidth>
18839 </field>
18840 <field>
18841 <name>MSIZE</name>
18842 <description>Memory data size</description>
18843 <bitOffset>13</bitOffset>
18844 <bitWidth>2</bitWidth>
18845 </field>
18846 <field>
18847 <name>PSIZE</name>
18848 <description>Peripheral data size</description>
18849 <bitOffset>11</bitOffset>
18850 <bitWidth>2</bitWidth>
18851 </field>
18852 <field>
18853 <name>MINC</name>
18854 <description>Memory increment mode</description>
18855 <bitOffset>10</bitOffset>
18856 <bitWidth>1</bitWidth>
18857 </field>
18858 <field>
18859 <name>PINC</name>
18860 <description>Peripheral increment mode</description>
18861 <bitOffset>9</bitOffset>
18862 <bitWidth>1</bitWidth>
18863 </field>
18864 <field>
18865 <name>CIRC</name>
18866 <description>Circular mode</description>
18867 <bitOffset>8</bitOffset>
18868 <bitWidth>1</bitWidth>
18869 </field>
18870 <field>
18871 <name>DIR</name>
18872 <description>Data transfer direction</description>
18873 <bitOffset>6</bitOffset>
18874 <bitWidth>2</bitWidth>
18875 </field>
18876 <field>
18877 <name>PFCTRL</name>
18878 <description>Peripheral flow controller</description>
18879 <bitOffset>5</bitOffset>
18880 <bitWidth>1</bitWidth>
18881 </field>
18882 <field>
18883 <name>TCIE</name>
18884 <description>Transfer complete interrupt
18885 enable</description>
18886 <bitOffset>4</bitOffset>
18887 <bitWidth>1</bitWidth>
18888 </field>
18889 <field>
18890 <name>HTIE</name>
18891 <description>Half transfer interrupt
18892 enable</description>
18893 <bitOffset>3</bitOffset>
18894 <bitWidth>1</bitWidth>
18895 </field>
18896 <field>
18897 <name>TEIE</name>
18898 <description>Transfer error interrupt
18899 enable</description>
18900 <bitOffset>2</bitOffset>
18901 <bitWidth>1</bitWidth>
18902 </field>
18903 <field>
18904 <name>DMEIE</name>
18905 <description>Direct mode error interrupt
18906 enable</description>
18907 <bitOffset>1</bitOffset>
18908 <bitWidth>1</bitWidth>
18909 </field>
18910 <field>
18911 <name>EN</name>
18912 <description>Stream enable / flag stream ready when
18913 read low</description>
18914 <bitOffset>0</bitOffset>
18915 <bitWidth>1</bitWidth>
18916 </field>
18917 </fields>
18918 </register>
18919 <register>
18920 <name>S3NDTR</name>
18921 <displayName>S3NDTR</displayName>
18922 <description>stream x number of data
18923 register</description>
18924 <addressOffset>0x5C</addressOffset>
18925 <size>0x20</size>
18926 <access>read-write</access>
18927 <resetValue>0x00000000</resetValue>
18928 <fields>
18929 <field>
18930 <name>NDT</name>
18931 <description>Number of data items to
18932 transfer</description>
18933 <bitOffset>0</bitOffset>
18934 <bitWidth>16</bitWidth>
18935 </field>
18936 </fields>
18937 </register>
18938 <register>
18939 <name>S3PAR</name>
18940 <displayName>S3PAR</displayName>
18941 <description>stream x peripheral address
18942 register</description>
18943 <addressOffset>0x60</addressOffset>
18944 <size>0x20</size>
18945 <access>read-write</access>
18946 <resetValue>0x00000000</resetValue>
18947 <fields>
18948 <field>
18949 <name>PA</name>
18950 <description>Peripheral address</description>
18951 <bitOffset>0</bitOffset>
18952 <bitWidth>32</bitWidth>
18953 </field>
18954 </fields>
18955 </register>
18956 <register>
18957 <name>S3M0AR</name>
18958 <displayName>S3M0AR</displayName>
18959 <description>stream x memory 0 address
18960 register</description>
18961 <addressOffset>0x64</addressOffset>
18962 <size>0x20</size>
18963 <access>read-write</access>
18964 <resetValue>0x00000000</resetValue>
18965 <fields>
18966 <field>
18967 <name>M0A</name>
18968 <description>Memory 0 address</description>
18969 <bitOffset>0</bitOffset>
18970 <bitWidth>32</bitWidth>
18971 </field>
18972 </fields>
18973 </register>
18974 <register>
18975 <name>S3M1AR</name>
18976 <displayName>S3M1AR</displayName>
18977 <description>stream x memory 1 address
18978 register</description>
18979 <addressOffset>0x68</addressOffset>
18980 <size>0x20</size>
18981 <access>read-write</access>
18982 <resetValue>0x00000000</resetValue>
18983 <fields>
18984 <field>
18985 <name>M1A</name>
18986 <description>Memory 1 address (used in case of Double
18987 buffer mode)</description>
18988 <bitOffset>0</bitOffset>
18989 <bitWidth>32</bitWidth>
18990 </field>
18991 </fields>
18992 </register>
18993 <register>
18994 <name>S3FCR</name>
18995 <displayName>S3FCR</displayName>
18996 <description>stream x FIFO control register</description>
18997 <addressOffset>0x6C</addressOffset>
18998 <size>0x20</size>
18999 <resetValue>0x00000021</resetValue>
19000 <fields>
19001 <field>
19002 <name>FEIE</name>
19003 <description>FIFO error interrupt
19004 enable</description>
19005 <bitOffset>7</bitOffset>
19006 <bitWidth>1</bitWidth>
19007 <access>read-write</access>
19008 </field>
19009 <field>
19010 <name>FS</name>
19011 <description>FIFO status</description>
19012 <bitOffset>3</bitOffset>
19013 <bitWidth>3</bitWidth>
19014 <access>read-only</access>
19015 </field>
19016 <field>
19017 <name>DMDIS</name>
19018 <description>Direct mode disable</description>
19019 <bitOffset>2</bitOffset>
19020 <bitWidth>1</bitWidth>
19021 <access>read-write</access>
19022 </field>
19023 <field>
19024 <name>FTH</name>
19025 <description>FIFO threshold selection</description>
19026 <bitOffset>0</bitOffset>
19027 <bitWidth>2</bitWidth>
19028 <access>read-write</access>
19029 </field>
19030 </fields>
19031 </register>
19032 <register>
19033 <name>S4CR</name>
19034 <displayName>S4CR</displayName>
19035 <description>stream x configuration
19036 register</description>
19037 <addressOffset>0x70</addressOffset>
19038 <size>0x20</size>
19039 <access>read-write</access>
19040 <resetValue>0x00000000</resetValue>
19041 <fields>
19042 <field>
19043 <name>CHSEL</name>
19044 <description>Channel selection</description>
19045 <bitOffset>25</bitOffset>
19046 <bitWidth>3</bitWidth>
19047 </field>
19048 <field>
19049 <name>MBURST</name>
19050 <description>Memory burst transfer
19051 configuration</description>
19052 <bitOffset>23</bitOffset>
19053 <bitWidth>2</bitWidth>
19054 </field>
19055 <field>
19056 <name>PBURST</name>
19057 <description>Peripheral burst transfer
19058 configuration</description>
19059 <bitOffset>21</bitOffset>
19060 <bitWidth>2</bitWidth>
19061 </field>
19062 <field>
19063 <name>ACK</name>
19064 <description>ACK</description>
19065 <bitOffset>20</bitOffset>
19066 <bitWidth>1</bitWidth>
19067 </field>
19068 <field>
19069 <name>CT</name>
19070 <description>Current target (only in double buffer
19071 mode)</description>
19072 <bitOffset>19</bitOffset>
19073 <bitWidth>1</bitWidth>
19074 </field>
19075 <field>
19076 <name>DBM</name>
19077 <description>Double buffer mode</description>
19078 <bitOffset>18</bitOffset>
19079 <bitWidth>1</bitWidth>
19080 </field>
19081 <field>
19082 <name>PL</name>
19083 <description>Priority level</description>
19084 <bitOffset>16</bitOffset>
19085 <bitWidth>2</bitWidth>
19086 </field>
19087 <field>
19088 <name>PINCOS</name>
19089 <description>Peripheral increment offset
19090 size</description>
19091 <bitOffset>15</bitOffset>
19092 <bitWidth>1</bitWidth>
19093 </field>
19094 <field>
19095 <name>MSIZE</name>
19096 <description>Memory data size</description>
19097 <bitOffset>13</bitOffset>
19098 <bitWidth>2</bitWidth>
19099 </field>
19100 <field>
19101 <name>PSIZE</name>
19102 <description>Peripheral data size</description>
19103 <bitOffset>11</bitOffset>
19104 <bitWidth>2</bitWidth>
19105 </field>
19106 <field>
19107 <name>MINC</name>
19108 <description>Memory increment mode</description>
19109 <bitOffset>10</bitOffset>
19110 <bitWidth>1</bitWidth>
19111 </field>
19112 <field>
19113 <name>PINC</name>
19114 <description>Peripheral increment mode</description>
19115 <bitOffset>9</bitOffset>
19116 <bitWidth>1</bitWidth>
19117 </field>
19118 <field>
19119 <name>CIRC</name>
19120 <description>Circular mode</description>
19121 <bitOffset>8</bitOffset>
19122 <bitWidth>1</bitWidth>
19123 </field>
19124 <field>
19125 <name>DIR</name>
19126 <description>Data transfer direction</description>
19127 <bitOffset>6</bitOffset>
19128 <bitWidth>2</bitWidth>
19129 </field>
19130 <field>
19131 <name>PFCTRL</name>
19132 <description>Peripheral flow controller</description>
19133 <bitOffset>5</bitOffset>
19134 <bitWidth>1</bitWidth>
19135 </field>
19136 <field>
19137 <name>TCIE</name>
19138 <description>Transfer complete interrupt
19139 enable</description>
19140 <bitOffset>4</bitOffset>
19141 <bitWidth>1</bitWidth>
19142 </field>
19143 <field>
19144 <name>HTIE</name>
19145 <description>Half transfer interrupt
19146 enable</description>
19147 <bitOffset>3</bitOffset>
19148 <bitWidth>1</bitWidth>
19149 </field>
19150 <field>
19151 <name>TEIE</name>
19152 <description>Transfer error interrupt
19153 enable</description>
19154 <bitOffset>2</bitOffset>
19155 <bitWidth>1</bitWidth>
19156 </field>
19157 <field>
19158 <name>DMEIE</name>
19159 <description>Direct mode error interrupt
19160 enable</description>
19161 <bitOffset>1</bitOffset>
19162 <bitWidth>1</bitWidth>
19163 </field>
19164 <field>
19165 <name>EN</name>
19166 <description>Stream enable / flag stream ready when
19167 read low</description>
19168 <bitOffset>0</bitOffset>
19169 <bitWidth>1</bitWidth>
19170 </field>
19171 </fields>
19172 </register>
19173 <register>
19174 <name>S4NDTR</name>
19175 <displayName>S4NDTR</displayName>
19176 <description>stream x number of data
19177 register</description>
19178 <addressOffset>0x74</addressOffset>
19179 <size>0x20</size>
19180 <access>read-write</access>
19181 <resetValue>0x00000000</resetValue>
19182 <fields>
19183 <field>
19184 <name>NDT</name>
19185 <description>Number of data items to
19186 transfer</description>
19187 <bitOffset>0</bitOffset>
19188 <bitWidth>16</bitWidth>
19189 </field>
19190 </fields>
19191 </register>
19192 <register>
19193 <name>S4PAR</name>
19194 <displayName>S4PAR</displayName>
19195 <description>stream x peripheral address
19196 register</description>
19197 <addressOffset>0x78</addressOffset>
19198 <size>0x20</size>
19199 <access>read-write</access>
19200 <resetValue>0x00000000</resetValue>
19201 <fields>
19202 <field>
19203 <name>PA</name>
19204 <description>Peripheral address</description>
19205 <bitOffset>0</bitOffset>
19206 <bitWidth>32</bitWidth>
19207 </field>
19208 </fields>
19209 </register>
19210 <register>
19211 <name>S4M0AR</name>
19212 <displayName>S4M0AR</displayName>
19213 <description>stream x memory 0 address
19214 register</description>
19215 <addressOffset>0x7C</addressOffset>
19216 <size>0x20</size>
19217 <access>read-write</access>
19218 <resetValue>0x00000000</resetValue>
19219 <fields>
19220 <field>
19221 <name>M0A</name>
19222 <description>Memory 0 address</description>
19223 <bitOffset>0</bitOffset>
19224 <bitWidth>32</bitWidth>
19225 </field>
19226 </fields>
19227 </register>
19228 <register>
19229 <name>S4M1AR</name>
19230 <displayName>S4M1AR</displayName>
19231 <description>stream x memory 1 address
19232 register</description>
19233 <addressOffset>0x80</addressOffset>
19234 <size>0x20</size>
19235 <access>read-write</access>
19236 <resetValue>0x00000000</resetValue>
19237 <fields>
19238 <field>
19239 <name>M1A</name>
19240 <description>Memory 1 address (used in case of Double
19241 buffer mode)</description>
19242 <bitOffset>0</bitOffset>
19243 <bitWidth>32</bitWidth>
19244 </field>
19245 </fields>
19246 </register>
19247 <register>
19248 <name>S4FCR</name>
19249 <displayName>S4FCR</displayName>
19250 <description>stream x FIFO control register</description>
19251 <addressOffset>0x84</addressOffset>
19252 <size>0x20</size>
19253 <resetValue>0x00000021</resetValue>
19254 <fields>
19255 <field>
19256 <name>FEIE</name>
19257 <description>FIFO error interrupt
19258 enable</description>
19259 <bitOffset>7</bitOffset>
19260 <bitWidth>1</bitWidth>
19261 <access>read-write</access>
19262 </field>
19263 <field>
19264 <name>FS</name>
19265 <description>FIFO status</description>
19266 <bitOffset>3</bitOffset>
19267 <bitWidth>3</bitWidth>
19268 <access>read-only</access>
19269 </field>
19270 <field>
19271 <name>DMDIS</name>
19272 <description>Direct mode disable</description>
19273 <bitOffset>2</bitOffset>
19274 <bitWidth>1</bitWidth>
19275 <access>read-write</access>
19276 </field>
19277 <field>
19278 <name>FTH</name>
19279 <description>FIFO threshold selection</description>
19280 <bitOffset>0</bitOffset>
19281 <bitWidth>2</bitWidth>
19282 <access>read-write</access>
19283 </field>
19284 </fields>
19285 </register>
19286 <register>
19287 <name>S5CR</name>
19288 <displayName>S5CR</displayName>
19289 <description>stream x configuration
19290 register</description>
19291 <addressOffset>0x88</addressOffset>
19292 <size>0x20</size>
19293 <access>read-write</access>
19294 <resetValue>0x00000000</resetValue>
19295 <fields>
19296 <field>
19297 <name>CHSEL</name>
19298 <description>Channel selection</description>
19299 <bitOffset>25</bitOffset>
19300 <bitWidth>3</bitWidth>
19301 </field>
19302 <field>
19303 <name>MBURST</name>
19304 <description>Memory burst transfer
19305 configuration</description>
19306 <bitOffset>23</bitOffset>
19307 <bitWidth>2</bitWidth>
19308 </field>
19309 <field>
19310 <name>PBURST</name>
19311 <description>Peripheral burst transfer
19312 configuration</description>
19313 <bitOffset>21</bitOffset>
19314 <bitWidth>2</bitWidth>
19315 </field>
19316 <field>
19317 <name>ACK</name>
19318 <description>ACK</description>
19319 <bitOffset>20</bitOffset>
19320 <bitWidth>1</bitWidth>
19321 </field>
19322 <field>
19323 <name>CT</name>
19324 <description>Current target (only in double buffer
19325 mode)</description>
19326 <bitOffset>19</bitOffset>
19327 <bitWidth>1</bitWidth>
19328 </field>
19329 <field>
19330 <name>DBM</name>
19331 <description>Double buffer mode</description>
19332 <bitOffset>18</bitOffset>
19333 <bitWidth>1</bitWidth>
19334 </field>
19335 <field>
19336 <name>PL</name>
19337 <description>Priority level</description>
19338 <bitOffset>16</bitOffset>
19339 <bitWidth>2</bitWidth>
19340 </field>
19341 <field>
19342 <name>PINCOS</name>
19343 <description>Peripheral increment offset
19344 size</description>
19345 <bitOffset>15</bitOffset>
19346 <bitWidth>1</bitWidth>
19347 </field>
19348 <field>
19349 <name>MSIZE</name>
19350 <description>Memory data size</description>
19351 <bitOffset>13</bitOffset>
19352 <bitWidth>2</bitWidth>
19353 </field>
19354 <field>
19355 <name>PSIZE</name>
19356 <description>Peripheral data size</description>
19357 <bitOffset>11</bitOffset>
19358 <bitWidth>2</bitWidth>
19359 </field>
19360 <field>
19361 <name>MINC</name>
19362 <description>Memory increment mode</description>
19363 <bitOffset>10</bitOffset>
19364 <bitWidth>1</bitWidth>
19365 </field>
19366 <field>
19367 <name>PINC</name>
19368 <description>Peripheral increment mode</description>
19369 <bitOffset>9</bitOffset>
19370 <bitWidth>1</bitWidth>
19371 </field>
19372 <field>
19373 <name>CIRC</name>
19374 <description>Circular mode</description>
19375 <bitOffset>8</bitOffset>
19376 <bitWidth>1</bitWidth>
19377 </field>
19378 <field>
19379 <name>DIR</name>
19380 <description>Data transfer direction</description>
19381 <bitOffset>6</bitOffset>
19382 <bitWidth>2</bitWidth>
19383 </field>
19384 <field>
19385 <name>PFCTRL</name>
19386 <description>Peripheral flow controller</description>
19387 <bitOffset>5</bitOffset>
19388 <bitWidth>1</bitWidth>
19389 </field>
19390 <field>
19391 <name>TCIE</name>
19392 <description>Transfer complete interrupt
19393 enable</description>
19394 <bitOffset>4</bitOffset>
19395 <bitWidth>1</bitWidth>
19396 </field>
19397 <field>
19398 <name>HTIE</name>
19399 <description>Half transfer interrupt
19400 enable</description>
19401 <bitOffset>3</bitOffset>
19402 <bitWidth>1</bitWidth>
19403 </field>
19404 <field>
19405 <name>TEIE</name>
19406 <description>Transfer error interrupt
19407 enable</description>
19408 <bitOffset>2</bitOffset>
19409 <bitWidth>1</bitWidth>
19410 </field>
19411 <field>
19412 <name>DMEIE</name>
19413 <description>Direct mode error interrupt
19414 enable</description>
19415 <bitOffset>1</bitOffset>
19416 <bitWidth>1</bitWidth>
19417 </field>
19418 <field>
19419 <name>EN</name>
19420 <description>Stream enable / flag stream ready when
19421 read low</description>
19422 <bitOffset>0</bitOffset>
19423 <bitWidth>1</bitWidth>
19424 </field>
19425 </fields>
19426 </register>
19427 <register>
19428 <name>S5NDTR</name>
19429 <displayName>S5NDTR</displayName>
19430 <description>stream x number of data
19431 register</description>
19432 <addressOffset>0x8C</addressOffset>
19433 <size>0x20</size>
19434 <access>read-write</access>
19435 <resetValue>0x00000000</resetValue>
19436 <fields>
19437 <field>
19438 <name>NDT</name>
19439 <description>Number of data items to
19440 transfer</description>
19441 <bitOffset>0</bitOffset>
19442 <bitWidth>16</bitWidth>
19443 </field>
19444 </fields>
19445 </register>
19446 <register>
19447 <name>S5PAR</name>
19448 <displayName>S5PAR</displayName>
19449 <description>stream x peripheral address
19450 register</description>
19451 <addressOffset>0x90</addressOffset>
19452 <size>0x20</size>
19453 <access>read-write</access>
19454 <resetValue>0x00000000</resetValue>
19455 <fields>
19456 <field>
19457 <name>PA</name>
19458 <description>Peripheral address</description>
19459 <bitOffset>0</bitOffset>
19460 <bitWidth>32</bitWidth>
19461 </field>
19462 </fields>
19463 </register>
19464 <register>
19465 <name>S5M0AR</name>
19466 <displayName>S5M0AR</displayName>
19467 <description>stream x memory 0 address
19468 register</description>
19469 <addressOffset>0x94</addressOffset>
19470 <size>0x20</size>
19471 <access>read-write</access>
19472 <resetValue>0x00000000</resetValue>
19473 <fields>
19474 <field>
19475 <name>M0A</name>
19476 <description>Memory 0 address</description>
19477 <bitOffset>0</bitOffset>
19478 <bitWidth>32</bitWidth>
19479 </field>
19480 </fields>
19481 </register>
19482 <register>
19483 <name>S5M1AR</name>
19484 <displayName>S5M1AR</displayName>
19485 <description>stream x memory 1 address
19486 register</description>
19487 <addressOffset>0x98</addressOffset>
19488 <size>0x20</size>
19489 <access>read-write</access>
19490 <resetValue>0x00000000</resetValue>
19491 <fields>
19492 <field>
19493 <name>M1A</name>
19494 <description>Memory 1 address (used in case of Double
19495 buffer mode)</description>
19496 <bitOffset>0</bitOffset>
19497 <bitWidth>32</bitWidth>
19498 </field>
19499 </fields>
19500 </register>
19501 <register>
19502 <name>S5FCR</name>
19503 <displayName>S5FCR</displayName>
19504 <description>stream x FIFO control register</description>
19505 <addressOffset>0x9C</addressOffset>
19506 <size>0x20</size>
19507 <resetValue>0x00000021</resetValue>
19508 <fields>
19509 <field>
19510 <name>FEIE</name>
19511 <description>FIFO error interrupt
19512 enable</description>
19513 <bitOffset>7</bitOffset>
19514 <bitWidth>1</bitWidth>
19515 <access>read-write</access>
19516 </field>
19517 <field>
19518 <name>FS</name>
19519 <description>FIFO status</description>
19520 <bitOffset>3</bitOffset>
19521 <bitWidth>3</bitWidth>
19522 <access>read-only</access>
19523 </field>
19524 <field>
19525 <name>DMDIS</name>
19526 <description>Direct mode disable</description>
19527 <bitOffset>2</bitOffset>
19528 <bitWidth>1</bitWidth>
19529 <access>read-write</access>
19530 </field>
19531 <field>
19532 <name>FTH</name>
19533 <description>FIFO threshold selection</description>
19534 <bitOffset>0</bitOffset>
19535 <bitWidth>2</bitWidth>
19536 <access>read-write</access>
19537 </field>
19538 </fields>
19539 </register>
19540 <register>
19541 <name>S6CR</name>
19542 <displayName>S6CR</displayName>
19543 <description>stream x configuration
19544 register</description>
19545 <addressOffset>0xA0</addressOffset>
19546 <size>0x20</size>
19547 <access>read-write</access>
19548 <resetValue>0x00000000</resetValue>
19549 <fields>
19550 <field>
19551 <name>CHSEL</name>
19552 <description>Channel selection</description>
19553 <bitOffset>25</bitOffset>
19554 <bitWidth>3</bitWidth>
19555 </field>
19556 <field>
19557 <name>MBURST</name>
19558 <description>Memory burst transfer
19559 configuration</description>
19560 <bitOffset>23</bitOffset>
19561 <bitWidth>2</bitWidth>
19562 </field>
19563 <field>
19564 <name>PBURST</name>
19565 <description>Peripheral burst transfer
19566 configuration</description>
19567 <bitOffset>21</bitOffset>
19568 <bitWidth>2</bitWidth>
19569 </field>
19570 <field>
19571 <name>ACK</name>
19572 <description>ACK</description>
19573 <bitOffset>20</bitOffset>
19574 <bitWidth>1</bitWidth>
19575 </field>
19576 <field>
19577 <name>CT</name>
19578 <description>Current target (only in double buffer
19579 mode)</description>
19580 <bitOffset>19</bitOffset>
19581 <bitWidth>1</bitWidth>
19582 </field>
19583 <field>
19584 <name>DBM</name>
19585 <description>Double buffer mode</description>
19586 <bitOffset>18</bitOffset>
19587 <bitWidth>1</bitWidth>
19588 </field>
19589 <field>
19590 <name>PL</name>
19591 <description>Priority level</description>
19592 <bitOffset>16</bitOffset>
19593 <bitWidth>2</bitWidth>
19594 </field>
19595 <field>
19596 <name>PINCOS</name>
19597 <description>Peripheral increment offset
19598 size</description>
19599 <bitOffset>15</bitOffset>
19600 <bitWidth>1</bitWidth>
19601 </field>
19602 <field>
19603 <name>MSIZE</name>
19604 <description>Memory data size</description>
19605 <bitOffset>13</bitOffset>
19606 <bitWidth>2</bitWidth>
19607 </field>
19608 <field>
19609 <name>PSIZE</name>
19610 <description>Peripheral data size</description>
19611 <bitOffset>11</bitOffset>
19612 <bitWidth>2</bitWidth>
19613 </field>
19614 <field>
19615 <name>MINC</name>
19616 <description>Memory increment mode</description>
19617 <bitOffset>10</bitOffset>
19618 <bitWidth>1</bitWidth>
19619 </field>
19620 <field>
19621 <name>PINC</name>
19622 <description>Peripheral increment mode</description>
19623 <bitOffset>9</bitOffset>
19624 <bitWidth>1</bitWidth>
19625 </field>
19626 <field>
19627 <name>CIRC</name>
19628 <description>Circular mode</description>
19629 <bitOffset>8</bitOffset>
19630 <bitWidth>1</bitWidth>
19631 </field>
19632 <field>
19633 <name>DIR</name>
19634 <description>Data transfer direction</description>
19635 <bitOffset>6</bitOffset>
19636 <bitWidth>2</bitWidth>
19637 </field>
19638 <field>
19639 <name>PFCTRL</name>
19640 <description>Peripheral flow controller</description>
19641 <bitOffset>5</bitOffset>
19642 <bitWidth>1</bitWidth>
19643 </field>
19644 <field>
19645 <name>TCIE</name>
19646 <description>Transfer complete interrupt
19647 enable</description>
19648 <bitOffset>4</bitOffset>
19649 <bitWidth>1</bitWidth>
19650 </field>
19651 <field>
19652 <name>HTIE</name>
19653 <description>Half transfer interrupt
19654 enable</description>
19655 <bitOffset>3</bitOffset>
19656 <bitWidth>1</bitWidth>
19657 </field>
19658 <field>
19659 <name>TEIE</name>
19660 <description>Transfer error interrupt
19661 enable</description>
19662 <bitOffset>2</bitOffset>
19663 <bitWidth>1</bitWidth>
19664 </field>
19665 <field>
19666 <name>DMEIE</name>
19667 <description>Direct mode error interrupt
19668 enable</description>
19669 <bitOffset>1</bitOffset>
19670 <bitWidth>1</bitWidth>
19671 </field>
19672 <field>
19673 <name>EN</name>
19674 <description>Stream enable / flag stream ready when
19675 read low</description>
19676 <bitOffset>0</bitOffset>
19677 <bitWidth>1</bitWidth>
19678 </field>
19679 </fields>
19680 </register>
19681 <register>
19682 <name>S6NDTR</name>
19683 <displayName>S6NDTR</displayName>
19684 <description>stream x number of data
19685 register</description>
19686 <addressOffset>0xA4</addressOffset>
19687 <size>0x20</size>
19688 <access>read-write</access>
19689 <resetValue>0x00000000</resetValue>
19690 <fields>
19691 <field>
19692 <name>NDT</name>
19693 <description>Number of data items to
19694 transfer</description>
19695 <bitOffset>0</bitOffset>
19696 <bitWidth>16</bitWidth>
19697 </field>
19698 </fields>
19699 </register>
19700 <register>
19701 <name>S6PAR</name>
19702 <displayName>S6PAR</displayName>
19703 <description>stream x peripheral address
19704 register</description>
19705 <addressOffset>0xA8</addressOffset>
19706 <size>0x20</size>
19707 <access>read-write</access>
19708 <resetValue>0x00000000</resetValue>
19709 <fields>
19710 <field>
19711 <name>PA</name>
19712 <description>Peripheral address</description>
19713 <bitOffset>0</bitOffset>
19714 <bitWidth>32</bitWidth>
19715 </field>
19716 </fields>
19717 </register>
19718 <register>
19719 <name>S6M0AR</name>
19720 <displayName>S6M0AR</displayName>
19721 <description>stream x memory 0 address
19722 register</description>
19723 <addressOffset>0xAC</addressOffset>
19724 <size>0x20</size>
19725 <access>read-write</access>
19726 <resetValue>0x00000000</resetValue>
19727 <fields>
19728 <field>
19729 <name>M0A</name>
19730 <description>Memory 0 address</description>
19731 <bitOffset>0</bitOffset>
19732 <bitWidth>32</bitWidth>
19733 </field>
19734 </fields>
19735 </register>
19736 <register>
19737 <name>S6M1AR</name>
19738 <displayName>S6M1AR</displayName>
19739 <description>stream x memory 1 address
19740 register</description>
19741 <addressOffset>0xB0</addressOffset>
19742 <size>0x20</size>
19743 <access>read-write</access>
19744 <resetValue>0x00000000</resetValue>
19745 <fields>
19746 <field>
19747 <name>M1A</name>
19748 <description>Memory 1 address (used in case of Double
19749 buffer mode)</description>
19750 <bitOffset>0</bitOffset>
19751 <bitWidth>32</bitWidth>
19752 </field>
19753 </fields>
19754 </register>
19755 <register>
19756 <name>S6FCR</name>
19757 <displayName>S6FCR</displayName>
19758 <description>stream x FIFO control register</description>
19759 <addressOffset>0xB4</addressOffset>
19760 <size>0x20</size>
19761 <resetValue>0x00000021</resetValue>
19762 <fields>
19763 <field>
19764 <name>FEIE</name>
19765 <description>FIFO error interrupt
19766 enable</description>
19767 <bitOffset>7</bitOffset>
19768 <bitWidth>1</bitWidth>
19769 <access>read-write</access>
19770 </field>
19771 <field>
19772 <name>FS</name>
19773 <description>FIFO status</description>
19774 <bitOffset>3</bitOffset>
19775 <bitWidth>3</bitWidth>
19776 <access>read-only</access>
19777 </field>
19778 <field>
19779 <name>DMDIS</name>
19780 <description>Direct mode disable</description>
19781 <bitOffset>2</bitOffset>
19782 <bitWidth>1</bitWidth>
19783 <access>read-write</access>
19784 </field>
19785 <field>
19786 <name>FTH</name>
19787 <description>FIFO threshold selection</description>
19788 <bitOffset>0</bitOffset>
19789 <bitWidth>2</bitWidth>
19790 <access>read-write</access>
19791 </field>
19792 </fields>
19793 </register>
19794 <register>
19795 <name>S7CR</name>
19796 <displayName>S7CR</displayName>
19797 <description>stream x configuration
19798 register</description>
19799 <addressOffset>0xB8</addressOffset>
19800 <size>0x20</size>
19801 <access>read-write</access>
19802 <resetValue>0x00000000</resetValue>
19803 <fields>
19804 <field>
19805 <name>CHSEL</name>
19806 <description>Channel selection</description>
19807 <bitOffset>25</bitOffset>
19808 <bitWidth>3</bitWidth>
19809 </field>
19810 <field>
19811 <name>MBURST</name>
19812 <description>Memory burst transfer
19813 configuration</description>
19814 <bitOffset>23</bitOffset>
19815 <bitWidth>2</bitWidth>
19816 </field>
19817 <field>
19818 <name>PBURST</name>
19819 <description>Peripheral burst transfer
19820 configuration</description>
19821 <bitOffset>21</bitOffset>
19822 <bitWidth>2</bitWidth>
19823 </field>
19824 <field>
19825 <name>ACK</name>
19826 <description>ACK</description>
19827 <bitOffset>20</bitOffset>
19828 <bitWidth>1</bitWidth>
19829 </field>
19830 <field>
19831 <name>CT</name>
19832 <description>Current target (only in double buffer
19833 mode)</description>
19834 <bitOffset>19</bitOffset>
19835 <bitWidth>1</bitWidth>
19836 </field>
19837 <field>
19838 <name>DBM</name>
19839 <description>Double buffer mode</description>
19840 <bitOffset>18</bitOffset>
19841 <bitWidth>1</bitWidth>
19842 </field>
19843 <field>
19844 <name>PL</name>
19845 <description>Priority level</description>
19846 <bitOffset>16</bitOffset>
19847 <bitWidth>2</bitWidth>
19848 </field>
19849 <field>
19850 <name>PINCOS</name>
19851 <description>Peripheral increment offset
19852 size</description>
19853 <bitOffset>15</bitOffset>
19854 <bitWidth>1</bitWidth>
19855 </field>
19856 <field>
19857 <name>MSIZE</name>
19858 <description>Memory data size</description>
19859 <bitOffset>13</bitOffset>
19860 <bitWidth>2</bitWidth>
19861 </field>
19862 <field>
19863 <name>PSIZE</name>
19864 <description>Peripheral data size</description>
19865 <bitOffset>11</bitOffset>
19866 <bitWidth>2</bitWidth>
19867 </field>
19868 <field>
19869 <name>MINC</name>
19870 <description>Memory increment mode</description>
19871 <bitOffset>10</bitOffset>
19872 <bitWidth>1</bitWidth>
19873 </field>
19874 <field>
19875 <name>PINC</name>
19876 <description>Peripheral increment mode</description>
19877 <bitOffset>9</bitOffset>
19878 <bitWidth>1</bitWidth>
19879 </field>
19880 <field>
19881 <name>CIRC</name>
19882 <description>Circular mode</description>
19883 <bitOffset>8</bitOffset>
19884 <bitWidth>1</bitWidth>
19885 </field>
19886 <field>
19887 <name>DIR</name>
19888 <description>Data transfer direction</description>
19889 <bitOffset>6</bitOffset>
19890 <bitWidth>2</bitWidth>
19891 </field>
19892 <field>
19893 <name>PFCTRL</name>
19894 <description>Peripheral flow controller</description>
19895 <bitOffset>5</bitOffset>
19896 <bitWidth>1</bitWidth>
19897 </field>
19898 <field>
19899 <name>TCIE</name>
19900 <description>Transfer complete interrupt
19901 enable</description>
19902 <bitOffset>4</bitOffset>
19903 <bitWidth>1</bitWidth>
19904 </field>
19905 <field>
19906 <name>HTIE</name>
19907 <description>Half transfer interrupt
19908 enable</description>
19909 <bitOffset>3</bitOffset>
19910 <bitWidth>1</bitWidth>
19911 </field>
19912 <field>
19913 <name>TEIE</name>
19914 <description>Transfer error interrupt
19915 enable</description>
19916 <bitOffset>2</bitOffset>
19917 <bitWidth>1</bitWidth>
19918 </field>
19919 <field>
19920 <name>DMEIE</name>
19921 <description>Direct mode error interrupt
19922 enable</description>
19923 <bitOffset>1</bitOffset>
19924 <bitWidth>1</bitWidth>
19925 </field>
19926 <field>
19927 <name>EN</name>
19928 <description>Stream enable / flag stream ready when
19929 read low</description>
19930 <bitOffset>0</bitOffset>
19931 <bitWidth>1</bitWidth>
19932 </field>
19933 </fields>
19934 </register>
19935 <register>
19936 <name>S7NDTR</name>
19937 <displayName>S7NDTR</displayName>
19938 <description>stream x number of data
19939 register</description>
19940 <addressOffset>0xBC</addressOffset>
19941 <size>0x20</size>
19942 <access>read-write</access>
19943 <resetValue>0x00000000</resetValue>
19944 <fields>
19945 <field>
19946 <name>NDT</name>
19947 <description>Number of data items to
19948 transfer</description>
19949 <bitOffset>0</bitOffset>
19950 <bitWidth>16</bitWidth>
19951 </field>
19952 </fields>
19953 </register>
19954 <register>
19955 <name>S7PAR</name>
19956 <displayName>S7PAR</displayName>
19957 <description>stream x peripheral address
19958 register</description>
19959 <addressOffset>0xC0</addressOffset>
19960 <size>0x20</size>
19961 <access>read-write</access>
19962 <resetValue>0x00000000</resetValue>
19963 <fields>
19964 <field>
19965 <name>PA</name>
19966 <description>Peripheral address</description>
19967 <bitOffset>0</bitOffset>
19968 <bitWidth>32</bitWidth>
19969 </field>
19970 </fields>
19971 </register>
19972 <register>
19973 <name>S7M0AR</name>
19974 <displayName>S7M0AR</displayName>
19975 <description>stream x memory 0 address
19976 register</description>
19977 <addressOffset>0xC4</addressOffset>
19978 <size>0x20</size>
19979 <access>read-write</access>
19980 <resetValue>0x00000000</resetValue>
19981 <fields>
19982 <field>
19983 <name>M0A</name>
19984 <description>Memory 0 address</description>
19985 <bitOffset>0</bitOffset>
19986 <bitWidth>32</bitWidth>
19987 </field>
19988 </fields>
19989 </register>
19990 <register>
19991 <name>S7M1AR</name>
19992 <displayName>S7M1AR</displayName>
19993 <description>stream x memory 1 address
19994 register</description>
19995 <addressOffset>0xC8</addressOffset>
19996 <size>0x20</size>
19997 <access>read-write</access>
19998 <resetValue>0x00000000</resetValue>
19999 <fields>
20000 <field>
20001 <name>M1A</name>
20002 <description>Memory 1 address (used in case of Double
20003 buffer mode)</description>
20004 <bitOffset>0</bitOffset>
20005 <bitWidth>32</bitWidth>
20006 </field>
20007 </fields>
20008 </register>
20009 <register>
20010 <name>S7FCR</name>
20011 <displayName>S7FCR</displayName>
20012 <description>stream x FIFO control register</description>
20013 <addressOffset>0xCC</addressOffset>
20014 <size>0x20</size>
20015 <resetValue>0x00000021</resetValue>
20016 <fields>
20017 <field>
20018 <name>FEIE</name>
20019 <description>FIFO error interrupt
20020 enable</description>
20021 <bitOffset>7</bitOffset>
20022 <bitWidth>1</bitWidth>
20023 <access>read-write</access>
20024 </field>
20025 <field>
20026 <name>FS</name>
20027 <description>FIFO status</description>
20028 <bitOffset>3</bitOffset>
20029 <bitWidth>3</bitWidth>
20030 <access>read-only</access>
20031 </field>
20032 <field>
20033 <name>DMDIS</name>
20034 <description>Direct mode disable</description>
20035 <bitOffset>2</bitOffset>
20036 <bitWidth>1</bitWidth>
20037 <access>read-write</access>
20038 </field>
20039 <field>
20040 <name>FTH</name>
20041 <description>FIFO threshold selection</description>
20042 <bitOffset>0</bitOffset>
20043 <bitWidth>2</bitWidth>
20044 <access>read-write</access>
20045 </field>
20046 </fields>
20047 </register>
20048 </registers>
20049 </peripheral>
20050 <peripheral derivedFrom="DMA2">
20051 <name>DMA1</name>
20052 <baseAddress>0x40026000</baseAddress>
20053 <interrupt>
20054 <name>RTC_WKUP</name>
20055 <description>RTC Wakeup interrupt through the EXTI
20056 line</description>
20057 <value>3</value>
20058 </interrupt>
20059 <interrupt>
20060 <name>RTC_Alarm</name>
20061 <description>RTC Alarms (A and B) through EXTI line
20062 interrupt</description>
20063 <value>41</value>
20064 </interrupt>
20065 </peripheral>
20066 <peripheral>
20067 <name>GPIOH</name>
20068 <description>General-purpose I/Os</description>
20069 <groupName>GPIO</groupName>
20070 <baseAddress>0x40021C00</baseAddress>
20071 <addressBlock>
20072 <offset>0x0</offset>
20073 <size>0x400</size>
20074 <usage>registers</usage>
20075 </addressBlock>
20076 <interrupt>
20077 <name>SDIO</name>
20078 <description>SDIO global interrupt</description>
20079 <value>49</value>
20080 </interrupt>
20081 <registers>
20082 <register>
20083 <name>MODER</name>
20084 <displayName>MODER</displayName>
20085 <description>GPIO port mode register</description>
20086 <addressOffset>0x0</addressOffset>
20087 <size>0x20</size>
20088 <access>read-write</access>
20089 <resetValue>0x00000000</resetValue>
20090 <fields>
20091 <field>
20092 <name>MODER15</name>
20093 <description>Port x configuration bits (y =
20094 0..15)</description>
20095 <bitOffset>30</bitOffset>
20096 <bitWidth>2</bitWidth>
20097 </field>
20098 <field>
20099 <name>MODER14</name>
20100 <description>Port x configuration bits (y =
20101 0..15)</description>
20102 <bitOffset>28</bitOffset>
20103 <bitWidth>2</bitWidth>
20104 </field>
20105 <field>
20106 <name>MODER13</name>
20107 <description>Port x configuration bits (y =
20108 0..15)</description>
20109 <bitOffset>26</bitOffset>
20110 <bitWidth>2</bitWidth>
20111 </field>
20112 <field>
20113 <name>MODER12</name>
20114 <description>Port x configuration bits (y =
20115 0..15)</description>
20116 <bitOffset>24</bitOffset>
20117 <bitWidth>2</bitWidth>
20118 </field>
20119 <field>
20120 <name>MODER11</name>
20121 <description>Port x configuration bits (y =
20122 0..15)</description>
20123 <bitOffset>22</bitOffset>
20124 <bitWidth>2</bitWidth>
20125 </field>
20126 <field>
20127 <name>MODER10</name>
20128 <description>Port x configuration bits (y =
20129 0..15)</description>
20130 <bitOffset>20</bitOffset>
20131 <bitWidth>2</bitWidth>
20132 </field>
20133 <field>
20134 <name>MODER9</name>
20135 <description>Port x configuration bits (y =
20136 0..15)</description>
20137 <bitOffset>18</bitOffset>
20138 <bitWidth>2</bitWidth>
20139 </field>
20140 <field>
20141 <name>MODER8</name>
20142 <description>Port x configuration bits (y =
20143 0..15)</description>
20144 <bitOffset>16</bitOffset>
20145 <bitWidth>2</bitWidth>
20146 </field>
20147 <field>
20148 <name>MODER7</name>
20149 <description>Port x configuration bits (y =
20150 0..15)</description>
20151 <bitOffset>14</bitOffset>
20152 <bitWidth>2</bitWidth>
20153 </field>
20154 <field>
20155 <name>MODER6</name>
20156 <description>Port x configuration bits (y =
20157 0..15)</description>
20158 <bitOffset>12</bitOffset>
20159 <bitWidth>2</bitWidth>
20160 </field>
20161 <field>
20162 <name>MODER5</name>
20163 <description>Port x configuration bits (y =
20164 0..15)</description>
20165 <bitOffset>10</bitOffset>
20166 <bitWidth>2</bitWidth>
20167 </field>
20168 <field>
20169 <name>MODER4</name>
20170 <description>Port x configuration bits (y =
20171 0..15)</description>
20172 <bitOffset>8</bitOffset>
20173 <bitWidth>2</bitWidth>
20174 </field>
20175 <field>
20176 <name>MODER3</name>
20177 <description>Port x configuration bits (y =
20178 0..15)</description>
20179 <bitOffset>6</bitOffset>
20180 <bitWidth>2</bitWidth>
20181 </field>
20182 <field>
20183 <name>MODER2</name>
20184 <description>Port x configuration bits (y =
20185 0..15)</description>
20186 <bitOffset>4</bitOffset>
20187 <bitWidth>2</bitWidth>
20188 </field>
20189 <field>
20190 <name>MODER1</name>
20191 <description>Port x configuration bits (y =
20192 0..15)</description>
20193 <bitOffset>2</bitOffset>
20194 <bitWidth>2</bitWidth>
20195 </field>
20196 <field>
20197 <name>MODER0</name>
20198 <description>Port x configuration bits (y =
20199 0..15)</description>
20200 <bitOffset>0</bitOffset>
20201 <bitWidth>2</bitWidth>
20202 </field>
20203 </fields>
20204 </register>
20205 <register>
20206 <name>OTYPER</name>
20207 <displayName>OTYPER</displayName>
20208 <description>GPIO port output type register</description>
20209 <addressOffset>0x4</addressOffset>
20210 <size>0x20</size>
20211 <access>read-write</access>
20212 <resetValue>0x00000000</resetValue>
20213 <fields>
20214 <field>
20215 <name>OT15</name>
20216 <description>Port x configuration bits (y =
20217 0..15)</description>
20218 <bitOffset>15</bitOffset>
20219 <bitWidth>1</bitWidth>
20220 </field>
20221 <field>
20222 <name>OT14</name>
20223 <description>Port x configuration bits (y =
20224 0..15)</description>
20225 <bitOffset>14</bitOffset>
20226 <bitWidth>1</bitWidth>
20227 </field>
20228 <field>
20229 <name>OT13</name>
20230 <description>Port x configuration bits (y =
20231 0..15)</description>
20232 <bitOffset>13</bitOffset>
20233 <bitWidth>1</bitWidth>
20234 </field>
20235 <field>
20236 <name>OT12</name>
20237 <description>Port x configuration bits (y =
20238 0..15)</description>
20239 <bitOffset>12</bitOffset>
20240 <bitWidth>1</bitWidth>
20241 </field>
20242 <field>
20243 <name>OT11</name>
20244 <description>Port x configuration bits (y =
20245 0..15)</description>
20246 <bitOffset>11</bitOffset>
20247 <bitWidth>1</bitWidth>
20248 </field>
20249 <field>
20250 <name>OT10</name>
20251 <description>Port x configuration bits (y =
20252 0..15)</description>
20253 <bitOffset>10</bitOffset>
20254 <bitWidth>1</bitWidth>
20255 </field>
20256 <field>
20257 <name>OT9</name>
20258 <description>Port x configuration bits (y =
20259 0..15)</description>
20260 <bitOffset>9</bitOffset>
20261 <bitWidth>1</bitWidth>
20262 </field>
20263 <field>
20264 <name>OT8</name>
20265 <description>Port x configuration bits (y =
20266 0..15)</description>
20267 <bitOffset>8</bitOffset>
20268 <bitWidth>1</bitWidth>
20269 </field>
20270 <field>
20271 <name>OT7</name>
20272 <description>Port x configuration bits (y =
20273 0..15)</description>
20274 <bitOffset>7</bitOffset>
20275 <bitWidth>1</bitWidth>
20276 </field>
20277 <field>
20278 <name>OT6</name>
20279 <description>Port x configuration bits (y =
20280 0..15)</description>
20281 <bitOffset>6</bitOffset>
20282 <bitWidth>1</bitWidth>
20283 </field>
20284 <field>
20285 <name>OT5</name>
20286 <description>Port x configuration bits (y =
20287 0..15)</description>
20288 <bitOffset>5</bitOffset>
20289 <bitWidth>1</bitWidth>
20290 </field>
20291 <field>
20292 <name>OT4</name>
20293 <description>Port x configuration bits (y =
20294 0..15)</description>
20295 <bitOffset>4</bitOffset>
20296 <bitWidth>1</bitWidth>
20297 </field>
20298 <field>
20299 <name>OT3</name>
20300 <description>Port x configuration bits (y =
20301 0..15)</description>
20302 <bitOffset>3</bitOffset>
20303 <bitWidth>1</bitWidth>
20304 </field>
20305 <field>
20306 <name>OT2</name>
20307 <description>Port x configuration bits (y =
20308 0..15)</description>
20309 <bitOffset>2</bitOffset>
20310 <bitWidth>1</bitWidth>
20311 </field>
20312 <field>
20313 <name>OT1</name>
20314 <description>Port x configuration bits (y =
20315 0..15)</description>
20316 <bitOffset>1</bitOffset>
20317 <bitWidth>1</bitWidth>
20318 </field>
20319 <field>
20320 <name>OT0</name>
20321 <description>Port x configuration bits (y =
20322 0..15)</description>
20323 <bitOffset>0</bitOffset>
20324 <bitWidth>1</bitWidth>
20325 </field>
20326 </fields>
20327 </register>
20328 <register>
20329 <name>OSPEEDR</name>
20330 <displayName>OSPEEDR</displayName>
20331 <description>GPIO port output speed
20332 register</description>
20333 <addressOffset>0x8</addressOffset>
20334 <size>0x20</size>
20335 <access>read-write</access>
20336 <resetValue>0x00000000</resetValue>
20337 <fields>
20338 <field>
20339 <name>OSPEEDR15</name>
20340 <description>Port x configuration bits (y =
20341 0..15)</description>
20342 <bitOffset>30</bitOffset>
20343 <bitWidth>2</bitWidth>
20344 </field>
20345 <field>
20346 <name>OSPEEDR14</name>
20347 <description>Port x configuration bits (y =
20348 0..15)</description>
20349 <bitOffset>28</bitOffset>
20350 <bitWidth>2</bitWidth>
20351 </field>
20352 <field>
20353 <name>OSPEEDR13</name>
20354 <description>Port x configuration bits (y =
20355 0..15)</description>
20356 <bitOffset>26</bitOffset>
20357 <bitWidth>2</bitWidth>
20358 </field>
20359 <field>
20360 <name>OSPEEDR12</name>
20361 <description>Port x configuration bits (y =
20362 0..15)</description>
20363 <bitOffset>24</bitOffset>
20364 <bitWidth>2</bitWidth>
20365 </field>
20366 <field>
20367 <name>OSPEEDR11</name>
20368 <description>Port x configuration bits (y =
20369 0..15)</description>
20370 <bitOffset>22</bitOffset>
20371 <bitWidth>2</bitWidth>
20372 </field>
20373 <field>
20374 <name>OSPEEDR10</name>
20375 <description>Port x configuration bits (y =
20376 0..15)</description>
20377 <bitOffset>20</bitOffset>
20378 <bitWidth>2</bitWidth>
20379 </field>
20380 <field>
20381 <name>OSPEEDR9</name>
20382 <description>Port x configuration bits (y =
20383 0..15)</description>
20384 <bitOffset>18</bitOffset>
20385 <bitWidth>2</bitWidth>
20386 </field>
20387 <field>
20388 <name>OSPEEDR8</name>
20389 <description>Port x configuration bits (y =
20390 0..15)</description>
20391 <bitOffset>16</bitOffset>
20392 <bitWidth>2</bitWidth>
20393 </field>
20394 <field>
20395 <name>OSPEEDR7</name>
20396 <description>Port x configuration bits (y =
20397 0..15)</description>
20398 <bitOffset>14</bitOffset>
20399 <bitWidth>2</bitWidth>
20400 </field>
20401 <field>
20402 <name>OSPEEDR6</name>
20403 <description>Port x configuration bits (y =
20404 0..15)</description>
20405 <bitOffset>12</bitOffset>
20406 <bitWidth>2</bitWidth>
20407 </field>
20408 <field>
20409 <name>OSPEEDR5</name>
20410 <description>Port x configuration bits (y =
20411 0..15)</description>
20412 <bitOffset>10</bitOffset>
20413 <bitWidth>2</bitWidth>
20414 </field>
20415 <field>
20416 <name>OSPEEDR4</name>
20417 <description>Port x configuration bits (y =
20418 0..15)</description>
20419 <bitOffset>8</bitOffset>
20420 <bitWidth>2</bitWidth>
20421 </field>
20422 <field>
20423 <name>OSPEEDR3</name>
20424 <description>Port x configuration bits (y =
20425 0..15)</description>
20426 <bitOffset>6</bitOffset>
20427 <bitWidth>2</bitWidth>
20428 </field>
20429 <field>
20430 <name>OSPEEDR2</name>
20431 <description>Port x configuration bits (y =
20432 0..15)</description>
20433 <bitOffset>4</bitOffset>
20434 <bitWidth>2</bitWidth>
20435 </field>
20436 <field>
20437 <name>OSPEEDR1</name>
20438 <description>Port x configuration bits (y =
20439 0..15)</description>
20440 <bitOffset>2</bitOffset>
20441 <bitWidth>2</bitWidth>
20442 </field>
20443 <field>
20444 <name>OSPEEDR0</name>
20445 <description>Port x configuration bits (y =
20446 0..15)</description>
20447 <bitOffset>0</bitOffset>
20448 <bitWidth>2</bitWidth>
20449 </field>
20450 </fields>
20451 </register>
20452 <register>
20453 <name>PUPDR</name>
20454 <displayName>PUPDR</displayName>
20455 <description>GPIO port pull-up/pull-down
20456 register</description>
20457 <addressOffset>0xC</addressOffset>
20458 <size>0x20</size>
20459 <access>read-write</access>
20460 <resetValue>0x00000000</resetValue>
20461 <fields>
20462 <field>
20463 <name>PUPDR15</name>
20464 <description>Port x configuration bits (y =
20465 0..15)</description>
20466 <bitOffset>30</bitOffset>
20467 <bitWidth>2</bitWidth>
20468 </field>
20469 <field>
20470 <name>PUPDR14</name>
20471 <description>Port x configuration bits (y =
20472 0..15)</description>
20473 <bitOffset>28</bitOffset>
20474 <bitWidth>2</bitWidth>
20475 </field>
20476 <field>
20477 <name>PUPDR13</name>
20478 <description>Port x configuration bits (y =
20479 0..15)</description>
20480 <bitOffset>26</bitOffset>
20481 <bitWidth>2</bitWidth>
20482 </field>
20483 <field>
20484 <name>PUPDR12</name>
20485 <description>Port x configuration bits (y =
20486 0..15)</description>
20487 <bitOffset>24</bitOffset>
20488 <bitWidth>2</bitWidth>
20489 </field>
20490 <field>
20491 <name>PUPDR11</name>
20492 <description>Port x configuration bits (y =
20493 0..15)</description>
20494 <bitOffset>22</bitOffset>
20495 <bitWidth>2</bitWidth>
20496 </field>
20497 <field>
20498 <name>PUPDR10</name>
20499 <description>Port x configuration bits (y =
20500 0..15)</description>
20501 <bitOffset>20</bitOffset>
20502 <bitWidth>2</bitWidth>
20503 </field>
20504 <field>
20505 <name>PUPDR9</name>
20506 <description>Port x configuration bits (y =
20507 0..15)</description>
20508 <bitOffset>18</bitOffset>
20509 <bitWidth>2</bitWidth>
20510 </field>
20511 <field>
20512 <name>PUPDR8</name>
20513 <description>Port x configuration bits (y =
20514 0..15)</description>
20515 <bitOffset>16</bitOffset>
20516 <bitWidth>2</bitWidth>
20517 </field>
20518 <field>
20519 <name>PUPDR7</name>
20520 <description>Port x configuration bits (y =
20521 0..15)</description>
20522 <bitOffset>14</bitOffset>
20523 <bitWidth>2</bitWidth>
20524 </field>
20525 <field>
20526 <name>PUPDR6</name>
20527 <description>Port x configuration bits (y =
20528 0..15)</description>
20529 <bitOffset>12</bitOffset>
20530 <bitWidth>2</bitWidth>
20531 </field>
20532 <field>
20533 <name>PUPDR5</name>
20534 <description>Port x configuration bits (y =
20535 0..15)</description>
20536 <bitOffset>10</bitOffset>
20537 <bitWidth>2</bitWidth>
20538 </field>
20539 <field>
20540 <name>PUPDR4</name>
20541 <description>Port x configuration bits (y =
20542 0..15)</description>
20543 <bitOffset>8</bitOffset>
20544 <bitWidth>2</bitWidth>
20545 </field>
20546 <field>
20547 <name>PUPDR3</name>
20548 <description>Port x configuration bits (y =
20549 0..15)</description>
20550 <bitOffset>6</bitOffset>
20551 <bitWidth>2</bitWidth>
20552 </field>
20553 <field>
20554 <name>PUPDR2</name>
20555 <description>Port x configuration bits (y =
20556 0..15)</description>
20557 <bitOffset>4</bitOffset>
20558 <bitWidth>2</bitWidth>
20559 </field>
20560 <field>
20561 <name>PUPDR1</name>
20562 <description>Port x configuration bits (y =
20563 0..15)</description>
20564 <bitOffset>2</bitOffset>
20565 <bitWidth>2</bitWidth>
20566 </field>
20567 <field>
20568 <name>PUPDR0</name>
20569 <description>Port x configuration bits (y =
20570 0..15)</description>
20571 <bitOffset>0</bitOffset>
20572 <bitWidth>2</bitWidth>
20573 </field>
20574 </fields>
20575 </register>
20576 <register>
20577 <name>IDR</name>
20578 <displayName>IDR</displayName>
20579 <description>GPIO port input data register</description>
20580 <addressOffset>0x10</addressOffset>
20581 <size>0x20</size>
20582 <access>read-only</access>
20583 <resetValue>0x00000000</resetValue>
20584 <fields>
20585 <field>
20586 <name>IDR15</name>
20587 <description>Port input data (y =
20588 0..15)</description>
20589 <bitOffset>15</bitOffset>
20590 <bitWidth>1</bitWidth>
20591 </field>
20592 <field>
20593 <name>IDR14</name>
20594 <description>Port input data (y =
20595 0..15)</description>
20596 <bitOffset>14</bitOffset>
20597 <bitWidth>1</bitWidth>
20598 </field>
20599 <field>
20600 <name>IDR13</name>
20601 <description>Port input data (y =
20602 0..15)</description>
20603 <bitOffset>13</bitOffset>
20604 <bitWidth>1</bitWidth>
20605 </field>
20606 <field>
20607 <name>IDR12</name>
20608 <description>Port input data (y =
20609 0..15)</description>
20610 <bitOffset>12</bitOffset>
20611 <bitWidth>1</bitWidth>
20612 </field>
20613 <field>
20614 <name>IDR11</name>
20615 <description>Port input data (y =
20616 0..15)</description>
20617 <bitOffset>11</bitOffset>
20618 <bitWidth>1</bitWidth>
20619 </field>
20620 <field>
20621 <name>IDR10</name>
20622 <description>Port input data (y =
20623 0..15)</description>
20624 <bitOffset>10</bitOffset>
20625 <bitWidth>1</bitWidth>
20626 </field>
20627 <field>
20628 <name>IDR9</name>
20629 <description>Port input data (y =
20630 0..15)</description>
20631 <bitOffset>9</bitOffset>
20632 <bitWidth>1</bitWidth>
20633 </field>
20634 <field>
20635 <name>IDR8</name>
20636 <description>Port input data (y =
20637 0..15)</description>
20638 <bitOffset>8</bitOffset>
20639 <bitWidth>1</bitWidth>
20640 </field>
20641 <field>
20642 <name>IDR7</name>
20643 <description>Port input data (y =
20644 0..15)</description>
20645 <bitOffset>7</bitOffset>
20646 <bitWidth>1</bitWidth>
20647 </field>
20648 <field>
20649 <name>IDR6</name>
20650 <description>Port input data (y =
20651 0..15)</description>
20652 <bitOffset>6</bitOffset>
20653 <bitWidth>1</bitWidth>
20654 </field>
20655 <field>
20656 <name>IDR5</name>
20657 <description>Port input data (y =
20658 0..15)</description>
20659 <bitOffset>5</bitOffset>
20660 <bitWidth>1</bitWidth>
20661 </field>
20662 <field>
20663 <name>IDR4</name>
20664 <description>Port input data (y =
20665 0..15)</description>
20666 <bitOffset>4</bitOffset>
20667 <bitWidth>1</bitWidth>
20668 </field>
20669 <field>
20670 <name>IDR3</name>
20671 <description>Port input data (y =
20672 0..15)</description>
20673 <bitOffset>3</bitOffset>
20674 <bitWidth>1</bitWidth>
20675 </field>
20676 <field>
20677 <name>IDR2</name>
20678 <description>Port input data (y =
20679 0..15)</description>
20680 <bitOffset>2</bitOffset>
20681 <bitWidth>1</bitWidth>
20682 </field>
20683 <field>
20684 <name>IDR1</name>
20685 <description>Port input data (y =
20686 0..15)</description>
20687 <bitOffset>1</bitOffset>
20688 <bitWidth>1</bitWidth>
20689 </field>
20690 <field>
20691 <name>IDR0</name>
20692 <description>Port input data (y =
20693 0..15)</description>
20694 <bitOffset>0</bitOffset>
20695 <bitWidth>1</bitWidth>
20696 </field>
20697 </fields>
20698 </register>
20699 <register>
20700 <name>ODR</name>
20701 <displayName>ODR</displayName>
20702 <description>GPIO port output data register</description>
20703 <addressOffset>0x14</addressOffset>
20704 <size>0x20</size>
20705 <access>read-write</access>
20706 <resetValue>0x00000000</resetValue>
20707 <fields>
20708 <field>
20709 <name>ODR15</name>
20710 <description>Port output data (y =
20711 0..15)</description>
20712 <bitOffset>15</bitOffset>
20713 <bitWidth>1</bitWidth>
20714 </field>
20715 <field>
20716 <name>ODR14</name>
20717 <description>Port output data (y =
20718 0..15)</description>
20719 <bitOffset>14</bitOffset>
20720 <bitWidth>1</bitWidth>
20721 </field>
20722 <field>
20723 <name>ODR13</name>
20724 <description>Port output data (y =
20725 0..15)</description>
20726 <bitOffset>13</bitOffset>
20727 <bitWidth>1</bitWidth>
20728 </field>
20729 <field>
20730 <name>ODR12</name>
20731 <description>Port output data (y =
20732 0..15)</description>
20733 <bitOffset>12</bitOffset>
20734 <bitWidth>1</bitWidth>
20735 </field>
20736 <field>
20737 <name>ODR11</name>
20738 <description>Port output data (y =
20739 0..15)</description>
20740 <bitOffset>11</bitOffset>
20741 <bitWidth>1</bitWidth>
20742 </field>
20743 <field>
20744 <name>ODR10</name>
20745 <description>Port output data (y =
20746 0..15)</description>
20747 <bitOffset>10</bitOffset>
20748 <bitWidth>1</bitWidth>
20749 </field>
20750 <field>
20751 <name>ODR9</name>
20752 <description>Port output data (y =
20753 0..15)</description>
20754 <bitOffset>9</bitOffset>
20755 <bitWidth>1</bitWidth>
20756 </field>
20757 <field>
20758 <name>ODR8</name>
20759 <description>Port output data (y =
20760 0..15)</description>
20761 <bitOffset>8</bitOffset>
20762 <bitWidth>1</bitWidth>
20763 </field>
20764 <field>
20765 <name>ODR7</name>
20766 <description>Port output data (y =
20767 0..15)</description>
20768 <bitOffset>7</bitOffset>
20769 <bitWidth>1</bitWidth>
20770 </field>
20771 <field>
20772 <name>ODR6</name>
20773 <description>Port output data (y =
20774 0..15)</description>
20775 <bitOffset>6</bitOffset>
20776 <bitWidth>1</bitWidth>
20777 </field>
20778 <field>
20779 <name>ODR5</name>
20780 <description>Port output data (y =
20781 0..15)</description>
20782 <bitOffset>5</bitOffset>
20783 <bitWidth>1</bitWidth>
20784 </field>
20785 <field>
20786 <name>ODR4</name>
20787 <description>Port output data (y =
20788 0..15)</description>
20789 <bitOffset>4</bitOffset>
20790 <bitWidth>1</bitWidth>
20791 </field>
20792 <field>
20793 <name>ODR3</name>
20794 <description>Port output data (y =
20795 0..15)</description>
20796 <bitOffset>3</bitOffset>
20797 <bitWidth>1</bitWidth>
20798 </field>
20799 <field>
20800 <name>ODR2</name>
20801 <description>Port output data (y =
20802 0..15)</description>
20803 <bitOffset>2</bitOffset>
20804 <bitWidth>1</bitWidth>
20805 </field>
20806 <field>
20807 <name>ODR1</name>
20808 <description>Port output data (y =
20809 0..15)</description>
20810 <bitOffset>1</bitOffset>
20811 <bitWidth>1</bitWidth>
20812 </field>
20813 <field>
20814 <name>ODR0</name>
20815 <description>Port output data (y =
20816 0..15)</description>
20817 <bitOffset>0</bitOffset>
20818 <bitWidth>1</bitWidth>
20819 </field>
20820 </fields>
20821 </register>
20822 <register>
20823 <name>BSRR</name>
20824 <displayName>BSRR</displayName>
20825 <description>GPIO port bit set/reset
20826 register</description>
20827 <addressOffset>0x18</addressOffset>
20828 <size>0x20</size>
20829 <access>write-only</access>
20830 <resetValue>0x00000000</resetValue>
20831 <fields>
20832 <field>
20833 <name>BR15</name>
20834 <description>Port x reset bit y (y =
20835 0..15)</description>
20836 <bitOffset>31</bitOffset>
20837 <bitWidth>1</bitWidth>
20838 </field>
20839 <field>
20840 <name>BR14</name>
20841 <description>Port x reset bit y (y =
20842 0..15)</description>
20843 <bitOffset>30</bitOffset>
20844 <bitWidth>1</bitWidth>
20845 </field>
20846 <field>
20847 <name>BR13</name>
20848 <description>Port x reset bit y (y =
20849 0..15)</description>
20850 <bitOffset>29</bitOffset>
20851 <bitWidth>1</bitWidth>
20852 </field>
20853 <field>
20854 <name>BR12</name>
20855 <description>Port x reset bit y (y =
20856 0..15)</description>
20857 <bitOffset>28</bitOffset>
20858 <bitWidth>1</bitWidth>
20859 </field>
20860 <field>
20861 <name>BR11</name>
20862 <description>Port x reset bit y (y =
20863 0..15)</description>
20864 <bitOffset>27</bitOffset>
20865 <bitWidth>1</bitWidth>
20866 </field>
20867 <field>
20868 <name>BR10</name>
20869 <description>Port x reset bit y (y =
20870 0..15)</description>
20871 <bitOffset>26</bitOffset>
20872 <bitWidth>1</bitWidth>
20873 </field>
20874 <field>
20875 <name>BR9</name>
20876 <description>Port x reset bit y (y =
20877 0..15)</description>
20878 <bitOffset>25</bitOffset>
20879 <bitWidth>1</bitWidth>
20880 </field>
20881 <field>
20882 <name>BR8</name>
20883 <description>Port x reset bit y (y =
20884 0..15)</description>
20885 <bitOffset>24</bitOffset>
20886 <bitWidth>1</bitWidth>
20887 </field>
20888 <field>
20889 <name>BR7</name>
20890 <description>Port x reset bit y (y =
20891 0..15)</description>
20892 <bitOffset>23</bitOffset>
20893 <bitWidth>1</bitWidth>
20894 </field>
20895 <field>
20896 <name>BR6</name>
20897 <description>Port x reset bit y (y =
20898 0..15)</description>
20899 <bitOffset>22</bitOffset>
20900 <bitWidth>1</bitWidth>
20901 </field>
20902 <field>
20903 <name>BR5</name>
20904 <description>Port x reset bit y (y =
20905 0..15)</description>
20906 <bitOffset>21</bitOffset>
20907 <bitWidth>1</bitWidth>
20908 </field>
20909 <field>
20910 <name>BR4</name>
20911 <description>Port x reset bit y (y =
20912 0..15)</description>
20913 <bitOffset>20</bitOffset>
20914 <bitWidth>1</bitWidth>
20915 </field>
20916 <field>
20917 <name>BR3</name>
20918 <description>Port x reset bit y (y =
20919 0..15)</description>
20920 <bitOffset>19</bitOffset>
20921 <bitWidth>1</bitWidth>
20922 </field>
20923 <field>
20924 <name>BR2</name>
20925 <description>Port x reset bit y (y =
20926 0..15)</description>
20927 <bitOffset>18</bitOffset>
20928 <bitWidth>1</bitWidth>
20929 </field>
20930 <field>
20931 <name>BR1</name>
20932 <description>Port x reset bit y (y =
20933 0..15)</description>
20934 <bitOffset>17</bitOffset>
20935 <bitWidth>1</bitWidth>
20936 </field>
20937 <field>
20938 <name>BR0</name>
20939 <description>Port x set bit y (y=
20940 0..15)</description>
20941 <bitOffset>16</bitOffset>
20942 <bitWidth>1</bitWidth>
20943 </field>
20944 <field>
20945 <name>BS15</name>
20946 <description>Port x set bit y (y=
20947 0..15)</description>
20948 <bitOffset>15</bitOffset>
20949 <bitWidth>1</bitWidth>
20950 </field>
20951 <field>
20952 <name>BS14</name>
20953 <description>Port x set bit y (y=
20954 0..15)</description>
20955 <bitOffset>14</bitOffset>
20956 <bitWidth>1</bitWidth>
20957 </field>
20958 <field>
20959 <name>BS13</name>
20960 <description>Port x set bit y (y=
20961 0..15)</description>
20962 <bitOffset>13</bitOffset>
20963 <bitWidth>1</bitWidth>
20964 </field>
20965 <field>
20966 <name>BS12</name>
20967 <description>Port x set bit y (y=
20968 0..15)</description>
20969 <bitOffset>12</bitOffset>
20970 <bitWidth>1</bitWidth>
20971 </field>
20972 <field>
20973 <name>BS11</name>
20974 <description>Port x set bit y (y=
20975 0..15)</description>
20976 <bitOffset>11</bitOffset>
20977 <bitWidth>1</bitWidth>
20978 </field>
20979 <field>
20980 <name>BS10</name>
20981 <description>Port x set bit y (y=
20982 0..15)</description>
20983 <bitOffset>10</bitOffset>
20984 <bitWidth>1</bitWidth>
20985 </field>
20986 <field>
20987 <name>BS9</name>
20988 <description>Port x set bit y (y=
20989 0..15)</description>
20990 <bitOffset>9</bitOffset>
20991 <bitWidth>1</bitWidth>
20992 </field>
20993 <field>
20994 <name>BS8</name>
20995 <description>Port x set bit y (y=
20996 0..15)</description>
20997 <bitOffset>8</bitOffset>
20998 <bitWidth>1</bitWidth>
20999 </field>
21000 <field>
21001 <name>BS7</name>
21002 <description>Port x set bit y (y=
21003 0..15)</description>
21004 <bitOffset>7</bitOffset>
21005 <bitWidth>1</bitWidth>
21006 </field>
21007 <field>
21008 <name>BS6</name>
21009 <description>Port x set bit y (y=
21010 0..15)</description>
21011 <bitOffset>6</bitOffset>
21012 <bitWidth>1</bitWidth>
21013 </field>
21014 <field>
21015 <name>BS5</name>
21016 <description>Port x set bit y (y=
21017 0..15)</description>
21018 <bitOffset>5</bitOffset>
21019 <bitWidth>1</bitWidth>
21020 </field>
21021 <field>
21022 <name>BS4</name>
21023 <description>Port x set bit y (y=
21024 0..15)</description>
21025 <bitOffset>4</bitOffset>
21026 <bitWidth>1</bitWidth>
21027 </field>
21028 <field>
21029 <name>BS3</name>
21030 <description>Port x set bit y (y=
21031 0..15)</description>
21032 <bitOffset>3</bitOffset>
21033 <bitWidth>1</bitWidth>
21034 </field>
21035 <field>
21036 <name>BS2</name>
21037 <description>Port x set bit y (y=
21038 0..15)</description>
21039 <bitOffset>2</bitOffset>
21040 <bitWidth>1</bitWidth>
21041 </field>
21042 <field>
21043 <name>BS1</name>
21044 <description>Port x set bit y (y=
21045 0..15)</description>
21046 <bitOffset>1</bitOffset>
21047 <bitWidth>1</bitWidth>
21048 </field>
21049 <field>
21050 <name>BS0</name>
21051 <description>Port x set bit y (y=
21052 0..15)</description>
21053 <bitOffset>0</bitOffset>
21054 <bitWidth>1</bitWidth>
21055 </field>
21056 </fields>
21057 </register>
21058 <register>
21059 <name>LCKR</name>
21060 <displayName>LCKR</displayName>
21061 <description>GPIO port configuration lock
21062 register</description>
21063 <addressOffset>0x1C</addressOffset>
21064 <size>0x20</size>
21065 <access>read-write</access>
21066 <resetValue>0x00000000</resetValue>
21067 <fields>
21068 <field>
21069 <name>LCKK</name>
21070 <description>Port x lock bit y (y=
21071 0..15)</description>
21072 <bitOffset>16</bitOffset>
21073 <bitWidth>1</bitWidth>
21074 </field>
21075 <field>
21076 <name>LCK15</name>
21077 <description>Port x lock bit y (y=
21078 0..15)</description>
21079 <bitOffset>15</bitOffset>
21080 <bitWidth>1</bitWidth>
21081 </field>
21082 <field>
21083 <name>LCK14</name>
21084 <description>Port x lock bit y (y=
21085 0..15)</description>
21086 <bitOffset>14</bitOffset>
21087 <bitWidth>1</bitWidth>
21088 </field>
21089 <field>
21090 <name>LCK13</name>
21091 <description>Port x lock bit y (y=
21092 0..15)</description>
21093 <bitOffset>13</bitOffset>
21094 <bitWidth>1</bitWidth>
21095 </field>
21096 <field>
21097 <name>LCK12</name>
21098 <description>Port x lock bit y (y=
21099 0..15)</description>
21100 <bitOffset>12</bitOffset>
21101 <bitWidth>1</bitWidth>
21102 </field>
21103 <field>
21104 <name>LCK11</name>
21105 <description>Port x lock bit y (y=
21106 0..15)</description>
21107 <bitOffset>11</bitOffset>
21108 <bitWidth>1</bitWidth>
21109 </field>
21110 <field>
21111 <name>LCK10</name>
21112 <description>Port x lock bit y (y=
21113 0..15)</description>
21114 <bitOffset>10</bitOffset>
21115 <bitWidth>1</bitWidth>
21116 </field>
21117 <field>
21118 <name>LCK9</name>
21119 <description>Port x lock bit y (y=
21120 0..15)</description>
21121 <bitOffset>9</bitOffset>
21122 <bitWidth>1</bitWidth>
21123 </field>
21124 <field>
21125 <name>LCK8</name>
21126 <description>Port x lock bit y (y=
21127 0..15)</description>
21128 <bitOffset>8</bitOffset>
21129 <bitWidth>1</bitWidth>
21130 </field>
21131 <field>
21132 <name>LCK7</name>
21133 <description>Port x lock bit y (y=
21134 0..15)</description>
21135 <bitOffset>7</bitOffset>
21136 <bitWidth>1</bitWidth>
21137 </field>
21138 <field>
21139 <name>LCK6</name>
21140 <description>Port x lock bit y (y=
21141 0..15)</description>
21142 <bitOffset>6</bitOffset>
21143 <bitWidth>1</bitWidth>
21144 </field>
21145 <field>
21146 <name>LCK5</name>
21147 <description>Port x lock bit y (y=
21148 0..15)</description>
21149 <bitOffset>5</bitOffset>
21150 <bitWidth>1</bitWidth>
21151 </field>
21152 <field>
21153 <name>LCK4</name>
21154 <description>Port x lock bit y (y=
21155 0..15)</description>
21156 <bitOffset>4</bitOffset>
21157 <bitWidth>1</bitWidth>
21158 </field>
21159 <field>
21160 <name>LCK3</name>
21161 <description>Port x lock bit y (y=
21162 0..15)</description>
21163 <bitOffset>3</bitOffset>
21164 <bitWidth>1</bitWidth>
21165 </field>
21166 <field>
21167 <name>LCK2</name>
21168 <description>Port x lock bit y (y=
21169 0..15)</description>
21170 <bitOffset>2</bitOffset>
21171 <bitWidth>1</bitWidth>
21172 </field>
21173 <field>
21174 <name>LCK1</name>
21175 <description>Port x lock bit y (y=
21176 0..15)</description>
21177 <bitOffset>1</bitOffset>
21178 <bitWidth>1</bitWidth>
21179 </field>
21180 <field>
21181 <name>LCK0</name>
21182 <description>Port x lock bit y (y=
21183 0..15)</description>
21184 <bitOffset>0</bitOffset>
21185 <bitWidth>1</bitWidth>
21186 </field>
21187 </fields>
21188 </register>
21189 <register>
21190 <name>AFRL</name>
21191 <displayName>AFRL</displayName>
21192 <description>GPIO alternate function low
21193 register</description>
21194 <addressOffset>0x20</addressOffset>
21195 <size>0x20</size>
21196 <access>read-write</access>
21197 <resetValue>0x00000000</resetValue>
21198 <fields>
21199 <field>
21200 <name>AFRL7</name>
21201 <description>Alternate function selection for port x
21202 bit y (y = 0..7)</description>
21203 <bitOffset>28</bitOffset>
21204 <bitWidth>4</bitWidth>
21205 </field>
21206 <field>
21207 <name>AFRL6</name>
21208 <description>Alternate function selection for port x
21209 bit y (y = 0..7)</description>
21210 <bitOffset>24</bitOffset>
21211 <bitWidth>4</bitWidth>
21212 </field>
21213 <field>
21214 <name>AFRL5</name>
21215 <description>Alternate function selection for port x
21216 bit y (y = 0..7)</description>
21217 <bitOffset>20</bitOffset>
21218 <bitWidth>4</bitWidth>
21219 </field>
21220 <field>
21221 <name>AFRL4</name>
21222 <description>Alternate function selection for port x
21223 bit y (y = 0..7)</description>
21224 <bitOffset>16</bitOffset>
21225 <bitWidth>4</bitWidth>
21226 </field>
21227 <field>
21228 <name>AFRL3</name>
21229 <description>Alternate function selection for port x
21230 bit y (y = 0..7)</description>
21231 <bitOffset>12</bitOffset>
21232 <bitWidth>4</bitWidth>
21233 </field>
21234 <field>
21235 <name>AFRL2</name>
21236 <description>Alternate function selection for port x
21237 bit y (y = 0..7)</description>
21238 <bitOffset>8</bitOffset>
21239 <bitWidth>4</bitWidth>
21240 </field>
21241 <field>
21242 <name>AFRL1</name>
21243 <description>Alternate function selection for port x
21244 bit y (y = 0..7)</description>
21245 <bitOffset>4</bitOffset>
21246 <bitWidth>4</bitWidth>
21247 </field>
21248 <field>
21249 <name>AFRL0</name>
21250 <description>Alternate function selection for port x
21251 bit y (y = 0..7)</description>
21252 <bitOffset>0</bitOffset>
21253 <bitWidth>4</bitWidth>
21254 </field>
21255 </fields>
21256 </register>
21257 <register>
21258 <name>AFRH</name>
21259 <displayName>AFRH</displayName>
21260 <description>GPIO alternate function high
21261 register</description>
21262 <addressOffset>0x24</addressOffset>
21263 <size>0x20</size>
21264 <access>read-write</access>
21265 <resetValue>0x00000000</resetValue>
21266 <fields>
21267 <field>
21268 <name>AFRH15</name>
21269 <description>Alternate function selection for port x
21270 bit y (y = 8..15)</description>
21271 <bitOffset>28</bitOffset>
21272 <bitWidth>4</bitWidth>
21273 </field>
21274 <field>
21275 <name>AFRH14</name>
21276 <description>Alternate function selection for port x
21277 bit y (y = 8..15)</description>
21278 <bitOffset>24</bitOffset>
21279 <bitWidth>4</bitWidth>
21280 </field>
21281 <field>
21282 <name>AFRH13</name>
21283 <description>Alternate function selection for port x
21284 bit y (y = 8..15)</description>
21285 <bitOffset>20</bitOffset>
21286 <bitWidth>4</bitWidth>
21287 </field>
21288 <field>
21289 <name>AFRH12</name>
21290 <description>Alternate function selection for port x
21291 bit y (y = 8..15)</description>
21292 <bitOffset>16</bitOffset>
21293 <bitWidth>4</bitWidth>
21294 </field>
21295 <field>
21296 <name>AFRH11</name>
21297 <description>Alternate function selection for port x
21298 bit y (y = 8..15)</description>
21299 <bitOffset>12</bitOffset>
21300 <bitWidth>4</bitWidth>
21301 </field>
21302 <field>
21303 <name>AFRH10</name>
21304 <description>Alternate function selection for port x
21305 bit y (y = 8..15)</description>
21306 <bitOffset>8</bitOffset>
21307 <bitWidth>4</bitWidth>
21308 </field>
21309 <field>
21310 <name>AFRH9</name>
21311 <description>Alternate function selection for port x
21312 bit y (y = 8..15)</description>
21313 <bitOffset>4</bitOffset>
21314 <bitWidth>4</bitWidth>
21315 </field>
21316 <field>
21317 <name>AFRH8</name>
21318 <description>Alternate function selection for port x
21319 bit y (y = 8..15)</description>
21320 <bitOffset>0</bitOffset>
21321 <bitWidth>4</bitWidth>
21322 </field>
21323 </fields>
21324 </register>
21325 </registers>
21326 </peripheral>
21327 <peripheral derivedFrom="GPIOH">
21328 <name>GPIOE</name>
21329 <baseAddress>0x40021000</baseAddress>
21330 </peripheral>
21331 <peripheral derivedFrom="GPIOH">
21332 <name>GPIOD</name>
21333 <baseAddress>0X40020C00</baseAddress>
21334 <interrupt>
21335 <name>TIM1_BRK_TIM9</name>
21336 <description>TIM1 Break interrupt and TIM9 global
21337 interrupt</description>
21338 <value>24</value>
21339 </interrupt>
21340 <interrupt>
21341 <name>TIM1_UP_TIM10</name>
21342 <description>TIM1 Update interrupt and TIM10 global
21343 interrupt</description>
21344 <value>25</value>
21345 </interrupt>
21346 <interrupt>
21347 <name>TIM1_TRG_COM_TIM11</name>
21348 <description>TIM1 Trigger and Commutation interrupts and
21349 TIM11 global interrupt</description>
21350 <value>26</value>
21351 </interrupt>
21352 <interrupt>
21353 <name>TIM1_CC</name>
21354 <description>TIM1 Capture Compare interrupt</description>
21355 <value>27</value>
21356 </interrupt>
21357 </peripheral>
21358 <peripheral derivedFrom="GPIOH">
21359 <name>GPIOC</name>
21360 <baseAddress>0x40020800</baseAddress>
21361 <interrupt>
21362 <name>TIM1_UP_TIM10</name>
21363 <description>TIM1 Update interrupt and TIM10 global
21364 interrupt</description>
21365 <value>25</value>
21366 </interrupt>
21367 </peripheral>
21368 <peripheral>
21369 <name>GPIOB</name>
21370 <description>General-purpose I/Os</description>
21371 <groupName>GPIO</groupName>
21372 <baseAddress>0x40020400</baseAddress>
21373 <addressBlock>
21374 <offset>0x0</offset>
21375 <size>0x400</size>
21376 <usage>registers</usage>
21377 </addressBlock>
21378 <interrupt>
21379 <name>TIM1_TRG_COM_TIM11</name>
21380 <description>TIM1 Trigger and Commutation interrupts and
21381 TIM11 global interrupt</description>
21382 <value>26</value>
21383 </interrupt>
21384 <registers>
21385 <register>
21386 <name>MODER</name>
21387 <displayName>MODER</displayName>
21388 <description>GPIO port mode register</description>
21389 <addressOffset>0x0</addressOffset>
21390 <size>0x20</size>
21391 <access>read-write</access>
21392 <resetValue>0x00000280</resetValue>
21393 <fields>
21394 <field>
21395 <name>MODER15</name>
21396 <description>Port x configuration bits (y =
21397 0..15)</description>
21398 <bitOffset>30</bitOffset>
21399 <bitWidth>2</bitWidth>
21400 </field>
21401 <field>
21402 <name>MODER14</name>
21403 <description>Port x configuration bits (y =
21404 0..15)</description>
21405 <bitOffset>28</bitOffset>
21406 <bitWidth>2</bitWidth>
21407 </field>
21408 <field>
21409 <name>MODER13</name>
21410 <description>Port x configuration bits (y =
21411 0..15)</description>
21412 <bitOffset>26</bitOffset>
21413 <bitWidth>2</bitWidth>
21414 </field>
21415 <field>
21416 <name>MODER12</name>
21417 <description>Port x configuration bits (y =
21418 0..15)</description>
21419 <bitOffset>24</bitOffset>
21420 <bitWidth>2</bitWidth>
21421 </field>
21422 <field>
21423 <name>MODER11</name>
21424 <description>Port x configuration bits (y =
21425 0..15)</description>
21426 <bitOffset>22</bitOffset>
21427 <bitWidth>2</bitWidth>
21428 </field>
21429 <field>
21430 <name>MODER10</name>
21431 <description>Port x configuration bits (y =
21432 0..15)</description>
21433 <bitOffset>20</bitOffset>
21434 <bitWidth>2</bitWidth>
21435 </field>
21436 <field>
21437 <name>MODER9</name>
21438 <description>Port x configuration bits (y =
21439 0..15)</description>
21440 <bitOffset>18</bitOffset>
21441 <bitWidth>2</bitWidth>
21442 </field>
21443 <field>
21444 <name>MODER8</name>
21445 <description>Port x configuration bits (y =
21446 0..15)</description>
21447 <bitOffset>16</bitOffset>
21448 <bitWidth>2</bitWidth>
21449 </field>
21450 <field>
21451 <name>MODER7</name>
21452 <description>Port x configuration bits (y =
21453 0..15)</description>
21454 <bitOffset>14</bitOffset>
21455 <bitWidth>2</bitWidth>
21456 </field>
21457 <field>
21458 <name>MODER6</name>
21459 <description>Port x configuration bits (y =
21460 0..15)</description>
21461 <bitOffset>12</bitOffset>
21462 <bitWidth>2</bitWidth>
21463 </field>
21464 <field>
21465 <name>MODER5</name>
21466 <description>Port x configuration bits (y =
21467 0..15)</description>
21468 <bitOffset>10</bitOffset>
21469 <bitWidth>2</bitWidth>
21470 </field>
21471 <field>
21472 <name>MODER4</name>
21473 <description>Port x configuration bits (y =
21474 0..15)</description>
21475 <bitOffset>8</bitOffset>
21476 <bitWidth>2</bitWidth>
21477 </field>
21478 <field>
21479 <name>MODER3</name>
21480 <description>Port x configuration bits (y =
21481 0..15)</description>
21482 <bitOffset>6</bitOffset>
21483 <bitWidth>2</bitWidth>
21484 </field>
21485 <field>
21486 <name>MODER2</name>
21487 <description>Port x configuration bits (y =
21488 0..15)</description>
21489 <bitOffset>4</bitOffset>
21490 <bitWidth>2</bitWidth>
21491 </field>
21492 <field>
21493 <name>MODER1</name>
21494 <description>Port x configuration bits (y =
21495 0..15)</description>
21496 <bitOffset>2</bitOffset>
21497 <bitWidth>2</bitWidth>
21498 </field>
21499 <field>
21500 <name>MODER0</name>
21501 <description>Port x configuration bits (y =
21502 0..15)</description>
21503 <bitOffset>0</bitOffset>
21504 <bitWidth>2</bitWidth>
21505 </field>
21506 </fields>
21507 </register>
21508 <register>
21509 <name>OTYPER</name>
21510 <displayName>OTYPER</displayName>
21511 <description>GPIO port output type register</description>
21512 <addressOffset>0x4</addressOffset>
21513 <size>0x20</size>
21514 <access>read-write</access>
21515 <resetValue>0x00000000</resetValue>
21516 <fields>
21517 <field>
21518 <name>OT15</name>
21519 <description>Port x configuration bits (y =
21520 0..15)</description>
21521 <bitOffset>15</bitOffset>
21522 <bitWidth>1</bitWidth>
21523 </field>
21524 <field>
21525 <name>OT14</name>
21526 <description>Port x configuration bits (y =
21527 0..15)</description>
21528 <bitOffset>14</bitOffset>
21529 <bitWidth>1</bitWidth>
21530 </field>
21531 <field>
21532 <name>OT13</name>
21533 <description>Port x configuration bits (y =
21534 0..15)</description>
21535 <bitOffset>13</bitOffset>
21536 <bitWidth>1</bitWidth>
21537 </field>
21538 <field>
21539 <name>OT12</name>
21540 <description>Port x configuration bits (y =
21541 0..15)</description>
21542 <bitOffset>12</bitOffset>
21543 <bitWidth>1</bitWidth>
21544 </field>
21545 <field>
21546 <name>OT11</name>
21547 <description>Port x configuration bits (y =
21548 0..15)</description>
21549 <bitOffset>11</bitOffset>
21550 <bitWidth>1</bitWidth>
21551 </field>
21552 <field>
21553 <name>OT10</name>
21554 <description>Port x configuration bits (y =
21555 0..15)</description>
21556 <bitOffset>10</bitOffset>
21557 <bitWidth>1</bitWidth>
21558 </field>
21559 <field>
21560 <name>OT9</name>
21561 <description>Port x configuration bits (y =
21562 0..15)</description>
21563 <bitOffset>9</bitOffset>
21564 <bitWidth>1</bitWidth>
21565 </field>
21566 <field>
21567 <name>OT8</name>
21568 <description>Port x configuration bits (y =
21569 0..15)</description>
21570 <bitOffset>8</bitOffset>
21571 <bitWidth>1</bitWidth>
21572 </field>
21573 <field>
21574 <name>OT7</name>
21575 <description>Port x configuration bits (y =
21576 0..15)</description>
21577 <bitOffset>7</bitOffset>
21578 <bitWidth>1</bitWidth>
21579 </field>
21580 <field>
21581 <name>OT6</name>
21582 <description>Port x configuration bits (y =
21583 0..15)</description>
21584 <bitOffset>6</bitOffset>
21585 <bitWidth>1</bitWidth>
21586 </field>
21587 <field>
21588 <name>OT5</name>
21589 <description>Port x configuration bits (y =
21590 0..15)</description>
21591 <bitOffset>5</bitOffset>
21592 <bitWidth>1</bitWidth>
21593 </field>
21594 <field>
21595 <name>OT4</name>
21596 <description>Port x configuration bits (y =
21597 0..15)</description>
21598 <bitOffset>4</bitOffset>
21599 <bitWidth>1</bitWidth>
21600 </field>
21601 <field>
21602 <name>OT3</name>
21603 <description>Port x configuration bits (y =
21604 0..15)</description>
21605 <bitOffset>3</bitOffset>
21606 <bitWidth>1</bitWidth>
21607 </field>
21608 <field>
21609 <name>OT2</name>
21610 <description>Port x configuration bits (y =
21611 0..15)</description>
21612 <bitOffset>2</bitOffset>
21613 <bitWidth>1</bitWidth>
21614 </field>
21615 <field>
21616 <name>OT1</name>
21617 <description>Port x configuration bits (y =
21618 0..15)</description>
21619 <bitOffset>1</bitOffset>
21620 <bitWidth>1</bitWidth>
21621 </field>
21622 <field>
21623 <name>OT0</name>
21624 <description>Port x configuration bits (y =
21625 0..15)</description>
21626 <bitOffset>0</bitOffset>
21627 <bitWidth>1</bitWidth>
21628 </field>
21629 </fields>
21630 </register>
21631 <register>
21632 <name>OSPEEDR</name>
21633 <displayName>OSPEEDR</displayName>
21634 <description>GPIO port output speed
21635 register</description>
21636 <addressOffset>0x8</addressOffset>
21637 <size>0x20</size>
21638 <access>read-write</access>
21639 <resetValue>0x000000C0</resetValue>
21640 <fields>
21641 <field>
21642 <name>OSPEEDR15</name>
21643 <description>Port x configuration bits (y =
21644 0..15)</description>
21645 <bitOffset>30</bitOffset>
21646 <bitWidth>2</bitWidth>
21647 </field>
21648 <field>
21649 <name>OSPEEDR14</name>
21650 <description>Port x configuration bits (y =
21651 0..15)</description>
21652 <bitOffset>28</bitOffset>
21653 <bitWidth>2</bitWidth>
21654 </field>
21655 <field>
21656 <name>OSPEEDR13</name>
21657 <description>Port x configuration bits (y =
21658 0..15)</description>
21659 <bitOffset>26</bitOffset>
21660 <bitWidth>2</bitWidth>
21661 </field>
21662 <field>
21663 <name>OSPEEDR12</name>
21664 <description>Port x configuration bits (y =
21665 0..15)</description>
21666 <bitOffset>24</bitOffset>
21667 <bitWidth>2</bitWidth>
21668 </field>
21669 <field>
21670 <name>OSPEEDR11</name>
21671 <description>Port x configuration bits (y =
21672 0..15)</description>
21673 <bitOffset>22</bitOffset>
21674 <bitWidth>2</bitWidth>
21675 </field>
21676 <field>
21677 <name>OSPEEDR10</name>
21678 <description>Port x configuration bits (y =
21679 0..15)</description>
21680 <bitOffset>20</bitOffset>
21681 <bitWidth>2</bitWidth>
21682 </field>
21683 <field>
21684 <name>OSPEEDR9</name>
21685 <description>Port x configuration bits (y =
21686 0..15)</description>
21687 <bitOffset>18</bitOffset>
21688 <bitWidth>2</bitWidth>
21689 </field>
21690 <field>
21691 <name>OSPEEDR8</name>
21692 <description>Port x configuration bits (y =
21693 0..15)</description>
21694 <bitOffset>16</bitOffset>
21695 <bitWidth>2</bitWidth>
21696 </field>
21697 <field>
21698 <name>OSPEEDR7</name>
21699 <description>Port x configuration bits (y =
21700 0..15)</description>
21701 <bitOffset>14</bitOffset>
21702 <bitWidth>2</bitWidth>
21703 </field>
21704 <field>
21705 <name>OSPEEDR6</name>
21706 <description>Port x configuration bits (y =
21707 0..15)</description>
21708 <bitOffset>12</bitOffset>
21709 <bitWidth>2</bitWidth>
21710 </field>
21711 <field>
21712 <name>OSPEEDR5</name>
21713 <description>Port x configuration bits (y =
21714 0..15)</description>
21715 <bitOffset>10</bitOffset>
21716 <bitWidth>2</bitWidth>
21717 </field>
21718 <field>
21719 <name>OSPEEDR4</name>
21720 <description>Port x configuration bits (y =
21721 0..15)</description>
21722 <bitOffset>8</bitOffset>
21723 <bitWidth>2</bitWidth>
21724 </field>
21725 <field>
21726 <name>OSPEEDR3</name>
21727 <description>Port x configuration bits (y =
21728 0..15)</description>
21729 <bitOffset>6</bitOffset>
21730 <bitWidth>2</bitWidth>
21731 </field>
21732 <field>
21733 <name>OSPEEDR2</name>
21734 <description>Port x configuration bits (y =
21735 0..15)</description>
21736 <bitOffset>4</bitOffset>
21737 <bitWidth>2</bitWidth>
21738 </field>
21739 <field>
21740 <name>OSPEEDR1</name>
21741 <description>Port x configuration bits (y =
21742 0..15)</description>
21743 <bitOffset>2</bitOffset>
21744 <bitWidth>2</bitWidth>
21745 </field>
21746 <field>
21747 <name>OSPEEDR0</name>
21748 <description>Port x configuration bits (y =
21749 0..15)</description>
21750 <bitOffset>0</bitOffset>
21751 <bitWidth>2</bitWidth>
21752 </field>
21753 </fields>
21754 </register>
21755 <register>
21756 <name>PUPDR</name>
21757 <displayName>PUPDR</displayName>
21758 <description>GPIO port pull-up/pull-down
21759 register</description>
21760 <addressOffset>0xC</addressOffset>
21761 <size>0x20</size>
21762 <access>read-write</access>
21763 <resetValue>0x00000100</resetValue>
21764 <fields>
21765 <field>
21766 <name>PUPDR15</name>
21767 <description>Port x configuration bits (y =
21768 0..15)</description>
21769 <bitOffset>30</bitOffset>
21770 <bitWidth>2</bitWidth>
21771 </field>
21772 <field>
21773 <name>PUPDR14</name>
21774 <description>Port x configuration bits (y =
21775 0..15)</description>
21776 <bitOffset>28</bitOffset>
21777 <bitWidth>2</bitWidth>
21778 </field>
21779 <field>
21780 <name>PUPDR13</name>
21781 <description>Port x configuration bits (y =
21782 0..15)</description>
21783 <bitOffset>26</bitOffset>
21784 <bitWidth>2</bitWidth>
21785 </field>
21786 <field>
21787 <name>PUPDR12</name>
21788 <description>Port x configuration bits (y =
21789 0..15)</description>
21790 <bitOffset>24</bitOffset>
21791 <bitWidth>2</bitWidth>
21792 </field>
21793 <field>
21794 <name>PUPDR11</name>
21795 <description>Port x configuration bits (y =
21796 0..15)</description>
21797 <bitOffset>22</bitOffset>
21798 <bitWidth>2</bitWidth>
21799 </field>
21800 <field>
21801 <name>PUPDR10</name>
21802 <description>Port x configuration bits (y =
21803 0..15)</description>
21804 <bitOffset>20</bitOffset>
21805 <bitWidth>2</bitWidth>
21806 </field>
21807 <field>
21808 <name>PUPDR9</name>
21809 <description>Port x configuration bits (y =
21810 0..15)</description>
21811 <bitOffset>18</bitOffset>
21812 <bitWidth>2</bitWidth>
21813 </field>
21814 <field>
21815 <name>PUPDR8</name>
21816 <description>Port x configuration bits (y =
21817 0..15)</description>
21818 <bitOffset>16</bitOffset>
21819 <bitWidth>2</bitWidth>
21820 </field>
21821 <field>
21822 <name>PUPDR7</name>
21823 <description>Port x configuration bits (y =
21824 0..15)</description>
21825 <bitOffset>14</bitOffset>
21826 <bitWidth>2</bitWidth>
21827 </field>
21828 <field>
21829 <name>PUPDR6</name>
21830 <description>Port x configuration bits (y =
21831 0..15)</description>
21832 <bitOffset>12</bitOffset>
21833 <bitWidth>2</bitWidth>
21834 </field>
21835 <field>
21836 <name>PUPDR5</name>
21837 <description>Port x configuration bits (y =
21838 0..15)</description>
21839 <bitOffset>10</bitOffset>
21840 <bitWidth>2</bitWidth>
21841 </field>
21842 <field>
21843 <name>PUPDR4</name>
21844 <description>Port x configuration bits (y =
21845 0..15)</description>
21846 <bitOffset>8</bitOffset>
21847 <bitWidth>2</bitWidth>
21848 </field>
21849 <field>
21850 <name>PUPDR3</name>
21851 <description>Port x configuration bits (y =
21852 0..15)</description>
21853 <bitOffset>6</bitOffset>
21854 <bitWidth>2</bitWidth>
21855 </field>
21856 <field>
21857 <name>PUPDR2</name>
21858 <description>Port x configuration bits (y =
21859 0..15)</description>
21860 <bitOffset>4</bitOffset>
21861 <bitWidth>2</bitWidth>
21862 </field>
21863 <field>
21864 <name>PUPDR1</name>
21865 <description>Port x configuration bits (y =
21866 0..15)</description>
21867 <bitOffset>2</bitOffset>
21868 <bitWidth>2</bitWidth>
21869 </field>
21870 <field>
21871 <name>PUPDR0</name>
21872 <description>Port x configuration bits (y =
21873 0..15)</description>
21874 <bitOffset>0</bitOffset>
21875 <bitWidth>2</bitWidth>
21876 </field>
21877 </fields>
21878 </register>
21879 <register>
21880 <name>IDR</name>
21881 <displayName>IDR</displayName>
21882 <description>GPIO port input data register</description>
21883 <addressOffset>0x10</addressOffset>
21884 <size>0x20</size>
21885 <access>read-only</access>
21886 <resetValue>0x00000000</resetValue>
21887 <fields>
21888 <field>
21889 <name>IDR15</name>
21890 <description>Port input data (y =
21891 0..15)</description>
21892 <bitOffset>15</bitOffset>
21893 <bitWidth>1</bitWidth>
21894 </field>
21895 <field>
21896 <name>IDR14</name>
21897 <description>Port input data (y =
21898 0..15)</description>
21899 <bitOffset>14</bitOffset>
21900 <bitWidth>1</bitWidth>
21901 </field>
21902 <field>
21903 <name>IDR13</name>
21904 <description>Port input data (y =
21905 0..15)</description>
21906 <bitOffset>13</bitOffset>
21907 <bitWidth>1</bitWidth>
21908 </field>
21909 <field>
21910 <name>IDR12</name>
21911 <description>Port input data (y =
21912 0..15)</description>
21913 <bitOffset>12</bitOffset>
21914 <bitWidth>1</bitWidth>
21915 </field>
21916 <field>
21917 <name>IDR11</name>
21918 <description>Port input data (y =
21919 0..15)</description>
21920 <bitOffset>11</bitOffset>
21921 <bitWidth>1</bitWidth>
21922 </field>
21923 <field>
21924 <name>IDR10</name>
21925 <description>Port input data (y =
21926 0..15)</description>
21927 <bitOffset>10</bitOffset>
21928 <bitWidth>1</bitWidth>
21929 </field>
21930 <field>
21931 <name>IDR9</name>
21932 <description>Port input data (y =
21933 0..15)</description>
21934 <bitOffset>9</bitOffset>
21935 <bitWidth>1</bitWidth>
21936 </field>
21937 <field>
21938 <name>IDR8</name>
21939 <description>Port input data (y =
21940 0..15)</description>
21941 <bitOffset>8</bitOffset>
21942 <bitWidth>1</bitWidth>
21943 </field>
21944 <field>
21945 <name>IDR7</name>
21946 <description>Port input data (y =
21947 0..15)</description>
21948 <bitOffset>7</bitOffset>
21949 <bitWidth>1</bitWidth>
21950 </field>
21951 <field>
21952 <name>IDR6</name>
21953 <description>Port input data (y =
21954 0..15)</description>
21955 <bitOffset>6</bitOffset>
21956 <bitWidth>1</bitWidth>
21957 </field>
21958 <field>
21959 <name>IDR5</name>
21960 <description>Port input data (y =
21961 0..15)</description>
21962 <bitOffset>5</bitOffset>
21963 <bitWidth>1</bitWidth>
21964 </field>
21965 <field>
21966 <name>IDR4</name>
21967 <description>Port input data (y =
21968 0..15)</description>
21969 <bitOffset>4</bitOffset>
21970 <bitWidth>1</bitWidth>
21971 </field>
21972 <field>
21973 <name>IDR3</name>
21974 <description>Port input data (y =
21975 0..15)</description>
21976 <bitOffset>3</bitOffset>
21977 <bitWidth>1</bitWidth>
21978 </field>
21979 <field>
21980 <name>IDR2</name>
21981 <description>Port input data (y =
21982 0..15)</description>
21983 <bitOffset>2</bitOffset>
21984 <bitWidth>1</bitWidth>
21985 </field>
21986 <field>
21987 <name>IDR1</name>
21988 <description>Port input data (y =
21989 0..15)</description>
21990 <bitOffset>1</bitOffset>
21991 <bitWidth>1</bitWidth>
21992 </field>
21993 <field>
21994 <name>IDR0</name>
21995 <description>Port input data (y =
21996 0..15)</description>
21997 <bitOffset>0</bitOffset>
21998 <bitWidth>1</bitWidth>
21999 </field>
22000 </fields>
22001 </register>
22002 <register>
22003 <name>ODR</name>
22004 <displayName>ODR</displayName>
22005 <description>GPIO port output data register</description>
22006 <addressOffset>0x14</addressOffset>
22007 <size>0x20</size>
22008 <access>read-write</access>
22009 <resetValue>0x00000000</resetValue>
22010 <fields>
22011 <field>
22012 <name>ODR15</name>
22013 <description>Port output data (y =
22014 0..15)</description>
22015 <bitOffset>15</bitOffset>
22016 <bitWidth>1</bitWidth>
22017 </field>
22018 <field>
22019 <name>ODR14</name>
22020 <description>Port output data (y =
22021 0..15)</description>
22022 <bitOffset>14</bitOffset>
22023 <bitWidth>1</bitWidth>
22024 </field>
22025 <field>
22026 <name>ODR13</name>
22027 <description>Port output data (y =
22028 0..15)</description>
22029 <bitOffset>13</bitOffset>
22030 <bitWidth>1</bitWidth>
22031 </field>
22032 <field>
22033 <name>ODR12</name>
22034 <description>Port output data (y =
22035 0..15)</description>
22036 <bitOffset>12</bitOffset>
22037 <bitWidth>1</bitWidth>
22038 </field>
22039 <field>
22040 <name>ODR11</name>
22041 <description>Port output data (y =
22042 0..15)</description>
22043 <bitOffset>11</bitOffset>
22044 <bitWidth>1</bitWidth>
22045 </field>
22046 <field>
22047 <name>ODR10</name>
22048 <description>Port output data (y =
22049 0..15)</description>
22050 <bitOffset>10</bitOffset>
22051 <bitWidth>1</bitWidth>
22052 </field>
22053 <field>
22054 <name>ODR9</name>
22055 <description>Port output data (y =
22056 0..15)</description>
22057 <bitOffset>9</bitOffset>
22058 <bitWidth>1</bitWidth>
22059 </field>
22060 <field>
22061 <name>ODR8</name>
22062 <description>Port output data (y =
22063 0..15)</description>
22064 <bitOffset>8</bitOffset>
22065 <bitWidth>1</bitWidth>
22066 </field>
22067 <field>
22068 <name>ODR7</name>
22069 <description>Port output data (y =
22070 0..15)</description>
22071 <bitOffset>7</bitOffset>
22072 <bitWidth>1</bitWidth>
22073 </field>
22074 <field>
22075 <name>ODR6</name>
22076 <description>Port output data (y =
22077 0..15)</description>
22078 <bitOffset>6</bitOffset>
22079 <bitWidth>1</bitWidth>
22080 </field>
22081 <field>
22082 <name>ODR5</name>
22083 <description>Port output data (y =
22084 0..15)</description>
22085 <bitOffset>5</bitOffset>
22086 <bitWidth>1</bitWidth>
22087 </field>
22088 <field>
22089 <name>ODR4</name>
22090 <description>Port output data (y =
22091 0..15)</description>
22092 <bitOffset>4</bitOffset>
22093 <bitWidth>1</bitWidth>
22094 </field>
22095 <field>
22096 <name>ODR3</name>
22097 <description>Port output data (y =
22098 0..15)</description>
22099 <bitOffset>3</bitOffset>
22100 <bitWidth>1</bitWidth>
22101 </field>
22102 <field>
22103 <name>ODR2</name>
22104 <description>Port output data (y =
22105 0..15)</description>
22106 <bitOffset>2</bitOffset>
22107 <bitWidth>1</bitWidth>
22108 </field>
22109 <field>
22110 <name>ODR1</name>
22111 <description>Port output data (y =
22112 0..15)</description>
22113 <bitOffset>1</bitOffset>
22114 <bitWidth>1</bitWidth>
22115 </field>
22116 <field>
22117 <name>ODR0</name>
22118 <description>Port output data (y =
22119 0..15)</description>
22120 <bitOffset>0</bitOffset>
22121 <bitWidth>1</bitWidth>
22122 </field>
22123 </fields>
22124 </register>
22125 <register>
22126 <name>BSRR</name>
22127 <displayName>BSRR</displayName>
22128 <description>GPIO port bit set/reset
22129 register</description>
22130 <addressOffset>0x18</addressOffset>
22131 <size>0x20</size>
22132 <access>write-only</access>
22133 <resetValue>0x00000000</resetValue>
22134 <fields>
22135 <field>
22136 <name>BR15</name>
22137 <description>Port x reset bit y (y =
22138 0..15)</description>
22139 <bitOffset>31</bitOffset>
22140 <bitWidth>1</bitWidth>
22141 </field>
22142 <field>
22143 <name>BR14</name>
22144 <description>Port x reset bit y (y =
22145 0..15)</description>
22146 <bitOffset>30</bitOffset>
22147 <bitWidth>1</bitWidth>
22148 </field>
22149 <field>
22150 <name>BR13</name>
22151 <description>Port x reset bit y (y =
22152 0..15)</description>
22153 <bitOffset>29</bitOffset>
22154 <bitWidth>1</bitWidth>
22155 </field>
22156 <field>
22157 <name>BR12</name>
22158 <description>Port x reset bit y (y =
22159 0..15)</description>
22160 <bitOffset>28</bitOffset>
22161 <bitWidth>1</bitWidth>
22162 </field>
22163 <field>
22164 <name>BR11</name>
22165 <description>Port x reset bit y (y =
22166 0..15)</description>
22167 <bitOffset>27</bitOffset>
22168 <bitWidth>1</bitWidth>
22169 </field>
22170 <field>
22171 <name>BR10</name>
22172 <description>Port x reset bit y (y =
22173 0..15)</description>
22174 <bitOffset>26</bitOffset>
22175 <bitWidth>1</bitWidth>
22176 </field>
22177 <field>
22178 <name>BR9</name>
22179 <description>Port x reset bit y (y =
22180 0..15)</description>
22181 <bitOffset>25</bitOffset>
22182 <bitWidth>1</bitWidth>
22183 </field>
22184 <field>
22185 <name>BR8</name>
22186 <description>Port x reset bit y (y =
22187 0..15)</description>
22188 <bitOffset>24</bitOffset>
22189 <bitWidth>1</bitWidth>
22190 </field>
22191 <field>
22192 <name>BR7</name>
22193 <description>Port x reset bit y (y =
22194 0..15)</description>
22195 <bitOffset>23</bitOffset>
22196 <bitWidth>1</bitWidth>
22197 </field>
22198 <field>
22199 <name>BR6</name>
22200 <description>Port x reset bit y (y =
22201 0..15)</description>
22202 <bitOffset>22</bitOffset>
22203 <bitWidth>1</bitWidth>
22204 </field>
22205 <field>
22206 <name>BR5</name>
22207 <description>Port x reset bit y (y =
22208 0..15)</description>
22209 <bitOffset>21</bitOffset>
22210 <bitWidth>1</bitWidth>
22211 </field>
22212 <field>
22213 <name>BR4</name>
22214 <description>Port x reset bit y (y =
22215 0..15)</description>
22216 <bitOffset>20</bitOffset>
22217 <bitWidth>1</bitWidth>
22218 </field>
22219 <field>
22220 <name>BR3</name>
22221 <description>Port x reset bit y (y =
22222 0..15)</description>
22223 <bitOffset>19</bitOffset>
22224 <bitWidth>1</bitWidth>
22225 </field>
22226 <field>
22227 <name>BR2</name>
22228 <description>Port x reset bit y (y =
22229 0..15)</description>
22230 <bitOffset>18</bitOffset>
22231 <bitWidth>1</bitWidth>
22232 </field>
22233 <field>
22234 <name>BR1</name>
22235 <description>Port x reset bit y (y =
22236 0..15)</description>
22237 <bitOffset>17</bitOffset>
22238 <bitWidth>1</bitWidth>
22239 </field>
22240 <field>
22241 <name>BR0</name>
22242 <description>Port x set bit y (y=
22243 0..15)</description>
22244 <bitOffset>16</bitOffset>
22245 <bitWidth>1</bitWidth>
22246 </field>
22247 <field>
22248 <name>BS15</name>
22249 <description>Port x set bit y (y=
22250 0..15)</description>
22251 <bitOffset>15</bitOffset>
22252 <bitWidth>1</bitWidth>
22253 </field>
22254 <field>
22255 <name>BS14</name>
22256 <description>Port x set bit y (y=
22257 0..15)</description>
22258 <bitOffset>14</bitOffset>
22259 <bitWidth>1</bitWidth>
22260 </field>
22261 <field>
22262 <name>BS13</name>
22263 <description>Port x set bit y (y=
22264 0..15)</description>
22265 <bitOffset>13</bitOffset>
22266 <bitWidth>1</bitWidth>
22267 </field>
22268 <field>
22269 <name>BS12</name>
22270 <description>Port x set bit y (y=
22271 0..15)</description>
22272 <bitOffset>12</bitOffset>
22273 <bitWidth>1</bitWidth>
22274 </field>
22275 <field>
22276 <name>BS11</name>
22277 <description>Port x set bit y (y=
22278 0..15)</description>
22279 <bitOffset>11</bitOffset>
22280 <bitWidth>1</bitWidth>
22281 </field>
22282 <field>
22283 <name>BS10</name>
22284 <description>Port x set bit y (y=
22285 0..15)</description>
22286 <bitOffset>10</bitOffset>
22287 <bitWidth>1</bitWidth>
22288 </field>
22289 <field>
22290 <name>BS9</name>
22291 <description>Port x set bit y (y=
22292 0..15)</description>
22293 <bitOffset>9</bitOffset>
22294 <bitWidth>1</bitWidth>
22295 </field>
22296 <field>
22297 <name>BS8</name>
22298 <description>Port x set bit y (y=
22299 0..15)</description>
22300 <bitOffset>8</bitOffset>
22301 <bitWidth>1</bitWidth>
22302 </field>
22303 <field>
22304 <name>BS7</name>
22305 <description>Port x set bit y (y=
22306 0..15)</description>
22307 <bitOffset>7</bitOffset>
22308 <bitWidth>1</bitWidth>
22309 </field>
22310 <field>
22311 <name>BS6</name>
22312 <description>Port x set bit y (y=
22313 0..15)</description>
22314 <bitOffset>6</bitOffset>
22315 <bitWidth>1</bitWidth>
22316 </field>
22317 <field>
22318 <name>BS5</name>
22319 <description>Port x set bit y (y=
22320 0..15)</description>
22321 <bitOffset>5</bitOffset>
22322 <bitWidth>1</bitWidth>
22323 </field>
22324 <field>
22325 <name>BS4</name>
22326 <description>Port x set bit y (y=
22327 0..15)</description>
22328 <bitOffset>4</bitOffset>
22329 <bitWidth>1</bitWidth>
22330 </field>
22331 <field>
22332 <name>BS3</name>
22333 <description>Port x set bit y (y=
22334 0..15)</description>
22335 <bitOffset>3</bitOffset>
22336 <bitWidth>1</bitWidth>
22337 </field>
22338 <field>
22339 <name>BS2</name>
22340 <description>Port x set bit y (y=
22341 0..15)</description>
22342 <bitOffset>2</bitOffset>
22343 <bitWidth>1</bitWidth>
22344 </field>
22345 <field>
22346 <name>BS1</name>
22347 <description>Port x set bit y (y=
22348 0..15)</description>
22349 <bitOffset>1</bitOffset>
22350 <bitWidth>1</bitWidth>
22351 </field>
22352 <field>
22353 <name>BS0</name>
22354 <description>Port x set bit y (y=
22355 0..15)</description>
22356 <bitOffset>0</bitOffset>
22357 <bitWidth>1</bitWidth>
22358 </field>
22359 </fields>
22360 </register>
22361 <register>
22362 <name>LCKR</name>
22363 <displayName>LCKR</displayName>
22364 <description>GPIO port configuration lock
22365 register</description>
22366 <addressOffset>0x1C</addressOffset>
22367 <size>0x20</size>
22368 <access>read-write</access>
22369 <resetValue>0x00000000</resetValue>
22370 <fields>
22371 <field>
22372 <name>LCKK</name>
22373 <description>Port x lock bit y (y=
22374 0..15)</description>
22375 <bitOffset>16</bitOffset>
22376 <bitWidth>1</bitWidth>
22377 </field>
22378 <field>
22379 <name>LCK15</name>
22380 <description>Port x lock bit y (y=
22381 0..15)</description>
22382 <bitOffset>15</bitOffset>
22383 <bitWidth>1</bitWidth>
22384 </field>
22385 <field>
22386 <name>LCK14</name>
22387 <description>Port x lock bit y (y=
22388 0..15)</description>
22389 <bitOffset>14</bitOffset>
22390 <bitWidth>1</bitWidth>
22391 </field>
22392 <field>
22393 <name>LCK13</name>
22394 <description>Port x lock bit y (y=
22395 0..15)</description>
22396 <bitOffset>13</bitOffset>
22397 <bitWidth>1</bitWidth>
22398 </field>
22399 <field>
22400 <name>LCK12</name>
22401 <description>Port x lock bit y (y=
22402 0..15)</description>
22403 <bitOffset>12</bitOffset>
22404 <bitWidth>1</bitWidth>
22405 </field>
22406 <field>
22407 <name>LCK11</name>
22408 <description>Port x lock bit y (y=
22409 0..15)</description>
22410 <bitOffset>11</bitOffset>
22411 <bitWidth>1</bitWidth>
22412 </field>
22413 <field>
22414 <name>LCK10</name>
22415 <description>Port x lock bit y (y=
22416 0..15)</description>
22417 <bitOffset>10</bitOffset>
22418 <bitWidth>1</bitWidth>
22419 </field>
22420 <field>
22421 <name>LCK9</name>
22422 <description>Port x lock bit y (y=
22423 0..15)</description>
22424 <bitOffset>9</bitOffset>
22425 <bitWidth>1</bitWidth>
22426 </field>
22427 <field>
22428 <name>LCK8</name>
22429 <description>Port x lock bit y (y=
22430 0..15)</description>
22431 <bitOffset>8</bitOffset>
22432 <bitWidth>1</bitWidth>
22433 </field>
22434 <field>
22435 <name>LCK7</name>
22436 <description>Port x lock bit y (y=
22437 0..15)</description>
22438 <bitOffset>7</bitOffset>
22439 <bitWidth>1</bitWidth>
22440 </field>
22441 <field>
22442 <name>LCK6</name>
22443 <description>Port x lock bit y (y=
22444 0..15)</description>
22445 <bitOffset>6</bitOffset>
22446 <bitWidth>1</bitWidth>
22447 </field>
22448 <field>
22449 <name>LCK5</name>
22450 <description>Port x lock bit y (y=
22451 0..15)</description>
22452 <bitOffset>5</bitOffset>
22453 <bitWidth>1</bitWidth>
22454 </field>
22455 <field>
22456 <name>LCK4</name>
22457 <description>Port x lock bit y (y=
22458 0..15)</description>
22459 <bitOffset>4</bitOffset>
22460 <bitWidth>1</bitWidth>
22461 </field>
22462 <field>
22463 <name>LCK3</name>
22464 <description>Port x lock bit y (y=
22465 0..15)</description>
22466 <bitOffset>3</bitOffset>
22467 <bitWidth>1</bitWidth>
22468 </field>
22469 <field>
22470 <name>LCK2</name>
22471 <description>Port x lock bit y (y=
22472 0..15)</description>
22473 <bitOffset>2</bitOffset>
22474 <bitWidth>1</bitWidth>
22475 </field>
22476 <field>
22477 <name>LCK1</name>
22478 <description>Port x lock bit y (y=
22479 0..15)</description>
22480 <bitOffset>1</bitOffset>
22481 <bitWidth>1</bitWidth>
22482 </field>
22483 <field>
22484 <name>LCK0</name>
22485 <description>Port x lock bit y (y=
22486 0..15)</description>
22487 <bitOffset>0</bitOffset>
22488 <bitWidth>1</bitWidth>
22489 </field>
22490 </fields>
22491 </register>
22492 <register>
22493 <name>AFRL</name>
22494 <displayName>AFRL</displayName>
22495 <description>GPIO alternate function low
22496 register</description>
22497 <addressOffset>0x20</addressOffset>
22498 <size>0x20</size>
22499 <access>read-write</access>
22500 <resetValue>0x00000000</resetValue>
22501 <fields>
22502 <field>
22503 <name>AFRL7</name>
22504 <description>Alternate function selection for port x
22505 bit y (y = 0..7)</description>
22506 <bitOffset>28</bitOffset>
22507 <bitWidth>4</bitWidth>
22508 </field>
22509 <field>
22510 <name>AFRL6</name>
22511 <description>Alternate function selection for port x
22512 bit y (y = 0..7)</description>
22513 <bitOffset>24</bitOffset>
22514 <bitWidth>4</bitWidth>
22515 </field>
22516 <field>
22517 <name>AFRL5</name>
22518 <description>Alternate function selection for port x
22519 bit y (y = 0..7)</description>
22520 <bitOffset>20</bitOffset>
22521 <bitWidth>4</bitWidth>
22522 </field>
22523 <field>
22524 <name>AFRL4</name>
22525 <description>Alternate function selection for port x
22526 bit y (y = 0..7)</description>
22527 <bitOffset>16</bitOffset>
22528 <bitWidth>4</bitWidth>
22529 </field>
22530 <field>
22531 <name>AFRL3</name>
22532 <description>Alternate function selection for port x
22533 bit y (y = 0..7)</description>
22534 <bitOffset>12</bitOffset>
22535 <bitWidth>4</bitWidth>
22536 </field>
22537 <field>
22538 <name>AFRL2</name>
22539 <description>Alternate function selection for port x
22540 bit y (y = 0..7)</description>
22541 <bitOffset>8</bitOffset>
22542 <bitWidth>4</bitWidth>
22543 </field>
22544 <field>
22545 <name>AFRL1</name>
22546 <description>Alternate function selection for port x
22547 bit y (y = 0..7)</description>
22548 <bitOffset>4</bitOffset>
22549 <bitWidth>4</bitWidth>
22550 </field>
22551 <field>
22552 <name>AFRL0</name>
22553 <description>Alternate function selection for port x
22554 bit y (y = 0..7)</description>
22555 <bitOffset>0</bitOffset>
22556 <bitWidth>4</bitWidth>
22557 </field>
22558 </fields>
22559 </register>
22560 <register>
22561 <name>AFRH</name>
22562 <displayName>AFRH</displayName>
22563 <description>GPIO alternate function high
22564 register</description>
22565 <addressOffset>0x24</addressOffset>
22566 <size>0x20</size>
22567 <access>read-write</access>
22568 <resetValue>0x00000000</resetValue>
22569 <fields>
22570 <field>
22571 <name>AFRH15</name>
22572 <description>Alternate function selection for port x
22573 bit y (y = 8..15)</description>
22574 <bitOffset>28</bitOffset>
22575 <bitWidth>4</bitWidth>
22576 </field>
22577 <field>
22578 <name>AFRH14</name>
22579 <description>Alternate function selection for port x
22580 bit y (y = 8..15)</description>
22581 <bitOffset>24</bitOffset>
22582 <bitWidth>4</bitWidth>
22583 </field>
22584 <field>
22585 <name>AFRH13</name>
22586 <description>Alternate function selection for port x
22587 bit y (y = 8..15)</description>
22588 <bitOffset>20</bitOffset>
22589 <bitWidth>4</bitWidth>
22590 </field>
22591 <field>
22592 <name>AFRH12</name>
22593 <description>Alternate function selection for port x
22594 bit y (y = 8..15)</description>
22595 <bitOffset>16</bitOffset>
22596 <bitWidth>4</bitWidth>
22597 </field>
22598 <field>
22599 <name>AFRH11</name>
22600 <description>Alternate function selection for port x
22601 bit y (y = 8..15)</description>
22602 <bitOffset>12</bitOffset>
22603 <bitWidth>4</bitWidth>
22604 </field>
22605 <field>
22606 <name>AFRH10</name>
22607 <description>Alternate function selection for port x
22608 bit y (y = 8..15)</description>
22609 <bitOffset>8</bitOffset>
22610 <bitWidth>4</bitWidth>
22611 </field>
22612 <field>
22613 <name>AFRH9</name>
22614 <description>Alternate function selection for port x
22615 bit y (y = 8..15)</description>
22616 <bitOffset>4</bitOffset>
22617 <bitWidth>4</bitWidth>
22618 </field>
22619 <field>
22620 <name>AFRH8</name>
22621 <description>Alternate function selection for port x
22622 bit y (y = 8..15)</description>
22623 <bitOffset>0</bitOffset>
22624 <bitWidth>4</bitWidth>
22625 </field>
22626 </fields>
22627 </register>
22628 </registers>
22629 </peripheral>
22630 <peripheral>
22631 <name>GPIOA</name>
22632 <description>General-purpose I/Os</description>
22633 <groupName>GPIO</groupName>
22634 <baseAddress>0x40020000</baseAddress>
22635 <addressBlock>
22636 <offset>0x0</offset>
22637 <size>0x400</size>
22638 <usage>registers</usage>
22639 </addressBlock>
22640 <interrupt>
22641 <name>TIM2</name>
22642 <description>TIM2 global interrupt</description>
22643 <value>28</value>
22644 </interrupt>
22645 <registers>
22646 <register>
22647 <name>MODER</name>
22648 <displayName>MODER</displayName>
22649 <description>GPIO port mode register</description>
22650 <addressOffset>0x0</addressOffset>
22651 <size>0x20</size>
22652 <access>read-write</access>
22653 <resetValue>0xA8000000</resetValue>
22654 <fields>
22655 <field>
22656 <name>MODER15</name>
22657 <description>Port x configuration bits (y =
22658 0..15)</description>
22659 <bitOffset>30</bitOffset>
22660 <bitWidth>2</bitWidth>
22661 </field>
22662 <field>
22663 <name>MODER14</name>
22664 <description>Port x configuration bits (y =
22665 0..15)</description>
22666 <bitOffset>28</bitOffset>
22667 <bitWidth>2</bitWidth>
22668 </field>
22669 <field>
22670 <name>MODER13</name>
22671 <description>Port x configuration bits (y =
22672 0..15)</description>
22673 <bitOffset>26</bitOffset>
22674 <bitWidth>2</bitWidth>
22675 </field>
22676 <field>
22677 <name>MODER12</name>
22678 <description>Port x configuration bits (y =
22679 0..15)</description>
22680 <bitOffset>24</bitOffset>
22681 <bitWidth>2</bitWidth>
22682 </field>
22683 <field>
22684 <name>MODER11</name>
22685 <description>Port x configuration bits (y =
22686 0..15)</description>
22687 <bitOffset>22</bitOffset>
22688 <bitWidth>2</bitWidth>
22689 </field>
22690 <field>
22691 <name>MODER10</name>
22692 <description>Port x configuration bits (y =
22693 0..15)</description>
22694 <bitOffset>20</bitOffset>
22695 <bitWidth>2</bitWidth>
22696 </field>
22697 <field>
22698 <name>MODER9</name>
22699 <description>Port x configuration bits (y =
22700 0..15)</description>
22701 <bitOffset>18</bitOffset>
22702 <bitWidth>2</bitWidth>
22703 </field>
22704 <field>
22705 <name>MODER8</name>
22706 <description>Port x configuration bits (y =
22707 0..15)</description>
22708 <bitOffset>16</bitOffset>
22709 <bitWidth>2</bitWidth>
22710 </field>
22711 <field>
22712 <name>MODER7</name>
22713 <description>Port x configuration bits (y =
22714 0..15)</description>
22715 <bitOffset>14</bitOffset>
22716 <bitWidth>2</bitWidth>
22717 </field>
22718 <field>
22719 <name>MODER6</name>
22720 <description>Port x configuration bits (y =
22721 0..15)</description>
22722 <bitOffset>12</bitOffset>
22723 <bitWidth>2</bitWidth>
22724 </field>
22725 <field>
22726 <name>MODER5</name>
22727 <description>Port x configuration bits (y =
22728 0..15)</description>
22729 <bitOffset>10</bitOffset>
22730 <bitWidth>2</bitWidth>
22731 </field>
22732 <field>
22733 <name>MODER4</name>
22734 <description>Port x configuration bits (y =
22735 0..15)</description>
22736 <bitOffset>8</bitOffset>
22737 <bitWidth>2</bitWidth>
22738 </field>
22739 <field>
22740 <name>MODER3</name>
22741 <description>Port x configuration bits (y =
22742 0..15)</description>
22743 <bitOffset>6</bitOffset>
22744 <bitWidth>2</bitWidth>
22745 </field>
22746 <field>
22747 <name>MODER2</name>
22748 <description>Port x configuration bits (y =
22749 0..15)</description>
22750 <bitOffset>4</bitOffset>
22751 <bitWidth>2</bitWidth>
22752 </field>
22753 <field>
22754 <name>MODER1</name>
22755 <description>Port x configuration bits (y =
22756 0..15)</description>
22757 <bitOffset>2</bitOffset>
22758 <bitWidth>2</bitWidth>
22759 </field>
22760 <field>
22761 <name>MODER0</name>
22762 <description>Port x configuration bits (y =
22763 0..15)</description>
22764 <bitOffset>0</bitOffset>
22765 <bitWidth>2</bitWidth>
22766 </field>
22767 </fields>
22768 </register>
22769 <register>
22770 <name>OTYPER</name>
22771 <displayName>OTYPER</displayName>
22772 <description>GPIO port output type register</description>
22773 <addressOffset>0x4</addressOffset>
22774 <size>0x20</size>
22775 <access>read-write</access>
22776 <resetValue>0x00000000</resetValue>
22777 <fields>
22778 <field>
22779 <name>OT15</name>
22780 <description>Port x configuration bits (y =
22781 0..15)</description>
22782 <bitOffset>15</bitOffset>
22783 <bitWidth>1</bitWidth>
22784 </field>
22785 <field>
22786 <name>OT14</name>
22787 <description>Port x configuration bits (y =
22788 0..15)</description>
22789 <bitOffset>14</bitOffset>
22790 <bitWidth>1</bitWidth>
22791 </field>
22792 <field>
22793 <name>OT13</name>
22794 <description>Port x configuration bits (y =
22795 0..15)</description>
22796 <bitOffset>13</bitOffset>
22797 <bitWidth>1</bitWidth>
22798 </field>
22799 <field>
22800 <name>OT12</name>
22801 <description>Port x configuration bits (y =
22802 0..15)</description>
22803 <bitOffset>12</bitOffset>
22804 <bitWidth>1</bitWidth>
22805 </field>
22806 <field>
22807 <name>OT11</name>
22808 <description>Port x configuration bits (y =
22809 0..15)</description>
22810 <bitOffset>11</bitOffset>
22811 <bitWidth>1</bitWidth>
22812 </field>
22813 <field>
22814 <name>OT10</name>
22815 <description>Port x configuration bits (y =
22816 0..15)</description>
22817 <bitOffset>10</bitOffset>
22818 <bitWidth>1</bitWidth>
22819 </field>
22820 <field>
22821 <name>OT9</name>
22822 <description>Port x configuration bits (y =
22823 0..15)</description>
22824 <bitOffset>9</bitOffset>
22825 <bitWidth>1</bitWidth>
22826 </field>
22827 <field>
22828 <name>OT8</name>
22829 <description>Port x configuration bits (y =
22830 0..15)</description>
22831 <bitOffset>8</bitOffset>
22832 <bitWidth>1</bitWidth>
22833 </field>
22834 <field>
22835 <name>OT7</name>
22836 <description>Port x configuration bits (y =
22837 0..15)</description>
22838 <bitOffset>7</bitOffset>
22839 <bitWidth>1</bitWidth>
22840 </field>
22841 <field>
22842 <name>OT6</name>
22843 <description>Port x configuration bits (y =
22844 0..15)</description>
22845 <bitOffset>6</bitOffset>
22846 <bitWidth>1</bitWidth>
22847 </field>
22848 <field>
22849 <name>OT5</name>
22850 <description>Port x configuration bits (y =
22851 0..15)</description>
22852 <bitOffset>5</bitOffset>
22853 <bitWidth>1</bitWidth>
22854 </field>
22855 <field>
22856 <name>OT4</name>
22857 <description>Port x configuration bits (y =
22858 0..15)</description>
22859 <bitOffset>4</bitOffset>
22860 <bitWidth>1</bitWidth>
22861 </field>
22862 <field>
22863 <name>OT3</name>
22864 <description>Port x configuration bits (y =
22865 0..15)</description>
22866 <bitOffset>3</bitOffset>
22867 <bitWidth>1</bitWidth>
22868 </field>
22869 <field>
22870 <name>OT2</name>
22871 <description>Port x configuration bits (y =
22872 0..15)</description>
22873 <bitOffset>2</bitOffset>
22874 <bitWidth>1</bitWidth>
22875 </field>
22876 <field>
22877 <name>OT1</name>
22878 <description>Port x configuration bits (y =
22879 0..15)</description>
22880 <bitOffset>1</bitOffset>
22881 <bitWidth>1</bitWidth>
22882 </field>
22883 <field>
22884 <name>OT0</name>
22885 <description>Port x configuration bits (y =
22886 0..15)</description>
22887 <bitOffset>0</bitOffset>
22888 <bitWidth>1</bitWidth>
22889 </field>
22890 </fields>
22891 </register>
22892 <register>
22893 <name>OSPEEDR</name>
22894 <displayName>OSPEEDR</displayName>
22895 <description>GPIO port output speed
22896 register</description>
22897 <addressOffset>0x8</addressOffset>
22898 <size>0x20</size>
22899 <access>read-write</access>
22900 <resetValue>0x00000000</resetValue>
22901 <fields>
22902 <field>
22903 <name>OSPEEDR15</name>
22904 <description>Port x configuration bits (y =
22905 0..15)</description>
22906 <bitOffset>30</bitOffset>
22907 <bitWidth>2</bitWidth>
22908 </field>
22909 <field>
22910 <name>OSPEEDR14</name>
22911 <description>Port x configuration bits (y =
22912 0..15)</description>
22913 <bitOffset>28</bitOffset>
22914 <bitWidth>2</bitWidth>
22915 </field>
22916 <field>
22917 <name>OSPEEDR13</name>
22918 <description>Port x configuration bits (y =
22919 0..15)</description>
22920 <bitOffset>26</bitOffset>
22921 <bitWidth>2</bitWidth>
22922 </field>
22923 <field>
22924 <name>OSPEEDR12</name>
22925 <description>Port x configuration bits (y =
22926 0..15)</description>
22927 <bitOffset>24</bitOffset>
22928 <bitWidth>2</bitWidth>
22929 </field>
22930 <field>
22931 <name>OSPEEDR11</name>
22932 <description>Port x configuration bits (y =
22933 0..15)</description>
22934 <bitOffset>22</bitOffset>
22935 <bitWidth>2</bitWidth>
22936 </field>
22937 <field>
22938 <name>OSPEEDR10</name>
22939 <description>Port x configuration bits (y =
22940 0..15)</description>
22941 <bitOffset>20</bitOffset>
22942 <bitWidth>2</bitWidth>
22943 </field>
22944 <field>
22945 <name>OSPEEDR9</name>
22946 <description>Port x configuration bits (y =
22947 0..15)</description>
22948 <bitOffset>18</bitOffset>
22949 <bitWidth>2</bitWidth>
22950 </field>
22951 <field>
22952 <name>OSPEEDR8</name>
22953 <description>Port x configuration bits (y =
22954 0..15)</description>
22955 <bitOffset>16</bitOffset>
22956 <bitWidth>2</bitWidth>
22957 </field>
22958 <field>
22959 <name>OSPEEDR7</name>
22960 <description>Port x configuration bits (y =
22961 0..15)</description>
22962 <bitOffset>14</bitOffset>
22963 <bitWidth>2</bitWidth>
22964 </field>
22965 <field>
22966 <name>OSPEEDR6</name>
22967 <description>Port x configuration bits (y =
22968 0..15)</description>
22969 <bitOffset>12</bitOffset>
22970 <bitWidth>2</bitWidth>
22971 </field>
22972 <field>
22973 <name>OSPEEDR5</name>
22974 <description>Port x configuration bits (y =
22975 0..15)</description>
22976 <bitOffset>10</bitOffset>
22977 <bitWidth>2</bitWidth>
22978 </field>
22979 <field>
22980 <name>OSPEEDR4</name>
22981 <description>Port x configuration bits (y =
22982 0..15)</description>
22983 <bitOffset>8</bitOffset>
22984 <bitWidth>2</bitWidth>
22985 </field>
22986 <field>
22987 <name>OSPEEDR3</name>
22988 <description>Port x configuration bits (y =
22989 0..15)</description>
22990 <bitOffset>6</bitOffset>
22991 <bitWidth>2</bitWidth>
22992 </field>
22993 <field>
22994 <name>OSPEEDR2</name>
22995 <description>Port x configuration bits (y =
22996 0..15)</description>
22997 <bitOffset>4</bitOffset>
22998 <bitWidth>2</bitWidth>
22999 </field>
23000 <field>
23001 <name>OSPEEDR1</name>
23002 <description>Port x configuration bits (y =
23003 0..15)</description>
23004 <bitOffset>2</bitOffset>
23005 <bitWidth>2</bitWidth>
23006 </field>
23007 <field>
23008 <name>OSPEEDR0</name>
23009 <description>Port x configuration bits (y =
23010 0..15)</description>
23011 <bitOffset>0</bitOffset>
23012 <bitWidth>2</bitWidth>
23013 </field>
23014 </fields>
23015 </register>
23016 <register>
23017 <name>PUPDR</name>
23018 <displayName>PUPDR</displayName>
23019 <description>GPIO port pull-up/pull-down
23020 register</description>
23021 <addressOffset>0xC</addressOffset>
23022 <size>0x20</size>
23023 <access>read-write</access>
23024 <resetValue>0x64000000</resetValue>
23025 <fields>
23026 <field>
23027 <name>PUPDR15</name>
23028 <description>Port x configuration bits (y =
23029 0..15)</description>
23030 <bitOffset>30</bitOffset>
23031 <bitWidth>2</bitWidth>
23032 </field>
23033 <field>
23034 <name>PUPDR14</name>
23035 <description>Port x configuration bits (y =
23036 0..15)</description>
23037 <bitOffset>28</bitOffset>
23038 <bitWidth>2</bitWidth>
23039 </field>
23040 <field>
23041 <name>PUPDR13</name>
23042 <description>Port x configuration bits (y =
23043 0..15)</description>
23044 <bitOffset>26</bitOffset>
23045 <bitWidth>2</bitWidth>
23046 </field>
23047 <field>
23048 <name>PUPDR12</name>
23049 <description>Port x configuration bits (y =
23050 0..15)</description>
23051 <bitOffset>24</bitOffset>
23052 <bitWidth>2</bitWidth>
23053 </field>
23054 <field>
23055 <name>PUPDR11</name>
23056 <description>Port x configuration bits (y =
23057 0..15)</description>
23058 <bitOffset>22</bitOffset>
23059 <bitWidth>2</bitWidth>
23060 </field>
23061 <field>
23062 <name>PUPDR10</name>
23063 <description>Port x configuration bits (y =
23064 0..15)</description>
23065 <bitOffset>20</bitOffset>
23066 <bitWidth>2</bitWidth>
23067 </field>
23068 <field>
23069 <name>PUPDR9</name>
23070 <description>Port x configuration bits (y =
23071 0..15)</description>
23072 <bitOffset>18</bitOffset>
23073 <bitWidth>2</bitWidth>
23074 </field>
23075 <field>
23076 <name>PUPDR8</name>
23077 <description>Port x configuration bits (y =
23078 0..15)</description>
23079 <bitOffset>16</bitOffset>
23080 <bitWidth>2</bitWidth>
23081 </field>
23082 <field>
23083 <name>PUPDR7</name>
23084 <description>Port x configuration bits (y =
23085 0..15)</description>
23086 <bitOffset>14</bitOffset>
23087 <bitWidth>2</bitWidth>
23088 </field>
23089 <field>
23090 <name>PUPDR6</name>
23091 <description>Port x configuration bits (y =
23092 0..15)</description>
23093 <bitOffset>12</bitOffset>
23094 <bitWidth>2</bitWidth>
23095 </field>
23096 <field>
23097 <name>PUPDR5</name>
23098 <description>Port x configuration bits (y =
23099 0..15)</description>
23100 <bitOffset>10</bitOffset>
23101 <bitWidth>2</bitWidth>
23102 </field>
23103 <field>
23104 <name>PUPDR4</name>
23105 <description>Port x configuration bits (y =
23106 0..15)</description>
23107 <bitOffset>8</bitOffset>
23108 <bitWidth>2</bitWidth>
23109 </field>
23110 <field>
23111 <name>PUPDR3</name>
23112 <description>Port x configuration bits (y =
23113 0..15)</description>
23114 <bitOffset>6</bitOffset>
23115 <bitWidth>2</bitWidth>
23116 </field>
23117 <field>
23118 <name>PUPDR2</name>
23119 <description>Port x configuration bits (y =
23120 0..15)</description>
23121 <bitOffset>4</bitOffset>
23122 <bitWidth>2</bitWidth>
23123 </field>
23124 <field>
23125 <name>PUPDR1</name>
23126 <description>Port x configuration bits (y =
23127 0..15)</description>
23128 <bitOffset>2</bitOffset>
23129 <bitWidth>2</bitWidth>
23130 </field>
23131 <field>
23132 <name>PUPDR0</name>
23133 <description>Port x configuration bits (y =
23134 0..15)</description>
23135 <bitOffset>0</bitOffset>
23136 <bitWidth>2</bitWidth>
23137 </field>
23138 </fields>
23139 </register>
23140 <register>
23141 <name>IDR</name>
23142 <displayName>IDR</displayName>
23143 <description>GPIO port input data register</description>
23144 <addressOffset>0x10</addressOffset>
23145 <size>0x20</size>
23146 <access>read-only</access>
23147 <resetValue>0x00000000</resetValue>
23148 <fields>
23149 <field>
23150 <name>IDR15</name>
23151 <description>Port input data (y =
23152 0..15)</description>
23153 <bitOffset>15</bitOffset>
23154 <bitWidth>1</bitWidth>
23155 </field>
23156 <field>
23157 <name>IDR14</name>
23158 <description>Port input data (y =
23159 0..15)</description>
23160 <bitOffset>14</bitOffset>
23161 <bitWidth>1</bitWidth>
23162 </field>
23163 <field>
23164 <name>IDR13</name>
23165 <description>Port input data (y =
23166 0..15)</description>
23167 <bitOffset>13</bitOffset>
23168 <bitWidth>1</bitWidth>
23169 </field>
23170 <field>
23171 <name>IDR12</name>
23172 <description>Port input data (y =
23173 0..15)</description>
23174 <bitOffset>12</bitOffset>
23175 <bitWidth>1</bitWidth>
23176 </field>
23177 <field>
23178 <name>IDR11</name>
23179 <description>Port input data (y =
23180 0..15)</description>
23181 <bitOffset>11</bitOffset>
23182 <bitWidth>1</bitWidth>
23183 </field>
23184 <field>
23185 <name>IDR10</name>
23186 <description>Port input data (y =
23187 0..15)</description>
23188 <bitOffset>10</bitOffset>
23189 <bitWidth>1</bitWidth>
23190 </field>
23191 <field>
23192 <name>IDR9</name>
23193 <description>Port input data (y =
23194 0..15)</description>
23195 <bitOffset>9</bitOffset>
23196 <bitWidth>1</bitWidth>
23197 </field>
23198 <field>
23199 <name>IDR8</name>
23200 <description>Port input data (y =
23201 0..15)</description>
23202 <bitOffset>8</bitOffset>
23203 <bitWidth>1</bitWidth>
23204 </field>
23205 <field>
23206 <name>IDR7</name>
23207 <description>Port input data (y =
23208 0..15)</description>
23209 <bitOffset>7</bitOffset>
23210 <bitWidth>1</bitWidth>
23211 </field>
23212 <field>
23213 <name>IDR6</name>
23214 <description>Port input data (y =
23215 0..15)</description>
23216 <bitOffset>6</bitOffset>
23217 <bitWidth>1</bitWidth>
23218 </field>
23219 <field>
23220 <name>IDR5</name>
23221 <description>Port input data (y =
23222 0..15)</description>
23223 <bitOffset>5</bitOffset>
23224 <bitWidth>1</bitWidth>
23225 </field>
23226 <field>
23227 <name>IDR4</name>
23228 <description>Port input data (y =
23229 0..15)</description>
23230 <bitOffset>4</bitOffset>
23231 <bitWidth>1</bitWidth>
23232 </field>
23233 <field>
23234 <name>IDR3</name>
23235 <description>Port input data (y =
23236 0..15)</description>
23237 <bitOffset>3</bitOffset>
23238 <bitWidth>1</bitWidth>
23239 </field>
23240 <field>
23241 <name>IDR2</name>
23242 <description>Port input data (y =
23243 0..15)</description>
23244 <bitOffset>2</bitOffset>
23245 <bitWidth>1</bitWidth>
23246 </field>
23247 <field>
23248 <name>IDR1</name>
23249 <description>Port input data (y =
23250 0..15)</description>
23251 <bitOffset>1</bitOffset>
23252 <bitWidth>1</bitWidth>
23253 </field>
23254 <field>
23255 <name>IDR0</name>
23256 <description>Port input data (y =
23257 0..15)</description>
23258 <bitOffset>0</bitOffset>
23259 <bitWidth>1</bitWidth>
23260 </field>
23261 </fields>
23262 </register>
23263 <register>
23264 <name>ODR</name>
23265 <displayName>ODR</displayName>
23266 <description>GPIO port output data register</description>
23267 <addressOffset>0x14</addressOffset>
23268 <size>0x20</size>
23269 <access>read-write</access>
23270 <resetValue>0x00000000</resetValue>
23271 <fields>
23272 <field>
23273 <name>ODR15</name>
23274 <description>Port output data (y =
23275 0..15)</description>
23276 <bitOffset>15</bitOffset>
23277 <bitWidth>1</bitWidth>
23278 </field>
23279 <field>
23280 <name>ODR14</name>
23281 <description>Port output data (y =
23282 0..15)</description>
23283 <bitOffset>14</bitOffset>
23284 <bitWidth>1</bitWidth>
23285 </field>
23286 <field>
23287 <name>ODR13</name>
23288 <description>Port output data (y =
23289 0..15)</description>
23290 <bitOffset>13</bitOffset>
23291 <bitWidth>1</bitWidth>
23292 </field>
23293 <field>
23294 <name>ODR12</name>
23295 <description>Port output data (y =
23296 0..15)</description>
23297 <bitOffset>12</bitOffset>
23298 <bitWidth>1</bitWidth>
23299 </field>
23300 <field>
23301 <name>ODR11</name>
23302 <description>Port output data (y =
23303 0..15)</description>
23304 <bitOffset>11</bitOffset>
23305 <bitWidth>1</bitWidth>
23306 </field>
23307 <field>
23308 <name>ODR10</name>
23309 <description>Port output data (y =
23310 0..15)</description>
23311 <bitOffset>10</bitOffset>
23312 <bitWidth>1</bitWidth>
23313 </field>
23314 <field>
23315 <name>ODR9</name>
23316 <description>Port output data (y =
23317 0..15)</description>
23318 <bitOffset>9</bitOffset>
23319 <bitWidth>1</bitWidth>
23320 </field>
23321 <field>
23322 <name>ODR8</name>
23323 <description>Port output data (y =
23324 0..15)</description>
23325 <bitOffset>8</bitOffset>
23326 <bitWidth>1</bitWidth>
23327 </field>
23328 <field>
23329 <name>ODR7</name>
23330 <description>Port output data (y =
23331 0..15)</description>
23332 <bitOffset>7</bitOffset>
23333 <bitWidth>1</bitWidth>
23334 </field>
23335 <field>
23336 <name>ODR6</name>
23337 <description>Port output data (y =
23338 0..15)</description>
23339 <bitOffset>6</bitOffset>
23340 <bitWidth>1</bitWidth>
23341 </field>
23342 <field>
23343 <name>ODR5</name>
23344 <description>Port output data (y =
23345 0..15)</description>
23346 <bitOffset>5</bitOffset>
23347 <bitWidth>1</bitWidth>
23348 </field>
23349 <field>
23350 <name>ODR4</name>
23351 <description>Port output data (y =
23352 0..15)</description>
23353 <bitOffset>4</bitOffset>
23354 <bitWidth>1</bitWidth>
23355 </field>
23356 <field>
23357 <name>ODR3</name>
23358 <description>Port output data (y =
23359 0..15)</description>
23360 <bitOffset>3</bitOffset>
23361 <bitWidth>1</bitWidth>
23362 </field>
23363 <field>
23364 <name>ODR2</name>
23365 <description>Port output data (y =
23366 0..15)</description>
23367 <bitOffset>2</bitOffset>
23368 <bitWidth>1</bitWidth>
23369 </field>
23370 <field>
23371 <name>ODR1</name>
23372 <description>Port output data (y =
23373 0..15)</description>
23374 <bitOffset>1</bitOffset>
23375 <bitWidth>1</bitWidth>
23376 </field>
23377 <field>
23378 <name>ODR0</name>
23379 <description>Port output data (y =
23380 0..15)</description>
23381 <bitOffset>0</bitOffset>
23382 <bitWidth>1</bitWidth>
23383 </field>
23384 </fields>
23385 </register>
23386 <register>
23387 <name>BSRR</name>
23388 <displayName>BSRR</displayName>
23389 <description>GPIO port bit set/reset
23390 register</description>
23391 <addressOffset>0x18</addressOffset>
23392 <size>0x20</size>
23393 <access>write-only</access>
23394 <resetValue>0x00000000</resetValue>
23395 <fields>
23396 <field>
23397 <name>BR15</name>
23398 <description>Port x reset bit y (y =
23399 0..15)</description>
23400 <bitOffset>31</bitOffset>
23401 <bitWidth>1</bitWidth>
23402 </field>
23403 <field>
23404 <name>BR14</name>
23405 <description>Port x reset bit y (y =
23406 0..15)</description>
23407 <bitOffset>30</bitOffset>
23408 <bitWidth>1</bitWidth>
23409 </field>
23410 <field>
23411 <name>BR13</name>
23412 <description>Port x reset bit y (y =
23413 0..15)</description>
23414 <bitOffset>29</bitOffset>
23415 <bitWidth>1</bitWidth>
23416 </field>
23417 <field>
23418 <name>BR12</name>
23419 <description>Port x reset bit y (y =
23420 0..15)</description>
23421 <bitOffset>28</bitOffset>
23422 <bitWidth>1</bitWidth>
23423 </field>
23424 <field>
23425 <name>BR11</name>
23426 <description>Port x reset bit y (y =
23427 0..15)</description>
23428 <bitOffset>27</bitOffset>
23429 <bitWidth>1</bitWidth>
23430 </field>
23431 <field>
23432 <name>BR10</name>
23433 <description>Port x reset bit y (y =
23434 0..15)</description>
23435 <bitOffset>26</bitOffset>
23436 <bitWidth>1</bitWidth>
23437 </field>
23438 <field>
23439 <name>BR9</name>
23440 <description>Port x reset bit y (y =
23441 0..15)</description>
23442 <bitOffset>25</bitOffset>
23443 <bitWidth>1</bitWidth>
23444 </field>
23445 <field>
23446 <name>BR8</name>
23447 <description>Port x reset bit y (y =
23448 0..15)</description>
23449 <bitOffset>24</bitOffset>
23450 <bitWidth>1</bitWidth>
23451 </field>
23452 <field>
23453 <name>BR7</name>
23454 <description>Port x reset bit y (y =
23455 0..15)</description>
23456 <bitOffset>23</bitOffset>
23457 <bitWidth>1</bitWidth>
23458 </field>
23459 <field>
23460 <name>BR6</name>
23461 <description>Port x reset bit y (y =
23462 0..15)</description>
23463 <bitOffset>22</bitOffset>
23464 <bitWidth>1</bitWidth>
23465 </field>
23466 <field>
23467 <name>BR5</name>
23468 <description>Port x reset bit y (y =
23469 0..15)</description>
23470 <bitOffset>21</bitOffset>
23471 <bitWidth>1</bitWidth>
23472 </field>
23473 <field>
23474 <name>BR4</name>
23475 <description>Port x reset bit y (y =
23476 0..15)</description>
23477 <bitOffset>20</bitOffset>
23478 <bitWidth>1</bitWidth>
23479 </field>
23480 <field>
23481 <name>BR3</name>
23482 <description>Port x reset bit y (y =
23483 0..15)</description>
23484 <bitOffset>19</bitOffset>
23485 <bitWidth>1</bitWidth>
23486 </field>
23487 <field>
23488 <name>BR2</name>
23489 <description>Port x reset bit y (y =
23490 0..15)</description>
23491 <bitOffset>18</bitOffset>
23492 <bitWidth>1</bitWidth>
23493 </field>
23494 <field>
23495 <name>BR1</name>
23496 <description>Port x reset bit y (y =
23497 0..15)</description>
23498 <bitOffset>17</bitOffset>
23499 <bitWidth>1</bitWidth>
23500 </field>
23501 <field>
23502 <name>BR0</name>
23503 <description>Port x set bit y (y=
23504 0..15)</description>
23505 <bitOffset>16</bitOffset>
23506 <bitWidth>1</bitWidth>
23507 </field>
23508 <field>
23509 <name>BS15</name>
23510 <description>Port x set bit y (y=
23511 0..15)</description>
23512 <bitOffset>15</bitOffset>
23513 <bitWidth>1</bitWidth>
23514 </field>
23515 <field>
23516 <name>BS14</name>
23517 <description>Port x set bit y (y=
23518 0..15)</description>
23519 <bitOffset>14</bitOffset>
23520 <bitWidth>1</bitWidth>
23521 </field>
23522 <field>
23523 <name>BS13</name>
23524 <description>Port x set bit y (y=
23525 0..15)</description>
23526 <bitOffset>13</bitOffset>
23527 <bitWidth>1</bitWidth>
23528 </field>
23529 <field>
23530 <name>BS12</name>
23531 <description>Port x set bit y (y=
23532 0..15)</description>
23533 <bitOffset>12</bitOffset>
23534 <bitWidth>1</bitWidth>
23535 </field>
23536 <field>
23537 <name>BS11</name>
23538 <description>Port x set bit y (y=
23539 0..15)</description>
23540 <bitOffset>11</bitOffset>
23541 <bitWidth>1</bitWidth>
23542 </field>
23543 <field>
23544 <name>BS10</name>
23545 <description>Port x set bit y (y=
23546 0..15)</description>
23547 <bitOffset>10</bitOffset>
23548 <bitWidth>1</bitWidth>
23549 </field>
23550 <field>
23551 <name>BS9</name>
23552 <description>Port x set bit y (y=
23553 0..15)</description>
23554 <bitOffset>9</bitOffset>
23555 <bitWidth>1</bitWidth>
23556 </field>
23557 <field>
23558 <name>BS8</name>
23559 <description>Port x set bit y (y=
23560 0..15)</description>
23561 <bitOffset>8</bitOffset>
23562 <bitWidth>1</bitWidth>
23563 </field>
23564 <field>
23565 <name>BS7</name>
23566 <description>Port x set bit y (y=
23567 0..15)</description>
23568 <bitOffset>7</bitOffset>
23569 <bitWidth>1</bitWidth>
23570 </field>
23571 <field>
23572 <name>BS6</name>
23573 <description>Port x set bit y (y=
23574 0..15)</description>
23575 <bitOffset>6</bitOffset>
23576 <bitWidth>1</bitWidth>
23577 </field>
23578 <field>
23579 <name>BS5</name>
23580 <description>Port x set bit y (y=
23581 0..15)</description>
23582 <bitOffset>5</bitOffset>
23583 <bitWidth>1</bitWidth>
23584 </field>
23585 <field>
23586 <name>BS4</name>
23587 <description>Port x set bit y (y=
23588 0..15)</description>
23589 <bitOffset>4</bitOffset>
23590 <bitWidth>1</bitWidth>
23591 </field>
23592 <field>
23593 <name>BS3</name>
23594 <description>Port x set bit y (y=
23595 0..15)</description>
23596 <bitOffset>3</bitOffset>
23597 <bitWidth>1</bitWidth>
23598 </field>
23599 <field>
23600 <name>BS2</name>
23601 <description>Port x set bit y (y=
23602 0..15)</description>
23603 <bitOffset>2</bitOffset>
23604 <bitWidth>1</bitWidth>
23605 </field>
23606 <field>
23607 <name>BS1</name>
23608 <description>Port x set bit y (y=
23609 0..15)</description>
23610 <bitOffset>1</bitOffset>
23611 <bitWidth>1</bitWidth>
23612 </field>
23613 <field>
23614 <name>BS0</name>
23615 <description>Port x set bit y (y=
23616 0..15)</description>
23617 <bitOffset>0</bitOffset>
23618 <bitWidth>1</bitWidth>
23619 </field>
23620 </fields>
23621 </register>
23622 <register>
23623 <name>LCKR</name>
23624 <displayName>LCKR</displayName>
23625 <description>GPIO port configuration lock
23626 register</description>
23627 <addressOffset>0x1C</addressOffset>
23628 <size>0x20</size>
23629 <access>read-write</access>
23630 <resetValue>0x00000000</resetValue>
23631 <fields>
23632 <field>
23633 <name>LCKK</name>
23634 <description>Port x lock bit y (y=
23635 0..15)</description>
23636 <bitOffset>16</bitOffset>
23637 <bitWidth>1</bitWidth>
23638 </field>
23639 <field>
23640 <name>LCK15</name>
23641 <description>Port x lock bit y (y=
23642 0..15)</description>
23643 <bitOffset>15</bitOffset>
23644 <bitWidth>1</bitWidth>
23645 </field>
23646 <field>
23647 <name>LCK14</name>
23648 <description>Port x lock bit y (y=
23649 0..15)</description>
23650 <bitOffset>14</bitOffset>
23651 <bitWidth>1</bitWidth>
23652 </field>
23653 <field>
23654 <name>LCK13</name>
23655 <description>Port x lock bit y (y=
23656 0..15)</description>
23657 <bitOffset>13</bitOffset>
23658 <bitWidth>1</bitWidth>
23659 </field>
23660 <field>
23661 <name>LCK12</name>
23662 <description>Port x lock bit y (y=
23663 0..15)</description>
23664 <bitOffset>12</bitOffset>
23665 <bitWidth>1</bitWidth>
23666 </field>
23667 <field>
23668 <name>LCK11</name>
23669 <description>Port x lock bit y (y=
23670 0..15)</description>
23671 <bitOffset>11</bitOffset>
23672 <bitWidth>1</bitWidth>
23673 </field>
23674 <field>
23675 <name>LCK10</name>
23676 <description>Port x lock bit y (y=
23677 0..15)</description>
23678 <bitOffset>10</bitOffset>
23679 <bitWidth>1</bitWidth>
23680 </field>
23681 <field>
23682 <name>LCK9</name>
23683 <description>Port x lock bit y (y=
23684 0..15)</description>
23685 <bitOffset>9</bitOffset>
23686 <bitWidth>1</bitWidth>
23687 </field>
23688 <field>
23689 <name>LCK8</name>
23690 <description>Port x lock bit y (y=
23691 0..15)</description>
23692 <bitOffset>8</bitOffset>
23693 <bitWidth>1</bitWidth>
23694 </field>
23695 <field>
23696 <name>LCK7</name>
23697 <description>Port x lock bit y (y=
23698 0..15)</description>
23699 <bitOffset>7</bitOffset>
23700 <bitWidth>1</bitWidth>
23701 </field>
23702 <field>
23703 <name>LCK6</name>
23704 <description>Port x lock bit y (y=
23705 0..15)</description>
23706 <bitOffset>6</bitOffset>
23707 <bitWidth>1</bitWidth>
23708 </field>
23709 <field>
23710 <name>LCK5</name>
23711 <description>Port x lock bit y (y=
23712 0..15)</description>
23713 <bitOffset>5</bitOffset>
23714 <bitWidth>1</bitWidth>
23715 </field>
23716 <field>
23717 <name>LCK4</name>
23718 <description>Port x lock bit y (y=
23719 0..15)</description>
23720 <bitOffset>4</bitOffset>
23721 <bitWidth>1</bitWidth>
23722 </field>
23723 <field>
23724 <name>LCK3</name>
23725 <description>Port x lock bit y (y=
23726 0..15)</description>
23727 <bitOffset>3</bitOffset>
23728 <bitWidth>1</bitWidth>
23729 </field>
23730 <field>
23731 <name>LCK2</name>
23732 <description>Port x lock bit y (y=
23733 0..15)</description>
23734 <bitOffset>2</bitOffset>
23735 <bitWidth>1</bitWidth>
23736 </field>
23737 <field>
23738 <name>LCK1</name>
23739 <description>Port x lock bit y (y=
23740 0..15)</description>
23741 <bitOffset>1</bitOffset>
23742 <bitWidth>1</bitWidth>
23743 </field>
23744 <field>
23745 <name>LCK0</name>
23746 <description>Port x lock bit y (y=
23747 0..15)</description>
23748 <bitOffset>0</bitOffset>
23749 <bitWidth>1</bitWidth>
23750 </field>
23751 </fields>
23752 </register>
23753 <register>
23754 <name>AFRL</name>
23755 <displayName>AFRL</displayName>
23756 <description>GPIO alternate function low
23757 register</description>
23758 <addressOffset>0x20</addressOffset>
23759 <size>0x20</size>
23760 <access>read-write</access>
23761 <resetValue>0x00000000</resetValue>
23762 <fields>
23763 <field>
23764 <name>AFRL7</name>
23765 <description>Alternate function selection for port x
23766 bit y (y = 0..7)</description>
23767 <bitOffset>28</bitOffset>
23768 <bitWidth>4</bitWidth>
23769 </field>
23770 <field>
23771 <name>AFRL6</name>
23772 <description>Alternate function selection for port x
23773 bit y (y = 0..7)</description>
23774 <bitOffset>24</bitOffset>
23775 <bitWidth>4</bitWidth>
23776 </field>
23777 <field>
23778 <name>AFRL5</name>
23779 <description>Alternate function selection for port x
23780 bit y (y = 0..7)</description>
23781 <bitOffset>20</bitOffset>
23782 <bitWidth>4</bitWidth>
23783 </field>
23784 <field>
23785 <name>AFRL4</name>
23786 <description>Alternate function selection for port x
23787 bit y (y = 0..7)</description>
23788 <bitOffset>16</bitOffset>
23789 <bitWidth>4</bitWidth>
23790 </field>
23791 <field>
23792 <name>AFRL3</name>
23793 <description>Alternate function selection for port x
23794 bit y (y = 0..7)</description>
23795 <bitOffset>12</bitOffset>
23796 <bitWidth>4</bitWidth>
23797 </field>
23798 <field>
23799 <name>AFRL2</name>
23800 <description>Alternate function selection for port x
23801 bit y (y = 0..7)</description>
23802 <bitOffset>8</bitOffset>
23803 <bitWidth>4</bitWidth>
23804 </field>
23805 <field>
23806 <name>AFRL1</name>
23807 <description>Alternate function selection for port x
23808 bit y (y = 0..7)</description>
23809 <bitOffset>4</bitOffset>
23810 <bitWidth>4</bitWidth>
23811 </field>
23812 <field>
23813 <name>AFRL0</name>
23814 <description>Alternate function selection for port x
23815 bit y (y = 0..7)</description>
23816 <bitOffset>0</bitOffset>
23817 <bitWidth>4</bitWidth>
23818 </field>
23819 </fields>
23820 </register>
23821 <register>
23822 <name>AFRH</name>
23823 <displayName>AFRH</displayName>
23824 <description>GPIO alternate function high
23825 register</description>
23826 <addressOffset>0x24</addressOffset>
23827 <size>0x20</size>
23828 <access>read-write</access>
23829 <resetValue>0x00000000</resetValue>
23830 <fields>
23831 <field>
23832 <name>AFRH15</name>
23833 <description>Alternate function selection for port x
23834 bit y (y = 8..15)</description>
23835 <bitOffset>28</bitOffset>
23836 <bitWidth>4</bitWidth>
23837 </field>
23838 <field>
23839 <name>AFRH14</name>
23840 <description>Alternate function selection for port x
23841 bit y (y = 8..15)</description>
23842 <bitOffset>24</bitOffset>
23843 <bitWidth>4</bitWidth>
23844 </field>
23845 <field>
23846 <name>AFRH13</name>
23847 <description>Alternate function selection for port x
23848 bit y (y = 8..15)</description>
23849 <bitOffset>20</bitOffset>
23850 <bitWidth>4</bitWidth>
23851 </field>
23852 <field>
23853 <name>AFRH12</name>
23854 <description>Alternate function selection for port x
23855 bit y (y = 8..15)</description>
23856 <bitOffset>16</bitOffset>
23857 <bitWidth>4</bitWidth>
23858 </field>
23859 <field>
23860 <name>AFRH11</name>
23861 <description>Alternate function selection for port x
23862 bit y (y = 8..15)</description>
23863 <bitOffset>12</bitOffset>
23864 <bitWidth>4</bitWidth>
23865 </field>
23866 <field>
23867 <name>AFRH10</name>
23868 <description>Alternate function selection for port x
23869 bit y (y = 8..15)</description>
23870 <bitOffset>8</bitOffset>
23871 <bitWidth>4</bitWidth>
23872 </field>
23873 <field>
23874 <name>AFRH9</name>
23875 <description>Alternate function selection for port x
23876 bit y (y = 8..15)</description>
23877 <bitOffset>4</bitOffset>
23878 <bitWidth>4</bitWidth>
23879 </field>
23880 <field>
23881 <name>AFRH8</name>
23882 <description>Alternate function selection for port x
23883 bit y (y = 8..15)</description>
23884 <bitOffset>0</bitOffset>
23885 <bitWidth>4</bitWidth>
23886 </field>
23887 </fields>
23888 </register>
23889 </registers>
23890 </peripheral>
23891 <peripheral>
23892 <name>I2C3</name>
23893 <description>Inter-integrated circuit</description>
23894 <groupName>I2C</groupName>
23895 <baseAddress>0x40005C00</baseAddress>
23896 <addressBlock>
23897 <offset>0x0</offset>
23898 <size>0x400</size>
23899 <usage>registers</usage>
23900 </addressBlock>
23901 <interrupt>
23902 <name>TIM3</name>
23903 <description>TIM3 global interrupt</description>
23904 <value>29</value>
23905 </interrupt>
23906 <registers>
23907 <register>
23908 <name>CR1</name>
23909 <displayName>CR1</displayName>
23910 <description>Control register 1</description>
23911 <addressOffset>0x0</addressOffset>
23912 <size>0x20</size>
23913 <access>read-write</access>
23914 <resetValue>0x0000</resetValue>
23915 <fields>
23916 <field>
23917 <name>SWRST</name>
23918 <description>Software reset</description>
23919 <bitOffset>15</bitOffset>
23920 <bitWidth>1</bitWidth>
23921 </field>
23922 <field>
23923 <name>ALERT</name>
23924 <description>SMBus alert</description>
23925 <bitOffset>13</bitOffset>
23926 <bitWidth>1</bitWidth>
23927 </field>
23928 <field>
23929 <name>PEC</name>
23930 <description>Packet error checking</description>
23931 <bitOffset>12</bitOffset>
23932 <bitWidth>1</bitWidth>
23933 </field>
23934 <field>
23935 <name>POS</name>
23936 <description>Acknowledge/PEC Position (for data
23937 reception)</description>
23938 <bitOffset>11</bitOffset>
23939 <bitWidth>1</bitWidth>
23940 </field>
23941 <field>
23942 <name>ACK</name>
23943 <description>Acknowledge enable</description>
23944 <bitOffset>10</bitOffset>
23945 <bitWidth>1</bitWidth>
23946 </field>
23947 <field>
23948 <name>STOP</name>
23949 <description>Stop generation</description>
23950 <bitOffset>9</bitOffset>
23951 <bitWidth>1</bitWidth>
23952 </field>
23953 <field>
23954 <name>START</name>
23955 <description>Start generation</description>
23956 <bitOffset>8</bitOffset>
23957 <bitWidth>1</bitWidth>
23958 </field>
23959 <field>
23960 <name>NOSTRETCH</name>
23961 <description>Clock stretching disable (Slave
23962 mode)</description>
23963 <bitOffset>7</bitOffset>
23964 <bitWidth>1</bitWidth>
23965 </field>
23966 <field>
23967 <name>ENGC</name>
23968 <description>General call enable</description>
23969 <bitOffset>6</bitOffset>
23970 <bitWidth>1</bitWidth>
23971 </field>
23972 <field>
23973 <name>ENPEC</name>
23974 <description>PEC enable</description>
23975 <bitOffset>5</bitOffset>
23976 <bitWidth>1</bitWidth>
23977 </field>
23978 <field>
23979 <name>ENARP</name>
23980 <description>ARP enable</description>
23981 <bitOffset>4</bitOffset>
23982 <bitWidth>1</bitWidth>
23983 </field>
23984 <field>
23985 <name>SMBTYPE</name>
23986 <description>SMBus type</description>
23987 <bitOffset>3</bitOffset>
23988 <bitWidth>1</bitWidth>
23989 </field>
23990 <field>
23991 <name>SMBUS</name>
23992 <description>SMBus mode</description>
23993 <bitOffset>1</bitOffset>
23994 <bitWidth>1</bitWidth>
23995 </field>
23996 <field>
23997 <name>PE</name>
23998 <description>Peripheral enable</description>
23999 <bitOffset>0</bitOffset>
24000 <bitWidth>1</bitWidth>
24001 </field>
24002 </fields>
24003 </register>
24004 <register>
24005 <name>CR2</name>
24006 <displayName>CR2</displayName>
24007 <description>Control register 2</description>
24008 <addressOffset>0x4</addressOffset>
24009 <size>0x20</size>
24010 <access>read-write</access>
24011 <resetValue>0x0000</resetValue>
24012 <fields>
24013 <field>
24014 <name>LAST</name>
24015 <description>DMA last transfer</description>
24016 <bitOffset>12</bitOffset>
24017 <bitWidth>1</bitWidth>
24018 </field>
24019 <field>
24020 <name>DMAEN</name>
24021 <description>DMA requests enable</description>
24022 <bitOffset>11</bitOffset>
24023 <bitWidth>1</bitWidth>
24024 </field>
24025 <field>
24026 <name>ITBUFEN</name>
24027 <description>Buffer interrupt enable</description>
24028 <bitOffset>10</bitOffset>
24029 <bitWidth>1</bitWidth>
24030 </field>
24031 <field>
24032 <name>ITEVTEN</name>
24033 <description>Event interrupt enable</description>
24034 <bitOffset>9</bitOffset>
24035 <bitWidth>1</bitWidth>
24036 </field>
24037 <field>
24038 <name>ITERREN</name>
24039 <description>Error interrupt enable</description>
24040 <bitOffset>8</bitOffset>
24041 <bitWidth>1</bitWidth>
24042 </field>
24043 <field>
24044 <name>FREQ</name>
24045 <description>Peripheral clock frequency</description>
24046 <bitOffset>0</bitOffset>
24047 <bitWidth>6</bitWidth>
24048 </field>
24049 </fields>
24050 </register>
24051 <register>
24052 <name>OAR1</name>
24053 <displayName>OAR1</displayName>
24054 <description>Own address register 1</description>
24055 <addressOffset>0x8</addressOffset>
24056 <size>0x20</size>
24057 <access>read-write</access>
24058 <resetValue>0x0000</resetValue>
24059 <fields>
24060 <field>
24061 <name>ADDMODE</name>
24062 <description>Addressing mode (slave
24063 mode)</description>
24064 <bitOffset>15</bitOffset>
24065 <bitWidth>1</bitWidth>
24066 </field>
24067 <field>
24068 <name>ADD10</name>
24069 <description>Interface address</description>
24070 <bitOffset>8</bitOffset>
24071 <bitWidth>2</bitWidth>
24072 </field>
24073 <field>
24074 <name>ADD7</name>
24075 <description>Interface address</description>
24076 <bitOffset>1</bitOffset>
24077 <bitWidth>7</bitWidth>
24078 </field>
24079 <field>
24080 <name>ADD0</name>
24081 <description>Interface address</description>
24082 <bitOffset>0</bitOffset>
24083 <bitWidth>1</bitWidth>
24084 </field>
24085 </fields>
24086 </register>
24087 <register>
24088 <name>OAR2</name>
24089 <displayName>OAR2</displayName>
24090 <description>Own address register 2</description>
24091 <addressOffset>0xC</addressOffset>
24092 <size>0x20</size>
24093 <access>read-write</access>
24094 <resetValue>0x0000</resetValue>
24095 <fields>
24096 <field>
24097 <name>ADD2</name>
24098 <description>Interface address</description>
24099 <bitOffset>1</bitOffset>
24100 <bitWidth>7</bitWidth>
24101 </field>
24102 <field>
24103 <name>ENDUAL</name>
24104 <description>Dual addressing mode
24105 enable</description>
24106 <bitOffset>0</bitOffset>
24107 <bitWidth>1</bitWidth>
24108 </field>
24109 </fields>
24110 </register>
24111 <register>
24112 <name>DR</name>
24113 <displayName>DR</displayName>
24114 <description>Data register</description>
24115 <addressOffset>0x10</addressOffset>
24116 <size>0x20</size>
24117 <access>read-write</access>
24118 <resetValue>0x0000</resetValue>
24119 <fields>
24120 <field>
24121 <name>DR</name>
24122 <description>8-bit data register</description>
24123 <bitOffset>0</bitOffset>
24124 <bitWidth>8</bitWidth>
24125 </field>
24126 </fields>
24127 </register>
24128 <register>
24129 <name>SR1</name>
24130 <displayName>SR1</displayName>
24131 <description>Status register 1</description>
24132 <addressOffset>0x14</addressOffset>
24133 <size>0x20</size>
24134 <resetValue>0x0000</resetValue>
24135 <fields>
24136 <field>
24137 <name>SMBALERT</name>
24138 <description>SMBus alert</description>
24139 <bitOffset>15</bitOffset>
24140 <bitWidth>1</bitWidth>
24141 <access>read-write</access>
24142 </field>
24143 <field>
24144 <name>TIMEOUT</name>
24145 <description>Timeout or Tlow error</description>
24146 <bitOffset>14</bitOffset>
24147 <bitWidth>1</bitWidth>
24148 <access>read-write</access>
24149 </field>
24150 <field>
24151 <name>PECERR</name>
24152 <description>PEC Error in reception</description>
24153 <bitOffset>12</bitOffset>
24154 <bitWidth>1</bitWidth>
24155 <access>read-write</access>
24156 </field>
24157 <field>
24158 <name>OVR</name>
24159 <description>Overrun/Underrun</description>
24160 <bitOffset>11</bitOffset>
24161 <bitWidth>1</bitWidth>
24162 <access>read-write</access>
24163 </field>
24164 <field>
24165 <name>AF</name>
24166 <description>Acknowledge failure</description>
24167 <bitOffset>10</bitOffset>
24168 <bitWidth>1</bitWidth>
24169 <access>read-write</access>
24170 </field>
24171 <field>
24172 <name>ARLO</name>
24173 <description>Arbitration lost (master
24174 mode)</description>
24175 <bitOffset>9</bitOffset>
24176 <bitWidth>1</bitWidth>
24177 <access>read-write</access>
24178 </field>
24179 <field>
24180 <name>BERR</name>
24181 <description>Bus error</description>
24182 <bitOffset>8</bitOffset>
24183 <bitWidth>1</bitWidth>
24184 <access>read-write</access>
24185 </field>
24186 <field>
24187 <name>TxE</name>
24188 <description>Data register empty
24189 (transmitters)</description>
24190 <bitOffset>7</bitOffset>
24191 <bitWidth>1</bitWidth>
24192 <access>read-only</access>
24193 </field>
24194 <field>
24195 <name>RxNE</name>
24196 <description>Data register not empty
24197 (receivers)</description>
24198 <bitOffset>6</bitOffset>
24199 <bitWidth>1</bitWidth>
24200 <access>read-only</access>
24201 </field>
24202 <field>
24203 <name>STOPF</name>
24204 <description>Stop detection (slave
24205 mode)</description>
24206 <bitOffset>4</bitOffset>
24207 <bitWidth>1</bitWidth>
24208 <access>read-only</access>
24209 </field>
24210 <field>
24211 <name>ADD10</name>
24212 <description>10-bit header sent (Master
24213 mode)</description>
24214 <bitOffset>3</bitOffset>
24215 <bitWidth>1</bitWidth>
24216 <access>read-only</access>
24217 </field>
24218 <field>
24219 <name>BTF</name>
24220 <description>Byte transfer finished</description>
24221 <bitOffset>2</bitOffset>
24222 <bitWidth>1</bitWidth>
24223 <access>read-only</access>
24224 </field>
24225 <field>
24226 <name>ADDR</name>
24227 <description>Address sent (master mode)/matched
24228 (slave mode)</description>
24229 <bitOffset>1</bitOffset>
24230 <bitWidth>1</bitWidth>
24231 <access>read-only</access>
24232 </field>
24233 <field>
24234 <name>SB</name>
24235 <description>Start bit (Master mode)</description>
24236 <bitOffset>0</bitOffset>
24237 <bitWidth>1</bitWidth>
24238 <access>read-only</access>
24239 </field>
24240 </fields>
24241 </register>
24242 <register>
24243 <name>SR2</name>
24244 <displayName>SR2</displayName>
24245 <description>Status register 2</description>
24246 <addressOffset>0x18</addressOffset>
24247 <size>0x20</size>
24248 <access>read-only</access>
24249 <resetValue>0x0000</resetValue>
24250 <fields>
24251 <field>
24252 <name>PEC</name>
24253 <description>acket error checking
24254 register</description>
24255 <bitOffset>8</bitOffset>
24256 <bitWidth>8</bitWidth>
24257 </field>
24258 <field>
24259 <name>DUALF</name>
24260 <description>Dual flag (Slave mode)</description>
24261 <bitOffset>7</bitOffset>
24262 <bitWidth>1</bitWidth>
24263 </field>
24264 <field>
24265 <name>SMBHOST</name>
24266 <description>SMBus host header (Slave
24267 mode)</description>
24268 <bitOffset>6</bitOffset>
24269 <bitWidth>1</bitWidth>
24270 </field>
24271 <field>
24272 <name>SMBDEFAULT</name>
24273 <description>SMBus device default address (Slave
24274 mode)</description>
24275 <bitOffset>5</bitOffset>
24276 <bitWidth>1</bitWidth>
24277 </field>
24278 <field>
24279 <name>GENCALL</name>
24280 <description>General call address (Slave
24281 mode)</description>
24282 <bitOffset>4</bitOffset>
24283 <bitWidth>1</bitWidth>
24284 </field>
24285 <field>
24286 <name>TRA</name>
24287 <description>Transmitter/receiver</description>
24288 <bitOffset>2</bitOffset>
24289 <bitWidth>1</bitWidth>
24290 </field>
24291 <field>
24292 <name>BUSY</name>
24293 <description>Bus busy</description>
24294 <bitOffset>1</bitOffset>
24295 <bitWidth>1</bitWidth>
24296 </field>
24297 <field>
24298 <name>MSL</name>
24299 <description>Master/slave</description>
24300 <bitOffset>0</bitOffset>
24301 <bitWidth>1</bitWidth>
24302 </field>
24303 </fields>
24304 </register>
24305 <register>
24306 <name>CCR</name>
24307 <displayName>CCR</displayName>
24308 <description>Clock control register</description>
24309 <addressOffset>0x1C</addressOffset>
24310 <size>0x20</size>
24311 <access>read-write</access>
24312 <resetValue>0x0000</resetValue>
24313 <fields>
24314 <field>
24315 <name>F_S</name>
24316 <description>I2C master mode selection</description>
24317 <bitOffset>15</bitOffset>
24318 <bitWidth>1</bitWidth>
24319 </field>
24320 <field>
24321 <name>DUTY</name>
24322 <description>Fast mode duty cycle</description>
24323 <bitOffset>14</bitOffset>
24324 <bitWidth>1</bitWidth>
24325 </field>
24326 <field>
24327 <name>CCR</name>
24328 <description>Clock control register in Fast/Standard
24329 mode (Master mode)</description>
24330 <bitOffset>0</bitOffset>
24331 <bitWidth>12</bitWidth>
24332 </field>
24333 </fields>
24334 </register>
24335 <register>
24336 <name>TRISE</name>
24337 <displayName>TRISE</displayName>
24338 <description>TRISE register</description>
24339 <addressOffset>0x20</addressOffset>
24340 <size>0x20</size>
24341 <access>read-write</access>
24342 <resetValue>0x0002</resetValue>
24343 <fields>
24344 <field>
24345 <name>TRISE</name>
24346 <description>Maximum rise time in Fast/Standard mode
24347 (Master mode)</description>
24348 <bitOffset>0</bitOffset>
24349 <bitWidth>6</bitWidth>
24350 </field>
24351 </fields>
24352 </register>
24353 </registers>
24354 </peripheral>
24355 <peripheral derivedFrom="I2C3">
24356 <name>I2C2</name>
24357 <baseAddress>0x40005800</baseAddress>
24358 <interrupt>
24359 <name>I2C3_EV</name>
24360 <description>I2C3 event interrupt</description>
24361 <value>72</value>
24362 </interrupt>
24363 <interrupt>
24364 <name>I2C3_ER</name>
24365 <description>I2C3 error interrupt</description>
24366 <value>73</value>
24367 </interrupt>
24368 </peripheral>
24369 <peripheral derivedFrom="I2C3">
24370 <name>I2C1</name>
24371 <baseAddress>0x40005400</baseAddress>
24372 <interrupt>
24373 <name>I2C2_EV</name>
24374 <description>I2C2 event interrupt</description>
24375 <value>33</value>
24376 </interrupt>
24377 <interrupt>
24378 <name>I2C2_ER</name>
24379 <description>I2C2 error interrupt</description>
24380 <value>34</value>
24381 </interrupt>
24382 </peripheral>
24383 <peripheral>
24384 <name>I2S2ext</name>
24385 <description>Serial peripheral interface</description>
24386 <groupName>SPI</groupName>
24387 <baseAddress>0x40003400</baseAddress>
24388 <addressBlock>
24389 <offset>0x0</offset>
24390 <size>0x400</size>
24391 <usage>registers</usage>
24392 </addressBlock>
24393 <interrupt>
24394 <name>I2C1_EV</name>
24395 <description>I2C1 event interrupt</description>
24396 <value>31</value>
24397 </interrupt>
24398 <interrupt>
24399 <name>I2C1_ER</name>
24400 <description>I2C1 error interrupt</description>
24401 <value>32</value>
24402 </interrupt>
24403 <registers>
24404 <register>
24405 <name>CR1</name>
24406 <displayName>CR1</displayName>
24407 <description>control register 1</description>
24408 <addressOffset>0x0</addressOffset>
24409 <size>0x20</size>
24410 <access>read-write</access>
24411 <resetValue>0x0000</resetValue>
24412 <fields>
24413 <field>
24414 <name>BIDIMODE</name>
24415 <description>Bidirectional data mode
24416 enable</description>
24417 <bitOffset>15</bitOffset>
24418 <bitWidth>1</bitWidth>
24419 </field>
24420 <field>
24421 <name>BIDIOE</name>
24422 <description>Output enable in bidirectional
24423 mode</description>
24424 <bitOffset>14</bitOffset>
24425 <bitWidth>1</bitWidth>
24426 </field>
24427 <field>
24428 <name>CRCEN</name>
24429 <description>Hardware CRC calculation
24430 enable</description>
24431 <bitOffset>13</bitOffset>
24432 <bitWidth>1</bitWidth>
24433 </field>
24434 <field>
24435 <name>CRCNEXT</name>
24436 <description>CRC transfer next</description>
24437 <bitOffset>12</bitOffset>
24438 <bitWidth>1</bitWidth>
24439 </field>
24440 <field>
24441 <name>DFF</name>
24442 <description>Data frame format</description>
24443 <bitOffset>11</bitOffset>
24444 <bitWidth>1</bitWidth>
24445 </field>
24446 <field>
24447 <name>RXONLY</name>
24448 <description>Receive only</description>
24449 <bitOffset>10</bitOffset>
24450 <bitWidth>1</bitWidth>
24451 </field>
24452 <field>
24453 <name>SSM</name>
24454 <description>Software slave management</description>
24455 <bitOffset>9</bitOffset>
24456 <bitWidth>1</bitWidth>
24457 </field>
24458 <field>
24459 <name>SSI</name>
24460 <description>Internal slave select</description>
24461 <bitOffset>8</bitOffset>
24462 <bitWidth>1</bitWidth>
24463 </field>
24464 <field>
24465 <name>LSBFIRST</name>
24466 <description>Frame format</description>
24467 <bitOffset>7</bitOffset>
24468 <bitWidth>1</bitWidth>
24469 </field>
24470 <field>
24471 <name>SPE</name>
24472 <description>SPI enable</description>
24473 <bitOffset>6</bitOffset>
24474 <bitWidth>1</bitWidth>
24475 </field>
24476 <field>
24477 <name>BR</name>
24478 <description>Baud rate control</description>
24479 <bitOffset>3</bitOffset>
24480 <bitWidth>3</bitWidth>
24481 </field>
24482 <field>
24483 <name>MSTR</name>
24484 <description>Master selection</description>
24485 <bitOffset>2</bitOffset>
24486 <bitWidth>1</bitWidth>
24487 </field>
24488 <field>
24489 <name>CPOL</name>
24490 <description>Clock polarity</description>
24491 <bitOffset>1</bitOffset>
24492 <bitWidth>1</bitWidth>
24493 </field>
24494 <field>
24495 <name>CPHA</name>
24496 <description>Clock phase</description>
24497 <bitOffset>0</bitOffset>
24498 <bitWidth>1</bitWidth>
24499 </field>
24500 </fields>
24501 </register>
24502 <register>
24503 <name>CR2</name>
24504 <displayName>CR2</displayName>
24505 <description>control register 2</description>
24506 <addressOffset>0x4</addressOffset>
24507 <size>0x20</size>
24508 <access>read-write</access>
24509 <resetValue>0x0000</resetValue>
24510 <fields>
24511 <field>
24512 <name>TXEIE</name>
24513 <description>Tx buffer empty interrupt
24514 enable</description>
24515 <bitOffset>7</bitOffset>
24516 <bitWidth>1</bitWidth>
24517 </field>
24518 <field>
24519 <name>RXNEIE</name>
24520 <description>RX buffer not empty interrupt
24521 enable</description>
24522 <bitOffset>6</bitOffset>
24523 <bitWidth>1</bitWidth>
24524 </field>
24525 <field>
24526 <name>ERRIE</name>
24527 <description>Error interrupt enable</description>
24528 <bitOffset>5</bitOffset>
24529 <bitWidth>1</bitWidth>
24530 </field>
24531 <field>
24532 <name>FRF</name>
24533 <description>Frame format</description>
24534 <bitOffset>4</bitOffset>
24535 <bitWidth>1</bitWidth>
24536 </field>
24537 <field>
24538 <name>SSOE</name>
24539 <description>SS output enable</description>
24540 <bitOffset>2</bitOffset>
24541 <bitWidth>1</bitWidth>
24542 </field>
24543 <field>
24544 <name>TXDMAEN</name>
24545 <description>Tx buffer DMA enable</description>
24546 <bitOffset>1</bitOffset>
24547 <bitWidth>1</bitWidth>
24548 </field>
24549 <field>
24550 <name>RXDMAEN</name>
24551 <description>Rx buffer DMA enable</description>
24552 <bitOffset>0</bitOffset>
24553 <bitWidth>1</bitWidth>
24554 </field>
24555 </fields>
24556 </register>
24557 <register>
24558 <name>SR</name>
24559 <displayName>SR</displayName>
24560 <description>status register</description>
24561 <addressOffset>0x8</addressOffset>
24562 <size>0x20</size>
24563 <resetValue>0x0002</resetValue>
24564 <fields>
24565 <field>
24566 <name>TIFRFE</name>
24567 <description>TI frame format error</description>
24568 <bitOffset>8</bitOffset>
24569 <bitWidth>1</bitWidth>
24570 <access>read-only</access>
24571 </field>
24572 <field>
24573 <name>BSY</name>
24574 <description>Busy flag</description>
24575 <bitOffset>7</bitOffset>
24576 <bitWidth>1</bitWidth>
24577 <access>read-only</access>
24578 </field>
24579 <field>
24580 <name>OVR</name>
24581 <description>Overrun flag</description>
24582 <bitOffset>6</bitOffset>
24583 <bitWidth>1</bitWidth>
24584 <access>read-only</access>
24585 </field>
24586 <field>
24587 <name>MODF</name>
24588 <description>Mode fault</description>
24589 <bitOffset>5</bitOffset>
24590 <bitWidth>1</bitWidth>
24591 <access>read-only</access>
24592 </field>
24593 <field>
24594 <name>CRCERR</name>
24595 <description>CRC error flag</description>
24596 <bitOffset>4</bitOffset>
24597 <bitWidth>1</bitWidth>
24598 <access>read-write</access>
24599 </field>
24600 <field>
24601 <name>UDR</name>
24602 <description>Underrun flag</description>
24603 <bitOffset>3</bitOffset>
24604 <bitWidth>1</bitWidth>
24605 <access>read-only</access>
24606 </field>
24607 <field>
24608 <name>CHSIDE</name>
24609 <description>Channel side</description>
24610 <bitOffset>2</bitOffset>
24611 <bitWidth>1</bitWidth>
24612 <access>read-only</access>
24613 </field>
24614 <field>
24615 <name>TXE</name>
24616 <description>Transmit buffer empty</description>
24617 <bitOffset>1</bitOffset>
24618 <bitWidth>1</bitWidth>
24619 <access>read-only</access>
24620 </field>
24621 <field>
24622 <name>RXNE</name>
24623 <description>Receive buffer not empty</description>
24624 <bitOffset>0</bitOffset>
24625 <bitWidth>1</bitWidth>
24626 <access>read-only</access>
24627 </field>
24628 </fields>
24629 </register>
24630 <register>
24631 <name>DR</name>
24632 <displayName>DR</displayName>
24633 <description>data register</description>
24634 <addressOffset>0xC</addressOffset>
24635 <size>0x20</size>
24636 <access>read-write</access>
24637 <resetValue>0x0000</resetValue>
24638 <fields>
24639 <field>
24640 <name>DR</name>
24641 <description>Data register</description>
24642 <bitOffset>0</bitOffset>
24643 <bitWidth>16</bitWidth>
24644 </field>
24645 </fields>
24646 </register>
24647 <register>
24648 <name>CRCPR</name>
24649 <displayName>CRCPR</displayName>
24650 <description>CRC polynomial register</description>
24651 <addressOffset>0x10</addressOffset>
24652 <size>0x20</size>
24653 <access>read-write</access>
24654 <resetValue>0x0007</resetValue>
24655 <fields>
24656 <field>
24657 <name>CRCPOLY</name>
24658 <description>CRC polynomial register</description>
24659 <bitOffset>0</bitOffset>
24660 <bitWidth>16</bitWidth>
24661 </field>
24662 </fields>
24663 </register>
24664 <register>
24665 <name>RXCRCR</name>
24666 <displayName>RXCRCR</displayName>
24667 <description>RX CRC register</description>
24668 <addressOffset>0x14</addressOffset>
24669 <size>0x20</size>
24670 <access>read-only</access>
24671 <resetValue>0x0000</resetValue>
24672 <fields>
24673 <field>
24674 <name>RxCRC</name>
24675 <description>Rx CRC register</description>
24676 <bitOffset>0</bitOffset>
24677 <bitWidth>16</bitWidth>
24678 </field>
24679 </fields>
24680 </register>
24681 <register>
24682 <name>TXCRCR</name>
24683 <displayName>TXCRCR</displayName>
24684 <description>TX CRC register</description>
24685 <addressOffset>0x18</addressOffset>
24686 <size>0x20</size>
24687 <access>read-only</access>
24688 <resetValue>0x0000</resetValue>
24689 <fields>
24690 <field>
24691 <name>TxCRC</name>
24692 <description>Tx CRC register</description>
24693 <bitOffset>0</bitOffset>
24694 <bitWidth>16</bitWidth>
24695 </field>
24696 </fields>
24697 </register>
24698 <register>
24699 <name>I2SCFGR</name>
24700 <displayName>I2SCFGR</displayName>
24701 <description>I2S configuration register</description>
24702 <addressOffset>0x1C</addressOffset>
24703 <size>0x20</size>
24704 <access>read-write</access>
24705 <resetValue>0x0000</resetValue>
24706 <fields>
24707 <field>
24708 <name>I2SMOD</name>
24709 <description>I2S mode selection</description>
24710 <bitOffset>11</bitOffset>
24711 <bitWidth>1</bitWidth>
24712 </field>
24713 <field>
24714 <name>I2SE</name>
24715 <description>I2S Enable</description>
24716 <bitOffset>10</bitOffset>
24717 <bitWidth>1</bitWidth>
24718 </field>
24719 <field>
24720 <name>I2SCFG</name>
24721 <description>I2S configuration mode</description>
24722 <bitOffset>8</bitOffset>
24723 <bitWidth>2</bitWidth>
24724 </field>
24725 <field>
24726 <name>PCMSYNC</name>
24727 <description>PCM frame synchronization</description>
24728 <bitOffset>7</bitOffset>
24729 <bitWidth>1</bitWidth>
24730 </field>
24731 <field>
24732 <name>I2SSTD</name>
24733 <description>I2S standard selection</description>
24734 <bitOffset>4</bitOffset>
24735 <bitWidth>2</bitWidth>
24736 </field>
24737 <field>
24738 <name>CKPOL</name>
24739 <description>Steady state clock
24740 polarity</description>
24741 <bitOffset>3</bitOffset>
24742 <bitWidth>1</bitWidth>
24743 </field>
24744 <field>
24745 <name>DATLEN</name>
24746 <description>Data length to be
24747 transferred</description>
24748 <bitOffset>1</bitOffset>
24749 <bitWidth>2</bitWidth>
24750 </field>
24751 <field>
24752 <name>CHLEN</name>
24753 <description>Channel length (number of bits per audio
24754 channel)</description>
24755 <bitOffset>0</bitOffset>
24756 <bitWidth>1</bitWidth>
24757 </field>
24758 </fields>
24759 </register>
24760 <register>
24761 <name>I2SPR</name>
24762 <displayName>I2SPR</displayName>
24763 <description>I2S prescaler register</description>
24764 <addressOffset>0x20</addressOffset>
24765 <size>0x20</size>
24766 <access>read-write</access>
24767 <resetValue>00000010</resetValue>
24768 <fields>
24769 <field>
24770 <name>MCKOE</name>
24771 <description>Master clock output enable</description>
24772 <bitOffset>9</bitOffset>
24773 <bitWidth>1</bitWidth>
24774 </field>
24775 <field>
24776 <name>ODD</name>
24777 <description>Odd factor for the
24778 prescaler</description>
24779 <bitOffset>8</bitOffset>
24780 <bitWidth>1</bitWidth>
24781 </field>
24782 <field>
24783 <name>I2SDIV</name>
24784 <description>I2S Linear prescaler</description>
24785 <bitOffset>0</bitOffset>
24786 <bitWidth>8</bitWidth>
24787 </field>
24788 </fields>
24789 </register>
24790 </registers>
24791 </peripheral>
24792 <peripheral derivedFrom="I2S2ext">
24793 <name>I2S3ext</name>
24794 <baseAddress>0x40004000</baseAddress>
24795 </peripheral>
24796 <peripheral derivedFrom="I2S2ext">
24797 <name>SPI1</name>
24798 <baseAddress>0x40013000</baseAddress>
24799 </peripheral>
24800 <peripheral derivedFrom="I2S2ext">
24801 <name>SPI2</name>
24802 <baseAddress>0x40003800</baseAddress>
24803 <interrupt>
24804 <name>SPI1</name>
24805 <description>SPI1 global interrupt</description>
24806 <value>35</value>
24807 </interrupt>
24808 </peripheral>
24809 <peripheral derivedFrom="I2S2ext">
24810 <name>SPI3</name>
24811 <baseAddress>0x40003C00</baseAddress>
24812 <interrupt>
24813 <name>SPI2</name>
24814 <description>SPI2 global interrupt</description>
24815 <value>36</value>
24816 </interrupt>
24817 </peripheral>
24818 <peripheral derivedFrom="I2S2ext">
24819 <name>SPI4</name>
24820 <baseAddress>0x40013400</baseAddress>
24821 <interrupt>
24822 <name>SPI3</name>
24823 <description>SPI3 global interrupt</description>
24824 <value>51</value>
24825 </interrupt>
24826 </peripheral>
24827 <peripheral derivedFrom="I2S2ext">
24828 <name>SPI5</name>
24829 <baseAddress>0x40015000</baseAddress>
24830 </peripheral>
24831 <peripheral>
24832 <name>NVIC</name>
24833 <description>Nested Vectored Interrupt
24834 Controller</description>
24835 <groupName>NVIC</groupName>
24836 <baseAddress>0xE000E100</baseAddress>
24837 <addressBlock>
24838 <offset>0x0</offset>
24839 <size>0x351</size>
24840 <usage>registers</usage>
24841 </addressBlock>
24842 <registers>
24843 <register>
24844 <name>ISER0</name>
24845 <displayName>ISER0</displayName>
24846 <description>Interrupt Set-Enable Register</description>
24847 <addressOffset>0x0</addressOffset>
24848 <size>0x20</size>
24849 <access>read-write</access>
24850 <resetValue>0x00000000</resetValue>
24851 <fields>
24852 <field>
24853 <name>SETENA</name>
24854 <description>SETENA</description>
24855 <bitOffset>0</bitOffset>
24856 <bitWidth>32</bitWidth>
24857 </field>
24858 </fields>
24859 </register>
24860 <register>
24861 <name>ISER1</name>
24862 <displayName>ISER1</displayName>
24863 <description>Interrupt Set-Enable Register</description>
24864 <addressOffset>0x4</addressOffset>
24865 <size>0x20</size>
24866 <access>read-write</access>
24867 <resetValue>0x00000000</resetValue>
24868 <fields>
24869 <field>
24870 <name>SETENA</name>
24871 <description>SETENA</description>
24872 <bitOffset>0</bitOffset>
24873 <bitWidth>32</bitWidth>
24874 </field>
24875 </fields>
24876 </register>
24877 <register>
24878 <name>ISER2</name>
24879 <displayName>ISER2</displayName>
24880 <description>Interrupt Set-Enable Register</description>
24881 <addressOffset>0x8</addressOffset>
24882 <size>0x20</size>
24883 <access>read-write</access>
24884 <resetValue>0x00000000</resetValue>
24885 <fields>
24886 <field>
24887 <name>SETENA</name>
24888 <description>SETENA</description>
24889 <bitOffset>0</bitOffset>
24890 <bitWidth>32</bitWidth>
24891 </field>
24892 </fields>
24893 </register>
24894 <register>
24895 <name>ICER0</name>
24896 <displayName>ICER0</displayName>
24897 <description>Interrupt Clear-Enable
24898 Register</description>
24899 <addressOffset>0x80</addressOffset>
24900 <size>0x20</size>
24901 <access>read-write</access>
24902 <resetValue>0x00000000</resetValue>
24903 <fields>
24904 <field>
24905 <name>CLRENA</name>
24906 <description>CLRENA</description>
24907 <bitOffset>0</bitOffset>
24908 <bitWidth>32</bitWidth>
24909 </field>
24910 </fields>
24911 </register>
24912 <register>
24913 <name>ICER1</name>
24914 <displayName>ICER1</displayName>
24915 <description>Interrupt Clear-Enable
24916 Register</description>
24917 <addressOffset>0x84</addressOffset>
24918 <size>0x20</size>
24919 <access>read-write</access>
24920 <resetValue>0x00000000</resetValue>
24921 <fields>
24922 <field>
24923 <name>CLRENA</name>
24924 <description>CLRENA</description>
24925 <bitOffset>0</bitOffset>
24926 <bitWidth>32</bitWidth>
24927 </field>
24928 </fields>
24929 </register>
24930 <register>
24931 <name>ICER2</name>
24932 <displayName>ICER2</displayName>
24933 <description>Interrupt Clear-Enable
24934 Register</description>
24935 <addressOffset>0x88</addressOffset>
24936 <size>0x20</size>
24937 <access>read-write</access>
24938 <resetValue>0x00000000</resetValue>
24939 <fields>
24940 <field>
24941 <name>CLRENA</name>
24942 <description>CLRENA</description>
24943 <bitOffset>0</bitOffset>
24944 <bitWidth>32</bitWidth>
24945 </field>
24946 </fields>
24947 </register>
24948 <register>
24949 <name>ISPR0</name>
24950 <displayName>ISPR0</displayName>
24951 <description>Interrupt Set-Pending Register</description>
24952 <addressOffset>0x100</addressOffset>
24953 <size>0x20</size>
24954 <access>read-write</access>
24955 <resetValue>0x00000000</resetValue>
24956 <fields>
24957 <field>
24958 <name>SETPEND</name>
24959 <description>SETPEND</description>
24960 <bitOffset>0</bitOffset>
24961 <bitWidth>32</bitWidth>
24962 </field>
24963 </fields>
24964 </register>
24965 <register>
24966 <name>ISPR1</name>
24967 <displayName>ISPR1</displayName>
24968 <description>Interrupt Set-Pending Register</description>
24969 <addressOffset>0x104</addressOffset>
24970 <size>0x20</size>
24971 <access>read-write</access>
24972 <resetValue>0x00000000</resetValue>
24973 <fields>
24974 <field>
24975 <name>SETPEND</name>
24976 <description>SETPEND</description>
24977 <bitOffset>0</bitOffset>
24978 <bitWidth>32</bitWidth>
24979 </field>
24980 </fields>
24981 </register>
24982 <register>
24983 <name>ISPR2</name>
24984 <displayName>ISPR2</displayName>
24985 <description>Interrupt Set-Pending Register</description>
24986 <addressOffset>0x108</addressOffset>
24987 <size>0x20</size>
24988 <access>read-write</access>
24989 <resetValue>0x00000000</resetValue>
24990 <fields>
24991 <field>
24992 <name>SETPEND</name>
24993 <description>SETPEND</description>
24994 <bitOffset>0</bitOffset>
24995 <bitWidth>32</bitWidth>
24996 </field>
24997 </fields>
24998 </register>
24999 <register>
25000 <name>ICPR0</name>
25001 <displayName>ICPR0</displayName>
25002 <description>Interrupt Clear-Pending
25003 Register</description>
25004 <addressOffset>0x180</addressOffset>
25005 <size>0x20</size>
25006 <access>read-write</access>
25007 <resetValue>0x00000000</resetValue>
25008 <fields>
25009 <field>
25010 <name>CLRPEND</name>
25011 <description>CLRPEND</description>
25012 <bitOffset>0</bitOffset>
25013 <bitWidth>32</bitWidth>
25014 </field>
25015 </fields>
25016 </register>
25017 <register>
25018 <name>ICPR1</name>
25019 <displayName>ICPR1</displayName>
25020 <description>Interrupt Clear-Pending
25021 Register</description>
25022 <addressOffset>0x184</addressOffset>
25023 <size>0x20</size>
25024 <access>read-write</access>
25025 <resetValue>0x00000000</resetValue>
25026 <fields>
25027 <field>
25028 <name>CLRPEND</name>
25029 <description>CLRPEND</description>
25030 <bitOffset>0</bitOffset>
25031 <bitWidth>32</bitWidth>
25032 </field>
25033 </fields>
25034 </register>
25035 <register>
25036 <name>ICPR2</name>
25037 <displayName>ICPR2</displayName>
25038 <description>Interrupt Clear-Pending
25039 Register</description>
25040 <addressOffset>0x188</addressOffset>
25041 <size>0x20</size>
25042 <access>read-write</access>
25043 <resetValue>0x00000000</resetValue>
25044 <fields>
25045 <field>
25046 <name>CLRPEND</name>
25047 <description>CLRPEND</description>
25048 <bitOffset>0</bitOffset>
25049 <bitWidth>32</bitWidth>
25050 </field>
25051 </fields>
25052 </register>
25053 <register>
25054 <name>IABR0</name>
25055 <displayName>IABR0</displayName>
25056 <description>Interrupt Active Bit Register</description>
25057 <addressOffset>0x200</addressOffset>
25058 <size>0x20</size>
25059 <access>read-only</access>
25060 <resetValue>0x00000000</resetValue>
25061 <fields>
25062 <field>
25063 <name>ACTIVE</name>
25064 <description>ACTIVE</description>
25065 <bitOffset>0</bitOffset>
25066 <bitWidth>32</bitWidth>
25067 </field>
25068 </fields>
25069 </register>
25070 <register>
25071 <name>IABR1</name>
25072 <displayName>IABR1</displayName>
25073 <description>Interrupt Active Bit Register</description>
25074 <addressOffset>0x204</addressOffset>
25075 <size>0x20</size>
25076 <access>read-only</access>
25077 <resetValue>0x00000000</resetValue>
25078 <fields>
25079 <field>
25080 <name>ACTIVE</name>
25081 <description>ACTIVE</description>
25082 <bitOffset>0</bitOffset>
25083 <bitWidth>32</bitWidth>
25084 </field>
25085 </fields>
25086 </register>
25087 <register>
25088 <name>IABR2</name>
25089 <displayName>IABR2</displayName>
25090 <description>Interrupt Active Bit Register</description>
25091 <addressOffset>0x208</addressOffset>
25092 <size>0x20</size>
25093 <access>read-only</access>
25094 <resetValue>0x00000000</resetValue>
25095 <fields>
25096 <field>
25097 <name>ACTIVE</name>
25098 <description>ACTIVE</description>
25099 <bitOffset>0</bitOffset>
25100 <bitWidth>32</bitWidth>
25101 </field>
25102 </fields>
25103 </register>
25104 <register>
25105 <name>IPR0</name>
25106 <displayName>IPR0</displayName>
25107 <description>Interrupt Priority Register</description>
25108 <addressOffset>0x300</addressOffset>
25109 <size>0x20</size>
25110 <access>read-write</access>
25111 <resetValue>0x00000000</resetValue>
25112 <fields>
25113 <field>
25114 <name>IPR_N0</name>
25115 <description>IPR_N0</description>
25116 <bitOffset>0</bitOffset>
25117 <bitWidth>8</bitWidth>
25118 </field>
25119 <field>
25120 <name>IPR_N1</name>
25121 <description>IPR_N1</description>
25122 <bitOffset>8</bitOffset>
25123 <bitWidth>8</bitWidth>
25124 </field>
25125 <field>
25126 <name>IPR_N2</name>
25127 <description>IPR_N2</description>
25128 <bitOffset>16</bitOffset>
25129 <bitWidth>8</bitWidth>
25130 </field>
25131 <field>
25132 <name>IPR_N3</name>
25133 <description>IPR_N3</description>
25134 <bitOffset>24</bitOffset>
25135 <bitWidth>8</bitWidth>
25136 </field>
25137 </fields>
25138 </register>
25139 <register>
25140 <name>IPR1</name>
25141 <displayName>IPR1</displayName>
25142 <description>Interrupt Priority Register</description>
25143 <addressOffset>0x304</addressOffset>
25144 <size>0x20</size>
25145 <access>read-write</access>
25146 <resetValue>0x00000000</resetValue>
25147 <fields>
25148 <field>
25149 <name>IPR_N0</name>
25150 <description>IPR_N0</description>
25151 <bitOffset>0</bitOffset>
25152 <bitWidth>8</bitWidth>
25153 </field>
25154 <field>
25155 <name>IPR_N1</name>
25156 <description>IPR_N1</description>
25157 <bitOffset>8</bitOffset>
25158 <bitWidth>8</bitWidth>
25159 </field>
25160 <field>
25161 <name>IPR_N2</name>
25162 <description>IPR_N2</description>
25163 <bitOffset>16</bitOffset>
25164 <bitWidth>8</bitWidth>
25165 </field>
25166 <field>
25167 <name>IPR_N3</name>
25168 <description>IPR_N3</description>
25169 <bitOffset>24</bitOffset>
25170 <bitWidth>8</bitWidth>
25171 </field>
25172 </fields>
25173 </register>
25174 <register>
25175 <name>IPR2</name>
25176 <displayName>IPR2</displayName>
25177 <description>Interrupt Priority Register</description>
25178 <addressOffset>0x308</addressOffset>
25179 <size>0x20</size>
25180 <access>read-write</access>
25181 <resetValue>0x00000000</resetValue>
25182 <fields>
25183 <field>
25184 <name>IPR_N0</name>
25185 <description>IPR_N0</description>
25186 <bitOffset>0</bitOffset>
25187 <bitWidth>8</bitWidth>
25188 </field>
25189 <field>
25190 <name>IPR_N1</name>
25191 <description>IPR_N1</description>
25192 <bitOffset>8</bitOffset>
25193 <bitWidth>8</bitWidth>
25194 </field>
25195 <field>
25196 <name>IPR_N2</name>
25197 <description>IPR_N2</description>
25198 <bitOffset>16</bitOffset>
25199 <bitWidth>8</bitWidth>
25200 </field>
25201 <field>
25202 <name>IPR_N3</name>
25203 <description>IPR_N3</description>
25204 <bitOffset>24</bitOffset>
25205 <bitWidth>8</bitWidth>
25206 </field>
25207 </fields>
25208 </register>
25209 <register>
25210 <name>IPR3</name>
25211 <displayName>IPR3</displayName>
25212 <description>Interrupt Priority Register</description>
25213 <addressOffset>0x30C</addressOffset>
25214 <size>0x20</size>
25215 <access>read-write</access>
25216 <resetValue>0x00000000</resetValue>
25217 <fields>
25218 <field>
25219 <name>IPR_N0</name>
25220 <description>IPR_N0</description>
25221 <bitOffset>0</bitOffset>
25222 <bitWidth>8</bitWidth>
25223 </field>
25224 <field>
25225 <name>IPR_N1</name>
25226 <description>IPR_N1</description>
25227 <bitOffset>8</bitOffset>
25228 <bitWidth>8</bitWidth>
25229 </field>
25230 <field>
25231 <name>IPR_N2</name>
25232 <description>IPR_N2</description>
25233 <bitOffset>16</bitOffset>
25234 <bitWidth>8</bitWidth>
25235 </field>
25236 <field>
25237 <name>IPR_N3</name>
25238 <description>IPR_N3</description>
25239 <bitOffset>24</bitOffset>
25240 <bitWidth>8</bitWidth>
25241 </field>
25242 </fields>
25243 </register>
25244 <register>
25245 <name>IPR4</name>
25246 <displayName>IPR4</displayName>
25247 <description>Interrupt Priority Register</description>
25248 <addressOffset>0x310</addressOffset>
25249 <size>0x20</size>
25250 <access>read-write</access>
25251 <resetValue>0x00000000</resetValue>
25252 <fields>
25253 <field>
25254 <name>IPR_N0</name>
25255 <description>IPR_N0</description>
25256 <bitOffset>0</bitOffset>
25257 <bitWidth>8</bitWidth>
25258 </field>
25259 <field>
25260 <name>IPR_N1</name>
25261 <description>IPR_N1</description>
25262 <bitOffset>8</bitOffset>
25263 <bitWidth>8</bitWidth>
25264 </field>
25265 <field>
25266 <name>IPR_N2</name>
25267 <description>IPR_N2</description>
25268 <bitOffset>16</bitOffset>
25269 <bitWidth>8</bitWidth>
25270 </field>
25271 <field>
25272 <name>IPR_N3</name>
25273 <description>IPR_N3</description>
25274 <bitOffset>24</bitOffset>
25275 <bitWidth>8</bitWidth>
25276 </field>
25277 </fields>
25278 </register>
25279 <register>
25280 <name>IPR5</name>
25281 <displayName>IPR5</displayName>
25282 <description>Interrupt Priority Register</description>
25283 <addressOffset>0x314</addressOffset>
25284 <size>0x20</size>
25285 <access>read-write</access>
25286 <resetValue>0x00000000</resetValue>
25287 <fields>
25288 <field>
25289 <name>IPR_N0</name>
25290 <description>IPR_N0</description>
25291 <bitOffset>0</bitOffset>
25292 <bitWidth>8</bitWidth>
25293 </field>
25294 <field>
25295 <name>IPR_N1</name>
25296 <description>IPR_N1</description>
25297 <bitOffset>8</bitOffset>
25298 <bitWidth>8</bitWidth>
25299 </field>
25300 <field>
25301 <name>IPR_N2</name>
25302 <description>IPR_N2</description>
25303 <bitOffset>16</bitOffset>
25304 <bitWidth>8</bitWidth>
25305 </field>
25306 <field>
25307 <name>IPR_N3</name>
25308 <description>IPR_N3</description>
25309 <bitOffset>24</bitOffset>
25310 <bitWidth>8</bitWidth>
25311 </field>
25312 </fields>
25313 </register>
25314 <register>
25315 <name>IPR6</name>
25316 <displayName>IPR6</displayName>
25317 <description>Interrupt Priority Register</description>
25318 <addressOffset>0x318</addressOffset>
25319 <size>0x20</size>
25320 <access>read-write</access>
25321 <resetValue>0x00000000</resetValue>
25322 <fields>
25323 <field>
25324 <name>IPR_N0</name>
25325 <description>IPR_N0</description>
25326 <bitOffset>0</bitOffset>
25327 <bitWidth>8</bitWidth>
25328 </field>
25329 <field>
25330 <name>IPR_N1</name>
25331 <description>IPR_N1</description>
25332 <bitOffset>8</bitOffset>
25333 <bitWidth>8</bitWidth>
25334 </field>
25335 <field>
25336 <name>IPR_N2</name>
25337 <description>IPR_N2</description>
25338 <bitOffset>16</bitOffset>
25339 <bitWidth>8</bitWidth>
25340 </field>
25341 <field>
25342 <name>IPR_N3</name>
25343 <description>IPR_N3</description>
25344 <bitOffset>24</bitOffset>
25345 <bitWidth>8</bitWidth>
25346 </field>
25347 </fields>
25348 </register>
25349 <register>
25350 <name>IPR7</name>
25351 <displayName>IPR7</displayName>
25352 <description>Interrupt Priority Register</description>
25353 <addressOffset>0x31C</addressOffset>
25354 <size>0x20</size>
25355 <access>read-write</access>
25356 <resetValue>0x00000000</resetValue>
25357 <fields>
25358 <field>
25359 <name>IPR_N0</name>
25360 <description>IPR_N0</description>
25361 <bitOffset>0</bitOffset>
25362 <bitWidth>8</bitWidth>
25363 </field>
25364 <field>
25365 <name>IPR_N1</name>
25366 <description>IPR_N1</description>
25367 <bitOffset>8</bitOffset>
25368 <bitWidth>8</bitWidth>
25369 </field>
25370 <field>
25371 <name>IPR_N2</name>
25372 <description>IPR_N2</description>
25373 <bitOffset>16</bitOffset>
25374 <bitWidth>8</bitWidth>
25375 </field>
25376 <field>
25377 <name>IPR_N3</name>
25378 <description>IPR_N3</description>
25379 <bitOffset>24</bitOffset>
25380 <bitWidth>8</bitWidth>
25381 </field>
25382 </fields>
25383 </register>
25384 <register>
25385 <name>IPR8</name>
25386 <displayName>IPR8</displayName>
25387 <description>Interrupt Priority Register</description>
25388 <addressOffset>0x320</addressOffset>
25389 <size>0x20</size>
25390 <access>read-write</access>
25391 <resetValue>0x00000000</resetValue>
25392 <fields>
25393 <field>
25394 <name>IPR_N0</name>
25395 <description>IPR_N0</description>
25396 <bitOffset>0</bitOffset>
25397 <bitWidth>8</bitWidth>
25398 </field>
25399 <field>
25400 <name>IPR_N1</name>
25401 <description>IPR_N1</description>
25402 <bitOffset>8</bitOffset>
25403 <bitWidth>8</bitWidth>
25404 </field>
25405 <field>
25406 <name>IPR_N2</name>
25407 <description>IPR_N2</description>
25408 <bitOffset>16</bitOffset>
25409 <bitWidth>8</bitWidth>
25410 </field>
25411 <field>
25412 <name>IPR_N3</name>
25413 <description>IPR_N3</description>
25414 <bitOffset>24</bitOffset>
25415 <bitWidth>8</bitWidth>
25416 </field>
25417 </fields>
25418 </register>
25419 <register>
25420 <name>IPR9</name>
25421 <displayName>IPR9</displayName>
25422 <description>Interrupt Priority Register</description>
25423 <addressOffset>0x324</addressOffset>
25424 <size>0x20</size>
25425 <access>read-write</access>
25426 <resetValue>0x00000000</resetValue>
25427 <fields>
25428 <field>
25429 <name>IPR_N0</name>
25430 <description>IPR_N0</description>
25431 <bitOffset>0</bitOffset>
25432 <bitWidth>8</bitWidth>
25433 </field>
25434 <field>
25435 <name>IPR_N1</name>
25436 <description>IPR_N1</description>
25437 <bitOffset>8</bitOffset>
25438 <bitWidth>8</bitWidth>
25439 </field>
25440 <field>
25441 <name>IPR_N2</name>
25442 <description>IPR_N2</description>
25443 <bitOffset>16</bitOffset>
25444 <bitWidth>8</bitWidth>
25445 </field>
25446 <field>
25447 <name>IPR_N3</name>
25448 <description>IPR_N3</description>
25449 <bitOffset>24</bitOffset>
25450 <bitWidth>8</bitWidth>
25451 </field>
25452 </fields>
25453 </register>
25454 <register>
25455 <name>IPR10</name>
25456 <displayName>IPR10</displayName>
25457 <description>Interrupt Priority Register</description>
25458 <addressOffset>0x328</addressOffset>
25459 <size>0x20</size>
25460 <access>read-write</access>
25461 <resetValue>0x00000000</resetValue>
25462 <fields>
25463 <field>
25464 <name>IPR_N0</name>
25465 <description>IPR_N0</description>
25466 <bitOffset>0</bitOffset>
25467 <bitWidth>8</bitWidth>
25468 </field>
25469 <field>
25470 <name>IPR_N1</name>
25471 <description>IPR_N1</description>
25472 <bitOffset>8</bitOffset>
25473 <bitWidth>8</bitWidth>
25474 </field>
25475 <field>
25476 <name>IPR_N2</name>
25477 <description>IPR_N2</description>
25478 <bitOffset>16</bitOffset>
25479 <bitWidth>8</bitWidth>
25480 </field>
25481 <field>
25482 <name>IPR_N3</name>
25483 <description>IPR_N3</description>
25484 <bitOffset>24</bitOffset>
25485 <bitWidth>8</bitWidth>
25486 </field>
25487 </fields>
25488 </register>
25489 <register>
25490 <name>IPR11</name>
25491 <displayName>IPR11</displayName>
25492 <description>Interrupt Priority Register</description>
25493 <addressOffset>0x32C</addressOffset>
25494 <size>0x20</size>
25495 <access>read-write</access>
25496 <resetValue>0x00000000</resetValue>
25497 <fields>
25498 <field>
25499 <name>IPR_N0</name>
25500 <description>IPR_N0</description>
25501 <bitOffset>0</bitOffset>
25502 <bitWidth>8</bitWidth>
25503 </field>
25504 <field>
25505 <name>IPR_N1</name>
25506 <description>IPR_N1</description>
25507 <bitOffset>8</bitOffset>
25508 <bitWidth>8</bitWidth>
25509 </field>
25510 <field>
25511 <name>IPR_N2</name>
25512 <description>IPR_N2</description>
25513 <bitOffset>16</bitOffset>
25514 <bitWidth>8</bitWidth>
25515 </field>
25516 <field>
25517 <name>IPR_N3</name>
25518 <description>IPR_N3</description>
25519 <bitOffset>24</bitOffset>
25520 <bitWidth>8</bitWidth>
25521 </field>
25522 </fields>
25523 </register>
25524 <register>
25525 <name>IPR12</name>
25526 <displayName>IPR12</displayName>
25527 <description>Interrupt Priority Register</description>
25528 <addressOffset>0x330</addressOffset>
25529 <size>0x20</size>
25530 <access>read-write</access>
25531 <resetValue>0x00000000</resetValue>
25532 <fields>
25533 <field>
25534 <name>IPR_N0</name>
25535 <description>IPR_N0</description>
25536 <bitOffset>0</bitOffset>
25537 <bitWidth>8</bitWidth>
25538 </field>
25539 <field>
25540 <name>IPR_N1</name>
25541 <description>IPR_N1</description>
25542 <bitOffset>8</bitOffset>
25543 <bitWidth>8</bitWidth>
25544 </field>
25545 <field>
25546 <name>IPR_N2</name>
25547 <description>IPR_N2</description>
25548 <bitOffset>16</bitOffset>
25549 <bitWidth>8</bitWidth>
25550 </field>
25551 <field>
25552 <name>IPR_N3</name>
25553 <description>IPR_N3</description>
25554 <bitOffset>24</bitOffset>
25555 <bitWidth>8</bitWidth>
25556 </field>
25557 </fields>
25558 </register>
25559 <register>
25560 <name>IPR13</name>
25561 <displayName>IPR13</displayName>
25562 <description>Interrupt Priority Register</description>
25563 <addressOffset>0x334</addressOffset>
25564 <size>0x20</size>
25565 <access>read-write</access>
25566 <resetValue>0x00000000</resetValue>
25567 <fields>
25568 <field>
25569 <name>IPR_N0</name>
25570 <description>IPR_N0</description>
25571 <bitOffset>0</bitOffset>
25572 <bitWidth>8</bitWidth>
25573 </field>
25574 <field>
25575 <name>IPR_N1</name>
25576 <description>IPR_N1</description>
25577 <bitOffset>8</bitOffset>
25578 <bitWidth>8</bitWidth>
25579 </field>
25580 <field>
25581 <name>IPR_N2</name>
25582 <description>IPR_N2</description>
25583 <bitOffset>16</bitOffset>
25584 <bitWidth>8</bitWidth>
25585 </field>
25586 <field>
25587 <name>IPR_N3</name>
25588 <description>IPR_N3</description>
25589 <bitOffset>24</bitOffset>
25590 <bitWidth>8</bitWidth>
25591 </field>
25592 </fields>
25593 </register>
25594 <register>
25595 <name>IPR14</name>
25596 <displayName>IPR14</displayName>
25597 <description>Interrupt Priority Register</description>
25598 <addressOffset>0x338</addressOffset>
25599 <size>0x20</size>
25600 <access>read-write</access>
25601 <resetValue>0x00000000</resetValue>
25602 <fields>
25603 <field>
25604 <name>IPR_N0</name>
25605 <description>IPR_N0</description>
25606 <bitOffset>0</bitOffset>
25607 <bitWidth>8</bitWidth>
25608 </field>
25609 <field>
25610 <name>IPR_N1</name>
25611 <description>IPR_N1</description>
25612 <bitOffset>8</bitOffset>
25613 <bitWidth>8</bitWidth>
25614 </field>
25615 <field>
25616 <name>IPR_N2</name>
25617 <description>IPR_N2</description>
25618 <bitOffset>16</bitOffset>
25619 <bitWidth>8</bitWidth>
25620 </field>
25621 <field>
25622 <name>IPR_N3</name>
25623 <description>IPR_N3</description>
25624 <bitOffset>24</bitOffset>
25625 <bitWidth>8</bitWidth>
25626 </field>
25627 </fields>
25628 </register>
25629 <register>
25630 <name>IPR15</name>
25631 <displayName>IPR15</displayName>
25632 <description>Interrupt Priority Register</description>
25633 <addressOffset>0x33C</addressOffset>
25634 <size>0x20</size>
25635 <access>read-write</access>
25636 <resetValue>0x00000000</resetValue>
25637 <fields>
25638 <field>
25639 <name>IPR_N0</name>
25640 <description>IPR_N0</description>
25641 <bitOffset>0</bitOffset>
25642 <bitWidth>8</bitWidth>
25643 </field>
25644 <field>
25645 <name>IPR_N1</name>
25646 <description>IPR_N1</description>
25647 <bitOffset>8</bitOffset>
25648 <bitWidth>8</bitWidth>
25649 </field>
25650 <field>
25651 <name>IPR_N2</name>
25652 <description>IPR_N2</description>
25653 <bitOffset>16</bitOffset>
25654 <bitWidth>8</bitWidth>
25655 </field>
25656 <field>
25657 <name>IPR_N3</name>
25658 <description>IPR_N3</description>
25659 <bitOffset>24</bitOffset>
25660 <bitWidth>8</bitWidth>
25661 </field>
25662 </fields>
25663 </register>
25664 <register>
25665 <name>IPR16</name>
25666 <displayName>IPR16</displayName>
25667 <description>Interrupt Priority Register</description>
25668 <addressOffset>0x340</addressOffset>
25669 <size>0x20</size>
25670 <access>read-write</access>
25671 <resetValue>0x00000000</resetValue>
25672 <fields>
25673 <field>
25674 <name>IPR_N0</name>
25675 <description>IPR_N0</description>
25676 <bitOffset>0</bitOffset>
25677 <bitWidth>8</bitWidth>
25678 </field>
25679 <field>
25680 <name>IPR_N1</name>
25681 <description>IPR_N1</description>
25682 <bitOffset>8</bitOffset>
25683 <bitWidth>8</bitWidth>
25684 </field>
25685 <field>
25686 <name>IPR_N2</name>
25687 <description>IPR_N2</description>
25688 <bitOffset>16</bitOffset>
25689 <bitWidth>8</bitWidth>
25690 </field>
25691 <field>
25692 <name>IPR_N3</name>
25693 <description>IPR_N3</description>
25694 <bitOffset>24</bitOffset>
25695 <bitWidth>8</bitWidth>
25696 </field>
25697 </fields>
25698 </register>
25699 <register>
25700 <name>IPR17</name>
25701 <displayName>IPR17</displayName>
25702 <description>Interrupt Priority Register</description>
25703 <addressOffset>0x344</addressOffset>
25704 <size>0x20</size>
25705 <access>read-write</access>
25706 <resetValue>0x00000000</resetValue>
25707 <fields>
25708 <field>
25709 <name>IPR_N0</name>
25710 <description>IPR_N0</description>
25711 <bitOffset>0</bitOffset>
25712 <bitWidth>8</bitWidth>
25713 </field>
25714 <field>
25715 <name>IPR_N1</name>
25716 <description>IPR_N1</description>
25717 <bitOffset>8</bitOffset>
25718 <bitWidth>8</bitWidth>
25719 </field>
25720 <field>
25721 <name>IPR_N2</name>
25722 <description>IPR_N2</description>
25723 <bitOffset>16</bitOffset>
25724 <bitWidth>8</bitWidth>
25725 </field>
25726 <field>
25727 <name>IPR_N3</name>
25728 <description>IPR_N3</description>
25729 <bitOffset>24</bitOffset>
25730 <bitWidth>8</bitWidth>
25731 </field>
25732 </fields>
25733 </register>
25734 <register>
25735 <name>IPR18</name>
25736 <displayName>IPR18</displayName>
25737 <description>Interrupt Priority Register</description>
25738 <addressOffset>0x348</addressOffset>
25739 <size>0x20</size>
25740 <access>read-write</access>
25741 <resetValue>0x00000000</resetValue>
25742 <fields>
25743 <field>
25744 <name>IPR_N0</name>
25745 <description>IPR_N0</description>
25746 <bitOffset>0</bitOffset>
25747 <bitWidth>8</bitWidth>
25748 </field>
25749 <field>
25750 <name>IPR_N1</name>
25751 <description>IPR_N1</description>
25752 <bitOffset>8</bitOffset>
25753 <bitWidth>8</bitWidth>
25754 </field>
25755 <field>
25756 <name>IPR_N2</name>
25757 <description>IPR_N2</description>
25758 <bitOffset>16</bitOffset>
25759 <bitWidth>8</bitWidth>
25760 </field>
25761 <field>
25762 <name>IPR_N3</name>
25763 <description>IPR_N3</description>
25764 <bitOffset>24</bitOffset>
25765 <bitWidth>8</bitWidth>
25766 </field>
25767 </fields>
25768 </register>
25769 <register>
25770 <name>IPR19</name>
25771 <displayName>IPR19</displayName>
25772 <description>Interrupt Priority Register</description>
25773 <addressOffset>0x34C</addressOffset>
25774 <size>0x20</size>
25775 <access>read-write</access>
25776 <resetValue>0x00000000</resetValue>
25777 <fields>
25778 <field>
25779 <name>IPR_N0</name>
25780 <description>IPR_N0</description>
25781 <bitOffset>0</bitOffset>
25782 <bitWidth>8</bitWidth>
25783 </field>
25784 <field>
25785 <name>IPR_N1</name>
25786 <description>IPR_N1</description>
25787 <bitOffset>8</bitOffset>
25788 <bitWidth>8</bitWidth>
25789 </field>
25790 <field>
25791 <name>IPR_N2</name>
25792 <description>IPR_N2</description>
25793 <bitOffset>16</bitOffset>
25794 <bitWidth>8</bitWidth>
25795 </field>
25796 <field>
25797 <name>IPR_N3</name>
25798 <description>IPR_N3</description>
25799 <bitOffset>24</bitOffset>
25800 <bitWidth>8</bitWidth>
25801 </field>
25802 </fields>
25803 </register>
25804 </registers>
25805 </peripheral>
25806 <peripheral>
25807 <name>FPU</name>
25808 <description>Floting point unit</description>
25809 <groupName>FPU</groupName>
25810 <baseAddress>0xE000EF34</baseAddress>
25811 <addressBlock>
25812 <offset>0x0</offset>
25813 <size>0xD</size>
25814 <usage>registers</usage>
25815 </addressBlock>
25816 <interrupt>
25817 <name>FPU</name>
25818 <description>Floating point unit interrupt</description>
25819 <value>81</value>
25820 </interrupt>
25821 <interrupt>
25822 <name>FPU</name>
25823 <description>Floating point interrupt</description>
25824 <value>81</value>
25825 </interrupt>
25826 <registers>
25827 <register>
25828 <name>FPCCR</name>
25829 <displayName>FPCCR</displayName>
25830 <description>Floating-point context control
25831 register</description>
25832 <addressOffset>0x0</addressOffset>
25833 <size>0x20</size>
25834 <access>read-write</access>
25835 <resetValue>0x00000000</resetValue>
25836 <fields>
25837 <field>
25838 <name>LSPACT</name>
25839 <description>LSPACT</description>
25840 <bitOffset>0</bitOffset>
25841 <bitWidth>1</bitWidth>
25842 </field>
25843 <field>
25844 <name>USER</name>
25845 <description>USER</description>
25846 <bitOffset>1</bitOffset>
25847 <bitWidth>1</bitWidth>
25848 </field>
25849 <field>
25850 <name>THREAD</name>
25851 <description>THREAD</description>
25852 <bitOffset>3</bitOffset>
25853 <bitWidth>1</bitWidth>
25854 </field>
25855 <field>
25856 <name>HFRDY</name>
25857 <description>HFRDY</description>
25858 <bitOffset>4</bitOffset>
25859 <bitWidth>1</bitWidth>
25860 </field>
25861 <field>
25862 <name>MMRDY</name>
25863 <description>MMRDY</description>
25864 <bitOffset>5</bitOffset>
25865 <bitWidth>1</bitWidth>
25866 </field>
25867 <field>
25868 <name>BFRDY</name>
25869 <description>BFRDY</description>
25870 <bitOffset>6</bitOffset>
25871 <bitWidth>1</bitWidth>
25872 </field>
25873 <field>
25874 <name>MONRDY</name>
25875 <description>MONRDY</description>
25876 <bitOffset>8</bitOffset>
25877 <bitWidth>1</bitWidth>
25878 </field>
25879 <field>
25880 <name>LSPEN</name>
25881 <description>LSPEN</description>
25882 <bitOffset>30</bitOffset>
25883 <bitWidth>1</bitWidth>
25884 </field>
25885 <field>
25886 <name>ASPEN</name>
25887 <description>ASPEN</description>
25888 <bitOffset>31</bitOffset>
25889 <bitWidth>1</bitWidth>
25890 </field>
25891 </fields>
25892 </register>
25893 <register>
25894 <name>FPCAR</name>
25895 <displayName>FPCAR</displayName>
25896 <description>Floating-point context address
25897 register</description>
25898 <addressOffset>0x4</addressOffset>
25899 <size>0x20</size>
25900 <access>read-write</access>
25901 <resetValue>0x00000000</resetValue>
25902 <fields>
25903 <field>
25904 <name>ADDRESS</name>
25905 <description>Location of unpopulated
25906 floating-point</description>
25907 <bitOffset>3</bitOffset>
25908 <bitWidth>29</bitWidth>
25909 </field>
25910 </fields>
25911 </register>
25912 <register>
25913 <name>FPSCR</name>
25914 <displayName>FPSCR</displayName>
25915 <description>Floating-point status control
25916 register</description>
25917 <addressOffset>0x8</addressOffset>
25918 <size>0x20</size>
25919 <access>read-write</access>
25920 <resetValue>0x00000000</resetValue>
25921 <fields>
25922 <field>
25923 <name>IOC</name>
25924 <description>Invalid operation cumulative exception
25925 bit</description>
25926 <bitOffset>0</bitOffset>
25927 <bitWidth>1</bitWidth>
25928 </field>
25929 <field>
25930 <name>DZC</name>
25931 <description>Division by zero cumulative exception
25932 bit.</description>
25933 <bitOffset>1</bitOffset>
25934 <bitWidth>1</bitWidth>
25935 </field>
25936 <field>
25937 <name>OFC</name>
25938 <description>Overflow cumulative exception
25939 bit</description>
25940 <bitOffset>2</bitOffset>
25941 <bitWidth>1</bitWidth>
25942 </field>
25943 <field>
25944 <name>UFC</name>
25945 <description>Underflow cumulative exception
25946 bit</description>
25947 <bitOffset>3</bitOffset>
25948 <bitWidth>1</bitWidth>
25949 </field>
25950 <field>
25951 <name>IXC</name>
25952 <description>Inexact cumulative exception
25953 bit</description>
25954 <bitOffset>4</bitOffset>
25955 <bitWidth>1</bitWidth>
25956 </field>
25957 <field>
25958 <name>IDC</name>
25959 <description>Input denormal cumulative exception
25960 bit.</description>
25961 <bitOffset>7</bitOffset>
25962 <bitWidth>1</bitWidth>
25963 </field>
25964 <field>
25965 <name>RMode</name>
25966 <description>Rounding Mode control
25967 field</description>
25968 <bitOffset>22</bitOffset>
25969 <bitWidth>2</bitWidth>
25970 </field>
25971 <field>
25972 <name>FZ</name>
25973 <description>Flush-to-zero mode control
25974 bit:</description>
25975 <bitOffset>24</bitOffset>
25976 <bitWidth>1</bitWidth>
25977 </field>
25978 <field>
25979 <name>DN</name>
25980 <description>Default NaN mode control
25981 bit</description>
25982 <bitOffset>25</bitOffset>
25983 <bitWidth>1</bitWidth>
25984 </field>
25985 <field>
25986 <name>AHP</name>
25987 <description>Alternative half-precision control
25988 bit</description>
25989 <bitOffset>26</bitOffset>
25990 <bitWidth>1</bitWidth>
25991 </field>
25992 <field>
25993 <name>V</name>
25994 <description>Overflow condition code
25995 flag</description>
25996 <bitOffset>28</bitOffset>
25997 <bitWidth>1</bitWidth>
25998 </field>
25999 <field>
26000 <name>C</name>
26001 <description>Carry condition code flag</description>
26002 <bitOffset>29</bitOffset>
26003 <bitWidth>1</bitWidth>
26004 </field>
26005 <field>
26006 <name>Z</name>
26007 <description>Zero condition code flag</description>
26008 <bitOffset>30</bitOffset>
26009 <bitWidth>1</bitWidth>
26010 </field>
26011 <field>
26012 <name>N</name>
26013 <description>Negative condition code
26014 flag</description>
26015 <bitOffset>31</bitOffset>
26016 <bitWidth>1</bitWidth>
26017 </field>
26018 </fields>
26019 </register>
26020 </registers>
26021 </peripheral>
26022 <peripheral>
26023 <name>MPU</name>
26024 <description>Memory protection unit</description>
26025 <groupName>MPU</groupName>
26026 <baseAddress>0xE000ED90</baseAddress>
26027 <addressBlock>
26028 <offset>0x0</offset>
26029 <size>0x15</size>
26030 <usage>registers</usage>
26031 </addressBlock>
26032 <registers>
26033 <register>
26034 <name>MPU_TYPER</name>
26035 <displayName>MPU_TYPER</displayName>
26036 <description>MPU type register</description>
26037 <addressOffset>0x0</addressOffset>
26038 <size>0x20</size>
26039 <access>read-only</access>
26040 <resetValue>0X00000800</resetValue>
26041 <fields>
26042 <field>
26043 <name>SEPARATE</name>
26044 <description>Separate flag</description>
26045 <bitOffset>0</bitOffset>
26046 <bitWidth>1</bitWidth>
26047 </field>
26048 <field>
26049 <name>DREGION</name>
26050 <description>Number of MPU data regions</description>
26051 <bitOffset>8</bitOffset>
26052 <bitWidth>8</bitWidth>
26053 </field>
26054 <field>
26055 <name>IREGION</name>
26056 <description>Number of MPU instruction
26057 regions</description>
26058 <bitOffset>16</bitOffset>
26059 <bitWidth>8</bitWidth>
26060 </field>
26061 </fields>
26062 </register>
26063 <register>
26064 <name>MPU_CTRL</name>
26065 <displayName>MPU_CTRL</displayName>
26066 <description>MPU control register</description>
26067 <addressOffset>0x4</addressOffset>
26068 <size>0x20</size>
26069 <access>read-only</access>
26070 <resetValue>0X00000000</resetValue>
26071 <fields>
26072 <field>
26073 <name>ENABLE</name>
26074 <description>Enables the MPU</description>
26075 <bitOffset>0</bitOffset>
26076 <bitWidth>1</bitWidth>
26077 </field>
26078 <field>
26079 <name>HFNMIENA</name>
26080 <description>Enables the operation of MPU during hard
26081 fault</description>
26082 <bitOffset>1</bitOffset>
26083 <bitWidth>1</bitWidth>
26084 </field>
26085 <field>
26086 <name>PRIVDEFENA</name>
26087 <description>Enable priviliged software access to
26088 default memory map</description>
26089 <bitOffset>2</bitOffset>
26090 <bitWidth>1</bitWidth>
26091 </field>
26092 </fields>
26093 </register>
26094 <register>
26095 <name>MPU_RNR</name>
26096 <displayName>MPU_RNR</displayName>
26097 <description>MPU region number register</description>
26098 <addressOffset>0x8</addressOffset>
26099 <size>0x20</size>
26100 <access>read-write</access>
26101 <resetValue>0X00000000</resetValue>
26102 <fields>
26103 <field>
26104 <name>REGION</name>
26105 <description>MPU region</description>
26106 <bitOffset>0</bitOffset>
26107 <bitWidth>8</bitWidth>
26108 </field>
26109 </fields>
26110 </register>
26111 <register>
26112 <name>MPU_RBAR</name>
26113 <displayName>MPU_RBAR</displayName>
26114 <description>MPU region base address
26115 register</description>
26116 <addressOffset>0xC</addressOffset>
26117 <size>0x20</size>
26118 <access>read-write</access>
26119 <resetValue>0X00000000</resetValue>
26120 <fields>
26121 <field>
26122 <name>REGION</name>
26123 <description>MPU region field</description>
26124 <bitOffset>0</bitOffset>
26125 <bitWidth>4</bitWidth>
26126 </field>
26127 <field>
26128 <name>VALID</name>
26129 <description>MPU region number valid</description>
26130 <bitOffset>4</bitOffset>
26131 <bitWidth>1</bitWidth>
26132 </field>
26133 <field>
26134 <name>ADDR</name>
26135 <description>Region base address field</description>
26136 <bitOffset>5</bitOffset>
26137 <bitWidth>27</bitWidth>
26138 </field>
26139 </fields>
26140 </register>
26141 <register>
26142 <name>MPU_RASR</name>
26143 <displayName>MPU_RASR</displayName>
26144 <description>MPU region attribute and size
26145 register</description>
26146 <addressOffset>0x10</addressOffset>
26147 <size>0x20</size>
26148 <access>read-write</access>
26149 <resetValue>0X00000000</resetValue>
26150 <fields>
26151 <field>
26152 <name>ENABLE</name>
26153 <description>Region enable bit.</description>
26154 <bitOffset>0</bitOffset>
26155 <bitWidth>1</bitWidth>
26156 </field>
26157 <field>
26158 <name>SIZE</name>
26159 <description>Size of the MPU protection
26160 region</description>
26161 <bitOffset>1</bitOffset>
26162 <bitWidth>5</bitWidth>
26163 </field>
26164 <field>
26165 <name>SRD</name>
26166 <description>Subregion disable bits</description>
26167 <bitOffset>8</bitOffset>
26168 <bitWidth>8</bitWidth>
26169 </field>
26170 <field>
26171 <name>B</name>
26172 <description>memory attribute</description>
26173 <bitOffset>16</bitOffset>
26174 <bitWidth>1</bitWidth>
26175 </field>
26176 <field>
26177 <name>C</name>
26178 <description>memory attribute</description>
26179 <bitOffset>17</bitOffset>
26180 <bitWidth>1</bitWidth>
26181 </field>
26182 <field>
26183 <name>S</name>
26184 <description>Shareable memory attribute</description>
26185 <bitOffset>18</bitOffset>
26186 <bitWidth>1</bitWidth>
26187 </field>
26188 <field>
26189 <name>TEX</name>
26190 <description>memory attribute</description>
26191 <bitOffset>19</bitOffset>
26192 <bitWidth>3</bitWidth>
26193 </field>
26194 <field>
26195 <name>AP</name>
26196 <description>Access permission</description>
26197 <bitOffset>24</bitOffset>
26198 <bitWidth>3</bitWidth>
26199 </field>
26200 <field>
26201 <name>XN</name>
26202 <description>Instruction access disable
26203 bit</description>
26204 <bitOffset>28</bitOffset>
26205 <bitWidth>1</bitWidth>
26206 </field>
26207 </fields>
26208 </register>
26209 </registers>
26210 </peripheral>
26211 <peripheral>
26212 <name>STK</name>
26213 <description>SysTick timer</description>
26214 <groupName>STK</groupName>
26215 <baseAddress>0xE000E010</baseAddress>
26216 <addressBlock>
26217 <offset>0x0</offset>
26218 <size>0x11</size>
26219 <usage>registers</usage>
26220 </addressBlock>
26221 <registers>
26222 <register>
26223 <name>CTRL</name>
26224 <displayName>CTRL</displayName>
26225 <description>SysTick control and status
26226 register</description>
26227 <addressOffset>0x0</addressOffset>
26228 <size>0x20</size>
26229 <access>read-write</access>
26230 <resetValue>0X00000000</resetValue>
26231 <fields>
26232 <field>
26233 <name>ENABLE</name>
26234 <description>Counter enable</description>
26235 <bitOffset>0</bitOffset>
26236 <bitWidth>1</bitWidth>
26237 </field>
26238 <field>
26239 <name>TICKINT</name>
26240 <description>SysTick exception request
26241 enable</description>
26242 <bitOffset>1</bitOffset>
26243 <bitWidth>1</bitWidth>
26244 </field>
26245 <field>
26246 <name>CLKSOURCE</name>
26247 <description>Clock source selection</description>
26248 <bitOffset>2</bitOffset>
26249 <bitWidth>1</bitWidth>
26250 </field>
26251 <field>
26252 <name>COUNTFLAG</name>
26253 <description>COUNTFLAG</description>
26254 <bitOffset>16</bitOffset>
26255 <bitWidth>1</bitWidth>
26256 </field>
26257 </fields>
26258 </register>
26259 <register>
26260 <name>LOAD</name>
26261 <displayName>LOAD</displayName>
26262 <description>SysTick reload value register</description>
26263 <addressOffset>0x4</addressOffset>
26264 <size>0x20</size>
26265 <access>read-write</access>
26266 <resetValue>0X00000000</resetValue>
26267 <fields>
26268 <field>
26269 <name>RELOAD</name>
26270 <description>RELOAD value</description>
26271 <bitOffset>0</bitOffset>
26272 <bitWidth>24</bitWidth>
26273 </field>
26274 </fields>
26275 </register>
26276 <register>
26277 <name>VAL</name>
26278 <displayName>VAL</displayName>
26279 <description>SysTick current value register</description>
26280 <addressOffset>0x8</addressOffset>
26281 <size>0x20</size>
26282 <access>read-write</access>
26283 <resetValue>0X00000000</resetValue>
26284 <fields>
26285 <field>
26286 <name>CURRENT</name>
26287 <description>Current counter value</description>
26288 <bitOffset>0</bitOffset>
26289 <bitWidth>24</bitWidth>
26290 </field>
26291 </fields>
26292 </register>
26293 <register>
26294 <name>CALIB</name>
26295 <displayName>CALIB</displayName>
26296 <description>SysTick calibration value
26297 register</description>
26298 <addressOffset>0xC</addressOffset>
26299 <size>0x20</size>
26300 <access>read-write</access>
26301 <resetValue>0X00000000</resetValue>
26302 <fields>
26303 <field>
26304 <name>TENMS</name>
26305 <description>Calibration value</description>
26306 <bitOffset>0</bitOffset>
26307 <bitWidth>24</bitWidth>
26308 </field>
26309 <field>
26310 <name>SKEW</name>
26311 <description>SKEW flag: Indicates whether the TENMS
26312 value is exact</description>
26313 <bitOffset>30</bitOffset>
26314 <bitWidth>1</bitWidth>
26315 </field>
26316 <field>
26317 <name>NOREF</name>
26318 <description>NOREF flag. Reads as zero</description>
26319 <bitOffset>31</bitOffset>
26320 <bitWidth>1</bitWidth>
26321 </field>
26322 </fields>
26323 </register>
26324 </registers>
26325 </peripheral>
26326 <peripheral>
26327 <name>SCB</name>
26328 <description>System control block</description>
26329 <groupName>SCB</groupName>
26330 <baseAddress>0xE000ED00</baseAddress>
26331 <addressBlock>
26332 <offset>0x0</offset>
26333 <size>0x41</size>
26334 <usage>registers</usage>
26335 </addressBlock>
26336 <registers>
26337 <register>
26338 <name>CPUID</name>
26339 <displayName>CPUID</displayName>
26340 <description>CPUID base register</description>
26341 <addressOffset>0x0</addressOffset>
26342 <size>0x20</size>
26343 <access>read-only</access>
26344 <resetValue>0x410FC241</resetValue>
26345 <fields>
26346 <field>
26347 <name>Revision</name>
26348 <description>Revision number</description>
26349 <bitOffset>0</bitOffset>
26350 <bitWidth>4</bitWidth>
26351 </field>
26352 <field>
26353 <name>PartNo</name>
26354 <description>Part number of the
26355 processor</description>
26356 <bitOffset>4</bitOffset>
26357 <bitWidth>12</bitWidth>
26358 </field>
26359 <field>
26360 <name>Constant</name>
26361 <description>Reads as 0xF</description>
26362 <bitOffset>16</bitOffset>
26363 <bitWidth>4</bitWidth>
26364 </field>
26365 <field>
26366 <name>Variant</name>
26367 <description>Variant number</description>
26368 <bitOffset>20</bitOffset>
26369 <bitWidth>4</bitWidth>
26370 </field>
26371 <field>
26372 <name>Implementer</name>
26373 <description>Implementer code</description>
26374 <bitOffset>24</bitOffset>
26375 <bitWidth>8</bitWidth>
26376 </field>
26377 </fields>
26378 </register>
26379 <register>
26380 <name>ICSR</name>
26381 <displayName>ICSR</displayName>
26382 <description>Interrupt control and state
26383 register</description>
26384 <addressOffset>0x4</addressOffset>
26385 <size>0x20</size>
26386 <access>read-write</access>
26387 <resetValue>0x00000000</resetValue>
26388 <fields>
26389 <field>
26390 <name>VECTACTIVE</name>
26391 <description>Active vector</description>
26392 <bitOffset>0</bitOffset>
26393 <bitWidth>9</bitWidth>
26394 </field>
26395 <field>
26396 <name>RETTOBASE</name>
26397 <description>Return to base level</description>
26398 <bitOffset>11</bitOffset>
26399 <bitWidth>1</bitWidth>
26400 </field>
26401 <field>
26402 <name>VECTPENDING</name>
26403 <description>Pending vector</description>
26404 <bitOffset>12</bitOffset>
26405 <bitWidth>7</bitWidth>
26406 </field>
26407 <field>
26408 <name>ISRPENDING</name>
26409 <description>Interrupt pending flag</description>
26410 <bitOffset>22</bitOffset>
26411 <bitWidth>1</bitWidth>
26412 </field>
26413 <field>
26414 <name>PENDSTCLR</name>
26415 <description>SysTick exception clear-pending
26416 bit</description>
26417 <bitOffset>25</bitOffset>
26418 <bitWidth>1</bitWidth>
26419 </field>
26420 <field>
26421 <name>PENDSTSET</name>
26422 <description>SysTick exception set-pending
26423 bit</description>
26424 <bitOffset>26</bitOffset>
26425 <bitWidth>1</bitWidth>
26426 </field>
26427 <field>
26428 <name>PENDSVCLR</name>
26429 <description>PendSV clear-pending bit</description>
26430 <bitOffset>27</bitOffset>
26431 <bitWidth>1</bitWidth>
26432 </field>
26433 <field>
26434 <name>PENDSVSET</name>
26435 <description>PendSV set-pending bit</description>
26436 <bitOffset>28</bitOffset>
26437 <bitWidth>1</bitWidth>
26438 </field>
26439 <field>
26440 <name>NMIPENDSET</name>
26441 <description>NMI set-pending bit.</description>
26442 <bitOffset>31</bitOffset>
26443 <bitWidth>1</bitWidth>
26444 </field>
26445 </fields>
26446 </register>
26447 <register>
26448 <name>VTOR</name>
26449 <displayName>VTOR</displayName>
26450 <description>Vector table offset register</description>
26451 <addressOffset>0x8</addressOffset>
26452 <size>0x20</size>
26453 <access>read-write</access>
26454 <resetValue>0x00000000</resetValue>
26455 <fields>
26456 <field>
26457 <name>TBLOFF</name>
26458 <description>Vector table base offset
26459 field</description>
26460 <bitOffset>9</bitOffset>
26461 <bitWidth>21</bitWidth>
26462 </field>
26463 </fields>
26464 </register>
26465 <register>
26466 <name>AIRCR</name>
26467 <displayName>AIRCR</displayName>
26468 <description>Application interrupt and reset control
26469 register</description>
26470 <addressOffset>0xC</addressOffset>
26471 <size>0x20</size>
26472 <access>read-write</access>
26473 <resetValue>0x00000000</resetValue>
26474 <fields>
26475 <field>
26476 <name>VECTRESET</name>
26477 <description>VECTRESET</description>
26478 <bitOffset>0</bitOffset>
26479 <bitWidth>1</bitWidth>
26480 </field>
26481 <field>
26482 <name>VECTCLRACTIVE</name>
26483 <description>VECTCLRACTIVE</description>
26484 <bitOffset>1</bitOffset>
26485 <bitWidth>1</bitWidth>
26486 </field>
26487 <field>
26488 <name>SYSRESETREQ</name>
26489 <description>SYSRESETREQ</description>
26490 <bitOffset>2</bitOffset>
26491 <bitWidth>1</bitWidth>
26492 </field>
26493 <field>
26494 <name>PRIGROUP</name>
26495 <description>PRIGROUP</description>
26496 <bitOffset>8</bitOffset>
26497 <bitWidth>3</bitWidth>
26498 </field>
26499 <field>
26500 <name>ENDIANESS</name>
26501 <description>ENDIANESS</description>
26502 <bitOffset>15</bitOffset>
26503 <bitWidth>1</bitWidth>
26504 </field>
26505 <field>
26506 <name>VECTKEYSTAT</name>
26507 <description>Register key</description>
26508 <bitOffset>16</bitOffset>
26509 <bitWidth>16</bitWidth>
26510 </field>
26511 </fields>
26512 </register>
26513 <register>
26514 <name>SCR</name>
26515 <displayName>SCR</displayName>
26516 <description>System control register</description>
26517 <addressOffset>0x10</addressOffset>
26518 <size>0x20</size>
26519 <access>read-write</access>
26520 <resetValue>0x00000000</resetValue>
26521 <fields>
26522 <field>
26523 <name>SLEEPONEXIT</name>
26524 <description>SLEEPONEXIT</description>
26525 <bitOffset>1</bitOffset>
26526 <bitWidth>1</bitWidth>
26527 </field>
26528 <field>
26529 <name>SLEEPDEEP</name>
26530 <description>SLEEPDEEP</description>
26531 <bitOffset>2</bitOffset>
26532 <bitWidth>1</bitWidth>
26533 </field>
26534 <field>
26535 <name>SEVEONPEND</name>
26536 <description>Send Event on Pending bit</description>
26537 <bitOffset>4</bitOffset>
26538 <bitWidth>1</bitWidth>
26539 </field>
26540 </fields>
26541 </register>
26542 <register>
26543 <name>CCR</name>
26544 <displayName>CCR</displayName>
26545 <description>Configuration and control
26546 register</description>
26547 <addressOffset>0x14</addressOffset>
26548 <size>0x20</size>
26549 <access>read-write</access>
26550 <resetValue>0x00000000</resetValue>
26551 <fields>
26552 <field>
26553 <name>NONBASETHRDENA</name>
26554 <description>Configures how the processor enters
26555 Thread mode</description>
26556 <bitOffset>0</bitOffset>
26557 <bitWidth>1</bitWidth>
26558 </field>
26559 <field>
26560 <name>USERSETMPEND</name>
26561 <description>USERSETMPEND</description>
26562 <bitOffset>1</bitOffset>
26563 <bitWidth>1</bitWidth>
26564 </field>
26565 <field>
26566 <name>UNALIGN__TRP</name>
26567 <description>UNALIGN_ TRP</description>
26568 <bitOffset>3</bitOffset>
26569 <bitWidth>1</bitWidth>
26570 </field>
26571 <field>
26572 <name>DIV_0_TRP</name>
26573 <description>DIV_0_TRP</description>
26574 <bitOffset>4</bitOffset>
26575 <bitWidth>1</bitWidth>
26576 </field>
26577 <field>
26578 <name>BFHFNMIGN</name>
26579 <description>BFHFNMIGN</description>
26580 <bitOffset>8</bitOffset>
26581 <bitWidth>1</bitWidth>
26582 </field>
26583 <field>
26584 <name>STKALIGN</name>
26585 <description>STKALIGN</description>
26586 <bitOffset>9</bitOffset>
26587 <bitWidth>1</bitWidth>
26588 </field>
26589 </fields>
26590 </register>
26591 <register>
26592 <name>SHPR1</name>
26593 <displayName>SHPR1</displayName>
26594 <description>System handler priority
26595 registers</description>
26596 <addressOffset>0x18</addressOffset>
26597 <size>0x20</size>
26598 <access>read-write</access>
26599 <resetValue>0x00000000</resetValue>
26600 <fields>
26601 <field>
26602 <name>PRI_4</name>
26603 <description>Priority of system handler
26604 4</description>
26605 <bitOffset>0</bitOffset>
26606 <bitWidth>8</bitWidth>
26607 </field>
26608 <field>
26609 <name>PRI_5</name>
26610 <description>Priority of system handler
26611 5</description>
26612 <bitOffset>8</bitOffset>
26613 <bitWidth>8</bitWidth>
26614 </field>
26615 <field>
26616 <name>PRI_6</name>
26617 <description>Priority of system handler
26618 6</description>
26619 <bitOffset>16</bitOffset>
26620 <bitWidth>8</bitWidth>
26621 </field>
26622 </fields>
26623 </register>
26624 <register>
26625 <name>SHPR2</name>
26626 <displayName>SHPR2</displayName>
26627 <description>System handler priority
26628 registers</description>
26629 <addressOffset>0x1C</addressOffset>
26630 <size>0x20</size>
26631 <access>read-write</access>
26632 <resetValue>0x00000000</resetValue>
26633 <fields>
26634 <field>
26635 <name>PRI_11</name>
26636 <description>Priority of system handler
26637 11</description>
26638 <bitOffset>24</bitOffset>
26639 <bitWidth>8</bitWidth>
26640 </field>
26641 </fields>
26642 </register>
26643 <register>
26644 <name>SHPR3</name>
26645 <displayName>SHPR3</displayName>
26646 <description>System handler priority
26647 registers</description>
26648 <addressOffset>0x20</addressOffset>
26649 <size>0x20</size>
26650 <access>read-write</access>
26651 <resetValue>0x00000000</resetValue>
26652 <fields>
26653 <field>
26654 <name>PRI_14</name>
26655 <description>Priority of system handler
26656 14</description>
26657 <bitOffset>16</bitOffset>
26658 <bitWidth>8</bitWidth>
26659 </field>
26660 <field>
26661 <name>PRI_15</name>
26662 <description>Priority of system handler
26663 15</description>
26664 <bitOffset>24</bitOffset>
26665 <bitWidth>8</bitWidth>
26666 </field>
26667 </fields>
26668 </register>
26669 <register>
26670 <name>SHCRS</name>
26671 <displayName>SHCRS</displayName>
26672 <description>System handler control and state
26673 register</description>
26674 <addressOffset>0x24</addressOffset>
26675 <size>0x20</size>
26676 <access>read-write</access>
26677 <resetValue>0x00000000</resetValue>
26678 <fields>
26679 <field>
26680 <name>MEMFAULTACT</name>
26681 <description>Memory management fault exception active
26682 bit</description>
26683 <bitOffset>0</bitOffset>
26684 <bitWidth>1</bitWidth>
26685 </field>
26686 <field>
26687 <name>BUSFAULTACT</name>
26688 <description>Bus fault exception active
26689 bit</description>
26690 <bitOffset>1</bitOffset>
26691 <bitWidth>1</bitWidth>
26692 </field>
26693 <field>
26694 <name>USGFAULTACT</name>
26695 <description>Usage fault exception active
26696 bit</description>
26697 <bitOffset>3</bitOffset>
26698 <bitWidth>1</bitWidth>
26699 </field>
26700 <field>
26701 <name>SVCALLACT</name>
26702 <description>SVC call active bit</description>
26703 <bitOffset>7</bitOffset>
26704 <bitWidth>1</bitWidth>
26705 </field>
26706 <field>
26707 <name>MONITORACT</name>
26708 <description>Debug monitor active bit</description>
26709 <bitOffset>8</bitOffset>
26710 <bitWidth>1</bitWidth>
26711 </field>
26712 <field>
26713 <name>PENDSVACT</name>
26714 <description>PendSV exception active
26715 bit</description>
26716 <bitOffset>10</bitOffset>
26717 <bitWidth>1</bitWidth>
26718 </field>
26719 <field>
26720 <name>SYSTICKACT</name>
26721 <description>SysTick exception active
26722 bit</description>
26723 <bitOffset>11</bitOffset>
26724 <bitWidth>1</bitWidth>
26725 </field>
26726 <field>
26727 <name>USGFAULTPENDED</name>
26728 <description>Usage fault exception pending
26729 bit</description>
26730 <bitOffset>12</bitOffset>
26731 <bitWidth>1</bitWidth>
26732 </field>
26733 <field>
26734 <name>MEMFAULTPENDED</name>
26735 <description>Memory management fault exception
26736 pending bit</description>
26737 <bitOffset>13</bitOffset>
26738 <bitWidth>1</bitWidth>
26739 </field>
26740 <field>
26741 <name>BUSFAULTPENDED</name>
26742 <description>Bus fault exception pending
26743 bit</description>
26744 <bitOffset>14</bitOffset>
26745 <bitWidth>1</bitWidth>
26746 </field>
26747 <field>
26748 <name>SVCALLPENDED</name>
26749 <description>SVC call pending bit</description>
26750 <bitOffset>15</bitOffset>
26751 <bitWidth>1</bitWidth>
26752 </field>
26753 <field>
26754 <name>MEMFAULTENA</name>
26755 <description>Memory management fault enable
26756 bit</description>
26757 <bitOffset>16</bitOffset>
26758 <bitWidth>1</bitWidth>
26759 </field>
26760 <field>
26761 <name>BUSFAULTENA</name>
26762 <description>Bus fault enable bit</description>
26763 <bitOffset>17</bitOffset>
26764 <bitWidth>1</bitWidth>
26765 </field>
26766 <field>
26767 <name>USGFAULTENA</name>
26768 <description>Usage fault enable bit</description>
26769 <bitOffset>18</bitOffset>
26770 <bitWidth>1</bitWidth>
26771 </field>
26772 </fields>
26773 </register>
26774 <register>
26775 <name>CFSR_UFSR_BFSR_MMFSR</name>
26776 <displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
26777 <description>Configurable fault status
26778 register</description>
26779 <addressOffset>0x28</addressOffset>
26780 <size>0x20</size>
26781 <access>read-write</access>
26782 <resetValue>0x00000000</resetValue>
26783 <fields>
26784 <field>
26785 <name>IACCVIOL</name>
26786 <description>Instruction access violation
26787 flag</description>
26788 <bitOffset>1</bitOffset>
26789 <bitWidth>1</bitWidth>
26790 </field>
26791 <field>
26792 <name>MUNSTKERR</name>
26793 <description>Memory manager fault on unstacking for a
26794 return from exception</description>
26795 <bitOffset>3</bitOffset>
26796 <bitWidth>1</bitWidth>
26797 </field>
26798 <field>
26799 <name>MSTKERR</name>
26800 <description>Memory manager fault on stacking for
26801 exception entry.</description>
26802 <bitOffset>4</bitOffset>
26803 <bitWidth>1</bitWidth>
26804 </field>
26805 <field>
26806 <name>MLSPERR</name>
26807 <description>MLSPERR</description>
26808 <bitOffset>5</bitOffset>
26809 <bitWidth>1</bitWidth>
26810 </field>
26811 <field>
26812 <name>MMARVALID</name>
26813 <description>Memory Management Fault Address Register
26814 (MMAR) valid flag</description>
26815 <bitOffset>7</bitOffset>
26816 <bitWidth>1</bitWidth>
26817 </field>
26818 <field>
26819 <name>IBUSERR</name>
26820 <description>Instruction bus error</description>
26821 <bitOffset>8</bitOffset>
26822 <bitWidth>1</bitWidth>
26823 </field>
26824 <field>
26825 <name>PRECISERR</name>
26826 <description>Precise data bus error</description>
26827 <bitOffset>9</bitOffset>
26828 <bitWidth>1</bitWidth>
26829 </field>
26830 <field>
26831 <name>IMPRECISERR</name>
26832 <description>Imprecise data bus error</description>
26833 <bitOffset>10</bitOffset>
26834 <bitWidth>1</bitWidth>
26835 </field>
26836 <field>
26837 <name>UNSTKERR</name>
26838 <description>Bus fault on unstacking for a return
26839 from exception</description>
26840 <bitOffset>11</bitOffset>
26841 <bitWidth>1</bitWidth>
26842 </field>
26843 <field>
26844 <name>STKERR</name>
26845 <description>Bus fault on stacking for exception
26846 entry</description>
26847 <bitOffset>12</bitOffset>
26848 <bitWidth>1</bitWidth>
26849 </field>
26850 <field>
26851 <name>LSPERR</name>
26852 <description>Bus fault on floating-point lazy state
26853 preservation</description>
26854 <bitOffset>13</bitOffset>
26855 <bitWidth>1</bitWidth>
26856 </field>
26857 <field>
26858 <name>BFARVALID</name>
26859 <description>Bus Fault Address Register (BFAR) valid
26860 flag</description>
26861 <bitOffset>15</bitOffset>
26862 <bitWidth>1</bitWidth>
26863 </field>
26864 <field>
26865 <name>UNDEFINSTR</name>
26866 <description>Undefined instruction usage
26867 fault</description>
26868 <bitOffset>16</bitOffset>
26869 <bitWidth>1</bitWidth>
26870 </field>
26871 <field>
26872 <name>INVSTATE</name>
26873 <description>Invalid state usage fault</description>
26874 <bitOffset>17</bitOffset>
26875 <bitWidth>1</bitWidth>
26876 </field>
26877 <field>
26878 <name>INVPC</name>
26879 <description>Invalid PC load usage
26880 fault</description>
26881 <bitOffset>18</bitOffset>
26882 <bitWidth>1</bitWidth>
26883 </field>
26884 <field>
26885 <name>NOCP</name>
26886 <description>No coprocessor usage
26887 fault.</description>
26888 <bitOffset>19</bitOffset>
26889 <bitWidth>1</bitWidth>
26890 </field>
26891 <field>
26892 <name>UNALIGNED</name>
26893 <description>Unaligned access usage
26894 fault</description>
26895 <bitOffset>24</bitOffset>
26896 <bitWidth>1</bitWidth>
26897 </field>
26898 <field>
26899 <name>DIVBYZERO</name>
26900 <description>Divide by zero usage fault</description>
26901 <bitOffset>25</bitOffset>
26902 <bitWidth>1</bitWidth>
26903 </field>
26904 </fields>
26905 </register>
26906 <register>
26907 <name>HFSR</name>
26908 <displayName>HFSR</displayName>
26909 <description>Hard fault status register</description>
26910 <addressOffset>0x2C</addressOffset>
26911 <size>0x20</size>
26912 <access>read-write</access>
26913 <resetValue>0x00000000</resetValue>
26914 <fields>
26915 <field>
26916 <name>VECTTBL</name>
26917 <description>Vector table hard fault</description>
26918 <bitOffset>1</bitOffset>
26919 <bitWidth>1</bitWidth>
26920 </field>
26921 <field>
26922 <name>FORCED</name>
26923 <description>Forced hard fault</description>
26924 <bitOffset>30</bitOffset>
26925 <bitWidth>1</bitWidth>
26926 </field>
26927 <field>
26928 <name>DEBUG_VT</name>
26929 <description>Reserved for Debug use</description>
26930 <bitOffset>31</bitOffset>
26931 <bitWidth>1</bitWidth>
26932 </field>
26933 </fields>
26934 </register>
26935 <register>
26936 <name>MMFAR</name>
26937 <displayName>MMFAR</displayName>
26938 <description>Memory management fault address
26939 register</description>
26940 <addressOffset>0x34</addressOffset>
26941 <size>0x20</size>
26942 <access>read-write</access>
26943 <resetValue>0x00000000</resetValue>
26944 <fields>
26945 <field>
26946 <name>MMFAR</name>
26947 <description>Memory management fault
26948 address</description>
26949 <bitOffset>0</bitOffset>
26950 <bitWidth>32</bitWidth>
26951 </field>
26952 </fields>
26953 </register>
26954 <register>
26955 <name>BFAR</name>
26956 <displayName>BFAR</displayName>
26957 <description>Bus fault address register</description>
26958 <addressOffset>0x38</addressOffset>
26959 <size>0x20</size>
26960 <access>read-write</access>
26961 <resetValue>0x00000000</resetValue>
26962 <fields>
26963 <field>
26964 <name>BFAR</name>
26965 <description>Bus fault address</description>
26966 <bitOffset>0</bitOffset>
26967 <bitWidth>32</bitWidth>
26968 </field>
26969 </fields>
26970 </register>
26971 <register>
26972 <name>AFSR</name>
26973 <displayName>AFSR</displayName>
26974 <description>Auxiliary fault status
26975 register</description>
26976 <addressOffset>0x3C</addressOffset>
26977 <size>0x20</size>
26978 <access>read-write</access>
26979 <resetValue>0x00000000</resetValue>
26980 <fields>
26981 <field>
26982 <name>IMPDEF</name>
26983 <description>Implementation defined</description>
26984 <bitOffset>0</bitOffset>
26985 <bitWidth>32</bitWidth>
26986 </field>
26987 </fields>
26988 </register>
26989 </registers>
26990 </peripheral>
26991 <peripheral>
26992 <name>NVIC_STIR</name>
26993 <description>Nested vectored interrupt
26994 controller</description>
26995 <groupName>NVIC</groupName>
26996 <baseAddress>0xE000EF00</baseAddress>
26997 <addressBlock>
26998 <offset>0x0</offset>
26999 <size>0x5</size>
27000 <usage>registers</usage>
27001 </addressBlock>
27002 <registers>
27003 <register>
27004 <name>STIR</name>
27005 <displayName>STIR</displayName>
27006 <description>Software trigger interrupt
27007 register</description>
27008 <addressOffset>0x0</addressOffset>
27009 <size>0x20</size>
27010 <access>read-write</access>
27011 <resetValue>0x00000000</resetValue>
27012 <fields>
27013 <field>
27014 <name>INTID</name>
27015 <description>Software generated interrupt
27016 ID</description>
27017 <bitOffset>0</bitOffset>
27018 <bitWidth>9</bitWidth>
27019 </field>
27020 </fields>
27021 </register>
27022 </registers>
27023 </peripheral>
27024 <peripheral>
27025 <name>FPU_CPACR</name>
27026 <description>Floating point unit CPACR</description>
27027 <groupName>FPU</groupName>
27028 <baseAddress>0xE000ED88</baseAddress>
27029 <addressBlock>
27030 <offset>0x0</offset>
27031 <size>0x5</size>
27032 <usage>registers</usage>
27033 </addressBlock>
27034 <registers>
27035 <register>
27036 <name>CPACR</name>
27037 <displayName>CPACR</displayName>
27038 <description>Coprocessor access control
27039 register</description>
27040 <addressOffset>0x0</addressOffset>
27041 <size>0x20</size>
27042 <access>read-write</access>
27043 <resetValue>0x0000000</resetValue>
27044 <fields>
27045 <field>
27046 <name>CP</name>
27047 <description>CP</description>
27048 <bitOffset>20</bitOffset>
27049 <bitWidth>4</bitWidth>
27050 </field>
27051 </fields>
27052 </register>
27053 </registers>
27054 </peripheral>
27055 <peripheral>
27056 <name>SCB_ACTRL</name>
27057 <description>System control block ACTLR</description>
27058 <groupName>SCB</groupName>
27059 <baseAddress>0xE000E008</baseAddress>
27060 <addressBlock>
27061 <offset>0x0</offset>
27062 <size>0x5</size>
27063 <usage>registers</usage>
27064 </addressBlock>
27065 <registers>
27066 <register>
27067 <name>ACTRL</name>
27068 <displayName>ACTRL</displayName>
27069 <description>Auxiliary control register</description>
27070 <addressOffset>0x0</addressOffset>
27071 <size>0x20</size>
27072 <access>read-write</access>
27073 <resetValue>0x00000000</resetValue>
27074 <fields>
27075 <field>
27076 <name>DISMCYCINT</name>
27077 <description>DISMCYCINT</description>
27078 <bitOffset>0</bitOffset>
27079 <bitWidth>1</bitWidth>
27080 </field>
27081 <field>
27082 <name>DISDEFWBUF</name>
27083 <description>DISDEFWBUF</description>
27084 <bitOffset>1</bitOffset>
27085 <bitWidth>1</bitWidth>
27086 </field>
27087 <field>
27088 <name>DISFOLD</name>
27089 <description>DISFOLD</description>
27090 <bitOffset>2</bitOffset>
27091 <bitWidth>1</bitWidth>
27092 </field>
27093 <field>
27094 <name>DISFPCA</name>
27095 <description>DISFPCA</description>
27096 <bitOffset>8</bitOffset>
27097 <bitWidth>1</bitWidth>
27098 </field>
27099 <field>
27100 <name>DISOOFP</name>
27101 <description>DISOOFP</description>
27102 <bitOffset>9</bitOffset>
27103 <bitWidth>1</bitWidth>
27104 </field>
27105 </fields>
27106 </register>
27107 </registers>
27108 </peripheral>
27109 </peripherals>
27110 </device>
INAV: Navigation-enabled flight control software