src/main/drivers/bus_i2c_stm32f40x.c

   1 /*
   2  * This file is part of Cleanflight.
   3  *
   4  * Cleanflight is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Cleanflight is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with Cleanflight.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <stdbool.h>
  19 #include <stdint.h>
  20 #include <stdlib.h>
  21
  22 #include <platform.h>
  23
  24 #include "build/atomic.h"
  25
  26 #include "common/utils.h"
  27
  28 #include "drivers/io.h"
  29 #include "drivers/time.h"
  30
  31 #include "drivers/bus_i2c.h"
  32 #include "drivers/nvic.h"
  33 #include "io_impl.h"
  34 #include "rcc.h"
  35 #include "drivers/light_led.h"
  36
  37 #ifndef SOFT_I2C
  38
  39 static void i2cUnstick(IO_t scl, IO_t sda);
  40
  41 #define GPIO_AF_I2C GPIO_AF_I2C1
  42
  43 #ifdef STM32F4
  44
  45 #if defined(USE_I2C_PULLUP)
  46 #define IOCFG_I2C IO_CONFIG(GPIO_Mode_AF, GPIO_Speed_50MHz, GPIO_OType_OD, GPIO_PuPd_UP)
  47 #else
  48 #define IOCFG_I2C IOCFG_AF_OD
  49 #endif
  50
  51 #ifndef I2C1_SCL
  52 #define I2C1_SCL PB8
  53 #endif
  54 #ifndef I2C1_SDA
  55 #define I2C1_SDA PB9
  56 #endif
  57
  58 #else
  59
  60 #ifndef I2C1_SCL
  61 #define I2C1_SCL PB6
  62 #endif
  63 #ifndef I2C1_SDA
  64 #define I2C1_SDA PB7
  65 #endif
  66 #define IOCFG_I2C   IO_CONFIG(GPIO_Mode_AF_OD, GPIO_Speed_50MHz)
  67
  68 #endif
  69
  70 #ifndef I2C2_SCL
  71 #define I2C2_SCL PB10
  72 #endif
  73
  74 #ifndef I2C2_SDA
  75 #define I2C2_SDA PB11
  76 #endif
  77
  78 #ifdef STM32F4
  79 #ifndef I2C3_SCL
  80 #define I2C3_SCL PA8
  81 #endif
  82 #ifndef I2C3_SDA
  83 #define I2C3_SDA PB4
  84 #endif
  85 #endif
  86
  87 typedef enum {
  88     I2C_STATE_STOPPED = 0,
  89     I2C_STATE_STOPPING,
  90     I2C_STATE_STARTING,
  91     I2C_STATE_STARTING_WAIT,
  92
  93     I2C_STATE_R_ADDR,
  94     I2C_STATE_R_ADDR_WAIT,
  95     I2C_STATE_R_REGISTER,
  96     I2C_STATE_R_REGISTER_WAIT,
  97     I2C_STATE_R_RESTARTING,
  98     I2C_STATE_R_RESTARTING_WAIT,
  99     I2C_STATE_R_RESTART_ADDR,
 100     I2C_STATE_R_RESTART_ADDR_WAIT,
 101     I2C_STATE_R_TRANSFER_EQ1,
 102     I2C_STATE_R_TRANSFER_EQ2,
 103     I2C_STATE_R_TRANSFER_GE2,
 104
 105     I2C_STATE_W_ADDR,
 106     I2C_STATE_W_ADDR_WAIT,
 107     I2C_STATE_W_REGISTER,
 108     I2C_STATE_W_TRANSFER_WAIT,
 109     I2C_STATE_W_TRANSFER,
 110
 111     I2C_STATE_NACK,
 112     I2C_STATE_BUS_ERROR,
 113 } i2cState_t;
 114
 115 typedef enum {
 116     I2C_TXN_READ,
 117     I2C_TXN_WRITE
 118 } i2cTransferDirection_t;
 119
 120 typedef struct i2cBusState_s {
 121     I2CDevice       device;
 122     bool            initialized;
 123     i2cState_t      state;
 124     timeUs_t        timeout;
 125
 126     /* Active transfer */
 127     bool                        allowRawAccess;
 128     uint8_t                     addr;   // device address
 129     i2cTransferDirection_t      rw;     // direction
 130     uint8_t                     reg;    // register
 131     uint32_t                    len;    // buffer length
 132     uint8_t                    *buf;    // buffer
 133     bool                        txnOk;
 134 } i2cBusState_t;
 135
 136 static volatile uint16_t i2cErrorCount = 0;
 137
 138 static i2cDevice_t i2cHardwareMap[] = {
 139     { .dev = I2C1, .scl = IO_TAG(I2C1_SCL), .sda = IO_TAG(I2C1_SDA), .rcc = RCC_APB1(I2C1), .speed = I2C_SPEED_400KHZ },
 140     { .dev = I2C2, .scl = IO_TAG(I2C2_SCL), .sda = IO_TAG(I2C2_SDA), .rcc = RCC_APB1(I2C2), .speed = I2C_SPEED_400KHZ },
 141 #ifdef STM32F4
 142     { .dev = I2C3, .scl = IO_TAG(I2C3_SCL), .sda = IO_TAG(I2C3_SDA), .rcc = RCC_APB1(I2C3), .speed = I2C_SPEED_400KHZ }
 143 #endif
 144 };
 145
 146 static i2cBusState_t busState[I2CDEV_COUNT] = { { 0 } };
 147
 148 static void i2cResetInterface(i2cBusState_t * i2cBusState)
 149 {
 150     const i2cDevice_t * i2c = &(i2cHardwareMap[i2cBusState->device]);
 151     IO_t scl = IOGetByTag(i2c->scl);
 152     IO_t sda = IOGetByTag(i2c->sda);
 153
 154     i2cErrorCount++;
 155     i2cUnstick(scl, sda);
 156     i2cInit(i2cBusState->device);
 157 }
 158
 159 static void i2cStateMachine(i2cBusState_t * i2cBusState, const timeUs_t currentTicksUs)
 160 {
 161     I2C_TypeDef * I2Cx = i2cHardwareMap[i2cBusState->device].dev;
 162
 163     switch (i2cBusState->state) {
 164         case I2C_STATE_BUS_ERROR:
 165             i2cResetInterface(i2cBusState);
 166             i2cBusState->state = I2C_STATE_STOPPED;
 167             break;
 168
 169         case I2C_STATE_STOPPING:
 170             // Wait for stop bit to clear
 171             // RM0090: When the STOP, START or PEC bit is set, the software must not perform any write access
 172             // to I2C_CR1 before this bit is cleared by hardware. Otherwise there is a risk of setting a second STOP, START or PEC request.
 173             if ((I2Cx->CR1 & I2C_CR1_STOP) == 0) {
 174                 i2cBusState->state = I2C_STATE_STOPPED;
 175             }
 176             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 177                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 178             }
 179             break;
 180
 181         case I2C_STATE_STOPPED:
 182             // Stick here
 183             break;
 184
 185         case I2C_STATE_STARTING:
 186             I2C_NACKPositionConfig(I2Cx, I2C_NACKPosition_Current);
 187             I2C_AcknowledgeConfig(I2Cx, ENABLE);
 188             I2C_GenerateSTART(I2Cx, ENABLE);
 189             i2cBusState->state = I2C_STATE_STARTING_WAIT;
 190             i2cBusState->timeout = currentTicksUs;
 191             FALLTHROUGH;
 192
 193         case I2C_STATE_STARTING_WAIT:
 194             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT) != ERROR) {
 195                 if (i2cBusState->rw == I2C_TXN_READ) {
 196                     // Special case - no register address
 197                     if (i2cBusState->reg == 0xFF && i2cBusState->allowRawAccess) {
 198                         i2cBusState->state = I2C_STATE_R_RESTART_ADDR;
 199                     }
 200                     else {
 201                         i2cBusState->state = I2C_STATE_R_ADDR;
 202                     }
 203                 }
 204                 else {
 205                     i2cBusState->state = I2C_STATE_W_ADDR;
 206                 }
 207             }
 208             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 209                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 210             }
 211             break;
 212
 213         case I2C_STATE_R_ADDR:
 214             I2C_Send7bitAddress(I2Cx, i2cBusState->addr, I2C_Direction_Transmitter);
 215             i2cBusState->state = I2C_STATE_R_ADDR_WAIT;
 216             i2cBusState->timeout = currentTicksUs;
 217             FALLTHROUGH;
 218
 219         case I2C_STATE_R_ADDR_WAIT:
 220             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) != ERROR) {
 221                 i2cBusState->state = I2C_STATE_R_REGISTER;
 222             }
 223             else if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_AF) != RESET) {
 224                 i2cBusState->state = I2C_STATE_NACK;
 225             }
 226             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 227                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 228             }
 229             break;
 230
 231         case I2C_STATE_R_REGISTER:      /* Send Register address */
 232             I2C_SendData(I2Cx, i2cBusState->reg);
 233             i2cBusState->state = I2C_STATE_R_REGISTER_WAIT;
 234             i2cBusState->timeout = currentTicksUs;
 235             FALLTHROUGH;
 236
 237         case I2C_STATE_R_REGISTER_WAIT:
 238             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED) != ERROR) {
 239                 if (i2cBusState->len == 0) {
 240                     I2C_GenerateSTOP(I2Cx, ENABLE);
 241                     i2cBusState->timeout = currentTicksUs;
 242                     i2cBusState->state = I2C_STATE_STOPPING;
 243                 }
 244                 else {
 245                     i2cBusState->state = I2C_STATE_R_RESTARTING;
 246                 }
 247             }
 248             else if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_AF) != RESET) {
 249                 i2cBusState->state = I2C_STATE_NACK;
 250             }
 251             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 252                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 253             }
 254             break;
 255
 256         case I2C_STATE_R_RESTARTING:
 257             I2C_GenerateSTART(I2Cx, ENABLE);
 258             i2cBusState->state = I2C_STATE_R_RESTARTING_WAIT;
 259             i2cBusState->timeout = currentTicksUs;
 260             FALLTHROUGH;
 261
 262         case I2C_STATE_R_RESTARTING_WAIT:
 263             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_MODE_SELECT) != ERROR) {
 264                 i2cBusState->state = I2C_STATE_R_RESTART_ADDR;
 265             }
 266             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 267                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 268             }
 269             break;
 270
 271         case I2C_STATE_R_RESTART_ADDR:
 272             I2C_Send7bitAddress(I2Cx, i2cBusState->addr, I2C_Direction_Receiver);
 273             i2cBusState->state = I2C_STATE_R_RESTART_ADDR_WAIT;
 274             i2cBusState->timeout = currentTicksUs;
 275             FALLTHROUGH;
 276
 277         case I2C_STATE_R_RESTART_ADDR_WAIT:
 278             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) != ERROR) {
 279                 if (i2cBusState->len == 1) {
 280                     // This TXN is 1-byte, disable ACK and generate stop early
 281                     I2C_AcknowledgeConfig(I2Cx, DISABLE);
 282
 283                     ATOMIC_BLOCK(NVIC_PRIO_MAX) {
 284                         (void) I2Cx->SR2;
 285                         I2C_GenerateSTOP(I2Cx, ENABLE);
 286                     }
 287
 288                     i2cBusState->state = I2C_STATE_R_TRANSFER_EQ1;
 289                 }
 290                 else if (i2cBusState->len == 2) {
 291                     // 2-byte transaction, disable ACK
 292                     I2C_NACKPositionConfig(I2Cx, I2C_NACKPosition_Next);
 293                     ATOMIC_BLOCK(NVIC_PRIO_MAX) {
 294                         (void) I2Cx->SR2;
 295                         I2C_AcknowledgeConfig(I2Cx, DISABLE);
 296                     }
 297
 298                     i2cBusState->state = I2C_STATE_R_TRANSFER_EQ2;
 299                 }
 300                 else {
 301                     (void) I2Cx->SR2;   // Clear ADDR flag
 302                     i2cBusState->state = I2C_STATE_R_TRANSFER_GE2;
 303                 }
 304
 305                 i2cBusState->timeout = currentTicksUs;
 306             }
 307             else if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_AF) != RESET) {
 308                 i2cBusState->state = I2C_STATE_NACK;
 309             }
 310             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 311                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 312             }
 313             break;
 314
 315         case I2C_STATE_R_TRANSFER_EQ1:
 316             if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_RXNE) != RESET) {
 317                 *i2cBusState->buf++ = I2C_ReceiveData(I2Cx);
 318                 i2cBusState->len--;
 319
 320                 // This was the last successful byte
 321                 i2cBusState->txnOk = true;
 322                 i2cBusState->timeout = currentTicksUs;
 323                 i2cBusState->state = I2C_STATE_STOPPING;
 324             }
 325             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 326                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 327             }
 328             break;
 329
 330         case I2C_STATE_R_TRANSFER_EQ2:
 331             if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF) != RESET) {
 332                 ATOMIC_BLOCK(NVIC_PRIO_MAX) {
 333                     I2C_GenerateSTOP(I2Cx,ENABLE);
 334                     *i2cBusState->buf++ = I2C_ReceiveData(I2Cx);
 335                 }
 336
 337                 *i2cBusState->buf++ = I2C_ReceiveData(I2Cx);
 338                 i2cBusState->len =- 2;
 339
 340                 // This was the last successful byte
 341                 i2cBusState->txnOk = true;
 342                 i2cBusState->timeout = currentTicksUs;
 343                 i2cBusState->state = I2C_STATE_STOPPING;
 344             }
 345             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 346                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 347             }
 348             break;
 349
 350         case I2C_STATE_R_TRANSFER_GE2:
 351             if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_BTF) != RESET) {
 352                 if (i2cBusState->len == 3) {
 353                     I2C_AcknowledgeConfig(I2Cx, DISABLE);           // clear ack bit
 354
 355                     ATOMIC_BLOCK(NVIC_PRIO_MAX) {
 356                         *i2cBusState->buf++ = I2C_ReceiveData(I2Cx);
 357                         I2C_GenerateSTOP(I2Cx,ENABLE);
 358                     }
 359
 360                     *i2cBusState->buf++ = I2C_ReceiveData(I2Cx);
 361                     i2cBusState->len -= 2;
 362
 363                     // Last byte remaining
 364                     i2cBusState->state = I2C_STATE_R_TRANSFER_EQ1;
 365                     i2cBusState->timeout = currentTicksUs;
 366                 }
 367                 else if (i2cBusState->len < 3) {
 368                     // Shouldn't happen - abort
 369                     I2C_AcknowledgeConfig(I2Cx, DISABLE);
 370                     I2C_GenerateSTOP(I2Cx,ENABLE);
 371                     I2C_ReceiveData(I2Cx);
 372
 373                     i2cBusState->txnOk = false;
 374                     i2cBusState->timeout = currentTicksUs;
 375                     i2cBusState->state = I2C_STATE_STOPPING;
 376                 }
 377                 else {
 378                     // 4 or more extra bytes remaining
 379                     *i2cBusState->buf++ = I2C_ReceiveData(I2Cx);
 380                     i2cBusState->len--;
 381
 382                     // Restart timeout and stay in this state
 383                     i2cBusState->timeout = currentTicksUs;
 384                 }
 385             }
 386             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 387                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 388             }
 389             break;
 390
 391         case I2C_STATE_W_ADDR:
 392             I2C_AcknowledgeConfig(I2Cx, DISABLE);
 393             I2C_Send7bitAddress(I2Cx, i2cBusState->addr, I2C_Direction_Transmitter);
 394             i2cBusState->state = I2C_STATE_W_ADDR_WAIT;
 395             i2cBusState->timeout = currentTicksUs;
 396             FALLTHROUGH;
 397
 398         case I2C_STATE_W_ADDR_WAIT:
 399             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) != ERROR) {
 400                 // Special no-address case, skip address byte transmission
 401                 if (i2cBusState->reg == 0xFF && i2cBusState->allowRawAccess) {
 402                     i2cBusState->state = I2C_STATE_W_TRANSFER;
 403                 }
 404                 else {
 405                     i2cBusState->state = I2C_STATE_W_REGISTER;
 406                 }
 407             }
 408             else if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_AF) != RESET) {
 409                 i2cBusState->state = I2C_STATE_NACK;
 410             }
 411             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 412                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 413             }
 414             break;
 415
 416         case I2C_STATE_W_REGISTER:      /* Send Register address */
 417             I2C_SendData(I2Cx, i2cBusState->reg);
 418             i2cBusState->state = I2C_STATE_W_TRANSFER_WAIT;
 419             i2cBusState->timeout = currentTicksUs;
 420             FALLTHROUGH;
 421
 422         case I2C_STATE_W_TRANSFER_WAIT:
 423             if (I2C_CheckEvent(I2Cx, I2C_EVENT_MASTER_BYTE_TRANSMITTED) != ERROR) {
 424                 i2cBusState->state = I2C_STATE_W_TRANSFER;
 425             }
 426             else if (I2C_GetFlagStatus(I2Cx, I2C_FLAG_AF) != RESET) {
 427                 i2cBusState->state = I2C_STATE_NACK;
 428             }
 429             else if ((currentTicksUs - i2cBusState->timeout) >= I2C_TIMEOUT) {
 430                 i2cBusState->state = I2C_STATE_BUS_ERROR;
 431             }
 432             break;
 433
 434         case I2C_STATE_W_TRANSFER:
 435             if (i2cBusState->len > 0) {
 436                 I2C_SendData(I2Cx, *i2cBusState->buf);
 437                 i2cBusState->buf++;
 438                 i2cBusState->len--;
 439                 i2cBusState->timeout = currentTicksUs;
 440                 i2cBusState->state = I2C_STATE_W_TRANSFER_WAIT;
 441             }
 442             else {
 443                 I2C_GenerateSTOP(I2Cx, ENABLE);
 444                 i2cBusState->timeout = currentTicksUs;
 445                 i2cBusState->txnOk = true;
 446                 i2cBusState->state = I2C_STATE_STOPPING;
 447             }
 448             break;
 449
 450         case I2C_STATE_NACK:
 451             I2C_GenerateSTOP(I2Cx, ENABLE);
 452             I2C_ClearFlag(I2Cx, I2C_FLAG_AF);
 453             i2cBusState->timeout = currentTicksUs;
 454             i2cBusState->state = I2C_STATE_STOPPING;
 455             break;
 456     }
 457 }
 458
 459 void i2cSetSpeed(uint8_t speed)
 460 {
 461     for (unsigned int i = 0; i < ARRAYLEN(i2cHardwareMap); i++) {
 462         i2cHardwareMap[i].speed = speed;
 463     }
 464 }
 465
 466 uint32_t i2cTimeoutUserCallback(void)
 467 {
 468     i2cErrorCount++;
 469     return false;
 470 }
 471
 472 void i2cInit(I2CDevice device)
 473 {
 474     if (device == I2CINVALID)
 475         return;
 476
 477     i2cDevice_t *i2c = &(i2cHardwareMap[device]);
 478
 479     IO_t scl = IOGetByTag(i2c->scl);
 480     IO_t sda = IOGetByTag(i2c->sda);
 481
 482     RCC_ClockCmd(i2c->rcc, ENABLE);
 483
 484     IOInit(scl, OWNER_I2C, RESOURCE_I2C_SCL, RESOURCE_INDEX(device));
 485     IOInit(sda, OWNER_I2C, RESOURCE_I2C_SDA, RESOURCE_INDEX(device));
 486
 487 #ifdef STM32F4
 488     IOConfigGPIOAF(scl, IOCFG_I2C, GPIO_AF_I2C);
 489     IOConfigGPIOAF(sda, IOCFG_I2C, GPIO_AF_I2C);
 490 #else
 491     IOConfigGPIO(scl, IOCFG_I2C);
 492     IOConfigGPIO(sda, IOCFG_I2C);
 493 #endif
 494
 495     I2C_DeInit(i2c->dev);
 496
 497     I2C_InitTypeDef i2cInit;
 498     I2C_StructInit(&i2cInit);
 499
 500     i2cInit.I2C_Mode = I2C_Mode_I2C;
 501     i2cInit.I2C_DutyCycle = I2C_DutyCycle_2;
 502     i2cInit.I2C_OwnAddress1 = 0x00;
 503     i2cInit.I2C_Ack = I2C_Ack_Enable;
 504     i2cInit.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
 505
 506     switch (i2c->speed) {
 507         case I2C_SPEED_400KHZ:
 508         default:
 509             i2cInit.I2C_ClockSpeed = 400000;
 510             break;
 511
 512         case I2C_SPEED_800KHZ:
 513             i2cInit.I2C_ClockSpeed = 800000;
 514             break;
 515
 516         case I2C_SPEED_100KHZ:
 517             i2cInit.I2C_ClockSpeed = 100000;
 518             break;
 519
 520         case I2C_SPEED_200KHZ:
 521             i2cInit.I2C_ClockSpeed = 200000;
 522             break;
 523     }
 524
 525     I2C_Init(i2c->dev, &i2cInit);
 526     I2C_StretchClockCmd(i2c->dev, ENABLE);
 527     I2C_Cmd(i2c->dev, ENABLE);
 528
 529     busState[device].device = device;
 530     busState[device].initialized = true;
 531     busState[device].state = I2C_STATE_STOPPED;
 532 }
 533
 534 uint16_t i2cGetErrorCounter(void)
 535 {
 536     return i2cErrorCount;
 537 }
 538
 539 static void i2cWaitForCompletion(I2CDevice device)
 540 {
 541     do {
 542         i2cStateMachine(&busState[device], micros());
 543     } while (busState[device].state != I2C_STATE_STOPPED);
 544 }
 545
 546 bool i2cWriteBuffer(I2CDevice device, uint8_t addr, uint8_t reg, uint8_t len, const uint8_t * data, bool allowRawAccess)
 547 {
 548     // Don't try to access the non-initialized device
 549     if (!busState[device].initialized)
 550         return false;
 551
 552     // Set up write transaction
 553     busState[device].addr = addr << 1;
 554     busState[device].reg = reg;
 555     busState[device].rw = I2C_TXN_WRITE;
 556     busState[device].len = len;
 557     busState[device].buf = CONST_CAST(uint8_t*, data);
 558     busState[device].txnOk = false;
 559     busState[device].state = I2C_STATE_STARTING;
 560     busState[device].allowRawAccess = allowRawAccess;
 561
 562     // Inject I2C_EVENT_START
 563     i2cWaitForCompletion(device);
 564
 565     return busState[device].txnOk;
 566 }
 567
 568 bool i2cWrite(I2CDevice device, uint8_t addr, uint8_t reg, uint8_t data, bool allowRawAccess)
 569 {
 570     return i2cWriteBuffer(device, addr, reg, 1, &data, allowRawAccess);
 571 }
 572
 573 bool i2cRead(I2CDevice device, uint8_t addr, uint8_t reg, uint8_t len, uint8_t* buf, bool allowRawAccess)
 574 {
 575     // Don't try to access the non-initialized device
 576     if (!busState[device].initialized)
 577         return false;
 578
 579     // Set up read transaction
 580     busState[device].addr = addr << 1;
 581     busState[device].reg = reg;
 582     busState[device].rw = I2C_TXN_READ;
 583     busState[device].len = len;
 584     busState[device].buf = buf;
 585     busState[device].txnOk = false;
 586     busState[device].state = I2C_STATE_STARTING;
 587     busState[device].allowRawAccess = allowRawAccess;
 588
 589     // Inject I2C_EVENT_START
 590     i2cWaitForCompletion(device);
 591
 592     return busState[device].txnOk;
 593 }
 594
 595 static void i2cUnstick(IO_t scl, IO_t sda)
 596 {
 597     int i;
 598
 599     IOHi(scl);
 600     IOHi(sda);
 601
 602     IOConfigGPIO(scl, IOCFG_OUT_OD);
 603     IOConfigGPIO(sda, IOCFG_OUT_OD);
 604
 605     // Analog Devices AN-686
 606     // We need 9 clock pulses + STOP condition
 607     for (i = 0; i < 9; i++) {
 608         // Wait for any clock stretching to finish
 609         int timeout = 100;
 610         while (!IORead(scl) && timeout) {
 611             delayMicroseconds(5);
 612             timeout--;
 613         }
 614
 615         // Pull low
 616         IOLo(scl); // Set bus low
 617         delayMicroseconds(5);
 618         IOHi(scl); // Set bus high
 619         delayMicroseconds(5);
 620     }
 621
 622     // Generate a stop condition in case there was none
 623     IOLo(scl);
 624     delayMicroseconds(5);
 625     IOLo(sda);
 626     delayMicroseconds(5);
 627
 628     IOHi(scl); // Set bus scl high
 629     delayMicroseconds(5);
 630     IOHi(sda); // Set bus sda high
 631 }
 632
 633 #endif