src/main/drivers/system_stm32f4xx.c

   1 /*
   2  * This file is part of Cleanflight.
   3  *
   4  * Cleanflight is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Cleanflight is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with Cleanflight.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <stdbool.h>
  19 #include <stdint.h>
  20 #include <string.h>
  21
  22 #include "platform.h"
  23
  24 #include "drivers/accgyro/accgyro_mpu.h"
  25 #include "drivers/exti.h"
  26 #include "drivers/nvic.h"
  27 #include "drivers/system.h"
  28
  29 #include "target/system.h"
  30
  31
  32 void SetSysClock(void);
  33
  34 void enableGPIOPowerUsageAndNoiseReductions(void)
  35 {
  36
  37     RCC_AHB1PeriphClockCmd(
  38         RCC_AHB1Periph_GPIOA |
  39         RCC_AHB1Periph_GPIOB |
  40         RCC_AHB1Periph_GPIOC |
  41         RCC_AHB1Periph_GPIOD |
  42         RCC_AHB1Periph_GPIOE |
  43 #ifdef STM32F40_41xxx
  44         RCC_AHB1Periph_GPIOF |
  45         RCC_AHB1Periph_GPIOG |
  46         RCC_AHB1Periph_GPIOH |
  47         RCC_AHB1Periph_GPIOI |
  48 #endif
  49         RCC_AHB1Periph_CRC |
  50         RCC_AHB1Periph_FLITF |
  51         RCC_AHB1Periph_SRAM1 |
  52         RCC_AHB1Periph_SRAM2 |
  53         RCC_AHB1Periph_BKPSRAM |
  54         RCC_AHB1Periph_DMA1 |
  55         RCC_AHB1Periph_DMA2 |
  56         0, ENABLE
  57     );
  58
  59     RCC_AHB2PeriphClockCmd(0, ENABLE);
  60 #ifdef STM32F40_41xxx
  61     RCC_AHB3PeriphClockCmd(0, ENABLE);
  62 #endif
  63     RCC_APB1PeriphClockCmd(
  64         RCC_APB1Periph_TIM2 |
  65         RCC_APB1Periph_TIM3 |
  66         RCC_APB1Periph_TIM4 |
  67         RCC_APB1Periph_TIM5 |
  68         RCC_APB1Periph_TIM6 |
  69         RCC_APB1Periph_TIM7 |
  70         RCC_APB1Periph_TIM12 |
  71         RCC_APB1Periph_TIM13 |
  72         RCC_APB1Periph_TIM14 |
  73         RCC_APB1Periph_WWDG |
  74         RCC_APB1Periph_SPI2 |
  75         RCC_APB1Periph_SPI3 |
  76         RCC_APB1Periph_USART2 |
  77         RCC_APB1Periph_USART3 |
  78         RCC_APB1Periph_UART4 |
  79         RCC_APB1Periph_UART5 |
  80         RCC_APB1Periph_I2C1 |
  81         RCC_APB1Periph_I2C2 |
  82         RCC_APB1Periph_I2C3 |
  83         // RCC_APB1Periph_CAN1 |
  84         // RCC_APB1Periph_CAN2 |
  85         RCC_APB1Periph_PWR |
  86         // RCC_APB1Periph_DAC |
  87         0, ENABLE);
  88
  89     RCC_APB2PeriphClockCmd(
  90         RCC_APB2Periph_TIM1 |
  91         RCC_APB2Periph_TIM8 |
  92         RCC_APB2Periph_USART1 |
  93         RCC_APB2Periph_USART6 |
  94         RCC_APB2Periph_ADC |
  95         RCC_APB2Periph_ADC1 |
  96         RCC_APB2Periph_ADC2 |
  97         RCC_APB2Periph_ADC3 |
  98         // RCC_APB2Periph_SDIO |
  99         RCC_APB2Periph_SPI1 |
 100         RCC_APB2Periph_SYSCFG |
 101         RCC_APB2Periph_TIM9 |
 102         RCC_APB2Periph_TIM10 |
 103         RCC_APB2Periph_TIM11 |
 104         0, ENABLE);
 105
 106     GPIO_InitTypeDef GPIO_InitStructure;
 107     GPIO_StructInit(&GPIO_InitStructure);
 108     GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
 109
 110     GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 111     GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_11 | GPIO_Pin_12); // leave USB D+/D- alone
 112
 113     GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14); // leave JTAG pins alone
 114     GPIO_Init(GPIOA, &GPIO_InitStructure);
 115
 116     GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 117     GPIO_Init(GPIOB, &GPIO_InitStructure);
 118
 119     GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 120     GPIO_Init(GPIOC, &GPIO_InitStructure);
 121     GPIO_Init(GPIOD, &GPIO_InitStructure);
 122     GPIO_Init(GPIOE, &GPIO_InitStructure);
 123
 124 #ifdef STM32F40_41xxx
 125     GPIO_Init(GPIOF, &GPIO_InitStructure);
 126     GPIO_Init(GPIOG, &GPIO_InitStructure);
 127     GPIO_Init(GPIOH, &GPIO_InitStructure);
 128     GPIO_Init(GPIOI, &GPIO_InitStructure);
 129 #endif
 130
 131 }
 132
 133 bool isMPUSoftReset(void)
 134 {
 135     if (RCC->CSR & RCC_CSR_SFTRSTF)
 136         return true;
 137     else
 138         return false;
 139 }
 140
 141 uint32_t systemBootloaderAddress(void)
 142 {
 143     return 0x1FFF0000;
 144 }
 145
 146 void systemClockSetup(uint8_t cpuUnderclock)
 147 {
 148     (void)cpuUnderclock;
 149     // This is a stub
 150 }
 151
 152 void systemInit(void)
 153 {
 154     SetSysClock();
 155
 156     // Configure NVIC preempt/priority groups
 157     NVIC_PriorityGroupConfig(NVIC_PRIORITY_GROUPING);
 158
 159     // cache RCC->CSR value to use it in isMPUSoftreset() and others
 160     cachedRccCsrValue = RCC->CSR;
 161
 162     /* Accounts for OP Bootloader, set the Vector Table base address as specified in .ld file */
 163     NVIC_SetVectorTable((uint32_t)&isr_vector_table_base, 0x0);
 164     RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, DISABLE);
 165
 166     RCC_ClearFlag();
 167
 168     enableGPIOPowerUsageAndNoiseReductions();
 169
 170     // Init cycle counter
 171     cycleCounterInit();
 172
 173     // SysTick
 174     SysTick_Config(SystemCoreClock / 1000);
 175 }