1 <?xml version=
"1.0" encoding=
"utf-8" standalone=
"no"?>
2 <device schemaVersion=
"1.1"
3 xmlns:
xs=
"http://www.w3.org/2001/XMLSchema-instance"
4 xs:
noNamespaceSchemaLocation=
"CMSIS-SVD_Schema_1_1.xsd">
7 <description>STM32F303
</description>
8 <!-- details about the cpu embedded in the device -->
11 <revision>r1p0
</revision>
12 <endian>little
</endian>
13 <mpuPresent>false
</mpuPresent>
14 <fpuPresent>false
</fpuPresent>
15 <nvicPrioBits>3</nvicPrioBits>
16 <vendorSystickConfig>false
</vendorSystickConfig>
18 <!--Bus Interface Properties-->
19 <!--Cortex-M4 is byte addressable-->
20 <addressUnitBits>8</addressUnitBits>
21 <!--the maximum data bit width accessible within a single transfer-->
23 <!--Register Default Properties-->
25 <resetValue>0x0</resetValue>
26 <resetMask>0xFFFFFFFF</resetMask>
30 <description>General-purpose I/Os
</description>
31 <groupName>GPIO
</groupName>
32 <baseAddress>0x48000000</baseAddress>
36 <usage>registers
</usage>
41 <displayName>MODER
</displayName>
42 <description>GPIO port mode register
</description>
43 <addressOffset>0x0</addressOffset>
45 <access>read-write
</access>
46 <resetValue>0x28000000</resetValue>
50 <description>Port x configuration bits (y =
52 <bitOffset>30</bitOffset>
53 <bitWidth>2</bitWidth>
57 <description>Port x configuration bits (y =
59 <bitOffset>28</bitOffset>
60 <bitWidth>2</bitWidth>
64 <description>Port x configuration bits (y =
66 <bitOffset>26</bitOffset>
67 <bitWidth>2</bitWidth>
71 <description>Port x configuration bits (y =
73 <bitOffset>24</bitOffset>
74 <bitWidth>2</bitWidth>
78 <description>Port x configuration bits (y =
80 <bitOffset>22</bitOffset>
81 <bitWidth>2</bitWidth>
85 <description>Port x configuration bits (y =
87 <bitOffset>20</bitOffset>
88 <bitWidth>2</bitWidth>
92 <description>Port x configuration bits (y =
94 <bitOffset>18</bitOffset>
95 <bitWidth>2</bitWidth>
99 <description>Port x configuration bits (y =
101 <bitOffset>16</bitOffset>
102 <bitWidth>2</bitWidth>
106 <description>Port x configuration bits (y =
108 <bitOffset>14</bitOffset>
109 <bitWidth>2</bitWidth>
113 <description>Port x configuration bits (y =
115 <bitOffset>12</bitOffset>
116 <bitWidth>2</bitWidth>
120 <description>Port x configuration bits (y =
122 <bitOffset>10</bitOffset>
123 <bitWidth>2</bitWidth>
127 <description>Port x configuration bits (y =
129 <bitOffset>8</bitOffset>
130 <bitWidth>2</bitWidth>
134 <description>Port x configuration bits (y =
136 <bitOffset>6</bitOffset>
137 <bitWidth>2</bitWidth>
141 <description>Port x configuration bits (y =
143 <bitOffset>4</bitOffset>
144 <bitWidth>2</bitWidth>
148 <description>Port x configuration bits (y =
150 <bitOffset>2</bitOffset>
151 <bitWidth>2</bitWidth>
155 <description>Port x configuration bits (y =
157 <bitOffset>0</bitOffset>
158 <bitWidth>2</bitWidth>
164 <displayName>OTYPER
</displayName>
165 <description>GPIO port output type register
</description>
166 <addressOffset>0x4</addressOffset>
168 <access>read-write
</access>
169 <resetValue>0x00000000</resetValue>
173 <description>Port x configuration bits (y =
175 <bitOffset>15</bitOffset>
176 <bitWidth>1</bitWidth>
180 <description>Port x configuration bits (y =
182 <bitOffset>14</bitOffset>
183 <bitWidth>1</bitWidth>
187 <description>Port x configuration bits (y =
189 <bitOffset>13</bitOffset>
190 <bitWidth>1</bitWidth>
194 <description>Port x configuration bits (y =
196 <bitOffset>12</bitOffset>
197 <bitWidth>1</bitWidth>
201 <description>Port x configuration bits (y =
203 <bitOffset>11</bitOffset>
204 <bitWidth>1</bitWidth>
208 <description>Port x configuration bits (y =
210 <bitOffset>10</bitOffset>
211 <bitWidth>1</bitWidth>
215 <description>Port x configuration bits (y =
217 <bitOffset>9</bitOffset>
218 <bitWidth>1</bitWidth>
222 <description>Port x configuration bits (y =
224 <bitOffset>8</bitOffset>
225 <bitWidth>1</bitWidth>
229 <description>Port x configuration bits (y =
231 <bitOffset>7</bitOffset>
232 <bitWidth>1</bitWidth>
236 <description>Port x configuration bits (y =
238 <bitOffset>6</bitOffset>
239 <bitWidth>1</bitWidth>
243 <description>Port x configuration bits (y =
245 <bitOffset>5</bitOffset>
246 <bitWidth>1</bitWidth>
250 <description>Port x configuration bits (y =
252 <bitOffset>4</bitOffset>
253 <bitWidth>1</bitWidth>
257 <description>Port x configuration bits (y =
259 <bitOffset>3</bitOffset>
260 <bitWidth>1</bitWidth>
264 <description>Port x configuration bits (y =
266 <bitOffset>2</bitOffset>
267 <bitWidth>1</bitWidth>
271 <description>Port x configuration bits (y =
273 <bitOffset>1</bitOffset>
274 <bitWidth>1</bitWidth>
278 <description>Port x configuration bits (y =
280 <bitOffset>0</bitOffset>
281 <bitWidth>1</bitWidth>
287 <displayName>OSPEEDR
</displayName>
288 <description>GPIO port output speed
289 register
</description>
290 <addressOffset>0x8</addressOffset>
292 <access>read-write
</access>
293 <resetValue>0x00000000</resetValue>
296 <name>OSPEEDR15
</name>
297 <description>Port x configuration bits (y =
299 <bitOffset>30</bitOffset>
300 <bitWidth>2</bitWidth>
303 <name>OSPEEDR14
</name>
304 <description>Port x configuration bits (y =
306 <bitOffset>28</bitOffset>
307 <bitWidth>2</bitWidth>
310 <name>OSPEEDR13
</name>
311 <description>Port x configuration bits (y =
313 <bitOffset>26</bitOffset>
314 <bitWidth>2</bitWidth>
317 <name>OSPEEDR12
</name>
318 <description>Port x configuration bits (y =
320 <bitOffset>24</bitOffset>
321 <bitWidth>2</bitWidth>
324 <name>OSPEEDR11
</name>
325 <description>Port x configuration bits (y =
327 <bitOffset>22</bitOffset>
328 <bitWidth>2</bitWidth>
331 <name>OSPEEDR10
</name>
332 <description>Port x configuration bits (y =
334 <bitOffset>20</bitOffset>
335 <bitWidth>2</bitWidth>
338 <name>OSPEEDR9
</name>
339 <description>Port x configuration bits (y =
341 <bitOffset>18</bitOffset>
342 <bitWidth>2</bitWidth>
345 <name>OSPEEDR8
</name>
346 <description>Port x configuration bits (y =
348 <bitOffset>16</bitOffset>
349 <bitWidth>2</bitWidth>
352 <name>OSPEEDR7
</name>
353 <description>Port x configuration bits (y =
355 <bitOffset>14</bitOffset>
356 <bitWidth>2</bitWidth>
359 <name>OSPEEDR6
</name>
360 <description>Port x configuration bits (y =
362 <bitOffset>12</bitOffset>
363 <bitWidth>2</bitWidth>
366 <name>OSPEEDR5
</name>
367 <description>Port x configuration bits (y =
369 <bitOffset>10</bitOffset>
370 <bitWidth>2</bitWidth>
373 <name>OSPEEDR4
</name>
374 <description>Port x configuration bits (y =
376 <bitOffset>8</bitOffset>
377 <bitWidth>2</bitWidth>
380 <name>OSPEEDR3
</name>
381 <description>Port x configuration bits (y =
383 <bitOffset>6</bitOffset>
384 <bitWidth>2</bitWidth>
387 <name>OSPEEDR2
</name>
388 <description>Port x configuration bits (y =
390 <bitOffset>4</bitOffset>
391 <bitWidth>2</bitWidth>
394 <name>OSPEEDR1
</name>
395 <description>Port x configuration bits (y =
397 <bitOffset>2</bitOffset>
398 <bitWidth>2</bitWidth>
401 <name>OSPEEDR0
</name>
402 <description>Port x configuration bits (y =
404 <bitOffset>0</bitOffset>
405 <bitWidth>2</bitWidth>
411 <displayName>PUPDR
</displayName>
412 <description>GPIO port pull-up/pull-down
413 register
</description>
414 <addressOffset>0xC</addressOffset>
416 <access>read-write
</access>
417 <resetValue>0x24000000</resetValue>
421 <description>Port x configuration bits (y =
423 <bitOffset>30</bitOffset>
424 <bitWidth>2</bitWidth>
428 <description>Port x configuration bits (y =
430 <bitOffset>28</bitOffset>
431 <bitWidth>2</bitWidth>
435 <description>Port x configuration bits (y =
437 <bitOffset>26</bitOffset>
438 <bitWidth>2</bitWidth>
442 <description>Port x configuration bits (y =
444 <bitOffset>24</bitOffset>
445 <bitWidth>2</bitWidth>
449 <description>Port x configuration bits (y =
451 <bitOffset>22</bitOffset>
452 <bitWidth>2</bitWidth>
456 <description>Port x configuration bits (y =
458 <bitOffset>20</bitOffset>
459 <bitWidth>2</bitWidth>
463 <description>Port x configuration bits (y =
465 <bitOffset>18</bitOffset>
466 <bitWidth>2</bitWidth>
470 <description>Port x configuration bits (y =
472 <bitOffset>16</bitOffset>
473 <bitWidth>2</bitWidth>
477 <description>Port x configuration bits (y =
479 <bitOffset>14</bitOffset>
480 <bitWidth>2</bitWidth>
484 <description>Port x configuration bits (y =
486 <bitOffset>12</bitOffset>
487 <bitWidth>2</bitWidth>
491 <description>Port x configuration bits (y =
493 <bitOffset>10</bitOffset>
494 <bitWidth>2</bitWidth>
498 <description>Port x configuration bits (y =
500 <bitOffset>8</bitOffset>
501 <bitWidth>2</bitWidth>
505 <description>Port x configuration bits (y =
507 <bitOffset>6</bitOffset>
508 <bitWidth>2</bitWidth>
512 <description>Port x configuration bits (y =
514 <bitOffset>4</bitOffset>
515 <bitWidth>2</bitWidth>
519 <description>Port x configuration bits (y =
521 <bitOffset>2</bitOffset>
522 <bitWidth>2</bitWidth>
526 <description>Port x configuration bits (y =
528 <bitOffset>0</bitOffset>
529 <bitWidth>2</bitWidth>
535 <displayName>IDR
</displayName>
536 <description>GPIO port input data register
</description>
537 <addressOffset>0x10</addressOffset>
539 <access>read-only
</access>
540 <resetValue>0x00000000</resetValue>
544 <description>Port input data (y =
546 <bitOffset>15</bitOffset>
547 <bitWidth>1</bitWidth>
551 <description>Port input data (y =
553 <bitOffset>14</bitOffset>
554 <bitWidth>1</bitWidth>
558 <description>Port input data (y =
560 <bitOffset>13</bitOffset>
561 <bitWidth>1</bitWidth>
565 <description>Port input data (y =
567 <bitOffset>12</bitOffset>
568 <bitWidth>1</bitWidth>
572 <description>Port input data (y =
574 <bitOffset>11</bitOffset>
575 <bitWidth>1</bitWidth>
579 <description>Port input data (y =
581 <bitOffset>10</bitOffset>
582 <bitWidth>1</bitWidth>
586 <description>Port input data (y =
588 <bitOffset>9</bitOffset>
589 <bitWidth>1</bitWidth>
593 <description>Port input data (y =
595 <bitOffset>8</bitOffset>
596 <bitWidth>1</bitWidth>
600 <description>Port input data (y =
602 <bitOffset>7</bitOffset>
603 <bitWidth>1</bitWidth>
607 <description>Port input data (y =
609 <bitOffset>6</bitOffset>
610 <bitWidth>1</bitWidth>
614 <description>Port input data (y =
616 <bitOffset>5</bitOffset>
617 <bitWidth>1</bitWidth>
621 <description>Port input data (y =
623 <bitOffset>4</bitOffset>
624 <bitWidth>1</bitWidth>
628 <description>Port input data (y =
630 <bitOffset>3</bitOffset>
631 <bitWidth>1</bitWidth>
635 <description>Port input data (y =
637 <bitOffset>2</bitOffset>
638 <bitWidth>1</bitWidth>
642 <description>Port input data (y =
644 <bitOffset>1</bitOffset>
645 <bitWidth>1</bitWidth>
649 <description>Port input data (y =
651 <bitOffset>0</bitOffset>
652 <bitWidth>1</bitWidth>
658 <displayName>ODR
</displayName>
659 <description>GPIO port output data register
</description>
660 <addressOffset>0x14</addressOffset>
662 <access>read-write
</access>
663 <resetValue>0x00000000</resetValue>
667 <description>Port output data (y =
669 <bitOffset>15</bitOffset>
670 <bitWidth>1</bitWidth>
674 <description>Port output data (y =
676 <bitOffset>14</bitOffset>
677 <bitWidth>1</bitWidth>
681 <description>Port output data (y =
683 <bitOffset>13</bitOffset>
684 <bitWidth>1</bitWidth>
688 <description>Port output data (y =
690 <bitOffset>12</bitOffset>
691 <bitWidth>1</bitWidth>
695 <description>Port output data (y =
697 <bitOffset>11</bitOffset>
698 <bitWidth>1</bitWidth>
702 <description>Port output data (y =
704 <bitOffset>10</bitOffset>
705 <bitWidth>1</bitWidth>
709 <description>Port output data (y =
711 <bitOffset>9</bitOffset>
712 <bitWidth>1</bitWidth>
716 <description>Port output data (y =
718 <bitOffset>8</bitOffset>
719 <bitWidth>1</bitWidth>
723 <description>Port output data (y =
725 <bitOffset>7</bitOffset>
726 <bitWidth>1</bitWidth>
730 <description>Port output data (y =
732 <bitOffset>6</bitOffset>
733 <bitWidth>1</bitWidth>
737 <description>Port output data (y =
739 <bitOffset>5</bitOffset>
740 <bitWidth>1</bitWidth>
744 <description>Port output data (y =
746 <bitOffset>4</bitOffset>
747 <bitWidth>1</bitWidth>
751 <description>Port output data (y =
753 <bitOffset>3</bitOffset>
754 <bitWidth>1</bitWidth>
758 <description>Port output data (y =
760 <bitOffset>2</bitOffset>
761 <bitWidth>1</bitWidth>
765 <description>Port output data (y =
767 <bitOffset>1</bitOffset>
768 <bitWidth>1</bitWidth>
772 <description>Port output data (y =
774 <bitOffset>0</bitOffset>
775 <bitWidth>1</bitWidth>
781 <displayName>BSRR
</displayName>
782 <description>GPIO port bit set/reset
783 register
</description>
784 <addressOffset>0x18</addressOffset>
786 <access>write-only
</access>
787 <resetValue>0x00000000</resetValue>
791 <description>Port x reset bit y (y =
793 <bitOffset>31</bitOffset>
794 <bitWidth>1</bitWidth>
798 <description>Port x reset bit y (y =
800 <bitOffset>30</bitOffset>
801 <bitWidth>1</bitWidth>
805 <description>Port x reset bit y (y =
807 <bitOffset>29</bitOffset>
808 <bitWidth>1</bitWidth>
812 <description>Port x reset bit y (y =
814 <bitOffset>28</bitOffset>
815 <bitWidth>1</bitWidth>
819 <description>Port x reset bit y (y =
821 <bitOffset>27</bitOffset>
822 <bitWidth>1</bitWidth>
826 <description>Port x reset bit y (y =
828 <bitOffset>26</bitOffset>
829 <bitWidth>1</bitWidth>
833 <description>Port x reset bit y (y =
835 <bitOffset>25</bitOffset>
836 <bitWidth>1</bitWidth>
840 <description>Port x reset bit y (y =
842 <bitOffset>24</bitOffset>
843 <bitWidth>1</bitWidth>
847 <description>Port x reset bit y (y =
849 <bitOffset>23</bitOffset>
850 <bitWidth>1</bitWidth>
854 <description>Port x reset bit y (y =
856 <bitOffset>22</bitOffset>
857 <bitWidth>1</bitWidth>
861 <description>Port x reset bit y (y =
863 <bitOffset>21</bitOffset>
864 <bitWidth>1</bitWidth>
868 <description>Port x reset bit y (y =
870 <bitOffset>20</bitOffset>
871 <bitWidth>1</bitWidth>
875 <description>Port x reset bit y (y =
877 <bitOffset>19</bitOffset>
878 <bitWidth>1</bitWidth>
882 <description>Port x reset bit y (y =
884 <bitOffset>18</bitOffset>
885 <bitWidth>1</bitWidth>
889 <description>Port x reset bit y (y =
891 <bitOffset>17</bitOffset>
892 <bitWidth>1</bitWidth>
896 <description>Port x set bit y (y=
898 <bitOffset>16</bitOffset>
899 <bitWidth>1</bitWidth>
903 <description>Port x set bit y (y=
905 <bitOffset>15</bitOffset>
906 <bitWidth>1</bitWidth>
910 <description>Port x set bit y (y=
912 <bitOffset>14</bitOffset>
913 <bitWidth>1</bitWidth>
917 <description>Port x set bit y (y=
919 <bitOffset>13</bitOffset>
920 <bitWidth>1</bitWidth>
924 <description>Port x set bit y (y=
926 <bitOffset>12</bitOffset>
927 <bitWidth>1</bitWidth>
931 <description>Port x set bit y (y=
933 <bitOffset>11</bitOffset>
934 <bitWidth>1</bitWidth>
938 <description>Port x set bit y (y=
940 <bitOffset>10</bitOffset>
941 <bitWidth>1</bitWidth>
945 <description>Port x set bit y (y=
947 <bitOffset>9</bitOffset>
948 <bitWidth>1</bitWidth>
952 <description>Port x set bit y (y=
954 <bitOffset>8</bitOffset>
955 <bitWidth>1</bitWidth>
959 <description>Port x set bit y (y=
961 <bitOffset>7</bitOffset>
962 <bitWidth>1</bitWidth>
966 <description>Port x set bit y (y=
968 <bitOffset>6</bitOffset>
969 <bitWidth>1</bitWidth>
973 <description>Port x set bit y (y=
975 <bitOffset>5</bitOffset>
976 <bitWidth>1</bitWidth>
980 <description>Port x set bit y (y=
982 <bitOffset>4</bitOffset>
983 <bitWidth>1</bitWidth>
987 <description>Port x set bit y (y=
989 <bitOffset>3</bitOffset>
990 <bitWidth>1</bitWidth>
994 <description>Port x set bit y (y=
996 <bitOffset>2</bitOffset>
997 <bitWidth>1</bitWidth>
1001 <description>Port x set bit y (y=
1002 0.
.15)
</description>
1003 <bitOffset>1</bitOffset>
1004 <bitWidth>1</bitWidth>
1008 <description>Port x set bit y (y=
1009 0.
.15)
</description>
1010 <bitOffset>0</bitOffset>
1011 <bitWidth>1</bitWidth>
1017 <displayName>LCKR
</displayName>
1018 <description>GPIO port configuration lock
1019 register
</description>
1020 <addressOffset>0x1C</addressOffset>
1022 <access>read-write
</access>
1023 <resetValue>0x00000000</resetValue>
1027 <description>Lok Key
</description>
1028 <bitOffset>16</bitOffset>
1029 <bitWidth>1</bitWidth>
1033 <description>Port x lock bit y (y=
1034 0.
.15)
</description>
1035 <bitOffset>15</bitOffset>
1036 <bitWidth>1</bitWidth>
1040 <description>Port x lock bit y (y=
1041 0.
.15)
</description>
1042 <bitOffset>14</bitOffset>
1043 <bitWidth>1</bitWidth>
1047 <description>Port x lock bit y (y=
1048 0.
.15)
</description>
1049 <bitOffset>13</bitOffset>
1050 <bitWidth>1</bitWidth>
1054 <description>Port x lock bit y (y=
1055 0.
.15)
</description>
1056 <bitOffset>12</bitOffset>
1057 <bitWidth>1</bitWidth>
1061 <description>Port x lock bit y (y=
1062 0.
.15)
</description>
1063 <bitOffset>11</bitOffset>
1064 <bitWidth>1</bitWidth>
1068 <description>Port x lock bit y (y=
1069 0.
.15)
</description>
1070 <bitOffset>10</bitOffset>
1071 <bitWidth>1</bitWidth>
1075 <description>Port x lock bit y (y=
1076 0.
.15)
</description>
1077 <bitOffset>9</bitOffset>
1078 <bitWidth>1</bitWidth>
1082 <description>Port x lock bit y (y=
1083 0.
.15)
</description>
1084 <bitOffset>8</bitOffset>
1085 <bitWidth>1</bitWidth>
1089 <description>Port x lock bit y (y=
1090 0.
.15)
</description>
1091 <bitOffset>7</bitOffset>
1092 <bitWidth>1</bitWidth>
1096 <description>Port x lock bit y (y=
1097 0.
.15)
</description>
1098 <bitOffset>6</bitOffset>
1099 <bitWidth>1</bitWidth>
1103 <description>Port x lock bit y (y=
1104 0.
.15)
</description>
1105 <bitOffset>5</bitOffset>
1106 <bitWidth>1</bitWidth>
1110 <description>Port x lock bit y (y=
1111 0.
.15)
</description>
1112 <bitOffset>4</bitOffset>
1113 <bitWidth>1</bitWidth>
1117 <description>Port x lock bit y (y=
1118 0.
.15)
</description>
1119 <bitOffset>3</bitOffset>
1120 <bitWidth>1</bitWidth>
1124 <description>Port x lock bit y (y=
1125 0.
.15)
</description>
1126 <bitOffset>2</bitOffset>
1127 <bitWidth>1</bitWidth>
1131 <description>Port x lock bit y (y=
1132 0.
.15)
</description>
1133 <bitOffset>1</bitOffset>
1134 <bitWidth>1</bitWidth>
1138 <description>Port x lock bit y (y=
1139 0.
.15)
</description>
1140 <bitOffset>0</bitOffset>
1141 <bitWidth>1</bitWidth>
1147 <displayName>AFRL
</displayName>
1148 <description>GPIO alternate function low
1149 register
</description>
1150 <addressOffset>0x20</addressOffset>
1152 <access>read-write
</access>
1153 <resetValue>0x00000000</resetValue>
1157 <description>Alternate function selection for port x
1158 bit y (y =
0.
.7)
</description>
1159 <bitOffset>28</bitOffset>
1160 <bitWidth>4</bitWidth>
1164 <description>Alternate function selection for port x
1165 bit y (y =
0.
.7)
</description>
1166 <bitOffset>24</bitOffset>
1167 <bitWidth>4</bitWidth>
1171 <description>Alternate function selection for port x
1172 bit y (y =
0.
.7)
</description>
1173 <bitOffset>20</bitOffset>
1174 <bitWidth>4</bitWidth>
1178 <description>Alternate function selection for port x
1179 bit y (y =
0.
.7)
</description>
1180 <bitOffset>16</bitOffset>
1181 <bitWidth>4</bitWidth>
1185 <description>Alternate function selection for port x
1186 bit y (y =
0.
.7)
</description>
1187 <bitOffset>12</bitOffset>
1188 <bitWidth>4</bitWidth>
1192 <description>Alternate function selection for port x
1193 bit y (y =
0.
.7)
</description>
1194 <bitOffset>8</bitOffset>
1195 <bitWidth>4</bitWidth>
1199 <description>Alternate function selection for port x
1200 bit y (y =
0.
.7)
</description>
1201 <bitOffset>4</bitOffset>
1202 <bitWidth>4</bitWidth>
1206 <description>Alternate function selection for port x
1207 bit y (y =
0.
.7)
</description>
1208 <bitOffset>0</bitOffset>
1209 <bitWidth>4</bitWidth>
1215 <displayName>AFRH
</displayName>
1216 <description>GPIO alternate function high
1217 register
</description>
1218 <addressOffset>0x24</addressOffset>
1220 <access>read-write
</access>
1221 <resetValue>0x00000000</resetValue>
1225 <description>Alternate function selection for port x
1226 bit y (y =
8.
.15)
</description>
1227 <bitOffset>28</bitOffset>
1228 <bitWidth>4</bitWidth>
1232 <description>Alternate function selection for port x
1233 bit y (y =
8.
.15)
</description>
1234 <bitOffset>24</bitOffset>
1235 <bitWidth>4</bitWidth>
1239 <description>Alternate function selection for port x
1240 bit y (y =
8.
.15)
</description>
1241 <bitOffset>20</bitOffset>
1242 <bitWidth>4</bitWidth>
1246 <description>Alternate function selection for port x
1247 bit y (y =
8.
.15)
</description>
1248 <bitOffset>16</bitOffset>
1249 <bitWidth>4</bitWidth>
1253 <description>Alternate function selection for port x
1254 bit y (y =
8.
.15)
</description>
1255 <bitOffset>12</bitOffset>
1256 <bitWidth>4</bitWidth>
1260 <description>Alternate function selection for port x
1261 bit y (y =
8.
.15)
</description>
1262 <bitOffset>8</bitOffset>
1263 <bitWidth>4</bitWidth>
1267 <description>Alternate function selection for port x
1268 bit y (y =
8.
.15)
</description>
1269 <bitOffset>4</bitOffset>
1270 <bitWidth>4</bitWidth>
1274 <description>Alternate function selection for port x
1275 bit y (y =
8.
.15)
</description>
1276 <bitOffset>0</bitOffset>
1277 <bitWidth>4</bitWidth>
1283 <displayName>BRR
</displayName>
1284 <description>Port bit reset register
</description>
1285 <addressOffset>0x28</addressOffset>
1287 <access>write-only
</access>
1288 <resetValue>0x00000000</resetValue>
1292 <description>Port x Reset bit y
</description>
1293 <bitOffset>0</bitOffset>
1294 <bitWidth>1</bitWidth>
1298 <description>Port x Reset bit y
</description>
1299 <bitOffset>1</bitOffset>
1300 <bitWidth>1</bitWidth>
1304 <description>Port x Reset bit y
</description>
1305 <bitOffset>2</bitOffset>
1306 <bitWidth>1</bitWidth>
1310 <description>Port x Reset bit y
</description>
1311 <bitOffset>3</bitOffset>
1312 <bitWidth>1</bitWidth>
1316 <description>Port x Reset bit y
</description>
1317 <bitOffset>4</bitOffset>
1318 <bitWidth>1</bitWidth>
1322 <description>Port x Reset bit y
</description>
1323 <bitOffset>5</bitOffset>
1324 <bitWidth>1</bitWidth>
1328 <description>Port x Reset bit y
</description>
1329 <bitOffset>6</bitOffset>
1330 <bitWidth>1</bitWidth>
1334 <description>Port x Reset bit y
</description>
1335 <bitOffset>7</bitOffset>
1336 <bitWidth>1</bitWidth>
1340 <description>Port x Reset bit y
</description>
1341 <bitOffset>8</bitOffset>
1342 <bitWidth>1</bitWidth>
1346 <description>Port x Reset bit y
</description>
1347 <bitOffset>9</bitOffset>
1348 <bitWidth>1</bitWidth>
1352 <description>Port x Reset bit y
</description>
1353 <bitOffset>10</bitOffset>
1354 <bitWidth>1</bitWidth>
1358 <description>Port x Reset bit y
</description>
1359 <bitOffset>11</bitOffset>
1360 <bitWidth>1</bitWidth>
1364 <description>Port x Reset bit y
</description>
1365 <bitOffset>12</bitOffset>
1366 <bitWidth>1</bitWidth>
1370 <description>Port x Reset bit y
</description>
1371 <bitOffset>13</bitOffset>
1372 <bitWidth>1</bitWidth>
1376 <description>Port x Reset bit y
</description>
1377 <bitOffset>14</bitOffset>
1378 <bitWidth>1</bitWidth>
1382 <description>Port x Reset bit y
</description>
1383 <bitOffset>15</bitOffset>
1384 <bitWidth>1</bitWidth>
1392 <description>General-purpose I/Os
</description>
1393 <groupName>GPIO
</groupName>
1394 <baseAddress>0x48000400</baseAddress>
1396 <offset>0x0</offset>
1398 <usage>registers
</usage>
1403 <displayName>MODER
</displayName>
1404 <description>GPIO port mode register
</description>
1405 <addressOffset>0x0</addressOffset>
1407 <access>read-write
</access>
1408 <resetValue>0x00000000</resetValue>
1411 <name>MODER15
</name>
1412 <description>Port x configuration bits (y =
1413 0.
.15)
</description>
1414 <bitOffset>30</bitOffset>
1415 <bitWidth>2</bitWidth>
1418 <name>MODER14
</name>
1419 <description>Port x configuration bits (y =
1420 0.
.15)
</description>
1421 <bitOffset>28</bitOffset>
1422 <bitWidth>2</bitWidth>
1425 <name>MODER13
</name>
1426 <description>Port x configuration bits (y =
1427 0.
.15)
</description>
1428 <bitOffset>26</bitOffset>
1429 <bitWidth>2</bitWidth>
1432 <name>MODER12
</name>
1433 <description>Port x configuration bits (y =
1434 0.
.15)
</description>
1435 <bitOffset>24</bitOffset>
1436 <bitWidth>2</bitWidth>
1439 <name>MODER11
</name>
1440 <description>Port x configuration bits (y =
1441 0.
.15)
</description>
1442 <bitOffset>22</bitOffset>
1443 <bitWidth>2</bitWidth>
1446 <name>MODER10
</name>
1447 <description>Port x configuration bits (y =
1448 0.
.15)
</description>
1449 <bitOffset>20</bitOffset>
1450 <bitWidth>2</bitWidth>
1454 <description>Port x configuration bits (y =
1455 0.
.15)
</description>
1456 <bitOffset>18</bitOffset>
1457 <bitWidth>2</bitWidth>
1461 <description>Port x configuration bits (y =
1462 0.
.15)
</description>
1463 <bitOffset>16</bitOffset>
1464 <bitWidth>2</bitWidth>
1468 <description>Port x configuration bits (y =
1469 0.
.15)
</description>
1470 <bitOffset>14</bitOffset>
1471 <bitWidth>2</bitWidth>
1475 <description>Port x configuration bits (y =
1476 0.
.15)
</description>
1477 <bitOffset>12</bitOffset>
1478 <bitWidth>2</bitWidth>
1482 <description>Port x configuration bits (y =
1483 0.
.15)
</description>
1484 <bitOffset>10</bitOffset>
1485 <bitWidth>2</bitWidth>
1489 <description>Port x configuration bits (y =
1490 0.
.15)
</description>
1491 <bitOffset>8</bitOffset>
1492 <bitWidth>2</bitWidth>
1496 <description>Port x configuration bits (y =
1497 0.
.15)
</description>
1498 <bitOffset>6</bitOffset>
1499 <bitWidth>2</bitWidth>
1503 <description>Port x configuration bits (y =
1504 0.
.15)
</description>
1505 <bitOffset>4</bitOffset>
1506 <bitWidth>2</bitWidth>
1510 <description>Port x configuration bits (y =
1511 0.
.15)
</description>
1512 <bitOffset>2</bitOffset>
1513 <bitWidth>2</bitWidth>
1517 <description>Port x configuration bits (y =
1518 0.
.15)
</description>
1519 <bitOffset>0</bitOffset>
1520 <bitWidth>2</bitWidth>
1526 <displayName>OTYPER
</displayName>
1527 <description>GPIO port output type register
</description>
1528 <addressOffset>0x4</addressOffset>
1530 <access>read-write
</access>
1531 <resetValue>0x00000000</resetValue>
1535 <description>Port x configuration bit
1537 <bitOffset>15</bitOffset>
1538 <bitWidth>1</bitWidth>
1542 <description>Port x configuration bit
1544 <bitOffset>14</bitOffset>
1545 <bitWidth>1</bitWidth>
1549 <description>Port x configuration bit
1551 <bitOffset>13</bitOffset>
1552 <bitWidth>1</bitWidth>
1556 <description>Port x configuration bit
1558 <bitOffset>12</bitOffset>
1559 <bitWidth>1</bitWidth>
1563 <description>Port x configuration bit
1565 <bitOffset>11</bitOffset>
1566 <bitWidth>1</bitWidth>
1570 <description>Port x configuration bit
1572 <bitOffset>10</bitOffset>
1573 <bitWidth>1</bitWidth>
1577 <description>Port x configuration bit
9</description>
1578 <bitOffset>9</bitOffset>
1579 <bitWidth>1</bitWidth>
1583 <description>Port x configuration bit
8</description>
1584 <bitOffset>8</bitOffset>
1585 <bitWidth>1</bitWidth>
1589 <description>Port x configuration bit
7</description>
1590 <bitOffset>7</bitOffset>
1591 <bitWidth>1</bitWidth>
1595 <description>Port x configuration bit
6</description>
1596 <bitOffset>6</bitOffset>
1597 <bitWidth>1</bitWidth>
1601 <description>Port x configuration bit
5</description>
1602 <bitOffset>5</bitOffset>
1603 <bitWidth>1</bitWidth>
1607 <description>Port x configuration bit
4</description>
1608 <bitOffset>4</bitOffset>
1609 <bitWidth>1</bitWidth>
1613 <description>Port x configuration bit
3</description>
1614 <bitOffset>3</bitOffset>
1615 <bitWidth>1</bitWidth>
1619 <description>Port x configuration bit
2</description>
1620 <bitOffset>2</bitOffset>
1621 <bitWidth>1</bitWidth>
1625 <description>Port x configuration bit
1</description>
1626 <bitOffset>1</bitOffset>
1627 <bitWidth>1</bitWidth>
1631 <description>Port x configuration bit
0</description>
1632 <bitOffset>0</bitOffset>
1633 <bitWidth>1</bitWidth>
1638 <name>OSPEEDR
</name>
1639 <displayName>OSPEEDR
</displayName>
1640 <description>GPIO port output speed
1641 register
</description>
1642 <addressOffset>0x8</addressOffset>
1644 <access>read-write
</access>
1645 <resetValue>0x00000000</resetValue>
1648 <name>OSPEEDR15
</name>
1649 <description>Port x configuration bits (y =
1650 0.
.15)
</description>
1651 <bitOffset>30</bitOffset>
1652 <bitWidth>2</bitWidth>
1655 <name>OSPEEDR14
</name>
1656 <description>Port x configuration bits (y =
1657 0.
.15)
</description>
1658 <bitOffset>28</bitOffset>
1659 <bitWidth>2</bitWidth>
1662 <name>OSPEEDR13
</name>
1663 <description>Port x configuration bits (y =
1664 0.
.15)
</description>
1665 <bitOffset>26</bitOffset>
1666 <bitWidth>2</bitWidth>
1669 <name>OSPEEDR12
</name>
1670 <description>Port x configuration bits (y =
1671 0.
.15)
</description>
1672 <bitOffset>24</bitOffset>
1673 <bitWidth>2</bitWidth>
1676 <name>OSPEEDR11
</name>
1677 <description>Port x configuration bits (y =
1678 0.
.15)
</description>
1679 <bitOffset>22</bitOffset>
1680 <bitWidth>2</bitWidth>
1683 <name>OSPEEDR10
</name>
1684 <description>Port x configuration bits (y =
1685 0.
.15)
</description>
1686 <bitOffset>20</bitOffset>
1687 <bitWidth>2</bitWidth>
1690 <name>OSPEEDR9
</name>
1691 <description>Port x configuration bits (y =
1692 0.
.15)
</description>
1693 <bitOffset>18</bitOffset>
1694 <bitWidth>2</bitWidth>
1697 <name>OSPEEDR8
</name>
1698 <description>Port x configuration bits (y =
1699 0.
.15)
</description>
1700 <bitOffset>16</bitOffset>
1701 <bitWidth>2</bitWidth>
1704 <name>OSPEEDR7
</name>
1705 <description>Port x configuration bits (y =
1706 0.
.15)
</description>
1707 <bitOffset>14</bitOffset>
1708 <bitWidth>2</bitWidth>
1711 <name>OSPEEDR6
</name>
1712 <description>Port x configuration bits (y =
1713 0.
.15)
</description>
1714 <bitOffset>12</bitOffset>
1715 <bitWidth>2</bitWidth>
1718 <name>OSPEEDR5
</name>
1719 <description>Port x configuration bits (y =
1720 0.
.15)
</description>
1721 <bitOffset>10</bitOffset>
1722 <bitWidth>2</bitWidth>
1725 <name>OSPEEDR4
</name>
1726 <description>Port x configuration bits (y =
1727 0.
.15)
</description>
1728 <bitOffset>8</bitOffset>
1729 <bitWidth>2</bitWidth>
1732 <name>OSPEEDR3
</name>
1733 <description>Port x configuration bits (y =
1734 0.
.15)
</description>
1735 <bitOffset>6</bitOffset>
1736 <bitWidth>2</bitWidth>
1739 <name>OSPEEDR2
</name>
1740 <description>Port x configuration bits (y =
1741 0.
.15)
</description>
1742 <bitOffset>4</bitOffset>
1743 <bitWidth>2</bitWidth>
1746 <name>OSPEEDR1
</name>
1747 <description>Port x configuration bits (y =
1748 0.
.15)
</description>
1749 <bitOffset>2</bitOffset>
1750 <bitWidth>2</bitWidth>
1753 <name>OSPEEDR0
</name>
1754 <description>Port x configuration bits (y =
1755 0.
.15)
</description>
1756 <bitOffset>0</bitOffset>
1757 <bitWidth>2</bitWidth>
1763 <displayName>PUPDR
</displayName>
1764 <description>GPIO port pull-up/pull-down
1765 register
</description>
1766 <addressOffset>0xC</addressOffset>
1768 <access>read-write
</access>
1769 <resetValue>0x00000000</resetValue>
1772 <name>PUPDR15
</name>
1773 <description>Port x configuration bits (y =
1774 0.
.15)
</description>
1775 <bitOffset>30</bitOffset>
1776 <bitWidth>2</bitWidth>
1779 <name>PUPDR14
</name>
1780 <description>Port x configuration bits (y =
1781 0.
.15)
</description>
1782 <bitOffset>28</bitOffset>
1783 <bitWidth>2</bitWidth>
1786 <name>PUPDR13
</name>
1787 <description>Port x configuration bits (y =
1788 0.
.15)
</description>
1789 <bitOffset>26</bitOffset>
1790 <bitWidth>2</bitWidth>
1793 <name>PUPDR12
</name>
1794 <description>Port x configuration bits (y =
1795 0.
.15)
</description>
1796 <bitOffset>24</bitOffset>
1797 <bitWidth>2</bitWidth>
1800 <name>PUPDR11
</name>
1801 <description>Port x configuration bits (y =
1802 0.
.15)
</description>
1803 <bitOffset>22</bitOffset>
1804 <bitWidth>2</bitWidth>
1807 <name>PUPDR10
</name>
1808 <description>Port x configuration bits (y =
1809 0.
.15)
</description>
1810 <bitOffset>20</bitOffset>
1811 <bitWidth>2</bitWidth>
1815 <description>Port x configuration bits (y =
1816 0.
.15)
</description>
1817 <bitOffset>18</bitOffset>
1818 <bitWidth>2</bitWidth>
1822 <description>Port x configuration bits (y =
1823 0.
.15)
</description>
1824 <bitOffset>16</bitOffset>
1825 <bitWidth>2</bitWidth>
1829 <description>Port x configuration bits (y =
1830 0.
.15)
</description>
1831 <bitOffset>14</bitOffset>
1832 <bitWidth>2</bitWidth>
1836 <description>Port x configuration bits (y =
1837 0.
.15)
</description>
1838 <bitOffset>12</bitOffset>
1839 <bitWidth>2</bitWidth>
1843 <description>Port x configuration bits (y =
1844 0.
.15)
</description>
1845 <bitOffset>10</bitOffset>
1846 <bitWidth>2</bitWidth>
1850 <description>Port x configuration bits (y =
1851 0.
.15)
</description>
1852 <bitOffset>8</bitOffset>
1853 <bitWidth>2</bitWidth>
1857 <description>Port x configuration bits (y =
1858 0.
.15)
</description>
1859 <bitOffset>6</bitOffset>
1860 <bitWidth>2</bitWidth>
1864 <description>Port x configuration bits (y =
1865 0.
.15)
</description>
1866 <bitOffset>4</bitOffset>
1867 <bitWidth>2</bitWidth>
1871 <description>Port x configuration bits (y =
1872 0.
.15)
</description>
1873 <bitOffset>2</bitOffset>
1874 <bitWidth>2</bitWidth>
1878 <description>Port x configuration bits (y =
1879 0.
.15)
</description>
1880 <bitOffset>0</bitOffset>
1881 <bitWidth>2</bitWidth>
1887 <displayName>IDR
</displayName>
1888 <description>GPIO port input data register
</description>
1889 <addressOffset>0x10</addressOffset>
1891 <access>read-only
</access>
1892 <resetValue>0x00000000</resetValue>
1896 <description>Port input data (y =
1897 0.
.15)
</description>
1898 <bitOffset>15</bitOffset>
1899 <bitWidth>1</bitWidth>
1903 <description>Port input data (y =
1904 0.
.15)
</description>
1905 <bitOffset>14</bitOffset>
1906 <bitWidth>1</bitWidth>
1910 <description>Port input data (y =
1911 0.
.15)
</description>
1912 <bitOffset>13</bitOffset>
1913 <bitWidth>1</bitWidth>
1917 <description>Port input data (y =
1918 0.
.15)
</description>
1919 <bitOffset>12</bitOffset>
1920 <bitWidth>1</bitWidth>
1924 <description>Port input data (y =
1925 0.
.15)
</description>
1926 <bitOffset>11</bitOffset>
1927 <bitWidth>1</bitWidth>
1931 <description>Port input data (y =
1932 0.
.15)
</description>
1933 <bitOffset>10</bitOffset>
1934 <bitWidth>1</bitWidth>
1938 <description>Port input data (y =
1939 0.
.15)
</description>
1940 <bitOffset>9</bitOffset>
1941 <bitWidth>1</bitWidth>
1945 <description>Port input data (y =
1946 0.
.15)
</description>
1947 <bitOffset>8</bitOffset>
1948 <bitWidth>1</bitWidth>
1952 <description>Port input data (y =
1953 0.
.15)
</description>
1954 <bitOffset>7</bitOffset>
1955 <bitWidth>1</bitWidth>
1959 <description>Port input data (y =
1960 0.
.15)
</description>
1961 <bitOffset>6</bitOffset>
1962 <bitWidth>1</bitWidth>
1966 <description>Port input data (y =
1967 0.
.15)
</description>
1968 <bitOffset>5</bitOffset>
1969 <bitWidth>1</bitWidth>
1973 <description>Port input data (y =
1974 0.
.15)
</description>
1975 <bitOffset>4</bitOffset>
1976 <bitWidth>1</bitWidth>
1980 <description>Port input data (y =
1981 0.
.15)
</description>
1982 <bitOffset>3</bitOffset>
1983 <bitWidth>1</bitWidth>
1987 <description>Port input data (y =
1988 0.
.15)
</description>
1989 <bitOffset>2</bitOffset>
1990 <bitWidth>1</bitWidth>
1994 <description>Port input data (y =
1995 0.
.15)
</description>
1996 <bitOffset>1</bitOffset>
1997 <bitWidth>1</bitWidth>
2001 <description>Port input data (y =
2002 0.
.15)
</description>
2003 <bitOffset>0</bitOffset>
2004 <bitWidth>1</bitWidth>
2010 <displayName>ODR
</displayName>
2011 <description>GPIO port output data register
</description>
2012 <addressOffset>0x14</addressOffset>
2014 <access>read-write
</access>
2015 <resetValue>0x00000000</resetValue>
2019 <description>Port output data (y =
2020 0.
.15)
</description>
2021 <bitOffset>15</bitOffset>
2022 <bitWidth>1</bitWidth>
2026 <description>Port output data (y =
2027 0.
.15)
</description>
2028 <bitOffset>14</bitOffset>
2029 <bitWidth>1</bitWidth>
2033 <description>Port output data (y =
2034 0.
.15)
</description>
2035 <bitOffset>13</bitOffset>
2036 <bitWidth>1</bitWidth>
2040 <description>Port output data (y =
2041 0.
.15)
</description>
2042 <bitOffset>12</bitOffset>
2043 <bitWidth>1</bitWidth>
2047 <description>Port output data (y =
2048 0.
.15)
</description>
2049 <bitOffset>11</bitOffset>
2050 <bitWidth>1</bitWidth>
2054 <description>Port output data (y =
2055 0.
.15)
</description>
2056 <bitOffset>10</bitOffset>
2057 <bitWidth>1</bitWidth>
2061 <description>Port output data (y =
2062 0.
.15)
</description>
2063 <bitOffset>9</bitOffset>
2064 <bitWidth>1</bitWidth>
2068 <description>Port output data (y =
2069 0.
.15)
</description>
2070 <bitOffset>8</bitOffset>
2071 <bitWidth>1</bitWidth>
2075 <description>Port output data (y =
2076 0.
.15)
</description>
2077 <bitOffset>7</bitOffset>
2078 <bitWidth>1</bitWidth>
2082 <description>Port output data (y =
2083 0.
.15)
</description>
2084 <bitOffset>6</bitOffset>
2085 <bitWidth>1</bitWidth>
2089 <description>Port output data (y =
2090 0.
.15)
</description>
2091 <bitOffset>5</bitOffset>
2092 <bitWidth>1</bitWidth>
2096 <description>Port output data (y =
2097 0.
.15)
</description>
2098 <bitOffset>4</bitOffset>
2099 <bitWidth>1</bitWidth>
2103 <description>Port output data (y =
2104 0.
.15)
</description>
2105 <bitOffset>3</bitOffset>
2106 <bitWidth>1</bitWidth>
2110 <description>Port output data (y =
2111 0.
.15)
</description>
2112 <bitOffset>2</bitOffset>
2113 <bitWidth>1</bitWidth>
2117 <description>Port output data (y =
2118 0.
.15)
</description>
2119 <bitOffset>1</bitOffset>
2120 <bitWidth>1</bitWidth>
2124 <description>Port output data (y =
2125 0.
.15)
</description>
2126 <bitOffset>0</bitOffset>
2127 <bitWidth>1</bitWidth>
2133 <displayName>BSRR
</displayName>
2134 <description>GPIO port bit set/reset
2135 register
</description>
2136 <addressOffset>0x18</addressOffset>
2138 <access>write-only
</access>
2139 <resetValue>0x00000000</resetValue>
2143 <description>Port x reset bit y (y =
2144 0.
.15)
</description>
2145 <bitOffset>31</bitOffset>
2146 <bitWidth>1</bitWidth>
2150 <description>Port x reset bit y (y =
2151 0.
.15)
</description>
2152 <bitOffset>30</bitOffset>
2153 <bitWidth>1</bitWidth>
2157 <description>Port x reset bit y (y =
2158 0.
.15)
</description>
2159 <bitOffset>29</bitOffset>
2160 <bitWidth>1</bitWidth>
2164 <description>Port x reset bit y (y =
2165 0.
.15)
</description>
2166 <bitOffset>28</bitOffset>
2167 <bitWidth>1</bitWidth>
2171 <description>Port x reset bit y (y =
2172 0.
.15)
</description>
2173 <bitOffset>27</bitOffset>
2174 <bitWidth>1</bitWidth>
2178 <description>Port x reset bit y (y =
2179 0.
.15)
</description>
2180 <bitOffset>26</bitOffset>
2181 <bitWidth>1</bitWidth>
2185 <description>Port x reset bit y (y =
2186 0.
.15)
</description>
2187 <bitOffset>25</bitOffset>
2188 <bitWidth>1</bitWidth>
2192 <description>Port x reset bit y (y =
2193 0.
.15)
</description>
2194 <bitOffset>24</bitOffset>
2195 <bitWidth>1</bitWidth>
2199 <description>Port x reset bit y (y =
2200 0.
.15)
</description>
2201 <bitOffset>23</bitOffset>
2202 <bitWidth>1</bitWidth>
2206 <description>Port x reset bit y (y =
2207 0.
.15)
</description>
2208 <bitOffset>22</bitOffset>
2209 <bitWidth>1</bitWidth>
2213 <description>Port x reset bit y (y =
2214 0.
.15)
</description>
2215 <bitOffset>21</bitOffset>
2216 <bitWidth>1</bitWidth>
2220 <description>Port x reset bit y (y =
2221 0.
.15)
</description>
2222 <bitOffset>20</bitOffset>
2223 <bitWidth>1</bitWidth>
2227 <description>Port x reset bit y (y =
2228 0.
.15)
</description>
2229 <bitOffset>19</bitOffset>
2230 <bitWidth>1</bitWidth>
2234 <description>Port x reset bit y (y =
2235 0.
.15)
</description>
2236 <bitOffset>18</bitOffset>
2237 <bitWidth>1</bitWidth>
2241 <description>Port x reset bit y (y =
2242 0.
.15)
</description>
2243 <bitOffset>17</bitOffset>
2244 <bitWidth>1</bitWidth>
2248 <description>Port x set bit y (y=
2249 0.
.15)
</description>
2250 <bitOffset>16</bitOffset>
2251 <bitWidth>1</bitWidth>
2255 <description>Port x set bit y (y=
2256 0.
.15)
</description>
2257 <bitOffset>15</bitOffset>
2258 <bitWidth>1</bitWidth>
2262 <description>Port x set bit y (y=
2263 0.
.15)
</description>
2264 <bitOffset>14</bitOffset>
2265 <bitWidth>1</bitWidth>
2269 <description>Port x set bit y (y=
2270 0.
.15)
</description>
2271 <bitOffset>13</bitOffset>
2272 <bitWidth>1</bitWidth>
2276 <description>Port x set bit y (y=
2277 0.
.15)
</description>
2278 <bitOffset>12</bitOffset>
2279 <bitWidth>1</bitWidth>
2283 <description>Port x set bit y (y=
2284 0.
.15)
</description>
2285 <bitOffset>11</bitOffset>
2286 <bitWidth>1</bitWidth>
2290 <description>Port x set bit y (y=
2291 0.
.15)
</description>
2292 <bitOffset>10</bitOffset>
2293 <bitWidth>1</bitWidth>
2297 <description>Port x set bit y (y=
2298 0.
.15)
</description>
2299 <bitOffset>9</bitOffset>
2300 <bitWidth>1</bitWidth>
2304 <description>Port x set bit y (y=
2305 0.
.15)
</description>
2306 <bitOffset>8</bitOffset>
2307 <bitWidth>1</bitWidth>
2311 <description>Port x set bit y (y=
2312 0.
.15)
</description>
2313 <bitOffset>7</bitOffset>
2314 <bitWidth>1</bitWidth>
2318 <description>Port x set bit y (y=
2319 0.
.15)
</description>
2320 <bitOffset>6</bitOffset>
2321 <bitWidth>1</bitWidth>
2325 <description>Port x set bit y (y=
2326 0.
.15)
</description>
2327 <bitOffset>5</bitOffset>
2328 <bitWidth>1</bitWidth>
2332 <description>Port x set bit y (y=
2333 0.
.15)
</description>
2334 <bitOffset>4</bitOffset>
2335 <bitWidth>1</bitWidth>
2339 <description>Port x set bit y (y=
2340 0.
.15)
</description>
2341 <bitOffset>3</bitOffset>
2342 <bitWidth>1</bitWidth>
2346 <description>Port x set bit y (y=
2347 0.
.15)
</description>
2348 <bitOffset>2</bitOffset>
2349 <bitWidth>1</bitWidth>
2353 <description>Port x set bit y (y=
2354 0.
.15)
</description>
2355 <bitOffset>1</bitOffset>
2356 <bitWidth>1</bitWidth>
2360 <description>Port x set bit y (y=
2361 0.
.15)
</description>
2362 <bitOffset>0</bitOffset>
2363 <bitWidth>1</bitWidth>
2369 <displayName>LCKR
</displayName>
2370 <description>GPIO port configuration lock
2371 register
</description>
2372 <addressOffset>0x1C</addressOffset>
2374 <access>read-write
</access>
2375 <resetValue>0x00000000</resetValue>
2379 <description>Lok Key
</description>
2380 <bitOffset>16</bitOffset>
2381 <bitWidth>1</bitWidth>
2385 <description>Port x lock bit y (y=
2386 0.
.15)
</description>
2387 <bitOffset>15</bitOffset>
2388 <bitWidth>1</bitWidth>
2392 <description>Port x lock bit y (y=
2393 0.
.15)
</description>
2394 <bitOffset>14</bitOffset>
2395 <bitWidth>1</bitWidth>
2399 <description>Port x lock bit y (y=
2400 0.
.15)
</description>
2401 <bitOffset>13</bitOffset>
2402 <bitWidth>1</bitWidth>
2406 <description>Port x lock bit y (y=
2407 0.
.15)
</description>
2408 <bitOffset>12</bitOffset>
2409 <bitWidth>1</bitWidth>
2413 <description>Port x lock bit y (y=
2414 0.
.15)
</description>
2415 <bitOffset>11</bitOffset>
2416 <bitWidth>1</bitWidth>
2420 <description>Port x lock bit y (y=
2421 0.
.15)
</description>
2422 <bitOffset>10</bitOffset>
2423 <bitWidth>1</bitWidth>
2427 <description>Port x lock bit y (y=
2428 0.
.15)
</description>
2429 <bitOffset>9</bitOffset>
2430 <bitWidth>1</bitWidth>
2434 <description>Port x lock bit y (y=
2435 0.
.15)
</description>
2436 <bitOffset>8</bitOffset>
2437 <bitWidth>1</bitWidth>
2441 <description>Port x lock bit y (y=
2442 0.
.15)
</description>
2443 <bitOffset>7</bitOffset>
2444 <bitWidth>1</bitWidth>
2448 <description>Port x lock bit y (y=
2449 0.
.15)
</description>
2450 <bitOffset>6</bitOffset>
2451 <bitWidth>1</bitWidth>
2455 <description>Port x lock bit y (y=
2456 0.
.15)
</description>
2457 <bitOffset>5</bitOffset>
2458 <bitWidth>1</bitWidth>
2462 <description>Port x lock bit y (y=
2463 0.
.15)
</description>
2464 <bitOffset>4</bitOffset>
2465 <bitWidth>1</bitWidth>
2469 <description>Port x lock bit y (y=
2470 0.
.15)
</description>
2471 <bitOffset>3</bitOffset>
2472 <bitWidth>1</bitWidth>
2476 <description>Port x lock bit y (y=
2477 0.
.15)
</description>
2478 <bitOffset>2</bitOffset>
2479 <bitWidth>1</bitWidth>
2483 <description>Port x lock bit y (y=
2484 0.
.15)
</description>
2485 <bitOffset>1</bitOffset>
2486 <bitWidth>1</bitWidth>
2490 <description>Port x lock bit y (y=
2491 0.
.15)
</description>
2492 <bitOffset>0</bitOffset>
2493 <bitWidth>1</bitWidth>
2499 <displayName>AFRL
</displayName>
2500 <description>GPIO alternate function low
2501 register
</description>
2502 <addressOffset>0x20</addressOffset>
2504 <access>read-write
</access>
2505 <resetValue>0x00000000</resetValue>
2509 <description>Alternate function selection for port x
2510 bit y (y =
0.
.7)
</description>
2511 <bitOffset>28</bitOffset>
2512 <bitWidth>4</bitWidth>
2516 <description>Alternate function selection for port x
2517 bit y (y =
0.
.7)
</description>
2518 <bitOffset>24</bitOffset>
2519 <bitWidth>4</bitWidth>
2523 <description>Alternate function selection for port x
2524 bit y (y =
0.
.7)
</description>
2525 <bitOffset>20</bitOffset>
2526 <bitWidth>4</bitWidth>
2530 <description>Alternate function selection for port x
2531 bit y (y =
0.
.7)
</description>
2532 <bitOffset>16</bitOffset>
2533 <bitWidth>4</bitWidth>
2537 <description>Alternate function selection for port x
2538 bit y (y =
0.
.7)
</description>
2539 <bitOffset>12</bitOffset>
2540 <bitWidth>4</bitWidth>
2544 <description>Alternate function selection for port x
2545 bit y (y =
0.
.7)
</description>
2546 <bitOffset>8</bitOffset>
2547 <bitWidth>4</bitWidth>
2551 <description>Alternate function selection for port x
2552 bit y (y =
0.
.7)
</description>
2553 <bitOffset>4</bitOffset>
2554 <bitWidth>4</bitWidth>
2558 <description>Alternate function selection for port x
2559 bit y (y =
0.
.7)
</description>
2560 <bitOffset>0</bitOffset>
2561 <bitWidth>4</bitWidth>
2567 <displayName>AFRH
</displayName>
2568 <description>GPIO alternate function high
2569 register
</description>
2570 <addressOffset>0x24</addressOffset>
2572 <access>read-write
</access>
2573 <resetValue>0x00000000</resetValue>
2577 <description>Alternate function selection for port x
2578 bit y (y =
8.
.15)
</description>
2579 <bitOffset>28</bitOffset>
2580 <bitWidth>4</bitWidth>
2584 <description>Alternate function selection for port x
2585 bit y (y =
8.
.15)
</description>
2586 <bitOffset>24</bitOffset>
2587 <bitWidth>4</bitWidth>
2591 <description>Alternate function selection for port x
2592 bit y (y =
8.
.15)
</description>
2593 <bitOffset>20</bitOffset>
2594 <bitWidth>4</bitWidth>
2598 <description>Alternate function selection for port x
2599 bit y (y =
8.
.15)
</description>
2600 <bitOffset>16</bitOffset>
2601 <bitWidth>4</bitWidth>
2605 <description>Alternate function selection for port x
2606 bit y (y =
8.
.15)
</description>
2607 <bitOffset>12</bitOffset>
2608 <bitWidth>4</bitWidth>
2612 <description>Alternate function selection for port x
2613 bit y (y =
8.
.15)
</description>
2614 <bitOffset>8</bitOffset>
2615 <bitWidth>4</bitWidth>
2619 <description>Alternate function selection for port x
2620 bit y (y =
8.
.15)
</description>
2621 <bitOffset>4</bitOffset>
2622 <bitWidth>4</bitWidth>
2626 <description>Alternate function selection for port x
2627 bit y (y =
8.
.15)
</description>
2628 <bitOffset>0</bitOffset>
2629 <bitWidth>4</bitWidth>
2635 <displayName>BRR
</displayName>
2636 <description>Port bit reset register
</description>
2637 <addressOffset>0x28</addressOffset>
2639 <access>write-only
</access>
2640 <resetValue>0x00000000</resetValue>
2644 <description>Port x Reset bit y
</description>
2645 <bitOffset>0</bitOffset>
2646 <bitWidth>1</bitWidth>
2650 <description>Port x Reset bit y
</description>
2651 <bitOffset>1</bitOffset>
2652 <bitWidth>1</bitWidth>
2656 <description>Port x Reset bit y
</description>
2657 <bitOffset>2</bitOffset>
2658 <bitWidth>1</bitWidth>
2662 <description>Port x Reset bit y
</description>
2663 <bitOffset>3</bitOffset>
2664 <bitWidth>1</bitWidth>
2668 <description>Port x Reset bit y
</description>
2669 <bitOffset>4</bitOffset>
2670 <bitWidth>1</bitWidth>
2674 <description>Port x Reset bit y
</description>
2675 <bitOffset>5</bitOffset>
2676 <bitWidth>1</bitWidth>
2680 <description>Port x Reset bit y
</description>
2681 <bitOffset>6</bitOffset>
2682 <bitWidth>1</bitWidth>
2686 <description>Port x Reset bit y
</description>
2687 <bitOffset>7</bitOffset>
2688 <bitWidth>1</bitWidth>
2692 <description>Port x Reset bit y
</description>
2693 <bitOffset>8</bitOffset>
2694 <bitWidth>1</bitWidth>
2698 <description>Port x Reset bit y
</description>
2699 <bitOffset>9</bitOffset>
2700 <bitWidth>1</bitWidth>
2704 <description>Port x Reset bit y
</description>
2705 <bitOffset>10</bitOffset>
2706 <bitWidth>1</bitWidth>
2710 <description>Port x Reset bit y
</description>
2711 <bitOffset>11</bitOffset>
2712 <bitWidth>1</bitWidth>
2716 <description>Port x Reset bit y
</description>
2717 <bitOffset>12</bitOffset>
2718 <bitWidth>1</bitWidth>
2722 <description>Port x Reset bit y
</description>
2723 <bitOffset>13</bitOffset>
2724 <bitWidth>1</bitWidth>
2728 <description>Port x Reset bit y
</description>
2729 <bitOffset>14</bitOffset>
2730 <bitWidth>1</bitWidth>
2734 <description>Port x Reset bit y
</description>
2735 <bitOffset>15</bitOffset>
2736 <bitWidth>1</bitWidth>
2742 <peripheral derivedFrom=
"GPIOB">
2744 <baseAddress>0x48000800</baseAddress>
2746 <peripheral derivedFrom=
"GPIOB">
2748 <baseAddress>0x48000C00</baseAddress>
2750 <peripheral derivedFrom=
"GPIOB">
2752 <baseAddress>0x48001000</baseAddress>
2754 <peripheral derivedFrom=
"GPIOB">
2756 <baseAddress>0x48001400</baseAddress>
2758 <peripheral derivedFrom=
"GPIOB">
2760 <baseAddress>0x48001800</baseAddress>
2762 <peripheral derivedFrom=
"GPIOB">
2764 <baseAddress>0x48001C00</baseAddress>
2768 <description>Touch sensing controller
</description>
2769 <groupName>TSC
</groupName>
2770 <baseAddress>0x40024000</baseAddress>
2772 <offset>0x0</offset>
2774 <usage>registers
</usage>
2777 <name>EXTI2_TSC
</name>
2778 <description>EXTI Line2 and Touch sensing
2779 interrupts
</description>
2785 <displayName>CR
</displayName>
2786 <description>control register
</description>
2787 <addressOffset>0x0</addressOffset>
2789 <access>read-write
</access>
2790 <resetValue>0x00000000</resetValue>
2794 <description>Charge transfer pulse high
</description>
2795 <bitOffset>28</bitOffset>
2796 <bitWidth>4</bitWidth>
2800 <description>Charge transfer pulse low
</description>
2801 <bitOffset>24</bitOffset>
2802 <bitWidth>4</bitWidth>
2806 <description>Spread spectrum deviation
</description>
2807 <bitOffset>17</bitOffset>
2808 <bitWidth>7</bitWidth>
2812 <description>Spread spectrum enable
</description>
2813 <bitOffset>16</bitOffset>
2814 <bitWidth>1</bitWidth>
2818 <description>Spread spectrum prescaler
</description>
2819 <bitOffset>15</bitOffset>
2820 <bitWidth>1</bitWidth>
2824 <description>pulse generator prescaler
</description>
2825 <bitOffset>12</bitOffset>
2826 <bitWidth>3</bitWidth>
2830 <description>Max count value
</description>
2831 <bitOffset>5</bitOffset>
2832 <bitWidth>3</bitWidth>
2836 <description>I/O Default mode
</description>
2837 <bitOffset>4</bitOffset>
2838 <bitWidth>1</bitWidth>
2841 <name>SYNCPOL
</name>
2842 <description>Synchronization pin
2843 polarity
</description>
2844 <bitOffset>3</bitOffset>
2845 <bitWidth>1</bitWidth>
2849 <description>Acquisition mode
</description>
2850 <bitOffset>2</bitOffset>
2851 <bitWidth>1</bitWidth>
2855 <description>Start a new acquisition
</description>
2856 <bitOffset>1</bitOffset>
2857 <bitWidth>1</bitWidth>
2861 <description>Touch sensing controller
2862 enable
</description>
2863 <bitOffset>0</bitOffset>
2864 <bitWidth>1</bitWidth>
2870 <displayName>IER
</displayName>
2871 <description>interrupt enable register
</description>
2872 <addressOffset>0x4</addressOffset>
2874 <access>read-write
</access>
2875 <resetValue>0x00000000</resetValue>
2879 <description>Max count error interrupt
2880 enable
</description>
2881 <bitOffset>1</bitOffset>
2882 <bitWidth>1</bitWidth>
2886 <description>End of acquisition interrupt
2887 enable
</description>
2888 <bitOffset>0</bitOffset>
2889 <bitWidth>1</bitWidth>
2895 <displayName>ICR
</displayName>
2896 <description>interrupt clear register
</description>
2897 <addressOffset>0x8</addressOffset>
2899 <access>read-write
</access>
2900 <resetValue>0x00000000</resetValue>
2904 <description>Max count error interrupt
2906 <bitOffset>1</bitOffset>
2907 <bitWidth>1</bitWidth>
2911 <description>End of acquisition interrupt
2913 <bitOffset>0</bitOffset>
2914 <bitWidth>1</bitWidth>
2920 <displayName>ISR
</displayName>
2921 <description>interrupt status register
</description>
2922 <addressOffset>0xC</addressOffset>
2924 <access>read-write
</access>
2925 <resetValue>0x00000000</resetValue>
2929 <description>Max count error flag
</description>
2930 <bitOffset>1</bitOffset>
2931 <bitWidth>1</bitWidth>
2935 <description>End of acquisition flag
</description>
2936 <bitOffset>0</bitOffset>
2937 <bitWidth>1</bitWidth>
2943 <displayName>IOHCR
</displayName>
2944 <description>I/O hysteresis control
2945 register
</description>
2946 <addressOffset>0x10</addressOffset>
2948 <access>read-write
</access>
2949 <resetValue>0xFFFFFFFF</resetValue>
2953 <description>G1_IO1 Schmitt trigger hysteresis
2955 <bitOffset>0</bitOffset>
2956 <bitWidth>1</bitWidth>
2960 <description>G1_IO2 Schmitt trigger hysteresis
2962 <bitOffset>1</bitOffset>
2963 <bitWidth>1</bitWidth>
2967 <description>G1_IO3 Schmitt trigger hysteresis
2969 <bitOffset>2</bitOffset>
2970 <bitWidth>1</bitWidth>
2974 <description>G1_IO4 Schmitt trigger hysteresis
2976 <bitOffset>3</bitOffset>
2977 <bitWidth>1</bitWidth>
2981 <description>G2_IO1 Schmitt trigger hysteresis
2983 <bitOffset>4</bitOffset>
2984 <bitWidth>1</bitWidth>
2988 <description>G2_IO2 Schmitt trigger hysteresis
2990 <bitOffset>5</bitOffset>
2991 <bitWidth>1</bitWidth>
2995 <description>G2_IO3 Schmitt trigger hysteresis
2997 <bitOffset>6</bitOffset>
2998 <bitWidth>1</bitWidth>
3002 <description>G2_IO4 Schmitt trigger hysteresis
3004 <bitOffset>7</bitOffset>
3005 <bitWidth>1</bitWidth>
3009 <description>G3_IO1 Schmitt trigger hysteresis
3011 <bitOffset>8</bitOffset>
3012 <bitWidth>1</bitWidth>
3016 <description>G3_IO2 Schmitt trigger hysteresis
3018 <bitOffset>9</bitOffset>
3019 <bitWidth>1</bitWidth>
3023 <description>G3_IO3 Schmitt trigger hysteresis
3025 <bitOffset>10</bitOffset>
3026 <bitWidth>1</bitWidth>
3030 <description>G3_IO4 Schmitt trigger hysteresis
3032 <bitOffset>11</bitOffset>
3033 <bitWidth>1</bitWidth>
3037 <description>G4_IO1 Schmitt trigger hysteresis
3039 <bitOffset>12</bitOffset>
3040 <bitWidth>1</bitWidth>
3044 <description>G4_IO2 Schmitt trigger hysteresis
3046 <bitOffset>13</bitOffset>
3047 <bitWidth>1</bitWidth>
3051 <description>G4_IO3 Schmitt trigger hysteresis
3053 <bitOffset>14</bitOffset>
3054 <bitWidth>1</bitWidth>
3058 <description>G4_IO4 Schmitt trigger hysteresis
3060 <bitOffset>15</bitOffset>
3061 <bitWidth>1</bitWidth>
3065 <description>G5_IO1 Schmitt trigger hysteresis
3067 <bitOffset>16</bitOffset>
3068 <bitWidth>1</bitWidth>
3072 <description>G5_IO2 Schmitt trigger hysteresis
3074 <bitOffset>17</bitOffset>
3075 <bitWidth>1</bitWidth>
3079 <description>G5_IO3 Schmitt trigger hysteresis
3081 <bitOffset>18</bitOffset>
3082 <bitWidth>1</bitWidth>
3086 <description>G5_IO4 Schmitt trigger hysteresis
3088 <bitOffset>19</bitOffset>
3089 <bitWidth>1</bitWidth>
3093 <description>G6_IO1 Schmitt trigger hysteresis
3095 <bitOffset>20</bitOffset>
3096 <bitWidth>1</bitWidth>
3100 <description>G6_IO2 Schmitt trigger hysteresis
3102 <bitOffset>21</bitOffset>
3103 <bitWidth>1</bitWidth>
3107 <description>G6_IO3 Schmitt trigger hysteresis
3109 <bitOffset>22</bitOffset>
3110 <bitWidth>1</bitWidth>
3114 <description>G6_IO4 Schmitt trigger hysteresis
3116 <bitOffset>23</bitOffset>
3117 <bitWidth>1</bitWidth>
3121 <description>G7_IO1 Schmitt trigger hysteresis
3123 <bitOffset>24</bitOffset>
3124 <bitWidth>1</bitWidth>
3128 <description>G7_IO2 Schmitt trigger hysteresis
3130 <bitOffset>25</bitOffset>
3131 <bitWidth>1</bitWidth>
3135 <description>G7_IO3 Schmitt trigger hysteresis
3137 <bitOffset>26</bitOffset>
3138 <bitWidth>1</bitWidth>
3142 <description>G7_IO4 Schmitt trigger hysteresis
3144 <bitOffset>27</bitOffset>
3145 <bitWidth>1</bitWidth>
3149 <description>G8_IO1 Schmitt trigger hysteresis
3151 <bitOffset>28</bitOffset>
3152 <bitWidth>1</bitWidth>
3156 <description>G8_IO2 Schmitt trigger hysteresis
3158 <bitOffset>29</bitOffset>
3159 <bitWidth>1</bitWidth>
3163 <description>G8_IO3 Schmitt trigger hysteresis
3165 <bitOffset>30</bitOffset>
3166 <bitWidth>1</bitWidth>
3170 <description>G8_IO4 Schmitt trigger hysteresis
3172 <bitOffset>31</bitOffset>
3173 <bitWidth>1</bitWidth>
3179 <displayName>IOASCR
</displayName>
3180 <description>I/O analog switch control
3181 register
</description>
3182 <addressOffset>0x18</addressOffset>
3184 <access>read-write
</access>
3185 <resetValue>0x00000000</resetValue>
3189 <description>G1_IO1 analog switch
3190 enable
</description>
3191 <bitOffset>0</bitOffset>
3192 <bitWidth>1</bitWidth>
3196 <description>G1_IO2 analog switch
3197 enable
</description>
3198 <bitOffset>1</bitOffset>
3199 <bitWidth>1</bitWidth>
3203 <description>G1_IO3 analog switch
3204 enable
</description>
3205 <bitOffset>2</bitOffset>
3206 <bitWidth>1</bitWidth>
3210 <description>G1_IO4 analog switch
3211 enable
</description>
3212 <bitOffset>3</bitOffset>
3213 <bitWidth>1</bitWidth>
3217 <description>G2_IO1 analog switch
3218 enable
</description>
3219 <bitOffset>4</bitOffset>
3220 <bitWidth>1</bitWidth>
3224 <description>G2_IO2 analog switch
3225 enable
</description>
3226 <bitOffset>5</bitOffset>
3227 <bitWidth>1</bitWidth>
3231 <description>G2_IO3 analog switch
3232 enable
</description>
3233 <bitOffset>6</bitOffset>
3234 <bitWidth>1</bitWidth>
3238 <description>G2_IO4 analog switch
3239 enable
</description>
3240 <bitOffset>7</bitOffset>
3241 <bitWidth>1</bitWidth>
3245 <description>G3_IO1 analog switch
3246 enable
</description>
3247 <bitOffset>8</bitOffset>
3248 <bitWidth>1</bitWidth>
3252 <description>G3_IO2 analog switch
3253 enable
</description>
3254 <bitOffset>9</bitOffset>
3255 <bitWidth>1</bitWidth>
3259 <description>G3_IO3 analog switch
3260 enable
</description>
3261 <bitOffset>10</bitOffset>
3262 <bitWidth>1</bitWidth>
3266 <description>G3_IO4 analog switch
3267 enable
</description>
3268 <bitOffset>11</bitOffset>
3269 <bitWidth>1</bitWidth>
3273 <description>G4_IO1 analog switch
3274 enable
</description>
3275 <bitOffset>12</bitOffset>
3276 <bitWidth>1</bitWidth>
3280 <description>G4_IO2 analog switch
3281 enable
</description>
3282 <bitOffset>13</bitOffset>
3283 <bitWidth>1</bitWidth>
3287 <description>G4_IO3 analog switch
3288 enable
</description>
3289 <bitOffset>14</bitOffset>
3290 <bitWidth>1</bitWidth>
3294 <description>G4_IO4 analog switch
3295 enable
</description>
3296 <bitOffset>15</bitOffset>
3297 <bitWidth>1</bitWidth>
3301 <description>G5_IO1 analog switch
3302 enable
</description>
3303 <bitOffset>16</bitOffset>
3304 <bitWidth>1</bitWidth>
3308 <description>G5_IO2 analog switch
3309 enable
</description>
3310 <bitOffset>17</bitOffset>
3311 <bitWidth>1</bitWidth>
3315 <description>G5_IO3 analog switch
3316 enable
</description>
3317 <bitOffset>18</bitOffset>
3318 <bitWidth>1</bitWidth>
3322 <description>G5_IO4 analog switch
3323 enable
</description>
3324 <bitOffset>19</bitOffset>
3325 <bitWidth>1</bitWidth>
3329 <description>G6_IO1 analog switch
3330 enable
</description>
3331 <bitOffset>20</bitOffset>
3332 <bitWidth>1</bitWidth>
3336 <description>G6_IO2 analog switch
3337 enable
</description>
3338 <bitOffset>21</bitOffset>
3339 <bitWidth>1</bitWidth>
3343 <description>G6_IO3 analog switch
3344 enable
</description>
3345 <bitOffset>22</bitOffset>
3346 <bitWidth>1</bitWidth>
3350 <description>G6_IO4 analog switch
3351 enable
</description>
3352 <bitOffset>23</bitOffset>
3353 <bitWidth>1</bitWidth>
3357 <description>G7_IO1 analog switch
3358 enable
</description>
3359 <bitOffset>24</bitOffset>
3360 <bitWidth>1</bitWidth>
3364 <description>G7_IO2 analog switch
3365 enable
</description>
3366 <bitOffset>25</bitOffset>
3367 <bitWidth>1</bitWidth>
3371 <description>G7_IO3 analog switch
3372 enable
</description>
3373 <bitOffset>26</bitOffset>
3374 <bitWidth>1</bitWidth>
3378 <description>G7_IO4 analog switch
3379 enable
</description>
3380 <bitOffset>27</bitOffset>
3381 <bitWidth>1</bitWidth>
3385 <description>G8_IO1 analog switch
3386 enable
</description>
3387 <bitOffset>28</bitOffset>
3388 <bitWidth>1</bitWidth>
3392 <description>G8_IO2 analog switch
3393 enable
</description>
3394 <bitOffset>29</bitOffset>
3395 <bitWidth>1</bitWidth>
3399 <description>G8_IO3 analog switch
3400 enable
</description>
3401 <bitOffset>30</bitOffset>
3402 <bitWidth>1</bitWidth>
3406 <description>G8_IO4 analog switch
3407 enable
</description>
3408 <bitOffset>31</bitOffset>
3409 <bitWidth>1</bitWidth>
3415 <displayName>IOSCR
</displayName>
3416 <description>I/O sampling control register
</description>
3417 <addressOffset>0x20</addressOffset>
3419 <access>read-write
</access>
3420 <resetValue>0x00000000</resetValue>
3424 <description>G1_IO1 sampling mode
</description>
3425 <bitOffset>0</bitOffset>
3426 <bitWidth>1</bitWidth>
3430 <description>G1_IO2 sampling mode
</description>
3431 <bitOffset>1</bitOffset>
3432 <bitWidth>1</bitWidth>
3436 <description>G1_IO3 sampling mode
</description>
3437 <bitOffset>2</bitOffset>
3438 <bitWidth>1</bitWidth>
3442 <description>G1_IO4 sampling mode
</description>
3443 <bitOffset>3</bitOffset>
3444 <bitWidth>1</bitWidth>
3448 <description>G2_IO1 sampling mode
</description>
3449 <bitOffset>4</bitOffset>
3450 <bitWidth>1</bitWidth>
3454 <description>G2_IO2 sampling mode
</description>
3455 <bitOffset>5</bitOffset>
3456 <bitWidth>1</bitWidth>
3460 <description>G2_IO3 sampling mode
</description>
3461 <bitOffset>6</bitOffset>
3462 <bitWidth>1</bitWidth>
3466 <description>G2_IO4 sampling mode
</description>
3467 <bitOffset>7</bitOffset>
3468 <bitWidth>1</bitWidth>
3472 <description>G3_IO1 sampling mode
</description>
3473 <bitOffset>8</bitOffset>
3474 <bitWidth>1</bitWidth>
3478 <description>G3_IO2 sampling mode
</description>
3479 <bitOffset>9</bitOffset>
3480 <bitWidth>1</bitWidth>
3484 <description>G3_IO3 sampling mode
</description>
3485 <bitOffset>10</bitOffset>
3486 <bitWidth>1</bitWidth>
3490 <description>G3_IO4 sampling mode
</description>
3491 <bitOffset>11</bitOffset>
3492 <bitWidth>1</bitWidth>
3496 <description>G4_IO1 sampling mode
</description>
3497 <bitOffset>12</bitOffset>
3498 <bitWidth>1</bitWidth>
3502 <description>G4_IO2 sampling mode
</description>
3503 <bitOffset>13</bitOffset>
3504 <bitWidth>1</bitWidth>
3508 <description>G4_IO3 sampling mode
</description>
3509 <bitOffset>14</bitOffset>
3510 <bitWidth>1</bitWidth>
3514 <description>G4_IO4 sampling mode
</description>
3515 <bitOffset>15</bitOffset>
3516 <bitWidth>1</bitWidth>
3520 <description>G5_IO1 sampling mode
</description>
3521 <bitOffset>16</bitOffset>
3522 <bitWidth>1</bitWidth>
3526 <description>G5_IO2 sampling mode
</description>
3527 <bitOffset>17</bitOffset>
3528 <bitWidth>1</bitWidth>
3532 <description>G5_IO3 sampling mode
</description>
3533 <bitOffset>18</bitOffset>
3534 <bitWidth>1</bitWidth>
3538 <description>G5_IO4 sampling mode
</description>
3539 <bitOffset>19</bitOffset>
3540 <bitWidth>1</bitWidth>
3544 <description>G6_IO1 sampling mode
</description>
3545 <bitOffset>20</bitOffset>
3546 <bitWidth>1</bitWidth>
3550 <description>G6_IO2 sampling mode
</description>
3551 <bitOffset>21</bitOffset>
3552 <bitWidth>1</bitWidth>
3556 <description>G6_IO3 sampling mode
</description>
3557 <bitOffset>22</bitOffset>
3558 <bitWidth>1</bitWidth>
3562 <description>G6_IO4 sampling mode
</description>
3563 <bitOffset>23</bitOffset>
3564 <bitWidth>1</bitWidth>
3568 <description>G7_IO1 sampling mode
</description>
3569 <bitOffset>24</bitOffset>
3570 <bitWidth>1</bitWidth>
3574 <description>G7_IO2 sampling mode
</description>
3575 <bitOffset>25</bitOffset>
3576 <bitWidth>1</bitWidth>
3580 <description>G7_IO3 sampling mode
</description>
3581 <bitOffset>26</bitOffset>
3582 <bitWidth>1</bitWidth>
3586 <description>G7_IO4 sampling mode
</description>
3587 <bitOffset>27</bitOffset>
3588 <bitWidth>1</bitWidth>
3592 <description>G8_IO1 sampling mode
</description>
3593 <bitOffset>28</bitOffset>
3594 <bitWidth>1</bitWidth>
3598 <description>G8_IO2 sampling mode
</description>
3599 <bitOffset>29</bitOffset>
3600 <bitWidth>1</bitWidth>
3604 <description>G8_IO3 sampling mode
</description>
3605 <bitOffset>30</bitOffset>
3606 <bitWidth>1</bitWidth>
3610 <description>G8_IO4 sampling mode
</description>
3611 <bitOffset>31</bitOffset>
3612 <bitWidth>1</bitWidth>
3618 <displayName>IOCCR
</displayName>
3619 <description>I/O channel control register
</description>
3620 <addressOffset>0x28</addressOffset>
3622 <access>read-write
</access>
3623 <resetValue>0x00000000</resetValue>
3627 <description>G1_IO1 channel mode
</description>
3628 <bitOffset>0</bitOffset>
3629 <bitWidth>1</bitWidth>
3633 <description>G1_IO2 channel mode
</description>
3634 <bitOffset>1</bitOffset>
3635 <bitWidth>1</bitWidth>
3639 <description>G1_IO3 channel mode
</description>
3640 <bitOffset>2</bitOffset>
3641 <bitWidth>1</bitWidth>
3645 <description>G1_IO4 channel mode
</description>
3646 <bitOffset>3</bitOffset>
3647 <bitWidth>1</bitWidth>
3651 <description>G2_IO1 channel mode
</description>
3652 <bitOffset>4</bitOffset>
3653 <bitWidth>1</bitWidth>
3657 <description>G2_IO2 channel mode
</description>
3658 <bitOffset>5</bitOffset>
3659 <bitWidth>1</bitWidth>
3663 <description>G2_IO3 channel mode
</description>
3664 <bitOffset>6</bitOffset>
3665 <bitWidth>1</bitWidth>
3669 <description>G2_IO4 channel mode
</description>
3670 <bitOffset>7</bitOffset>
3671 <bitWidth>1</bitWidth>
3675 <description>G3_IO1 channel mode
</description>
3676 <bitOffset>8</bitOffset>
3677 <bitWidth>1</bitWidth>
3681 <description>G3_IO2 channel mode
</description>
3682 <bitOffset>9</bitOffset>
3683 <bitWidth>1</bitWidth>
3687 <description>G3_IO3 channel mode
</description>
3688 <bitOffset>10</bitOffset>
3689 <bitWidth>1</bitWidth>
3693 <description>G3_IO4 channel mode
</description>
3694 <bitOffset>11</bitOffset>
3695 <bitWidth>1</bitWidth>
3699 <description>G4_IO1 channel mode
</description>
3700 <bitOffset>12</bitOffset>
3701 <bitWidth>1</bitWidth>
3705 <description>G4_IO2 channel mode
</description>
3706 <bitOffset>13</bitOffset>
3707 <bitWidth>1</bitWidth>
3711 <description>G4_IO3 channel mode
</description>
3712 <bitOffset>14</bitOffset>
3713 <bitWidth>1</bitWidth>
3717 <description>G4_IO4 channel mode
</description>
3718 <bitOffset>15</bitOffset>
3719 <bitWidth>1</bitWidth>
3723 <description>G5_IO1 channel mode
</description>
3724 <bitOffset>16</bitOffset>
3725 <bitWidth>1</bitWidth>
3729 <description>G5_IO2 channel mode
</description>
3730 <bitOffset>17</bitOffset>
3731 <bitWidth>1</bitWidth>
3735 <description>G5_IO3 channel mode
</description>
3736 <bitOffset>18</bitOffset>
3737 <bitWidth>1</bitWidth>
3741 <description>G5_IO4 channel mode
</description>
3742 <bitOffset>19</bitOffset>
3743 <bitWidth>1</bitWidth>
3747 <description>G6_IO1 channel mode
</description>
3748 <bitOffset>20</bitOffset>
3749 <bitWidth>1</bitWidth>
3753 <description>G6_IO2 channel mode
</description>
3754 <bitOffset>21</bitOffset>
3755 <bitWidth>1</bitWidth>
3759 <description>G6_IO3 channel mode
</description>
3760 <bitOffset>22</bitOffset>
3761 <bitWidth>1</bitWidth>
3765 <description>G6_IO4 channel mode
</description>
3766 <bitOffset>23</bitOffset>
3767 <bitWidth>1</bitWidth>
3771 <description>G7_IO1 channel mode
</description>
3772 <bitOffset>24</bitOffset>
3773 <bitWidth>1</bitWidth>
3777 <description>G7_IO2 channel mode
</description>
3778 <bitOffset>25</bitOffset>
3779 <bitWidth>1</bitWidth>
3783 <description>G7_IO3 channel mode
</description>
3784 <bitOffset>26</bitOffset>
3785 <bitWidth>1</bitWidth>
3789 <description>G7_IO4 channel mode
</description>
3790 <bitOffset>27</bitOffset>
3791 <bitWidth>1</bitWidth>
3795 <description>G8_IO1 channel mode
</description>
3796 <bitOffset>28</bitOffset>
3797 <bitWidth>1</bitWidth>
3801 <description>G8_IO2 channel mode
</description>
3802 <bitOffset>29</bitOffset>
3803 <bitWidth>1</bitWidth>
3807 <description>G8_IO3 channel mode
</description>
3808 <bitOffset>30</bitOffset>
3809 <bitWidth>1</bitWidth>
3813 <description>G8_IO4 channel mode
</description>
3814 <bitOffset>31</bitOffset>
3815 <bitWidth>1</bitWidth>
3821 <displayName>IOGCSR
</displayName>
3822 <description>I/O group control status
3823 register
</description>
3824 <addressOffset>0x30</addressOffset>
3826 <resetValue>0x00000000</resetValue>
3830 <description>Analog I/O group x status
</description>
3831 <bitOffset>23</bitOffset>
3832 <bitWidth>1</bitWidth>
3833 <access>read-write
</access>
3837 <description>Analog I/O group x status
</description>
3838 <bitOffset>22</bitOffset>
3839 <bitWidth>1</bitWidth>
3840 <access>read-write
</access>
3844 <description>Analog I/O group x status
</description>
3845 <bitOffset>21</bitOffset>
3846 <bitWidth>1</bitWidth>
3847 <access>read-only
</access>
3851 <description>Analog I/O group x status
</description>
3852 <bitOffset>20</bitOffset>
3853 <bitWidth>1</bitWidth>
3854 <access>read-only
</access>
3858 <description>Analog I/O group x status
</description>
3859 <bitOffset>19</bitOffset>
3860 <bitWidth>1</bitWidth>
3861 <access>read-only
</access>
3865 <description>Analog I/O group x status
</description>
3866 <bitOffset>18</bitOffset>
3867 <bitWidth>1</bitWidth>
3868 <access>read-only
</access>
3872 <description>Analog I/O group x status
</description>
3873 <bitOffset>17</bitOffset>
3874 <bitWidth>1</bitWidth>
3875 <access>read-only
</access>
3879 <description>Analog I/O group x status
</description>
3880 <bitOffset>16</bitOffset>
3881 <bitWidth>1</bitWidth>
3882 <access>read-only
</access>
3886 <description>Analog I/O group x enable
</description>
3887 <bitOffset>7</bitOffset>
3888 <bitWidth>1</bitWidth>
3889 <access>read-write
</access>
3893 <description>Analog I/O group x enable
</description>
3894 <bitOffset>6</bitOffset>
3895 <bitWidth>1</bitWidth>
3896 <access>read-write
</access>
3900 <description>Analog I/O group x enable
</description>
3901 <bitOffset>5</bitOffset>
3902 <bitWidth>1</bitWidth>
3903 <access>read-write
</access>
3907 <description>Analog I/O group x enable
</description>
3908 <bitOffset>4</bitOffset>
3909 <bitWidth>1</bitWidth>
3910 <access>read-write
</access>
3914 <description>Analog I/O group x enable
</description>
3915 <bitOffset>3</bitOffset>
3916 <bitWidth>1</bitWidth>
3917 <access>read-write
</access>
3921 <description>Analog I/O group x enable
</description>
3922 <bitOffset>2</bitOffset>
3923 <bitWidth>1</bitWidth>
3924 <access>read-write
</access>
3928 <description>Analog I/O group x enable
</description>
3929 <bitOffset>1</bitOffset>
3930 <bitWidth>1</bitWidth>
3931 <access>read-write
</access>
3935 <description>Analog I/O group x enable
</description>
3936 <bitOffset>0</bitOffset>
3937 <bitWidth>1</bitWidth>
3938 <access>read-write
</access>
3944 <displayName>IOG1CR
</displayName>
3945 <description>I/O group x counter register
</description>
3946 <addressOffset>0x34</addressOffset>
3948 <access>read-only
</access>
3949 <resetValue>0x00000000</resetValue>
3953 <description>Counter value
</description>
3954 <bitOffset>0</bitOffset>
3955 <bitWidth>14</bitWidth>
3961 <displayName>IOG2CR
</displayName>
3962 <description>I/O group x counter register
</description>
3963 <addressOffset>0x38</addressOffset>
3965 <access>read-only
</access>
3966 <resetValue>0x00000000</resetValue>
3970 <description>Counter value
</description>
3971 <bitOffset>0</bitOffset>
3972 <bitWidth>14</bitWidth>
3978 <displayName>IOG3CR
</displayName>
3979 <description>I/O group x counter register
</description>
3980 <addressOffset>0x3C</addressOffset>
3982 <access>read-only
</access>
3983 <resetValue>0x00000000</resetValue>
3987 <description>Counter value
</description>
3988 <bitOffset>0</bitOffset>
3989 <bitWidth>14</bitWidth>
3995 <displayName>IOG4CR
</displayName>
3996 <description>I/O group x counter register
</description>
3997 <addressOffset>0x40</addressOffset>
3999 <access>read-only
</access>
4000 <resetValue>0x00000000</resetValue>
4004 <description>Counter value
</description>
4005 <bitOffset>0</bitOffset>
4006 <bitWidth>14</bitWidth>
4012 <displayName>IOG5CR
</displayName>
4013 <description>I/O group x counter register
</description>
4014 <addressOffset>0x44</addressOffset>
4016 <access>read-only
</access>
4017 <resetValue>0x00000000</resetValue>
4021 <description>Counter value
</description>
4022 <bitOffset>0</bitOffset>
4023 <bitWidth>14</bitWidth>
4029 <displayName>IOG6CR
</displayName>
4030 <description>I/O group x counter register
</description>
4031 <addressOffset>0x48</addressOffset>
4033 <access>read-only
</access>
4034 <resetValue>0x00000000</resetValue>
4038 <description>Counter value
</description>
4039 <bitOffset>0</bitOffset>
4040 <bitWidth>14</bitWidth>
4046 <displayName>IOG7CR
</displayName>
4047 <description>I/O group x counter register
</description>
4048 <addressOffset>0x4C</addressOffset>
4050 <access>read-only
</access>
4051 <resetValue>0x00000000</resetValue>
4055 <description>Counter value
</description>
4056 <bitOffset>0</bitOffset>
4057 <bitWidth>14</bitWidth>
4063 <displayName>IOG8CR
</displayName>
4064 <description>I/O group x counter register
</description>
4065 <addressOffset>0x50</addressOffset>
4067 <access>read-only
</access>
4068 <resetValue>0x00000000</resetValue>
4072 <description>Counter value
</description>
4073 <bitOffset>0</bitOffset>
4074 <bitWidth>14</bitWidth>
4082 <description>cyclic redundancy check calculation
4084 <groupName>CRC
</groupName>
4085 <baseAddress>0x40023000</baseAddress>
4087 <offset>0x0</offset>
4089 <usage>registers
</usage>
4094 <displayName>DR
</displayName>
4095 <description>Data register
</description>
4096 <addressOffset>0x0</addressOffset>
4098 <access>read-write
</access>
4099 <resetValue>0xFFFFFFFF</resetValue>
4103 <description>Data register bits
</description>
4104 <bitOffset>0</bitOffset>
4105 <bitWidth>32</bitWidth>
4111 <displayName>IDR
</displayName>
4112 <description>Independent data register
</description>
4113 <addressOffset>0x4</addressOffset>
4115 <access>read-write
</access>
4116 <resetValue>0x00000000</resetValue>
4120 <description>General-purpose
8-bit data register
4122 <bitOffset>0</bitOffset>
4123 <bitWidth>8</bitWidth>
4129 <displayName>CR
</displayName>
4130 <description>Control register
</description>
4131 <addressOffset>0x8</addressOffset>
4133 <access>read-write
</access>
4134 <resetValue>0x00000000</resetValue>
4138 <description>reset bit
</description>
4139 <bitOffset>0</bitOffset>
4140 <bitWidth>1</bitWidth>
4143 <name>POLYSIZE
</name>
4144 <description>Polynomial size
</description>
4145 <bitOffset>3</bitOffset>
4146 <bitWidth>2</bitWidth>
4150 <description>Reverse input data
</description>
4151 <bitOffset>5</bitOffset>
4152 <bitWidth>2</bitWidth>
4155 <name>REV_OUT
</name>
4156 <description>Reverse output data
</description>
4157 <bitOffset>7</bitOffset>
4158 <bitWidth>1</bitWidth>
4164 <displayName>INIT
</displayName>
4165 <description>Initial CRC value
</description>
4166 <addressOffset>0x10</addressOffset>
4168 <access>read-write
</access>
4169 <resetValue>0xFFFFFFFF</resetValue>
4173 <description>Programmable initial CRC
4175 <bitOffset>0</bitOffset>
4176 <bitWidth>32</bitWidth>
4182 <displayName>POL
</displayName>
4183 <description>CRC polynomial
</description>
4184 <addressOffset>0x14</addressOffset>
4186 <access>read-write
</access>
4187 <resetValue>0x04C11DB7</resetValue>
4191 <description>Programmable polynomial
</description>
4192 <bitOffset>0</bitOffset>
4193 <bitWidth>32</bitWidth>
4201 <description>Flash
</description>
4202 <groupName>Flash
</groupName>
4203 <baseAddress>0x40022000</baseAddress>
4205 <offset>0x0</offset>
4207 <usage>registers
</usage>
4211 <description>Flash global interrupt
</description>
4217 <displayName>ACR
</displayName>
4218 <description>Flash access control register
</description>
4219 <addressOffset>0x0</addressOffset>
4221 <resetValue>0x00000030</resetValue>
4224 <name>LATENCY
</name>
4225 <description>LATENCY
</description>
4226 <bitOffset>0</bitOffset>
4227 <bitWidth>3</bitWidth>
4228 <access>read-write
</access>
4232 <description>PRFTBE
</description>
4233 <bitOffset>4</bitOffset>
4234 <bitWidth>1</bitWidth>
4235 <access>read-write
</access>
4239 <description>PRFTBS
</description>
4240 <bitOffset>5</bitOffset>
4241 <bitWidth>1</bitWidth>
4242 <access>read-only
</access>
4248 <displayName>KEYR
</displayName>
4249 <description>Flash key register
</description>
4250 <addressOffset>0x4</addressOffset>
4252 <access>write-only
</access>
4253 <resetValue>0x00000000</resetValue>
4257 <description>Flash Key
</description>
4258 <bitOffset>0</bitOffset>
4259 <bitWidth>32</bitWidth>
4264 <name>OPTKEYR
</name>
4265 <displayName>OPTKEYR
</displayName>
4266 <description>Flash option key register
</description>
4267 <addressOffset>0x8</addressOffset>
4269 <access>write-only
</access>
4270 <resetValue>0x00000000</resetValue>
4273 <name>OPTKEYR
</name>
4274 <description>Option byte key
</description>
4275 <bitOffset>0</bitOffset>
4276 <bitWidth>32</bitWidth>
4282 <displayName>SR
</displayName>
4283 <description>Flash status register
</description>
4284 <addressOffset>0xC</addressOffset>
4286 <resetValue>0x00000000</resetValue>
4290 <description>End of operation
</description>
4291 <bitOffset>5</bitOffset>
4292 <bitWidth>1</bitWidth>
4293 <access>read-write
</access>
4297 <description>Write protection error
</description>
4298 <bitOffset>4</bitOffset>
4299 <bitWidth>1</bitWidth>
4300 <access>read-write
</access>
4304 <description>Programming error
</description>
4305 <bitOffset>2</bitOffset>
4306 <bitWidth>1</bitWidth>
4307 <access>read-write
</access>
4311 <description>Busy
</description>
4312 <bitOffset>0</bitOffset>
4313 <bitWidth>1</bitWidth>
4314 <access>read-only
</access>
4320 <displayName>CR
</displayName>
4321 <description>Flash control register
</description>
4322 <addressOffset>0x10</addressOffset>
4324 <access>read-write
</access>
4325 <resetValue>0x00000080</resetValue>
4328 <name>FORCE_OPTLOAD
</name>
4329 <description>Force option byte loading
</description>
4330 <bitOffset>13</bitOffset>
4331 <bitWidth>1</bitWidth>
4335 <description>End of operation interrupt
4336 enable
</description>
4337 <bitOffset>12</bitOffset>
4338 <bitWidth>1</bitWidth>
4342 <description>Error interrupt enable
</description>
4343 <bitOffset>10</bitOffset>
4344 <bitWidth>1</bitWidth>
4348 <description>Option bytes write enable
</description>
4349 <bitOffset>9</bitOffset>
4350 <bitWidth>1</bitWidth>
4354 <description>Lock
</description>
4355 <bitOffset>7</bitOffset>
4356 <bitWidth>1</bitWidth>
4360 <description>Start
</description>
4361 <bitOffset>6</bitOffset>
4362 <bitWidth>1</bitWidth>
4366 <description>Option byte erase
</description>
4367 <bitOffset>5</bitOffset>
4368 <bitWidth>1</bitWidth>
4372 <description>Option byte programming
</description>
4373 <bitOffset>4</bitOffset>
4374 <bitWidth>1</bitWidth>
4378 <description>Mass erase
</description>
4379 <bitOffset>2</bitOffset>
4380 <bitWidth>1</bitWidth>
4384 <description>Page erase
</description>
4385 <bitOffset>1</bitOffset>
4386 <bitWidth>1</bitWidth>
4390 <description>Programming
</description>
4391 <bitOffset>0</bitOffset>
4392 <bitWidth>1</bitWidth>
4398 <displayName>AR
</displayName>
4399 <description>Flash address register
</description>
4400 <addressOffset>0x14</addressOffset>
4402 <access>write-only
</access>
4403 <resetValue>0x00000000</resetValue>
4407 <description>Flash address
</description>
4408 <bitOffset>0</bitOffset>
4409 <bitWidth>32</bitWidth>
4415 <displayName>OBR
</displayName>
4416 <description>Option byte register
</description>
4417 <addressOffset>0x1C</addressOffset>
4419 <access>read-only
</access>
4420 <resetValue>0xFFFFFF02</resetValue>
4424 <description>Option byte error
</description>
4425 <bitOffset>0</bitOffset>
4426 <bitWidth>1</bitWidth>
4429 <name>LEVEL1_PROT
</name>
4430 <description>Level
1 protection status
</description>
4431 <bitOffset>1</bitOffset>
4432 <bitWidth>1</bitWidth>
4435 <name>LEVEL2_PROT
</name>
4436 <description>Level
2 protection status
</description>
4437 <bitOffset>2</bitOffset>
4438 <bitWidth>1</bitWidth>
4442 <description>WDG_SW
</description>
4443 <bitOffset>8</bitOffset>
4444 <bitWidth>1</bitWidth>
4447 <name>nRST_STOP
</name>
4448 <description>nRST_STOP
</description>
4449 <bitOffset>9</bitOffset>
4450 <bitWidth>1</bitWidth>
4453 <name>nRST_STDBY
</name>
4454 <description>nRST_STDBY
</description>
4455 <bitOffset>10</bitOffset>
4456 <bitWidth>1</bitWidth>
4460 <description>BOOT1
</description>
4461 <bitOffset>12</bitOffset>
4462 <bitWidth>1</bitWidth>
4465 <name>VDDA_MONITOR
</name>
4466 <description>VDDA_MONITOR
</description>
4467 <bitOffset>13</bitOffset>
4468 <bitWidth>1</bitWidth>
4471 <name>SRAM_PARITY_CHECK
</name>
4472 <description>SRAM_PARITY_CHECK
</description>
4473 <bitOffset>14</bitOffset>
4474 <bitWidth>1</bitWidth>
4478 <description>Data0
</description>
4479 <bitOffset>16</bitOffset>
4480 <bitWidth>8</bitWidth>
4484 <description>Data1
</description>
4485 <bitOffset>24</bitOffset>
4486 <bitWidth>8</bitWidth>
4492 <displayName>WRPR
</displayName>
4493 <description>Write protection register
</description>
4494 <addressOffset>0x20</addressOffset>
4496 <access>read-only
</access>
4497 <resetValue>0xFFFFFFFF</resetValue>
4501 <description>Write protect
</description>
4502 <bitOffset>0</bitOffset>
4503 <bitWidth>32</bitWidth>
4511 <description>Reset and clock control
</description>
4512 <groupName>RCC
</groupName>
4513 <baseAddress>0x40021000</baseAddress>
4515 <offset>0x0</offset>
4517 <usage>registers
</usage>
4521 <description>RCC global interrupt
</description>
4527 <displayName>CR
</displayName>
4528 <description>Clock control register
</description>
4529 <addressOffset>0x0</addressOffset>
4531 <resetValue>0x00000083</resetValue>
4535 <description>Internal High Speed clock
4536 enable
</description>
4537 <bitOffset>0</bitOffset>
4538 <bitWidth>1</bitWidth>
4539 <access>read-write
</access>
4543 <description>Internal High Speed clock ready
4545 <bitOffset>1</bitOffset>
4546 <bitWidth>1</bitWidth>
4547 <access>read-only
</access>
4550 <name>HSITRIM
</name>
4551 <description>Internal High Speed clock
4552 trimming
</description>
4553 <bitOffset>3</bitOffset>
4554 <bitWidth>5</bitWidth>
4555 <access>read-write
</access>
4559 <description>Internal High Speed clock
4560 Calibration
</description>
4561 <bitOffset>8</bitOffset>
4562 <bitWidth>8</bitWidth>
4563 <access>read-only
</access>
4567 <description>External High Speed clock
4568 enable
</description>
4569 <bitOffset>16</bitOffset>
4570 <bitWidth>1</bitWidth>
4571 <access>read-write
</access>
4575 <description>External High Speed clock ready
4577 <bitOffset>17</bitOffset>
4578 <bitWidth>1</bitWidth>
4579 <access>read-only
</access>
4583 <description>External High Speed clock
4584 Bypass
</description>
4585 <bitOffset>18</bitOffset>
4586 <bitWidth>1</bitWidth>
4587 <access>read-write
</access>
4591 <description>Clock Security System
4592 enable
</description>
4593 <bitOffset>19</bitOffset>
4594 <bitWidth>1</bitWidth>
4595 <access>read-write
</access>
4599 <description>PLL enable
</description>
4600 <bitOffset>24</bitOffset>
4601 <bitWidth>1</bitWidth>
4602 <access>read-write
</access>
4606 <description>PLL clock ready flag
</description>
4607 <bitOffset>25</bitOffset>
4608 <bitWidth>1</bitWidth>
4609 <access>read-only
</access>
4615 <displayName>CFGR
</displayName>
4616 <description>Clock configuration register
4617 (RCC_CFGR)
</description>
4618 <addressOffset>0x4</addressOffset>
4620 <resetValue>0x00000000</resetValue>
4624 <description>System clock Switch
</description>
4625 <bitOffset>0</bitOffset>
4626 <bitWidth>2</bitWidth>
4627 <access>read-write
</access>
4631 <description>System Clock Switch Status
</description>
4632 <bitOffset>2</bitOffset>
4633 <bitWidth>2</bitWidth>
4634 <access>read-only
</access>
4638 <description>AHB prescaler
</description>
4639 <bitOffset>4</bitOffset>
4640 <bitWidth>4</bitWidth>
4641 <access>read-write
</access>
4645 <description>APB Low speed prescaler
4646 (APB1)
</description>
4647 <bitOffset>8</bitOffset>
4648 <bitWidth>3</bitWidth>
4649 <access>read-write
</access>
4653 <description>APB high speed prescaler
4654 (APB2)
</description>
4655 <bitOffset>11</bitOffset>
4656 <bitWidth>3</bitWidth>
4657 <access>read-write
</access>
4661 <description>PLL entry clock source
</description>
4662 <bitOffset>15</bitOffset>
4663 <bitWidth>2</bitWidth>
4664 <access>read-write
</access>
4667 <name>PLLXTPRE
</name>
4668 <description>HSE divider for PLL entry
</description>
4669 <bitOffset>17</bitOffset>
4670 <bitWidth>1</bitWidth>
4671 <access>read-write
</access>
4675 <description>PLL Multiplication Factor
</description>
4676 <bitOffset>18</bitOffset>
4677 <bitWidth>4</bitWidth>
4678 <access>read-write
</access>
4681 <name>USBPRES
</name>
4682 <description>USB prescaler
</description>
4683 <bitOffset>22</bitOffset>
4684 <bitWidth>1</bitWidth>
4685 <access>read-write
</access>
4689 <description>Microcontroller clock
4690 output
</description>
4691 <bitOffset>24</bitOffset>
4692 <bitWidth>3</bitWidth>
4693 <access>read-write
</access>
4697 <description>Microcontroller Clock Output
4699 <bitOffset>28</bitOffset>
4700 <bitWidth>1</bitWidth>
4701 <access>read-only
</access>
4705 <description>I2S external clock source
4706 selection
</description>
4707 <bitOffset>23</bitOffset>
4708 <bitWidth>1</bitWidth>
4709 <access>read-write
</access>
4715 <displayName>CIR
</displayName>
4716 <description>Clock interrupt register
4717 (RCC_CIR)
</description>
4718 <addressOffset>0x8</addressOffset>
4720 <resetValue>0x00000000</resetValue>
4723 <name>LSIRDYF
</name>
4724 <description>LSI Ready Interrupt flag
</description>
4725 <bitOffset>0</bitOffset>
4726 <bitWidth>1</bitWidth>
4727 <access>read-only
</access>
4730 <name>LSERDYF
</name>
4731 <description>LSE Ready Interrupt flag
</description>
4732 <bitOffset>1</bitOffset>
4733 <bitWidth>1</bitWidth>
4734 <access>read-only
</access>
4737 <name>HSIRDYF
</name>
4738 <description>HSI Ready Interrupt flag
</description>
4739 <bitOffset>2</bitOffset>
4740 <bitWidth>1</bitWidth>
4741 <access>read-only
</access>
4744 <name>HSERDYF
</name>
4745 <description>HSE Ready Interrupt flag
</description>
4746 <bitOffset>3</bitOffset>
4747 <bitWidth>1</bitWidth>
4748 <access>read-only
</access>
4751 <name>PLLRDYF
</name>
4752 <description>PLL Ready Interrupt flag
</description>
4753 <bitOffset>4</bitOffset>
4754 <bitWidth>1</bitWidth>
4755 <access>read-only
</access>
4759 <description>Clock Security System Interrupt
4761 <bitOffset>7</bitOffset>
4762 <bitWidth>1</bitWidth>
4763 <access>read-only
</access>
4766 <name>LSIRDYIE
</name>
4767 <description>LSI Ready Interrupt Enable
</description>
4768 <bitOffset>8</bitOffset>
4769 <bitWidth>1</bitWidth>
4770 <access>read-write
</access>
4773 <name>LSERDYIE
</name>
4774 <description>LSE Ready Interrupt Enable
</description>
4775 <bitOffset>9</bitOffset>
4776 <bitWidth>1</bitWidth>
4777 <access>read-write
</access>
4780 <name>HSIRDYIE
</name>
4781 <description>HSI Ready Interrupt Enable
</description>
4782 <bitOffset>10</bitOffset>
4783 <bitWidth>1</bitWidth>
4784 <access>read-write
</access>
4787 <name>HSERDYIE
</name>
4788 <description>HSE Ready Interrupt Enable
</description>
4789 <bitOffset>11</bitOffset>
4790 <bitWidth>1</bitWidth>
4791 <access>read-write
</access>
4794 <name>PLLRDYIE
</name>
4795 <description>PLL Ready Interrupt Enable
</description>
4796 <bitOffset>12</bitOffset>
4797 <bitWidth>1</bitWidth>
4798 <access>read-write
</access>
4801 <name>LSIRDYC
</name>
4802 <description>LSI Ready Interrupt Clear
</description>
4803 <bitOffset>16</bitOffset>
4804 <bitWidth>1</bitWidth>
4805 <access>write-only
</access>
4808 <name>LSERDYC
</name>
4809 <description>LSE Ready Interrupt Clear
</description>
4810 <bitOffset>17</bitOffset>
4811 <bitWidth>1</bitWidth>
4812 <access>write-only
</access>
4815 <name>HSIRDYC
</name>
4816 <description>HSI Ready Interrupt Clear
</description>
4817 <bitOffset>18</bitOffset>
4818 <bitWidth>1</bitWidth>
4819 <access>write-only
</access>
4822 <name>HSERDYC
</name>
4823 <description>HSE Ready Interrupt Clear
</description>
4824 <bitOffset>19</bitOffset>
4825 <bitWidth>1</bitWidth>
4826 <access>write-only
</access>
4829 <name>PLLRDYC
</name>
4830 <description>PLL Ready Interrupt Clear
</description>
4831 <bitOffset>20</bitOffset>
4832 <bitWidth>1</bitWidth>
4833 <access>write-only
</access>
4837 <description>Clock security system interrupt
4839 <bitOffset>23</bitOffset>
4840 <bitWidth>1</bitWidth>
4841 <access>write-only
</access>
4846 <name>APB2RSTR
</name>
4847 <displayName>APB2RSTR
</displayName>
4848 <description>APB2 peripheral reset register
4849 (RCC_APB2RSTR)
</description>
4850 <addressOffset>0xC</addressOffset>
4852 <access>read-write
</access>
4853 <resetValue>0x00000000</resetValue>
4856 <name>SYSCFGRST
</name>
4857 <description>SYSCFG and COMP reset
</description>
4858 <bitOffset>0</bitOffset>
4859 <bitWidth>1</bitWidth>
4862 <name>TIM1RST
</name>
4863 <description>TIM1 timer reset
</description>
4864 <bitOffset>11</bitOffset>
4865 <bitWidth>1</bitWidth>
4868 <name>SPI1RST
</name>
4869 <description>SPI
1 reset
</description>
4870 <bitOffset>12</bitOffset>
4871 <bitWidth>1</bitWidth>
4874 <name>TIM8RST
</name>
4875 <description>TIM8 timer reset
</description>
4876 <bitOffset>13</bitOffset>
4877 <bitWidth>1</bitWidth>
4880 <name>USART1RST
</name>
4881 <description>USART1 reset
</description>
4882 <bitOffset>14</bitOffset>
4883 <bitWidth>1</bitWidth>
4886 <name>TIM15RST
</name>
4887 <description>TIM15 timer reset
</description>
4888 <bitOffset>16</bitOffset>
4889 <bitWidth>1</bitWidth>
4892 <name>TIM16RST
</name>
4893 <description>TIM16 timer reset
</description>
4894 <bitOffset>17</bitOffset>
4895 <bitWidth>1</bitWidth>
4898 <name>TIM17RST
</name>
4899 <description>TIM17 timer reset
</description>
4900 <bitOffset>18</bitOffset>
4901 <bitWidth>1</bitWidth>
4906 <name>APB1RSTR
</name>
4907 <displayName>APB1RSTR
</displayName>
4908 <description>APB1 peripheral reset register
4909 (RCC_APB1RSTR)
</description>
4910 <addressOffset>0x10</addressOffset>
4912 <access>read-write
</access>
4913 <resetValue>0x00000000</resetValue>
4916 <name>TIM2RST
</name>
4917 <description>Timer
2 reset
</description>
4918 <bitOffset>0</bitOffset>
4919 <bitWidth>1</bitWidth>
4922 <name>TIM3RST
</name>
4923 <description>Timer
3 reset
</description>
4924 <bitOffset>1</bitOffset>
4925 <bitWidth>1</bitWidth>
4928 <name>TIM4RST
</name>
4929 <description>Timer
14 reset
</description>
4930 <bitOffset>2</bitOffset>
4931 <bitWidth>1</bitWidth>
4934 <name>TIM6RST
</name>
4935 <description>Timer
6 reset
</description>
4936 <bitOffset>4</bitOffset>
4937 <bitWidth>1</bitWidth>
4940 <name>TIM7RST
</name>
4941 <description>Timer
7 reset
</description>
4942 <bitOffset>5</bitOffset>
4943 <bitWidth>1</bitWidth>
4946 <name>WWDGRST
</name>
4947 <description>Window watchdog reset
</description>
4948 <bitOffset>11</bitOffset>
4949 <bitWidth>1</bitWidth>
4952 <name>SPI2RST
</name>
4953 <description>SPI2 reset
</description>
4954 <bitOffset>14</bitOffset>
4955 <bitWidth>1</bitWidth>
4958 <name>SPI3RST
</name>
4959 <description>SPI3 reset
</description>
4960 <bitOffset>15</bitOffset>
4961 <bitWidth>1</bitWidth>
4964 <name>USART2RST
</name>
4965 <description>USART
2 reset
</description>
4966 <bitOffset>17</bitOffset>
4967 <bitWidth>1</bitWidth>
4970 <name>USART3RST
</name>
4971 <description>USART3 reset
</description>
4972 <bitOffset>18</bitOffset>
4973 <bitWidth>1</bitWidth>
4976 <name>UART4RST
</name>
4977 <description>UART
4 reset
</description>
4978 <bitOffset>19</bitOffset>
4979 <bitWidth>1</bitWidth>
4982 <name>UART5RST
</name>
4983 <description>UART
5 reset
</description>
4984 <bitOffset>20</bitOffset>
4985 <bitWidth>1</bitWidth>
4988 <name>I2C1RST
</name>
4989 <description>I2C1 reset
</description>
4990 <bitOffset>21</bitOffset>
4991 <bitWidth>1</bitWidth>
4994 <name>I2C2RST
</name>
4995 <description>I2C2 reset
</description>
4996 <bitOffset>22</bitOffset>
4997 <bitWidth>1</bitWidth>
5001 <description>USB reset
</description>
5002 <bitOffset>23</bitOffset>
5003 <bitWidth>1</bitWidth>
5007 <description>CAN reset
</description>
5008 <bitOffset>25</bitOffset>
5009 <bitWidth>1</bitWidth>
5013 <description>Power interface reset
</description>
5014 <bitOffset>28</bitOffset>
5015 <bitWidth>1</bitWidth>
5019 <description>DAC interface reset
</description>
5020 <bitOffset>29</bitOffset>
5021 <bitWidth>1</bitWidth>
5024 <name>I2C3RST
</name>
5025 <description>I2C3 reset
</description>
5026 <bitOffset>30</bitOffset>
5027 <bitWidth>1</bitWidth>
5033 <displayName>AHBENR
</displayName>
5034 <description>AHB Peripheral Clock enable register
5035 (RCC_AHBENR)
</description>
5036 <addressOffset>0x14</addressOffset>
5038 <access>read-write
</access>
5039 <resetValue>0x00000014</resetValue>
5043 <description>DMA1 clock enable
</description>
5044 <bitOffset>0</bitOffset>
5045 <bitWidth>1</bitWidth>
5049 <description>DMA2 clock enable
</description>
5050 <bitOffset>1</bitOffset>
5051 <bitWidth>1</bitWidth>
5055 <description>SRAM interface clock
5056 enable
</description>
5057 <bitOffset>2</bitOffset>
5058 <bitWidth>1</bitWidth>
5061 <name>FLITFEN
</name>
5062 <description>FLITF clock enable
</description>
5063 <bitOffset>4</bitOffset>
5064 <bitWidth>1</bitWidth>
5068 <description>FMC clock enable
</description>
5069 <bitOffset>5</bitOffset>
5070 <bitWidth>1</bitWidth>
5074 <description>CRC clock enable
</description>
5075 <bitOffset>6</bitOffset>
5076 <bitWidth>1</bitWidth>
5080 <description>IO port H clock enable
</description>
5081 <bitOffset>16</bitOffset>
5082 <bitWidth>1</bitWidth>
5086 <description>I/O port A clock enable
</description>
5087 <bitOffset>17</bitOffset>
5088 <bitWidth>1</bitWidth>
5092 <description>I/O port B clock enable
</description>
5093 <bitOffset>18</bitOffset>
5094 <bitWidth>1</bitWidth>
5098 <description>I/O port C clock enable
</description>
5099 <bitOffset>19</bitOffset>
5100 <bitWidth>1</bitWidth>
5104 <description>I/O port D clock enable
</description>
5105 <bitOffset>20</bitOffset>
5106 <bitWidth>1</bitWidth>
5110 <description>I/O port E clock enable
</description>
5111 <bitOffset>21</bitOffset>
5112 <bitWidth>1</bitWidth>
5116 <description>I/O port F clock enable
</description>
5117 <bitOffset>22</bitOffset>
5118 <bitWidth>1</bitWidth>
5122 <description>I/O port G clock enable
</description>
5123 <bitOffset>23</bitOffset>
5124 <bitWidth>1</bitWidth>
5128 <description>Touch sensing controller clock
5129 enable
</description>
5130 <bitOffset>24</bitOffset>
5131 <bitWidth>1</bitWidth>
5134 <name>ADC12EN
</name>
5135 <description>ADC1 and ADC2 clock enable
</description>
5136 <bitOffset>28</bitOffset>
5137 <bitWidth>1</bitWidth>
5140 <name>ADC34EN
</name>
5141 <description>ADC3 and ADC4 clock enable
</description>
5142 <bitOffset>29</bitOffset>
5143 <bitWidth>1</bitWidth>
5148 <name>APB2ENR
</name>
5149 <displayName>APB2ENR
</displayName>
5150 <description>APB2 peripheral clock enable register
5151 (RCC_APB2ENR)
</description>
5152 <addressOffset>0x18</addressOffset>
5154 <access>read-write
</access>
5155 <resetValue>0x00000000</resetValue>
5158 <name>SYSCFGEN
</name>
5159 <description>SYSCFG clock enable
</description>
5160 <bitOffset>0</bitOffset>
5161 <bitWidth>1</bitWidth>
5165 <description>TIM1 Timer clock enable
</description>
5166 <bitOffset>11</bitOffset>
5167 <bitWidth>1</bitWidth>
5171 <description>SPI
1 clock enable
</description>
5172 <bitOffset>12</bitOffset>
5173 <bitWidth>1</bitWidth>
5177 <description>TIM8 Timer clock enable
</description>
5178 <bitOffset>13</bitOffset>
5179 <bitWidth>1</bitWidth>
5182 <name>USART1EN
</name>
5183 <description>USART1 clock enable
</description>
5184 <bitOffset>14</bitOffset>
5185 <bitWidth>1</bitWidth>
5188 <name>TIM15EN
</name>
5189 <description>TIM15 timer clock enable
</description>
5190 <bitOffset>16</bitOffset>
5191 <bitWidth>1</bitWidth>
5194 <name>TIM16EN
</name>
5195 <description>TIM16 timer clock enable
</description>
5196 <bitOffset>17</bitOffset>
5197 <bitWidth>1</bitWidth>
5200 <name>TIM17EN
</name>
5201 <description>TIM17 timer clock enable
</description>
5202 <bitOffset>18</bitOffset>
5203 <bitWidth>1</bitWidth>
5208 <name>APB1ENR
</name>
5209 <displayName>APB1ENR
</displayName>
5210 <description>APB1 peripheral clock enable register
5211 (RCC_APB1ENR)
</description>
5212 <addressOffset>0x1C</addressOffset>
5214 <access>read-write
</access>
5215 <resetValue>0x00000000</resetValue>
5219 <description>Timer
2 clock enable
</description>
5220 <bitOffset>0</bitOffset>
5221 <bitWidth>1</bitWidth>
5225 <description>Timer
3 clock enable
</description>
5226 <bitOffset>1</bitOffset>
5227 <bitWidth>1</bitWidth>
5231 <description>Timer
4 clock enable
</description>
5232 <bitOffset>2</bitOffset>
5233 <bitWidth>1</bitWidth>
5237 <description>Timer
6 clock enable
</description>
5238 <bitOffset>4</bitOffset>
5239 <bitWidth>1</bitWidth>
5243 <description>Timer
7 clock enable
</description>
5244 <bitOffset>5</bitOffset>
5245 <bitWidth>1</bitWidth>
5249 <description>Window watchdog clock
5250 enable
</description>
5251 <bitOffset>11</bitOffset>
5252 <bitWidth>1</bitWidth>
5256 <description>SPI
2 clock enable
</description>
5257 <bitOffset>14</bitOffset>
5258 <bitWidth>1</bitWidth>
5262 <description>SPI
3 clock enable
</description>
5263 <bitOffset>15</bitOffset>
5264 <bitWidth>1</bitWidth>
5267 <name>USART2EN
</name>
5268 <description>USART
2 clock enable
</description>
5269 <bitOffset>17</bitOffset>
5270 <bitWidth>1</bitWidth>
5273 <name>USART3EN
</name>
5274 <description>USART
3 clock enable
</description>
5275 <bitOffset>18</bitOffset>
5276 <bitWidth>1</bitWidth>
5279 <name>USART4EN
</name>
5280 <description>USART
4 clock enable
</description>
5281 <bitOffset>19</bitOffset>
5282 <bitWidth>1</bitWidth>
5285 <name>USART5EN
</name>
5286 <description>USART
5 clock enable
</description>
5287 <bitOffset>20</bitOffset>
5288 <bitWidth>1</bitWidth>
5292 <description>I2C
1 clock enable
</description>
5293 <bitOffset>21</bitOffset>
5294 <bitWidth>1</bitWidth>
5298 <description>I2C
2 clock enable
</description>
5299 <bitOffset>22</bitOffset>
5300 <bitWidth>1</bitWidth>
5304 <description>USB clock enable
</description>
5305 <bitOffset>23</bitOffset>
5306 <bitWidth>1</bitWidth>
5310 <description>CAN clock enable
</description>
5311 <bitOffset>25</bitOffset>
5312 <bitWidth>1</bitWidth>
5316 <description>DAC2 interface clock
5317 enable
</description>
5318 <bitOffset>26</bitOffset>
5319 <bitWidth>1</bitWidth>
5323 <description>Power interface clock
5324 enable
</description>
5325 <bitOffset>28</bitOffset>
5326 <bitWidth>1</bitWidth>
5330 <description>DAC interface clock enable
</description>
5331 <bitOffset>29</bitOffset>
5332 <bitWidth>1</bitWidth>
5336 <description>I2C3 clock enable
</description>
5337 <bitOffset>30</bitOffset>
5338 <bitWidth>1</bitWidth>
5344 <displayName>BDCR
</displayName>
5345 <description>Backup domain control register
5346 (RCC_BDCR)
</description>
5347 <addressOffset>0x20</addressOffset>
5349 <resetValue>0x00000000</resetValue>
5353 <description>External Low Speed oscillator
5354 enable
</description>
5355 <bitOffset>0</bitOffset>
5356 <bitWidth>1</bitWidth>
5357 <access>read-write
</access>
5361 <description>External Low Speed oscillator
5363 <bitOffset>1</bitOffset>
5364 <bitWidth>1</bitWidth>
5365 <access>read-only
</access>
5369 <description>External Low Speed oscillator
5370 bypass
</description>
5371 <bitOffset>2</bitOffset>
5372 <bitWidth>1</bitWidth>
5373 <access>read-write
</access>
5377 <description>LSE oscillator drive
5378 capability
</description>
5379 <bitOffset>3</bitOffset>
5380 <bitWidth>2</bitWidth>
5381 <access>read-write
</access>
5385 <description>RTC clock source selection
</description>
5386 <bitOffset>8</bitOffset>
5387 <bitWidth>2</bitWidth>
5388 <access>read-write
</access>
5392 <description>RTC clock enable
</description>
5393 <bitOffset>15</bitOffset>
5394 <bitWidth>1</bitWidth>
5395 <access>read-write
</access>
5399 <description>Backup domain software
5401 <bitOffset>16</bitOffset>
5402 <bitWidth>1</bitWidth>
5403 <access>read-write
</access>
5409 <displayName>CSR
</displayName>
5410 <description>Control/status register
5411 (RCC_CSR)
</description>
5412 <addressOffset>0x24</addressOffset>
5414 <resetValue>0x0C000000</resetValue>
5418 <description>Internal low speed oscillator
5419 enable
</description>
5420 <bitOffset>0</bitOffset>
5421 <bitWidth>1</bitWidth>
5422 <access>read-write
</access>
5426 <description>Internal low speed oscillator
5428 <bitOffset>1</bitOffset>
5429 <bitWidth>1</bitWidth>
5430 <access>read-only
</access>
5434 <description>Remove reset flag
</description>
5435 <bitOffset>24</bitOffset>
5436 <bitWidth>1</bitWidth>
5437 <access>read-write
</access>
5440 <name>OBLRSTF
</name>
5441 <description>Option byte loader reset
5443 <bitOffset>25</bitOffset>
5444 <bitWidth>1</bitWidth>
5445 <access>read-write
</access>
5448 <name>PINRSTF
</name>
5449 <description>PIN reset flag
</description>
5450 <bitOffset>26</bitOffset>
5451 <bitWidth>1</bitWidth>
5452 <access>read-write
</access>
5455 <name>PORRSTF
</name>
5456 <description>POR/PDR reset flag
</description>
5457 <bitOffset>27</bitOffset>
5458 <bitWidth>1</bitWidth>
5459 <access>read-write
</access>
5462 <name>SFTRSTF
</name>
5463 <description>Software reset flag
</description>
5464 <bitOffset>28</bitOffset>
5465 <bitWidth>1</bitWidth>
5466 <access>read-write
</access>
5469 <name>IWDGRSTF
</name>
5470 <description>Independent watchdog reset
5472 <bitOffset>29</bitOffset>
5473 <bitWidth>1</bitWidth>
5474 <access>read-write
</access>
5477 <name>WWDGRSTF
</name>
5478 <description>Window watchdog reset flag
</description>
5479 <bitOffset>30</bitOffset>
5480 <bitWidth>1</bitWidth>
5481 <access>read-write
</access>
5484 <name>LPWRRSTF
</name>
5485 <description>Low-power reset flag
</description>
5486 <bitOffset>31</bitOffset>
5487 <bitWidth>1</bitWidth>
5488 <access>read-write
</access>
5493 <name>AHBRSTR
</name>
5494 <displayName>AHBRSTR
</displayName>
5495 <description>AHB peripheral reset register
</description>
5496 <addressOffset>0x28</addressOffset>
5498 <access>read-write
</access>
5499 <resetValue>0x00000000</resetValue>
5503 <description>FMC reset
</description>
5504 <bitOffset>5</bitOffset>
5505 <bitWidth>1</bitWidth>
5508 <name>IOPHRST
</name>
5509 <description>I/O port H reset
</description>
5510 <bitOffset>16</bitOffset>
5511 <bitWidth>1</bitWidth>
5514 <name>IOPARST
</name>
5515 <description>I/O port A reset
</description>
5516 <bitOffset>17</bitOffset>
5517 <bitWidth>1</bitWidth>
5520 <name>IOPBRST
</name>
5521 <description>I/O port B reset
</description>
5522 <bitOffset>18</bitOffset>
5523 <bitWidth>1</bitWidth>
5526 <name>IOPCRST
</name>
5527 <description>I/O port C reset
</description>
5528 <bitOffset>19</bitOffset>
5529 <bitWidth>1</bitWidth>
5532 <name>IOPDRST
</name>
5533 <description>I/O port D reset
</description>
5534 <bitOffset>20</bitOffset>
5535 <bitWidth>1</bitWidth>
5538 <name>IOPERST
</name>
5539 <description>I/O port E reset
</description>
5540 <bitOffset>21</bitOffset>
5541 <bitWidth>1</bitWidth>
5544 <name>IOPFRST
</name>
5545 <description>I/O port F reset
</description>
5546 <bitOffset>22</bitOffset>
5547 <bitWidth>1</bitWidth>
5550 <name>IOPGRST
</name>
5551 <description>Touch sensing controller
5553 <bitOffset>23</bitOffset>
5554 <bitWidth>1</bitWidth>
5558 <description>Touch sensing controller
5560 <bitOffset>24</bitOffset>
5561 <bitWidth>1</bitWidth>
5564 <name>ADC12RST
</name>
5565 <description>ADC1 and ADC2 reset
</description>
5566 <bitOffset>28</bitOffset>
5567 <bitWidth>1</bitWidth>
5570 <name>ADC34RST
</name>
5571 <description>ADC3 and ADC4 reset
</description>
5572 <bitOffset>29</bitOffset>
5573 <bitWidth>1</bitWidth>
5579 <displayName>CFGR2
</displayName>
5580 <description>Clock configuration register
2</description>
5581 <addressOffset>0x2C</addressOffset>
5583 <access>read-write
</access>
5584 <resetValue>0x00000000</resetValue>
5588 <description>PREDIV division factor
</description>
5589 <bitOffset>0</bitOffset>
5590 <bitWidth>4</bitWidth>
5593 <name>ADC12PRES
</name>
5594 <description>ADC1 and ADC2 prescaler
</description>
5595 <bitOffset>4</bitOffset>
5596 <bitWidth>5</bitWidth>
5599 <name>ADC34PRES
</name>
5600 <description>ADC3 and ADC4 prescaler
</description>
5601 <bitOffset>9</bitOffset>
5602 <bitWidth>5</bitWidth>
5608 <displayName>CFGR3
</displayName>
5609 <description>Clock configuration register
3</description>
5610 <addressOffset>0x30</addressOffset>
5612 <access>read-write
</access>
5613 <resetValue>0x00000000</resetValue>
5616 <name>USART1SW
</name>
5617 <description>USART1 clock source
5618 selection
</description>
5619 <bitOffset>0</bitOffset>
5620 <bitWidth>2</bitWidth>
5624 <description>I2C1 clock source
5625 selection
</description>
5626 <bitOffset>4</bitOffset>
5627 <bitWidth>1</bitWidth>
5631 <description>I2C2 clock source
5632 selection
</description>
5633 <bitOffset>5</bitOffset>
5634 <bitWidth>1</bitWidth>
5638 <description>I2C3 clock source
5639 selection
</description>
5640 <bitOffset>6</bitOffset>
5641 <bitWidth>1</bitWidth>
5644 <name>USART2SW
</name>
5645 <description>USART2 clock source
5646 selection
</description>
5647 <bitOffset>16</bitOffset>
5648 <bitWidth>2</bitWidth>
5651 <name>USART3SW
</name>
5652 <description>USART3 clock source
5653 selection
</description>
5654 <bitOffset>18</bitOffset>
5655 <bitWidth>2</bitWidth>
5659 <description>Timer1 clock source
5660 selection
</description>
5661 <bitOffset>8</bitOffset>
5662 <bitWidth>1</bitWidth>
5666 <description>Timer8 clock source
5667 selection
</description>
5668 <bitOffset>9</bitOffset>
5669 <bitWidth>1</bitWidth>
5672 <name>UART4SW
</name>
5673 <description>UART4 clock source
5674 selection
</description>
5675 <bitOffset>20</bitOffset>
5676 <bitWidth>2</bitWidth>
5679 <name>UART5SW
</name>
5680 <description>UART5 clock source
5681 selection
</description>
5682 <bitOffset>22</bitOffset>
5683 <bitWidth>2</bitWidth>
5691 <description>DMA controller
1</description>
5692 <groupName>DMA
</groupName>
5693 <baseAddress>0x40020000</baseAddress>
5695 <offset>0x0</offset>
5697 <usage>registers
</usage>
5700 <name>DMA1_CH1
</name>
5701 <description>DMA1 channel
1 interrupt
</description>
5705 <name>DMA1_CH2
</name>
5706 <description>DMA1 channel
2 interrupt
</description>
5710 <name>DMA1_CH3
</name>
5711 <description>DMA1 channel
3 interrupt
</description>
5715 <name>DMA1_CH4
</name>
5716 <description>DMA1 channel
4 interrupt
</description>
5720 <name>DMA1_CH5
</name>
5721 <description>DMA1 channel
5 interrupt
</description>
5725 <name>DMA1_CH6
</name>
5726 <description>DMA1 channel
6 interrupt
</description>
5730 <name>DMA1_CH7
</name>
5731 <description>DMA1 channel
7interrupt
</description>
5737 <displayName>ISR
</displayName>
5738 <description>DMA interrupt status register
5739 (DMA_ISR)
</description>
5740 <addressOffset>0x0</addressOffset>
5742 <access>read-only
</access>
5743 <resetValue>0x00000000</resetValue>
5747 <description>Channel
1 Global interrupt
5749 <bitOffset>0</bitOffset>
5750 <bitWidth>1</bitWidth>
5754 <description>Channel
1 Transfer Complete
5756 <bitOffset>1</bitOffset>
5757 <bitWidth>1</bitWidth>
5761 <description>Channel
1 Half Transfer Complete
5763 <bitOffset>2</bitOffset>
5764 <bitWidth>1</bitWidth>
5768 <description>Channel
1 Transfer Error
5770 <bitOffset>3</bitOffset>
5771 <bitWidth>1</bitWidth>
5775 <description>Channel
2 Global interrupt
5777 <bitOffset>4</bitOffset>
5778 <bitWidth>1</bitWidth>
5782 <description>Channel
2 Transfer Complete
5784 <bitOffset>5</bitOffset>
5785 <bitWidth>1</bitWidth>
5789 <description>Channel
2 Half Transfer Complete
5791 <bitOffset>6</bitOffset>
5792 <bitWidth>1</bitWidth>
5796 <description>Channel
2 Transfer Error
5798 <bitOffset>7</bitOffset>
5799 <bitWidth>1</bitWidth>
5803 <description>Channel
3 Global interrupt
5805 <bitOffset>8</bitOffset>
5806 <bitWidth>1</bitWidth>
5810 <description>Channel
3 Transfer Complete
5812 <bitOffset>9</bitOffset>
5813 <bitWidth>1</bitWidth>
5817 <description>Channel
3 Half Transfer Complete
5819 <bitOffset>10</bitOffset>
5820 <bitWidth>1</bitWidth>
5824 <description>Channel
3 Transfer Error
5826 <bitOffset>11</bitOffset>
5827 <bitWidth>1</bitWidth>
5831 <description>Channel
4 Global interrupt
5833 <bitOffset>12</bitOffset>
5834 <bitWidth>1</bitWidth>
5838 <description>Channel
4 Transfer Complete
5840 <bitOffset>13</bitOffset>
5841 <bitWidth>1</bitWidth>
5845 <description>Channel
4 Half Transfer Complete
5847 <bitOffset>14</bitOffset>
5848 <bitWidth>1</bitWidth>
5852 <description>Channel
4 Transfer Error
5854 <bitOffset>15</bitOffset>
5855 <bitWidth>1</bitWidth>
5859 <description>Channel
5 Global interrupt
5861 <bitOffset>16</bitOffset>
5862 <bitWidth>1</bitWidth>
5866 <description>Channel
5 Transfer Complete
5868 <bitOffset>17</bitOffset>
5869 <bitWidth>1</bitWidth>
5873 <description>Channel
5 Half Transfer Complete
5875 <bitOffset>18</bitOffset>
5876 <bitWidth>1</bitWidth>
5880 <description>Channel
5 Transfer Error
5882 <bitOffset>19</bitOffset>
5883 <bitWidth>1</bitWidth>
5887 <description>Channel
6 Global interrupt
5889 <bitOffset>20</bitOffset>
5890 <bitWidth>1</bitWidth>
5894 <description>Channel
6 Transfer Complete
5896 <bitOffset>21</bitOffset>
5897 <bitWidth>1</bitWidth>
5901 <description>Channel
6 Half Transfer Complete
5903 <bitOffset>22</bitOffset>
5904 <bitWidth>1</bitWidth>
5908 <description>Channel
6 Transfer Error
5910 <bitOffset>23</bitOffset>
5911 <bitWidth>1</bitWidth>
5915 <description>Channel
7 Global interrupt
5917 <bitOffset>24</bitOffset>
5918 <bitWidth>1</bitWidth>
5922 <description>Channel
7 Transfer Complete
5924 <bitOffset>25</bitOffset>
5925 <bitWidth>1</bitWidth>
5929 <description>Channel
7 Half Transfer Complete
5931 <bitOffset>26</bitOffset>
5932 <bitWidth>1</bitWidth>
5936 <description>Channel
7 Transfer Error
5938 <bitOffset>27</bitOffset>
5939 <bitWidth>1</bitWidth>
5945 <displayName>IFCR
</displayName>
5946 <description>DMA interrupt flag clear register
5947 (DMA_IFCR)
</description>
5948 <addressOffset>0x4</addressOffset>
5950 <access>write-only
</access>
5951 <resetValue>0x00000000</resetValue>
5955 <description>Channel
1 Global interrupt
5957 <bitOffset>0</bitOffset>
5958 <bitWidth>1</bitWidth>
5962 <description>Channel
1 Transfer Complete
5964 <bitOffset>1</bitOffset>
5965 <bitWidth>1</bitWidth>
5969 <description>Channel
1 Half Transfer
5971 <bitOffset>2</bitOffset>
5972 <bitWidth>1</bitWidth>
5976 <description>Channel
1 Transfer Error
5978 <bitOffset>3</bitOffset>
5979 <bitWidth>1</bitWidth>
5983 <description>Channel
2 Global interrupt
5985 <bitOffset>4</bitOffset>
5986 <bitWidth>1</bitWidth>
5990 <description>Channel
2 Transfer Complete
5992 <bitOffset>5</bitOffset>
5993 <bitWidth>1</bitWidth>
5997 <description>Channel
2 Half Transfer
5999 <bitOffset>6</bitOffset>
6000 <bitWidth>1</bitWidth>
6004 <description>Channel
2 Transfer Error
6006 <bitOffset>7</bitOffset>
6007 <bitWidth>1</bitWidth>
6011 <description>Channel
3 Global interrupt
6013 <bitOffset>8</bitOffset>
6014 <bitWidth>1</bitWidth>
6018 <description>Channel
3 Transfer Complete
6020 <bitOffset>9</bitOffset>
6021 <bitWidth>1</bitWidth>
6025 <description>Channel
3 Half Transfer
6027 <bitOffset>10</bitOffset>
6028 <bitWidth>1</bitWidth>
6032 <description>Channel
3 Transfer Error
6034 <bitOffset>11</bitOffset>
6035 <bitWidth>1</bitWidth>
6039 <description>Channel
4 Global interrupt
6041 <bitOffset>12</bitOffset>
6042 <bitWidth>1</bitWidth>
6046 <description>Channel
4 Transfer Complete
6048 <bitOffset>13</bitOffset>
6049 <bitWidth>1</bitWidth>
6053 <description>Channel
4 Half Transfer
6055 <bitOffset>14</bitOffset>
6056 <bitWidth>1</bitWidth>
6060 <description>Channel
4 Transfer Error
6062 <bitOffset>15</bitOffset>
6063 <bitWidth>1</bitWidth>
6067 <description>Channel
5 Global interrupt
6069 <bitOffset>16</bitOffset>
6070 <bitWidth>1</bitWidth>
6074 <description>Channel
5 Transfer Complete
6076 <bitOffset>17</bitOffset>
6077 <bitWidth>1</bitWidth>
6081 <description>Channel
5 Half Transfer
6083 <bitOffset>18</bitOffset>
6084 <bitWidth>1</bitWidth>
6088 <description>Channel
5 Transfer Error
6090 <bitOffset>19</bitOffset>
6091 <bitWidth>1</bitWidth>
6095 <description>Channel
6 Global interrupt
6097 <bitOffset>20</bitOffset>
6098 <bitWidth>1</bitWidth>
6102 <description>Channel
6 Transfer Complete
6104 <bitOffset>21</bitOffset>
6105 <bitWidth>1</bitWidth>
6109 <description>Channel
6 Half Transfer
6111 <bitOffset>22</bitOffset>
6112 <bitWidth>1</bitWidth>
6116 <description>Channel
6 Transfer Error
6118 <bitOffset>23</bitOffset>
6119 <bitWidth>1</bitWidth>
6123 <description>Channel
7 Global interrupt
6125 <bitOffset>24</bitOffset>
6126 <bitWidth>1</bitWidth>
6130 <description>Channel
7 Transfer Complete
6132 <bitOffset>25</bitOffset>
6133 <bitWidth>1</bitWidth>
6137 <description>Channel
7 Half Transfer
6139 <bitOffset>26</bitOffset>
6140 <bitWidth>1</bitWidth>
6144 <description>Channel
7 Transfer Error
6146 <bitOffset>27</bitOffset>
6147 <bitWidth>1</bitWidth>
6153 <displayName>CCR1
</displayName>
6154 <description>DMA channel configuration register
6155 (DMA_CCR)
</description>
6156 <addressOffset>0x8</addressOffset>
6158 <access>read-write
</access>
6159 <resetValue>0x00000000</resetValue>
6163 <description>Channel enable
</description>
6164 <bitOffset>0</bitOffset>
6165 <bitWidth>1</bitWidth>
6169 <description>Transfer complete interrupt
6170 enable
</description>
6171 <bitOffset>1</bitOffset>
6172 <bitWidth>1</bitWidth>
6176 <description>Half Transfer interrupt
6177 enable
</description>
6178 <bitOffset>2</bitOffset>
6179 <bitWidth>1</bitWidth>
6183 <description>Transfer error interrupt
6184 enable
</description>
6185 <bitOffset>3</bitOffset>
6186 <bitWidth>1</bitWidth>
6190 <description>Data transfer direction
</description>
6191 <bitOffset>4</bitOffset>
6192 <bitWidth>1</bitWidth>
6196 <description>Circular mode
</description>
6197 <bitOffset>5</bitOffset>
6198 <bitWidth>1</bitWidth>
6202 <description>Peripheral increment mode
</description>
6203 <bitOffset>6</bitOffset>
6204 <bitWidth>1</bitWidth>
6208 <description>Memory increment mode
</description>
6209 <bitOffset>7</bitOffset>
6210 <bitWidth>1</bitWidth>
6214 <description>Peripheral size
</description>
6215 <bitOffset>8</bitOffset>
6216 <bitWidth>2</bitWidth>
6220 <description>Memory size
</description>
6221 <bitOffset>10</bitOffset>
6222 <bitWidth>2</bitWidth>
6226 <description>Channel Priority level
</description>
6227 <bitOffset>12</bitOffset>
6228 <bitWidth>2</bitWidth>
6231 <name>MEM2MEM
</name>
6232 <description>Memory to memory mode
</description>
6233 <bitOffset>14</bitOffset>
6234 <bitWidth>1</bitWidth>
6240 <displayName>CNDTR1
</displayName>
6241 <description>DMA channel
1 number of data
6242 register
</description>
6243 <addressOffset>0xC</addressOffset>
6245 <access>read-write
</access>
6246 <resetValue>0x00000000</resetValue>
6250 <description>Number of data to transfer
</description>
6251 <bitOffset>0</bitOffset>
6252 <bitWidth>16</bitWidth>
6258 <displayName>CPAR1
</displayName>
6259 <description>DMA channel
1 peripheral address
6260 register
</description>
6261 <addressOffset>0x10</addressOffset>
6263 <access>read-write
</access>
6264 <resetValue>0x00000000</resetValue>
6268 <description>Peripheral address
</description>
6269 <bitOffset>0</bitOffset>
6270 <bitWidth>32</bitWidth>
6276 <displayName>CMAR1
</displayName>
6277 <description>DMA channel
1 memory address
6278 register
</description>
6279 <addressOffset>0x14</addressOffset>
6281 <access>read-write
</access>
6282 <resetValue>0x00000000</resetValue>
6286 <description>Memory address
</description>
6287 <bitOffset>0</bitOffset>
6288 <bitWidth>32</bitWidth>
6294 <displayName>CCR2
</displayName>
6295 <description>DMA channel configuration register
6296 (DMA_CCR)
</description>
6297 <addressOffset>0x1C</addressOffset>
6299 <access>read-write
</access>
6300 <resetValue>0x00000000</resetValue>
6304 <description>Channel enable
</description>
6305 <bitOffset>0</bitOffset>
6306 <bitWidth>1</bitWidth>
6310 <description>Transfer complete interrupt
6311 enable
</description>
6312 <bitOffset>1</bitOffset>
6313 <bitWidth>1</bitWidth>
6317 <description>Half Transfer interrupt
6318 enable
</description>
6319 <bitOffset>2</bitOffset>
6320 <bitWidth>1</bitWidth>
6324 <description>Transfer error interrupt
6325 enable
</description>
6326 <bitOffset>3</bitOffset>
6327 <bitWidth>1</bitWidth>
6331 <description>Data transfer direction
</description>
6332 <bitOffset>4</bitOffset>
6333 <bitWidth>1</bitWidth>
6337 <description>Circular mode
</description>
6338 <bitOffset>5</bitOffset>
6339 <bitWidth>1</bitWidth>
6343 <description>Peripheral increment mode
</description>
6344 <bitOffset>6</bitOffset>
6345 <bitWidth>1</bitWidth>
6349 <description>Memory increment mode
</description>
6350 <bitOffset>7</bitOffset>
6351 <bitWidth>1</bitWidth>
6355 <description>Peripheral size
</description>
6356 <bitOffset>8</bitOffset>
6357 <bitWidth>2</bitWidth>
6361 <description>Memory size
</description>
6362 <bitOffset>10</bitOffset>
6363 <bitWidth>2</bitWidth>
6367 <description>Channel Priority level
</description>
6368 <bitOffset>12</bitOffset>
6369 <bitWidth>2</bitWidth>
6372 <name>MEM2MEM
</name>
6373 <description>Memory to memory mode
</description>
6374 <bitOffset>14</bitOffset>
6375 <bitWidth>1</bitWidth>
6381 <displayName>CNDTR2
</displayName>
6382 <description>DMA channel
2 number of data
6383 register
</description>
6384 <addressOffset>0x20</addressOffset>
6386 <access>read-write
</access>
6387 <resetValue>0x00000000</resetValue>
6391 <description>Number of data to transfer
</description>
6392 <bitOffset>0</bitOffset>
6393 <bitWidth>16</bitWidth>
6399 <displayName>CPAR2
</displayName>
6400 <description>DMA channel
2 peripheral address
6401 register
</description>
6402 <addressOffset>0x24</addressOffset>
6404 <access>read-write
</access>
6405 <resetValue>0x00000000</resetValue>
6409 <description>Peripheral address
</description>
6410 <bitOffset>0</bitOffset>
6411 <bitWidth>32</bitWidth>
6417 <displayName>CMAR2
</displayName>
6418 <description>DMA channel
2 memory address
6419 register
</description>
6420 <addressOffset>0x28</addressOffset>
6422 <access>read-write
</access>
6423 <resetValue>0x00000000</resetValue>
6427 <description>Memory address
</description>
6428 <bitOffset>0</bitOffset>
6429 <bitWidth>32</bitWidth>
6435 <displayName>CCR3
</displayName>
6436 <description>DMA channel configuration register
6437 (DMA_CCR)
</description>
6438 <addressOffset>0x30</addressOffset>
6440 <access>read-write
</access>
6441 <resetValue>0x00000000</resetValue>
6445 <description>Channel enable
</description>
6446 <bitOffset>0</bitOffset>
6447 <bitWidth>1</bitWidth>
6451 <description>Transfer complete interrupt
6452 enable
</description>
6453 <bitOffset>1</bitOffset>
6454 <bitWidth>1</bitWidth>
6458 <description>Half Transfer interrupt
6459 enable
</description>
6460 <bitOffset>2</bitOffset>
6461 <bitWidth>1</bitWidth>
6465 <description>Transfer error interrupt
6466 enable
</description>
6467 <bitOffset>3</bitOffset>
6468 <bitWidth>1</bitWidth>
6472 <description>Data transfer direction
</description>
6473 <bitOffset>4</bitOffset>
6474 <bitWidth>1</bitWidth>
6478 <description>Circular mode
</description>
6479 <bitOffset>5</bitOffset>
6480 <bitWidth>1</bitWidth>
6484 <description>Peripheral increment mode
</description>
6485 <bitOffset>6</bitOffset>
6486 <bitWidth>1</bitWidth>
6490 <description>Memory increment mode
</description>
6491 <bitOffset>7</bitOffset>
6492 <bitWidth>1</bitWidth>
6496 <description>Peripheral size
</description>
6497 <bitOffset>8</bitOffset>
6498 <bitWidth>2</bitWidth>
6502 <description>Memory size
</description>
6503 <bitOffset>10</bitOffset>
6504 <bitWidth>2</bitWidth>
6508 <description>Channel Priority level
</description>
6509 <bitOffset>12</bitOffset>
6510 <bitWidth>2</bitWidth>
6513 <name>MEM2MEM
</name>
6514 <description>Memory to memory mode
</description>
6515 <bitOffset>14</bitOffset>
6516 <bitWidth>1</bitWidth>
6522 <displayName>CNDTR3
</displayName>
6523 <description>DMA channel
3 number of data
6524 register
</description>
6525 <addressOffset>0x34</addressOffset>
6527 <access>read-write
</access>
6528 <resetValue>0x00000000</resetValue>
6532 <description>Number of data to transfer
</description>
6533 <bitOffset>0</bitOffset>
6534 <bitWidth>16</bitWidth>
6540 <displayName>CPAR3
</displayName>
6541 <description>DMA channel
3 peripheral address
6542 register
</description>
6543 <addressOffset>0x38</addressOffset>
6545 <access>read-write
</access>
6546 <resetValue>0x00000000</resetValue>
6550 <description>Peripheral address
</description>
6551 <bitOffset>0</bitOffset>
6552 <bitWidth>32</bitWidth>
6558 <displayName>CMAR3
</displayName>
6559 <description>DMA channel
3 memory address
6560 register
</description>
6561 <addressOffset>0x3C</addressOffset>
6563 <access>read-write
</access>
6564 <resetValue>0x00000000</resetValue>
6568 <description>Memory address
</description>
6569 <bitOffset>0</bitOffset>
6570 <bitWidth>32</bitWidth>
6576 <displayName>CCR4
</displayName>
6577 <description>DMA channel configuration register
6578 (DMA_CCR)
</description>
6579 <addressOffset>0x44</addressOffset>
6581 <access>read-write
</access>
6582 <resetValue>0x00000000</resetValue>
6586 <description>Channel enable
</description>
6587 <bitOffset>0</bitOffset>
6588 <bitWidth>1</bitWidth>
6592 <description>Transfer complete interrupt
6593 enable
</description>
6594 <bitOffset>1</bitOffset>
6595 <bitWidth>1</bitWidth>
6599 <description>Half Transfer interrupt
6600 enable
</description>
6601 <bitOffset>2</bitOffset>
6602 <bitWidth>1</bitWidth>
6606 <description>Transfer error interrupt
6607 enable
</description>
6608 <bitOffset>3</bitOffset>
6609 <bitWidth>1</bitWidth>
6613 <description>Data transfer direction
</description>
6614 <bitOffset>4</bitOffset>
6615 <bitWidth>1</bitWidth>
6619 <description>Circular mode
</description>
6620 <bitOffset>5</bitOffset>
6621 <bitWidth>1</bitWidth>
6625 <description>Peripheral increment mode
</description>
6626 <bitOffset>6</bitOffset>
6627 <bitWidth>1</bitWidth>
6631 <description>Memory increment mode
</description>
6632 <bitOffset>7</bitOffset>
6633 <bitWidth>1</bitWidth>
6637 <description>Peripheral size
</description>
6638 <bitOffset>8</bitOffset>
6639 <bitWidth>2</bitWidth>
6643 <description>Memory size
</description>
6644 <bitOffset>10</bitOffset>
6645 <bitWidth>2</bitWidth>
6649 <description>Channel Priority level
</description>
6650 <bitOffset>12</bitOffset>
6651 <bitWidth>2</bitWidth>
6654 <name>MEM2MEM
</name>
6655 <description>Memory to memory mode
</description>
6656 <bitOffset>14</bitOffset>
6657 <bitWidth>1</bitWidth>
6663 <displayName>CNDTR4
</displayName>
6664 <description>DMA channel
4 number of data
6665 register
</description>
6666 <addressOffset>0x48</addressOffset>
6668 <access>read-write
</access>
6669 <resetValue>0x00000000</resetValue>
6673 <description>Number of data to transfer
</description>
6674 <bitOffset>0</bitOffset>
6675 <bitWidth>16</bitWidth>
6681 <displayName>CPAR4
</displayName>
6682 <description>DMA channel
4 peripheral address
6683 register
</description>
6684 <addressOffset>0x4C</addressOffset>
6686 <access>read-write
</access>
6687 <resetValue>0x00000000</resetValue>
6691 <description>Peripheral address
</description>
6692 <bitOffset>0</bitOffset>
6693 <bitWidth>32</bitWidth>
6699 <displayName>CMAR4
</displayName>
6700 <description>DMA channel
4 memory address
6701 register
</description>
6702 <addressOffset>0x50</addressOffset>
6704 <access>read-write
</access>
6705 <resetValue>0x00000000</resetValue>
6709 <description>Memory address
</description>
6710 <bitOffset>0</bitOffset>
6711 <bitWidth>32</bitWidth>
6717 <displayName>CCR5
</displayName>
6718 <description>DMA channel configuration register
6719 (DMA_CCR)
</description>
6720 <addressOffset>0x58</addressOffset>
6722 <access>read-write
</access>
6723 <resetValue>0x00000000</resetValue>
6727 <description>Channel enable
</description>
6728 <bitOffset>0</bitOffset>
6729 <bitWidth>1</bitWidth>
6733 <description>Transfer complete interrupt
6734 enable
</description>
6735 <bitOffset>1</bitOffset>
6736 <bitWidth>1</bitWidth>
6740 <description>Half Transfer interrupt
6741 enable
</description>
6742 <bitOffset>2</bitOffset>
6743 <bitWidth>1</bitWidth>
6747 <description>Transfer error interrupt
6748 enable
</description>
6749 <bitOffset>3</bitOffset>
6750 <bitWidth>1</bitWidth>
6754 <description>Data transfer direction
</description>
6755 <bitOffset>4</bitOffset>
6756 <bitWidth>1</bitWidth>
6760 <description>Circular mode
</description>
6761 <bitOffset>5</bitOffset>
6762 <bitWidth>1</bitWidth>
6766 <description>Peripheral increment mode
</description>
6767 <bitOffset>6</bitOffset>
6768 <bitWidth>1</bitWidth>
6772 <description>Memory increment mode
</description>
6773 <bitOffset>7</bitOffset>
6774 <bitWidth>1</bitWidth>
6778 <description>Peripheral size
</description>
6779 <bitOffset>8</bitOffset>
6780 <bitWidth>2</bitWidth>
6784 <description>Memory size
</description>
6785 <bitOffset>10</bitOffset>
6786 <bitWidth>2</bitWidth>
6790 <description>Channel Priority level
</description>
6791 <bitOffset>12</bitOffset>
6792 <bitWidth>2</bitWidth>
6795 <name>MEM2MEM
</name>
6796 <description>Memory to memory mode
</description>
6797 <bitOffset>14</bitOffset>
6798 <bitWidth>1</bitWidth>
6804 <displayName>CNDTR5
</displayName>
6805 <description>DMA channel
5 number of data
6806 register
</description>
6807 <addressOffset>0x5C</addressOffset>
6809 <access>read-write
</access>
6810 <resetValue>0x00000000</resetValue>
6814 <description>Number of data to transfer
</description>
6815 <bitOffset>0</bitOffset>
6816 <bitWidth>16</bitWidth>
6822 <displayName>CPAR5
</displayName>
6823 <description>DMA channel
5 peripheral address
6824 register
</description>
6825 <addressOffset>0x60</addressOffset>
6827 <access>read-write
</access>
6828 <resetValue>0x00000000</resetValue>
6832 <description>Peripheral address
</description>
6833 <bitOffset>0</bitOffset>
6834 <bitWidth>32</bitWidth>
6840 <displayName>CMAR5
</displayName>
6841 <description>DMA channel
5 memory address
6842 register
</description>
6843 <addressOffset>0x64</addressOffset>
6845 <access>read-write
</access>
6846 <resetValue>0x00000000</resetValue>
6850 <description>Memory address
</description>
6851 <bitOffset>0</bitOffset>
6852 <bitWidth>32</bitWidth>
6858 <displayName>CCR6
</displayName>
6859 <description>DMA channel configuration register
6860 (DMA_CCR)
</description>
6861 <addressOffset>0x6C</addressOffset>
6863 <access>read-write
</access>
6864 <resetValue>0x00000000</resetValue>
6868 <description>Channel enable
</description>
6869 <bitOffset>0</bitOffset>
6870 <bitWidth>1</bitWidth>
6874 <description>Transfer complete interrupt
6875 enable
</description>
6876 <bitOffset>1</bitOffset>
6877 <bitWidth>1</bitWidth>
6881 <description>Half Transfer interrupt
6882 enable
</description>
6883 <bitOffset>2</bitOffset>
6884 <bitWidth>1</bitWidth>
6888 <description>Transfer error interrupt
6889 enable
</description>
6890 <bitOffset>3</bitOffset>
6891 <bitWidth>1</bitWidth>
6895 <description>Data transfer direction
</description>
6896 <bitOffset>4</bitOffset>
6897 <bitWidth>1</bitWidth>
6901 <description>Circular mode
</description>
6902 <bitOffset>5</bitOffset>
6903 <bitWidth>1</bitWidth>
6907 <description>Peripheral increment mode
</description>
6908 <bitOffset>6</bitOffset>
6909 <bitWidth>1</bitWidth>
6913 <description>Memory increment mode
</description>
6914 <bitOffset>7</bitOffset>
6915 <bitWidth>1</bitWidth>
6919 <description>Peripheral size
</description>
6920 <bitOffset>8</bitOffset>
6921 <bitWidth>2</bitWidth>
6925 <description>Memory size
</description>
6926 <bitOffset>10</bitOffset>
6927 <bitWidth>2</bitWidth>
6931 <description>Channel Priority level
</description>
6932 <bitOffset>12</bitOffset>
6933 <bitWidth>2</bitWidth>
6936 <name>MEM2MEM
</name>
6937 <description>Memory to memory mode
</description>
6938 <bitOffset>14</bitOffset>
6939 <bitWidth>1</bitWidth>
6945 <displayName>CNDTR6
</displayName>
6946 <description>DMA channel
6 number of data
6947 register
</description>
6948 <addressOffset>0x70</addressOffset>
6950 <access>read-write
</access>
6951 <resetValue>0x00000000</resetValue>
6955 <description>Number of data to transfer
</description>
6956 <bitOffset>0</bitOffset>
6957 <bitWidth>16</bitWidth>
6963 <displayName>CPAR6
</displayName>
6964 <description>DMA channel
6 peripheral address
6965 register
</description>
6966 <addressOffset>0x74</addressOffset>
6968 <access>read-write
</access>
6969 <resetValue>0x00000000</resetValue>
6973 <description>Peripheral address
</description>
6974 <bitOffset>0</bitOffset>
6975 <bitWidth>32</bitWidth>
6981 <displayName>CMAR6
</displayName>
6982 <description>DMA channel
6 memory address
6983 register
</description>
6984 <addressOffset>0x78</addressOffset>
6986 <access>read-write
</access>
6987 <resetValue>0x00000000</resetValue>
6991 <description>Memory address
</description>
6992 <bitOffset>0</bitOffset>
6993 <bitWidth>32</bitWidth>
6999 <displayName>CCR7
</displayName>
7000 <description>DMA channel configuration register
7001 (DMA_CCR)
</description>
7002 <addressOffset>0x80</addressOffset>
7004 <access>read-write
</access>
7005 <resetValue>0x00000000</resetValue>
7009 <description>Channel enable
</description>
7010 <bitOffset>0</bitOffset>
7011 <bitWidth>1</bitWidth>
7015 <description>Transfer complete interrupt
7016 enable
</description>
7017 <bitOffset>1</bitOffset>
7018 <bitWidth>1</bitWidth>
7022 <description>Half Transfer interrupt
7023 enable
</description>
7024 <bitOffset>2</bitOffset>
7025 <bitWidth>1</bitWidth>
7029 <description>Transfer error interrupt
7030 enable
</description>
7031 <bitOffset>3</bitOffset>
7032 <bitWidth>1</bitWidth>
7036 <description>Data transfer direction
</description>
7037 <bitOffset>4</bitOffset>
7038 <bitWidth>1</bitWidth>
7042 <description>Circular mode
</description>
7043 <bitOffset>5</bitOffset>
7044 <bitWidth>1</bitWidth>
7048 <description>Peripheral increment mode
</description>
7049 <bitOffset>6</bitOffset>
7050 <bitWidth>1</bitWidth>
7054 <description>Memory increment mode
</description>
7055 <bitOffset>7</bitOffset>
7056 <bitWidth>1</bitWidth>
7060 <description>Peripheral size
</description>
7061 <bitOffset>8</bitOffset>
7062 <bitWidth>2</bitWidth>
7066 <description>Memory size
</description>
7067 <bitOffset>10</bitOffset>
7068 <bitWidth>2</bitWidth>
7072 <description>Channel Priority level
</description>
7073 <bitOffset>12</bitOffset>
7074 <bitWidth>2</bitWidth>
7077 <name>MEM2MEM
</name>
7078 <description>Memory to memory mode
</description>
7079 <bitOffset>14</bitOffset>
7080 <bitWidth>1</bitWidth>
7086 <displayName>CNDTR7
</displayName>
7087 <description>DMA channel
7 number of data
7088 register
</description>
7089 <addressOffset>0x84</addressOffset>
7091 <access>read-write
</access>
7092 <resetValue>0x00000000</resetValue>
7096 <description>Number of data to transfer
</description>
7097 <bitOffset>0</bitOffset>
7098 <bitWidth>16</bitWidth>
7104 <displayName>CPAR7
</displayName>
7105 <description>DMA channel
7 peripheral address
7106 register
</description>
7107 <addressOffset>0x88</addressOffset>
7109 <access>read-write
</access>
7110 <resetValue>0x00000000</resetValue>
7114 <description>Peripheral address
</description>
7115 <bitOffset>0</bitOffset>
7116 <bitWidth>32</bitWidth>
7122 <displayName>CMAR7
</displayName>
7123 <description>DMA channel
7 memory address
7124 register
</description>
7125 <addressOffset>0x8C</addressOffset>
7127 <access>read-write
</access>
7128 <resetValue>0x00000000</resetValue>
7132 <description>Memory address
</description>
7133 <bitOffset>0</bitOffset>
7134 <bitWidth>32</bitWidth>
7140 <peripheral derivedFrom=
"DMA1">
7142 <baseAddress>0x40020400</baseAddress>
7144 <name>DMA2_CH1
</name>
7145 <description>DMA2 channel1 global interrupt
</description>
7149 <name>DMA2_CH2
</name>
7150 <description>DMA2 channel2 global interrupt
</description>
7154 <name>DMA2_CH3
</name>
7155 <description>DMA2 channel3 global interrupt
</description>
7159 <name>DMA2_CH4
</name>
7160 <description>DMA2 channel4 global interrupt
</description>
7164 <name>DMA2_CH5
</name>
7165 <description>DMA2 channel5 global interrupt
</description>
7171 <description>General purpose timer
</description>
7172 <groupName>TIMs
</groupName>
7173 <baseAddress>0x40000000</baseAddress>
7175 <offset>0x0</offset>
7177 <usage>registers
</usage>
7181 <description>TIM2 global interrupt
</description>
7187 <displayName>CR1
</displayName>
7188 <description>control register
1</description>
7189 <addressOffset>0x0</addressOffset>
7191 <access>read-write
</access>
7192 <resetValue>0x0000</resetValue>
7196 <description>Counter enable
</description>
7197 <bitOffset>0</bitOffset>
7198 <bitWidth>1</bitWidth>
7202 <description>Update disable
</description>
7203 <bitOffset>1</bitOffset>
7204 <bitWidth>1</bitWidth>
7208 <description>Update request source
</description>
7209 <bitOffset>2</bitOffset>
7210 <bitWidth>1</bitWidth>
7214 <description>One-pulse mode
</description>
7215 <bitOffset>3</bitOffset>
7216 <bitWidth>1</bitWidth>
7220 <description>Direction
</description>
7221 <bitOffset>4</bitOffset>
7222 <bitWidth>1</bitWidth>
7226 <description>Center-aligned mode
7227 selection
</description>
7228 <bitOffset>5</bitOffset>
7229 <bitWidth>2</bitWidth>
7233 <description>Auto-reload preload enable
</description>
7234 <bitOffset>7</bitOffset>
7235 <bitWidth>1</bitWidth>
7239 <description>Clock division
</description>
7240 <bitOffset>8</bitOffset>
7241 <bitWidth>2</bitWidth>
7244 <name>UIFREMAP
</name>
7245 <description>UIF status bit remapping
</description>
7246 <bitOffset>11</bitOffset>
7247 <bitWidth>1</bitWidth>
7253 <displayName>CR2
</displayName>
7254 <description>control register
2</description>
7255 <addressOffset>0x4</addressOffset>
7257 <access>read-write
</access>
7258 <resetValue>0x0000</resetValue>
7262 <description>TI1 selection
</description>
7263 <bitOffset>7</bitOffset>
7264 <bitWidth>1</bitWidth>
7268 <description>Master mode selection
</description>
7269 <bitOffset>4</bitOffset>
7270 <bitWidth>3</bitWidth>
7274 <description>Capture/compare DMA
7275 selection
</description>
7276 <bitOffset>3</bitOffset>
7277 <bitWidth>1</bitWidth>
7283 <displayName>SMCR
</displayName>
7284 <description>slave mode control register
</description>
7285 <addressOffset>0x8</addressOffset>
7287 <access>read-write
</access>
7288 <resetValue>0x0000</resetValue>
7292 <description>Slave mode selection
</description>
7293 <bitOffset>0</bitOffset>
7294 <bitWidth>3</bitWidth>
7298 <description>OCREF clear selection
</description>
7299 <bitOffset>3</bitOffset>
7300 <bitWidth>1</bitWidth>
7304 <description>Trigger selection
</description>
7305 <bitOffset>4</bitOffset>
7306 <bitWidth>3</bitWidth>
7310 <description>Master/Slave mode
</description>
7311 <bitOffset>7</bitOffset>
7312 <bitWidth>1</bitWidth>
7316 <description>External trigger filter
</description>
7317 <bitOffset>8</bitOffset>
7318 <bitWidth>4</bitWidth>
7322 <description>External trigger prescaler
</description>
7323 <bitOffset>12</bitOffset>
7324 <bitWidth>2</bitWidth>
7328 <description>External clock enable
</description>
7329 <bitOffset>14</bitOffset>
7330 <bitWidth>1</bitWidth>
7334 <description>External trigger polarity
</description>
7335 <bitOffset>15</bitOffset>
7336 <bitWidth>1</bitWidth>
7340 <description>Slave mode selection bit3
</description>
7341 <bitOffset>16</bitOffset>
7342 <bitWidth>1</bitWidth>
7348 <displayName>DIER
</displayName>
7349 <description>DMA/Interrupt enable register
</description>
7350 <addressOffset>0xC</addressOffset>
7352 <access>read-write
</access>
7353 <resetValue>0x0000</resetValue>
7357 <description>Trigger DMA request enable
</description>
7358 <bitOffset>14</bitOffset>
7359 <bitWidth>1</bitWidth>
7363 <description>Capture/Compare
4 DMA request
7364 enable
</description>
7365 <bitOffset>12</bitOffset>
7366 <bitWidth>1</bitWidth>
7370 <description>Capture/Compare
3 DMA request
7371 enable
</description>
7372 <bitOffset>11</bitOffset>
7373 <bitWidth>1</bitWidth>
7377 <description>Capture/Compare
2 DMA request
7378 enable
</description>
7379 <bitOffset>10</bitOffset>
7380 <bitWidth>1</bitWidth>
7384 <description>Capture/Compare
1 DMA request
7385 enable
</description>
7386 <bitOffset>9</bitOffset>
7387 <bitWidth>1</bitWidth>
7391 <description>Update DMA request enable
</description>
7392 <bitOffset>8</bitOffset>
7393 <bitWidth>1</bitWidth>
7397 <description>Trigger interrupt enable
</description>
7398 <bitOffset>6</bitOffset>
7399 <bitWidth>1</bitWidth>
7403 <description>Capture/Compare
4 interrupt
7404 enable
</description>
7405 <bitOffset>4</bitOffset>
7406 <bitWidth>1</bitWidth>
7410 <description>Capture/Compare
3 interrupt
7411 enable
</description>
7412 <bitOffset>3</bitOffset>
7413 <bitWidth>1</bitWidth>
7417 <description>Capture/Compare
2 interrupt
7418 enable
</description>
7419 <bitOffset>2</bitOffset>
7420 <bitWidth>1</bitWidth>
7424 <description>Capture/Compare
1 interrupt
7425 enable
</description>
7426 <bitOffset>1</bitOffset>
7427 <bitWidth>1</bitWidth>
7431 <description>Update interrupt enable
</description>
7432 <bitOffset>0</bitOffset>
7433 <bitWidth>1</bitWidth>
7439 <displayName>SR
</displayName>
7440 <description>status register
</description>
7441 <addressOffset>0x10</addressOffset>
7443 <access>read-write
</access>
7444 <resetValue>0x0000</resetValue>
7448 <description>Capture/Compare
4 overcapture
7450 <bitOffset>12</bitOffset>
7451 <bitWidth>1</bitWidth>
7455 <description>Capture/Compare
3 overcapture
7457 <bitOffset>11</bitOffset>
7458 <bitWidth>1</bitWidth>
7462 <description>Capture/compare
2 overcapture
7464 <bitOffset>10</bitOffset>
7465 <bitWidth>1</bitWidth>
7469 <description>Capture/Compare
1 overcapture
7471 <bitOffset>9</bitOffset>
7472 <bitWidth>1</bitWidth>
7476 <description>Trigger interrupt flag
</description>
7477 <bitOffset>6</bitOffset>
7478 <bitWidth>1</bitWidth>
7482 <description>Capture/Compare
4 interrupt
7484 <bitOffset>4</bitOffset>
7485 <bitWidth>1</bitWidth>
7489 <description>Capture/Compare
3 interrupt
7491 <bitOffset>3</bitOffset>
7492 <bitWidth>1</bitWidth>
7496 <description>Capture/Compare
2 interrupt
7498 <bitOffset>2</bitOffset>
7499 <bitWidth>1</bitWidth>
7503 <description>Capture/compare
1 interrupt
7505 <bitOffset>1</bitOffset>
7506 <bitWidth>1</bitWidth>
7510 <description>Update interrupt flag
</description>
7511 <bitOffset>0</bitOffset>
7512 <bitWidth>1</bitWidth>
7518 <displayName>EGR
</displayName>
7519 <description>event generation register
</description>
7520 <addressOffset>0x14</addressOffset>
7522 <access>write-only
</access>
7523 <resetValue>0x0000</resetValue>
7527 <description>Trigger generation
</description>
7528 <bitOffset>6</bitOffset>
7529 <bitWidth>1</bitWidth>
7533 <description>Capture/compare
4
7534 generation
</description>
7535 <bitOffset>4</bitOffset>
7536 <bitWidth>1</bitWidth>
7540 <description>Capture/compare
3
7541 generation
</description>
7542 <bitOffset>3</bitOffset>
7543 <bitWidth>1</bitWidth>
7547 <description>Capture/compare
2
7548 generation
</description>
7549 <bitOffset>2</bitOffset>
7550 <bitWidth>1</bitWidth>
7554 <description>Capture/compare
1
7555 generation
</description>
7556 <bitOffset>1</bitOffset>
7557 <bitWidth>1</bitWidth>
7561 <description>Update generation
</description>
7562 <bitOffset>0</bitOffset>
7563 <bitWidth>1</bitWidth>
7568 <name>CCMR1_Output
</name>
7569 <displayName>CCMR1_Output
</displayName>
7570 <description>capture/compare mode register
1 (output
7572 <addressOffset>0x18</addressOffset>
7574 <access>read-write
</access>
7575 <resetValue>0x00000000</resetValue>
7579 <description>Capture/Compare
1
7580 selection
</description>
7581 <bitOffset>0</bitOffset>
7582 <bitWidth>2</bitWidth>
7586 <description>Output compare
1 fast
7587 enable
</description>
7588 <bitOffset>2</bitOffset>
7589 <bitWidth>1</bitWidth>
7593 <description>Output compare
1 preload
7594 enable
</description>
7595 <bitOffset>3</bitOffset>
7596 <bitWidth>1</bitWidth>
7600 <description>Output compare
1 mode
</description>
7601 <bitOffset>4</bitOffset>
7602 <bitWidth>3</bitWidth>
7606 <description>Output compare
1 clear
7607 enable
</description>
7608 <bitOffset>7</bitOffset>
7609 <bitWidth>1</bitWidth>
7613 <description>Capture/Compare
2
7614 selection
</description>
7615 <bitOffset>8</bitOffset>
7616 <bitWidth>2</bitWidth>
7620 <description>Output compare
2 fast
7621 enable
</description>
7622 <bitOffset>10</bitOffset>
7623 <bitWidth>1</bitWidth>
7627 <description>Output compare
2 preload
7628 enable
</description>
7629 <bitOffset>11</bitOffset>
7630 <bitWidth>1</bitWidth>
7634 <description>Output compare
2 mode
</description>
7635 <bitOffset>12</bitOffset>
7636 <bitWidth>3</bitWidth>
7640 <description>Output compare
2 clear
7641 enable
</description>
7642 <bitOffset>15</bitOffset>
7643 <bitWidth>1</bitWidth>
7647 <description>Output compare
1 mode bit
7649 <bitOffset>16</bitOffset>
7650 <bitWidth>1</bitWidth>
7654 <description>Output compare
2 mode bit
7656 <bitOffset>24</bitOffset>
7657 <bitWidth>1</bitWidth>
7662 <name>CCMR1_Input
</name>
7663 <displayName>CCMR1_Input
</displayName>
7664 <description>capture/compare mode register
1 (input
7666 <alternateRegister>CCMR1_Output
</alternateRegister>
7667 <addressOffset>0x18</addressOffset>
7669 <access>read-write
</access>
7670 <resetValue>0x00000000</resetValue>
7674 <description>Input capture
2 filter
</description>
7675 <bitOffset>12</bitOffset>
7676 <bitWidth>4</bitWidth>
7680 <description>Input capture
2 prescaler
</description>
7681 <bitOffset>10</bitOffset>
7682 <bitWidth>2</bitWidth>
7686 <description>Capture/compare
2
7687 selection
</description>
7688 <bitOffset>8</bitOffset>
7689 <bitWidth>2</bitWidth>
7693 <description>Input capture
1 filter
</description>
7694 <bitOffset>4</bitOffset>
7695 <bitWidth>4</bitWidth>
7699 <description>Input capture
1 prescaler
</description>
7700 <bitOffset>2</bitOffset>
7701 <bitWidth>2</bitWidth>
7705 <description>Capture/Compare
1
7706 selection
</description>
7707 <bitOffset>0</bitOffset>
7708 <bitWidth>2</bitWidth>
7713 <name>CCMR2_Output
</name>
7714 <displayName>CCMR2_Output
</displayName>
7715 <description>capture/compare mode register
2 (output
7717 <addressOffset>0x1C</addressOffset>
7719 <access>read-write
</access>
7720 <resetValue>0x00000000</resetValue>
7724 <description>Capture/Compare
3
7725 selection
</description>
7726 <bitOffset>0</bitOffset>
7727 <bitWidth>2</bitWidth>
7731 <description>Output compare
3 fast
7732 enable
</description>
7733 <bitOffset>2</bitOffset>
7734 <bitWidth>1</bitWidth>
7738 <description>Output compare
3 preload
7739 enable
</description>
7740 <bitOffset>3</bitOffset>
7741 <bitWidth>1</bitWidth>
7745 <description>Output compare
3 mode
</description>
7746 <bitOffset>4</bitOffset>
7747 <bitWidth>3</bitWidth>
7751 <description>Output compare
3 clear
7752 enable
</description>
7753 <bitOffset>7</bitOffset>
7754 <bitWidth>1</bitWidth>
7758 <description>Capture/Compare
4
7759 selection
</description>
7760 <bitOffset>8</bitOffset>
7761 <bitWidth>2</bitWidth>
7765 <description>Output compare
4 fast
7766 enable
</description>
7767 <bitOffset>10</bitOffset>
7768 <bitWidth>1</bitWidth>
7772 <description>Output compare
4 preload
7773 enable
</description>
7774 <bitOffset>11</bitOffset>
7775 <bitWidth>1</bitWidth>
7779 <description>Output compare
4 mode
</description>
7780 <bitOffset>12</bitOffset>
7781 <bitWidth>3</bitWidth>
7785 <description>Output compare
4 clear
7786 enable
</description>
7787 <bitOffset>15</bitOffset>
7788 <bitWidth>1</bitWidth>
7792 <description>Output compare
3 mode bit3
</description>
7793 <bitOffset>16</bitOffset>
7794 <bitWidth>1</bitWidth>
7798 <description>Output compare
4 mode bit3
</description>
7799 <bitOffset>24</bitOffset>
7800 <bitWidth>1</bitWidth>
7805 <name>CCMR2_Input
</name>
7806 <displayName>CCMR2_Input
</displayName>
7807 <description>capture/compare mode register
2 (input
7809 <alternateRegister>CCMR2_Output
</alternateRegister>
7810 <addressOffset>0x1C</addressOffset>
7812 <access>read-write
</access>
7813 <resetValue>0x00000000</resetValue>
7817 <description>Input capture
4 filter
</description>
7818 <bitOffset>12</bitOffset>
7819 <bitWidth>4</bitWidth>
7823 <description>Input capture
4 prescaler
</description>
7824 <bitOffset>10</bitOffset>
7825 <bitWidth>2</bitWidth>
7829 <description>Capture/Compare
4
7830 selection
</description>
7831 <bitOffset>8</bitOffset>
7832 <bitWidth>2</bitWidth>
7836 <description>Input capture
3 filter
</description>
7837 <bitOffset>4</bitOffset>
7838 <bitWidth>4</bitWidth>
7842 <description>Input capture
3 prescaler
</description>
7843 <bitOffset>2</bitOffset>
7844 <bitWidth>2</bitWidth>
7848 <description>Capture/Compare
3
7849 selection
</description>
7850 <bitOffset>0</bitOffset>
7851 <bitWidth>2</bitWidth>
7857 <displayName>CCER
</displayName>
7858 <description>capture/compare enable
7859 register
</description>
7860 <addressOffset>0x20</addressOffset>
7862 <access>read-write
</access>
7863 <resetValue>0x0000</resetValue>
7867 <description>Capture/Compare
1 output
7868 enable
</description>
7869 <bitOffset>0</bitOffset>
7870 <bitWidth>1</bitWidth>
7874 <description>Capture/Compare
1 output
7875 Polarity
</description>
7876 <bitOffset>1</bitOffset>
7877 <bitWidth>1</bitWidth>
7881 <description>Capture/Compare
1 output
7882 Polarity
</description>
7883 <bitOffset>3</bitOffset>
7884 <bitWidth>1</bitWidth>
7888 <description>Capture/Compare
2 output
7889 enable
</description>
7890 <bitOffset>4</bitOffset>
7891 <bitWidth>1</bitWidth>
7895 <description>Capture/Compare
2 output
7896 Polarity
</description>
7897 <bitOffset>5</bitOffset>
7898 <bitWidth>1</bitWidth>
7902 <description>Capture/Compare
2 output
7903 Polarity
</description>
7904 <bitOffset>7</bitOffset>
7905 <bitWidth>1</bitWidth>
7909 <description>Capture/Compare
3 output
7910 enable
</description>
7911 <bitOffset>8</bitOffset>
7912 <bitWidth>1</bitWidth>
7916 <description>Capture/Compare
3 output
7917 Polarity
</description>
7918 <bitOffset>9</bitOffset>
7919 <bitWidth>1</bitWidth>
7923 <description>Capture/Compare
3 output
7924 Polarity
</description>
7925 <bitOffset>11</bitOffset>
7926 <bitWidth>1</bitWidth>
7930 <description>Capture/Compare
4 output
7931 enable
</description>
7932 <bitOffset>12</bitOffset>
7933 <bitWidth>1</bitWidth>
7937 <description>Capture/Compare
3 output
7938 Polarity
</description>
7939 <bitOffset>13</bitOffset>
7940 <bitWidth>1</bitWidth>
7944 <description>Capture/Compare
3 output
7945 Polarity
</description>
7946 <bitOffset>15</bitOffset>
7947 <bitWidth>1</bitWidth>
7953 <displayName>CNT
</displayName>
7954 <description>counter
</description>
7955 <addressOffset>0x24</addressOffset>
7957 <access>read-write
</access>
7958 <resetValue>0x00000000</resetValue>
7962 <description>Low counter value
</description>
7963 <bitOffset>0</bitOffset>
7964 <bitWidth>16</bitWidth>
7968 <description>High counter value
</description>
7969 <bitOffset>16</bitOffset>
7970 <bitWidth>15</bitWidth>
7973 <name>CNT_or_UIFCPY
</name>
7974 <description>if IUFREMAP=
0 than CNT with read write
7975 access else UIFCPY with read only
7976 access
</description>
7977 <bitOffset>31</bitOffset>
7978 <bitWidth>1</bitWidth>
7984 <displayName>PSC
</displayName>
7985 <description>prescaler
</description>
7986 <addressOffset>0x28</addressOffset>
7988 <access>read-write
</access>
7989 <resetValue>0x0000</resetValue>
7993 <description>Prescaler value
</description>
7994 <bitOffset>0</bitOffset>
7995 <bitWidth>16</bitWidth>
8001 <displayName>ARR
</displayName>
8002 <description>auto-reload register
</description>
8003 <addressOffset>0x2C</addressOffset>
8005 <access>read-write
</access>
8006 <resetValue>0x00000000</resetValue>
8010 <description>Low Auto-reload value
</description>
8011 <bitOffset>0</bitOffset>
8012 <bitWidth>16</bitWidth>
8016 <description>High Auto-reload value
</description>
8017 <bitOffset>16</bitOffset>
8018 <bitWidth>16</bitWidth>
8024 <displayName>CCR1
</displayName>
8025 <description>capture/compare register
1</description>
8026 <addressOffset>0x34</addressOffset>
8028 <access>read-write
</access>
8029 <resetValue>0x00000000</resetValue>
8033 <description>Low Capture/Compare
1
8035 <bitOffset>0</bitOffset>
8036 <bitWidth>16</bitWidth>
8040 <description>High Capture/Compare
1 value (on
8042 <bitOffset>16</bitOffset>
8043 <bitWidth>16</bitWidth>
8049 <displayName>CCR2
</displayName>
8050 <description>capture/compare register
2</description>
8051 <addressOffset>0x38</addressOffset>
8053 <access>read-write
</access>
8054 <resetValue>0x00000000</resetValue>
8058 <description>Low Capture/Compare
2
8060 <bitOffset>0</bitOffset>
8061 <bitWidth>16</bitWidth>
8065 <description>High Capture/Compare
2 value (on
8067 <bitOffset>16</bitOffset>
8068 <bitWidth>16</bitWidth>
8074 <displayName>CCR3
</displayName>
8075 <description>capture/compare register
3</description>
8076 <addressOffset>0x3C</addressOffset>
8078 <access>read-write
</access>
8079 <resetValue>0x00000000</resetValue>
8083 <description>Low Capture/Compare value
</description>
8084 <bitOffset>0</bitOffset>
8085 <bitWidth>16</bitWidth>
8089 <description>High Capture/Compare value (on
8091 <bitOffset>16</bitOffset>
8092 <bitWidth>16</bitWidth>
8098 <displayName>CCR4
</displayName>
8099 <description>capture/compare register
4</description>
8100 <addressOffset>0x40</addressOffset>
8102 <access>read-write
</access>
8103 <resetValue>0x00000000</resetValue>
8107 <description>Low Capture/Compare value
</description>
8108 <bitOffset>0</bitOffset>
8109 <bitWidth>16</bitWidth>
8113 <description>High Capture/Compare value (on
8115 <bitOffset>16</bitOffset>
8116 <bitWidth>16</bitWidth>
8122 <displayName>DCR
</displayName>
8123 <description>DMA control register
</description>
8124 <addressOffset>0x48</addressOffset>
8126 <access>read-write
</access>
8127 <resetValue>0x0000</resetValue>
8131 <description>DMA burst length
</description>
8132 <bitOffset>8</bitOffset>
8133 <bitWidth>5</bitWidth>
8137 <description>DMA base address
</description>
8138 <bitOffset>0</bitOffset>
8139 <bitWidth>5</bitWidth>
8145 <displayName>DMAR
</displayName>
8146 <description>DMA address for full transfer
</description>
8147 <addressOffset>0x4C</addressOffset>
8149 <access>read-write
</access>
8150 <resetValue>0x0000</resetValue>
8154 <description>DMA register for burst
8155 accesses
</description>
8156 <bitOffset>0</bitOffset>
8157 <bitWidth>16</bitWidth>
8163 <peripheral derivedFrom=
"TIM2">
8165 <baseAddress>0x40000400</baseAddress>
8168 <description>TIM3 global interrupt
</description>
8172 <peripheral derivedFrom=
"TIM2">
8174 <baseAddress>0x40000800</baseAddress>
8177 <description>TIM4 global interrupt
</description>
8183 <description>General purpose timers
</description>
8184 <groupName>TIMs
</groupName>
8185 <baseAddress>0x40014000</baseAddress>
8187 <offset>0x0</offset>
8189 <usage>registers
</usage>
8192 <name>TIM1_BRK_TIM15
</name>
8193 <description>TIM1 Break/TIM15 global
8194 interruts
</description>
8200 <displayName>CR1
</displayName>
8201 <description>control register
1</description>
8202 <addressOffset>0x0</addressOffset>
8204 <access>read-write
</access>
8205 <resetValue>0x0000</resetValue>
8209 <description>Counter enable
</description>
8210 <bitOffset>0</bitOffset>
8211 <bitWidth>1</bitWidth>
8215 <description>Update disable
</description>
8216 <bitOffset>1</bitOffset>
8217 <bitWidth>1</bitWidth>
8221 <description>Update request source
</description>
8222 <bitOffset>2</bitOffset>
8223 <bitWidth>1</bitWidth>
8227 <description>One-pulse mode
</description>
8228 <bitOffset>3</bitOffset>
8229 <bitWidth>1</bitWidth>
8233 <description>Auto-reload preload enable
</description>
8234 <bitOffset>7</bitOffset>
8235 <bitWidth>1</bitWidth>
8239 <description>Clock division
</description>
8240 <bitOffset>8</bitOffset>
8241 <bitWidth>2</bitWidth>
8244 <name>UIFREMAP
</name>
8245 <description>UIF status bit remapping
</description>
8246 <bitOffset>11</bitOffset>
8247 <bitWidth>1</bitWidth>
8253 <displayName>CR2
</displayName>
8254 <description>control register
2</description>
8255 <addressOffset>0x4</addressOffset>
8257 <access>read-write
</access>
8258 <resetValue>0x0000</resetValue>
8262 <description>Capture/compare preloaded
8263 control
</description>
8264 <bitOffset>0</bitOffset>
8265 <bitWidth>1</bitWidth>
8269 <description>Capture/compare control update
8270 selection
</description>
8271 <bitOffset>2</bitOffset>
8272 <bitWidth>1</bitWidth>
8276 <description>Capture/compare DMA
8277 selection
</description>
8278 <bitOffset>3</bitOffset>
8279 <bitWidth>1</bitWidth>
8283 <description>Master mode selection
</description>
8284 <bitOffset>4</bitOffset>
8285 <bitWidth>3</bitWidth>
8289 <description>TI1 selection
</description>
8290 <bitOffset>7</bitOffset>
8291 <bitWidth>1</bitWidth>
8295 <description>Output Idle state
1</description>
8296 <bitOffset>8</bitOffset>
8297 <bitWidth>1</bitWidth>
8301 <description>Output Idle state
1</description>
8302 <bitOffset>9</bitOffset>
8303 <bitWidth>1</bitWidth>
8307 <description>Output Idle state
2</description>
8308 <bitOffset>10</bitOffset>
8309 <bitWidth>1</bitWidth>
8315 <displayName>SMCR
</displayName>
8316 <description>slave mode control register
</description>
8317 <addressOffset>0x8</addressOffset>
8319 <access>read-write
</access>
8320 <resetValue>0x0000</resetValue>
8324 <description>Slave mode selection
</description>
8325 <bitOffset>0</bitOffset>
8326 <bitWidth>3</bitWidth>
8330 <description>Trigger selection
</description>
8331 <bitOffset>4</bitOffset>
8332 <bitWidth>3</bitWidth>
8336 <description>Master/Slave mode
</description>
8337 <bitOffset>7</bitOffset>
8338 <bitWidth>1</bitWidth>
8342 <description>Slave mode selection bit
3</description>
8343 <bitOffset>16</bitOffset>
8344 <bitWidth>1</bitWidth>
8350 <displayName>DIER
</displayName>
8351 <description>DMA/Interrupt enable register
</description>
8352 <addressOffset>0xC</addressOffset>
8354 <access>read-write
</access>
8355 <resetValue>0x0000</resetValue>
8359 <description>Update interrupt enable
</description>
8360 <bitOffset>0</bitOffset>
8361 <bitWidth>1</bitWidth>
8365 <description>Capture/Compare
1 interrupt
8366 enable
</description>
8367 <bitOffset>1</bitOffset>
8368 <bitWidth>1</bitWidth>
8372 <description>Capture/Compare
2 interrupt
8373 enable
</description>
8374 <bitOffset>2</bitOffset>
8375 <bitWidth>1</bitWidth>
8379 <description>COM interrupt enable
</description>
8380 <bitOffset>5</bitOffset>
8381 <bitWidth>1</bitWidth>
8385 <description>Trigger interrupt enable
</description>
8386 <bitOffset>6</bitOffset>
8387 <bitWidth>1</bitWidth>
8391 <description>Break interrupt enable
</description>
8392 <bitOffset>7</bitOffset>
8393 <bitWidth>1</bitWidth>
8397 <description>Update DMA request enable
</description>
8398 <bitOffset>8</bitOffset>
8399 <bitWidth>1</bitWidth>
8403 <description>Capture/Compare
1 DMA request
8404 enable
</description>
8405 <bitOffset>9</bitOffset>
8406 <bitWidth>1</bitWidth>
8410 <description>Capture/Compare
2 DMA request
8411 enable
</description>
8412 <bitOffset>10</bitOffset>
8413 <bitWidth>1</bitWidth>
8417 <description>COM DMA request enable
</description>
8418 <bitOffset>13</bitOffset>
8419 <bitWidth>1</bitWidth>
8423 <description>Trigger DMA request enable
</description>
8424 <bitOffset>14</bitOffset>
8425 <bitWidth>1</bitWidth>
8431 <displayName>SR
</displayName>
8432 <description>status register
</description>
8433 <addressOffset>0x10</addressOffset>
8435 <access>read-write
</access>
8436 <resetValue>0x0000</resetValue>
8440 <description>Capture/compare
2 overcapture
8442 <bitOffset>10</bitOffset>
8443 <bitWidth>1</bitWidth>
8447 <description>Capture/Compare
1 overcapture
8449 <bitOffset>9</bitOffset>
8450 <bitWidth>1</bitWidth>
8454 <description>Break interrupt flag
</description>
8455 <bitOffset>7</bitOffset>
8456 <bitWidth>1</bitWidth>
8460 <description>Trigger interrupt flag
</description>
8461 <bitOffset>6</bitOffset>
8462 <bitWidth>1</bitWidth>
8466 <description>COM interrupt flag
</description>
8467 <bitOffset>5</bitOffset>
8468 <bitWidth>1</bitWidth>
8472 <description>Capture/Compare
2 interrupt
8474 <bitOffset>2</bitOffset>
8475 <bitWidth>1</bitWidth>
8479 <description>Capture/compare
1 interrupt
8481 <bitOffset>1</bitOffset>
8482 <bitWidth>1</bitWidth>
8486 <description>Update interrupt flag
</description>
8487 <bitOffset>0</bitOffset>
8488 <bitWidth>1</bitWidth>
8494 <displayName>EGR
</displayName>
8495 <description>event generation register
</description>
8496 <addressOffset>0x14</addressOffset>
8498 <access>write-only
</access>
8499 <resetValue>0x0000</resetValue>
8503 <description>Break generation
</description>
8504 <bitOffset>7</bitOffset>
8505 <bitWidth>1</bitWidth>
8509 <description>Trigger generation
</description>
8510 <bitOffset>6</bitOffset>
8511 <bitWidth>1</bitWidth>
8515 <description>Capture/Compare control update
8516 generation
</description>
8517 <bitOffset>5</bitOffset>
8518 <bitWidth>1</bitWidth>
8522 <description>Capture/compare
2
8523 generation
</description>
8524 <bitOffset>2</bitOffset>
8525 <bitWidth>1</bitWidth>
8529 <description>Capture/compare
1
8530 generation
</description>
8531 <bitOffset>1</bitOffset>
8532 <bitWidth>1</bitWidth>
8536 <description>Update generation
</description>
8537 <bitOffset>0</bitOffset>
8538 <bitWidth>1</bitWidth>
8543 <name>CCMR1_Output
</name>
8544 <displayName>CCMR1_Output
</displayName>
8545 <description>capture/compare mode register (output
8547 <addressOffset>0x18</addressOffset>
8549 <access>read-write
</access>
8550 <resetValue>0x00000000</resetValue>
8554 <description>Capture/Compare
1
8555 selection
</description>
8556 <bitOffset>0</bitOffset>
8557 <bitWidth>2</bitWidth>
8561 <description>Output Compare
1 fast
8562 enable
</description>
8563 <bitOffset>2</bitOffset>
8564 <bitWidth>1</bitWidth>
8568 <description>Output Compare
1 preload
8569 enable
</description>
8570 <bitOffset>3</bitOffset>
8571 <bitWidth>1</bitWidth>
8575 <description>Output Compare
1 mode
</description>
8576 <bitOffset>4</bitOffset>
8577 <bitWidth>3</bitWidth>
8581 <description>Capture/Compare
2
8582 selection
</description>
8583 <bitOffset>8</bitOffset>
8584 <bitWidth>2</bitWidth>
8588 <description>Output Compare
2 fast
8589 enable
</description>
8590 <bitOffset>10</bitOffset>
8591 <bitWidth>1</bitWidth>
8595 <description>Output Compare
2 preload
8596 enable
</description>
8597 <bitOffset>11</bitOffset>
8598 <bitWidth>1</bitWidth>
8602 <description>Output Compare
2 mode
</description>
8603 <bitOffset>12</bitOffset>
8604 <bitWidth>3</bitWidth>
8608 <description>Output Compare
1 mode bit
8610 <bitOffset>16</bitOffset>
8611 <bitWidth>1</bitWidth>
8615 <description>Output Compare
2 mode bit
8617 <bitOffset>24</bitOffset>
8618 <bitWidth>1</bitWidth>
8623 <name>CCMR1_Input
</name>
8624 <displayName>CCMR1_Input
</displayName>
8625 <description>capture/compare mode register
1 (input
8627 <alternateRegister>CCMR1_Output
</alternateRegister>
8628 <addressOffset>0x18</addressOffset>
8630 <access>read-write
</access>
8631 <resetValue>0x00000000</resetValue>
8635 <description>Input capture
2 filter
</description>
8636 <bitOffset>12</bitOffset>
8637 <bitWidth>4</bitWidth>
8641 <description>Input capture
2 prescaler
</description>
8642 <bitOffset>10</bitOffset>
8643 <bitWidth>2</bitWidth>
8647 <description>Capture/Compare
2
8648 selection
</description>
8649 <bitOffset>8</bitOffset>
8650 <bitWidth>2</bitWidth>
8654 <description>Input capture
1 filter
</description>
8655 <bitOffset>4</bitOffset>
8656 <bitWidth>4</bitWidth>
8660 <description>Input capture
1 prescaler
</description>
8661 <bitOffset>2</bitOffset>
8662 <bitWidth>2</bitWidth>
8666 <description>Capture/Compare
1
8667 selection
</description>
8668 <bitOffset>0</bitOffset>
8669 <bitWidth>2</bitWidth>
8675 <displayName>CCER
</displayName>
8676 <description>capture/compare enable
8677 register
</description>
8678 <addressOffset>0x20</addressOffset>
8680 <access>read-write
</access>
8681 <resetValue>0x0000</resetValue>
8685 <description>Capture/Compare
2 output
8686 Polarity
</description>
8687 <bitOffset>7</bitOffset>
8688 <bitWidth>1</bitWidth>
8692 <description>Capture/Compare
2 output
8693 Polarity
</description>
8694 <bitOffset>5</bitOffset>
8695 <bitWidth>1</bitWidth>
8699 <description>Capture/Compare
2 output
8700 enable
</description>
8701 <bitOffset>4</bitOffset>
8702 <bitWidth>1</bitWidth>
8706 <description>Capture/Compare
1 output
8707 Polarity
</description>
8708 <bitOffset>3</bitOffset>
8709 <bitWidth>1</bitWidth>
8713 <description>Capture/Compare
1 complementary output
8714 enable
</description>
8715 <bitOffset>2</bitOffset>
8716 <bitWidth>1</bitWidth>
8720 <description>Capture/Compare
1 output
8721 Polarity
</description>
8722 <bitOffset>1</bitOffset>
8723 <bitWidth>1</bitWidth>
8727 <description>Capture/Compare
1 output
8728 enable
</description>
8729 <bitOffset>0</bitOffset>
8730 <bitWidth>1</bitWidth>
8736 <displayName>CNT
</displayName>
8737 <description>counter
</description>
8738 <addressOffset>0x24</addressOffset>
8740 <resetValue>0x00000000</resetValue>
8744 <description>counter value
</description>
8745 <bitOffset>0</bitOffset>
8746 <bitWidth>16</bitWidth>
8747 <access>read-write
</access>
8751 <description>UIF copy
</description>
8752 <bitOffset>31</bitOffset>
8753 <bitWidth>1</bitWidth>
8754 <access>read-only
</access>
8760 <displayName>PSC
</displayName>
8761 <description>prescaler
</description>
8762 <addressOffset>0x28</addressOffset>
8764 <access>read-write
</access>
8765 <resetValue>0x0000</resetValue>
8769 <description>Prescaler value
</description>
8770 <bitOffset>0</bitOffset>
8771 <bitWidth>16</bitWidth>
8777 <displayName>ARR
</displayName>
8778 <description>auto-reload register
</description>
8779 <addressOffset>0x2C</addressOffset>
8781 <access>read-write
</access>
8782 <resetValue>0x00000000</resetValue>
8786 <description>Auto-reload value
</description>
8787 <bitOffset>0</bitOffset>
8788 <bitWidth>16</bitWidth>
8794 <displayName>RCR
</displayName>
8795 <description>repetition counter register
</description>
8796 <addressOffset>0x30</addressOffset>
8798 <access>read-write
</access>
8799 <resetValue>0x0000</resetValue>
8803 <description>Repetition counter value
</description>
8804 <bitOffset>0</bitOffset>
8805 <bitWidth>8</bitWidth>
8811 <displayName>CCR1
</displayName>
8812 <description>capture/compare register
1</description>
8813 <addressOffset>0x34</addressOffset>
8815 <access>read-write
</access>
8816 <resetValue>0x00000000</resetValue>
8820 <description>Capture/Compare
1 value
</description>
8821 <bitOffset>0</bitOffset>
8822 <bitWidth>16</bitWidth>
8828 <displayName>CCR2
</displayName>
8829 <description>capture/compare register
2</description>
8830 <addressOffset>0x38</addressOffset>
8832 <access>read-write
</access>
8833 <resetValue>0x00000000</resetValue>
8837 <description>Capture/Compare
2 value
</description>
8838 <bitOffset>0</bitOffset>
8839 <bitWidth>16</bitWidth>
8845 <displayName>BDTR
</displayName>
8846 <description>break and dead-time register
</description>
8847 <addressOffset>0x44</addressOffset>
8849 <access>read-write
</access>
8850 <resetValue>0x0000</resetValue>
8854 <description>Main output enable
</description>
8855 <bitOffset>15</bitOffset>
8856 <bitWidth>1</bitWidth>
8860 <description>Automatic output enable
</description>
8861 <bitOffset>14</bitOffset>
8862 <bitWidth>1</bitWidth>
8866 <description>Break polarity
</description>
8867 <bitOffset>13</bitOffset>
8868 <bitWidth>1</bitWidth>
8872 <description>Break enable
</description>
8873 <bitOffset>12</bitOffset>
8874 <bitWidth>1</bitWidth>
8878 <description>Off-state selection for Run
8880 <bitOffset>11</bitOffset>
8881 <bitWidth>1</bitWidth>
8885 <description>Off-state selection for Idle
8887 <bitOffset>10</bitOffset>
8888 <bitWidth>1</bitWidth>
8892 <description>Lock configuration
</description>
8893 <bitOffset>8</bitOffset>
8894 <bitWidth>2</bitWidth>
8898 <description>Dead-time generator setup
</description>
8899 <bitOffset>0</bitOffset>
8900 <bitWidth>8</bitWidth>
8904 <description>Break filter
</description>
8905 <bitOffset>16</bitOffset>
8906 <bitWidth>4</bitWidth>
8912 <displayName>DCR
</displayName>
8913 <description>DMA control register
</description>
8914 <addressOffset>0x48</addressOffset>
8916 <access>read-write
</access>
8917 <resetValue>0x0000</resetValue>
8921 <description>DMA burst length
</description>
8922 <bitOffset>8</bitOffset>
8923 <bitWidth>5</bitWidth>
8927 <description>DMA base address
</description>
8928 <bitOffset>0</bitOffset>
8929 <bitWidth>5</bitWidth>
8935 <displayName>DMAR
</displayName>
8936 <description>DMA address for full transfer
</description>
8937 <addressOffset>0x4C</addressOffset>
8939 <access>read-write
</access>
8940 <resetValue>0x0000</resetValue>
8944 <description>DMA register for burst
8945 accesses
</description>
8946 <bitOffset>0</bitOffset>
8947 <bitWidth>16</bitWidth>
8955 <description>General-purpose-timers
</description>
8956 <groupName>TIMs
</groupName>
8957 <baseAddress>0x40014400</baseAddress>
8959 <offset>0x0</offset>
8961 <usage>registers
</usage>
8964 <name>TIM1_UP_TIM16
</name>
8965 <description>TIM1 Update/TIM16 global
8966 interrupts
</description>
8972 <displayName>CR1
</displayName>
8973 <description>control register
1</description>
8974 <addressOffset>0x0</addressOffset>
8976 <access>read-write
</access>
8977 <resetValue>0x0000</resetValue>
8981 <description>Counter enable
</description>
8982 <bitOffset>0</bitOffset>
8983 <bitWidth>1</bitWidth>
8987 <description>Update disable
</description>
8988 <bitOffset>1</bitOffset>
8989 <bitWidth>1</bitWidth>
8993 <description>Update request source
</description>
8994 <bitOffset>2</bitOffset>
8995 <bitWidth>1</bitWidth>
8999 <description>One-pulse mode
</description>
9000 <bitOffset>3</bitOffset>
9001 <bitWidth>1</bitWidth>
9005 <description>Auto-reload preload enable
</description>
9006 <bitOffset>7</bitOffset>
9007 <bitWidth>1</bitWidth>
9011 <description>Clock division
</description>
9012 <bitOffset>8</bitOffset>
9013 <bitWidth>2</bitWidth>
9016 <name>UIFREMAP
</name>
9017 <description>UIF status bit remapping
</description>
9018 <bitOffset>11</bitOffset>
9019 <bitWidth>1</bitWidth>
9025 <displayName>CR2
</displayName>
9026 <description>control register
2</description>
9027 <addressOffset>0x4</addressOffset>
9029 <access>read-write
</access>
9030 <resetValue>0x0000</resetValue>
9034 <description>Output Idle state
1</description>
9035 <bitOffset>9</bitOffset>
9036 <bitWidth>1</bitWidth>
9040 <description>Output Idle state
1</description>
9041 <bitOffset>8</bitOffset>
9042 <bitWidth>1</bitWidth>
9046 <description>Capture/compare DMA
9047 selection
</description>
9048 <bitOffset>3</bitOffset>
9049 <bitWidth>1</bitWidth>
9053 <description>Capture/compare control update
9054 selection
</description>
9055 <bitOffset>2</bitOffset>
9056 <bitWidth>1</bitWidth>
9060 <description>Capture/compare preloaded
9061 control
</description>
9062 <bitOffset>0</bitOffset>
9063 <bitWidth>1</bitWidth>
9069 <displayName>DIER
</displayName>
9070 <description>DMA/Interrupt enable register
</description>
9071 <addressOffset>0xC</addressOffset>
9073 <access>read-write
</access>
9074 <resetValue>0x0000</resetValue>
9078 <description>Update interrupt enable
</description>
9079 <bitOffset>0</bitOffset>
9080 <bitWidth>1</bitWidth>
9084 <description>Capture/Compare
1 interrupt
9085 enable
</description>
9086 <bitOffset>1</bitOffset>
9087 <bitWidth>1</bitWidth>
9091 <description>COM interrupt enable
</description>
9092 <bitOffset>5</bitOffset>
9093 <bitWidth>1</bitWidth>
9097 <description>Trigger interrupt enable
</description>
9098 <bitOffset>6</bitOffset>
9099 <bitWidth>1</bitWidth>
9103 <description>Break interrupt enable
</description>
9104 <bitOffset>7</bitOffset>
9105 <bitWidth>1</bitWidth>
9109 <description>Update DMA request enable
</description>
9110 <bitOffset>8</bitOffset>
9111 <bitWidth>1</bitWidth>
9115 <description>Capture/Compare
1 DMA request
9116 enable
</description>
9117 <bitOffset>9</bitOffset>
9118 <bitWidth>1</bitWidth>
9122 <description>COM DMA request enable
</description>
9123 <bitOffset>13</bitOffset>
9124 <bitWidth>1</bitWidth>
9128 <description>Trigger DMA request enable
</description>
9129 <bitOffset>14</bitOffset>
9130 <bitWidth>1</bitWidth>
9136 <displayName>SR
</displayName>
9137 <description>status register
</description>
9138 <addressOffset>0x10</addressOffset>
9140 <access>read-write
</access>
9141 <resetValue>0x0000</resetValue>
9145 <description>Capture/Compare
1 overcapture
9147 <bitOffset>9</bitOffset>
9148 <bitWidth>1</bitWidth>
9152 <description>Break interrupt flag
</description>
9153 <bitOffset>7</bitOffset>
9154 <bitWidth>1</bitWidth>
9158 <description>Trigger interrupt flag
</description>
9159 <bitOffset>6</bitOffset>
9160 <bitWidth>1</bitWidth>
9164 <description>COM interrupt flag
</description>
9165 <bitOffset>5</bitOffset>
9166 <bitWidth>1</bitWidth>
9170 <description>Capture/compare
1 interrupt
9172 <bitOffset>1</bitOffset>
9173 <bitWidth>1</bitWidth>
9177 <description>Update interrupt flag
</description>
9178 <bitOffset>0</bitOffset>
9179 <bitWidth>1</bitWidth>
9185 <displayName>EGR
</displayName>
9186 <description>event generation register
</description>
9187 <addressOffset>0x14</addressOffset>
9189 <access>write-only
</access>
9190 <resetValue>0x0000</resetValue>
9194 <description>Break generation
</description>
9195 <bitOffset>7</bitOffset>
9196 <bitWidth>1</bitWidth>
9200 <description>Trigger generation
</description>
9201 <bitOffset>6</bitOffset>
9202 <bitWidth>1</bitWidth>
9206 <description>Capture/Compare control update
9207 generation
</description>
9208 <bitOffset>5</bitOffset>
9209 <bitWidth>1</bitWidth>
9213 <description>Capture/compare
1
9214 generation
</description>
9215 <bitOffset>1</bitOffset>
9216 <bitWidth>1</bitWidth>
9220 <description>Update generation
</description>
9221 <bitOffset>0</bitOffset>
9222 <bitWidth>1</bitWidth>
9227 <name>CCMR1_Output
</name>
9228 <displayName>CCMR1_Output
</displayName>
9229 <description>capture/compare mode register (output
9231 <addressOffset>0x18</addressOffset>
9233 <access>read-write
</access>
9234 <resetValue>0x00000000</resetValue>
9238 <description>Capture/Compare
1
9239 selection
</description>
9240 <bitOffset>0</bitOffset>
9241 <bitWidth>2</bitWidth>
9245 <description>Output Compare
1 fast
9246 enable
</description>
9247 <bitOffset>2</bitOffset>
9248 <bitWidth>1</bitWidth>
9252 <description>Output Compare
1 preload
9253 enable
</description>
9254 <bitOffset>3</bitOffset>
9255 <bitWidth>1</bitWidth>
9259 <description>Output Compare
1 mode
</description>
9260 <bitOffset>4</bitOffset>
9261 <bitWidth>3</bitWidth>
9265 <description>Output Compare
1 mode
</description>
9266 <bitOffset>16</bitOffset>
9267 <bitWidth>1</bitWidth>
9272 <name>CCMR1_Input
</name>
9273 <displayName>CCMR1_Input
</displayName>
9274 <description>capture/compare mode register
1 (input
9276 <alternateRegister>CCMR1_Output
</alternateRegister>
9277 <addressOffset>0x18</addressOffset>
9279 <access>read-write
</access>
9280 <resetValue>0x00000000</resetValue>
9284 <description>Input capture
1 filter
</description>
9285 <bitOffset>4</bitOffset>
9286 <bitWidth>4</bitWidth>
9290 <description>Input capture
1 prescaler
</description>
9291 <bitOffset>2</bitOffset>
9292 <bitWidth>2</bitWidth>
9296 <description>Capture/Compare
1
9297 selection
</description>
9298 <bitOffset>0</bitOffset>
9299 <bitWidth>2</bitWidth>
9305 <displayName>CCER
</displayName>
9306 <description>capture/compare enable
9307 register
</description>
9308 <addressOffset>0x20</addressOffset>
9310 <access>read-write
</access>
9311 <resetValue>0x0000</resetValue>
9315 <description>Capture/Compare
1 output
9316 Polarity
</description>
9317 <bitOffset>3</bitOffset>
9318 <bitWidth>1</bitWidth>
9322 <description>Capture/Compare
1 complementary output
9323 enable
</description>
9324 <bitOffset>2</bitOffset>
9325 <bitWidth>1</bitWidth>
9329 <description>Capture/Compare
1 output
9330 Polarity
</description>
9331 <bitOffset>1</bitOffset>
9332 <bitWidth>1</bitWidth>
9336 <description>Capture/Compare
1 output
9337 enable
</description>
9338 <bitOffset>0</bitOffset>
9339 <bitWidth>1</bitWidth>
9345 <displayName>CNT
</displayName>
9346 <description>counter
</description>
9347 <addressOffset>0x24</addressOffset>
9349 <resetValue>0x00000000</resetValue>
9353 <description>counter value
</description>
9354 <bitOffset>0</bitOffset>
9355 <bitWidth>16</bitWidth>
9356 <access>read-write
</access>
9360 <description>UIF Copy
</description>
9361 <bitOffset>31</bitOffset>
9362 <bitWidth>1</bitWidth>
9363 <access>read-only
</access>
9369 <displayName>PSC
</displayName>
9370 <description>prescaler
</description>
9371 <addressOffset>0x28</addressOffset>
9373 <access>read-write
</access>
9374 <resetValue>0x0000</resetValue>
9378 <description>Prescaler value
</description>
9379 <bitOffset>0</bitOffset>
9380 <bitWidth>16</bitWidth>
9386 <displayName>ARR
</displayName>
9387 <description>auto-reload register
</description>
9388 <addressOffset>0x2C</addressOffset>
9390 <access>read-write
</access>
9391 <resetValue>0x00000000</resetValue>
9395 <description>Auto-reload value
</description>
9396 <bitOffset>0</bitOffset>
9397 <bitWidth>16</bitWidth>
9403 <displayName>RCR
</displayName>
9404 <description>repetition counter register
</description>
9405 <addressOffset>0x30</addressOffset>
9407 <access>read-write
</access>
9408 <resetValue>0x0000</resetValue>
9412 <description>Repetition counter value
</description>
9413 <bitOffset>0</bitOffset>
9414 <bitWidth>8</bitWidth>
9420 <displayName>CCR1
</displayName>
9421 <description>capture/compare register
1</description>
9422 <addressOffset>0x34</addressOffset>
9424 <access>read-write
</access>
9425 <resetValue>0x00000000</resetValue>
9429 <description>Capture/Compare
1 value
</description>
9430 <bitOffset>0</bitOffset>
9431 <bitWidth>16</bitWidth>
9437 <displayName>BDTR
</displayName>
9438 <description>break and dead-time register
</description>
9439 <addressOffset>0x44</addressOffset>
9441 <access>read-write
</access>
9442 <resetValue>0x0000</resetValue>
9446 <description>Dead-time generator setup
</description>
9447 <bitOffset>0</bitOffset>
9448 <bitWidth>8</bitWidth>
9452 <description>Lock configuration
</description>
9453 <bitOffset>8</bitOffset>
9454 <bitWidth>2</bitWidth>
9458 <description>Off-state selection for Idle
9460 <bitOffset>10</bitOffset>
9461 <bitWidth>1</bitWidth>
9465 <description>Off-state selection for Run
9467 <bitOffset>11</bitOffset>
9468 <bitWidth>1</bitWidth>
9472 <description>Break enable
</description>
9473 <bitOffset>12</bitOffset>
9474 <bitWidth>1</bitWidth>
9478 <description>Break polarity
</description>
9479 <bitOffset>13</bitOffset>
9480 <bitWidth>1</bitWidth>
9484 <description>Automatic output enable
</description>
9485 <bitOffset>14</bitOffset>
9486 <bitWidth>1</bitWidth>
9490 <description>Main output enable
</description>
9491 <bitOffset>15</bitOffset>
9492 <bitWidth>1</bitWidth>
9496 <description>Break filter
</description>
9497 <bitOffset>16</bitOffset>
9498 <bitWidth>4</bitWidth>
9504 <displayName>DCR
</displayName>
9505 <description>DMA control register
</description>
9506 <addressOffset>0x48</addressOffset>
9508 <access>read-write
</access>
9509 <resetValue>0x0000</resetValue>
9513 <description>DMA burst length
</description>
9514 <bitOffset>8</bitOffset>
9515 <bitWidth>5</bitWidth>
9519 <description>DMA base address
</description>
9520 <bitOffset>0</bitOffset>
9521 <bitWidth>5</bitWidth>
9527 <displayName>DMAR
</displayName>
9528 <description>DMA address for full transfer
</description>
9529 <addressOffset>0x4C</addressOffset>
9531 <access>read-write
</access>
9532 <resetValue>0x0000</resetValue>
9536 <description>DMA register for burst
9537 accesses
</description>
9538 <bitOffset>0</bitOffset>
9539 <bitWidth>16</bitWidth>
9545 <displayName>OR
</displayName>
9546 <description>option register
</description>
9547 <addressOffset>0x50</addressOffset>
9549 <access>read-write
</access>
9550 <resetValue>0x0000</resetValue>
9556 <description>General purpose timer
</description>
9557 <groupName>TIMs
</groupName>
9558 <baseAddress>0x40014800</baseAddress>
9560 <offset>0x0</offset>
9562 <usage>registers
</usage>
9565 <name>TIM1_TRG_COM_TIM17
</name>
9566 <description>TIM1 trigger and commutation/TIM17
9567 interrupts
</description>
9573 <displayName>CR1
</displayName>
9574 <description>control register
1</description>
9575 <addressOffset>0x0</addressOffset>
9577 <access>read-write
</access>
9578 <resetValue>0x0000</resetValue>
9582 <description>Counter enable
</description>
9583 <bitOffset>0</bitOffset>
9584 <bitWidth>1</bitWidth>
9588 <description>Update disable
</description>
9589 <bitOffset>1</bitOffset>
9590 <bitWidth>1</bitWidth>
9594 <description>Update request source
</description>
9595 <bitOffset>2</bitOffset>
9596 <bitWidth>1</bitWidth>
9600 <description>One-pulse mode
</description>
9601 <bitOffset>3</bitOffset>
9602 <bitWidth>1</bitWidth>
9606 <description>Auto-reload preload enable
</description>
9607 <bitOffset>7</bitOffset>
9608 <bitWidth>1</bitWidth>
9612 <description>Clock division
</description>
9613 <bitOffset>8</bitOffset>
9614 <bitWidth>2</bitWidth>
9617 <name>UIFREMAP
</name>
9618 <description>UIF status bit remapping
</description>
9619 <bitOffset>11</bitOffset>
9620 <bitWidth>1</bitWidth>
9626 <displayName>CR2
</displayName>
9627 <description>control register
2</description>
9628 <addressOffset>0x4</addressOffset>
9630 <access>read-write
</access>
9631 <resetValue>0x0000</resetValue>
9635 <description>Output Idle state
1</description>
9636 <bitOffset>9</bitOffset>
9637 <bitWidth>1</bitWidth>
9641 <description>Output Idle state
1</description>
9642 <bitOffset>8</bitOffset>
9643 <bitWidth>1</bitWidth>
9647 <description>Capture/compare DMA
9648 selection
</description>
9649 <bitOffset>3</bitOffset>
9650 <bitWidth>1</bitWidth>
9654 <description>Capture/compare control update
9655 selection
</description>
9656 <bitOffset>2</bitOffset>
9657 <bitWidth>1</bitWidth>
9661 <description>Capture/compare preloaded
9662 control
</description>
9663 <bitOffset>0</bitOffset>
9664 <bitWidth>1</bitWidth>
9670 <displayName>DIER
</displayName>
9671 <description>DMA/Interrupt enable register
</description>
9672 <addressOffset>0xC</addressOffset>
9674 <access>read-write
</access>
9675 <resetValue>0x0000</resetValue>
9679 <description>Update interrupt enable
</description>
9680 <bitOffset>0</bitOffset>
9681 <bitWidth>1</bitWidth>
9685 <description>Capture/Compare
1 interrupt
9686 enable
</description>
9687 <bitOffset>1</bitOffset>
9688 <bitWidth>1</bitWidth>
9692 <description>COM interrupt enable
</description>
9693 <bitOffset>5</bitOffset>
9694 <bitWidth>1</bitWidth>
9698 <description>Trigger interrupt enable
</description>
9699 <bitOffset>6</bitOffset>
9700 <bitWidth>1</bitWidth>
9704 <description>Break interrupt enable
</description>
9705 <bitOffset>7</bitOffset>
9706 <bitWidth>1</bitWidth>
9710 <description>Update DMA request enable
</description>
9711 <bitOffset>8</bitOffset>
9712 <bitWidth>1</bitWidth>
9716 <description>Capture/Compare
1 DMA request
9717 enable
</description>
9718 <bitOffset>9</bitOffset>
9719 <bitWidth>1</bitWidth>
9723 <description>COM DMA request enable
</description>
9724 <bitOffset>13</bitOffset>
9725 <bitWidth>1</bitWidth>
9729 <description>Trigger DMA request enable
</description>
9730 <bitOffset>14</bitOffset>
9731 <bitWidth>1</bitWidth>
9737 <displayName>SR
</displayName>
9738 <description>status register
</description>
9739 <addressOffset>0x10</addressOffset>
9741 <access>read-write
</access>
9742 <resetValue>0x0000</resetValue>
9746 <description>Capture/Compare
1 overcapture
9748 <bitOffset>9</bitOffset>
9749 <bitWidth>1</bitWidth>
9753 <description>Break interrupt flag
</description>
9754 <bitOffset>7</bitOffset>
9755 <bitWidth>1</bitWidth>
9759 <description>Trigger interrupt flag
</description>
9760 <bitOffset>6</bitOffset>
9761 <bitWidth>1</bitWidth>
9765 <description>COM interrupt flag
</description>
9766 <bitOffset>5</bitOffset>
9767 <bitWidth>1</bitWidth>
9771 <description>Capture/compare
1 interrupt
9773 <bitOffset>1</bitOffset>
9774 <bitWidth>1</bitWidth>
9778 <description>Update interrupt flag
</description>
9779 <bitOffset>0</bitOffset>
9780 <bitWidth>1</bitWidth>
9786 <displayName>EGR
</displayName>
9787 <description>event generation register
</description>
9788 <addressOffset>0x14</addressOffset>
9790 <access>write-only
</access>
9791 <resetValue>0x0000</resetValue>
9795 <description>Break generation
</description>
9796 <bitOffset>7</bitOffset>
9797 <bitWidth>1</bitWidth>
9801 <description>Trigger generation
</description>
9802 <bitOffset>6</bitOffset>
9803 <bitWidth>1</bitWidth>
9807 <description>Capture/Compare control update
9808 generation
</description>
9809 <bitOffset>5</bitOffset>
9810 <bitWidth>1</bitWidth>
9814 <description>Capture/compare
1
9815 generation
</description>
9816 <bitOffset>1</bitOffset>
9817 <bitWidth>1</bitWidth>
9821 <description>Update generation
</description>
9822 <bitOffset>0</bitOffset>
9823 <bitWidth>1</bitWidth>
9828 <name>CCMR1_Output
</name>
9829 <displayName>CCMR1_Output
</displayName>
9830 <description>capture/compare mode register (output
9832 <addressOffset>0x18</addressOffset>
9834 <access>read-write
</access>
9835 <resetValue>0x00000000</resetValue>
9839 <description>Capture/Compare
1
9840 selection
</description>
9841 <bitOffset>0</bitOffset>
9842 <bitWidth>2</bitWidth>
9846 <description>Output Compare
1 fast
9847 enable
</description>
9848 <bitOffset>2</bitOffset>
9849 <bitWidth>1</bitWidth>
9853 <description>Output Compare
1 preload
9854 enable
</description>
9855 <bitOffset>3</bitOffset>
9856 <bitWidth>1</bitWidth>
9860 <description>Output Compare
1 mode
</description>
9861 <bitOffset>4</bitOffset>
9862 <bitWidth>3</bitWidth>
9866 <description>Output Compare
1 mode
</description>
9867 <bitOffset>16</bitOffset>
9868 <bitWidth>1</bitWidth>
9873 <name>CCMR1_Input
</name>
9874 <displayName>CCMR1_Input
</displayName>
9875 <description>capture/compare mode register
1 (input
9877 <alternateRegister>CCMR1_Output
</alternateRegister>
9878 <addressOffset>0x18</addressOffset>
9880 <access>read-write
</access>
9881 <resetValue>0x00000000</resetValue>
9885 <description>Input capture
1 filter
</description>
9886 <bitOffset>4</bitOffset>
9887 <bitWidth>4</bitWidth>
9891 <description>Input capture
1 prescaler
</description>
9892 <bitOffset>2</bitOffset>
9893 <bitWidth>2</bitWidth>
9897 <description>Capture/Compare
1
9898 selection
</description>
9899 <bitOffset>0</bitOffset>
9900 <bitWidth>2</bitWidth>
9906 <displayName>CCER
</displayName>
9907 <description>capture/compare enable
9908 register
</description>
9909 <addressOffset>0x20</addressOffset>
9911 <access>read-write
</access>
9912 <resetValue>0x0000</resetValue>
9916 <description>Capture/Compare
1 output
9917 Polarity
</description>
9918 <bitOffset>3</bitOffset>
9919 <bitWidth>1</bitWidth>
9923 <description>Capture/Compare
1 complementary output
9924 enable
</description>
9925 <bitOffset>2</bitOffset>
9926 <bitWidth>1</bitWidth>
9930 <description>Capture/Compare
1 output
9931 Polarity
</description>
9932 <bitOffset>1</bitOffset>
9933 <bitWidth>1</bitWidth>
9937 <description>Capture/Compare
1 output
9938 enable
</description>
9939 <bitOffset>0</bitOffset>
9940 <bitWidth>1</bitWidth>
9946 <displayName>CNT
</displayName>
9947 <description>counter
</description>
9948 <addressOffset>0x24</addressOffset>
9950 <resetValue>0x00000000</resetValue>
9954 <description>counter value
</description>
9955 <bitOffset>0</bitOffset>
9956 <bitWidth>16</bitWidth>
9957 <access>read-write
</access>
9961 <description>UIF Copy
</description>
9962 <bitOffset>31</bitOffset>
9963 <bitWidth>1</bitWidth>
9964 <access>read-only
</access>
9970 <displayName>PSC
</displayName>
9971 <description>prescaler
</description>
9972 <addressOffset>0x28</addressOffset>
9974 <access>read-write
</access>
9975 <resetValue>0x0000</resetValue>
9979 <description>Prescaler value
</description>
9980 <bitOffset>0</bitOffset>
9981 <bitWidth>16</bitWidth>
9987 <displayName>ARR
</displayName>
9988 <description>auto-reload register
</description>
9989 <addressOffset>0x2C</addressOffset>
9991 <access>read-write
</access>
9992 <resetValue>0x00000000</resetValue>
9996 <description>Auto-reload value
</description>
9997 <bitOffset>0</bitOffset>
9998 <bitWidth>16</bitWidth>
10004 <displayName>RCR
</displayName>
10005 <description>repetition counter register
</description>
10006 <addressOffset>0x30</addressOffset>
10008 <access>read-write
</access>
10009 <resetValue>0x0000</resetValue>
10013 <description>Repetition counter value
</description>
10014 <bitOffset>0</bitOffset>
10015 <bitWidth>8</bitWidth>
10021 <displayName>CCR1
</displayName>
10022 <description>capture/compare register
1</description>
10023 <addressOffset>0x34</addressOffset>
10025 <access>read-write
</access>
10026 <resetValue>0x00000000</resetValue>
10030 <description>Capture/Compare
1 value
</description>
10031 <bitOffset>0</bitOffset>
10032 <bitWidth>16</bitWidth>
10038 <displayName>BDTR
</displayName>
10039 <description>break and dead-time register
</description>
10040 <addressOffset>0x44</addressOffset>
10042 <access>read-write
</access>
10043 <resetValue>0x0000</resetValue>
10047 <description>Dead-time generator setup
</description>
10048 <bitOffset>0</bitOffset>
10049 <bitWidth>8</bitWidth>
10053 <description>Lock configuration
</description>
10054 <bitOffset>8</bitOffset>
10055 <bitWidth>2</bitWidth>
10059 <description>Off-state selection for Idle
10061 <bitOffset>10</bitOffset>
10062 <bitWidth>1</bitWidth>
10066 <description>Off-state selection for Run
10068 <bitOffset>11</bitOffset>
10069 <bitWidth>1</bitWidth>
10073 <description>Break enable
</description>
10074 <bitOffset>12</bitOffset>
10075 <bitWidth>1</bitWidth>
10079 <description>Break polarity
</description>
10080 <bitOffset>13</bitOffset>
10081 <bitWidth>1</bitWidth>
10085 <description>Automatic output enable
</description>
10086 <bitOffset>14</bitOffset>
10087 <bitWidth>1</bitWidth>
10091 <description>Main output enable
</description>
10092 <bitOffset>15</bitOffset>
10093 <bitWidth>1</bitWidth>
10097 <description>Break filter
</description>
10098 <bitOffset>16</bitOffset>
10099 <bitWidth>4</bitWidth>
10105 <displayName>DCR
</displayName>
10106 <description>DMA control register
</description>
10107 <addressOffset>0x48</addressOffset>
10109 <access>read-write
</access>
10110 <resetValue>0x0000</resetValue>
10114 <description>DMA burst length
</description>
10115 <bitOffset>8</bitOffset>
10116 <bitWidth>5</bitWidth>
10120 <description>DMA base address
</description>
10121 <bitOffset>0</bitOffset>
10122 <bitWidth>5</bitWidth>
10128 <displayName>DMAR
</displayName>
10129 <description>DMA address for full transfer
</description>
10130 <addressOffset>0x4C</addressOffset>
10132 <access>read-write
</access>
10133 <resetValue>0x0000</resetValue>
10137 <description>DMA register for burst
10138 accesses
</description>
10139 <bitOffset>0</bitOffset>
10140 <bitWidth>16</bitWidth>
10147 <name>USART1
</name>
10148 <description>Universal synchronous asynchronous receiver
10149 transmitter
</description>
10150 <groupName>USART
</groupName>
10151 <baseAddress>0x40013800</baseAddress>
10153 <offset>0x0</offset>
10155 <usage>registers
</usage>
10158 <name>USART1_EXTI25
</name>
10159 <description>USART1 global interrupt and EXTI Line
25
10160 interrupt
</description>
10166 <displayName>CR1
</displayName>
10167 <description>Control register
1</description>
10168 <addressOffset>0x0</addressOffset>
10170 <access>read-write
</access>
10171 <resetValue>0x0000</resetValue>
10175 <description>End of Block interrupt
10176 enable
</description>
10177 <bitOffset>27</bitOffset>
10178 <bitWidth>1</bitWidth>
10182 <description>Receiver timeout interrupt
10183 enable
</description>
10184 <bitOffset>26</bitOffset>
10185 <bitWidth>1</bitWidth>
10189 <description>Driver Enable assertion
10191 <bitOffset>21</bitOffset>
10192 <bitWidth>5</bitWidth>
10196 <description>Driver Enable deassertion
10198 <bitOffset>16</bitOffset>
10199 <bitWidth>5</bitWidth>
10203 <description>Oversampling mode
</description>
10204 <bitOffset>15</bitOffset>
10205 <bitWidth>1</bitWidth>
10209 <description>Character match interrupt
10210 enable
</description>
10211 <bitOffset>14</bitOffset>
10212 <bitWidth>1</bitWidth>
10216 <description>Mute mode enable
</description>
10217 <bitOffset>13</bitOffset>
10218 <bitWidth>1</bitWidth>
10222 <description>Word length
</description>
10223 <bitOffset>12</bitOffset>
10224 <bitWidth>1</bitWidth>
10228 <description>Receiver wakeup method
</description>
10229 <bitOffset>11</bitOffset>
10230 <bitWidth>1</bitWidth>
10234 <description>Parity control enable
</description>
10235 <bitOffset>10</bitOffset>
10236 <bitWidth>1</bitWidth>
10240 <description>Parity selection
</description>
10241 <bitOffset>9</bitOffset>
10242 <bitWidth>1</bitWidth>
10246 <description>PE interrupt enable
</description>
10247 <bitOffset>8</bitOffset>
10248 <bitWidth>1</bitWidth>
10252 <description>interrupt enable
</description>
10253 <bitOffset>7</bitOffset>
10254 <bitWidth>1</bitWidth>
10258 <description>Transmission complete interrupt
10259 enable
</description>
10260 <bitOffset>6</bitOffset>
10261 <bitWidth>1</bitWidth>
10264 <name>RXNEIE
</name>
10265 <description>RXNE interrupt enable
</description>
10266 <bitOffset>5</bitOffset>
10267 <bitWidth>1</bitWidth>
10270 <name>IDLEIE
</name>
10271 <description>IDLE interrupt enable
</description>
10272 <bitOffset>4</bitOffset>
10273 <bitWidth>1</bitWidth>
10277 <description>Transmitter enable
</description>
10278 <bitOffset>3</bitOffset>
10279 <bitWidth>1</bitWidth>
10283 <description>Receiver enable
</description>
10284 <bitOffset>2</bitOffset>
10285 <bitWidth>1</bitWidth>
10289 <description>USART enable in Stop mode
</description>
10290 <bitOffset>1</bitOffset>
10291 <bitWidth>1</bitWidth>
10295 <description>USART enable
</description>
10296 <bitOffset>0</bitOffset>
10297 <bitWidth>1</bitWidth>
10303 <displayName>CR2
</displayName>
10304 <description>Control register
2</description>
10305 <addressOffset>0x4</addressOffset>
10307 <access>read-write
</access>
10308 <resetValue>0x0000</resetValue>
10312 <description>Address of the USART node
</description>
10313 <bitOffset>28</bitOffset>
10314 <bitWidth>4</bitWidth>
10318 <description>Address of the USART node
</description>
10319 <bitOffset>24</bitOffset>
10320 <bitWidth>4</bitWidth>
10324 <description>Receiver timeout enable
</description>
10325 <bitOffset>23</bitOffset>
10326 <bitWidth>1</bitWidth>
10329 <name>ABRMOD
</name>
10330 <description>Auto baud rate mode
</description>
10331 <bitOffset>21</bitOffset>
10332 <bitWidth>2</bitWidth>
10336 <description>Auto baud rate enable
</description>
10337 <bitOffset>20</bitOffset>
10338 <bitWidth>1</bitWidth>
10341 <name>MSBFIRST
</name>
10342 <description>Most significant bit first
</description>
10343 <bitOffset>19</bitOffset>
10344 <bitWidth>1</bitWidth>
10347 <name>DATAINV
</name>
10348 <description>Binary data inversion
</description>
10349 <bitOffset>18</bitOffset>
10350 <bitWidth>1</bitWidth>
10354 <description>TX pin active level
10355 inversion
</description>
10356 <bitOffset>17</bitOffset>
10357 <bitWidth>1</bitWidth>
10361 <description>RX pin active level
10362 inversion
</description>
10363 <bitOffset>16</bitOffset>
10364 <bitWidth>1</bitWidth>
10368 <description>Swap TX/RX pins
</description>
10369 <bitOffset>15</bitOffset>
10370 <bitWidth>1</bitWidth>
10374 <description>LIN mode enable
</description>
10375 <bitOffset>14</bitOffset>
10376 <bitWidth>1</bitWidth>
10380 <description>STOP bits
</description>
10381 <bitOffset>12</bitOffset>
10382 <bitWidth>2</bitWidth>
10386 <description>Clock enable
</description>
10387 <bitOffset>11</bitOffset>
10388 <bitWidth>1</bitWidth>
10392 <description>Clock polarity
</description>
10393 <bitOffset>10</bitOffset>
10394 <bitWidth>1</bitWidth>
10398 <description>Clock phase
</description>
10399 <bitOffset>9</bitOffset>
10400 <bitWidth>1</bitWidth>
10404 <description>Last bit clock pulse
</description>
10405 <bitOffset>8</bitOffset>
10406 <bitWidth>1</bitWidth>
10410 <description>LIN break detection interrupt
10411 enable
</description>
10412 <bitOffset>6</bitOffset>
10413 <bitWidth>1</bitWidth>
10417 <description>LIN break detection length
</description>
10418 <bitOffset>5</bitOffset>
10419 <bitWidth>1</bitWidth>
10423 <description>7-bit Address Detection/
4-bit Address
10424 Detection
</description>
10425 <bitOffset>4</bitOffset>
10426 <bitWidth>1</bitWidth>
10432 <displayName>CR3
</displayName>
10433 <description>Control register
3</description>
10434 <addressOffset>0x8</addressOffset>
10436 <access>read-write
</access>
10437 <resetValue>0x0000</resetValue>
10441 <description>Wakeup from Stop mode interrupt
10442 enable
</description>
10443 <bitOffset>22</bitOffset>
10444 <bitWidth>1</bitWidth>
10448 <description>Wakeup from Stop mode interrupt flag
10449 selection
</description>
10450 <bitOffset>20</bitOffset>
10451 <bitWidth>2</bitWidth>
10454 <name>SCARCNT
</name>
10455 <description>Smartcard auto-retry count
</description>
10456 <bitOffset>17</bitOffset>
10457 <bitWidth>3</bitWidth>
10461 <description>Driver enable polarity
10462 selection
</description>
10463 <bitOffset>15</bitOffset>
10464 <bitWidth>1</bitWidth>
10468 <description>Driver enable mode
</description>
10469 <bitOffset>14</bitOffset>
10470 <bitWidth>1</bitWidth>
10474 <description>DMA Disable on Reception
10475 Error
</description>
10476 <bitOffset>13</bitOffset>
10477 <bitWidth>1</bitWidth>
10480 <name>OVRDIS
</name>
10481 <description>Overrun Disable
</description>
10482 <bitOffset>12</bitOffset>
10483 <bitWidth>1</bitWidth>
10486 <name>ONEBIT
</name>
10487 <description>One sample bit method
10488 enable
</description>
10489 <bitOffset>11</bitOffset>
10490 <bitWidth>1</bitWidth>
10494 <description>CTS interrupt enable
</description>
10495 <bitOffset>10</bitOffset>
10496 <bitWidth>1</bitWidth>
10500 <description>CTS enable
</description>
10501 <bitOffset>9</bitOffset>
10502 <bitWidth>1</bitWidth>
10506 <description>RTS enable
</description>
10507 <bitOffset>8</bitOffset>
10508 <bitWidth>1</bitWidth>
10512 <description>DMA enable transmitter
</description>
10513 <bitOffset>7</bitOffset>
10514 <bitWidth>1</bitWidth>
10518 <description>DMA enable receiver
</description>
10519 <bitOffset>6</bitOffset>
10520 <bitWidth>1</bitWidth>
10524 <description>Smartcard mode enable
</description>
10525 <bitOffset>5</bitOffset>
10526 <bitWidth>1</bitWidth>
10530 <description>Smartcard NACK enable
</description>
10531 <bitOffset>4</bitOffset>
10532 <bitWidth>1</bitWidth>
10536 <description>Half-duplex selection
</description>
10537 <bitOffset>3</bitOffset>
10538 <bitWidth>1</bitWidth>
10542 <description>IrDA low-power
</description>
10543 <bitOffset>2</bitOffset>
10544 <bitWidth>1</bitWidth>
10548 <description>IrDA mode enable
</description>
10549 <bitOffset>1</bitOffset>
10550 <bitWidth>1</bitWidth>
10554 <description>Error interrupt enable
</description>
10555 <bitOffset>0</bitOffset>
10556 <bitWidth>1</bitWidth>
10562 <displayName>BRR
</displayName>
10563 <description>Baud rate register
</description>
10564 <addressOffset>0xC</addressOffset>
10566 <access>read-write
</access>
10567 <resetValue>0x0000</resetValue>
10570 <name>DIV_Mantissa
</name>
10571 <description>mantissa of USARTDIV
</description>
10572 <bitOffset>4</bitOffset>
10573 <bitWidth>12</bitWidth>
10576 <name>DIV_Fraction
</name>
10577 <description>fraction of USARTDIV
</description>
10578 <bitOffset>0</bitOffset>
10579 <bitWidth>4</bitWidth>
10585 <displayName>GTPR
</displayName>
10586 <description>Guard time and prescaler
10587 register
</description>
10588 <addressOffset>0x10</addressOffset>
10590 <access>read-write
</access>
10591 <resetValue>0x0000</resetValue>
10595 <description>Guard time value
</description>
10596 <bitOffset>8</bitOffset>
10597 <bitWidth>8</bitWidth>
10601 <description>Prescaler value
</description>
10602 <bitOffset>0</bitOffset>
10603 <bitWidth>8</bitWidth>
10609 <displayName>RTOR
</displayName>
10610 <description>Receiver timeout register
</description>
10611 <addressOffset>0x14</addressOffset>
10613 <access>read-write
</access>
10614 <resetValue>0x0000</resetValue>
10618 <description>Block Length
</description>
10619 <bitOffset>24</bitOffset>
10620 <bitWidth>8</bitWidth>
10624 <description>Receiver timeout value
</description>
10625 <bitOffset>0</bitOffset>
10626 <bitWidth>24</bitWidth>
10632 <displayName>RQR
</displayName>
10633 <description>Request register
</description>
10634 <addressOffset>0x18</addressOffset>
10636 <access>read-write
</access>
10637 <resetValue>0x0000</resetValue>
10641 <description>Transmit data flush
10642 request
</description>
10643 <bitOffset>4</bitOffset>
10644 <bitWidth>1</bitWidth>
10648 <description>Receive data flush request
</description>
10649 <bitOffset>3</bitOffset>
10650 <bitWidth>1</bitWidth>
10654 <description>Mute mode request
</description>
10655 <bitOffset>2</bitOffset>
10656 <bitWidth>1</bitWidth>
10660 <description>Send break request
</description>
10661 <bitOffset>1</bitOffset>
10662 <bitWidth>1</bitWidth>
10666 <description>Auto baud rate request
</description>
10667 <bitOffset>0</bitOffset>
10668 <bitWidth>1</bitWidth>
10674 <displayName>ISR
</displayName>
10675 <description>Interrupt
& status
10676 register
</description>
10677 <addressOffset>0x1C</addressOffset>
10679 <access>read-only
</access>
10680 <resetValue>0x00C0</resetValue>
10684 <description>Receive enable acknowledge
10686 <bitOffset>22</bitOffset>
10687 <bitWidth>1</bitWidth>
10691 <description>Transmit enable acknowledge
10693 <bitOffset>21</bitOffset>
10694 <bitWidth>1</bitWidth>
10698 <description>Wakeup from Stop mode flag
</description>
10699 <bitOffset>20</bitOffset>
10700 <bitWidth>1</bitWidth>
10704 <description>Receiver wakeup from Mute
10706 <bitOffset>19</bitOffset>
10707 <bitWidth>1</bitWidth>
10711 <description>Send break flag
</description>
10712 <bitOffset>18</bitOffset>
10713 <bitWidth>1</bitWidth>
10717 <description>character match flag
</description>
10718 <bitOffset>17</bitOffset>
10719 <bitWidth>1</bitWidth>
10723 <description>Busy flag
</description>
10724 <bitOffset>16</bitOffset>
10725 <bitWidth>1</bitWidth>
10729 <description>Auto baud rate flag
</description>
10730 <bitOffset>15</bitOffset>
10731 <bitWidth>1</bitWidth>
10735 <description>Auto baud rate error
</description>
10736 <bitOffset>14</bitOffset>
10737 <bitWidth>1</bitWidth>
10741 <description>End of block flag
</description>
10742 <bitOffset>12</bitOffset>
10743 <bitWidth>1</bitWidth>
10747 <description>Receiver timeout
</description>
10748 <bitOffset>11</bitOffset>
10749 <bitWidth>1</bitWidth>
10753 <description>CTS flag
</description>
10754 <bitOffset>10</bitOffset>
10755 <bitWidth>1</bitWidth>
10759 <description>CTS interrupt flag
</description>
10760 <bitOffset>9</bitOffset>
10761 <bitWidth>1</bitWidth>
10765 <description>LIN break detection flag
</description>
10766 <bitOffset>8</bitOffset>
10767 <bitWidth>1</bitWidth>
10771 <description>Transmit data register
10772 empty
</description>
10773 <bitOffset>7</bitOffset>
10774 <bitWidth>1</bitWidth>
10778 <description>Transmission complete
</description>
10779 <bitOffset>6</bitOffset>
10780 <bitWidth>1</bitWidth>
10784 <description>Read data register not
10785 empty
</description>
10786 <bitOffset>5</bitOffset>
10787 <bitWidth>1</bitWidth>
10791 <description>Idle line detected
</description>
10792 <bitOffset>4</bitOffset>
10793 <bitWidth>1</bitWidth>
10797 <description>Overrun error
</description>
10798 <bitOffset>3</bitOffset>
10799 <bitWidth>1</bitWidth>
10803 <description>Noise detected flag
</description>
10804 <bitOffset>2</bitOffset>
10805 <bitWidth>1</bitWidth>
10809 <description>Framing error
</description>
10810 <bitOffset>1</bitOffset>
10811 <bitWidth>1</bitWidth>
10815 <description>Parity error
</description>
10816 <bitOffset>0</bitOffset>
10817 <bitWidth>1</bitWidth>
10823 <displayName>ICR
</displayName>
10824 <description>Interrupt flag clear register
</description>
10825 <addressOffset>0x20</addressOffset>
10827 <access>read-write
</access>
10828 <resetValue>0x0000</resetValue>
10832 <description>Wakeup from Stop mode clear
10834 <bitOffset>20</bitOffset>
10835 <bitWidth>1</bitWidth>
10839 <description>Character match clear flag
</description>
10840 <bitOffset>17</bitOffset>
10841 <bitWidth>1</bitWidth>
10845 <description>End of timeout clear flag
</description>
10846 <bitOffset>12</bitOffset>
10847 <bitWidth>1</bitWidth>
10851 <description>Receiver timeout clear
10853 <bitOffset>11</bitOffset>
10854 <bitWidth>1</bitWidth>
10858 <description>CTS clear flag
</description>
10859 <bitOffset>9</bitOffset>
10860 <bitWidth>1</bitWidth>
10864 <description>LIN break detection clear
10866 <bitOffset>8</bitOffset>
10867 <bitWidth>1</bitWidth>
10871 <description>Transmission complete clear
10873 <bitOffset>6</bitOffset>
10874 <bitWidth>1</bitWidth>
10877 <name>IDLECF
</name>
10878 <description>Idle line detected clear
10880 <bitOffset>4</bitOffset>
10881 <bitWidth>1</bitWidth>
10885 <description>Overrun error clear flag
</description>
10886 <bitOffset>3</bitOffset>
10887 <bitWidth>1</bitWidth>
10891 <description>Noise detected clear flag
</description>
10892 <bitOffset>2</bitOffset>
10893 <bitWidth>1</bitWidth>
10897 <description>Framing error clear flag
</description>
10898 <bitOffset>1</bitOffset>
10899 <bitWidth>1</bitWidth>
10903 <description>Parity error clear flag
</description>
10904 <bitOffset>0</bitOffset>
10905 <bitWidth>1</bitWidth>
10911 <displayName>RDR
</displayName>
10912 <description>Receive data register
</description>
10913 <addressOffset>0x24</addressOffset>
10915 <access>read-only
</access>
10916 <resetValue>0x0000</resetValue>
10920 <description>Receive data value
</description>
10921 <bitOffset>0</bitOffset>
10922 <bitWidth>9</bitWidth>
10928 <displayName>TDR
</displayName>
10929 <description>Transmit data register
</description>
10930 <addressOffset>0x28</addressOffset>
10932 <access>read-write
</access>
10933 <resetValue>0x0000</resetValue>
10937 <description>Transmit data value
</description>
10938 <bitOffset>0</bitOffset>
10939 <bitWidth>9</bitWidth>
10945 <peripheral derivedFrom=
"USART1">
10946 <name>USART2
</name>
10947 <baseAddress>0x40004400</baseAddress>
10949 <name>USART2_EXTI26
</name>
10950 <description>USART2 global interrupt and EXTI Line
26
10951 interrupt
</description>
10955 <peripheral derivedFrom=
"USART1">
10956 <name>USART3
</name>
10957 <baseAddress>0x40004800</baseAddress>
10959 <name>USART3_EXTI28
</name>
10960 <description>USART3 global interrupt and EXTI Line
28
10961 interrupt
</description>
10965 <peripheral derivedFrom=
"USART1">
10967 <baseAddress>0x40004C00</baseAddress>
10969 <name>UART4_EXTI34
</name>
10970 <description>UART4 global and EXTI Line
34
10971 interrupts
</description>
10975 <peripheral derivedFrom=
"USART1">
10977 <baseAddress>0x40005000</baseAddress>
10979 <name>UART5_EXTI35
</name>
10980 <description>UART5 global and EXTI Line
35
10981 interrupts
</description>
10987 <description>Serial peripheral interface/Inter-IC
10988 sound
</description>
10989 <groupName>SPI
</groupName>
10990 <baseAddress>0x40013000</baseAddress>
10992 <offset>0x0</offset>
10994 <usage>registers
</usage>
10998 <description>SPI1 global interrupt
</description>
11004 <displayName>CR1
</displayName>
11005 <description>control register
1</description>
11006 <addressOffset>0x0</addressOffset>
11008 <access>read-write
</access>
11009 <resetValue>0x0000</resetValue>
11012 <name>BIDIMODE
</name>
11013 <description>Bidirectional data mode
11014 enable
</description>
11015 <bitOffset>15</bitOffset>
11016 <bitWidth>1</bitWidth>
11019 <name>BIDIOE
</name>
11020 <description>Output enable in bidirectional
11022 <bitOffset>14</bitOffset>
11023 <bitWidth>1</bitWidth>
11027 <description>Hardware CRC calculation
11028 enable
</description>
11029 <bitOffset>13</bitOffset>
11030 <bitWidth>1</bitWidth>
11033 <name>CRCNEXT
</name>
11034 <description>CRC transfer next
</description>
11035 <bitOffset>12</bitOffset>
11036 <bitWidth>1</bitWidth>
11040 <description>CRC length
</description>
11041 <bitOffset>11</bitOffset>
11042 <bitWidth>1</bitWidth>
11045 <name>RXONLY
</name>
11046 <description>Receive only
</description>
11047 <bitOffset>10</bitOffset>
11048 <bitWidth>1</bitWidth>
11052 <description>Software slave management
</description>
11053 <bitOffset>9</bitOffset>
11054 <bitWidth>1</bitWidth>
11058 <description>Internal slave select
</description>
11059 <bitOffset>8</bitOffset>
11060 <bitWidth>1</bitWidth>
11063 <name>LSBFIRST
</name>
11064 <description>Frame format
</description>
11065 <bitOffset>7</bitOffset>
11066 <bitWidth>1</bitWidth>
11070 <description>SPI enable
</description>
11071 <bitOffset>6</bitOffset>
11072 <bitWidth>1</bitWidth>
11076 <description>Baud rate control
</description>
11077 <bitOffset>3</bitOffset>
11078 <bitWidth>3</bitWidth>
11082 <description>Master selection
</description>
11083 <bitOffset>2</bitOffset>
11084 <bitWidth>1</bitWidth>
11088 <description>Clock polarity
</description>
11089 <bitOffset>1</bitOffset>
11090 <bitWidth>1</bitWidth>
11094 <description>Clock phase
</description>
11095 <bitOffset>0</bitOffset>
11096 <bitWidth>1</bitWidth>
11102 <displayName>CR2
</displayName>
11103 <description>control register
2</description>
11104 <addressOffset>0x4</addressOffset>
11106 <access>read-write
</access>
11107 <resetValue>0x0000</resetValue>
11110 <name>RXDMAEN
</name>
11111 <description>Rx buffer DMA enable
</description>
11112 <bitOffset>0</bitOffset>
11113 <bitWidth>1</bitWidth>
11116 <name>TXDMAEN
</name>
11117 <description>Tx buffer DMA enable
</description>
11118 <bitOffset>1</bitOffset>
11119 <bitWidth>1</bitWidth>
11123 <description>SS output enable
</description>
11124 <bitOffset>2</bitOffset>
11125 <bitWidth>1</bitWidth>
11129 <description>NSS pulse management
</description>
11130 <bitOffset>3</bitOffset>
11131 <bitWidth>1</bitWidth>
11135 <description>Frame format
</description>
11136 <bitOffset>4</bitOffset>
11137 <bitWidth>1</bitWidth>
11141 <description>Error interrupt enable
</description>
11142 <bitOffset>5</bitOffset>
11143 <bitWidth>1</bitWidth>
11146 <name>RXNEIE
</name>
11147 <description>RX buffer not empty interrupt
11148 enable
</description>
11149 <bitOffset>6</bitOffset>
11150 <bitWidth>1</bitWidth>
11154 <description>Tx buffer empty interrupt
11155 enable
</description>
11156 <bitOffset>7</bitOffset>
11157 <bitWidth>1</bitWidth>
11161 <description>Data size
</description>
11162 <bitOffset>8</bitOffset>
11163 <bitWidth>4</bitWidth>
11167 <description>FIFO reception threshold
</description>
11168 <bitOffset>12</bitOffset>
11169 <bitWidth>1</bitWidth>
11172 <name>LDMA_RX
</name>
11173 <description>Last DMA transfer for
11174 reception
</description>
11175 <bitOffset>13</bitOffset>
11176 <bitWidth>1</bitWidth>
11179 <name>LDMA_TX
</name>
11180 <description>Last DMA transfer for
11181 transmission
</description>
11182 <bitOffset>14</bitOffset>
11183 <bitWidth>1</bitWidth>
11189 <displayName>SR
</displayName>
11190 <description>status register
</description>
11191 <addressOffset>0x8</addressOffset>
11193 <resetValue>0x0002</resetValue>
11197 <description>Receive buffer not empty
</description>
11198 <bitOffset>0</bitOffset>
11199 <bitWidth>1</bitWidth>
11200 <access>read-only
</access>
11204 <description>Transmit buffer empty
</description>
11205 <bitOffset>1</bitOffset>
11206 <bitWidth>1</bitWidth>
11207 <access>read-only
</access>
11210 <name>CHSIDE
</name>
11211 <description>Channel side
</description>
11212 <bitOffset>2</bitOffset>
11213 <bitWidth>1</bitWidth>
11214 <access>read-only
</access>
11218 <description>Underrun flag
</description>
11219 <bitOffset>3</bitOffset>
11220 <bitWidth>1</bitWidth>
11221 <access>read-only
</access>
11224 <name>CRCERR
</name>
11225 <description>CRC error flag
</description>
11226 <bitOffset>4</bitOffset>
11227 <bitWidth>1</bitWidth>
11228 <access>read-write
</access>
11232 <description>Mode fault
</description>
11233 <bitOffset>5</bitOffset>
11234 <bitWidth>1</bitWidth>
11235 <access>read-only
</access>
11239 <description>Overrun flag
</description>
11240 <bitOffset>6</bitOffset>
11241 <bitWidth>1</bitWidth>
11242 <access>read-only
</access>
11246 <description>Busy flag
</description>
11247 <bitOffset>7</bitOffset>
11248 <bitWidth>1</bitWidth>
11249 <access>read-only
</access>
11252 <name>TIFRFE
</name>
11253 <description>TI frame format error
</description>
11254 <bitOffset>8</bitOffset>
11255 <bitWidth>1</bitWidth>
11256 <access>read-only
</access>
11260 <description>FIFO reception level
</description>
11261 <bitOffset>9</bitOffset>
11262 <bitWidth>2</bitWidth>
11263 <access>read-only
</access>
11267 <description>FIFO transmission level
</description>
11268 <bitOffset>11</bitOffset>
11269 <bitWidth>2</bitWidth>
11270 <access>read-only
</access>
11276 <displayName>DR
</displayName>
11277 <description>data register
</description>
11278 <addressOffset>0xC</addressOffset>
11280 <access>read-write
</access>
11281 <resetValue>0x0000</resetValue>
11285 <description>Data register
</description>
11286 <bitOffset>0</bitOffset>
11287 <bitWidth>16</bitWidth>
11293 <displayName>CRCPR
</displayName>
11294 <description>CRC polynomial register
</description>
11295 <addressOffset>0x10</addressOffset>
11297 <access>read-write
</access>
11298 <resetValue>0x0007</resetValue>
11301 <name>CRCPOLY
</name>
11302 <description>CRC polynomial register
</description>
11303 <bitOffset>0</bitOffset>
11304 <bitWidth>16</bitWidth>
11309 <name>RXCRCR
</name>
11310 <displayName>RXCRCR
</displayName>
11311 <description>RX CRC register
</description>
11312 <addressOffset>0x14</addressOffset>
11314 <access>read-only
</access>
11315 <resetValue>0x0000</resetValue>
11319 <description>Rx CRC register
</description>
11320 <bitOffset>0</bitOffset>
11321 <bitWidth>16</bitWidth>
11326 <name>TXCRCR
</name>
11327 <displayName>TXCRCR
</displayName>
11328 <description>TX CRC register
</description>
11329 <addressOffset>0x18</addressOffset>
11331 <access>read-only
</access>
11332 <resetValue>0x0000</resetValue>
11336 <description>Tx CRC register
</description>
11337 <bitOffset>0</bitOffset>
11338 <bitWidth>16</bitWidth>
11343 <name>I2SCFGR
</name>
11344 <displayName>I2SCFGR
</displayName>
11345 <description>I2S configuration register
</description>
11346 <addressOffset>0x1C</addressOffset>
11348 <access>read-write
</access>
11349 <resetValue>0x0000</resetValue>
11352 <name>I2SMOD
</name>
11353 <description>I2S mode selection
</description>
11354 <bitOffset>11</bitOffset>
11355 <bitWidth>1</bitWidth>
11359 <description>I2S Enable
</description>
11360 <bitOffset>10</bitOffset>
11361 <bitWidth>1</bitWidth>
11364 <name>I2SCFG
</name>
11365 <description>I2S configuration mode
</description>
11366 <bitOffset>8</bitOffset>
11367 <bitWidth>2</bitWidth>
11370 <name>PCMSYNC
</name>
11371 <description>PCM frame synchronization
</description>
11372 <bitOffset>7</bitOffset>
11373 <bitWidth>1</bitWidth>
11376 <name>I2SSTD
</name>
11377 <description>I2S standard selection
</description>
11378 <bitOffset>4</bitOffset>
11379 <bitWidth>2</bitWidth>
11383 <description>Steady state clock
11384 polarity
</description>
11385 <bitOffset>3</bitOffset>
11386 <bitWidth>1</bitWidth>
11389 <name>DATLEN
</name>
11390 <description>Data length to be
11391 transferred
</description>
11392 <bitOffset>1</bitOffset>
11393 <bitWidth>2</bitWidth>
11397 <description>Channel length (number of bits per audio
11398 channel)
</description>
11399 <bitOffset>0</bitOffset>
11400 <bitWidth>1</bitWidth>
11406 <displayName>I2SPR
</displayName>
11407 <description>I2S prescaler register
</description>
11408 <addressOffset>0x20</addressOffset>
11410 <access>read-write
</access>
11411 <resetValue>0x00000010</resetValue>
11415 <description>Master clock output enable
</description>
11416 <bitOffset>9</bitOffset>
11417 <bitWidth>1</bitWidth>
11421 <description>Odd factor for the
11422 prescaler
</description>
11423 <bitOffset>8</bitOffset>
11424 <bitWidth>1</bitWidth>
11427 <name>I2SDIV
</name>
11428 <description>I2S Linear prescaler
</description>
11429 <bitOffset>0</bitOffset>
11430 <bitWidth>8</bitWidth>
11436 <peripheral derivedFrom=
"SPI1">
11438 <baseAddress>0x40003800</baseAddress>
11441 <description>SPI2 global interrupt
</description>
11445 <peripheral derivedFrom=
"SPI1">
11447 <baseAddress>0x40003C00</baseAddress>
11450 <description>SPI3 global interrupt
</description>
11454 <peripheral derivedFrom=
"SPI1">
11455 <name>I2S2ext
</name>
11456 <baseAddress>0x40003400</baseAddress>
11458 <peripheral derivedFrom=
"SPI1">
11459 <name>I2S3ext
</name>
11460 <baseAddress>0x40004000</baseAddress>
11462 <peripheral derivedFrom=
"SPI1">
11464 <baseAddress>0x40013C00</baseAddress>
11467 <description>SPI3 global interrupt
</description>
11472 <description>SPI4 Global interrupt
</description>
11478 <description>External interrupt/event
11479 controller
</description>
11480 <groupName>EXTI
</groupName>
11481 <baseAddress>0x40010400</baseAddress>
11483 <offset>0x0</offset>
11485 <usage>registers
</usage>
11488 <name>TAMP_STAMP
</name>
11489 <description>Tamper and TimeStamp interrupts
</description>
11494 <description>EXTI Line0 interrupt
</description>
11499 <description>EXTI Line3 interrupt
</description>
11503 <name>EXTI2_TSC
</name>
11504 <description>EXTI Line2 and Touch sensing
11505 interrupts
</description>
11510 <description>EXTI Line3 interrupt
</description>
11515 <description>EXTI Line4 interrupt
</description>
11519 <name>EXTI9_5
</name>
11520 <description>EXTI Line5 to Line9 interrupts
</description>
11524 <name>I2C1_EV_EXTI23
</name>
11525 <description>I2C1 event interrupt and EXTI Line23
11526 interrupt
</description>
11530 <name>USART1_EXTI25
</name>
11531 <description>USART1 global interrupt and EXTI Line
25
11532 interrupt
</description>
11536 <name>USART2_EXTI26
</name>
11537 <description>USART2 global interrupt and EXTI Line
26
11538 interrupt
</description>
11542 <name>USART3_EXTI28
</name>
11543 <description>USART3 global interrupt and EXTI Line
28
11544 interrupt
</description>
11548 <name>EXTI15_10
</name>
11549 <description>EXTI Line15 to Line10 interrupts
</description>
11553 <name>UART4_EXTI34
</name>
11554 <description>UART4 global and EXTI Line
34
11555 interrupts
</description>
11559 <name>UART5_EXTI35
</name>
11560 <description>UART5 global and EXTI Line
35
11561 interrupts
</description>
11565 <name>USB_WKUP_EXTI
</name>
11566 <description>USB wakeup from Suspend and EXTI Line
11573 <displayName>IMR1
</displayName>
11574 <description>Interrupt mask register
</description>
11575 <addressOffset>0x0</addressOffset>
11577 <access>read-write
</access>
11578 <resetValue>0x1F800000</resetValue>
11582 <description>Interrupt Mask on line
0</description>
11583 <bitOffset>0</bitOffset>
11584 <bitWidth>1</bitWidth>
11588 <description>Interrupt Mask on line
1</description>
11589 <bitOffset>1</bitOffset>
11590 <bitWidth>1</bitWidth>
11594 <description>Interrupt Mask on line
2</description>
11595 <bitOffset>2</bitOffset>
11596 <bitWidth>1</bitWidth>
11600 <description>Interrupt Mask on line
3</description>
11601 <bitOffset>3</bitOffset>
11602 <bitWidth>1</bitWidth>
11606 <description>Interrupt Mask on line
4</description>
11607 <bitOffset>4</bitOffset>
11608 <bitWidth>1</bitWidth>
11612 <description>Interrupt Mask on line
5</description>
11613 <bitOffset>5</bitOffset>
11614 <bitWidth>1</bitWidth>
11618 <description>Interrupt Mask on line
6</description>
11619 <bitOffset>6</bitOffset>
11620 <bitWidth>1</bitWidth>
11624 <description>Interrupt Mask on line
7</description>
11625 <bitOffset>7</bitOffset>
11626 <bitWidth>1</bitWidth>
11630 <description>Interrupt Mask on line
8</description>
11631 <bitOffset>8</bitOffset>
11632 <bitWidth>1</bitWidth>
11636 <description>Interrupt Mask on line
9</description>
11637 <bitOffset>9</bitOffset>
11638 <bitWidth>1</bitWidth>
11642 <description>Interrupt Mask on line
10</description>
11643 <bitOffset>10</bitOffset>
11644 <bitWidth>1</bitWidth>
11648 <description>Interrupt Mask on line
11</description>
11649 <bitOffset>11</bitOffset>
11650 <bitWidth>1</bitWidth>
11654 <description>Interrupt Mask on line
12</description>
11655 <bitOffset>12</bitOffset>
11656 <bitWidth>1</bitWidth>
11660 <description>Interrupt Mask on line
13</description>
11661 <bitOffset>13</bitOffset>
11662 <bitWidth>1</bitWidth>
11666 <description>Interrupt Mask on line
14</description>
11667 <bitOffset>14</bitOffset>
11668 <bitWidth>1</bitWidth>
11672 <description>Interrupt Mask on line
15</description>
11673 <bitOffset>15</bitOffset>
11674 <bitWidth>1</bitWidth>
11678 <description>Interrupt Mask on line
16</description>
11679 <bitOffset>16</bitOffset>
11680 <bitWidth>1</bitWidth>
11684 <description>Interrupt Mask on line
17</description>
11685 <bitOffset>17</bitOffset>
11686 <bitWidth>1</bitWidth>
11690 <description>Interrupt Mask on line
18</description>
11691 <bitOffset>18</bitOffset>
11692 <bitWidth>1</bitWidth>
11696 <description>Interrupt Mask on line
19</description>
11697 <bitOffset>19</bitOffset>
11698 <bitWidth>1</bitWidth>
11702 <description>Interrupt Mask on line
20</description>
11703 <bitOffset>20</bitOffset>
11704 <bitWidth>1</bitWidth>
11708 <description>Interrupt Mask on line
21</description>
11709 <bitOffset>21</bitOffset>
11710 <bitWidth>1</bitWidth>
11714 <description>Interrupt Mask on line
22</description>
11715 <bitOffset>22</bitOffset>
11716 <bitWidth>1</bitWidth>
11720 <description>Interrupt Mask on line
23</description>
11721 <bitOffset>23</bitOffset>
11722 <bitWidth>1</bitWidth>
11726 <description>Interrupt Mask on line
24</description>
11727 <bitOffset>24</bitOffset>
11728 <bitWidth>1</bitWidth>
11732 <description>Interrupt Mask on line
25</description>
11733 <bitOffset>25</bitOffset>
11734 <bitWidth>1</bitWidth>
11738 <description>Interrupt Mask on line
26</description>
11739 <bitOffset>26</bitOffset>
11740 <bitWidth>1</bitWidth>
11744 <description>Interrupt Mask on line
27</description>
11745 <bitOffset>27</bitOffset>
11746 <bitWidth>1</bitWidth>
11750 <description>Interrupt Mask on line
28</description>
11751 <bitOffset>28</bitOffset>
11752 <bitWidth>1</bitWidth>
11756 <description>Interrupt Mask on line
29</description>
11757 <bitOffset>29</bitOffset>
11758 <bitWidth>1</bitWidth>
11762 <description>Interrupt Mask on line
30</description>
11763 <bitOffset>30</bitOffset>
11764 <bitWidth>1</bitWidth>
11768 <description>Interrupt Mask on line
31</description>
11769 <bitOffset>31</bitOffset>
11770 <bitWidth>1</bitWidth>
11776 <displayName>EMR1
</displayName>
11777 <description>Event mask register
</description>
11778 <addressOffset>0x4</addressOffset>
11780 <access>read-write
</access>
11781 <resetValue>0x00000000</resetValue>
11785 <description>Event Mask on line
0</description>
11786 <bitOffset>0</bitOffset>
11787 <bitWidth>1</bitWidth>
11791 <description>Event Mask on line
1</description>
11792 <bitOffset>1</bitOffset>
11793 <bitWidth>1</bitWidth>
11797 <description>Event Mask on line
2</description>
11798 <bitOffset>2</bitOffset>
11799 <bitWidth>1</bitWidth>
11803 <description>Event Mask on line
3</description>
11804 <bitOffset>3</bitOffset>
11805 <bitWidth>1</bitWidth>
11809 <description>Event Mask on line
4</description>
11810 <bitOffset>4</bitOffset>
11811 <bitWidth>1</bitWidth>
11815 <description>Event Mask on line
5</description>
11816 <bitOffset>5</bitOffset>
11817 <bitWidth>1</bitWidth>
11821 <description>Event Mask on line
6</description>
11822 <bitOffset>6</bitOffset>
11823 <bitWidth>1</bitWidth>
11827 <description>Event Mask on line
7</description>
11828 <bitOffset>7</bitOffset>
11829 <bitWidth>1</bitWidth>
11833 <description>Event Mask on line
8</description>
11834 <bitOffset>8</bitOffset>
11835 <bitWidth>1</bitWidth>
11839 <description>Event Mask on line
9</description>
11840 <bitOffset>9</bitOffset>
11841 <bitWidth>1</bitWidth>
11845 <description>Event Mask on line
10</description>
11846 <bitOffset>10</bitOffset>
11847 <bitWidth>1</bitWidth>
11851 <description>Event Mask on line
11</description>
11852 <bitOffset>11</bitOffset>
11853 <bitWidth>1</bitWidth>
11857 <description>Event Mask on line
12</description>
11858 <bitOffset>12</bitOffset>
11859 <bitWidth>1</bitWidth>
11863 <description>Event Mask on line
13</description>
11864 <bitOffset>13</bitOffset>
11865 <bitWidth>1</bitWidth>
11869 <description>Event Mask on line
14</description>
11870 <bitOffset>14</bitOffset>
11871 <bitWidth>1</bitWidth>
11875 <description>Event Mask on line
15</description>
11876 <bitOffset>15</bitOffset>
11877 <bitWidth>1</bitWidth>
11881 <description>Event Mask on line
16</description>
11882 <bitOffset>16</bitOffset>
11883 <bitWidth>1</bitWidth>
11887 <description>Event Mask on line
17</description>
11888 <bitOffset>17</bitOffset>
11889 <bitWidth>1</bitWidth>
11893 <description>Event Mask on line
18</description>
11894 <bitOffset>18</bitOffset>
11895 <bitWidth>1</bitWidth>
11899 <description>Event Mask on line
19</description>
11900 <bitOffset>19</bitOffset>
11901 <bitWidth>1</bitWidth>
11905 <description>Event Mask on line
20</description>
11906 <bitOffset>20</bitOffset>
11907 <bitWidth>1</bitWidth>
11911 <description>Event Mask on line
21</description>
11912 <bitOffset>21</bitOffset>
11913 <bitWidth>1</bitWidth>
11917 <description>Event Mask on line
22</description>
11918 <bitOffset>22</bitOffset>
11919 <bitWidth>1</bitWidth>
11923 <description>Event Mask on line
23</description>
11924 <bitOffset>23</bitOffset>
11925 <bitWidth>1</bitWidth>
11929 <description>Event Mask on line
24</description>
11930 <bitOffset>24</bitOffset>
11931 <bitWidth>1</bitWidth>
11935 <description>Event Mask on line
25</description>
11936 <bitOffset>25</bitOffset>
11937 <bitWidth>1</bitWidth>
11941 <description>Event Mask on line
26</description>
11942 <bitOffset>26</bitOffset>
11943 <bitWidth>1</bitWidth>
11947 <description>Event Mask on line
27</description>
11948 <bitOffset>27</bitOffset>
11949 <bitWidth>1</bitWidth>
11953 <description>Event Mask on line
28</description>
11954 <bitOffset>28</bitOffset>
11955 <bitWidth>1</bitWidth>
11959 <description>Event Mask on line
29</description>
11960 <bitOffset>29</bitOffset>
11961 <bitWidth>1</bitWidth>
11965 <description>Event Mask on line
30</description>
11966 <bitOffset>30</bitOffset>
11967 <bitWidth>1</bitWidth>
11971 <description>Event Mask on line
31</description>
11972 <bitOffset>31</bitOffset>
11973 <bitWidth>1</bitWidth>
11979 <displayName>RTSR1
</displayName>
11980 <description>Rising Trigger selection
11981 register
</description>
11982 <addressOffset>0x8</addressOffset>
11984 <access>read-write
</access>
11985 <resetValue>0x00000000</resetValue>
11989 <description>Rising trigger event configuration of
11990 line
0</description>
11991 <bitOffset>0</bitOffset>
11992 <bitWidth>1</bitWidth>
11996 <description>Rising trigger event configuration of
11997 line
1</description>
11998 <bitOffset>1</bitOffset>
11999 <bitWidth>1</bitWidth>
12003 <description>Rising trigger event configuration of
12004 line
2</description>
12005 <bitOffset>2</bitOffset>
12006 <bitWidth>1</bitWidth>
12010 <description>Rising trigger event configuration of
12011 line
3</description>
12012 <bitOffset>3</bitOffset>
12013 <bitWidth>1</bitWidth>
12017 <description>Rising trigger event configuration of
12018 line
4</description>
12019 <bitOffset>4</bitOffset>
12020 <bitWidth>1</bitWidth>
12024 <description>Rising trigger event configuration of
12025 line
5</description>
12026 <bitOffset>5</bitOffset>
12027 <bitWidth>1</bitWidth>
12031 <description>Rising trigger event configuration of
12032 line
6</description>
12033 <bitOffset>6</bitOffset>
12034 <bitWidth>1</bitWidth>
12038 <description>Rising trigger event configuration of
12039 line
7</description>
12040 <bitOffset>7</bitOffset>
12041 <bitWidth>1</bitWidth>
12045 <description>Rising trigger event configuration of
12046 line
8</description>
12047 <bitOffset>8</bitOffset>
12048 <bitWidth>1</bitWidth>
12052 <description>Rising trigger event configuration of
12053 line
9</description>
12054 <bitOffset>9</bitOffset>
12055 <bitWidth>1</bitWidth>
12059 <description>Rising trigger event configuration of
12060 line
10</description>
12061 <bitOffset>10</bitOffset>
12062 <bitWidth>1</bitWidth>
12066 <description>Rising trigger event configuration of
12067 line
11</description>
12068 <bitOffset>11</bitOffset>
12069 <bitWidth>1</bitWidth>
12073 <description>Rising trigger event configuration of
12074 line
12</description>
12075 <bitOffset>12</bitOffset>
12076 <bitWidth>1</bitWidth>
12080 <description>Rising trigger event configuration of
12081 line
13</description>
12082 <bitOffset>13</bitOffset>
12083 <bitWidth>1</bitWidth>
12087 <description>Rising trigger event configuration of
12088 line
14</description>
12089 <bitOffset>14</bitOffset>
12090 <bitWidth>1</bitWidth>
12094 <description>Rising trigger event configuration of
12095 line
15</description>
12096 <bitOffset>15</bitOffset>
12097 <bitWidth>1</bitWidth>
12101 <description>Rising trigger event configuration of
12102 line
16</description>
12103 <bitOffset>16</bitOffset>
12104 <bitWidth>1</bitWidth>
12108 <description>Rising trigger event configuration of
12109 line
17</description>
12110 <bitOffset>17</bitOffset>
12111 <bitWidth>1</bitWidth>
12115 <description>Rising trigger event configuration of
12116 line
18</description>
12117 <bitOffset>18</bitOffset>
12118 <bitWidth>1</bitWidth>
12122 <description>Rising trigger event configuration of
12123 line
19</description>
12124 <bitOffset>19</bitOffset>
12125 <bitWidth>1</bitWidth>
12129 <description>Rising trigger event configuration of
12130 line
20</description>
12131 <bitOffset>20</bitOffset>
12132 <bitWidth>1</bitWidth>
12136 <description>Rising trigger event configuration of
12137 line
21</description>
12138 <bitOffset>21</bitOffset>
12139 <bitWidth>1</bitWidth>
12143 <description>Rising trigger event configuration of
12144 line
22</description>
12145 <bitOffset>22</bitOffset>
12146 <bitWidth>1</bitWidth>
12150 <description>Rising trigger event configuration of
12151 line
29</description>
12152 <bitOffset>29</bitOffset>
12153 <bitWidth>1</bitWidth>
12157 <description>Rising trigger event configuration of
12158 line
30</description>
12159 <bitOffset>30</bitOffset>
12160 <bitWidth>1</bitWidth>
12164 <description>Rising trigger event configuration of
12165 line
31</description>
12166 <bitOffset>31</bitOffset>
12167 <bitWidth>1</bitWidth>
12173 <displayName>FTSR1
</displayName>
12174 <description>Falling Trigger selection
12175 register
</description>
12176 <addressOffset>0xC</addressOffset>
12178 <access>read-write
</access>
12179 <resetValue>0x00000000</resetValue>
12183 <description>Falling trigger event configuration of
12184 line
0</description>
12185 <bitOffset>0</bitOffset>
12186 <bitWidth>1</bitWidth>
12190 <description>Falling trigger event configuration of
12191 line
1</description>
12192 <bitOffset>1</bitOffset>
12193 <bitWidth>1</bitWidth>
12197 <description>Falling trigger event configuration of
12198 line
2</description>
12199 <bitOffset>2</bitOffset>
12200 <bitWidth>1</bitWidth>
12204 <description>Falling trigger event configuration of
12205 line
3</description>
12206 <bitOffset>3</bitOffset>
12207 <bitWidth>1</bitWidth>
12211 <description>Falling trigger event configuration of
12212 line
4</description>
12213 <bitOffset>4</bitOffset>
12214 <bitWidth>1</bitWidth>
12218 <description>Falling trigger event configuration of
12219 line
5</description>
12220 <bitOffset>5</bitOffset>
12221 <bitWidth>1</bitWidth>
12225 <description>Falling trigger event configuration of
12226 line
6</description>
12227 <bitOffset>6</bitOffset>
12228 <bitWidth>1</bitWidth>
12232 <description>Falling trigger event configuration of
12233 line
7</description>
12234 <bitOffset>7</bitOffset>
12235 <bitWidth>1</bitWidth>
12239 <description>Falling trigger event configuration of
12240 line
8</description>
12241 <bitOffset>8</bitOffset>
12242 <bitWidth>1</bitWidth>
12246 <description>Falling trigger event configuration of
12247 line
9</description>
12248 <bitOffset>9</bitOffset>
12249 <bitWidth>1</bitWidth>
12253 <description>Falling trigger event configuration of
12254 line
10</description>
12255 <bitOffset>10</bitOffset>
12256 <bitWidth>1</bitWidth>
12260 <description>Falling trigger event configuration of
12261 line
11</description>
12262 <bitOffset>11</bitOffset>
12263 <bitWidth>1</bitWidth>
12267 <description>Falling trigger event configuration of
12268 line
12</description>
12269 <bitOffset>12</bitOffset>
12270 <bitWidth>1</bitWidth>
12274 <description>Falling trigger event configuration of
12275 line
13</description>
12276 <bitOffset>13</bitOffset>
12277 <bitWidth>1</bitWidth>
12281 <description>Falling trigger event configuration of
12282 line
14</description>
12283 <bitOffset>14</bitOffset>
12284 <bitWidth>1</bitWidth>
12288 <description>Falling trigger event configuration of
12289 line
15</description>
12290 <bitOffset>15</bitOffset>
12291 <bitWidth>1</bitWidth>
12295 <description>Falling trigger event configuration of
12296 line
16</description>
12297 <bitOffset>16</bitOffset>
12298 <bitWidth>1</bitWidth>
12302 <description>Falling trigger event configuration of
12303 line
17</description>
12304 <bitOffset>17</bitOffset>
12305 <bitWidth>1</bitWidth>
12309 <description>Falling trigger event configuration of
12310 line
18</description>
12311 <bitOffset>18</bitOffset>
12312 <bitWidth>1</bitWidth>
12316 <description>Falling trigger event configuration of
12317 line
19</description>
12318 <bitOffset>19</bitOffset>
12319 <bitWidth>1</bitWidth>
12323 <description>Falling trigger event configuration of
12324 line
20</description>
12325 <bitOffset>20</bitOffset>
12326 <bitWidth>1</bitWidth>
12330 <description>Falling trigger event configuration of
12331 line
21</description>
12332 <bitOffset>21</bitOffset>
12333 <bitWidth>1</bitWidth>
12337 <description>Falling trigger event configuration of
12338 line
22</description>
12339 <bitOffset>22</bitOffset>
12340 <bitWidth>1</bitWidth>
12344 <description>Falling trigger event configuration of
12345 line
29</description>
12346 <bitOffset>29</bitOffset>
12347 <bitWidth>1</bitWidth>
12351 <description>Falling trigger event configuration of
12352 line
30.
</description>
12353 <bitOffset>30</bitOffset>
12354 <bitWidth>1</bitWidth>
12358 <description>Falling trigger event configuration of
12359 line
31</description>
12360 <bitOffset>31</bitOffset>
12361 <bitWidth>1</bitWidth>
12366 <name>SWIER1
</name>
12367 <displayName>SWIER1
</displayName>
12368 <description>Software interrupt event
12369 register
</description>
12370 <addressOffset>0x10</addressOffset>
12372 <access>read-write
</access>
12373 <resetValue>0x00000000</resetValue>
12376 <name>SWIER0
</name>
12377 <description>Software Interrupt on line
12379 <bitOffset>0</bitOffset>
12380 <bitWidth>1</bitWidth>
12383 <name>SWIER1
</name>
12384 <description>Software Interrupt on line
12386 <bitOffset>1</bitOffset>
12387 <bitWidth>1</bitWidth>
12390 <name>SWIER2
</name>
12391 <description>Software Interrupt on line
12393 <bitOffset>2</bitOffset>
12394 <bitWidth>1</bitWidth>
12397 <name>SWIER3
</name>
12398 <description>Software Interrupt on line
12400 <bitOffset>3</bitOffset>
12401 <bitWidth>1</bitWidth>
12404 <name>SWIER4
</name>
12405 <description>Software Interrupt on line
12407 <bitOffset>4</bitOffset>
12408 <bitWidth>1</bitWidth>
12411 <name>SWIER5
</name>
12412 <description>Software Interrupt on line
12414 <bitOffset>5</bitOffset>
12415 <bitWidth>1</bitWidth>
12418 <name>SWIER6
</name>
12419 <description>Software Interrupt on line
12421 <bitOffset>6</bitOffset>
12422 <bitWidth>1</bitWidth>
12425 <name>SWIER7
</name>
12426 <description>Software Interrupt on line
12428 <bitOffset>7</bitOffset>
12429 <bitWidth>1</bitWidth>
12432 <name>SWIER8
</name>
12433 <description>Software Interrupt on line
12435 <bitOffset>8</bitOffset>
12436 <bitWidth>1</bitWidth>
12439 <name>SWIER9
</name>
12440 <description>Software Interrupt on line
12442 <bitOffset>9</bitOffset>
12443 <bitWidth>1</bitWidth>
12446 <name>SWIER10
</name>
12447 <description>Software Interrupt on line
12449 <bitOffset>10</bitOffset>
12450 <bitWidth>1</bitWidth>
12453 <name>SWIER11
</name>
12454 <description>Software Interrupt on line
12456 <bitOffset>11</bitOffset>
12457 <bitWidth>1</bitWidth>
12460 <name>SWIER12
</name>
12461 <description>Software Interrupt on line
12463 <bitOffset>12</bitOffset>
12464 <bitWidth>1</bitWidth>
12467 <name>SWIER13
</name>
12468 <description>Software Interrupt on line
12470 <bitOffset>13</bitOffset>
12471 <bitWidth>1</bitWidth>
12474 <name>SWIER14
</name>
12475 <description>Software Interrupt on line
12477 <bitOffset>14</bitOffset>
12478 <bitWidth>1</bitWidth>
12481 <name>SWIER15
</name>
12482 <description>Software Interrupt on line
12484 <bitOffset>15</bitOffset>
12485 <bitWidth>1</bitWidth>
12488 <name>SWIER16
</name>
12489 <description>Software Interrupt on line
12491 <bitOffset>16</bitOffset>
12492 <bitWidth>1</bitWidth>
12495 <name>SWIER17
</name>
12496 <description>Software Interrupt on line
12498 <bitOffset>17</bitOffset>
12499 <bitWidth>1</bitWidth>
12502 <name>SWIER18
</name>
12503 <description>Software Interrupt on line
12505 <bitOffset>18</bitOffset>
12506 <bitWidth>1</bitWidth>
12509 <name>SWIER19
</name>
12510 <description>Software Interrupt on line
12512 <bitOffset>19</bitOffset>
12513 <bitWidth>1</bitWidth>
12516 <name>SWIER20
</name>
12517 <description>Software Interrupt on line
12519 <bitOffset>20</bitOffset>
12520 <bitWidth>1</bitWidth>
12523 <name>SWIER21
</name>
12524 <description>Software Interrupt on line
12526 <bitOffset>21</bitOffset>
12527 <bitWidth>1</bitWidth>
12530 <name>SWIER22
</name>
12531 <description>Software Interrupt on line
12533 <bitOffset>22</bitOffset>
12534 <bitWidth>1</bitWidth>
12537 <name>SWIER29
</name>
12538 <description>Software Interrupt on line
12540 <bitOffset>29</bitOffset>
12541 <bitWidth>1</bitWidth>
12544 <name>SWIER30
</name>
12545 <description>Software Interrupt on line
12547 <bitOffset>30</bitOffset>
12548 <bitWidth>1</bitWidth>
12551 <name>SWIER31
</name>
12552 <description>Software Interrupt on line
12554 <bitOffset>31</bitOffset>
12555 <bitWidth>1</bitWidth>
12561 <displayName>PR1
</displayName>
12562 <description>Pending register
</description>
12563 <addressOffset>0x14</addressOffset>
12565 <access>read-write
</access>
12566 <resetValue>0x00000000</resetValue>
12570 <description>Pending bit
0</description>
12571 <bitOffset>0</bitOffset>
12572 <bitWidth>1</bitWidth>
12576 <description>Pending bit
1</description>
12577 <bitOffset>1</bitOffset>
12578 <bitWidth>1</bitWidth>
12582 <description>Pending bit
2</description>
12583 <bitOffset>2</bitOffset>
12584 <bitWidth>1</bitWidth>
12588 <description>Pending bit
3</description>
12589 <bitOffset>3</bitOffset>
12590 <bitWidth>1</bitWidth>
12594 <description>Pending bit
4</description>
12595 <bitOffset>4</bitOffset>
12596 <bitWidth>1</bitWidth>
12600 <description>Pending bit
5</description>
12601 <bitOffset>5</bitOffset>
12602 <bitWidth>1</bitWidth>
12606 <description>Pending bit
6</description>
12607 <bitOffset>6</bitOffset>
12608 <bitWidth>1</bitWidth>
12612 <description>Pending bit
7</description>
12613 <bitOffset>7</bitOffset>
12614 <bitWidth>1</bitWidth>
12618 <description>Pending bit
8</description>
12619 <bitOffset>8</bitOffset>
12620 <bitWidth>1</bitWidth>
12624 <description>Pending bit
9</description>
12625 <bitOffset>9</bitOffset>
12626 <bitWidth>1</bitWidth>
12630 <description>Pending bit
10</description>
12631 <bitOffset>10</bitOffset>
12632 <bitWidth>1</bitWidth>
12636 <description>Pending bit
11</description>
12637 <bitOffset>11</bitOffset>
12638 <bitWidth>1</bitWidth>
12642 <description>Pending bit
12</description>
12643 <bitOffset>12</bitOffset>
12644 <bitWidth>1</bitWidth>
12648 <description>Pending bit
13</description>
12649 <bitOffset>13</bitOffset>
12650 <bitWidth>1</bitWidth>
12654 <description>Pending bit
14</description>
12655 <bitOffset>14</bitOffset>
12656 <bitWidth>1</bitWidth>
12660 <description>Pending bit
15</description>
12661 <bitOffset>15</bitOffset>
12662 <bitWidth>1</bitWidth>
12666 <description>Pending bit
16</description>
12667 <bitOffset>16</bitOffset>
12668 <bitWidth>1</bitWidth>
12672 <description>Pending bit
17</description>
12673 <bitOffset>17</bitOffset>
12674 <bitWidth>1</bitWidth>
12678 <description>Pending bit
18</description>
12679 <bitOffset>18</bitOffset>
12680 <bitWidth>1</bitWidth>
12684 <description>Pending bit
19</description>
12685 <bitOffset>19</bitOffset>
12686 <bitWidth>1</bitWidth>
12690 <description>Pending bit
20</description>
12691 <bitOffset>20</bitOffset>
12692 <bitWidth>1</bitWidth>
12696 <description>Pending bit
21</description>
12697 <bitOffset>21</bitOffset>
12698 <bitWidth>1</bitWidth>
12702 <description>Pending bit
22</description>
12703 <bitOffset>22</bitOffset>
12704 <bitWidth>1</bitWidth>
12708 <description>Pending bit
29</description>
12709 <bitOffset>29</bitOffset>
12710 <bitWidth>1</bitWidth>
12714 <description>Pending bit
30</description>
12715 <bitOffset>30</bitOffset>
12716 <bitWidth>1</bitWidth>
12720 <description>Pending bit
31</description>
12721 <bitOffset>31</bitOffset>
12722 <bitWidth>1</bitWidth>
12728 <displayName>IMR2
</displayName>
12729 <description>Interrupt mask register
</description>
12730 <addressOffset>0x18</addressOffset>
12732 <access>read-write
</access>
12733 <resetValue>0xFFFFFFFC</resetValue>
12737 <description>Interrupt Mask on external/internal line
12739 <bitOffset>0</bitOffset>
12740 <bitWidth>1</bitWidth>
12744 <description>Interrupt Mask on external/internal line
12746 <bitOffset>1</bitOffset>
12747 <bitWidth>1</bitWidth>
12751 <description>Interrupt Mask on external/internal line
12753 <bitOffset>2</bitOffset>
12754 <bitWidth>1</bitWidth>
12758 <description>Interrupt Mask on external/internal line
12760 <bitOffset>3</bitOffset>
12761 <bitWidth>1</bitWidth>
12767 <displayName>EMR2
</displayName>
12768 <description>Event mask register
</description>
12769 <addressOffset>0x1C</addressOffset>
12771 <access>read-write
</access>
12772 <resetValue>0x00000000</resetValue>
12776 <description>Event mask on external/internal line
12778 <bitOffset>0</bitOffset>
12779 <bitWidth>1</bitWidth>
12783 <description>Event mask on external/internal line
12785 <bitOffset>1</bitOffset>
12786 <bitWidth>1</bitWidth>
12790 <description>Event mask on external/internal line
12792 <bitOffset>2</bitOffset>
12793 <bitWidth>1</bitWidth>
12797 <description>Event mask on external/internal line
12799 <bitOffset>3</bitOffset>
12800 <bitWidth>1</bitWidth>
12806 <displayName>RTSR2
</displayName>
12807 <description>Rising Trigger selection
12808 register
</description>
12809 <addressOffset>0x20</addressOffset>
12811 <access>read-write
</access>
12812 <resetValue>0x00000000</resetValue>
12816 <description>Rising trigger event configuration bit
12817 of line
32</description>
12818 <bitOffset>0</bitOffset>
12819 <bitWidth>1</bitWidth>
12823 <description>Rising trigger event configuration bit
12824 of line
33</description>
12825 <bitOffset>1</bitOffset>
12826 <bitWidth>1</bitWidth>
12832 <displayName>FTSR2
</displayName>
12833 <description>Falling Trigger selection
12834 register
</description>
12835 <addressOffset>0x24</addressOffset>
12837 <access>read-write
</access>
12838 <resetValue>0x00000000</resetValue>
12842 <description>Falling trigger event configuration bit
12843 of line
32</description>
12844 <bitOffset>0</bitOffset>
12845 <bitWidth>1</bitWidth>
12849 <description>Falling trigger event configuration bit
12850 of line
33</description>
12851 <bitOffset>1</bitOffset>
12852 <bitWidth>1</bitWidth>
12857 <name>SWIER2
</name>
12858 <displayName>SWIER2
</displayName>
12859 <description>Software interrupt event
12860 register
</description>
12861 <addressOffset>0x28</addressOffset>
12863 <access>read-write
</access>
12864 <resetValue>0x00000000</resetValue>
12867 <name>SWIER32
</name>
12868 <description>Software interrupt on line
12870 <bitOffset>0</bitOffset>
12871 <bitWidth>1</bitWidth>
12874 <name>SWIER33
</name>
12875 <description>Software interrupt on line
12877 <bitOffset>1</bitOffset>
12878 <bitWidth>1</bitWidth>
12884 <displayName>PR2
</displayName>
12885 <description>Pending register
</description>
12886 <addressOffset>0x2C</addressOffset>
12888 <access>read-write
</access>
12889 <resetValue>0x00000000</resetValue>
12893 <description>Pending bit on line
32</description>
12894 <bitOffset>0</bitOffset>
12895 <bitWidth>1</bitWidth>
12899 <description>Pending bit on line
33</description>
12900 <bitOffset>1</bitOffset>
12901 <bitWidth>1</bitWidth>
12909 <description>Power control
</description>
12910 <groupName>PWR
</groupName>
12911 <baseAddress>0x40007000</baseAddress>
12913 <offset>0x0</offset>
12915 <usage>registers
</usage>
12919 <description>PVD through EXTI line detection
12920 interrupt
</description>
12926 <displayName>CR
</displayName>
12927 <description>power control register
</description>
12928 <addressOffset>0x0</addressOffset>
12930 <access>read-write
</access>
12931 <resetValue>0x00000000</resetValue>
12935 <description>Low-power deep sleep
</description>
12936 <bitOffset>0</bitOffset>
12937 <bitWidth>1</bitWidth>
12941 <description>Power down deepsleep
</description>
12942 <bitOffset>1</bitOffset>
12943 <bitWidth>1</bitWidth>
12947 <description>Clear wakeup flag
</description>
12948 <bitOffset>2</bitOffset>
12949 <bitWidth>1</bitWidth>
12953 <description>Clear standby flag
</description>
12954 <bitOffset>3</bitOffset>
12955 <bitWidth>1</bitWidth>
12959 <description>Power voltage detector
12960 enable
</description>
12961 <bitOffset>4</bitOffset>
12962 <bitWidth>1</bitWidth>
12966 <description>PVD level selection
</description>
12967 <bitOffset>5</bitOffset>
12968 <bitWidth>3</bitWidth>
12972 <description>Disable backup domain write
12973 protection
</description>
12974 <bitOffset>8</bitOffset>
12975 <bitWidth>1</bitWidth>
12981 <displayName>CSR
</displayName>
12982 <description>power control/status register
</description>
12983 <addressOffset>0x4</addressOffset>
12985 <resetValue>0x00000000</resetValue>
12989 <description>Wakeup flag
</description>
12990 <bitOffset>0</bitOffset>
12991 <bitWidth>1</bitWidth>
12992 <access>read-only
</access>
12996 <description>Standby flag
</description>
12997 <bitOffset>1</bitOffset>
12998 <bitWidth>1</bitWidth>
12999 <access>read-only
</access>
13003 <description>PVD output
</description>
13004 <bitOffset>2</bitOffset>
13005 <bitWidth>1</bitWidth>
13006 <access>read-only
</access>
13010 <description>Enable WKUP1 pin
</description>
13011 <bitOffset>8</bitOffset>
13012 <bitWidth>1</bitWidth>
13013 <access>read-write
</access>
13017 <description>Enable WKUP2 pin
</description>
13018 <bitOffset>9</bitOffset>
13019 <bitWidth>1</bitWidth>
13020 <access>read-write
</access>
13028 <description>Controller area network
</description>
13029 <groupName>CAN
</groupName>
13030 <baseAddress>0x40006400</baseAddress>
13032 <offset>0x0</offset>
13034 <usage>registers
</usage>
13037 <name>USB_HP_CAN_TX
</name>
13038 <description>USB High Priority/CAN_TX
13039 interrupts
</description>
13043 <name>USB_LP_CAN_RX0
</name>
13044 <description>USB Low Priority/CAN_RX0
13045 interrupts
</description>
13049 <name>CAN_RX1
</name>
13050 <description>CAN_RX1 interrupt
</description>
13054 <name>CAN_SCE
</name>
13055 <description>CAN_SCE interrupt
</description>
13061 <displayName>MCR
</displayName>
13062 <description>master control register
</description>
13063 <addressOffset>0x0</addressOffset>
13065 <access>read-write
</access>
13066 <resetValue>0x00010002</resetValue>
13070 <description>DBF
</description>
13071 <bitOffset>16</bitOffset>
13072 <bitWidth>1</bitWidth>
13076 <description>RESET
</description>
13077 <bitOffset>15</bitOffset>
13078 <bitWidth>1</bitWidth>
13082 <description>TTCM
</description>
13083 <bitOffset>7</bitOffset>
13084 <bitWidth>1</bitWidth>
13088 <description>ABOM
</description>
13089 <bitOffset>6</bitOffset>
13090 <bitWidth>1</bitWidth>
13094 <description>AWUM
</description>
13095 <bitOffset>5</bitOffset>
13096 <bitWidth>1</bitWidth>
13100 <description>NART
</description>
13101 <bitOffset>4</bitOffset>
13102 <bitWidth>1</bitWidth>
13106 <description>RFLM
</description>
13107 <bitOffset>3</bitOffset>
13108 <bitWidth>1</bitWidth>
13112 <description>TXFP
</description>
13113 <bitOffset>2</bitOffset>
13114 <bitWidth>1</bitWidth>
13118 <description>SLEEP
</description>
13119 <bitOffset>1</bitOffset>
13120 <bitWidth>1</bitWidth>
13124 <description>INRQ
</description>
13125 <bitOffset>0</bitOffset>
13126 <bitWidth>1</bitWidth>
13132 <displayName>MSR
</displayName>
13133 <description>master status register
</description>
13134 <addressOffset>0x4</addressOffset>
13136 <resetValue>0x00000C02</resetValue>
13140 <description>RX
</description>
13141 <bitOffset>11</bitOffset>
13142 <bitWidth>1</bitWidth>
13143 <access>read-only
</access>
13147 <description>SAMP
</description>
13148 <bitOffset>10</bitOffset>
13149 <bitWidth>1</bitWidth>
13150 <access>read-only
</access>
13154 <description>RXM
</description>
13155 <bitOffset>9</bitOffset>
13156 <bitWidth>1</bitWidth>
13157 <access>read-only
</access>
13161 <description>TXM
</description>
13162 <bitOffset>8</bitOffset>
13163 <bitWidth>1</bitWidth>
13164 <access>read-only
</access>
13168 <description>SLAKI
</description>
13169 <bitOffset>4</bitOffset>
13170 <bitWidth>1</bitWidth>
13171 <access>read-write
</access>
13175 <description>WKUI
</description>
13176 <bitOffset>3</bitOffset>
13177 <bitWidth>1</bitWidth>
13178 <access>read-write
</access>
13182 <description>ERRI
</description>
13183 <bitOffset>2</bitOffset>
13184 <bitWidth>1</bitWidth>
13185 <access>read-write
</access>
13189 <description>SLAK
</description>
13190 <bitOffset>1</bitOffset>
13191 <bitWidth>1</bitWidth>
13192 <access>read-only
</access>
13196 <description>INAK
</description>
13197 <bitOffset>0</bitOffset>
13198 <bitWidth>1</bitWidth>
13199 <access>read-only
</access>
13205 <displayName>TSR
</displayName>
13206 <description>transmit status register
</description>
13207 <addressOffset>0x8</addressOffset>
13209 <resetValue>0x1C000000</resetValue>
13213 <description>Lowest priority flag for mailbox
13215 <bitOffset>31</bitOffset>
13216 <bitWidth>1</bitWidth>
13217 <access>read-only
</access>
13221 <description>Lowest priority flag for mailbox
13223 <bitOffset>30</bitOffset>
13224 <bitWidth>1</bitWidth>
13225 <access>read-only
</access>
13229 <description>Lowest priority flag for mailbox
13231 <bitOffset>29</bitOffset>
13232 <bitWidth>1</bitWidth>
13233 <access>read-only
</access>
13237 <description>Lowest priority flag for mailbox
13239 <bitOffset>28</bitOffset>
13240 <bitWidth>1</bitWidth>
13241 <access>read-only
</access>
13245 <description>Lowest priority flag for mailbox
13247 <bitOffset>27</bitOffset>
13248 <bitWidth>1</bitWidth>
13249 <access>read-only
</access>
13253 <description>Lowest priority flag for mailbox
13255 <bitOffset>26</bitOffset>
13256 <bitWidth>1</bitWidth>
13257 <access>read-only
</access>
13261 <description>CODE
</description>
13262 <bitOffset>24</bitOffset>
13263 <bitWidth>2</bitWidth>
13264 <access>read-only
</access>
13268 <description>ABRQ2
</description>
13269 <bitOffset>23</bitOffset>
13270 <bitWidth>1</bitWidth>
13271 <access>read-write
</access>
13275 <description>TERR2
</description>
13276 <bitOffset>19</bitOffset>
13277 <bitWidth>1</bitWidth>
13278 <access>read-write
</access>
13282 <description>ALST2
</description>
13283 <bitOffset>18</bitOffset>
13284 <bitWidth>1</bitWidth>
13285 <access>read-write
</access>
13289 <description>TXOK2
</description>
13290 <bitOffset>17</bitOffset>
13291 <bitWidth>1</bitWidth>
13292 <access>read-write
</access>
13296 <description>RQCP2
</description>
13297 <bitOffset>16</bitOffset>
13298 <bitWidth>1</bitWidth>
13299 <access>read-write
</access>
13303 <description>ABRQ1
</description>
13304 <bitOffset>15</bitOffset>
13305 <bitWidth>1</bitWidth>
13306 <access>read-write
</access>
13310 <description>TERR1
</description>
13311 <bitOffset>11</bitOffset>
13312 <bitWidth>1</bitWidth>
13313 <access>read-write
</access>
13317 <description>ALST1
</description>
13318 <bitOffset>10</bitOffset>
13319 <bitWidth>1</bitWidth>
13320 <access>read-write
</access>
13324 <description>TXOK1
</description>
13325 <bitOffset>9</bitOffset>
13326 <bitWidth>1</bitWidth>
13327 <access>read-write
</access>
13331 <description>RQCP1
</description>
13332 <bitOffset>8</bitOffset>
13333 <bitWidth>1</bitWidth>
13334 <access>read-write
</access>
13338 <description>ABRQ0
</description>
13339 <bitOffset>7</bitOffset>
13340 <bitWidth>1</bitWidth>
13341 <access>read-write
</access>
13345 <description>TERR0
</description>
13346 <bitOffset>3</bitOffset>
13347 <bitWidth>1</bitWidth>
13348 <access>read-write
</access>
13352 <description>ALST0
</description>
13353 <bitOffset>2</bitOffset>
13354 <bitWidth>1</bitWidth>
13355 <access>read-write
</access>
13359 <description>TXOK0
</description>
13360 <bitOffset>1</bitOffset>
13361 <bitWidth>1</bitWidth>
13362 <access>read-write
</access>
13366 <description>RQCP0
</description>
13367 <bitOffset>0</bitOffset>
13368 <bitWidth>1</bitWidth>
13369 <access>read-write
</access>
13375 <displayName>RF0R
</displayName>
13376 <description>receive FIFO
0 register
</description>
13377 <addressOffset>0xC</addressOffset>
13379 <resetValue>0x00000000</resetValue>
13383 <description>RFOM0
</description>
13384 <bitOffset>5</bitOffset>
13385 <bitWidth>1</bitWidth>
13386 <access>read-write
</access>
13390 <description>FOVR0
</description>
13391 <bitOffset>4</bitOffset>
13392 <bitWidth>1</bitWidth>
13393 <access>read-write
</access>
13397 <description>FULL0
</description>
13398 <bitOffset>3</bitOffset>
13399 <bitWidth>1</bitWidth>
13400 <access>read-write
</access>
13404 <description>FMP0
</description>
13405 <bitOffset>0</bitOffset>
13406 <bitWidth>2</bitWidth>
13407 <access>read-only
</access>
13413 <displayName>RF1R
</displayName>
13414 <description>receive FIFO
1 register
</description>
13415 <addressOffset>0x10</addressOffset>
13417 <resetValue>0x00000000</resetValue>
13421 <description>RFOM1
</description>
13422 <bitOffset>5</bitOffset>
13423 <bitWidth>1</bitWidth>
13424 <access>read-write
</access>
13428 <description>FOVR1
</description>
13429 <bitOffset>4</bitOffset>
13430 <bitWidth>1</bitWidth>
13431 <access>read-write
</access>
13435 <description>FULL1
</description>
13436 <bitOffset>3</bitOffset>
13437 <bitWidth>1</bitWidth>
13438 <access>read-write
</access>
13442 <description>FMP1
</description>
13443 <bitOffset>0</bitOffset>
13444 <bitWidth>2</bitWidth>
13445 <access>read-only
</access>
13451 <displayName>IER
</displayName>
13452 <description>interrupt enable register
</description>
13453 <addressOffset>0x14</addressOffset>
13455 <access>read-write
</access>
13456 <resetValue>0x00000000</resetValue>
13460 <description>SLKIE
</description>
13461 <bitOffset>17</bitOffset>
13462 <bitWidth>1</bitWidth>
13466 <description>WKUIE
</description>
13467 <bitOffset>16</bitOffset>
13468 <bitWidth>1</bitWidth>
13472 <description>ERRIE
</description>
13473 <bitOffset>15</bitOffset>
13474 <bitWidth>1</bitWidth>
13478 <description>LECIE
</description>
13479 <bitOffset>11</bitOffset>
13480 <bitWidth>1</bitWidth>
13484 <description>BOFIE
</description>
13485 <bitOffset>10</bitOffset>
13486 <bitWidth>1</bitWidth>
13490 <description>EPVIE
</description>
13491 <bitOffset>9</bitOffset>
13492 <bitWidth>1</bitWidth>
13496 <description>EWGIE
</description>
13497 <bitOffset>8</bitOffset>
13498 <bitWidth>1</bitWidth>
13501 <name>FOVIE1
</name>
13502 <description>FOVIE1
</description>
13503 <bitOffset>6</bitOffset>
13504 <bitWidth>1</bitWidth>
13508 <description>FFIE1
</description>
13509 <bitOffset>5</bitOffset>
13510 <bitWidth>1</bitWidth>
13513 <name>FMPIE1
</name>
13514 <description>FMPIE1
</description>
13515 <bitOffset>4</bitOffset>
13516 <bitWidth>1</bitWidth>
13519 <name>FOVIE0
</name>
13520 <description>FOVIE0
</description>
13521 <bitOffset>3</bitOffset>
13522 <bitWidth>1</bitWidth>
13526 <description>FFIE0
</description>
13527 <bitOffset>2</bitOffset>
13528 <bitWidth>1</bitWidth>
13531 <name>FMPIE0
</name>
13532 <description>FMPIE0
</description>
13533 <bitOffset>1</bitOffset>
13534 <bitWidth>1</bitWidth>
13538 <description>TMEIE
</description>
13539 <bitOffset>0</bitOffset>
13540 <bitWidth>1</bitWidth>
13546 <displayName>ESR
</displayName>
13547 <description>error status register
</description>
13548 <addressOffset>0x18</addressOffset>
13550 <resetValue>0x00000000</resetValue>
13554 <description>REC
</description>
13555 <bitOffset>24</bitOffset>
13556 <bitWidth>8</bitWidth>
13557 <access>read-only
</access>
13561 <description>TEC
</description>
13562 <bitOffset>16</bitOffset>
13563 <bitWidth>8</bitWidth>
13564 <access>read-only
</access>
13568 <description>LEC
</description>
13569 <bitOffset>4</bitOffset>
13570 <bitWidth>3</bitWidth>
13571 <access>read-write
</access>
13575 <description>BOFF
</description>
13576 <bitOffset>2</bitOffset>
13577 <bitWidth>1</bitWidth>
13578 <access>read-only
</access>
13582 <description>EPVF
</description>
13583 <bitOffset>1</bitOffset>
13584 <bitWidth>1</bitWidth>
13585 <access>read-only
</access>
13589 <description>EWGF
</description>
13590 <bitOffset>0</bitOffset>
13591 <bitWidth>1</bitWidth>
13592 <access>read-only
</access>
13598 <displayName>BTR
</displayName>
13599 <description>bit timing register
</description>
13600 <addressOffset>0x1C</addressOffset>
13602 <access>read-write
</access>
13603 <resetValue>0x01230000</resetValue>
13607 <description>SILM
</description>
13608 <bitOffset>31</bitOffset>
13609 <bitWidth>1</bitWidth>
13613 <description>LBKM
</description>
13614 <bitOffset>30</bitOffset>
13615 <bitWidth>1</bitWidth>
13619 <description>SJW
</description>
13620 <bitOffset>24</bitOffset>
13621 <bitWidth>2</bitWidth>
13625 <description>TS2
</description>
13626 <bitOffset>20</bitOffset>
13627 <bitWidth>3</bitWidth>
13631 <description>TS1
</description>
13632 <bitOffset>16</bitOffset>
13633 <bitWidth>4</bitWidth>
13637 <description>BRP
</description>
13638 <bitOffset>0</bitOffset>
13639 <bitWidth>10</bitWidth>
13645 <displayName>TI0R
</displayName>
13646 <description>TX mailbox identifier register
</description>
13647 <addressOffset>0x180</addressOffset>
13649 <access>read-write
</access>
13650 <resetValue>0x00000000</resetValue>
13654 <description>STID
</description>
13655 <bitOffset>21</bitOffset>
13656 <bitWidth>11</bitWidth>
13660 <description>EXID
</description>
13661 <bitOffset>3</bitOffset>
13662 <bitWidth>18</bitWidth>
13666 <description>IDE
</description>
13667 <bitOffset>2</bitOffset>
13668 <bitWidth>1</bitWidth>
13672 <description>RTR
</description>
13673 <bitOffset>1</bitOffset>
13674 <bitWidth>1</bitWidth>
13678 <description>TXRQ
</description>
13679 <bitOffset>0</bitOffset>
13680 <bitWidth>1</bitWidth>
13686 <displayName>TDT0R
</displayName>
13687 <description>mailbox data length control and time stamp
13688 register
</description>
13689 <addressOffset>0x184</addressOffset>
13691 <access>read-write
</access>
13692 <resetValue>0x00000000</resetValue>
13696 <description>TIME
</description>
13697 <bitOffset>16</bitOffset>
13698 <bitWidth>16</bitWidth>
13702 <description>TGT
</description>
13703 <bitOffset>8</bitOffset>
13704 <bitWidth>1</bitWidth>
13708 <description>DLC
</description>
13709 <bitOffset>0</bitOffset>
13710 <bitWidth>4</bitWidth>
13716 <displayName>TDL0R
</displayName>
13717 <description>mailbox data low register
</description>
13718 <addressOffset>0x188</addressOffset>
13720 <access>read-write
</access>
13721 <resetValue>0x00000000</resetValue>
13725 <description>DATA3
</description>
13726 <bitOffset>24</bitOffset>
13727 <bitWidth>8</bitWidth>
13731 <description>DATA2
</description>
13732 <bitOffset>16</bitOffset>
13733 <bitWidth>8</bitWidth>
13737 <description>DATA1
</description>
13738 <bitOffset>8</bitOffset>
13739 <bitWidth>8</bitWidth>
13743 <description>DATA0
</description>
13744 <bitOffset>0</bitOffset>
13745 <bitWidth>8</bitWidth>
13751 <displayName>TDH0R
</displayName>
13752 <description>mailbox data high register
</description>
13753 <addressOffset>0x18C</addressOffset>
13755 <access>read-write
</access>
13756 <resetValue>0x00000000</resetValue>
13760 <description>DATA7
</description>
13761 <bitOffset>24</bitOffset>
13762 <bitWidth>8</bitWidth>
13766 <description>DATA6
</description>
13767 <bitOffset>16</bitOffset>
13768 <bitWidth>8</bitWidth>
13772 <description>DATA5
</description>
13773 <bitOffset>8</bitOffset>
13774 <bitWidth>8</bitWidth>
13778 <description>DATA4
</description>
13779 <bitOffset>0</bitOffset>
13780 <bitWidth>8</bitWidth>
13786 <displayName>TI1R
</displayName>
13787 <description>TX mailbox identifier register
</description>
13788 <addressOffset>0x190</addressOffset>
13790 <access>read-write
</access>
13791 <resetValue>0x00000000</resetValue>
13795 <description>STID
</description>
13796 <bitOffset>21</bitOffset>
13797 <bitWidth>11</bitWidth>
13801 <description>EXID
</description>
13802 <bitOffset>3</bitOffset>
13803 <bitWidth>18</bitWidth>
13807 <description>IDE
</description>
13808 <bitOffset>2</bitOffset>
13809 <bitWidth>1</bitWidth>
13813 <description>RTR
</description>
13814 <bitOffset>1</bitOffset>
13815 <bitWidth>1</bitWidth>
13819 <description>TXRQ
</description>
13820 <bitOffset>0</bitOffset>
13821 <bitWidth>1</bitWidth>
13827 <displayName>TDT1R
</displayName>
13828 <description>mailbox data length control and time stamp
13829 register
</description>
13830 <addressOffset>0x194</addressOffset>
13832 <access>read-write
</access>
13833 <resetValue>0x00000000</resetValue>
13837 <description>TIME
</description>
13838 <bitOffset>16</bitOffset>
13839 <bitWidth>16</bitWidth>
13843 <description>TGT
</description>
13844 <bitOffset>8</bitOffset>
13845 <bitWidth>1</bitWidth>
13849 <description>DLC
</description>
13850 <bitOffset>0</bitOffset>
13851 <bitWidth>4</bitWidth>
13857 <displayName>TDL1R
</displayName>
13858 <description>mailbox data low register
</description>
13859 <addressOffset>0x198</addressOffset>
13861 <access>read-write
</access>
13862 <resetValue>0x00000000</resetValue>
13866 <description>DATA3
</description>
13867 <bitOffset>24</bitOffset>
13868 <bitWidth>8</bitWidth>
13872 <description>DATA2
</description>
13873 <bitOffset>16</bitOffset>
13874 <bitWidth>8</bitWidth>
13878 <description>DATA1
</description>
13879 <bitOffset>8</bitOffset>
13880 <bitWidth>8</bitWidth>
13884 <description>DATA0
</description>
13885 <bitOffset>0</bitOffset>
13886 <bitWidth>8</bitWidth>
13892 <displayName>TDH1R
</displayName>
13893 <description>mailbox data high register
</description>
13894 <addressOffset>0x19C</addressOffset>
13896 <access>read-write
</access>
13897 <resetValue>0x00000000</resetValue>
13901 <description>DATA7
</description>
13902 <bitOffset>24</bitOffset>
13903 <bitWidth>8</bitWidth>
13907 <description>DATA6
</description>
13908 <bitOffset>16</bitOffset>
13909 <bitWidth>8</bitWidth>
13913 <description>DATA5
</description>
13914 <bitOffset>8</bitOffset>
13915 <bitWidth>8</bitWidth>
13919 <description>DATA4
</description>
13920 <bitOffset>0</bitOffset>
13921 <bitWidth>8</bitWidth>
13927 <displayName>TI2R
</displayName>
13928 <description>TX mailbox identifier register
</description>
13929 <addressOffset>0x1A0</addressOffset>
13931 <access>read-write
</access>
13932 <resetValue>0x00000000</resetValue>
13936 <description>STID
</description>
13937 <bitOffset>21</bitOffset>
13938 <bitWidth>11</bitWidth>
13942 <description>EXID
</description>
13943 <bitOffset>3</bitOffset>
13944 <bitWidth>18</bitWidth>
13948 <description>IDE
</description>
13949 <bitOffset>2</bitOffset>
13950 <bitWidth>1</bitWidth>
13954 <description>RTR
</description>
13955 <bitOffset>1</bitOffset>
13956 <bitWidth>1</bitWidth>
13960 <description>TXRQ
</description>
13961 <bitOffset>0</bitOffset>
13962 <bitWidth>1</bitWidth>
13968 <displayName>TDT2R
</displayName>
13969 <description>mailbox data length control and time stamp
13970 register
</description>
13971 <addressOffset>0x1A4</addressOffset>
13973 <access>read-write
</access>
13974 <resetValue>0x00000000</resetValue>
13978 <description>TIME
</description>
13979 <bitOffset>16</bitOffset>
13980 <bitWidth>16</bitWidth>
13984 <description>TGT
</description>
13985 <bitOffset>8</bitOffset>
13986 <bitWidth>1</bitWidth>
13990 <description>DLC
</description>
13991 <bitOffset>0</bitOffset>
13992 <bitWidth>4</bitWidth>
13998 <displayName>TDL2R
</displayName>
13999 <description>mailbox data low register
</description>
14000 <addressOffset>0x1A8</addressOffset>
14002 <access>read-write
</access>
14003 <resetValue>0x00000000</resetValue>
14007 <description>DATA3
</description>
14008 <bitOffset>24</bitOffset>
14009 <bitWidth>8</bitWidth>
14013 <description>DATA2
</description>
14014 <bitOffset>16</bitOffset>
14015 <bitWidth>8</bitWidth>
14019 <description>DATA1
</description>
14020 <bitOffset>8</bitOffset>
14021 <bitWidth>8</bitWidth>
14025 <description>DATA0
</description>
14026 <bitOffset>0</bitOffset>
14027 <bitWidth>8</bitWidth>
14033 <displayName>TDH2R
</displayName>
14034 <description>mailbox data high register
</description>
14035 <addressOffset>0x1AC</addressOffset>
14037 <access>read-write
</access>
14038 <resetValue>0x00000000</resetValue>
14042 <description>DATA7
</description>
14043 <bitOffset>24</bitOffset>
14044 <bitWidth>8</bitWidth>
14048 <description>DATA6
</description>
14049 <bitOffset>16</bitOffset>
14050 <bitWidth>8</bitWidth>
14054 <description>DATA5
</description>
14055 <bitOffset>8</bitOffset>
14056 <bitWidth>8</bitWidth>
14060 <description>DATA4
</description>
14061 <bitOffset>0</bitOffset>
14062 <bitWidth>8</bitWidth>
14068 <displayName>RI0R
</displayName>
14069 <description>receive FIFO mailbox identifier
14070 register
</description>
14071 <addressOffset>0x1B0</addressOffset>
14073 <access>read-only
</access>
14074 <resetValue>0x00000000</resetValue>
14078 <description>STID
</description>
14079 <bitOffset>21</bitOffset>
14080 <bitWidth>11</bitWidth>
14084 <description>EXID
</description>
14085 <bitOffset>3</bitOffset>
14086 <bitWidth>18</bitWidth>
14090 <description>IDE
</description>
14091 <bitOffset>2</bitOffset>
14092 <bitWidth>1</bitWidth>
14096 <description>RTR
</description>
14097 <bitOffset>1</bitOffset>
14098 <bitWidth>1</bitWidth>
14104 <displayName>RDT0R
</displayName>
14105 <description>receive FIFO mailbox data length control and
14106 time stamp register
</description>
14107 <addressOffset>0x1B4</addressOffset>
14109 <access>read-only
</access>
14110 <resetValue>0x00000000</resetValue>
14114 <description>TIME
</description>
14115 <bitOffset>16</bitOffset>
14116 <bitWidth>16</bitWidth>
14120 <description>FMI
</description>
14121 <bitOffset>8</bitOffset>
14122 <bitWidth>8</bitWidth>
14126 <description>DLC
</description>
14127 <bitOffset>0</bitOffset>
14128 <bitWidth>4</bitWidth>
14134 <displayName>RDL0R
</displayName>
14135 <description>receive FIFO mailbox data low
14136 register
</description>
14137 <addressOffset>0x1B8</addressOffset>
14139 <access>read-only
</access>
14140 <resetValue>0x00000000</resetValue>
14144 <description>DATA3
</description>
14145 <bitOffset>24</bitOffset>
14146 <bitWidth>8</bitWidth>
14150 <description>DATA2
</description>
14151 <bitOffset>16</bitOffset>
14152 <bitWidth>8</bitWidth>
14156 <description>DATA1
</description>
14157 <bitOffset>8</bitOffset>
14158 <bitWidth>8</bitWidth>
14162 <description>DATA0
</description>
14163 <bitOffset>0</bitOffset>
14164 <bitWidth>8</bitWidth>
14170 <displayName>RDH0R
</displayName>
14171 <description>receive FIFO mailbox data high
14172 register
</description>
14173 <addressOffset>0x1BC</addressOffset>
14175 <access>read-only
</access>
14176 <resetValue>0x00000000</resetValue>
14180 <description>DATA7
</description>
14181 <bitOffset>24</bitOffset>
14182 <bitWidth>8</bitWidth>
14186 <description>DATA6
</description>
14187 <bitOffset>16</bitOffset>
14188 <bitWidth>8</bitWidth>
14192 <description>DATA5
</description>
14193 <bitOffset>8</bitOffset>
14194 <bitWidth>8</bitWidth>
14198 <description>DATA4
</description>
14199 <bitOffset>0</bitOffset>
14200 <bitWidth>8</bitWidth>
14206 <displayName>RI1R
</displayName>
14207 <description>receive FIFO mailbox identifier
14208 register
</description>
14209 <addressOffset>0x1C0</addressOffset>
14211 <access>read-only
</access>
14212 <resetValue>0x00000000</resetValue>
14216 <description>STID
</description>
14217 <bitOffset>21</bitOffset>
14218 <bitWidth>11</bitWidth>
14222 <description>EXID
</description>
14223 <bitOffset>3</bitOffset>
14224 <bitWidth>18</bitWidth>
14228 <description>IDE
</description>
14229 <bitOffset>2</bitOffset>
14230 <bitWidth>1</bitWidth>
14234 <description>RTR
</description>
14235 <bitOffset>1</bitOffset>
14236 <bitWidth>1</bitWidth>
14242 <displayName>RDT1R
</displayName>
14243 <description>receive FIFO mailbox data length control and
14244 time stamp register
</description>
14245 <addressOffset>0x1C4</addressOffset>
14247 <access>read-only
</access>
14248 <resetValue>0x00000000</resetValue>
14252 <description>TIME
</description>
14253 <bitOffset>16</bitOffset>
14254 <bitWidth>16</bitWidth>
14258 <description>FMI
</description>
14259 <bitOffset>8</bitOffset>
14260 <bitWidth>8</bitWidth>
14264 <description>DLC
</description>
14265 <bitOffset>0</bitOffset>
14266 <bitWidth>4</bitWidth>
14272 <displayName>RDL1R
</displayName>
14273 <description>receive FIFO mailbox data low
14274 register
</description>
14275 <addressOffset>0x1C8</addressOffset>
14277 <access>read-only
</access>
14278 <resetValue>0x00000000</resetValue>
14282 <description>DATA3
</description>
14283 <bitOffset>24</bitOffset>
14284 <bitWidth>8</bitWidth>
14288 <description>DATA2
</description>
14289 <bitOffset>16</bitOffset>
14290 <bitWidth>8</bitWidth>
14294 <description>DATA1
</description>
14295 <bitOffset>8</bitOffset>
14296 <bitWidth>8</bitWidth>
14300 <description>DATA0
</description>
14301 <bitOffset>0</bitOffset>
14302 <bitWidth>8</bitWidth>
14308 <displayName>RDH1R
</displayName>
14309 <description>receive FIFO mailbox data high
14310 register
</description>
14311 <addressOffset>0x1CC</addressOffset>
14313 <access>read-only
</access>
14314 <resetValue>0x00000000</resetValue>
14318 <description>DATA7
</description>
14319 <bitOffset>24</bitOffset>
14320 <bitWidth>8</bitWidth>
14324 <description>DATA6
</description>
14325 <bitOffset>16</bitOffset>
14326 <bitWidth>8</bitWidth>
14330 <description>DATA5
</description>
14331 <bitOffset>8</bitOffset>
14332 <bitWidth>8</bitWidth>
14336 <description>DATA4
</description>
14337 <bitOffset>0</bitOffset>
14338 <bitWidth>8</bitWidth>
14344 <displayName>FMR
</displayName>
14345 <description>filter master register
</description>
14346 <addressOffset>0x200</addressOffset>
14348 <access>read-write
</access>
14349 <resetValue>0x2A1C0E01</resetValue>
14352 <name>CAN2SB
</name>
14353 <description>CAN2 start bank
</description>
14354 <bitOffset>8</bitOffset>
14355 <bitWidth>6</bitWidth>
14359 <description>Filter init mode
</description>
14360 <bitOffset>0</bitOffset>
14361 <bitWidth>1</bitWidth>
14367 <displayName>FM1R
</displayName>
14368 <description>filter mode register
</description>
14369 <addressOffset>0x204</addressOffset>
14371 <access>read-write
</access>
14372 <resetValue>0x00000000</resetValue>
14376 <description>Filter mode
</description>
14377 <bitOffset>0</bitOffset>
14378 <bitWidth>1</bitWidth>
14382 <description>Filter mode
</description>
14383 <bitOffset>1</bitOffset>
14384 <bitWidth>1</bitWidth>
14388 <description>Filter mode
</description>
14389 <bitOffset>2</bitOffset>
14390 <bitWidth>1</bitWidth>
14394 <description>Filter mode
</description>
14395 <bitOffset>3</bitOffset>
14396 <bitWidth>1</bitWidth>
14400 <description>Filter mode
</description>
14401 <bitOffset>4</bitOffset>
14402 <bitWidth>1</bitWidth>
14406 <description>Filter mode
</description>
14407 <bitOffset>5</bitOffset>
14408 <bitWidth>1</bitWidth>
14412 <description>Filter mode
</description>
14413 <bitOffset>6</bitOffset>
14414 <bitWidth>1</bitWidth>
14418 <description>Filter mode
</description>
14419 <bitOffset>7</bitOffset>
14420 <bitWidth>1</bitWidth>
14424 <description>Filter mode
</description>
14425 <bitOffset>8</bitOffset>
14426 <bitWidth>1</bitWidth>
14430 <description>Filter mode
</description>
14431 <bitOffset>9</bitOffset>
14432 <bitWidth>1</bitWidth>
14436 <description>Filter mode
</description>
14437 <bitOffset>10</bitOffset>
14438 <bitWidth>1</bitWidth>
14442 <description>Filter mode
</description>
14443 <bitOffset>11</bitOffset>
14444 <bitWidth>1</bitWidth>
14448 <description>Filter mode
</description>
14449 <bitOffset>12</bitOffset>
14450 <bitWidth>1</bitWidth>
14454 <description>Filter mode
</description>
14455 <bitOffset>13</bitOffset>
14456 <bitWidth>1</bitWidth>
14460 <description>Filter mode
</description>
14461 <bitOffset>14</bitOffset>
14462 <bitWidth>1</bitWidth>
14466 <description>Filter mode
</description>
14467 <bitOffset>15</bitOffset>
14468 <bitWidth>1</bitWidth>
14472 <description>Filter mode
</description>
14473 <bitOffset>16</bitOffset>
14474 <bitWidth>1</bitWidth>
14478 <description>Filter mode
</description>
14479 <bitOffset>17</bitOffset>
14480 <bitWidth>1</bitWidth>
14484 <description>Filter mode
</description>
14485 <bitOffset>18</bitOffset>
14486 <bitWidth>1</bitWidth>
14490 <description>Filter mode
</description>
14491 <bitOffset>19</bitOffset>
14492 <bitWidth>1</bitWidth>
14496 <description>Filter mode
</description>
14497 <bitOffset>20</bitOffset>
14498 <bitWidth>1</bitWidth>
14502 <description>Filter mode
</description>
14503 <bitOffset>21</bitOffset>
14504 <bitWidth>1</bitWidth>
14508 <description>Filter mode
</description>
14509 <bitOffset>22</bitOffset>
14510 <bitWidth>1</bitWidth>
14514 <description>Filter mode
</description>
14515 <bitOffset>23</bitOffset>
14516 <bitWidth>1</bitWidth>
14520 <description>Filter mode
</description>
14521 <bitOffset>24</bitOffset>
14522 <bitWidth>1</bitWidth>
14526 <description>Filter mode
</description>
14527 <bitOffset>25</bitOffset>
14528 <bitWidth>1</bitWidth>
14532 <description>Filter mode
</description>
14533 <bitOffset>26</bitOffset>
14534 <bitWidth>1</bitWidth>
14538 <description>Filter mode
</description>
14539 <bitOffset>27</bitOffset>
14540 <bitWidth>1</bitWidth>
14546 <displayName>FS1R
</displayName>
14547 <description>filter scale register
</description>
14548 <addressOffset>0x20C</addressOffset>
14550 <access>read-write
</access>
14551 <resetValue>0x00000000</resetValue>
14555 <description>Filter scale configuration
</description>
14556 <bitOffset>0</bitOffset>
14557 <bitWidth>1</bitWidth>
14561 <description>Filter scale configuration
</description>
14562 <bitOffset>1</bitOffset>
14563 <bitWidth>1</bitWidth>
14567 <description>Filter scale configuration
</description>
14568 <bitOffset>2</bitOffset>
14569 <bitWidth>1</bitWidth>
14573 <description>Filter scale configuration
</description>
14574 <bitOffset>3</bitOffset>
14575 <bitWidth>1</bitWidth>
14579 <description>Filter scale configuration
</description>
14580 <bitOffset>4</bitOffset>
14581 <bitWidth>1</bitWidth>
14585 <description>Filter scale configuration
</description>
14586 <bitOffset>5</bitOffset>
14587 <bitWidth>1</bitWidth>
14591 <description>Filter scale configuration
</description>
14592 <bitOffset>6</bitOffset>
14593 <bitWidth>1</bitWidth>
14597 <description>Filter scale configuration
</description>
14598 <bitOffset>7</bitOffset>
14599 <bitWidth>1</bitWidth>
14603 <description>Filter scale configuration
</description>
14604 <bitOffset>8</bitOffset>
14605 <bitWidth>1</bitWidth>
14609 <description>Filter scale configuration
</description>
14610 <bitOffset>9</bitOffset>
14611 <bitWidth>1</bitWidth>
14615 <description>Filter scale configuration
</description>
14616 <bitOffset>10</bitOffset>
14617 <bitWidth>1</bitWidth>
14621 <description>Filter scale configuration
</description>
14622 <bitOffset>11</bitOffset>
14623 <bitWidth>1</bitWidth>
14627 <description>Filter scale configuration
</description>
14628 <bitOffset>12</bitOffset>
14629 <bitWidth>1</bitWidth>
14633 <description>Filter scale configuration
</description>
14634 <bitOffset>13</bitOffset>
14635 <bitWidth>1</bitWidth>
14639 <description>Filter scale configuration
</description>
14640 <bitOffset>14</bitOffset>
14641 <bitWidth>1</bitWidth>
14645 <description>Filter scale configuration
</description>
14646 <bitOffset>15</bitOffset>
14647 <bitWidth>1</bitWidth>
14651 <description>Filter scale configuration
</description>
14652 <bitOffset>16</bitOffset>
14653 <bitWidth>1</bitWidth>
14657 <description>Filter scale configuration
</description>
14658 <bitOffset>17</bitOffset>
14659 <bitWidth>1</bitWidth>
14663 <description>Filter scale configuration
</description>
14664 <bitOffset>18</bitOffset>
14665 <bitWidth>1</bitWidth>
14669 <description>Filter scale configuration
</description>
14670 <bitOffset>19</bitOffset>
14671 <bitWidth>1</bitWidth>
14675 <description>Filter scale configuration
</description>
14676 <bitOffset>20</bitOffset>
14677 <bitWidth>1</bitWidth>
14681 <description>Filter scale configuration
</description>
14682 <bitOffset>21</bitOffset>
14683 <bitWidth>1</bitWidth>
14687 <description>Filter scale configuration
</description>
14688 <bitOffset>22</bitOffset>
14689 <bitWidth>1</bitWidth>
14693 <description>Filter scale configuration
</description>
14694 <bitOffset>23</bitOffset>
14695 <bitWidth>1</bitWidth>
14699 <description>Filter scale configuration
</description>
14700 <bitOffset>24</bitOffset>
14701 <bitWidth>1</bitWidth>
14705 <description>Filter scale configuration
</description>
14706 <bitOffset>25</bitOffset>
14707 <bitWidth>1</bitWidth>
14711 <description>Filter scale configuration
</description>
14712 <bitOffset>26</bitOffset>
14713 <bitWidth>1</bitWidth>
14717 <description>Filter scale configuration
</description>
14718 <bitOffset>27</bitOffset>
14719 <bitWidth>1</bitWidth>
14725 <displayName>FFA1R
</displayName>
14726 <description>filter FIFO assignment
14727 register
</description>
14728 <addressOffset>0x214</addressOffset>
14730 <access>read-write
</access>
14731 <resetValue>0x00000000</resetValue>
14735 <description>Filter FIFO assignment for filter
14737 <bitOffset>0</bitOffset>
14738 <bitWidth>1</bitWidth>
14742 <description>Filter FIFO assignment for filter
14744 <bitOffset>1</bitOffset>
14745 <bitWidth>1</bitWidth>
14749 <description>Filter FIFO assignment for filter
14751 <bitOffset>2</bitOffset>
14752 <bitWidth>1</bitWidth>
14756 <description>Filter FIFO assignment for filter
14758 <bitOffset>3</bitOffset>
14759 <bitWidth>1</bitWidth>
14763 <description>Filter FIFO assignment for filter
14765 <bitOffset>4</bitOffset>
14766 <bitWidth>1</bitWidth>
14770 <description>Filter FIFO assignment for filter
14772 <bitOffset>5</bitOffset>
14773 <bitWidth>1</bitWidth>
14777 <description>Filter FIFO assignment for filter
14779 <bitOffset>6</bitOffset>
14780 <bitWidth>1</bitWidth>
14784 <description>Filter FIFO assignment for filter
14786 <bitOffset>7</bitOffset>
14787 <bitWidth>1</bitWidth>
14791 <description>Filter FIFO assignment for filter
14793 <bitOffset>8</bitOffset>
14794 <bitWidth>1</bitWidth>
14798 <description>Filter FIFO assignment for filter
14800 <bitOffset>9</bitOffset>
14801 <bitWidth>1</bitWidth>
14805 <description>Filter FIFO assignment for filter
14807 <bitOffset>10</bitOffset>
14808 <bitWidth>1</bitWidth>
14812 <description>Filter FIFO assignment for filter
14814 <bitOffset>11</bitOffset>
14815 <bitWidth>1</bitWidth>
14819 <description>Filter FIFO assignment for filter
14821 <bitOffset>12</bitOffset>
14822 <bitWidth>1</bitWidth>
14826 <description>Filter FIFO assignment for filter
14828 <bitOffset>13</bitOffset>
14829 <bitWidth>1</bitWidth>
14833 <description>Filter FIFO assignment for filter
14835 <bitOffset>14</bitOffset>
14836 <bitWidth>1</bitWidth>
14840 <description>Filter FIFO assignment for filter
14842 <bitOffset>15</bitOffset>
14843 <bitWidth>1</bitWidth>
14847 <description>Filter FIFO assignment for filter
14849 <bitOffset>16</bitOffset>
14850 <bitWidth>1</bitWidth>
14854 <description>Filter FIFO assignment for filter
14856 <bitOffset>17</bitOffset>
14857 <bitWidth>1</bitWidth>
14861 <description>Filter FIFO assignment for filter
14863 <bitOffset>18</bitOffset>
14864 <bitWidth>1</bitWidth>
14868 <description>Filter FIFO assignment for filter
14870 <bitOffset>19</bitOffset>
14871 <bitWidth>1</bitWidth>
14875 <description>Filter FIFO assignment for filter
14877 <bitOffset>20</bitOffset>
14878 <bitWidth>1</bitWidth>
14882 <description>Filter FIFO assignment for filter
14884 <bitOffset>21</bitOffset>
14885 <bitWidth>1</bitWidth>
14889 <description>Filter FIFO assignment for filter
14891 <bitOffset>22</bitOffset>
14892 <bitWidth>1</bitWidth>
14896 <description>Filter FIFO assignment for filter
14898 <bitOffset>23</bitOffset>
14899 <bitWidth>1</bitWidth>
14903 <description>Filter FIFO assignment for filter
14905 <bitOffset>24</bitOffset>
14906 <bitWidth>1</bitWidth>
14910 <description>Filter FIFO assignment for filter
14912 <bitOffset>25</bitOffset>
14913 <bitWidth>1</bitWidth>
14917 <description>Filter FIFO assignment for filter
14919 <bitOffset>26</bitOffset>
14920 <bitWidth>1</bitWidth>
14924 <description>Filter FIFO assignment for filter
14926 <bitOffset>27</bitOffset>
14927 <bitWidth>1</bitWidth>
14933 <displayName>FA1R
</displayName>
14934 <description>CAN filter activation register
</description>
14935 <addressOffset>0x21C</addressOffset>
14937 <access>read-write
</access>
14938 <resetValue>0x00000000</resetValue>
14942 <description>Filter active
</description>
14943 <bitOffset>0</bitOffset>
14944 <bitWidth>1</bitWidth>
14948 <description>Filter active
</description>
14949 <bitOffset>1</bitOffset>
14950 <bitWidth>1</bitWidth>
14954 <description>Filter active
</description>
14955 <bitOffset>2</bitOffset>
14956 <bitWidth>1</bitWidth>
14960 <description>Filter active
</description>
14961 <bitOffset>3</bitOffset>
14962 <bitWidth>1</bitWidth>
14966 <description>Filter active
</description>
14967 <bitOffset>4</bitOffset>
14968 <bitWidth>1</bitWidth>
14972 <description>Filter active
</description>
14973 <bitOffset>5</bitOffset>
14974 <bitWidth>1</bitWidth>
14978 <description>Filter active
</description>
14979 <bitOffset>6</bitOffset>
14980 <bitWidth>1</bitWidth>
14984 <description>Filter active
</description>
14985 <bitOffset>7</bitOffset>
14986 <bitWidth>1</bitWidth>
14990 <description>Filter active
</description>
14991 <bitOffset>8</bitOffset>
14992 <bitWidth>1</bitWidth>
14996 <description>Filter active
</description>
14997 <bitOffset>9</bitOffset>
14998 <bitWidth>1</bitWidth>
15001 <name>FACT10
</name>
15002 <description>Filter active
</description>
15003 <bitOffset>10</bitOffset>
15004 <bitWidth>1</bitWidth>
15007 <name>FACT11
</name>
15008 <description>Filter active
</description>
15009 <bitOffset>11</bitOffset>
15010 <bitWidth>1</bitWidth>
15013 <name>FACT12
</name>
15014 <description>Filter active
</description>
15015 <bitOffset>12</bitOffset>
15016 <bitWidth>1</bitWidth>
15019 <name>FACT13
</name>
15020 <description>Filter active
</description>
15021 <bitOffset>13</bitOffset>
15022 <bitWidth>1</bitWidth>
15025 <name>FACT14
</name>
15026 <description>Filter active
</description>
15027 <bitOffset>14</bitOffset>
15028 <bitWidth>1</bitWidth>
15031 <name>FACT15
</name>
15032 <description>Filter active
</description>
15033 <bitOffset>15</bitOffset>
15034 <bitWidth>1</bitWidth>
15037 <name>FACT16
</name>
15038 <description>Filter active
</description>
15039 <bitOffset>16</bitOffset>
15040 <bitWidth>1</bitWidth>
15043 <name>FACT17
</name>
15044 <description>Filter active
</description>
15045 <bitOffset>17</bitOffset>
15046 <bitWidth>1</bitWidth>
15049 <name>FACT18
</name>
15050 <description>Filter active
</description>
15051 <bitOffset>18</bitOffset>
15052 <bitWidth>1</bitWidth>
15055 <name>FACT19
</name>
15056 <description>Filter active
</description>
15057 <bitOffset>19</bitOffset>
15058 <bitWidth>1</bitWidth>
15061 <name>FACT20
</name>
15062 <description>Filter active
</description>
15063 <bitOffset>20</bitOffset>
15064 <bitWidth>1</bitWidth>
15067 <name>FACT21
</name>
15068 <description>Filter active
</description>
15069 <bitOffset>21</bitOffset>
15070 <bitWidth>1</bitWidth>
15073 <name>FACT22
</name>
15074 <description>Filter active
</description>
15075 <bitOffset>22</bitOffset>
15076 <bitWidth>1</bitWidth>
15079 <name>FACT23
</name>
15080 <description>Filter active
</description>
15081 <bitOffset>23</bitOffset>
15082 <bitWidth>1</bitWidth>
15085 <name>FACT24
</name>
15086 <description>Filter active
</description>
15087 <bitOffset>24</bitOffset>
15088 <bitWidth>1</bitWidth>
15091 <name>FACT25
</name>
15092 <description>Filter active
</description>
15093 <bitOffset>25</bitOffset>
15094 <bitWidth>1</bitWidth>
15097 <name>FACT26
</name>
15098 <description>Filter active
</description>
15099 <bitOffset>26</bitOffset>
15100 <bitWidth>1</bitWidth>
15103 <name>FACT27
</name>
15104 <description>Filter active
</description>
15105 <bitOffset>27</bitOffset>
15106 <bitWidth>1</bitWidth>
15112 <displayName>F0R1
</displayName>
15113 <description>Filter bank
0 register
1</description>
15114 <addressOffset>0x240</addressOffset>
15116 <access>read-write
</access>
15117 <resetValue>0x00000000</resetValue>
15121 <description>Filter bits
</description>
15122 <bitOffset>0</bitOffset>
15123 <bitWidth>1</bitWidth>
15127 <description>Filter bits
</description>
15128 <bitOffset>1</bitOffset>
15129 <bitWidth>1</bitWidth>
15133 <description>Filter bits
</description>
15134 <bitOffset>2</bitOffset>
15135 <bitWidth>1</bitWidth>
15139 <description>Filter bits
</description>
15140 <bitOffset>3</bitOffset>
15141 <bitWidth>1</bitWidth>
15145 <description>Filter bits
</description>
15146 <bitOffset>4</bitOffset>
15147 <bitWidth>1</bitWidth>
15151 <description>Filter bits
</description>
15152 <bitOffset>5</bitOffset>
15153 <bitWidth>1</bitWidth>
15157 <description>Filter bits
</description>
15158 <bitOffset>6</bitOffset>
15159 <bitWidth>1</bitWidth>
15163 <description>Filter bits
</description>
15164 <bitOffset>7</bitOffset>
15165 <bitWidth>1</bitWidth>
15169 <description>Filter bits
</description>
15170 <bitOffset>8</bitOffset>
15171 <bitWidth>1</bitWidth>
15175 <description>Filter bits
</description>
15176 <bitOffset>9</bitOffset>
15177 <bitWidth>1</bitWidth>
15181 <description>Filter bits
</description>
15182 <bitOffset>10</bitOffset>
15183 <bitWidth>1</bitWidth>
15187 <description>Filter bits
</description>
15188 <bitOffset>11</bitOffset>
15189 <bitWidth>1</bitWidth>
15193 <description>Filter bits
</description>
15194 <bitOffset>12</bitOffset>
15195 <bitWidth>1</bitWidth>
15199 <description>Filter bits
</description>
15200 <bitOffset>13</bitOffset>
15201 <bitWidth>1</bitWidth>
15205 <description>Filter bits
</description>
15206 <bitOffset>14</bitOffset>
15207 <bitWidth>1</bitWidth>
15211 <description>Filter bits
</description>
15212 <bitOffset>15</bitOffset>
15213 <bitWidth>1</bitWidth>
15217 <description>Filter bits
</description>
15218 <bitOffset>16</bitOffset>
15219 <bitWidth>1</bitWidth>
15223 <description>Filter bits
</description>
15224 <bitOffset>17</bitOffset>
15225 <bitWidth>1</bitWidth>
15229 <description>Filter bits
</description>
15230 <bitOffset>18</bitOffset>
15231 <bitWidth>1</bitWidth>
15235 <description>Filter bits
</description>
15236 <bitOffset>19</bitOffset>
15237 <bitWidth>1</bitWidth>
15241 <description>Filter bits
</description>
15242 <bitOffset>20</bitOffset>
15243 <bitWidth>1</bitWidth>
15247 <description>Filter bits
</description>
15248 <bitOffset>21</bitOffset>
15249 <bitWidth>1</bitWidth>
15253 <description>Filter bits
</description>
15254 <bitOffset>22</bitOffset>
15255 <bitWidth>1</bitWidth>
15259 <description>Filter bits
</description>
15260 <bitOffset>23</bitOffset>
15261 <bitWidth>1</bitWidth>
15265 <description>Filter bits
</description>
15266 <bitOffset>24</bitOffset>
15267 <bitWidth>1</bitWidth>
15271 <description>Filter bits
</description>
15272 <bitOffset>25</bitOffset>
15273 <bitWidth>1</bitWidth>
15277 <description>Filter bits
</description>
15278 <bitOffset>26</bitOffset>
15279 <bitWidth>1</bitWidth>
15283 <description>Filter bits
</description>
15284 <bitOffset>27</bitOffset>
15285 <bitWidth>1</bitWidth>
15289 <description>Filter bits
</description>
15290 <bitOffset>28</bitOffset>
15291 <bitWidth>1</bitWidth>
15295 <description>Filter bits
</description>
15296 <bitOffset>29</bitOffset>
15297 <bitWidth>1</bitWidth>
15301 <description>Filter bits
</description>
15302 <bitOffset>30</bitOffset>
15303 <bitWidth>1</bitWidth>
15307 <description>Filter bits
</description>
15308 <bitOffset>31</bitOffset>
15309 <bitWidth>1</bitWidth>
15315 <displayName>F0R2
</displayName>
15316 <description>Filter bank
0 register
2</description>
15317 <addressOffset>0x244</addressOffset>
15319 <access>read-write
</access>
15320 <resetValue>0x00000000</resetValue>
15324 <description>Filter bits
</description>
15325 <bitOffset>0</bitOffset>
15326 <bitWidth>1</bitWidth>
15330 <description>Filter bits
</description>
15331 <bitOffset>1</bitOffset>
15332 <bitWidth>1</bitWidth>
15336 <description>Filter bits
</description>
15337 <bitOffset>2</bitOffset>
15338 <bitWidth>1</bitWidth>
15342 <description>Filter bits
</description>
15343 <bitOffset>3</bitOffset>
15344 <bitWidth>1</bitWidth>
15348 <description>Filter bits
</description>
15349 <bitOffset>4</bitOffset>
15350 <bitWidth>1</bitWidth>
15354 <description>Filter bits
</description>
15355 <bitOffset>5</bitOffset>
15356 <bitWidth>1</bitWidth>
15360 <description>Filter bits
</description>
15361 <bitOffset>6</bitOffset>
15362 <bitWidth>1</bitWidth>
15366 <description>Filter bits
</description>
15367 <bitOffset>7</bitOffset>
15368 <bitWidth>1</bitWidth>
15372 <description>Filter bits
</description>
15373 <bitOffset>8</bitOffset>
15374 <bitWidth>1</bitWidth>
15378 <description>Filter bits
</description>
15379 <bitOffset>9</bitOffset>
15380 <bitWidth>1</bitWidth>
15384 <description>Filter bits
</description>
15385 <bitOffset>10</bitOffset>
15386 <bitWidth>1</bitWidth>
15390 <description>Filter bits
</description>
15391 <bitOffset>11</bitOffset>
15392 <bitWidth>1</bitWidth>
15396 <description>Filter bits
</description>
15397 <bitOffset>12</bitOffset>
15398 <bitWidth>1</bitWidth>
15402 <description>Filter bits
</description>
15403 <bitOffset>13</bitOffset>
15404 <bitWidth>1</bitWidth>
15408 <description>Filter bits
</description>
15409 <bitOffset>14</bitOffset>
15410 <bitWidth>1</bitWidth>
15414 <description>Filter bits
</description>
15415 <bitOffset>15</bitOffset>
15416 <bitWidth>1</bitWidth>
15420 <description>Filter bits
</description>
15421 <bitOffset>16</bitOffset>
15422 <bitWidth>1</bitWidth>
15426 <description>Filter bits
</description>
15427 <bitOffset>17</bitOffset>
15428 <bitWidth>1</bitWidth>
15432 <description>Filter bits
</description>
15433 <bitOffset>18</bitOffset>
15434 <bitWidth>1</bitWidth>
15438 <description>Filter bits
</description>
15439 <bitOffset>19</bitOffset>
15440 <bitWidth>1</bitWidth>
15444 <description>Filter bits
</description>
15445 <bitOffset>20</bitOffset>
15446 <bitWidth>1</bitWidth>
15450 <description>Filter bits
</description>
15451 <bitOffset>21</bitOffset>
15452 <bitWidth>1</bitWidth>
15456 <description>Filter bits
</description>
15457 <bitOffset>22</bitOffset>
15458 <bitWidth>1</bitWidth>
15462 <description>Filter bits
</description>
15463 <bitOffset>23</bitOffset>
15464 <bitWidth>1</bitWidth>
15468 <description>Filter bits
</description>
15469 <bitOffset>24</bitOffset>
15470 <bitWidth>1</bitWidth>
15474 <description>Filter bits
</description>
15475 <bitOffset>25</bitOffset>
15476 <bitWidth>1</bitWidth>
15480 <description>Filter bits
</description>
15481 <bitOffset>26</bitOffset>
15482 <bitWidth>1</bitWidth>
15486 <description>Filter bits
</description>
15487 <bitOffset>27</bitOffset>
15488 <bitWidth>1</bitWidth>
15492 <description>Filter bits
</description>
15493 <bitOffset>28</bitOffset>
15494 <bitWidth>1</bitWidth>
15498 <description>Filter bits
</description>
15499 <bitOffset>29</bitOffset>
15500 <bitWidth>1</bitWidth>
15504 <description>Filter bits
</description>
15505 <bitOffset>30</bitOffset>
15506 <bitWidth>1</bitWidth>
15510 <description>Filter bits
</description>
15511 <bitOffset>31</bitOffset>
15512 <bitWidth>1</bitWidth>
15518 <displayName>F1R1
</displayName>
15519 <description>Filter bank
1 register
1</description>
15520 <addressOffset>0x248</addressOffset>
15522 <access>read-write
</access>
15523 <resetValue>0x00000000</resetValue>
15527 <description>Filter bits
</description>
15528 <bitOffset>0</bitOffset>
15529 <bitWidth>1</bitWidth>
15533 <description>Filter bits
</description>
15534 <bitOffset>1</bitOffset>
15535 <bitWidth>1</bitWidth>
15539 <description>Filter bits
</description>
15540 <bitOffset>2</bitOffset>
15541 <bitWidth>1</bitWidth>
15545 <description>Filter bits
</description>
15546 <bitOffset>3</bitOffset>
15547 <bitWidth>1</bitWidth>
15551 <description>Filter bits
</description>
15552 <bitOffset>4</bitOffset>
15553 <bitWidth>1</bitWidth>
15557 <description>Filter bits
</description>
15558 <bitOffset>5</bitOffset>
15559 <bitWidth>1</bitWidth>
15563 <description>Filter bits
</description>
15564 <bitOffset>6</bitOffset>
15565 <bitWidth>1</bitWidth>
15569 <description>Filter bits
</description>
15570 <bitOffset>7</bitOffset>
15571 <bitWidth>1</bitWidth>
15575 <description>Filter bits
</description>
15576 <bitOffset>8</bitOffset>
15577 <bitWidth>1</bitWidth>
15581 <description>Filter bits
</description>
15582 <bitOffset>9</bitOffset>
15583 <bitWidth>1</bitWidth>
15587 <description>Filter bits
</description>
15588 <bitOffset>10</bitOffset>
15589 <bitWidth>1</bitWidth>
15593 <description>Filter bits
</description>
15594 <bitOffset>11</bitOffset>
15595 <bitWidth>1</bitWidth>
15599 <description>Filter bits
</description>
15600 <bitOffset>12</bitOffset>
15601 <bitWidth>1</bitWidth>
15605 <description>Filter bits
</description>
15606 <bitOffset>13</bitOffset>
15607 <bitWidth>1</bitWidth>
15611 <description>Filter bits
</description>
15612 <bitOffset>14</bitOffset>
15613 <bitWidth>1</bitWidth>
15617 <description>Filter bits
</description>
15618 <bitOffset>15</bitOffset>
15619 <bitWidth>1</bitWidth>
15623 <description>Filter bits
</description>
15624 <bitOffset>16</bitOffset>
15625 <bitWidth>1</bitWidth>
15629 <description>Filter bits
</description>
15630 <bitOffset>17</bitOffset>
15631 <bitWidth>1</bitWidth>
15635 <description>Filter bits
</description>
15636 <bitOffset>18</bitOffset>
15637 <bitWidth>1</bitWidth>
15641 <description>Filter bits
</description>
15642 <bitOffset>19</bitOffset>
15643 <bitWidth>1</bitWidth>
15647 <description>Filter bits
</description>
15648 <bitOffset>20</bitOffset>
15649 <bitWidth>1</bitWidth>
15653 <description>Filter bits
</description>
15654 <bitOffset>21</bitOffset>
15655 <bitWidth>1</bitWidth>
15659 <description>Filter bits
</description>
15660 <bitOffset>22</bitOffset>
15661 <bitWidth>1</bitWidth>
15665 <description>Filter bits
</description>
15666 <bitOffset>23</bitOffset>
15667 <bitWidth>1</bitWidth>
15671 <description>Filter bits
</description>
15672 <bitOffset>24</bitOffset>
15673 <bitWidth>1</bitWidth>
15677 <description>Filter bits
</description>
15678 <bitOffset>25</bitOffset>
15679 <bitWidth>1</bitWidth>
15683 <description>Filter bits
</description>
15684 <bitOffset>26</bitOffset>
15685 <bitWidth>1</bitWidth>
15689 <description>Filter bits
</description>
15690 <bitOffset>27</bitOffset>
15691 <bitWidth>1</bitWidth>
15695 <description>Filter bits
</description>
15696 <bitOffset>28</bitOffset>
15697 <bitWidth>1</bitWidth>
15701 <description>Filter bits
</description>
15702 <bitOffset>29</bitOffset>
15703 <bitWidth>1</bitWidth>
15707 <description>Filter bits
</description>
15708 <bitOffset>30</bitOffset>
15709 <bitWidth>1</bitWidth>
15713 <description>Filter bits
</description>
15714 <bitOffset>31</bitOffset>
15715 <bitWidth>1</bitWidth>
15721 <displayName>F1R2
</displayName>
15722 <description>Filter bank
1 register
2</description>
15723 <addressOffset>0x24C</addressOffset>
15725 <access>read-write
</access>
15726 <resetValue>0x00000000</resetValue>
15730 <description>Filter bits
</description>
15731 <bitOffset>0</bitOffset>
15732 <bitWidth>1</bitWidth>
15736 <description>Filter bits
</description>
15737 <bitOffset>1</bitOffset>
15738 <bitWidth>1</bitWidth>
15742 <description>Filter bits
</description>
15743 <bitOffset>2</bitOffset>
15744 <bitWidth>1</bitWidth>
15748 <description>Filter bits
</description>
15749 <bitOffset>3</bitOffset>
15750 <bitWidth>1</bitWidth>
15754 <description>Filter bits
</description>
15755 <bitOffset>4</bitOffset>
15756 <bitWidth>1</bitWidth>
15760 <description>Filter bits
</description>
15761 <bitOffset>5</bitOffset>
15762 <bitWidth>1</bitWidth>
15766 <description>Filter bits
</description>
15767 <bitOffset>6</bitOffset>
15768 <bitWidth>1</bitWidth>
15772 <description>Filter bits
</description>
15773 <bitOffset>7</bitOffset>
15774 <bitWidth>1</bitWidth>
15778 <description>Filter bits
</description>
15779 <bitOffset>8</bitOffset>
15780 <bitWidth>1</bitWidth>
15784 <description>Filter bits
</description>
15785 <bitOffset>9</bitOffset>
15786 <bitWidth>1</bitWidth>
15790 <description>Filter bits
</description>
15791 <bitOffset>10</bitOffset>
15792 <bitWidth>1</bitWidth>
15796 <description>Filter bits
</description>
15797 <bitOffset>11</bitOffset>
15798 <bitWidth>1</bitWidth>
15802 <description>Filter bits
</description>
15803 <bitOffset>12</bitOffset>
15804 <bitWidth>1</bitWidth>
15808 <description>Filter bits
</description>
15809 <bitOffset>13</bitOffset>
15810 <bitWidth>1</bitWidth>
15814 <description>Filter bits
</description>
15815 <bitOffset>14</bitOffset>
15816 <bitWidth>1</bitWidth>
15820 <description>Filter bits
</description>
15821 <bitOffset>15</bitOffset>
15822 <bitWidth>1</bitWidth>
15826 <description>Filter bits
</description>
15827 <bitOffset>16</bitOffset>
15828 <bitWidth>1</bitWidth>
15832 <description>Filter bits
</description>
15833 <bitOffset>17</bitOffset>
15834 <bitWidth>1</bitWidth>
15838 <description>Filter bits
</description>
15839 <bitOffset>18</bitOffset>
15840 <bitWidth>1</bitWidth>
15844 <description>Filter bits
</description>
15845 <bitOffset>19</bitOffset>
15846 <bitWidth>1</bitWidth>
15850 <description>Filter bits
</description>
15851 <bitOffset>20</bitOffset>
15852 <bitWidth>1</bitWidth>
15856 <description>Filter bits
</description>
15857 <bitOffset>21</bitOffset>
15858 <bitWidth>1</bitWidth>
15862 <description>Filter bits
</description>
15863 <bitOffset>22</bitOffset>
15864 <bitWidth>1</bitWidth>
15868 <description>Filter bits
</description>
15869 <bitOffset>23</bitOffset>
15870 <bitWidth>1</bitWidth>
15874 <description>Filter bits
</description>
15875 <bitOffset>24</bitOffset>
15876 <bitWidth>1</bitWidth>
15880 <description>Filter bits
</description>
15881 <bitOffset>25</bitOffset>
15882 <bitWidth>1</bitWidth>
15886 <description>Filter bits
</description>
15887 <bitOffset>26</bitOffset>
15888 <bitWidth>1</bitWidth>
15892 <description>Filter bits
</description>
15893 <bitOffset>27</bitOffset>
15894 <bitWidth>1</bitWidth>
15898 <description>Filter bits
</description>
15899 <bitOffset>28</bitOffset>
15900 <bitWidth>1</bitWidth>
15904 <description>Filter bits
</description>
15905 <bitOffset>29</bitOffset>
15906 <bitWidth>1</bitWidth>
15910 <description>Filter bits
</description>
15911 <bitOffset>30</bitOffset>
15912 <bitWidth>1</bitWidth>
15916 <description>Filter bits
</description>
15917 <bitOffset>31</bitOffset>
15918 <bitWidth>1</bitWidth>
15924 <displayName>F2R1
</displayName>
15925 <description>Filter bank
2 register
1</description>
15926 <addressOffset>0x250</addressOffset>
15928 <access>read-write
</access>
15929 <resetValue>0x00000000</resetValue>
15933 <description>Filter bits
</description>
15934 <bitOffset>0</bitOffset>
15935 <bitWidth>1</bitWidth>
15939 <description>Filter bits
</description>
15940 <bitOffset>1</bitOffset>
15941 <bitWidth>1</bitWidth>
15945 <description>Filter bits
</description>
15946 <bitOffset>2</bitOffset>
15947 <bitWidth>1</bitWidth>
15951 <description>Filter bits
</description>
15952 <bitOffset>3</bitOffset>
15953 <bitWidth>1</bitWidth>
15957 <description>Filter bits
</description>
15958 <bitOffset>4</bitOffset>
15959 <bitWidth>1</bitWidth>
15963 <description>Filter bits
</description>
15964 <bitOffset>5</bitOffset>
15965 <bitWidth>1</bitWidth>
15969 <description>Filter bits
</description>
15970 <bitOffset>6</bitOffset>
15971 <bitWidth>1</bitWidth>
15975 <description>Filter bits
</description>
15976 <bitOffset>7</bitOffset>
15977 <bitWidth>1</bitWidth>
15981 <description>Filter bits
</description>
15982 <bitOffset>8</bitOffset>
15983 <bitWidth>1</bitWidth>
15987 <description>Filter bits
</description>
15988 <bitOffset>9</bitOffset>
15989 <bitWidth>1</bitWidth>
15993 <description>Filter bits
</description>
15994 <bitOffset>10</bitOffset>
15995 <bitWidth>1</bitWidth>
15999 <description>Filter bits
</description>
16000 <bitOffset>11</bitOffset>
16001 <bitWidth>1</bitWidth>
16005 <description>Filter bits
</description>
16006 <bitOffset>12</bitOffset>
16007 <bitWidth>1</bitWidth>
16011 <description>Filter bits
</description>
16012 <bitOffset>13</bitOffset>
16013 <bitWidth>1</bitWidth>
16017 <description>Filter bits
</description>
16018 <bitOffset>14</bitOffset>
16019 <bitWidth>1</bitWidth>
16023 <description>Filter bits
</description>
16024 <bitOffset>15</bitOffset>
16025 <bitWidth>1</bitWidth>
16029 <description>Filter bits
</description>
16030 <bitOffset>16</bitOffset>
16031 <bitWidth>1</bitWidth>
16035 <description>Filter bits
</description>
16036 <bitOffset>17</bitOffset>
16037 <bitWidth>1</bitWidth>
16041 <description>Filter bits
</description>
16042 <bitOffset>18</bitOffset>
16043 <bitWidth>1</bitWidth>
16047 <description>Filter bits
</description>
16048 <bitOffset>19</bitOffset>
16049 <bitWidth>1</bitWidth>
16053 <description>Filter bits
</description>
16054 <bitOffset>20</bitOffset>
16055 <bitWidth>1</bitWidth>
16059 <description>Filter bits
</description>
16060 <bitOffset>21</bitOffset>
16061 <bitWidth>1</bitWidth>
16065 <description>Filter bits
</description>
16066 <bitOffset>22</bitOffset>
16067 <bitWidth>1</bitWidth>
16071 <description>Filter bits
</description>
16072 <bitOffset>23</bitOffset>
16073 <bitWidth>1</bitWidth>
16077 <description>Filter bits
</description>
16078 <bitOffset>24</bitOffset>
16079 <bitWidth>1</bitWidth>
16083 <description>Filter bits
</description>
16084 <bitOffset>25</bitOffset>
16085 <bitWidth>1</bitWidth>
16089 <description>Filter bits
</description>
16090 <bitOffset>26</bitOffset>
16091 <bitWidth>1</bitWidth>
16095 <description>Filter bits
</description>
16096 <bitOffset>27</bitOffset>
16097 <bitWidth>1</bitWidth>
16101 <description>Filter bits
</description>
16102 <bitOffset>28</bitOffset>
16103 <bitWidth>1</bitWidth>
16107 <description>Filter bits
</description>
16108 <bitOffset>29</bitOffset>
16109 <bitWidth>1</bitWidth>
16113 <description>Filter bits
</description>
16114 <bitOffset>30</bitOffset>
16115 <bitWidth>1</bitWidth>
16119 <description>Filter bits
</description>
16120 <bitOffset>31</bitOffset>
16121 <bitWidth>1</bitWidth>
16127 <displayName>F2R2
</displayName>
16128 <description>Filter bank
2 register
2</description>
16129 <addressOffset>0x254</addressOffset>
16131 <access>read-write
</access>
16132 <resetValue>0x00000000</resetValue>
16136 <description>Filter bits
</description>
16137 <bitOffset>0</bitOffset>
16138 <bitWidth>1</bitWidth>
16142 <description>Filter bits
</description>
16143 <bitOffset>1</bitOffset>
16144 <bitWidth>1</bitWidth>
16148 <description>Filter bits
</description>
16149 <bitOffset>2</bitOffset>
16150 <bitWidth>1</bitWidth>
16154 <description>Filter bits
</description>
16155 <bitOffset>3</bitOffset>
16156 <bitWidth>1</bitWidth>
16160 <description>Filter bits
</description>
16161 <bitOffset>4</bitOffset>
16162 <bitWidth>1</bitWidth>
16166 <description>Filter bits
</description>
16167 <bitOffset>5</bitOffset>
16168 <bitWidth>1</bitWidth>
16172 <description>Filter bits
</description>
16173 <bitOffset>6</bitOffset>
16174 <bitWidth>1</bitWidth>
16178 <description>Filter bits
</description>
16179 <bitOffset>7</bitOffset>
16180 <bitWidth>1</bitWidth>
16184 <description>Filter bits
</description>
16185 <bitOffset>8</bitOffset>
16186 <bitWidth>1</bitWidth>
16190 <description>Filter bits
</description>
16191 <bitOffset>9</bitOffset>
16192 <bitWidth>1</bitWidth>
16196 <description>Filter bits
</description>
16197 <bitOffset>10</bitOffset>
16198 <bitWidth>1</bitWidth>
16202 <description>Filter bits
</description>
16203 <bitOffset>11</bitOffset>
16204 <bitWidth>1</bitWidth>
16208 <description>Filter bits
</description>
16209 <bitOffset>12</bitOffset>
16210 <bitWidth>1</bitWidth>
16214 <description>Filter bits
</description>
16215 <bitOffset>13</bitOffset>
16216 <bitWidth>1</bitWidth>
16220 <description>Filter bits
</description>
16221 <bitOffset>14</bitOffset>
16222 <bitWidth>1</bitWidth>
16226 <description>Filter bits
</description>
16227 <bitOffset>15</bitOffset>
16228 <bitWidth>1</bitWidth>
16232 <description>Filter bits
</description>
16233 <bitOffset>16</bitOffset>
16234 <bitWidth>1</bitWidth>
16238 <description>Filter bits
</description>
16239 <bitOffset>17</bitOffset>
16240 <bitWidth>1</bitWidth>
16244 <description>Filter bits
</description>
16245 <bitOffset>18</bitOffset>
16246 <bitWidth>1</bitWidth>
16250 <description>Filter bits
</description>
16251 <bitOffset>19</bitOffset>
16252 <bitWidth>1</bitWidth>
16256 <description>Filter bits
</description>
16257 <bitOffset>20</bitOffset>
16258 <bitWidth>1</bitWidth>
16262 <description>Filter bits
</description>
16263 <bitOffset>21</bitOffset>
16264 <bitWidth>1</bitWidth>
16268 <description>Filter bits
</description>
16269 <bitOffset>22</bitOffset>
16270 <bitWidth>1</bitWidth>
16274 <description>Filter bits
</description>
16275 <bitOffset>23</bitOffset>
16276 <bitWidth>1</bitWidth>
16280 <description>Filter bits
</description>
16281 <bitOffset>24</bitOffset>
16282 <bitWidth>1</bitWidth>
16286 <description>Filter bits
</description>
16287 <bitOffset>25</bitOffset>
16288 <bitWidth>1</bitWidth>
16292 <description>Filter bits
</description>
16293 <bitOffset>26</bitOffset>
16294 <bitWidth>1</bitWidth>
16298 <description>Filter bits
</description>
16299 <bitOffset>27</bitOffset>
16300 <bitWidth>1</bitWidth>
16304 <description>Filter bits
</description>
16305 <bitOffset>28</bitOffset>
16306 <bitWidth>1</bitWidth>
16310 <description>Filter bits
</description>
16311 <bitOffset>29</bitOffset>
16312 <bitWidth>1</bitWidth>
16316 <description>Filter bits
</description>
16317 <bitOffset>30</bitOffset>
16318 <bitWidth>1</bitWidth>
16322 <description>Filter bits
</description>
16323 <bitOffset>31</bitOffset>
16324 <bitWidth>1</bitWidth>
16330 <displayName>F3R1
</displayName>
16331 <description>Filter bank
3 register
1</description>
16332 <addressOffset>0x258</addressOffset>
16334 <access>read-write
</access>
16335 <resetValue>0x00000000</resetValue>
16339 <description>Filter bits
</description>
16340 <bitOffset>0</bitOffset>
16341 <bitWidth>1</bitWidth>
16345 <description>Filter bits
</description>
16346 <bitOffset>1</bitOffset>
16347 <bitWidth>1</bitWidth>
16351 <description>Filter bits
</description>
16352 <bitOffset>2</bitOffset>
16353 <bitWidth>1</bitWidth>
16357 <description>Filter bits
</description>
16358 <bitOffset>3</bitOffset>
16359 <bitWidth>1</bitWidth>
16363 <description>Filter bits
</description>
16364 <bitOffset>4</bitOffset>
16365 <bitWidth>1</bitWidth>
16369 <description>Filter bits
</description>
16370 <bitOffset>5</bitOffset>
16371 <bitWidth>1</bitWidth>
16375 <description>Filter bits
</description>
16376 <bitOffset>6</bitOffset>
16377 <bitWidth>1</bitWidth>
16381 <description>Filter bits
</description>
16382 <bitOffset>7</bitOffset>
16383 <bitWidth>1</bitWidth>
16387 <description>Filter bits
</description>
16388 <bitOffset>8</bitOffset>
16389 <bitWidth>1</bitWidth>
16393 <description>Filter bits
</description>
16394 <bitOffset>9</bitOffset>
16395 <bitWidth>1</bitWidth>
16399 <description>Filter bits
</description>
16400 <bitOffset>10</bitOffset>
16401 <bitWidth>1</bitWidth>
16405 <description>Filter bits
</description>
16406 <bitOffset>11</bitOffset>
16407 <bitWidth>1</bitWidth>
16411 <description>Filter bits
</description>
16412 <bitOffset>12</bitOffset>
16413 <bitWidth>1</bitWidth>
16417 <description>Filter bits
</description>
16418 <bitOffset>13</bitOffset>
16419 <bitWidth>1</bitWidth>
16423 <description>Filter bits
</description>
16424 <bitOffset>14</bitOffset>
16425 <bitWidth>1</bitWidth>
16429 <description>Filter bits
</description>
16430 <bitOffset>15</bitOffset>
16431 <bitWidth>1</bitWidth>
16435 <description>Filter bits
</description>
16436 <bitOffset>16</bitOffset>
16437 <bitWidth>1</bitWidth>
16441 <description>Filter bits
</description>
16442 <bitOffset>17</bitOffset>
16443 <bitWidth>1</bitWidth>
16447 <description>Filter bits
</description>
16448 <bitOffset>18</bitOffset>
16449 <bitWidth>1</bitWidth>
16453 <description>Filter bits
</description>
16454 <bitOffset>19</bitOffset>
16455 <bitWidth>1</bitWidth>
16459 <description>Filter bits
</description>
16460 <bitOffset>20</bitOffset>
16461 <bitWidth>1</bitWidth>
16465 <description>Filter bits
</description>
16466 <bitOffset>21</bitOffset>
16467 <bitWidth>1</bitWidth>
16471 <description>Filter bits
</description>
16472 <bitOffset>22</bitOffset>
16473 <bitWidth>1</bitWidth>
16477 <description>Filter bits
</description>
16478 <bitOffset>23</bitOffset>
16479 <bitWidth>1</bitWidth>
16483 <description>Filter bits
</description>
16484 <bitOffset>24</bitOffset>
16485 <bitWidth>1</bitWidth>
16489 <description>Filter bits
</description>
16490 <bitOffset>25</bitOffset>
16491 <bitWidth>1</bitWidth>
16495 <description>Filter bits
</description>
16496 <bitOffset>26</bitOffset>
16497 <bitWidth>1</bitWidth>
16501 <description>Filter bits
</description>
16502 <bitOffset>27</bitOffset>
16503 <bitWidth>1</bitWidth>
16507 <description>Filter bits
</description>
16508 <bitOffset>28</bitOffset>
16509 <bitWidth>1</bitWidth>
16513 <description>Filter bits
</description>
16514 <bitOffset>29</bitOffset>
16515 <bitWidth>1</bitWidth>
16519 <description>Filter bits
</description>
16520 <bitOffset>30</bitOffset>
16521 <bitWidth>1</bitWidth>
16525 <description>Filter bits
</description>
16526 <bitOffset>31</bitOffset>
16527 <bitWidth>1</bitWidth>
16533 <displayName>F3R2
</displayName>
16534 <description>Filter bank
3 register
2</description>
16535 <addressOffset>0x25C</addressOffset>
16537 <access>read-write
</access>
16538 <resetValue>0x00000000</resetValue>
16542 <description>Filter bits
</description>
16543 <bitOffset>0</bitOffset>
16544 <bitWidth>1</bitWidth>
16548 <description>Filter bits
</description>
16549 <bitOffset>1</bitOffset>
16550 <bitWidth>1</bitWidth>
16554 <description>Filter bits
</description>
16555 <bitOffset>2</bitOffset>
16556 <bitWidth>1</bitWidth>
16560 <description>Filter bits
</description>
16561 <bitOffset>3</bitOffset>
16562 <bitWidth>1</bitWidth>
16566 <description>Filter bits
</description>
16567 <bitOffset>4</bitOffset>
16568 <bitWidth>1</bitWidth>
16572 <description>Filter bits
</description>
16573 <bitOffset>5</bitOffset>
16574 <bitWidth>1</bitWidth>
16578 <description>Filter bits
</description>
16579 <bitOffset>6</bitOffset>
16580 <bitWidth>1</bitWidth>
16584 <description>Filter bits
</description>
16585 <bitOffset>7</bitOffset>
16586 <bitWidth>1</bitWidth>
16590 <description>Filter bits
</description>
16591 <bitOffset>8</bitOffset>
16592 <bitWidth>1</bitWidth>
16596 <description>Filter bits
</description>
16597 <bitOffset>9</bitOffset>
16598 <bitWidth>1</bitWidth>
16602 <description>Filter bits
</description>
16603 <bitOffset>10</bitOffset>
16604 <bitWidth>1</bitWidth>
16608 <description>Filter bits
</description>
16609 <bitOffset>11</bitOffset>
16610 <bitWidth>1</bitWidth>
16614 <description>Filter bits
</description>
16615 <bitOffset>12</bitOffset>
16616 <bitWidth>1</bitWidth>
16620 <description>Filter bits
</description>
16621 <bitOffset>13</bitOffset>
16622 <bitWidth>1</bitWidth>
16626 <description>Filter bits
</description>
16627 <bitOffset>14</bitOffset>
16628 <bitWidth>1</bitWidth>
16632 <description>Filter bits
</description>
16633 <bitOffset>15</bitOffset>
16634 <bitWidth>1</bitWidth>
16638 <description>Filter bits
</description>
16639 <bitOffset>16</bitOffset>
16640 <bitWidth>1</bitWidth>
16644 <description>Filter bits
</description>
16645 <bitOffset>17</bitOffset>
16646 <bitWidth>1</bitWidth>
16650 <description>Filter bits
</description>
16651 <bitOffset>18</bitOffset>
16652 <bitWidth>1</bitWidth>
16656 <description>Filter bits
</description>
16657 <bitOffset>19</bitOffset>
16658 <bitWidth>1</bitWidth>
16662 <description>Filter bits
</description>
16663 <bitOffset>20</bitOffset>
16664 <bitWidth>1</bitWidth>
16668 <description>Filter bits
</description>
16669 <bitOffset>21</bitOffset>
16670 <bitWidth>1</bitWidth>
16674 <description>Filter bits
</description>
16675 <bitOffset>22</bitOffset>
16676 <bitWidth>1</bitWidth>
16680 <description>Filter bits
</description>
16681 <bitOffset>23</bitOffset>
16682 <bitWidth>1</bitWidth>
16686 <description>Filter bits
</description>
16687 <bitOffset>24</bitOffset>
16688 <bitWidth>1</bitWidth>
16692 <description>Filter bits
</description>
16693 <bitOffset>25</bitOffset>
16694 <bitWidth>1</bitWidth>
16698 <description>Filter bits
</description>
16699 <bitOffset>26</bitOffset>
16700 <bitWidth>1</bitWidth>
16704 <description>Filter bits
</description>
16705 <bitOffset>27</bitOffset>
16706 <bitWidth>1</bitWidth>
16710 <description>Filter bits
</description>
16711 <bitOffset>28</bitOffset>
16712 <bitWidth>1</bitWidth>
16716 <description>Filter bits
</description>
16717 <bitOffset>29</bitOffset>
16718 <bitWidth>1</bitWidth>
16722 <description>Filter bits
</description>
16723 <bitOffset>30</bitOffset>
16724 <bitWidth>1</bitWidth>
16728 <description>Filter bits
</description>
16729 <bitOffset>31</bitOffset>
16730 <bitWidth>1</bitWidth>
16736 <displayName>F4R1
</displayName>
16737 <description>Filter bank
4 register
1</description>
16738 <addressOffset>0x260</addressOffset>
16740 <access>read-write
</access>
16741 <resetValue>0x00000000</resetValue>
16745 <description>Filter bits
</description>
16746 <bitOffset>0</bitOffset>
16747 <bitWidth>1</bitWidth>
16751 <description>Filter bits
</description>
16752 <bitOffset>1</bitOffset>
16753 <bitWidth>1</bitWidth>
16757 <description>Filter bits
</description>
16758 <bitOffset>2</bitOffset>
16759 <bitWidth>1</bitWidth>
16763 <description>Filter bits
</description>
16764 <bitOffset>3</bitOffset>
16765 <bitWidth>1</bitWidth>
16769 <description>Filter bits
</description>
16770 <bitOffset>4</bitOffset>
16771 <bitWidth>1</bitWidth>
16775 <description>Filter bits
</description>
16776 <bitOffset>5</bitOffset>
16777 <bitWidth>1</bitWidth>
16781 <description>Filter bits
</description>
16782 <bitOffset>6</bitOffset>
16783 <bitWidth>1</bitWidth>
16787 <description>Filter bits
</description>
16788 <bitOffset>7</bitOffset>
16789 <bitWidth>1</bitWidth>
16793 <description>Filter bits
</description>
16794 <bitOffset>8</bitOffset>
16795 <bitWidth>1</bitWidth>
16799 <description>Filter bits
</description>
16800 <bitOffset>9</bitOffset>
16801 <bitWidth>1</bitWidth>
16805 <description>Filter bits
</description>
16806 <bitOffset>10</bitOffset>
16807 <bitWidth>1</bitWidth>
16811 <description>Filter bits
</description>
16812 <bitOffset>11</bitOffset>
16813 <bitWidth>1</bitWidth>
16817 <description>Filter bits
</description>
16818 <bitOffset>12</bitOffset>
16819 <bitWidth>1</bitWidth>
16823 <description>Filter bits
</description>
16824 <bitOffset>13</bitOffset>
16825 <bitWidth>1</bitWidth>
16829 <description>Filter bits
</description>
16830 <bitOffset>14</bitOffset>
16831 <bitWidth>1</bitWidth>
16835 <description>Filter bits
</description>
16836 <bitOffset>15</bitOffset>
16837 <bitWidth>1</bitWidth>
16841 <description>Filter bits
</description>
16842 <bitOffset>16</bitOffset>
16843 <bitWidth>1</bitWidth>
16847 <description>Filter bits
</description>
16848 <bitOffset>17</bitOffset>
16849 <bitWidth>1</bitWidth>
16853 <description>Filter bits
</description>
16854 <bitOffset>18</bitOffset>
16855 <bitWidth>1</bitWidth>
16859 <description>Filter bits
</description>
16860 <bitOffset>19</bitOffset>
16861 <bitWidth>1</bitWidth>
16865 <description>Filter bits
</description>
16866 <bitOffset>20</bitOffset>
16867 <bitWidth>1</bitWidth>
16871 <description>Filter bits
</description>
16872 <bitOffset>21</bitOffset>
16873 <bitWidth>1</bitWidth>
16877 <description>Filter bits
</description>
16878 <bitOffset>22</bitOffset>
16879 <bitWidth>1</bitWidth>
16883 <description>Filter bits
</description>
16884 <bitOffset>23</bitOffset>
16885 <bitWidth>1</bitWidth>
16889 <description>Filter bits
</description>
16890 <bitOffset>24</bitOffset>
16891 <bitWidth>1</bitWidth>
16895 <description>Filter bits
</description>
16896 <bitOffset>25</bitOffset>
16897 <bitWidth>1</bitWidth>
16901 <description>Filter bits
</description>
16902 <bitOffset>26</bitOffset>
16903 <bitWidth>1</bitWidth>
16907 <description>Filter bits
</description>
16908 <bitOffset>27</bitOffset>
16909 <bitWidth>1</bitWidth>
16913 <description>Filter bits
</description>
16914 <bitOffset>28</bitOffset>
16915 <bitWidth>1</bitWidth>
16919 <description>Filter bits
</description>
16920 <bitOffset>29</bitOffset>
16921 <bitWidth>1</bitWidth>
16925 <description>Filter bits
</description>
16926 <bitOffset>30</bitOffset>
16927 <bitWidth>1</bitWidth>
16931 <description>Filter bits
</description>
16932 <bitOffset>31</bitOffset>
16933 <bitWidth>1</bitWidth>
16939 <displayName>F4R2
</displayName>
16940 <description>Filter bank
4 register
2</description>
16941 <addressOffset>0x264</addressOffset>
16943 <access>read-write
</access>
16944 <resetValue>0x00000000</resetValue>
16948 <description>Filter bits
</description>
16949 <bitOffset>0</bitOffset>
16950 <bitWidth>1</bitWidth>
16954 <description>Filter bits
</description>
16955 <bitOffset>1</bitOffset>
16956 <bitWidth>1</bitWidth>
16960 <description>Filter bits
</description>
16961 <bitOffset>2</bitOffset>
16962 <bitWidth>1</bitWidth>
16966 <description>Filter bits
</description>
16967 <bitOffset>3</bitOffset>
16968 <bitWidth>1</bitWidth>
16972 <description>Filter bits
</description>
16973 <bitOffset>4</bitOffset>
16974 <bitWidth>1</bitWidth>
16978 <description>Filter bits
</description>
16979 <bitOffset>5</bitOffset>
16980 <bitWidth>1</bitWidth>
16984 <description>Filter bits
</description>
16985 <bitOffset>6</bitOffset>
16986 <bitWidth>1</bitWidth>
16990 <description>Filter bits
</description>
16991 <bitOffset>7</bitOffset>
16992 <bitWidth>1</bitWidth>
16996 <description>Filter bits
</description>
16997 <bitOffset>8</bitOffset>
16998 <bitWidth>1</bitWidth>
17002 <description>Filter bits
</description>
17003 <bitOffset>9</bitOffset>
17004 <bitWidth>1</bitWidth>
17008 <description>Filter bits
</description>
17009 <bitOffset>10</bitOffset>
17010 <bitWidth>1</bitWidth>
17014 <description>Filter bits
</description>
17015 <bitOffset>11</bitOffset>
17016 <bitWidth>1</bitWidth>
17020 <description>Filter bits
</description>
17021 <bitOffset>12</bitOffset>
17022 <bitWidth>1</bitWidth>
17026 <description>Filter bits
</description>
17027 <bitOffset>13</bitOffset>
17028 <bitWidth>1</bitWidth>
17032 <description>Filter bits
</description>
17033 <bitOffset>14</bitOffset>
17034 <bitWidth>1</bitWidth>
17038 <description>Filter bits
</description>
17039 <bitOffset>15</bitOffset>
17040 <bitWidth>1</bitWidth>
17044 <description>Filter bits
</description>
17045 <bitOffset>16</bitOffset>
17046 <bitWidth>1</bitWidth>
17050 <description>Filter bits
</description>
17051 <bitOffset>17</bitOffset>
17052 <bitWidth>1</bitWidth>
17056 <description>Filter bits
</description>
17057 <bitOffset>18</bitOffset>
17058 <bitWidth>1</bitWidth>
17062 <description>Filter bits
</description>
17063 <bitOffset>19</bitOffset>
17064 <bitWidth>1</bitWidth>
17068 <description>Filter bits
</description>
17069 <bitOffset>20</bitOffset>
17070 <bitWidth>1</bitWidth>
17074 <description>Filter bits
</description>
17075 <bitOffset>21</bitOffset>
17076 <bitWidth>1</bitWidth>
17080 <description>Filter bits
</description>
17081 <bitOffset>22</bitOffset>
17082 <bitWidth>1</bitWidth>
17086 <description>Filter bits
</description>
17087 <bitOffset>23</bitOffset>
17088 <bitWidth>1</bitWidth>
17092 <description>Filter bits
</description>
17093 <bitOffset>24</bitOffset>
17094 <bitWidth>1</bitWidth>
17098 <description>Filter bits
</description>
17099 <bitOffset>25</bitOffset>
17100 <bitWidth>1</bitWidth>
17104 <description>Filter bits
</description>
17105 <bitOffset>26</bitOffset>
17106 <bitWidth>1</bitWidth>
17110 <description>Filter bits
</description>
17111 <bitOffset>27</bitOffset>
17112 <bitWidth>1</bitWidth>
17116 <description>Filter bits
</description>
17117 <bitOffset>28</bitOffset>
17118 <bitWidth>1</bitWidth>
17122 <description>Filter bits
</description>
17123 <bitOffset>29</bitOffset>
17124 <bitWidth>1</bitWidth>
17128 <description>Filter bits
</description>
17129 <bitOffset>30</bitOffset>
17130 <bitWidth>1</bitWidth>
17134 <description>Filter bits
</description>
17135 <bitOffset>31</bitOffset>
17136 <bitWidth>1</bitWidth>
17142 <displayName>F5R1
</displayName>
17143 <description>Filter bank
5 register
1</description>
17144 <addressOffset>0x268</addressOffset>
17146 <access>read-write
</access>
17147 <resetValue>0x00000000</resetValue>
17151 <description>Filter bits
</description>
17152 <bitOffset>0</bitOffset>
17153 <bitWidth>1</bitWidth>
17157 <description>Filter bits
</description>
17158 <bitOffset>1</bitOffset>
17159 <bitWidth>1</bitWidth>
17163 <description>Filter bits
</description>
17164 <bitOffset>2</bitOffset>
17165 <bitWidth>1</bitWidth>
17169 <description>Filter bits
</description>
17170 <bitOffset>3</bitOffset>
17171 <bitWidth>1</bitWidth>
17175 <description>Filter bits
</description>
17176 <bitOffset>4</bitOffset>
17177 <bitWidth>1</bitWidth>
17181 <description>Filter bits
</description>
17182 <bitOffset>5</bitOffset>
17183 <bitWidth>1</bitWidth>
17187 <description>Filter bits
</description>
17188 <bitOffset>6</bitOffset>
17189 <bitWidth>1</bitWidth>
17193 <description>Filter bits
</description>
17194 <bitOffset>7</bitOffset>
17195 <bitWidth>1</bitWidth>
17199 <description>Filter bits
</description>
17200 <bitOffset>8</bitOffset>
17201 <bitWidth>1</bitWidth>
17205 <description>Filter bits
</description>
17206 <bitOffset>9</bitOffset>
17207 <bitWidth>1</bitWidth>
17211 <description>Filter bits
</description>
17212 <bitOffset>10</bitOffset>
17213 <bitWidth>1</bitWidth>
17217 <description>Filter bits
</description>
17218 <bitOffset>11</bitOffset>
17219 <bitWidth>1</bitWidth>
17223 <description>Filter bits
</description>
17224 <bitOffset>12</bitOffset>
17225 <bitWidth>1</bitWidth>
17229 <description>Filter bits
</description>
17230 <bitOffset>13</bitOffset>
17231 <bitWidth>1</bitWidth>
17235 <description>Filter bits
</description>
17236 <bitOffset>14</bitOffset>
17237 <bitWidth>1</bitWidth>
17241 <description>Filter bits
</description>
17242 <bitOffset>15</bitOffset>
17243 <bitWidth>1</bitWidth>
17247 <description>Filter bits
</description>
17248 <bitOffset>16</bitOffset>
17249 <bitWidth>1</bitWidth>
17253 <description>Filter bits
</description>
17254 <bitOffset>17</bitOffset>
17255 <bitWidth>1</bitWidth>
17259 <description>Filter bits
</description>
17260 <bitOffset>18</bitOffset>
17261 <bitWidth>1</bitWidth>
17265 <description>Filter bits
</description>
17266 <bitOffset>19</bitOffset>
17267 <bitWidth>1</bitWidth>
17271 <description>Filter bits
</description>
17272 <bitOffset>20</bitOffset>
17273 <bitWidth>1</bitWidth>
17277 <description>Filter bits
</description>
17278 <bitOffset>21</bitOffset>
17279 <bitWidth>1</bitWidth>
17283 <description>Filter bits
</description>
17284 <bitOffset>22</bitOffset>
17285 <bitWidth>1</bitWidth>
17289 <description>Filter bits
</description>
17290 <bitOffset>23</bitOffset>
17291 <bitWidth>1</bitWidth>
17295 <description>Filter bits
</description>
17296 <bitOffset>24</bitOffset>
17297 <bitWidth>1</bitWidth>
17301 <description>Filter bits
</description>
17302 <bitOffset>25</bitOffset>
17303 <bitWidth>1</bitWidth>
17307 <description>Filter bits
</description>
17308 <bitOffset>26</bitOffset>
17309 <bitWidth>1</bitWidth>
17313 <description>Filter bits
</description>
17314 <bitOffset>27</bitOffset>
17315 <bitWidth>1</bitWidth>
17319 <description>Filter bits
</description>
17320 <bitOffset>28</bitOffset>
17321 <bitWidth>1</bitWidth>
17325 <description>Filter bits
</description>
17326 <bitOffset>29</bitOffset>
17327 <bitWidth>1</bitWidth>
17331 <description>Filter bits
</description>
17332 <bitOffset>30</bitOffset>
17333 <bitWidth>1</bitWidth>
17337 <description>Filter bits
</description>
17338 <bitOffset>31</bitOffset>
17339 <bitWidth>1</bitWidth>
17345 <displayName>F5R2
</displayName>
17346 <description>Filter bank
5 register
2</description>
17347 <addressOffset>0x26C</addressOffset>
17349 <access>read-write
</access>
17350 <resetValue>0x00000000</resetValue>
17354 <description>Filter bits
</description>
17355 <bitOffset>0</bitOffset>
17356 <bitWidth>1</bitWidth>
17360 <description>Filter bits
</description>
17361 <bitOffset>1</bitOffset>
17362 <bitWidth>1</bitWidth>
17366 <description>Filter bits
</description>
17367 <bitOffset>2</bitOffset>
17368 <bitWidth>1</bitWidth>
17372 <description>Filter bits
</description>
17373 <bitOffset>3</bitOffset>
17374 <bitWidth>1</bitWidth>
17378 <description>Filter bits
</description>
17379 <bitOffset>4</bitOffset>
17380 <bitWidth>1</bitWidth>
17384 <description>Filter bits
</description>
17385 <bitOffset>5</bitOffset>
17386 <bitWidth>1</bitWidth>
17390 <description>Filter bits
</description>
17391 <bitOffset>6</bitOffset>
17392 <bitWidth>1</bitWidth>
17396 <description>Filter bits
</description>
17397 <bitOffset>7</bitOffset>
17398 <bitWidth>1</bitWidth>
17402 <description>Filter bits
</description>
17403 <bitOffset>8</bitOffset>
17404 <bitWidth>1</bitWidth>
17408 <description>Filter bits
</description>
17409 <bitOffset>9</bitOffset>
17410 <bitWidth>1</bitWidth>
17414 <description>Filter bits
</description>
17415 <bitOffset>10</bitOffset>
17416 <bitWidth>1</bitWidth>
17420 <description>Filter bits
</description>
17421 <bitOffset>11</bitOffset>
17422 <bitWidth>1</bitWidth>
17426 <description>Filter bits
</description>
17427 <bitOffset>12</bitOffset>
17428 <bitWidth>1</bitWidth>
17432 <description>Filter bits
</description>
17433 <bitOffset>13</bitOffset>
17434 <bitWidth>1</bitWidth>
17438 <description>Filter bits
</description>
17439 <bitOffset>14</bitOffset>
17440 <bitWidth>1</bitWidth>
17444 <description>Filter bits
</description>
17445 <bitOffset>15</bitOffset>
17446 <bitWidth>1</bitWidth>
17450 <description>Filter bits
</description>
17451 <bitOffset>16</bitOffset>
17452 <bitWidth>1</bitWidth>
17456 <description>Filter bits
</description>
17457 <bitOffset>17</bitOffset>
17458 <bitWidth>1</bitWidth>
17462 <description>Filter bits
</description>
17463 <bitOffset>18</bitOffset>
17464 <bitWidth>1</bitWidth>
17468 <description>Filter bits
</description>
17469 <bitOffset>19</bitOffset>
17470 <bitWidth>1</bitWidth>
17474 <description>Filter bits
</description>
17475 <bitOffset>20</bitOffset>
17476 <bitWidth>1</bitWidth>
17480 <description>Filter bits
</description>
17481 <bitOffset>21</bitOffset>
17482 <bitWidth>1</bitWidth>
17486 <description>Filter bits
</description>
17487 <bitOffset>22</bitOffset>
17488 <bitWidth>1</bitWidth>
17492 <description>Filter bits
</description>
17493 <bitOffset>23</bitOffset>
17494 <bitWidth>1</bitWidth>
17498 <description>Filter bits
</description>
17499 <bitOffset>24</bitOffset>
17500 <bitWidth>1</bitWidth>
17504 <description>Filter bits
</description>
17505 <bitOffset>25</bitOffset>
17506 <bitWidth>1</bitWidth>
17510 <description>Filter bits
</description>
17511 <bitOffset>26</bitOffset>
17512 <bitWidth>1</bitWidth>
17516 <description>Filter bits
</description>
17517 <bitOffset>27</bitOffset>
17518 <bitWidth>1</bitWidth>
17522 <description>Filter bits
</description>
17523 <bitOffset>28</bitOffset>
17524 <bitWidth>1</bitWidth>
17528 <description>Filter bits
</description>
17529 <bitOffset>29</bitOffset>
17530 <bitWidth>1</bitWidth>
17534 <description>Filter bits
</description>
17535 <bitOffset>30</bitOffset>
17536 <bitWidth>1</bitWidth>
17540 <description>Filter bits
</description>
17541 <bitOffset>31</bitOffset>
17542 <bitWidth>1</bitWidth>
17548 <displayName>F6R1
</displayName>
17549 <description>Filter bank
6 register
1</description>
17550 <addressOffset>0x270</addressOffset>
17552 <access>read-write
</access>
17553 <resetValue>0x00000000</resetValue>
17557 <description>Filter bits
</description>
17558 <bitOffset>0</bitOffset>
17559 <bitWidth>1</bitWidth>
17563 <description>Filter bits
</description>
17564 <bitOffset>1</bitOffset>
17565 <bitWidth>1</bitWidth>
17569 <description>Filter bits
</description>
17570 <bitOffset>2</bitOffset>
17571 <bitWidth>1</bitWidth>
17575 <description>Filter bits
</description>
17576 <bitOffset>3</bitOffset>
17577 <bitWidth>1</bitWidth>
17581 <description>Filter bits
</description>
17582 <bitOffset>4</bitOffset>
17583 <bitWidth>1</bitWidth>
17587 <description>Filter bits
</description>
17588 <bitOffset>5</bitOffset>
17589 <bitWidth>1</bitWidth>
17593 <description>Filter bits
</description>
17594 <bitOffset>6</bitOffset>
17595 <bitWidth>1</bitWidth>
17599 <description>Filter bits
</description>
17600 <bitOffset>7</bitOffset>
17601 <bitWidth>1</bitWidth>
17605 <description>Filter bits
</description>
17606 <bitOffset>8</bitOffset>
17607 <bitWidth>1</bitWidth>
17611 <description>Filter bits
</description>
17612 <bitOffset>9</bitOffset>
17613 <bitWidth>1</bitWidth>
17617 <description>Filter bits
</description>
17618 <bitOffset>10</bitOffset>
17619 <bitWidth>1</bitWidth>
17623 <description>Filter bits
</description>
17624 <bitOffset>11</bitOffset>
17625 <bitWidth>1</bitWidth>
17629 <description>Filter bits
</description>
17630 <bitOffset>12</bitOffset>
17631 <bitWidth>1</bitWidth>
17635 <description>Filter bits
</description>
17636 <bitOffset>13</bitOffset>
17637 <bitWidth>1</bitWidth>
17641 <description>Filter bits
</description>
17642 <bitOffset>14</bitOffset>
17643 <bitWidth>1</bitWidth>
17647 <description>Filter bits
</description>
17648 <bitOffset>15</bitOffset>
17649 <bitWidth>1</bitWidth>
17653 <description>Filter bits
</description>
17654 <bitOffset>16</bitOffset>
17655 <bitWidth>1</bitWidth>
17659 <description>Filter bits
</description>
17660 <bitOffset>17</bitOffset>
17661 <bitWidth>1</bitWidth>
17665 <description>Filter bits
</description>
17666 <bitOffset>18</bitOffset>
17667 <bitWidth>1</bitWidth>
17671 <description>Filter bits
</description>
17672 <bitOffset>19</bitOffset>
17673 <bitWidth>1</bitWidth>
17677 <description>Filter bits
</description>
17678 <bitOffset>20</bitOffset>
17679 <bitWidth>1</bitWidth>
17683 <description>Filter bits
</description>
17684 <bitOffset>21</bitOffset>
17685 <bitWidth>1</bitWidth>
17689 <description>Filter bits
</description>
17690 <bitOffset>22</bitOffset>
17691 <bitWidth>1</bitWidth>
17695 <description>Filter bits
</description>
17696 <bitOffset>23</bitOffset>
17697 <bitWidth>1</bitWidth>
17701 <description>Filter bits
</description>
17702 <bitOffset>24</bitOffset>
17703 <bitWidth>1</bitWidth>
17707 <description>Filter bits
</description>
17708 <bitOffset>25</bitOffset>
17709 <bitWidth>1</bitWidth>
17713 <description>Filter bits
</description>
17714 <bitOffset>26</bitOffset>
17715 <bitWidth>1</bitWidth>
17719 <description>Filter bits
</description>
17720 <bitOffset>27</bitOffset>
17721 <bitWidth>1</bitWidth>
17725 <description>Filter bits
</description>
17726 <bitOffset>28</bitOffset>
17727 <bitWidth>1</bitWidth>
17731 <description>Filter bits
</description>
17732 <bitOffset>29</bitOffset>
17733 <bitWidth>1</bitWidth>
17737 <description>Filter bits
</description>
17738 <bitOffset>30</bitOffset>
17739 <bitWidth>1</bitWidth>
17743 <description>Filter bits
</description>
17744 <bitOffset>31</bitOffset>
17745 <bitWidth>1</bitWidth>
17751 <displayName>F6R2
</displayName>
17752 <description>Filter bank
6 register
2</description>
17753 <addressOffset>0x274</addressOffset>
17755 <access>read-write
</access>
17756 <resetValue>0x00000000</resetValue>
17760 <description>Filter bits
</description>
17761 <bitOffset>0</bitOffset>
17762 <bitWidth>1</bitWidth>
17766 <description>Filter bits
</description>
17767 <bitOffset>1</bitOffset>
17768 <bitWidth>1</bitWidth>
17772 <description>Filter bits
</description>
17773 <bitOffset>2</bitOffset>
17774 <bitWidth>1</bitWidth>
17778 <description>Filter bits
</description>
17779 <bitOffset>3</bitOffset>
17780 <bitWidth>1</bitWidth>
17784 <description>Filter bits
</description>
17785 <bitOffset>4</bitOffset>
17786 <bitWidth>1</bitWidth>
17790 <description>Filter bits
</description>
17791 <bitOffset>5</bitOffset>
17792 <bitWidth>1</bitWidth>
17796 <description>Filter bits
</description>
17797 <bitOffset>6</bitOffset>
17798 <bitWidth>1</bitWidth>
17802 <description>Filter bits
</description>
17803 <bitOffset>7</bitOffset>
17804 <bitWidth>1</bitWidth>
17808 <description>Filter bits
</description>
17809 <bitOffset>8</bitOffset>
17810 <bitWidth>1</bitWidth>
17814 <description>Filter bits
</description>
17815 <bitOffset>9</bitOffset>
17816 <bitWidth>1</bitWidth>
17820 <description>Filter bits
</description>
17821 <bitOffset>10</bitOffset>
17822 <bitWidth>1</bitWidth>
17826 <description>Filter bits
</description>
17827 <bitOffset>11</bitOffset>
17828 <bitWidth>1</bitWidth>
17832 <description>Filter bits
</description>
17833 <bitOffset>12</bitOffset>
17834 <bitWidth>1</bitWidth>
17838 <description>Filter bits
</description>
17839 <bitOffset>13</bitOffset>
17840 <bitWidth>1</bitWidth>
17844 <description>Filter bits
</description>
17845 <bitOffset>14</bitOffset>
17846 <bitWidth>1</bitWidth>
17850 <description>Filter bits
</description>
17851 <bitOffset>15</bitOffset>
17852 <bitWidth>1</bitWidth>
17856 <description>Filter bits
</description>
17857 <bitOffset>16</bitOffset>
17858 <bitWidth>1</bitWidth>
17862 <description>Filter bits
</description>
17863 <bitOffset>17</bitOffset>
17864 <bitWidth>1</bitWidth>
17868 <description>Filter bits
</description>
17869 <bitOffset>18</bitOffset>
17870 <bitWidth>1</bitWidth>
17874 <description>Filter bits
</description>
17875 <bitOffset>19</bitOffset>
17876 <bitWidth>1</bitWidth>
17880 <description>Filter bits
</description>
17881 <bitOffset>20</bitOffset>
17882 <bitWidth>1</bitWidth>
17886 <description>Filter bits
</description>
17887 <bitOffset>21</bitOffset>
17888 <bitWidth>1</bitWidth>
17892 <description>Filter bits
</description>
17893 <bitOffset>22</bitOffset>
17894 <bitWidth>1</bitWidth>
17898 <description>Filter bits
</description>
17899 <bitOffset>23</bitOffset>
17900 <bitWidth>1</bitWidth>
17904 <description>Filter bits
</description>
17905 <bitOffset>24</bitOffset>
17906 <bitWidth>1</bitWidth>
17910 <description>Filter bits
</description>
17911 <bitOffset>25</bitOffset>
17912 <bitWidth>1</bitWidth>
17916 <description>Filter bits
</description>
17917 <bitOffset>26</bitOffset>
17918 <bitWidth>1</bitWidth>
17922 <description>Filter bits
</description>
17923 <bitOffset>27</bitOffset>
17924 <bitWidth>1</bitWidth>
17928 <description>Filter bits
</description>
17929 <bitOffset>28</bitOffset>
17930 <bitWidth>1</bitWidth>
17934 <description>Filter bits
</description>
17935 <bitOffset>29</bitOffset>
17936 <bitWidth>1</bitWidth>
17940 <description>Filter bits
</description>
17941 <bitOffset>30</bitOffset>
17942 <bitWidth>1</bitWidth>
17946 <description>Filter bits
</description>
17947 <bitOffset>31</bitOffset>
17948 <bitWidth>1</bitWidth>
17954 <displayName>F7R1
</displayName>
17955 <description>Filter bank
7 register
1</description>
17956 <addressOffset>0x278</addressOffset>
17958 <access>read-write
</access>
17959 <resetValue>0x00000000</resetValue>
17963 <description>Filter bits
</description>
17964 <bitOffset>0</bitOffset>
17965 <bitWidth>1</bitWidth>
17969 <description>Filter bits
</description>
17970 <bitOffset>1</bitOffset>
17971 <bitWidth>1</bitWidth>
17975 <description>Filter bits
</description>
17976 <bitOffset>2</bitOffset>
17977 <bitWidth>1</bitWidth>
17981 <description>Filter bits
</description>
17982 <bitOffset>3</bitOffset>
17983 <bitWidth>1</bitWidth>
17987 <description>Filter bits
</description>
17988 <bitOffset>4</bitOffset>
17989 <bitWidth>1</bitWidth>
17993 <description>Filter bits
</description>
17994 <bitOffset>5</bitOffset>
17995 <bitWidth>1</bitWidth>
17999 <description>Filter bits
</description>
18000 <bitOffset>6</bitOffset>
18001 <bitWidth>1</bitWidth>
18005 <description>Filter bits
</description>
18006 <bitOffset>7</bitOffset>
18007 <bitWidth>1</bitWidth>
18011 <description>Filter bits
</description>
18012 <bitOffset>8</bitOffset>
18013 <bitWidth>1</bitWidth>
18017 <description>Filter bits
</description>
18018 <bitOffset>9</bitOffset>
18019 <bitWidth>1</bitWidth>
18023 <description>Filter bits
</description>
18024 <bitOffset>10</bitOffset>
18025 <bitWidth>1</bitWidth>
18029 <description>Filter bits
</description>
18030 <bitOffset>11</bitOffset>
18031 <bitWidth>1</bitWidth>
18035 <description>Filter bits
</description>
18036 <bitOffset>12</bitOffset>
18037 <bitWidth>1</bitWidth>
18041 <description>Filter bits
</description>
18042 <bitOffset>13</bitOffset>
18043 <bitWidth>1</bitWidth>
18047 <description>Filter bits
</description>
18048 <bitOffset>14</bitOffset>
18049 <bitWidth>1</bitWidth>
18053 <description>Filter bits
</description>
18054 <bitOffset>15</bitOffset>
18055 <bitWidth>1</bitWidth>
18059 <description>Filter bits
</description>
18060 <bitOffset>16</bitOffset>
18061 <bitWidth>1</bitWidth>
18065 <description>Filter bits
</description>
18066 <bitOffset>17</bitOffset>
18067 <bitWidth>1</bitWidth>
18071 <description>Filter bits
</description>
18072 <bitOffset>18</bitOffset>
18073 <bitWidth>1</bitWidth>
18077 <description>Filter bits
</description>
18078 <bitOffset>19</bitOffset>
18079 <bitWidth>1</bitWidth>
18083 <description>Filter bits
</description>
18084 <bitOffset>20</bitOffset>
18085 <bitWidth>1</bitWidth>
18089 <description>Filter bits
</description>
18090 <bitOffset>21</bitOffset>
18091 <bitWidth>1</bitWidth>
18095 <description>Filter bits
</description>
18096 <bitOffset>22</bitOffset>
18097 <bitWidth>1</bitWidth>
18101 <description>Filter bits
</description>
18102 <bitOffset>23</bitOffset>
18103 <bitWidth>1</bitWidth>
18107 <description>Filter bits
</description>
18108 <bitOffset>24</bitOffset>
18109 <bitWidth>1</bitWidth>
18113 <description>Filter bits
</description>
18114 <bitOffset>25</bitOffset>
18115 <bitWidth>1</bitWidth>
18119 <description>Filter bits
</description>
18120 <bitOffset>26</bitOffset>
18121 <bitWidth>1</bitWidth>
18125 <description>Filter bits
</description>
18126 <bitOffset>27</bitOffset>
18127 <bitWidth>1</bitWidth>
18131 <description>Filter bits
</description>
18132 <bitOffset>28</bitOffset>
18133 <bitWidth>1</bitWidth>
18137 <description>Filter bits
</description>
18138 <bitOffset>29</bitOffset>
18139 <bitWidth>1</bitWidth>
18143 <description>Filter bits
</description>
18144 <bitOffset>30</bitOffset>
18145 <bitWidth>1</bitWidth>
18149 <description>Filter bits
</description>
18150 <bitOffset>31</bitOffset>
18151 <bitWidth>1</bitWidth>
18157 <displayName>F7R2
</displayName>
18158 <description>Filter bank
7 register
2</description>
18159 <addressOffset>0x27C</addressOffset>
18161 <access>read-write
</access>
18162 <resetValue>0x00000000</resetValue>
18166 <description>Filter bits
</description>
18167 <bitOffset>0</bitOffset>
18168 <bitWidth>1</bitWidth>
18172 <description>Filter bits
</description>
18173 <bitOffset>1</bitOffset>
18174 <bitWidth>1</bitWidth>
18178 <description>Filter bits
</description>
18179 <bitOffset>2</bitOffset>
18180 <bitWidth>1</bitWidth>
18184 <description>Filter bits
</description>
18185 <bitOffset>3</bitOffset>
18186 <bitWidth>1</bitWidth>
18190 <description>Filter bits
</description>
18191 <bitOffset>4</bitOffset>
18192 <bitWidth>1</bitWidth>
18196 <description>Filter bits
</description>
18197 <bitOffset>5</bitOffset>
18198 <bitWidth>1</bitWidth>
18202 <description>Filter bits
</description>
18203 <bitOffset>6</bitOffset>
18204 <bitWidth>1</bitWidth>
18208 <description>Filter bits
</description>
18209 <bitOffset>7</bitOffset>
18210 <bitWidth>1</bitWidth>
18214 <description>Filter bits
</description>
18215 <bitOffset>8</bitOffset>
18216 <bitWidth>1</bitWidth>
18220 <description>Filter bits
</description>
18221 <bitOffset>9</bitOffset>
18222 <bitWidth>1</bitWidth>
18226 <description>Filter bits
</description>
18227 <bitOffset>10</bitOffset>
18228 <bitWidth>1</bitWidth>
18232 <description>Filter bits
</description>
18233 <bitOffset>11</bitOffset>
18234 <bitWidth>1</bitWidth>
18238 <description>Filter bits
</description>
18239 <bitOffset>12</bitOffset>
18240 <bitWidth>1</bitWidth>
18244 <description>Filter bits
</description>
18245 <bitOffset>13</bitOffset>
18246 <bitWidth>1</bitWidth>
18250 <description>Filter bits
</description>
18251 <bitOffset>14</bitOffset>
18252 <bitWidth>1</bitWidth>
18256 <description>Filter bits
</description>
18257 <bitOffset>15</bitOffset>
18258 <bitWidth>1</bitWidth>
18262 <description>Filter bits
</description>
18263 <bitOffset>16</bitOffset>
18264 <bitWidth>1</bitWidth>
18268 <description>Filter bits
</description>
18269 <bitOffset>17</bitOffset>
18270 <bitWidth>1</bitWidth>
18274 <description>Filter bits
</description>
18275 <bitOffset>18</bitOffset>
18276 <bitWidth>1</bitWidth>
18280 <description>Filter bits
</description>
18281 <bitOffset>19</bitOffset>
18282 <bitWidth>1</bitWidth>
18286 <description>Filter bits
</description>
18287 <bitOffset>20</bitOffset>
18288 <bitWidth>1</bitWidth>
18292 <description>Filter bits
</description>
18293 <bitOffset>21</bitOffset>
18294 <bitWidth>1</bitWidth>
18298 <description>Filter bits
</description>
18299 <bitOffset>22</bitOffset>
18300 <bitWidth>1</bitWidth>
18304 <description>Filter bits
</description>
18305 <bitOffset>23</bitOffset>
18306 <bitWidth>1</bitWidth>
18310 <description>Filter bits
</description>
18311 <bitOffset>24</bitOffset>
18312 <bitWidth>1</bitWidth>
18316 <description>Filter bits
</description>
18317 <bitOffset>25</bitOffset>
18318 <bitWidth>1</bitWidth>
18322 <description>Filter bits
</description>
18323 <bitOffset>26</bitOffset>
18324 <bitWidth>1</bitWidth>
18328 <description>Filter bits
</description>
18329 <bitOffset>27</bitOffset>
18330 <bitWidth>1</bitWidth>
18334 <description>Filter bits
</description>
18335 <bitOffset>28</bitOffset>
18336 <bitWidth>1</bitWidth>
18340 <description>Filter bits
</description>
18341 <bitOffset>29</bitOffset>
18342 <bitWidth>1</bitWidth>
18346 <description>Filter bits
</description>
18347 <bitOffset>30</bitOffset>
18348 <bitWidth>1</bitWidth>
18352 <description>Filter bits
</description>
18353 <bitOffset>31</bitOffset>
18354 <bitWidth>1</bitWidth>
18360 <displayName>F8R1
</displayName>
18361 <description>Filter bank
8 register
1</description>
18362 <addressOffset>0x280</addressOffset>
18364 <access>read-write
</access>
18365 <resetValue>0x00000000</resetValue>
18369 <description>Filter bits
</description>
18370 <bitOffset>0</bitOffset>
18371 <bitWidth>1</bitWidth>
18375 <description>Filter bits
</description>
18376 <bitOffset>1</bitOffset>
18377 <bitWidth>1</bitWidth>
18381 <description>Filter bits
</description>
18382 <bitOffset>2</bitOffset>
18383 <bitWidth>1</bitWidth>
18387 <description>Filter bits
</description>
18388 <bitOffset>3</bitOffset>
18389 <bitWidth>1</bitWidth>
18393 <description>Filter bits
</description>
18394 <bitOffset>4</bitOffset>
18395 <bitWidth>1</bitWidth>
18399 <description>Filter bits
</description>
18400 <bitOffset>5</bitOffset>
18401 <bitWidth>1</bitWidth>
18405 <description>Filter bits
</description>
18406 <bitOffset>6</bitOffset>
18407 <bitWidth>1</bitWidth>
18411 <description>Filter bits
</description>
18412 <bitOffset>7</bitOffset>
18413 <bitWidth>1</bitWidth>
18417 <description>Filter bits
</description>
18418 <bitOffset>8</bitOffset>
18419 <bitWidth>1</bitWidth>
18423 <description>Filter bits
</description>
18424 <bitOffset>9</bitOffset>
18425 <bitWidth>1</bitWidth>
18429 <description>Filter bits
</description>
18430 <bitOffset>10</bitOffset>
18431 <bitWidth>1</bitWidth>
18435 <description>Filter bits
</description>
18436 <bitOffset>11</bitOffset>
18437 <bitWidth>1</bitWidth>
18441 <description>Filter bits
</description>
18442 <bitOffset>12</bitOffset>
18443 <bitWidth>1</bitWidth>
18447 <description>Filter bits
</description>
18448 <bitOffset>13</bitOffset>
18449 <bitWidth>1</bitWidth>
18453 <description>Filter bits
</description>
18454 <bitOffset>14</bitOffset>
18455 <bitWidth>1</bitWidth>
18459 <description>Filter bits
</description>
18460 <bitOffset>15</bitOffset>
18461 <bitWidth>1</bitWidth>
18465 <description>Filter bits
</description>
18466 <bitOffset>16</bitOffset>
18467 <bitWidth>1</bitWidth>
18471 <description>Filter bits
</description>
18472 <bitOffset>17</bitOffset>
18473 <bitWidth>1</bitWidth>
18477 <description>Filter bits
</description>
18478 <bitOffset>18</bitOffset>
18479 <bitWidth>1</bitWidth>
18483 <description>Filter bits
</description>
18484 <bitOffset>19</bitOffset>
18485 <bitWidth>1</bitWidth>
18489 <description>Filter bits
</description>
18490 <bitOffset>20</bitOffset>
18491 <bitWidth>1</bitWidth>
18495 <description>Filter bits
</description>
18496 <bitOffset>21</bitOffset>
18497 <bitWidth>1</bitWidth>
18501 <description>Filter bits
</description>
18502 <bitOffset>22</bitOffset>
18503 <bitWidth>1</bitWidth>
18507 <description>Filter bits
</description>
18508 <bitOffset>23</bitOffset>
18509 <bitWidth>1</bitWidth>
18513 <description>Filter bits
</description>
18514 <bitOffset>24</bitOffset>
18515 <bitWidth>1</bitWidth>
18519 <description>Filter bits
</description>
18520 <bitOffset>25</bitOffset>
18521 <bitWidth>1</bitWidth>
18525 <description>Filter bits
</description>
18526 <bitOffset>26</bitOffset>
18527 <bitWidth>1</bitWidth>
18531 <description>Filter bits
</description>
18532 <bitOffset>27</bitOffset>
18533 <bitWidth>1</bitWidth>
18537 <description>Filter bits
</description>
18538 <bitOffset>28</bitOffset>
18539 <bitWidth>1</bitWidth>
18543 <description>Filter bits
</description>
18544 <bitOffset>29</bitOffset>
18545 <bitWidth>1</bitWidth>
18549 <description>Filter bits
</description>
18550 <bitOffset>30</bitOffset>
18551 <bitWidth>1</bitWidth>
18555 <description>Filter bits
</description>
18556 <bitOffset>31</bitOffset>
18557 <bitWidth>1</bitWidth>
18563 <displayName>F8R2
</displayName>
18564 <description>Filter bank
8 register
2</description>
18565 <addressOffset>0x284</addressOffset>
18567 <access>read-write
</access>
18568 <resetValue>0x00000000</resetValue>
18572 <description>Filter bits
</description>
18573 <bitOffset>0</bitOffset>
18574 <bitWidth>1</bitWidth>
18578 <description>Filter bits
</description>
18579 <bitOffset>1</bitOffset>
18580 <bitWidth>1</bitWidth>
18584 <description>Filter bits
</description>
18585 <bitOffset>2</bitOffset>
18586 <bitWidth>1</bitWidth>
18590 <description>Filter bits
</description>
18591 <bitOffset>3</bitOffset>
18592 <bitWidth>1</bitWidth>
18596 <description>Filter bits
</description>
18597 <bitOffset>4</bitOffset>
18598 <bitWidth>1</bitWidth>
18602 <description>Filter bits
</description>
18603 <bitOffset>5</bitOffset>
18604 <bitWidth>1</bitWidth>
18608 <description>Filter bits
</description>
18609 <bitOffset>6</bitOffset>
18610 <bitWidth>1</bitWidth>
18614 <description>Filter bits
</description>
18615 <bitOffset>7</bitOffset>
18616 <bitWidth>1</bitWidth>
18620 <description>Filter bits
</description>
18621 <bitOffset>8</bitOffset>
18622 <bitWidth>1</bitWidth>
18626 <description>Filter bits
</description>
18627 <bitOffset>9</bitOffset>
18628 <bitWidth>1</bitWidth>
18632 <description>Filter bits
</description>
18633 <bitOffset>10</bitOffset>
18634 <bitWidth>1</bitWidth>
18638 <description>Filter bits
</description>
18639 <bitOffset>11</bitOffset>
18640 <bitWidth>1</bitWidth>
18644 <description>Filter bits
</description>
18645 <bitOffset>12</bitOffset>
18646 <bitWidth>1</bitWidth>
18650 <description>Filter bits
</description>
18651 <bitOffset>13</bitOffset>
18652 <bitWidth>1</bitWidth>
18656 <description>Filter bits
</description>
18657 <bitOffset>14</bitOffset>
18658 <bitWidth>1</bitWidth>
18662 <description>Filter bits
</description>
18663 <bitOffset>15</bitOffset>
18664 <bitWidth>1</bitWidth>
18668 <description>Filter bits
</description>
18669 <bitOffset>16</bitOffset>
18670 <bitWidth>1</bitWidth>
18674 <description>Filter bits
</description>
18675 <bitOffset>17</bitOffset>
18676 <bitWidth>1</bitWidth>
18680 <description>Filter bits
</description>
18681 <bitOffset>18</bitOffset>
18682 <bitWidth>1</bitWidth>
18686 <description>Filter bits
</description>
18687 <bitOffset>19</bitOffset>
18688 <bitWidth>1</bitWidth>
18692 <description>Filter bits
</description>
18693 <bitOffset>20</bitOffset>
18694 <bitWidth>1</bitWidth>
18698 <description>Filter bits
</description>
18699 <bitOffset>21</bitOffset>
18700 <bitWidth>1</bitWidth>
18704 <description>Filter bits
</description>
18705 <bitOffset>22</bitOffset>
18706 <bitWidth>1</bitWidth>
18710 <description>Filter bits
</description>
18711 <bitOffset>23</bitOffset>
18712 <bitWidth>1</bitWidth>
18716 <description>Filter bits
</description>
18717 <bitOffset>24</bitOffset>
18718 <bitWidth>1</bitWidth>
18722 <description>Filter bits
</description>
18723 <bitOffset>25</bitOffset>
18724 <bitWidth>1</bitWidth>
18728 <description>Filter bits
</description>
18729 <bitOffset>26</bitOffset>
18730 <bitWidth>1</bitWidth>
18734 <description>Filter bits
</description>
18735 <bitOffset>27</bitOffset>
18736 <bitWidth>1</bitWidth>
18740 <description>Filter bits
</description>
18741 <bitOffset>28</bitOffset>
18742 <bitWidth>1</bitWidth>
18746 <description>Filter bits
</description>
18747 <bitOffset>29</bitOffset>
18748 <bitWidth>1</bitWidth>
18752 <description>Filter bits
</description>
18753 <bitOffset>30</bitOffset>
18754 <bitWidth>1</bitWidth>
18758 <description>Filter bits
</description>
18759 <bitOffset>31</bitOffset>
18760 <bitWidth>1</bitWidth>
18766 <displayName>F9R1
</displayName>
18767 <description>Filter bank
9 register
1</description>
18768 <addressOffset>0x288</addressOffset>
18770 <access>read-write
</access>
18771 <resetValue>0x00000000</resetValue>
18775 <description>Filter bits
</description>
18776 <bitOffset>0</bitOffset>
18777 <bitWidth>1</bitWidth>
18781 <description>Filter bits
</description>
18782 <bitOffset>1</bitOffset>
18783 <bitWidth>1</bitWidth>
18787 <description>Filter bits
</description>
18788 <bitOffset>2</bitOffset>
18789 <bitWidth>1</bitWidth>
18793 <description>Filter bits
</description>
18794 <bitOffset>3</bitOffset>
18795 <bitWidth>1</bitWidth>
18799 <description>Filter bits
</description>
18800 <bitOffset>4</bitOffset>
18801 <bitWidth>1</bitWidth>
18805 <description>Filter bits
</description>
18806 <bitOffset>5</bitOffset>
18807 <bitWidth>1</bitWidth>
18811 <description>Filter bits
</description>
18812 <bitOffset>6</bitOffset>
18813 <bitWidth>1</bitWidth>
18817 <description>Filter bits
</description>
18818 <bitOffset>7</bitOffset>
18819 <bitWidth>1</bitWidth>
18823 <description>Filter bits
</description>
18824 <bitOffset>8</bitOffset>
18825 <bitWidth>1</bitWidth>
18829 <description>Filter bits
</description>
18830 <bitOffset>9</bitOffset>
18831 <bitWidth>1</bitWidth>
18835 <description>Filter bits
</description>
18836 <bitOffset>10</bitOffset>
18837 <bitWidth>1</bitWidth>
18841 <description>Filter bits
</description>
18842 <bitOffset>11</bitOffset>
18843 <bitWidth>1</bitWidth>
18847 <description>Filter bits
</description>
18848 <bitOffset>12</bitOffset>
18849 <bitWidth>1</bitWidth>
18853 <description>Filter bits
</description>
18854 <bitOffset>13</bitOffset>
18855 <bitWidth>1</bitWidth>
18859 <description>Filter bits
</description>
18860 <bitOffset>14</bitOffset>
18861 <bitWidth>1</bitWidth>
18865 <description>Filter bits
</description>
18866 <bitOffset>15</bitOffset>
18867 <bitWidth>1</bitWidth>
18871 <description>Filter bits
</description>
18872 <bitOffset>16</bitOffset>
18873 <bitWidth>1</bitWidth>
18877 <description>Filter bits
</description>
18878 <bitOffset>17</bitOffset>
18879 <bitWidth>1</bitWidth>
18883 <description>Filter bits
</description>
18884 <bitOffset>18</bitOffset>
18885 <bitWidth>1</bitWidth>
18889 <description>Filter bits
</description>
18890 <bitOffset>19</bitOffset>
18891 <bitWidth>1</bitWidth>
18895 <description>Filter bits
</description>
18896 <bitOffset>20</bitOffset>
18897 <bitWidth>1</bitWidth>
18901 <description>Filter bits
</description>
18902 <bitOffset>21</bitOffset>
18903 <bitWidth>1</bitWidth>
18907 <description>Filter bits
</description>
18908 <bitOffset>22</bitOffset>
18909 <bitWidth>1</bitWidth>
18913 <description>Filter bits
</description>
18914 <bitOffset>23</bitOffset>
18915 <bitWidth>1</bitWidth>
18919 <description>Filter bits
</description>
18920 <bitOffset>24</bitOffset>
18921 <bitWidth>1</bitWidth>
18925 <description>Filter bits
</description>
18926 <bitOffset>25</bitOffset>
18927 <bitWidth>1</bitWidth>
18931 <description>Filter bits
</description>
18932 <bitOffset>26</bitOffset>
18933 <bitWidth>1</bitWidth>
18937 <description>Filter bits
</description>
18938 <bitOffset>27</bitOffset>
18939 <bitWidth>1</bitWidth>
18943 <description>Filter bits
</description>
18944 <bitOffset>28</bitOffset>
18945 <bitWidth>1</bitWidth>
18949 <description>Filter bits
</description>
18950 <bitOffset>29</bitOffset>
18951 <bitWidth>1</bitWidth>
18955 <description>Filter bits
</description>
18956 <bitOffset>30</bitOffset>
18957 <bitWidth>1</bitWidth>
18961 <description>Filter bits
</description>
18962 <bitOffset>31</bitOffset>
18963 <bitWidth>1</bitWidth>
18969 <displayName>F9R2
</displayName>
18970 <description>Filter bank
9 register
2</description>
18971 <addressOffset>0x28C</addressOffset>
18973 <access>read-write
</access>
18974 <resetValue>0x00000000</resetValue>
18978 <description>Filter bits
</description>
18979 <bitOffset>0</bitOffset>
18980 <bitWidth>1</bitWidth>
18984 <description>Filter bits
</description>
18985 <bitOffset>1</bitOffset>
18986 <bitWidth>1</bitWidth>
18990 <description>Filter bits
</description>
18991 <bitOffset>2</bitOffset>
18992 <bitWidth>1</bitWidth>
18996 <description>Filter bits
</description>
18997 <bitOffset>3</bitOffset>
18998 <bitWidth>1</bitWidth>
19002 <description>Filter bits
</description>
19003 <bitOffset>4</bitOffset>
19004 <bitWidth>1</bitWidth>
19008 <description>Filter bits
</description>
19009 <bitOffset>5</bitOffset>
19010 <bitWidth>1</bitWidth>
19014 <description>Filter bits
</description>
19015 <bitOffset>6</bitOffset>
19016 <bitWidth>1</bitWidth>
19020 <description>Filter bits
</description>
19021 <bitOffset>7</bitOffset>
19022 <bitWidth>1</bitWidth>
19026 <description>Filter bits
</description>
19027 <bitOffset>8</bitOffset>
19028 <bitWidth>1</bitWidth>
19032 <description>Filter bits
</description>
19033 <bitOffset>9</bitOffset>
19034 <bitWidth>1</bitWidth>
19038 <description>Filter bits
</description>
19039 <bitOffset>10</bitOffset>
19040 <bitWidth>1</bitWidth>
19044 <description>Filter bits
</description>
19045 <bitOffset>11</bitOffset>
19046 <bitWidth>1</bitWidth>
19050 <description>Filter bits
</description>
19051 <bitOffset>12</bitOffset>
19052 <bitWidth>1</bitWidth>
19056 <description>Filter bits
</description>
19057 <bitOffset>13</bitOffset>
19058 <bitWidth>1</bitWidth>
19062 <description>Filter bits
</description>
19063 <bitOffset>14</bitOffset>
19064 <bitWidth>1</bitWidth>
19068 <description>Filter bits
</description>
19069 <bitOffset>15</bitOffset>
19070 <bitWidth>1</bitWidth>
19074 <description>Filter bits
</description>
19075 <bitOffset>16</bitOffset>
19076 <bitWidth>1</bitWidth>
19080 <description>Filter bits
</description>
19081 <bitOffset>17</bitOffset>
19082 <bitWidth>1</bitWidth>
19086 <description>Filter bits
</description>
19087 <bitOffset>18</bitOffset>
19088 <bitWidth>1</bitWidth>
19092 <description>Filter bits
</description>
19093 <bitOffset>19</bitOffset>
19094 <bitWidth>1</bitWidth>
19098 <description>Filter bits
</description>
19099 <bitOffset>20</bitOffset>
19100 <bitWidth>1</bitWidth>
19104 <description>Filter bits
</description>
19105 <bitOffset>21</bitOffset>
19106 <bitWidth>1</bitWidth>
19110 <description>Filter bits
</description>
19111 <bitOffset>22</bitOffset>
19112 <bitWidth>1</bitWidth>
19116 <description>Filter bits
</description>
19117 <bitOffset>23</bitOffset>
19118 <bitWidth>1</bitWidth>
19122 <description>Filter bits
</description>
19123 <bitOffset>24</bitOffset>
19124 <bitWidth>1</bitWidth>
19128 <description>Filter bits
</description>
19129 <bitOffset>25</bitOffset>
19130 <bitWidth>1</bitWidth>
19134 <description>Filter bits
</description>
19135 <bitOffset>26</bitOffset>
19136 <bitWidth>1</bitWidth>
19140 <description>Filter bits
</description>
19141 <bitOffset>27</bitOffset>
19142 <bitWidth>1</bitWidth>
19146 <description>Filter bits
</description>
19147 <bitOffset>28</bitOffset>
19148 <bitWidth>1</bitWidth>
19152 <description>Filter bits
</description>
19153 <bitOffset>29</bitOffset>
19154 <bitWidth>1</bitWidth>
19158 <description>Filter bits
</description>
19159 <bitOffset>30</bitOffset>
19160 <bitWidth>1</bitWidth>
19164 <description>Filter bits
</description>
19165 <bitOffset>31</bitOffset>
19166 <bitWidth>1</bitWidth>
19172 <displayName>F10R1
</displayName>
19173 <description>Filter bank
10 register
1</description>
19174 <addressOffset>0x290</addressOffset>
19176 <access>read-write
</access>
19177 <resetValue>0x00000000</resetValue>
19181 <description>Filter bits
</description>
19182 <bitOffset>0</bitOffset>
19183 <bitWidth>1</bitWidth>
19187 <description>Filter bits
</description>
19188 <bitOffset>1</bitOffset>
19189 <bitWidth>1</bitWidth>
19193 <description>Filter bits
</description>
19194 <bitOffset>2</bitOffset>
19195 <bitWidth>1</bitWidth>
19199 <description>Filter bits
</description>
19200 <bitOffset>3</bitOffset>
19201 <bitWidth>1</bitWidth>
19205 <description>Filter bits
</description>
19206 <bitOffset>4</bitOffset>
19207 <bitWidth>1</bitWidth>
19211 <description>Filter bits
</description>
19212 <bitOffset>5</bitOffset>
19213 <bitWidth>1</bitWidth>
19217 <description>Filter bits
</description>
19218 <bitOffset>6</bitOffset>
19219 <bitWidth>1</bitWidth>
19223 <description>Filter bits
</description>
19224 <bitOffset>7</bitOffset>
19225 <bitWidth>1</bitWidth>
19229 <description>Filter bits
</description>
19230 <bitOffset>8</bitOffset>
19231 <bitWidth>1</bitWidth>
19235 <description>Filter bits
</description>
19236 <bitOffset>9</bitOffset>
19237 <bitWidth>1</bitWidth>
19241 <description>Filter bits
</description>
19242 <bitOffset>10</bitOffset>
19243 <bitWidth>1</bitWidth>
19247 <description>Filter bits
</description>
19248 <bitOffset>11</bitOffset>
19249 <bitWidth>1</bitWidth>
19253 <description>Filter bits
</description>
19254 <bitOffset>12</bitOffset>
19255 <bitWidth>1</bitWidth>
19259 <description>Filter bits
</description>
19260 <bitOffset>13</bitOffset>
19261 <bitWidth>1</bitWidth>
19265 <description>Filter bits
</description>
19266 <bitOffset>14</bitOffset>
19267 <bitWidth>1</bitWidth>
19271 <description>Filter bits
</description>
19272 <bitOffset>15</bitOffset>
19273 <bitWidth>1</bitWidth>
19277 <description>Filter bits
</description>
19278 <bitOffset>16</bitOffset>
19279 <bitWidth>1</bitWidth>
19283 <description>Filter bits
</description>
19284 <bitOffset>17</bitOffset>
19285 <bitWidth>1</bitWidth>
19289 <description>Filter bits
</description>
19290 <bitOffset>18</bitOffset>
19291 <bitWidth>1</bitWidth>
19295 <description>Filter bits
</description>
19296 <bitOffset>19</bitOffset>
19297 <bitWidth>1</bitWidth>
19301 <description>Filter bits
</description>
19302 <bitOffset>20</bitOffset>
19303 <bitWidth>1</bitWidth>
19307 <description>Filter bits
</description>
19308 <bitOffset>21</bitOffset>
19309 <bitWidth>1</bitWidth>
19313 <description>Filter bits
</description>
19314 <bitOffset>22</bitOffset>
19315 <bitWidth>1</bitWidth>
19319 <description>Filter bits
</description>
19320 <bitOffset>23</bitOffset>
19321 <bitWidth>1</bitWidth>
19325 <description>Filter bits
</description>
19326 <bitOffset>24</bitOffset>
19327 <bitWidth>1</bitWidth>
19331 <description>Filter bits
</description>
19332 <bitOffset>25</bitOffset>
19333 <bitWidth>1</bitWidth>
19337 <description>Filter bits
</description>
19338 <bitOffset>26</bitOffset>
19339 <bitWidth>1</bitWidth>
19343 <description>Filter bits
</description>
19344 <bitOffset>27</bitOffset>
19345 <bitWidth>1</bitWidth>
19349 <description>Filter bits
</description>
19350 <bitOffset>28</bitOffset>
19351 <bitWidth>1</bitWidth>
19355 <description>Filter bits
</description>
19356 <bitOffset>29</bitOffset>
19357 <bitWidth>1</bitWidth>
19361 <description>Filter bits
</description>
19362 <bitOffset>30</bitOffset>
19363 <bitWidth>1</bitWidth>
19367 <description>Filter bits
</description>
19368 <bitOffset>31</bitOffset>
19369 <bitWidth>1</bitWidth>
19375 <displayName>F10R2
</displayName>
19376 <description>Filter bank
10 register
2</description>
19377 <addressOffset>0x294</addressOffset>
19379 <access>read-write
</access>
19380 <resetValue>0x00000000</resetValue>
19384 <description>Filter bits
</description>
19385 <bitOffset>0</bitOffset>
19386 <bitWidth>1</bitWidth>
19390 <description>Filter bits
</description>
19391 <bitOffset>1</bitOffset>
19392 <bitWidth>1</bitWidth>
19396 <description>Filter bits
</description>
19397 <bitOffset>2</bitOffset>
19398 <bitWidth>1</bitWidth>
19402 <description>Filter bits
</description>
19403 <bitOffset>3</bitOffset>
19404 <bitWidth>1</bitWidth>
19408 <description>Filter bits
</description>
19409 <bitOffset>4</bitOffset>
19410 <bitWidth>1</bitWidth>
19414 <description>Filter bits
</description>
19415 <bitOffset>5</bitOffset>
19416 <bitWidth>1</bitWidth>
19420 <description>Filter bits
</description>
19421 <bitOffset>6</bitOffset>
19422 <bitWidth>1</bitWidth>
19426 <description>Filter bits
</description>
19427 <bitOffset>7</bitOffset>
19428 <bitWidth>1</bitWidth>
19432 <description>Filter bits
</description>
19433 <bitOffset>8</bitOffset>
19434 <bitWidth>1</bitWidth>
19438 <description>Filter bits
</description>
19439 <bitOffset>9</bitOffset>
19440 <bitWidth>1</bitWidth>
19444 <description>Filter bits
</description>
19445 <bitOffset>10</bitOffset>
19446 <bitWidth>1</bitWidth>
19450 <description>Filter bits
</description>
19451 <bitOffset>11</bitOffset>
19452 <bitWidth>1</bitWidth>
19456 <description>Filter bits
</description>
19457 <bitOffset>12</bitOffset>
19458 <bitWidth>1</bitWidth>
19462 <description>Filter bits
</description>
19463 <bitOffset>13</bitOffset>
19464 <bitWidth>1</bitWidth>
19468 <description>Filter bits
</description>
19469 <bitOffset>14</bitOffset>
19470 <bitWidth>1</bitWidth>
19474 <description>Filter bits
</description>
19475 <bitOffset>15</bitOffset>
19476 <bitWidth>1</bitWidth>
19480 <description>Filter bits
</description>
19481 <bitOffset>16</bitOffset>
19482 <bitWidth>1</bitWidth>
19486 <description>Filter bits
</description>
19487 <bitOffset>17</bitOffset>
19488 <bitWidth>1</bitWidth>
19492 <description>Filter bits
</description>
19493 <bitOffset>18</bitOffset>
19494 <bitWidth>1</bitWidth>
19498 <description>Filter bits
</description>
19499 <bitOffset>19</bitOffset>
19500 <bitWidth>1</bitWidth>
19504 <description>Filter bits
</description>
19505 <bitOffset>20</bitOffset>
19506 <bitWidth>1</bitWidth>
19510 <description>Filter bits
</description>
19511 <bitOffset>21</bitOffset>
19512 <bitWidth>1</bitWidth>
19516 <description>Filter bits
</description>
19517 <bitOffset>22</bitOffset>
19518 <bitWidth>1</bitWidth>
19522 <description>Filter bits
</description>
19523 <bitOffset>23</bitOffset>
19524 <bitWidth>1</bitWidth>
19528 <description>Filter bits
</description>
19529 <bitOffset>24</bitOffset>
19530 <bitWidth>1</bitWidth>
19534 <description>Filter bits
</description>
19535 <bitOffset>25</bitOffset>
19536 <bitWidth>1</bitWidth>
19540 <description>Filter bits
</description>
19541 <bitOffset>26</bitOffset>
19542 <bitWidth>1</bitWidth>
19546 <description>Filter bits
</description>
19547 <bitOffset>27</bitOffset>
19548 <bitWidth>1</bitWidth>
19552 <description>Filter bits
</description>
19553 <bitOffset>28</bitOffset>
19554 <bitWidth>1</bitWidth>
19558 <description>Filter bits
</description>
19559 <bitOffset>29</bitOffset>
19560 <bitWidth>1</bitWidth>
19564 <description>Filter bits
</description>
19565 <bitOffset>30</bitOffset>
19566 <bitWidth>1</bitWidth>
19570 <description>Filter bits
</description>
19571 <bitOffset>31</bitOffset>
19572 <bitWidth>1</bitWidth>
19578 <displayName>F11R1
</displayName>
19579 <description>Filter bank
11 register
1</description>
19580 <addressOffset>0x298</addressOffset>
19582 <access>read-write
</access>
19583 <resetValue>0x00000000</resetValue>
19587 <description>Filter bits
</description>
19588 <bitOffset>0</bitOffset>
19589 <bitWidth>1</bitWidth>
19593 <description>Filter bits
</description>
19594 <bitOffset>1</bitOffset>
19595 <bitWidth>1</bitWidth>
19599 <description>Filter bits
</description>
19600 <bitOffset>2</bitOffset>
19601 <bitWidth>1</bitWidth>
19605 <description>Filter bits
</description>
19606 <bitOffset>3</bitOffset>
19607 <bitWidth>1</bitWidth>
19611 <description>Filter bits
</description>
19612 <bitOffset>4</bitOffset>
19613 <bitWidth>1</bitWidth>
19617 <description>Filter bits
</description>
19618 <bitOffset>5</bitOffset>
19619 <bitWidth>1</bitWidth>
19623 <description>Filter bits
</description>
19624 <bitOffset>6</bitOffset>
19625 <bitWidth>1</bitWidth>
19629 <description>Filter bits
</description>
19630 <bitOffset>7</bitOffset>
19631 <bitWidth>1</bitWidth>
19635 <description>Filter bits
</description>
19636 <bitOffset>8</bitOffset>
19637 <bitWidth>1</bitWidth>
19641 <description>Filter bits
</description>
19642 <bitOffset>9</bitOffset>
19643 <bitWidth>1</bitWidth>
19647 <description>Filter bits
</description>
19648 <bitOffset>10</bitOffset>
19649 <bitWidth>1</bitWidth>
19653 <description>Filter bits
</description>
19654 <bitOffset>11</bitOffset>
19655 <bitWidth>1</bitWidth>
19659 <description>Filter bits
</description>
19660 <bitOffset>12</bitOffset>
19661 <bitWidth>1</bitWidth>
19665 <description>Filter bits
</description>
19666 <bitOffset>13</bitOffset>
19667 <bitWidth>1</bitWidth>
19671 <description>Filter bits
</description>
19672 <bitOffset>14</bitOffset>
19673 <bitWidth>1</bitWidth>
19677 <description>Filter bits
</description>
19678 <bitOffset>15</bitOffset>
19679 <bitWidth>1</bitWidth>
19683 <description>Filter bits
</description>
19684 <bitOffset>16</bitOffset>
19685 <bitWidth>1</bitWidth>
19689 <description>Filter bits
</description>
19690 <bitOffset>17</bitOffset>
19691 <bitWidth>1</bitWidth>
19695 <description>Filter bits
</description>
19696 <bitOffset>18</bitOffset>
19697 <bitWidth>1</bitWidth>
19701 <description>Filter bits
</description>
19702 <bitOffset>19</bitOffset>
19703 <bitWidth>1</bitWidth>
19707 <description>Filter bits
</description>
19708 <bitOffset>20</bitOffset>
19709 <bitWidth>1</bitWidth>
19713 <description>Filter bits
</description>
19714 <bitOffset>21</bitOffset>
19715 <bitWidth>1</bitWidth>
19719 <description>Filter bits
</description>
19720 <bitOffset>22</bitOffset>
19721 <bitWidth>1</bitWidth>
19725 <description>Filter bits
</description>
19726 <bitOffset>23</bitOffset>
19727 <bitWidth>1</bitWidth>
19731 <description>Filter bits
</description>
19732 <bitOffset>24</bitOffset>
19733 <bitWidth>1</bitWidth>
19737 <description>Filter bits
</description>
19738 <bitOffset>25</bitOffset>
19739 <bitWidth>1</bitWidth>
19743 <description>Filter bits
</description>
19744 <bitOffset>26</bitOffset>
19745 <bitWidth>1</bitWidth>
19749 <description>Filter bits
</description>
19750 <bitOffset>27</bitOffset>
19751 <bitWidth>1</bitWidth>
19755 <description>Filter bits
</description>
19756 <bitOffset>28</bitOffset>
19757 <bitWidth>1</bitWidth>
19761 <description>Filter bits
</description>
19762 <bitOffset>29</bitOffset>
19763 <bitWidth>1</bitWidth>
19767 <description>Filter bits
</description>
19768 <bitOffset>30</bitOffset>
19769 <bitWidth>1</bitWidth>
19773 <description>Filter bits
</description>
19774 <bitOffset>31</bitOffset>
19775 <bitWidth>1</bitWidth>
19781 <displayName>F11R2
</displayName>
19782 <description>Filter bank
11 register
2</description>
19783 <addressOffset>0x29C</addressOffset>
19785 <access>read-write
</access>
19786 <resetValue>0x00000000</resetValue>
19790 <description>Filter bits
</description>
19791 <bitOffset>0</bitOffset>
19792 <bitWidth>1</bitWidth>
19796 <description>Filter bits
</description>
19797 <bitOffset>1</bitOffset>
19798 <bitWidth>1</bitWidth>
19802 <description>Filter bits
</description>
19803 <bitOffset>2</bitOffset>
19804 <bitWidth>1</bitWidth>
19808 <description>Filter bits
</description>
19809 <bitOffset>3</bitOffset>
19810 <bitWidth>1</bitWidth>
19814 <description>Filter bits
</description>
19815 <bitOffset>4</bitOffset>
19816 <bitWidth>1</bitWidth>
19820 <description>Filter bits
</description>
19821 <bitOffset>5</bitOffset>
19822 <bitWidth>1</bitWidth>
19826 <description>Filter bits
</description>
19827 <bitOffset>6</bitOffset>
19828 <bitWidth>1</bitWidth>
19832 <description>Filter bits
</description>
19833 <bitOffset>7</bitOffset>
19834 <bitWidth>1</bitWidth>
19838 <description>Filter bits
</description>
19839 <bitOffset>8</bitOffset>
19840 <bitWidth>1</bitWidth>
19844 <description>Filter bits
</description>
19845 <bitOffset>9</bitOffset>
19846 <bitWidth>1</bitWidth>
19850 <description>Filter bits
</description>
19851 <bitOffset>10</bitOffset>
19852 <bitWidth>1</bitWidth>
19856 <description>Filter bits
</description>
19857 <bitOffset>11</bitOffset>
19858 <bitWidth>1</bitWidth>
19862 <description>Filter bits
</description>
19863 <bitOffset>12</bitOffset>
19864 <bitWidth>1</bitWidth>
19868 <description>Filter bits
</description>
19869 <bitOffset>13</bitOffset>
19870 <bitWidth>1</bitWidth>
19874 <description>Filter bits
</description>
19875 <bitOffset>14</bitOffset>
19876 <bitWidth>1</bitWidth>
19880 <description>Filter bits
</description>
19881 <bitOffset>15</bitOffset>
19882 <bitWidth>1</bitWidth>
19886 <description>Filter bits
</description>
19887 <bitOffset>16</bitOffset>
19888 <bitWidth>1</bitWidth>
19892 <description>Filter bits
</description>
19893 <bitOffset>17</bitOffset>
19894 <bitWidth>1</bitWidth>
19898 <description>Filter bits
</description>
19899 <bitOffset>18</bitOffset>
19900 <bitWidth>1</bitWidth>
19904 <description>Filter bits
</description>
19905 <bitOffset>19</bitOffset>
19906 <bitWidth>1</bitWidth>
19910 <description>Filter bits
</description>
19911 <bitOffset>20</bitOffset>
19912 <bitWidth>1</bitWidth>
19916 <description>Filter bits
</description>
19917 <bitOffset>21</bitOffset>
19918 <bitWidth>1</bitWidth>
19922 <description>Filter bits
</description>
19923 <bitOffset>22</bitOffset>
19924 <bitWidth>1</bitWidth>
19928 <description>Filter bits
</description>
19929 <bitOffset>23</bitOffset>
19930 <bitWidth>1</bitWidth>
19934 <description>Filter bits
</description>
19935 <bitOffset>24</bitOffset>
19936 <bitWidth>1</bitWidth>
19940 <description>Filter bits
</description>
19941 <bitOffset>25</bitOffset>
19942 <bitWidth>1</bitWidth>
19946 <description>Filter bits
</description>
19947 <bitOffset>26</bitOffset>
19948 <bitWidth>1</bitWidth>
19952 <description>Filter bits
</description>
19953 <bitOffset>27</bitOffset>
19954 <bitWidth>1</bitWidth>
19958 <description>Filter bits
</description>
19959 <bitOffset>28</bitOffset>
19960 <bitWidth>1</bitWidth>
19964 <description>Filter bits
</description>
19965 <bitOffset>29</bitOffset>
19966 <bitWidth>1</bitWidth>
19970 <description>Filter bits
</description>
19971 <bitOffset>30</bitOffset>
19972 <bitWidth>1</bitWidth>
19976 <description>Filter bits
</description>
19977 <bitOffset>31</bitOffset>
19978 <bitWidth>1</bitWidth>
19984 <displayName>F12R1
</displayName>
19985 <description>Filter bank
4 register
1</description>
19986 <addressOffset>0x2A0</addressOffset>
19988 <access>read-write
</access>
19989 <resetValue>0x00000000</resetValue>
19993 <description>Filter bits
</description>
19994 <bitOffset>0</bitOffset>
19995 <bitWidth>1</bitWidth>
19999 <description>Filter bits
</description>
20000 <bitOffset>1</bitOffset>
20001 <bitWidth>1</bitWidth>
20005 <description>Filter bits
</description>
20006 <bitOffset>2</bitOffset>
20007 <bitWidth>1</bitWidth>
20011 <description>Filter bits
</description>
20012 <bitOffset>3</bitOffset>
20013 <bitWidth>1</bitWidth>
20017 <description>Filter bits
</description>
20018 <bitOffset>4</bitOffset>
20019 <bitWidth>1</bitWidth>
20023 <description>Filter bits
</description>
20024 <bitOffset>5</bitOffset>
20025 <bitWidth>1</bitWidth>
20029 <description>Filter bits
</description>
20030 <bitOffset>6</bitOffset>
20031 <bitWidth>1</bitWidth>
20035 <description>Filter bits
</description>
20036 <bitOffset>7</bitOffset>
20037 <bitWidth>1</bitWidth>
20041 <description>Filter bits
</description>
20042 <bitOffset>8</bitOffset>
20043 <bitWidth>1</bitWidth>
20047 <description>Filter bits
</description>
20048 <bitOffset>9</bitOffset>
20049 <bitWidth>1</bitWidth>
20053 <description>Filter bits
</description>
20054 <bitOffset>10</bitOffset>
20055 <bitWidth>1</bitWidth>
20059 <description>Filter bits
</description>
20060 <bitOffset>11</bitOffset>
20061 <bitWidth>1</bitWidth>
20065 <description>Filter bits
</description>
20066 <bitOffset>12</bitOffset>
20067 <bitWidth>1</bitWidth>
20071 <description>Filter bits
</description>
20072 <bitOffset>13</bitOffset>
20073 <bitWidth>1</bitWidth>
20077 <description>Filter bits
</description>
20078 <bitOffset>14</bitOffset>
20079 <bitWidth>1</bitWidth>
20083 <description>Filter bits
</description>
20084 <bitOffset>15</bitOffset>
20085 <bitWidth>1</bitWidth>
20089 <description>Filter bits
</description>
20090 <bitOffset>16</bitOffset>
20091 <bitWidth>1</bitWidth>
20095 <description>Filter bits
</description>
20096 <bitOffset>17</bitOffset>
20097 <bitWidth>1</bitWidth>
20101 <description>Filter bits
</description>
20102 <bitOffset>18</bitOffset>
20103 <bitWidth>1</bitWidth>
20107 <description>Filter bits
</description>
20108 <bitOffset>19</bitOffset>
20109 <bitWidth>1</bitWidth>
20113 <description>Filter bits
</description>
20114 <bitOffset>20</bitOffset>
20115 <bitWidth>1</bitWidth>
20119 <description>Filter bits
</description>
20120 <bitOffset>21</bitOffset>
20121 <bitWidth>1</bitWidth>
20125 <description>Filter bits
</description>
20126 <bitOffset>22</bitOffset>
20127 <bitWidth>1</bitWidth>
20131 <description>Filter bits
</description>
20132 <bitOffset>23</bitOffset>
20133 <bitWidth>1</bitWidth>
20137 <description>Filter bits
</description>
20138 <bitOffset>24</bitOffset>
20139 <bitWidth>1</bitWidth>
20143 <description>Filter bits
</description>
20144 <bitOffset>25</bitOffset>
20145 <bitWidth>1</bitWidth>
20149 <description>Filter bits
</description>
20150 <bitOffset>26</bitOffset>
20151 <bitWidth>1</bitWidth>
20155 <description>Filter bits
</description>
20156 <bitOffset>27</bitOffset>
20157 <bitWidth>1</bitWidth>
20161 <description>Filter bits
</description>
20162 <bitOffset>28</bitOffset>
20163 <bitWidth>1</bitWidth>
20167 <description>Filter bits
</description>
20168 <bitOffset>29</bitOffset>
20169 <bitWidth>1</bitWidth>
20173 <description>Filter bits
</description>
20174 <bitOffset>30</bitOffset>
20175 <bitWidth>1</bitWidth>
20179 <description>Filter bits
</description>
20180 <bitOffset>31</bitOffset>
20181 <bitWidth>1</bitWidth>
20187 <displayName>F12R2
</displayName>
20188 <description>Filter bank
12 register
2</description>
20189 <addressOffset>0x2A4</addressOffset>
20191 <access>read-write
</access>
20192 <resetValue>0x00000000</resetValue>
20196 <description>Filter bits
</description>
20197 <bitOffset>0</bitOffset>
20198 <bitWidth>1</bitWidth>
20202 <description>Filter bits
</description>
20203 <bitOffset>1</bitOffset>
20204 <bitWidth>1</bitWidth>
20208 <description>Filter bits
</description>
20209 <bitOffset>2</bitOffset>
20210 <bitWidth>1</bitWidth>
20214 <description>Filter bits
</description>
20215 <bitOffset>3</bitOffset>
20216 <bitWidth>1</bitWidth>
20220 <description>Filter bits
</description>
20221 <bitOffset>4</bitOffset>
20222 <bitWidth>1</bitWidth>
20226 <description>Filter bits
</description>
20227 <bitOffset>5</bitOffset>
20228 <bitWidth>1</bitWidth>
20232 <description>Filter bits
</description>
20233 <bitOffset>6</bitOffset>
20234 <bitWidth>1</bitWidth>
20238 <description>Filter bits
</description>
20239 <bitOffset>7</bitOffset>
20240 <bitWidth>1</bitWidth>
20244 <description>Filter bits
</description>
20245 <bitOffset>8</bitOffset>
20246 <bitWidth>1</bitWidth>
20250 <description>Filter bits
</description>
20251 <bitOffset>9</bitOffset>
20252 <bitWidth>1</bitWidth>
20256 <description>Filter bits
</description>
20257 <bitOffset>10</bitOffset>
20258 <bitWidth>1</bitWidth>
20262 <description>Filter bits
</description>
20263 <bitOffset>11</bitOffset>
20264 <bitWidth>1</bitWidth>
20268 <description>Filter bits
</description>
20269 <bitOffset>12</bitOffset>
20270 <bitWidth>1</bitWidth>
20274 <description>Filter bits
</description>
20275 <bitOffset>13</bitOffset>
20276 <bitWidth>1</bitWidth>
20280 <description>Filter bits
</description>
20281 <bitOffset>14</bitOffset>
20282 <bitWidth>1</bitWidth>
20286 <description>Filter bits
</description>
20287 <bitOffset>15</bitOffset>
20288 <bitWidth>1</bitWidth>
20292 <description>Filter bits
</description>
20293 <bitOffset>16</bitOffset>
20294 <bitWidth>1</bitWidth>
20298 <description>Filter bits
</description>
20299 <bitOffset>17</bitOffset>
20300 <bitWidth>1</bitWidth>
20304 <description>Filter bits
</description>
20305 <bitOffset>18</bitOffset>
20306 <bitWidth>1</bitWidth>
20310 <description>Filter bits
</description>
20311 <bitOffset>19</bitOffset>
20312 <bitWidth>1</bitWidth>
20316 <description>Filter bits
</description>
20317 <bitOffset>20</bitOffset>
20318 <bitWidth>1</bitWidth>
20322 <description>Filter bits
</description>
20323 <bitOffset>21</bitOffset>
20324 <bitWidth>1</bitWidth>
20328 <description>Filter bits
</description>
20329 <bitOffset>22</bitOffset>
20330 <bitWidth>1</bitWidth>
20334 <description>Filter bits
</description>
20335 <bitOffset>23</bitOffset>
20336 <bitWidth>1</bitWidth>
20340 <description>Filter bits
</description>
20341 <bitOffset>24</bitOffset>
20342 <bitWidth>1</bitWidth>
20346 <description>Filter bits
</description>
20347 <bitOffset>25</bitOffset>
20348 <bitWidth>1</bitWidth>
20352 <description>Filter bits
</description>
20353 <bitOffset>26</bitOffset>
20354 <bitWidth>1</bitWidth>
20358 <description>Filter bits
</description>
20359 <bitOffset>27</bitOffset>
20360 <bitWidth>1</bitWidth>
20364 <description>Filter bits
</description>
20365 <bitOffset>28</bitOffset>
20366 <bitWidth>1</bitWidth>
20370 <description>Filter bits
</description>
20371 <bitOffset>29</bitOffset>
20372 <bitWidth>1</bitWidth>
20376 <description>Filter bits
</description>
20377 <bitOffset>30</bitOffset>
20378 <bitWidth>1</bitWidth>
20382 <description>Filter bits
</description>
20383 <bitOffset>31</bitOffset>
20384 <bitWidth>1</bitWidth>
20390 <displayName>F13R1
</displayName>
20391 <description>Filter bank
13 register
1</description>
20392 <addressOffset>0x2A8</addressOffset>
20394 <access>read-write
</access>
20395 <resetValue>0x00000000</resetValue>
20399 <description>Filter bits
</description>
20400 <bitOffset>0</bitOffset>
20401 <bitWidth>1</bitWidth>
20405 <description>Filter bits
</description>
20406 <bitOffset>1</bitOffset>
20407 <bitWidth>1</bitWidth>
20411 <description>Filter bits
</description>
20412 <bitOffset>2</bitOffset>
20413 <bitWidth>1</bitWidth>
20417 <description>Filter bits
</description>
20418 <bitOffset>3</bitOffset>
20419 <bitWidth>1</bitWidth>
20423 <description>Filter bits
</description>
20424 <bitOffset>4</bitOffset>
20425 <bitWidth>1</bitWidth>
20429 <description>Filter bits
</description>
20430 <bitOffset>5</bitOffset>
20431 <bitWidth>1</bitWidth>
20435 <description>Filter bits
</description>
20436 <bitOffset>6</bitOffset>
20437 <bitWidth>1</bitWidth>
20441 <description>Filter bits
</description>
20442 <bitOffset>7</bitOffset>
20443 <bitWidth>1</bitWidth>
20447 <description>Filter bits
</description>
20448 <bitOffset>8</bitOffset>
20449 <bitWidth>1</bitWidth>
20453 <description>Filter bits
</description>
20454 <bitOffset>9</bitOffset>
20455 <bitWidth>1</bitWidth>
20459 <description>Filter bits
</description>
20460 <bitOffset>10</bitOffset>
20461 <bitWidth>1</bitWidth>
20465 <description>Filter bits
</description>
20466 <bitOffset>11</bitOffset>
20467 <bitWidth>1</bitWidth>
20471 <description>Filter bits
</description>
20472 <bitOffset>12</bitOffset>
20473 <bitWidth>1</bitWidth>
20477 <description>Filter bits
</description>
20478 <bitOffset>13</bitOffset>
20479 <bitWidth>1</bitWidth>
20483 <description>Filter bits
</description>
20484 <bitOffset>14</bitOffset>
20485 <bitWidth>1</bitWidth>
20489 <description>Filter bits
</description>
20490 <bitOffset>15</bitOffset>
20491 <bitWidth>1</bitWidth>
20495 <description>Filter bits
</description>
20496 <bitOffset>16</bitOffset>
20497 <bitWidth>1</bitWidth>
20501 <description>Filter bits
</description>
20502 <bitOffset>17</bitOffset>
20503 <bitWidth>1</bitWidth>
20507 <description>Filter bits
</description>
20508 <bitOffset>18</bitOffset>
20509 <bitWidth>1</bitWidth>
20513 <description>Filter bits
</description>
20514 <bitOffset>19</bitOffset>
20515 <bitWidth>1</bitWidth>
20519 <description>Filter bits
</description>
20520 <bitOffset>20</bitOffset>
20521 <bitWidth>1</bitWidth>
20525 <description>Filter bits
</description>
20526 <bitOffset>21</bitOffset>
20527 <bitWidth>1</bitWidth>
20531 <description>Filter bits
</description>
20532 <bitOffset>22</bitOffset>
20533 <bitWidth>1</bitWidth>
20537 <description>Filter bits
</description>
20538 <bitOffset>23</bitOffset>
20539 <bitWidth>1</bitWidth>
20543 <description>Filter bits
</description>
20544 <bitOffset>24</bitOffset>
20545 <bitWidth>1</bitWidth>
20549 <description>Filter bits
</description>
20550 <bitOffset>25</bitOffset>
20551 <bitWidth>1</bitWidth>
20555 <description>Filter bits
</description>
20556 <bitOffset>26</bitOffset>
20557 <bitWidth>1</bitWidth>
20561 <description>Filter bits
</description>
20562 <bitOffset>27</bitOffset>
20563 <bitWidth>1</bitWidth>
20567 <description>Filter bits
</description>
20568 <bitOffset>28</bitOffset>
20569 <bitWidth>1</bitWidth>
20573 <description>Filter bits
</description>
20574 <bitOffset>29</bitOffset>
20575 <bitWidth>1</bitWidth>
20579 <description>Filter bits
</description>
20580 <bitOffset>30</bitOffset>
20581 <bitWidth>1</bitWidth>
20585 <description>Filter bits
</description>
20586 <bitOffset>31</bitOffset>
20587 <bitWidth>1</bitWidth>
20593 <displayName>F13R2
</displayName>
20594 <description>Filter bank
13 register
2</description>
20595 <addressOffset>0x2AC</addressOffset>
20597 <access>read-write
</access>
20598 <resetValue>0x00000000</resetValue>
20602 <description>Filter bits
</description>
20603 <bitOffset>0</bitOffset>
20604 <bitWidth>1</bitWidth>
20608 <description>Filter bits
</description>
20609 <bitOffset>1</bitOffset>
20610 <bitWidth>1</bitWidth>
20614 <description>Filter bits
</description>
20615 <bitOffset>2</bitOffset>
20616 <bitWidth>1</bitWidth>
20620 <description>Filter bits
</description>
20621 <bitOffset>3</bitOffset>
20622 <bitWidth>1</bitWidth>
20626 <description>Filter bits
</description>
20627 <bitOffset>4</bitOffset>
20628 <bitWidth>1</bitWidth>
20632 <description>Filter bits
</description>
20633 <bitOffset>5</bitOffset>
20634 <bitWidth>1</bitWidth>
20638 <description>Filter bits
</description>
20639 <bitOffset>6</bitOffset>
20640 <bitWidth>1</bitWidth>
20644 <description>Filter bits
</description>
20645 <bitOffset>7</bitOffset>
20646 <bitWidth>1</bitWidth>
20650 <description>Filter bits
</description>
20651 <bitOffset>8</bitOffset>
20652 <bitWidth>1</bitWidth>
20656 <description>Filter bits
</description>
20657 <bitOffset>9</bitOffset>
20658 <bitWidth>1</bitWidth>
20662 <description>Filter bits
</description>
20663 <bitOffset>10</bitOffset>
20664 <bitWidth>1</bitWidth>
20668 <description>Filter bits
</description>
20669 <bitOffset>11</bitOffset>
20670 <bitWidth>1</bitWidth>
20674 <description>Filter bits
</description>
20675 <bitOffset>12</bitOffset>
20676 <bitWidth>1</bitWidth>
20680 <description>Filter bits
</description>
20681 <bitOffset>13</bitOffset>
20682 <bitWidth>1</bitWidth>
20686 <description>Filter bits
</description>
20687 <bitOffset>14</bitOffset>
20688 <bitWidth>1</bitWidth>
20692 <description>Filter bits
</description>
20693 <bitOffset>15</bitOffset>
20694 <bitWidth>1</bitWidth>
20698 <description>Filter bits
</description>
20699 <bitOffset>16</bitOffset>
20700 <bitWidth>1</bitWidth>
20704 <description>Filter bits
</description>
20705 <bitOffset>17</bitOffset>
20706 <bitWidth>1</bitWidth>
20710 <description>Filter bits
</description>
20711 <bitOffset>18</bitOffset>
20712 <bitWidth>1</bitWidth>
20716 <description>Filter bits
</description>
20717 <bitOffset>19</bitOffset>
20718 <bitWidth>1</bitWidth>
20722 <description>Filter bits
</description>
20723 <bitOffset>20</bitOffset>
20724 <bitWidth>1</bitWidth>
20728 <description>Filter bits
</description>
20729 <bitOffset>21</bitOffset>
20730 <bitWidth>1</bitWidth>
20734 <description>Filter bits
</description>
20735 <bitOffset>22</bitOffset>
20736 <bitWidth>1</bitWidth>
20740 <description>Filter bits
</description>
20741 <bitOffset>23</bitOffset>
20742 <bitWidth>1</bitWidth>
20746 <description>Filter bits
</description>
20747 <bitOffset>24</bitOffset>
20748 <bitWidth>1</bitWidth>
20752 <description>Filter bits
</description>
20753 <bitOffset>25</bitOffset>
20754 <bitWidth>1</bitWidth>
20758 <description>Filter bits
</description>
20759 <bitOffset>26</bitOffset>
20760 <bitWidth>1</bitWidth>
20764 <description>Filter bits
</description>
20765 <bitOffset>27</bitOffset>
20766 <bitWidth>1</bitWidth>
20770 <description>Filter bits
</description>
20771 <bitOffset>28</bitOffset>
20772 <bitWidth>1</bitWidth>
20776 <description>Filter bits
</description>
20777 <bitOffset>29</bitOffset>
20778 <bitWidth>1</bitWidth>
20782 <description>Filter bits
</description>
20783 <bitOffset>30</bitOffset>
20784 <bitWidth>1</bitWidth>
20788 <description>Filter bits
</description>
20789 <bitOffset>31</bitOffset>
20790 <bitWidth>1</bitWidth>
20796 <displayName>F14R1
</displayName>
20797 <description>Filter bank
14 register
1</description>
20798 <addressOffset>0x2B0</addressOffset>
20800 <access>read-write
</access>
20801 <resetValue>0x00000000</resetValue>
20805 <description>Filter bits
</description>
20806 <bitOffset>0</bitOffset>
20807 <bitWidth>1</bitWidth>
20811 <description>Filter bits
</description>
20812 <bitOffset>1</bitOffset>
20813 <bitWidth>1</bitWidth>
20817 <description>Filter bits
</description>
20818 <bitOffset>2</bitOffset>
20819 <bitWidth>1</bitWidth>
20823 <description>Filter bits
</description>
20824 <bitOffset>3</bitOffset>
20825 <bitWidth>1</bitWidth>
20829 <description>Filter bits
</description>
20830 <bitOffset>4</bitOffset>
20831 <bitWidth>1</bitWidth>
20835 <description>Filter bits
</description>
20836 <bitOffset>5</bitOffset>
20837 <bitWidth>1</bitWidth>
20841 <description>Filter bits
</description>
20842 <bitOffset>6</bitOffset>
20843 <bitWidth>1</bitWidth>
20847 <description>Filter bits
</description>
20848 <bitOffset>7</bitOffset>
20849 <bitWidth>1</bitWidth>
20853 <description>Filter bits
</description>
20854 <bitOffset>8</bitOffset>
20855 <bitWidth>1</bitWidth>
20859 <description>Filter bits
</description>
20860 <bitOffset>9</bitOffset>
20861 <bitWidth>1</bitWidth>
20865 <description>Filter bits
</description>
20866 <bitOffset>10</bitOffset>
20867 <bitWidth>1</bitWidth>
20871 <description>Filter bits
</description>
20872 <bitOffset>11</bitOffset>
20873 <bitWidth>1</bitWidth>
20877 <description>Filter bits
</description>
20878 <bitOffset>12</bitOffset>
20879 <bitWidth>1</bitWidth>
20883 <description>Filter bits
</description>
20884 <bitOffset>13</bitOffset>
20885 <bitWidth>1</bitWidth>
20889 <description>Filter bits
</description>
20890 <bitOffset>14</bitOffset>
20891 <bitWidth>1</bitWidth>
20895 <description>Filter bits
</description>
20896 <bitOffset>15</bitOffset>
20897 <bitWidth>1</bitWidth>
20901 <description>Filter bits
</description>
20902 <bitOffset>16</bitOffset>
20903 <bitWidth>1</bitWidth>
20907 <description>Filter bits
</description>
20908 <bitOffset>17</bitOffset>
20909 <bitWidth>1</bitWidth>
20913 <description>Filter bits
</description>
20914 <bitOffset>18</bitOffset>
20915 <bitWidth>1</bitWidth>
20919 <description>Filter bits
</description>
20920 <bitOffset>19</bitOffset>
20921 <bitWidth>1</bitWidth>
20925 <description>Filter bits
</description>
20926 <bitOffset>20</bitOffset>
20927 <bitWidth>1</bitWidth>
20931 <description>Filter bits
</description>
20932 <bitOffset>21</bitOffset>
20933 <bitWidth>1</bitWidth>
20937 <description>Filter bits
</description>
20938 <bitOffset>22</bitOffset>
20939 <bitWidth>1</bitWidth>
20943 <description>Filter bits
</description>
20944 <bitOffset>23</bitOffset>
20945 <bitWidth>1</bitWidth>
20949 <description>Filter bits
</description>
20950 <bitOffset>24</bitOffset>
20951 <bitWidth>1</bitWidth>
20955 <description>Filter bits
</description>
20956 <bitOffset>25</bitOffset>
20957 <bitWidth>1</bitWidth>
20961 <description>Filter bits
</description>
20962 <bitOffset>26</bitOffset>
20963 <bitWidth>1</bitWidth>
20967 <description>Filter bits
</description>
20968 <bitOffset>27</bitOffset>
20969 <bitWidth>1</bitWidth>
20973 <description>Filter bits
</description>
20974 <bitOffset>28</bitOffset>
20975 <bitWidth>1</bitWidth>
20979 <description>Filter bits
</description>
20980 <bitOffset>29</bitOffset>
20981 <bitWidth>1</bitWidth>
20985 <description>Filter bits
</description>
20986 <bitOffset>30</bitOffset>
20987 <bitWidth>1</bitWidth>
20991 <description>Filter bits
</description>
20992 <bitOffset>31</bitOffset>
20993 <bitWidth>1</bitWidth>
20999 <displayName>F14R2
</displayName>
21000 <description>Filter bank
14 register
2</description>
21001 <addressOffset>0x2B4</addressOffset>
21003 <access>read-write
</access>
21004 <resetValue>0x00000000</resetValue>
21008 <description>Filter bits
</description>
21009 <bitOffset>0</bitOffset>
21010 <bitWidth>1</bitWidth>
21014 <description>Filter bits
</description>
21015 <bitOffset>1</bitOffset>
21016 <bitWidth>1</bitWidth>
21020 <description>Filter bits
</description>
21021 <bitOffset>2</bitOffset>
21022 <bitWidth>1</bitWidth>
21026 <description>Filter bits
</description>
21027 <bitOffset>3</bitOffset>
21028 <bitWidth>1</bitWidth>
21032 <description>Filter bits
</description>
21033 <bitOffset>4</bitOffset>
21034 <bitWidth>1</bitWidth>
21038 <description>Filter bits
</description>
21039 <bitOffset>5</bitOffset>
21040 <bitWidth>1</bitWidth>
21044 <description>Filter bits
</description>
21045 <bitOffset>6</bitOffset>
21046 <bitWidth>1</bitWidth>
21050 <description>Filter bits
</description>
21051 <bitOffset>7</bitOffset>
21052 <bitWidth>1</bitWidth>
21056 <description>Filter bits
</description>
21057 <bitOffset>8</bitOffset>
21058 <bitWidth>1</bitWidth>
21062 <description>Filter bits
</description>
21063 <bitOffset>9</bitOffset>
21064 <bitWidth>1</bitWidth>
21068 <description>Filter bits
</description>
21069 <bitOffset>10</bitOffset>
21070 <bitWidth>1</bitWidth>
21074 <description>Filter bits
</description>
21075 <bitOffset>11</bitOffset>
21076 <bitWidth>1</bitWidth>
21080 <description>Filter bits
</description>
21081 <bitOffset>12</bitOffset>
21082 <bitWidth>1</bitWidth>
21086 <description>Filter bits
</description>
21087 <bitOffset>13</bitOffset>
21088 <bitWidth>1</bitWidth>
21092 <description>Filter bits
</description>
21093 <bitOffset>14</bitOffset>
21094 <bitWidth>1</bitWidth>
21098 <description>Filter bits
</description>
21099 <bitOffset>15</bitOffset>
21100 <bitWidth>1</bitWidth>
21104 <description>Filter bits
</description>
21105 <bitOffset>16</bitOffset>
21106 <bitWidth>1</bitWidth>
21110 <description>Filter bits
</description>
21111 <bitOffset>17</bitOffset>
21112 <bitWidth>1</bitWidth>
21116 <description>Filter bits
</description>
21117 <bitOffset>18</bitOffset>
21118 <bitWidth>1</bitWidth>
21122 <description>Filter bits
</description>
21123 <bitOffset>19</bitOffset>
21124 <bitWidth>1</bitWidth>
21128 <description>Filter bits
</description>
21129 <bitOffset>20</bitOffset>
21130 <bitWidth>1</bitWidth>
21134 <description>Filter bits
</description>
21135 <bitOffset>21</bitOffset>
21136 <bitWidth>1</bitWidth>
21140 <description>Filter bits
</description>
21141 <bitOffset>22</bitOffset>
21142 <bitWidth>1</bitWidth>
21146 <description>Filter bits
</description>
21147 <bitOffset>23</bitOffset>
21148 <bitWidth>1</bitWidth>
21152 <description>Filter bits
</description>
21153 <bitOffset>24</bitOffset>
21154 <bitWidth>1</bitWidth>
21158 <description>Filter bits
</description>
21159 <bitOffset>25</bitOffset>
21160 <bitWidth>1</bitWidth>
21164 <description>Filter bits
</description>
21165 <bitOffset>26</bitOffset>
21166 <bitWidth>1</bitWidth>
21170 <description>Filter bits
</description>
21171 <bitOffset>27</bitOffset>
21172 <bitWidth>1</bitWidth>
21176 <description>Filter bits
</description>
21177 <bitOffset>28</bitOffset>
21178 <bitWidth>1</bitWidth>
21182 <description>Filter bits
</description>
21183 <bitOffset>29</bitOffset>
21184 <bitWidth>1</bitWidth>
21188 <description>Filter bits
</description>
21189 <bitOffset>30</bitOffset>
21190 <bitWidth>1</bitWidth>
21194 <description>Filter bits
</description>
21195 <bitOffset>31</bitOffset>
21196 <bitWidth>1</bitWidth>
21202 <displayName>F15R1
</displayName>
21203 <description>Filter bank
15 register
1</description>
21204 <addressOffset>0x2B8</addressOffset>
21206 <access>read-write
</access>
21207 <resetValue>0x00000000</resetValue>
21211 <description>Filter bits
</description>
21212 <bitOffset>0</bitOffset>
21213 <bitWidth>1</bitWidth>
21217 <description>Filter bits
</description>
21218 <bitOffset>1</bitOffset>
21219 <bitWidth>1</bitWidth>
21223 <description>Filter bits
</description>
21224 <bitOffset>2</bitOffset>
21225 <bitWidth>1</bitWidth>
21229 <description>Filter bits
</description>
21230 <bitOffset>3</bitOffset>
21231 <bitWidth>1</bitWidth>
21235 <description>Filter bits
</description>
21236 <bitOffset>4</bitOffset>
21237 <bitWidth>1</bitWidth>
21241 <description>Filter bits
</description>
21242 <bitOffset>5</bitOffset>
21243 <bitWidth>1</bitWidth>
21247 <description>Filter bits
</description>
21248 <bitOffset>6</bitOffset>
21249 <bitWidth>1</bitWidth>
21253 <description>Filter bits
</description>
21254 <bitOffset>7</bitOffset>
21255 <bitWidth>1</bitWidth>
21259 <description>Filter bits
</description>
21260 <bitOffset>8</bitOffset>
21261 <bitWidth>1</bitWidth>
21265 <description>Filter bits
</description>
21266 <bitOffset>9</bitOffset>
21267 <bitWidth>1</bitWidth>
21271 <description>Filter bits
</description>
21272 <bitOffset>10</bitOffset>
21273 <bitWidth>1</bitWidth>
21277 <description>Filter bits
</description>
21278 <bitOffset>11</bitOffset>
21279 <bitWidth>1</bitWidth>
21283 <description>Filter bits
</description>
21284 <bitOffset>12</bitOffset>
21285 <bitWidth>1</bitWidth>
21289 <description>Filter bits
</description>
21290 <bitOffset>13</bitOffset>
21291 <bitWidth>1</bitWidth>
21295 <description>Filter bits
</description>
21296 <bitOffset>14</bitOffset>
21297 <bitWidth>1</bitWidth>
21301 <description>Filter bits
</description>
21302 <bitOffset>15</bitOffset>
21303 <bitWidth>1</bitWidth>
21307 <description>Filter bits
</description>
21308 <bitOffset>16</bitOffset>
21309 <bitWidth>1</bitWidth>
21313 <description>Filter bits
</description>
21314 <bitOffset>17</bitOffset>
21315 <bitWidth>1</bitWidth>
21319 <description>Filter bits
</description>
21320 <bitOffset>18</bitOffset>
21321 <bitWidth>1</bitWidth>
21325 <description>Filter bits
</description>
21326 <bitOffset>19</bitOffset>
21327 <bitWidth>1</bitWidth>
21331 <description>Filter bits
</description>
21332 <bitOffset>20</bitOffset>
21333 <bitWidth>1</bitWidth>
21337 <description>Filter bits
</description>
21338 <bitOffset>21</bitOffset>
21339 <bitWidth>1</bitWidth>
21343 <description>Filter bits
</description>
21344 <bitOffset>22</bitOffset>
21345 <bitWidth>1</bitWidth>
21349 <description>Filter bits
</description>
21350 <bitOffset>23</bitOffset>
21351 <bitWidth>1</bitWidth>
21355 <description>Filter bits
</description>
21356 <bitOffset>24</bitOffset>
21357 <bitWidth>1</bitWidth>
21361 <description>Filter bits
</description>
21362 <bitOffset>25</bitOffset>
21363 <bitWidth>1</bitWidth>
21367 <description>Filter bits
</description>
21368 <bitOffset>26</bitOffset>
21369 <bitWidth>1</bitWidth>
21373 <description>Filter bits
</description>
21374 <bitOffset>27</bitOffset>
21375 <bitWidth>1</bitWidth>
21379 <description>Filter bits
</description>
21380 <bitOffset>28</bitOffset>
21381 <bitWidth>1</bitWidth>
21385 <description>Filter bits
</description>
21386 <bitOffset>29</bitOffset>
21387 <bitWidth>1</bitWidth>
21391 <description>Filter bits
</description>
21392 <bitOffset>30</bitOffset>
21393 <bitWidth>1</bitWidth>
21397 <description>Filter bits
</description>
21398 <bitOffset>31</bitOffset>
21399 <bitWidth>1</bitWidth>
21405 <displayName>F15R2
</displayName>
21406 <description>Filter bank
15 register
2</description>
21407 <addressOffset>0x2BC</addressOffset>
21409 <access>read-write
</access>
21410 <resetValue>0x00000000</resetValue>
21414 <description>Filter bits
</description>
21415 <bitOffset>0</bitOffset>
21416 <bitWidth>1</bitWidth>
21420 <description>Filter bits
</description>
21421 <bitOffset>1</bitOffset>
21422 <bitWidth>1</bitWidth>
21426 <description>Filter bits
</description>
21427 <bitOffset>2</bitOffset>
21428 <bitWidth>1</bitWidth>
21432 <description>Filter bits
</description>
21433 <bitOffset>3</bitOffset>
21434 <bitWidth>1</bitWidth>
21438 <description>Filter bits
</description>
21439 <bitOffset>4</bitOffset>
21440 <bitWidth>1</bitWidth>
21444 <description>Filter bits
</description>
21445 <bitOffset>5</bitOffset>
21446 <bitWidth>1</bitWidth>
21450 <description>Filter bits
</description>
21451 <bitOffset>6</bitOffset>
21452 <bitWidth>1</bitWidth>
21456 <description>Filter bits
</description>
21457 <bitOffset>7</bitOffset>
21458 <bitWidth>1</bitWidth>
21462 <description>Filter bits
</description>
21463 <bitOffset>8</bitOffset>
21464 <bitWidth>1</bitWidth>
21468 <description>Filter bits
</description>
21469 <bitOffset>9</bitOffset>
21470 <bitWidth>1</bitWidth>
21474 <description>Filter bits
</description>
21475 <bitOffset>10</bitOffset>
21476 <bitWidth>1</bitWidth>
21480 <description>Filter bits
</description>
21481 <bitOffset>11</bitOffset>
21482 <bitWidth>1</bitWidth>
21486 <description>Filter bits
</description>
21487 <bitOffset>12</bitOffset>
21488 <bitWidth>1</bitWidth>
21492 <description>Filter bits
</description>
21493 <bitOffset>13</bitOffset>
21494 <bitWidth>1</bitWidth>
21498 <description>Filter bits
</description>
21499 <bitOffset>14</bitOffset>
21500 <bitWidth>1</bitWidth>
21504 <description>Filter bits
</description>
21505 <bitOffset>15</bitOffset>
21506 <bitWidth>1</bitWidth>
21510 <description>Filter bits
</description>
21511 <bitOffset>16</bitOffset>
21512 <bitWidth>1</bitWidth>
21516 <description>Filter bits
</description>
21517 <bitOffset>17</bitOffset>
21518 <bitWidth>1</bitWidth>
21522 <description>Filter bits
</description>
21523 <bitOffset>18</bitOffset>
21524 <bitWidth>1</bitWidth>
21528 <description>Filter bits
</description>
21529 <bitOffset>19</bitOffset>
21530 <bitWidth>1</bitWidth>
21534 <description>Filter bits
</description>
21535 <bitOffset>20</bitOffset>
21536 <bitWidth>1</bitWidth>
21540 <description>Filter bits
</description>
21541 <bitOffset>21</bitOffset>
21542 <bitWidth>1</bitWidth>
21546 <description>Filter bits
</description>
21547 <bitOffset>22</bitOffset>
21548 <bitWidth>1</bitWidth>
21552 <description>Filter bits
</description>
21553 <bitOffset>23</bitOffset>
21554 <bitWidth>1</bitWidth>
21558 <description>Filter bits
</description>
21559 <bitOffset>24</bitOffset>
21560 <bitWidth>1</bitWidth>
21564 <description>Filter bits
</description>
21565 <bitOffset>25</bitOffset>
21566 <bitWidth>1</bitWidth>
21570 <description>Filter bits
</description>
21571 <bitOffset>26</bitOffset>
21572 <bitWidth>1</bitWidth>
21576 <description>Filter bits
</description>
21577 <bitOffset>27</bitOffset>
21578 <bitWidth>1</bitWidth>
21582 <description>Filter bits
</description>
21583 <bitOffset>28</bitOffset>
21584 <bitWidth>1</bitWidth>
21588 <description>Filter bits
</description>
21589 <bitOffset>29</bitOffset>
21590 <bitWidth>1</bitWidth>
21594 <description>Filter bits
</description>
21595 <bitOffset>30</bitOffset>
21596 <bitWidth>1</bitWidth>
21600 <description>Filter bits
</description>
21601 <bitOffset>31</bitOffset>
21602 <bitWidth>1</bitWidth>
21608 <displayName>F16R1
</displayName>
21609 <description>Filter bank
16 register
1</description>
21610 <addressOffset>0x2C0</addressOffset>
21612 <access>read-write
</access>
21613 <resetValue>0x00000000</resetValue>
21617 <description>Filter bits
</description>
21618 <bitOffset>0</bitOffset>
21619 <bitWidth>1</bitWidth>
21623 <description>Filter bits
</description>
21624 <bitOffset>1</bitOffset>
21625 <bitWidth>1</bitWidth>
21629 <description>Filter bits
</description>
21630 <bitOffset>2</bitOffset>
21631 <bitWidth>1</bitWidth>
21635 <description>Filter bits
</description>
21636 <bitOffset>3</bitOffset>
21637 <bitWidth>1</bitWidth>
21641 <description>Filter bits
</description>
21642 <bitOffset>4</bitOffset>
21643 <bitWidth>1</bitWidth>
21647 <description>Filter bits
</description>
21648 <bitOffset>5</bitOffset>
21649 <bitWidth>1</bitWidth>
21653 <description>Filter bits
</description>
21654 <bitOffset>6</bitOffset>
21655 <bitWidth>1</bitWidth>
21659 <description>Filter bits
</description>
21660 <bitOffset>7</bitOffset>
21661 <bitWidth>1</bitWidth>
21665 <description>Filter bits
</description>
21666 <bitOffset>8</bitOffset>
21667 <bitWidth>1</bitWidth>
21671 <description>Filter bits
</description>
21672 <bitOffset>9</bitOffset>
21673 <bitWidth>1</bitWidth>
21677 <description>Filter bits
</description>
21678 <bitOffset>10</bitOffset>
21679 <bitWidth>1</bitWidth>
21683 <description>Filter bits
</description>
21684 <bitOffset>11</bitOffset>
21685 <bitWidth>1</bitWidth>
21689 <description>Filter bits
</description>
21690 <bitOffset>12</bitOffset>
21691 <bitWidth>1</bitWidth>
21695 <description>Filter bits
</description>
21696 <bitOffset>13</bitOffset>
21697 <bitWidth>1</bitWidth>
21701 <description>Filter bits
</description>
21702 <bitOffset>14</bitOffset>
21703 <bitWidth>1</bitWidth>
21707 <description>Filter bits
</description>
21708 <bitOffset>15</bitOffset>
21709 <bitWidth>1</bitWidth>
21713 <description>Filter bits
</description>
21714 <bitOffset>16</bitOffset>
21715 <bitWidth>1</bitWidth>
21719 <description>Filter bits
</description>
21720 <bitOffset>17</bitOffset>
21721 <bitWidth>1</bitWidth>
21725 <description>Filter bits
</description>
21726 <bitOffset>18</bitOffset>
21727 <bitWidth>1</bitWidth>
21731 <description>Filter bits
</description>
21732 <bitOffset>19</bitOffset>
21733 <bitWidth>1</bitWidth>
21737 <description>Filter bits
</description>
21738 <bitOffset>20</bitOffset>
21739 <bitWidth>1</bitWidth>
21743 <description>Filter bits
</description>
21744 <bitOffset>21</bitOffset>
21745 <bitWidth>1</bitWidth>
21749 <description>Filter bits
</description>
21750 <bitOffset>22</bitOffset>
21751 <bitWidth>1</bitWidth>
21755 <description>Filter bits
</description>
21756 <bitOffset>23</bitOffset>
21757 <bitWidth>1</bitWidth>
21761 <description>Filter bits
</description>
21762 <bitOffset>24</bitOffset>
21763 <bitWidth>1</bitWidth>
21767 <description>Filter bits
</description>
21768 <bitOffset>25</bitOffset>
21769 <bitWidth>1</bitWidth>
21773 <description>Filter bits
</description>
21774 <bitOffset>26</bitOffset>
21775 <bitWidth>1</bitWidth>
21779 <description>Filter bits
</description>
21780 <bitOffset>27</bitOffset>
21781 <bitWidth>1</bitWidth>
21785 <description>Filter bits
</description>
21786 <bitOffset>28</bitOffset>
21787 <bitWidth>1</bitWidth>
21791 <description>Filter bits
</description>
21792 <bitOffset>29</bitOffset>
21793 <bitWidth>1</bitWidth>
21797 <description>Filter bits
</description>
21798 <bitOffset>30</bitOffset>
21799 <bitWidth>1</bitWidth>
21803 <description>Filter bits
</description>
21804 <bitOffset>31</bitOffset>
21805 <bitWidth>1</bitWidth>
21811 <displayName>F16R2
</displayName>
21812 <description>Filter bank
16 register
2</description>
21813 <addressOffset>0x2C4</addressOffset>
21815 <access>read-write
</access>
21816 <resetValue>0x00000000</resetValue>
21820 <description>Filter bits
</description>
21821 <bitOffset>0</bitOffset>
21822 <bitWidth>1</bitWidth>
21826 <description>Filter bits
</description>
21827 <bitOffset>1</bitOffset>
21828 <bitWidth>1</bitWidth>
21832 <description>Filter bits
</description>
21833 <bitOffset>2</bitOffset>
21834 <bitWidth>1</bitWidth>
21838 <description>Filter bits
</description>
21839 <bitOffset>3</bitOffset>
21840 <bitWidth>1</bitWidth>
21844 <description>Filter bits
</description>
21845 <bitOffset>4</bitOffset>
21846 <bitWidth>1</bitWidth>
21850 <description>Filter bits
</description>
21851 <bitOffset>5</bitOffset>
21852 <bitWidth>1</bitWidth>
21856 <description>Filter bits
</description>
21857 <bitOffset>6</bitOffset>
21858 <bitWidth>1</bitWidth>
21862 <description>Filter bits
</description>
21863 <bitOffset>7</bitOffset>
21864 <bitWidth>1</bitWidth>
21868 <description>Filter bits
</description>
21869 <bitOffset>8</bitOffset>
21870 <bitWidth>1</bitWidth>
21874 <description>Filter bits
</description>
21875 <bitOffset>9</bitOffset>
21876 <bitWidth>1</bitWidth>
21880 <description>Filter bits
</description>
21881 <bitOffset>10</bitOffset>
21882 <bitWidth>1</bitWidth>
21886 <description>Filter bits
</description>
21887 <bitOffset>11</bitOffset>
21888 <bitWidth>1</bitWidth>
21892 <description>Filter bits
</description>
21893 <bitOffset>12</bitOffset>
21894 <bitWidth>1</bitWidth>
21898 <description>Filter bits
</description>
21899 <bitOffset>13</bitOffset>
21900 <bitWidth>1</bitWidth>
21904 <description>Filter bits
</description>
21905 <bitOffset>14</bitOffset>
21906 <bitWidth>1</bitWidth>
21910 <description>Filter bits
</description>
21911 <bitOffset>15</bitOffset>
21912 <bitWidth>1</bitWidth>
21916 <description>Filter bits
</description>
21917 <bitOffset>16</bitOffset>
21918 <bitWidth>1</bitWidth>
21922 <description>Filter bits
</description>
21923 <bitOffset>17</bitOffset>
21924 <bitWidth>1</bitWidth>
21928 <description>Filter bits
</description>
21929 <bitOffset>18</bitOffset>
21930 <bitWidth>1</bitWidth>
21934 <description>Filter bits
</description>
21935 <bitOffset>19</bitOffset>
21936 <bitWidth>1</bitWidth>
21940 <description>Filter bits
</description>
21941 <bitOffset>20</bitOffset>
21942 <bitWidth>1</bitWidth>
21946 <description>Filter bits
</description>
21947 <bitOffset>21</bitOffset>
21948 <bitWidth>1</bitWidth>
21952 <description>Filter bits
</description>
21953 <bitOffset>22</bitOffset>
21954 <bitWidth>1</bitWidth>
21958 <description>Filter bits
</description>
21959 <bitOffset>23</bitOffset>
21960 <bitWidth>1</bitWidth>
21964 <description>Filter bits
</description>
21965 <bitOffset>24</bitOffset>
21966 <bitWidth>1</bitWidth>
21970 <description>Filter bits
</description>
21971 <bitOffset>25</bitOffset>
21972 <bitWidth>1</bitWidth>
21976 <description>Filter bits
</description>
21977 <bitOffset>26</bitOffset>
21978 <bitWidth>1</bitWidth>
21982 <description>Filter bits
</description>
21983 <bitOffset>27</bitOffset>
21984 <bitWidth>1</bitWidth>
21988 <description>Filter bits
</description>
21989 <bitOffset>28</bitOffset>
21990 <bitWidth>1</bitWidth>
21994 <description>Filter bits
</description>
21995 <bitOffset>29</bitOffset>
21996 <bitWidth>1</bitWidth>
22000 <description>Filter bits
</description>
22001 <bitOffset>30</bitOffset>
22002 <bitWidth>1</bitWidth>
22006 <description>Filter bits
</description>
22007 <bitOffset>31</bitOffset>
22008 <bitWidth>1</bitWidth>
22014 <displayName>F17R1
</displayName>
22015 <description>Filter bank
17 register
1</description>
22016 <addressOffset>0x2C8</addressOffset>
22018 <access>read-write
</access>
22019 <resetValue>0x00000000</resetValue>
22023 <description>Filter bits
</description>
22024 <bitOffset>0</bitOffset>
22025 <bitWidth>1</bitWidth>
22029 <description>Filter bits
</description>
22030 <bitOffset>1</bitOffset>
22031 <bitWidth>1</bitWidth>
22035 <description>Filter bits
</description>
22036 <bitOffset>2</bitOffset>
22037 <bitWidth>1</bitWidth>
22041 <description>Filter bits
</description>
22042 <bitOffset>3</bitOffset>
22043 <bitWidth>1</bitWidth>
22047 <description>Filter bits
</description>
22048 <bitOffset>4</bitOffset>
22049 <bitWidth>1</bitWidth>
22053 <description>Filter bits
</description>
22054 <bitOffset>5</bitOffset>
22055 <bitWidth>1</bitWidth>
22059 <description>Filter bits
</description>
22060 <bitOffset>6</bitOffset>
22061 <bitWidth>1</bitWidth>
22065 <description>Filter bits
</description>
22066 <bitOffset>7</bitOffset>
22067 <bitWidth>1</bitWidth>
22071 <description>Filter bits
</description>
22072 <bitOffset>8</bitOffset>
22073 <bitWidth>1</bitWidth>
22077 <description>Filter bits
</description>
22078 <bitOffset>9</bitOffset>
22079 <bitWidth>1</bitWidth>
22083 <description>Filter bits
</description>
22084 <bitOffset>10</bitOffset>
22085 <bitWidth>1</bitWidth>
22089 <description>Filter bits
</description>
22090 <bitOffset>11</bitOffset>
22091 <bitWidth>1</bitWidth>
22095 <description>Filter bits
</description>
22096 <bitOffset>12</bitOffset>
22097 <bitWidth>1</bitWidth>
22101 <description>Filter bits
</description>
22102 <bitOffset>13</bitOffset>
22103 <bitWidth>1</bitWidth>
22107 <description>Filter bits
</description>
22108 <bitOffset>14</bitOffset>
22109 <bitWidth>1</bitWidth>
22113 <description>Filter bits
</description>
22114 <bitOffset>15</bitOffset>
22115 <bitWidth>1</bitWidth>
22119 <description>Filter bits
</description>
22120 <bitOffset>16</bitOffset>
22121 <bitWidth>1</bitWidth>
22125 <description>Filter bits
</description>
22126 <bitOffset>17</bitOffset>
22127 <bitWidth>1</bitWidth>
22131 <description>Filter bits
</description>
22132 <bitOffset>18</bitOffset>
22133 <bitWidth>1</bitWidth>
22137 <description>Filter bits
</description>
22138 <bitOffset>19</bitOffset>
22139 <bitWidth>1</bitWidth>
22143 <description>Filter bits
</description>
22144 <bitOffset>20</bitOffset>
22145 <bitWidth>1</bitWidth>
22149 <description>Filter bits
</description>
22150 <bitOffset>21</bitOffset>
22151 <bitWidth>1</bitWidth>
22155 <description>Filter bits
</description>
22156 <bitOffset>22</bitOffset>
22157 <bitWidth>1</bitWidth>
22161 <description>Filter bits
</description>
22162 <bitOffset>23</bitOffset>
22163 <bitWidth>1</bitWidth>
22167 <description>Filter bits
</description>
22168 <bitOffset>24</bitOffset>
22169 <bitWidth>1</bitWidth>
22173 <description>Filter bits
</description>
22174 <bitOffset>25</bitOffset>
22175 <bitWidth>1</bitWidth>
22179 <description>Filter bits
</description>
22180 <bitOffset>26</bitOffset>
22181 <bitWidth>1</bitWidth>
22185 <description>Filter bits
</description>
22186 <bitOffset>27</bitOffset>
22187 <bitWidth>1</bitWidth>
22191 <description>Filter bits
</description>
22192 <bitOffset>28</bitOffset>
22193 <bitWidth>1</bitWidth>
22197 <description>Filter bits
</description>
22198 <bitOffset>29</bitOffset>
22199 <bitWidth>1</bitWidth>
22203 <description>Filter bits
</description>
22204 <bitOffset>30</bitOffset>
22205 <bitWidth>1</bitWidth>
22209 <description>Filter bits
</description>
22210 <bitOffset>31</bitOffset>
22211 <bitWidth>1</bitWidth>
22217 <displayName>F17R2
</displayName>
22218 <description>Filter bank
17 register
2</description>
22219 <addressOffset>0x2CC</addressOffset>
22221 <access>read-write
</access>
22222 <resetValue>0x00000000</resetValue>
22226 <description>Filter bits
</description>
22227 <bitOffset>0</bitOffset>
22228 <bitWidth>1</bitWidth>
22232 <description>Filter bits
</description>
22233 <bitOffset>1</bitOffset>
22234 <bitWidth>1</bitWidth>
22238 <description>Filter bits
</description>
22239 <bitOffset>2</bitOffset>
22240 <bitWidth>1</bitWidth>
22244 <description>Filter bits
</description>
22245 <bitOffset>3</bitOffset>
22246 <bitWidth>1</bitWidth>
22250 <description>Filter bits
</description>
22251 <bitOffset>4</bitOffset>
22252 <bitWidth>1</bitWidth>
22256 <description>Filter bits
</description>
22257 <bitOffset>5</bitOffset>
22258 <bitWidth>1</bitWidth>
22262 <description>Filter bits
</description>
22263 <bitOffset>6</bitOffset>
22264 <bitWidth>1</bitWidth>
22268 <description>Filter bits
</description>
22269 <bitOffset>7</bitOffset>
22270 <bitWidth>1</bitWidth>
22274 <description>Filter bits
</description>
22275 <bitOffset>8</bitOffset>
22276 <bitWidth>1</bitWidth>
22280 <description>Filter bits
</description>
22281 <bitOffset>9</bitOffset>
22282 <bitWidth>1</bitWidth>
22286 <description>Filter bits
</description>
22287 <bitOffset>10</bitOffset>
22288 <bitWidth>1</bitWidth>
22292 <description>Filter bits
</description>
22293 <bitOffset>11</bitOffset>
22294 <bitWidth>1</bitWidth>
22298 <description>Filter bits
</description>
22299 <bitOffset>12</bitOffset>
22300 <bitWidth>1</bitWidth>
22304 <description>Filter bits
</description>
22305 <bitOffset>13</bitOffset>
22306 <bitWidth>1</bitWidth>
22310 <description>Filter bits
</description>
22311 <bitOffset>14</bitOffset>
22312 <bitWidth>1</bitWidth>
22316 <description>Filter bits
</description>
22317 <bitOffset>15</bitOffset>
22318 <bitWidth>1</bitWidth>
22322 <description>Filter bits
</description>
22323 <bitOffset>16</bitOffset>
22324 <bitWidth>1</bitWidth>
22328 <description>Filter bits
</description>
22329 <bitOffset>17</bitOffset>
22330 <bitWidth>1</bitWidth>
22334 <description>Filter bits
</description>
22335 <bitOffset>18</bitOffset>
22336 <bitWidth>1</bitWidth>
22340 <description>Filter bits
</description>
22341 <bitOffset>19</bitOffset>
22342 <bitWidth>1</bitWidth>
22346 <description>Filter bits
</description>
22347 <bitOffset>20</bitOffset>
22348 <bitWidth>1</bitWidth>
22352 <description>Filter bits
</description>
22353 <bitOffset>21</bitOffset>
22354 <bitWidth>1</bitWidth>
22358 <description>Filter bits
</description>
22359 <bitOffset>22</bitOffset>
22360 <bitWidth>1</bitWidth>
22364 <description>Filter bits
</description>
22365 <bitOffset>23</bitOffset>
22366 <bitWidth>1</bitWidth>
22370 <description>Filter bits
</description>
22371 <bitOffset>24</bitOffset>
22372 <bitWidth>1</bitWidth>
22376 <description>Filter bits
</description>
22377 <bitOffset>25</bitOffset>
22378 <bitWidth>1</bitWidth>
22382 <description>Filter bits
</description>
22383 <bitOffset>26</bitOffset>
22384 <bitWidth>1</bitWidth>
22388 <description>Filter bits
</description>
22389 <bitOffset>27</bitOffset>
22390 <bitWidth>1</bitWidth>
22394 <description>Filter bits
</description>
22395 <bitOffset>28</bitOffset>
22396 <bitWidth>1</bitWidth>
22400 <description>Filter bits
</description>
22401 <bitOffset>29</bitOffset>
22402 <bitWidth>1</bitWidth>
22406 <description>Filter bits
</description>
22407 <bitOffset>30</bitOffset>
22408 <bitWidth>1</bitWidth>
22412 <description>Filter bits
</description>
22413 <bitOffset>31</bitOffset>
22414 <bitWidth>1</bitWidth>
22420 <displayName>F18R1
</displayName>
22421 <description>Filter bank
18 register
1</description>
22422 <addressOffset>0x2D0</addressOffset>
22424 <access>read-write
</access>
22425 <resetValue>0x00000000</resetValue>
22429 <description>Filter bits
</description>
22430 <bitOffset>0</bitOffset>
22431 <bitWidth>1</bitWidth>
22435 <description>Filter bits
</description>
22436 <bitOffset>1</bitOffset>
22437 <bitWidth>1</bitWidth>
22441 <description>Filter bits
</description>
22442 <bitOffset>2</bitOffset>
22443 <bitWidth>1</bitWidth>
22447 <description>Filter bits
</description>
22448 <bitOffset>3</bitOffset>
22449 <bitWidth>1</bitWidth>
22453 <description>Filter bits
</description>
22454 <bitOffset>4</bitOffset>
22455 <bitWidth>1</bitWidth>
22459 <description>Filter bits
</description>
22460 <bitOffset>5</bitOffset>
22461 <bitWidth>1</bitWidth>
22465 <description>Filter bits
</description>
22466 <bitOffset>6</bitOffset>
22467 <bitWidth>1</bitWidth>
22471 <description>Filter bits
</description>
22472 <bitOffset>7</bitOffset>
22473 <bitWidth>1</bitWidth>
22477 <description>Filter bits
</description>
22478 <bitOffset>8</bitOffset>
22479 <bitWidth>1</bitWidth>
22483 <description>Filter bits
</description>
22484 <bitOffset>9</bitOffset>
22485 <bitWidth>1</bitWidth>
22489 <description>Filter bits
</description>
22490 <bitOffset>10</bitOffset>
22491 <bitWidth>1</bitWidth>
22495 <description>Filter bits
</description>
22496 <bitOffset>11</bitOffset>
22497 <bitWidth>1</bitWidth>
22501 <description>Filter bits
</description>
22502 <bitOffset>12</bitOffset>
22503 <bitWidth>1</bitWidth>
22507 <description>Filter bits
</description>
22508 <bitOffset>13</bitOffset>
22509 <bitWidth>1</bitWidth>
22513 <description>Filter bits
</description>
22514 <bitOffset>14</bitOffset>
22515 <bitWidth>1</bitWidth>
22519 <description>Filter bits
</description>
22520 <bitOffset>15</bitOffset>
22521 <bitWidth>1</bitWidth>
22525 <description>Filter bits
</description>
22526 <bitOffset>16</bitOffset>
22527 <bitWidth>1</bitWidth>
22531 <description>Filter bits
</description>
22532 <bitOffset>17</bitOffset>
22533 <bitWidth>1</bitWidth>
22537 <description>Filter bits
</description>
22538 <bitOffset>18</bitOffset>
22539 <bitWidth>1</bitWidth>
22543 <description>Filter bits
</description>
22544 <bitOffset>19</bitOffset>
22545 <bitWidth>1</bitWidth>
22549 <description>Filter bits
</description>
22550 <bitOffset>20</bitOffset>
22551 <bitWidth>1</bitWidth>
22555 <description>Filter bits
</description>
22556 <bitOffset>21</bitOffset>
22557 <bitWidth>1</bitWidth>
22561 <description>Filter bits
</description>
22562 <bitOffset>22</bitOffset>
22563 <bitWidth>1</bitWidth>
22567 <description>Filter bits
</description>
22568 <bitOffset>23</bitOffset>
22569 <bitWidth>1</bitWidth>
22573 <description>Filter bits
</description>
22574 <bitOffset>24</bitOffset>
22575 <bitWidth>1</bitWidth>
22579 <description>Filter bits
</description>
22580 <bitOffset>25</bitOffset>
22581 <bitWidth>1</bitWidth>
22585 <description>Filter bits
</description>
22586 <bitOffset>26</bitOffset>
22587 <bitWidth>1</bitWidth>
22591 <description>Filter bits
</description>
22592 <bitOffset>27</bitOffset>
22593 <bitWidth>1</bitWidth>
22597 <description>Filter bits
</description>
22598 <bitOffset>28</bitOffset>
22599 <bitWidth>1</bitWidth>
22603 <description>Filter bits
</description>
22604 <bitOffset>29</bitOffset>
22605 <bitWidth>1</bitWidth>
22609 <description>Filter bits
</description>
22610 <bitOffset>30</bitOffset>
22611 <bitWidth>1</bitWidth>
22615 <description>Filter bits
</description>
22616 <bitOffset>31</bitOffset>
22617 <bitWidth>1</bitWidth>
22623 <displayName>F18R2
</displayName>
22624 <description>Filter bank
18 register
2</description>
22625 <addressOffset>0x2D4</addressOffset>
22627 <access>read-write
</access>
22628 <resetValue>0x00000000</resetValue>
22632 <description>Filter bits
</description>
22633 <bitOffset>0</bitOffset>
22634 <bitWidth>1</bitWidth>
22638 <description>Filter bits
</description>
22639 <bitOffset>1</bitOffset>
22640 <bitWidth>1</bitWidth>
22644 <description>Filter bits
</description>
22645 <bitOffset>2</bitOffset>
22646 <bitWidth>1</bitWidth>
22650 <description>Filter bits
</description>
22651 <bitOffset>3</bitOffset>
22652 <bitWidth>1</bitWidth>
22656 <description>Filter bits
</description>
22657 <bitOffset>4</bitOffset>
22658 <bitWidth>1</bitWidth>
22662 <description>Filter bits
</description>
22663 <bitOffset>5</bitOffset>
22664 <bitWidth>1</bitWidth>
22668 <description>Filter bits
</description>
22669 <bitOffset>6</bitOffset>
22670 <bitWidth>1</bitWidth>
22674 <description>Filter bits
</description>
22675 <bitOffset>7</bitOffset>
22676 <bitWidth>1</bitWidth>
22680 <description>Filter bits
</description>
22681 <bitOffset>8</bitOffset>
22682 <bitWidth>1</bitWidth>
22686 <description>Filter bits
</description>
22687 <bitOffset>9</bitOffset>
22688 <bitWidth>1</bitWidth>
22692 <description>Filter bits
</description>
22693 <bitOffset>10</bitOffset>
22694 <bitWidth>1</bitWidth>
22698 <description>Filter bits
</description>
22699 <bitOffset>11</bitOffset>
22700 <bitWidth>1</bitWidth>
22704 <description>Filter bits
</description>
22705 <bitOffset>12</bitOffset>
22706 <bitWidth>1</bitWidth>
22710 <description>Filter bits
</description>
22711 <bitOffset>13</bitOffset>
22712 <bitWidth>1</bitWidth>
22716 <description>Filter bits
</description>
22717 <bitOffset>14</bitOffset>
22718 <bitWidth>1</bitWidth>
22722 <description>Filter bits
</description>
22723 <bitOffset>15</bitOffset>
22724 <bitWidth>1</bitWidth>
22728 <description>Filter bits
</description>
22729 <bitOffset>16</bitOffset>
22730 <bitWidth>1</bitWidth>
22734 <description>Filter bits
</description>
22735 <bitOffset>17</bitOffset>
22736 <bitWidth>1</bitWidth>
22740 <description>Filter bits
</description>
22741 <bitOffset>18</bitOffset>
22742 <bitWidth>1</bitWidth>
22746 <description>Filter bits
</description>
22747 <bitOffset>19</bitOffset>
22748 <bitWidth>1</bitWidth>
22752 <description>Filter bits
</description>
22753 <bitOffset>20</bitOffset>
22754 <bitWidth>1</bitWidth>
22758 <description>Filter bits
</description>
22759 <bitOffset>21</bitOffset>
22760 <bitWidth>1</bitWidth>
22764 <description>Filter bits
</description>
22765 <bitOffset>22</bitOffset>
22766 <bitWidth>1</bitWidth>
22770 <description>Filter bits
</description>
22771 <bitOffset>23</bitOffset>
22772 <bitWidth>1</bitWidth>
22776 <description>Filter bits
</description>
22777 <bitOffset>24</bitOffset>
22778 <bitWidth>1</bitWidth>
22782 <description>Filter bits
</description>
22783 <bitOffset>25</bitOffset>
22784 <bitWidth>1</bitWidth>
22788 <description>Filter bits
</description>
22789 <bitOffset>26</bitOffset>
22790 <bitWidth>1</bitWidth>
22794 <description>Filter bits
</description>
22795 <bitOffset>27</bitOffset>
22796 <bitWidth>1</bitWidth>
22800 <description>Filter bits
</description>
22801 <bitOffset>28</bitOffset>
22802 <bitWidth>1</bitWidth>
22806 <description>Filter bits
</description>
22807 <bitOffset>29</bitOffset>
22808 <bitWidth>1</bitWidth>
22812 <description>Filter bits
</description>
22813 <bitOffset>30</bitOffset>
22814 <bitWidth>1</bitWidth>
22818 <description>Filter bits
</description>
22819 <bitOffset>31</bitOffset>
22820 <bitWidth>1</bitWidth>
22826 <displayName>F19R1
</displayName>
22827 <description>Filter bank
19 register
1</description>
22828 <addressOffset>0x2D8</addressOffset>
22830 <access>read-write
</access>
22831 <resetValue>0x00000000</resetValue>
22835 <description>Filter bits
</description>
22836 <bitOffset>0</bitOffset>
22837 <bitWidth>1</bitWidth>
22841 <description>Filter bits
</description>
22842 <bitOffset>1</bitOffset>
22843 <bitWidth>1</bitWidth>
22847 <description>Filter bits
</description>
22848 <bitOffset>2</bitOffset>
22849 <bitWidth>1</bitWidth>
22853 <description>Filter bits
</description>
22854 <bitOffset>3</bitOffset>
22855 <bitWidth>1</bitWidth>
22859 <description>Filter bits
</description>
22860 <bitOffset>4</bitOffset>
22861 <bitWidth>1</bitWidth>
22865 <description>Filter bits
</description>
22866 <bitOffset>5</bitOffset>
22867 <bitWidth>1</bitWidth>
22871 <description>Filter bits
</description>
22872 <bitOffset>6</bitOffset>
22873 <bitWidth>1</bitWidth>
22877 <description>Filter bits
</description>
22878 <bitOffset>7</bitOffset>
22879 <bitWidth>1</bitWidth>
22883 <description>Filter bits
</description>
22884 <bitOffset>8</bitOffset>
22885 <bitWidth>1</bitWidth>
22889 <description>Filter bits
</description>
22890 <bitOffset>9</bitOffset>
22891 <bitWidth>1</bitWidth>
22895 <description>Filter bits
</description>
22896 <bitOffset>10</bitOffset>
22897 <bitWidth>1</bitWidth>
22901 <description>Filter bits
</description>
22902 <bitOffset>11</bitOffset>
22903 <bitWidth>1</bitWidth>
22907 <description>Filter bits
</description>
22908 <bitOffset>12</bitOffset>
22909 <bitWidth>1</bitWidth>
22913 <description>Filter bits
</description>
22914 <bitOffset>13</bitOffset>
22915 <bitWidth>1</bitWidth>
22919 <description>Filter bits
</description>
22920 <bitOffset>14</bitOffset>
22921 <bitWidth>1</bitWidth>
22925 <description>Filter bits
</description>
22926 <bitOffset>15</bitOffset>
22927 <bitWidth>1</bitWidth>
22931 <description>Filter bits
</description>
22932 <bitOffset>16</bitOffset>
22933 <bitWidth>1</bitWidth>
22937 <description>Filter bits
</description>
22938 <bitOffset>17</bitOffset>
22939 <bitWidth>1</bitWidth>
22943 <description>Filter bits
</description>
22944 <bitOffset>18</bitOffset>
22945 <bitWidth>1</bitWidth>
22949 <description>Filter bits
</description>
22950 <bitOffset>19</bitOffset>
22951 <bitWidth>1</bitWidth>
22955 <description>Filter bits
</description>
22956 <bitOffset>20</bitOffset>
22957 <bitWidth>1</bitWidth>
22961 <description>Filter bits
</description>
22962 <bitOffset>21</bitOffset>
22963 <bitWidth>1</bitWidth>
22967 <description>Filter bits
</description>
22968 <bitOffset>22</bitOffset>
22969 <bitWidth>1</bitWidth>
22973 <description>Filter bits
</description>
22974 <bitOffset>23</bitOffset>
22975 <bitWidth>1</bitWidth>
22979 <description>Filter bits
</description>
22980 <bitOffset>24</bitOffset>
22981 <bitWidth>1</bitWidth>
22985 <description>Filter bits
</description>
22986 <bitOffset>25</bitOffset>
22987 <bitWidth>1</bitWidth>
22991 <description>Filter bits
</description>
22992 <bitOffset>26</bitOffset>
22993 <bitWidth>1</bitWidth>
22997 <description>Filter bits
</description>
22998 <bitOffset>27</bitOffset>
22999 <bitWidth>1</bitWidth>
23003 <description>Filter bits
</description>
23004 <bitOffset>28</bitOffset>
23005 <bitWidth>1</bitWidth>
23009 <description>Filter bits
</description>
23010 <bitOffset>29</bitOffset>
23011 <bitWidth>1</bitWidth>
23015 <description>Filter bits
</description>
23016 <bitOffset>30</bitOffset>
23017 <bitWidth>1</bitWidth>
23021 <description>Filter bits
</description>
23022 <bitOffset>31</bitOffset>
23023 <bitWidth>1</bitWidth>
23029 <displayName>F19R2
</displayName>
23030 <description>Filter bank
19 register
2</description>
23031 <addressOffset>0x2DC</addressOffset>
23033 <access>read-write
</access>
23034 <resetValue>0x00000000</resetValue>
23038 <description>Filter bits
</description>
23039 <bitOffset>0</bitOffset>
23040 <bitWidth>1</bitWidth>
23044 <description>Filter bits
</description>
23045 <bitOffset>1</bitOffset>
23046 <bitWidth>1</bitWidth>
23050 <description>Filter bits
</description>
23051 <bitOffset>2</bitOffset>
23052 <bitWidth>1</bitWidth>
23056 <description>Filter bits
</description>
23057 <bitOffset>3</bitOffset>
23058 <bitWidth>1</bitWidth>
23062 <description>Filter bits
</description>
23063 <bitOffset>4</bitOffset>
23064 <bitWidth>1</bitWidth>
23068 <description>Filter bits
</description>
23069 <bitOffset>5</bitOffset>
23070 <bitWidth>1</bitWidth>
23074 <description>Filter bits
</description>
23075 <bitOffset>6</bitOffset>
23076 <bitWidth>1</bitWidth>
23080 <description>Filter bits
</description>
23081 <bitOffset>7</bitOffset>
23082 <bitWidth>1</bitWidth>
23086 <description>Filter bits
</description>
23087 <bitOffset>8</bitOffset>
23088 <bitWidth>1</bitWidth>
23092 <description>Filter bits
</description>
23093 <bitOffset>9</bitOffset>
23094 <bitWidth>1</bitWidth>
23098 <description>Filter bits
</description>
23099 <bitOffset>10</bitOffset>
23100 <bitWidth>1</bitWidth>
23104 <description>Filter bits
</description>
23105 <bitOffset>11</bitOffset>
23106 <bitWidth>1</bitWidth>
23110 <description>Filter bits
</description>
23111 <bitOffset>12</bitOffset>
23112 <bitWidth>1</bitWidth>
23116 <description>Filter bits
</description>
23117 <bitOffset>13</bitOffset>
23118 <bitWidth>1</bitWidth>
23122 <description>Filter bits
</description>
23123 <bitOffset>14</bitOffset>
23124 <bitWidth>1</bitWidth>
23128 <description>Filter bits
</description>
23129 <bitOffset>15</bitOffset>
23130 <bitWidth>1</bitWidth>
23134 <description>Filter bits
</description>
23135 <bitOffset>16</bitOffset>
23136 <bitWidth>1</bitWidth>
23140 <description>Filter bits
</description>
23141 <bitOffset>17</bitOffset>
23142 <bitWidth>1</bitWidth>
23146 <description>Filter bits
</description>
23147 <bitOffset>18</bitOffset>
23148 <bitWidth>1</bitWidth>
23152 <description>Filter bits
</description>
23153 <bitOffset>19</bitOffset>
23154 <bitWidth>1</bitWidth>
23158 <description>Filter bits
</description>
23159 <bitOffset>20</bitOffset>
23160 <bitWidth>1</bitWidth>
23164 <description>Filter bits
</description>
23165 <bitOffset>21</bitOffset>
23166 <bitWidth>1</bitWidth>
23170 <description>Filter bits
</description>
23171 <bitOffset>22</bitOffset>
23172 <bitWidth>1</bitWidth>
23176 <description>Filter bits
</description>
23177 <bitOffset>23</bitOffset>
23178 <bitWidth>1</bitWidth>
23182 <description>Filter bits
</description>
23183 <bitOffset>24</bitOffset>
23184 <bitWidth>1</bitWidth>
23188 <description>Filter bits
</description>
23189 <bitOffset>25</bitOffset>
23190 <bitWidth>1</bitWidth>
23194 <description>Filter bits
</description>
23195 <bitOffset>26</bitOffset>
23196 <bitWidth>1</bitWidth>
23200 <description>Filter bits
</description>
23201 <bitOffset>27</bitOffset>
23202 <bitWidth>1</bitWidth>
23206 <description>Filter bits
</description>
23207 <bitOffset>28</bitOffset>
23208 <bitWidth>1</bitWidth>
23212 <description>Filter bits
</description>
23213 <bitOffset>29</bitOffset>
23214 <bitWidth>1</bitWidth>
23218 <description>Filter bits
</description>
23219 <bitOffset>30</bitOffset>
23220 <bitWidth>1</bitWidth>
23224 <description>Filter bits
</description>
23225 <bitOffset>31</bitOffset>
23226 <bitWidth>1</bitWidth>
23232 <displayName>F20R1
</displayName>
23233 <description>Filter bank
20 register
1</description>
23234 <addressOffset>0x2E0</addressOffset>
23236 <access>read-write
</access>
23237 <resetValue>0x00000000</resetValue>
23241 <description>Filter bits
</description>
23242 <bitOffset>0</bitOffset>
23243 <bitWidth>1</bitWidth>
23247 <description>Filter bits
</description>
23248 <bitOffset>1</bitOffset>
23249 <bitWidth>1</bitWidth>
23253 <description>Filter bits
</description>
23254 <bitOffset>2</bitOffset>
23255 <bitWidth>1</bitWidth>
23259 <description>Filter bits
</description>
23260 <bitOffset>3</bitOffset>
23261 <bitWidth>1</bitWidth>
23265 <description>Filter bits
</description>
23266 <bitOffset>4</bitOffset>
23267 <bitWidth>1</bitWidth>
23271 <description>Filter bits
</description>
23272 <bitOffset>5</bitOffset>
23273 <bitWidth>1</bitWidth>
23277 <description>Filter bits
</description>
23278 <bitOffset>6</bitOffset>
23279 <bitWidth>1</bitWidth>
23283 <description>Filter bits
</description>
23284 <bitOffset>7</bitOffset>
23285 <bitWidth>1</bitWidth>
23289 <description>Filter bits
</description>
23290 <bitOffset>8</bitOffset>
23291 <bitWidth>1</bitWidth>
23295 <description>Filter bits
</description>
23296 <bitOffset>9</bitOffset>
23297 <bitWidth>1</bitWidth>
23301 <description>Filter bits
</description>
23302 <bitOffset>10</bitOffset>
23303 <bitWidth>1</bitWidth>
23307 <description>Filter bits
</description>
23308 <bitOffset>11</bitOffset>
23309 <bitWidth>1</bitWidth>
23313 <description>Filter bits
</description>
23314 <bitOffset>12</bitOffset>
23315 <bitWidth>1</bitWidth>
23319 <description>Filter bits
</description>
23320 <bitOffset>13</bitOffset>
23321 <bitWidth>1</bitWidth>
23325 <description>Filter bits
</description>
23326 <bitOffset>14</bitOffset>
23327 <bitWidth>1</bitWidth>
23331 <description>Filter bits
</description>
23332 <bitOffset>15</bitOffset>
23333 <bitWidth>1</bitWidth>
23337 <description>Filter bits
</description>
23338 <bitOffset>16</bitOffset>
23339 <bitWidth>1</bitWidth>
23343 <description>Filter bits
</description>
23344 <bitOffset>17</bitOffset>
23345 <bitWidth>1</bitWidth>
23349 <description>Filter bits
</description>
23350 <bitOffset>18</bitOffset>
23351 <bitWidth>1</bitWidth>
23355 <description>Filter bits
</description>
23356 <bitOffset>19</bitOffset>
23357 <bitWidth>1</bitWidth>
23361 <description>Filter bits
</description>
23362 <bitOffset>20</bitOffset>
23363 <bitWidth>1</bitWidth>
23367 <description>Filter bits
</description>
23368 <bitOffset>21</bitOffset>
23369 <bitWidth>1</bitWidth>
23373 <description>Filter bits
</description>
23374 <bitOffset>22</bitOffset>
23375 <bitWidth>1</bitWidth>
23379 <description>Filter bits
</description>
23380 <bitOffset>23</bitOffset>
23381 <bitWidth>1</bitWidth>
23385 <description>Filter bits
</description>
23386 <bitOffset>24</bitOffset>
23387 <bitWidth>1</bitWidth>
23391 <description>Filter bits
</description>
23392 <bitOffset>25</bitOffset>
23393 <bitWidth>1</bitWidth>
23397 <description>Filter bits
</description>
23398 <bitOffset>26</bitOffset>
23399 <bitWidth>1</bitWidth>
23403 <description>Filter bits
</description>
23404 <bitOffset>27</bitOffset>
23405 <bitWidth>1</bitWidth>
23409 <description>Filter bits
</description>
23410 <bitOffset>28</bitOffset>
23411 <bitWidth>1</bitWidth>
23415 <description>Filter bits
</description>
23416 <bitOffset>29</bitOffset>
23417 <bitWidth>1</bitWidth>
23421 <description>Filter bits
</description>
23422 <bitOffset>30</bitOffset>
23423 <bitWidth>1</bitWidth>
23427 <description>Filter bits
</description>
23428 <bitOffset>31</bitOffset>
23429 <bitWidth>1</bitWidth>
23435 <displayName>F20R2
</displayName>
23436 <description>Filter bank
20 register
2</description>
23437 <addressOffset>0x2E4</addressOffset>
23439 <access>read-write
</access>
23440 <resetValue>0x00000000</resetValue>
23444 <description>Filter bits
</description>
23445 <bitOffset>0</bitOffset>
23446 <bitWidth>1</bitWidth>
23450 <description>Filter bits
</description>
23451 <bitOffset>1</bitOffset>
23452 <bitWidth>1</bitWidth>
23456 <description>Filter bits
</description>
23457 <bitOffset>2</bitOffset>
23458 <bitWidth>1</bitWidth>
23462 <description>Filter bits
</description>
23463 <bitOffset>3</bitOffset>
23464 <bitWidth>1</bitWidth>
23468 <description>Filter bits
</description>
23469 <bitOffset>4</bitOffset>
23470 <bitWidth>1</bitWidth>
23474 <description>Filter bits
</description>
23475 <bitOffset>5</bitOffset>
23476 <bitWidth>1</bitWidth>
23480 <description>Filter bits
</description>
23481 <bitOffset>6</bitOffset>
23482 <bitWidth>1</bitWidth>
23486 <description>Filter bits
</description>
23487 <bitOffset>7</bitOffset>
23488 <bitWidth>1</bitWidth>
23492 <description>Filter bits
</description>
23493 <bitOffset>8</bitOffset>
23494 <bitWidth>1</bitWidth>
23498 <description>Filter bits
</description>
23499 <bitOffset>9</bitOffset>
23500 <bitWidth>1</bitWidth>
23504 <description>Filter bits
</description>
23505 <bitOffset>10</bitOffset>
23506 <bitWidth>1</bitWidth>
23510 <description>Filter bits
</description>
23511 <bitOffset>11</bitOffset>
23512 <bitWidth>1</bitWidth>
23516 <description>Filter bits
</description>
23517 <bitOffset>12</bitOffset>
23518 <bitWidth>1</bitWidth>
23522 <description>Filter bits
</description>
23523 <bitOffset>13</bitOffset>
23524 <bitWidth>1</bitWidth>
23528 <description>Filter bits
</description>
23529 <bitOffset>14</bitOffset>
23530 <bitWidth>1</bitWidth>
23534 <description>Filter bits
</description>
23535 <bitOffset>15</bitOffset>
23536 <bitWidth>1</bitWidth>
23540 <description>Filter bits
</description>
23541 <bitOffset>16</bitOffset>
23542 <bitWidth>1</bitWidth>
23546 <description>Filter bits
</description>
23547 <bitOffset>17</bitOffset>
23548 <bitWidth>1</bitWidth>
23552 <description>Filter bits
</description>
23553 <bitOffset>18</bitOffset>
23554 <bitWidth>1</bitWidth>
23558 <description>Filter bits
</description>
23559 <bitOffset>19</bitOffset>
23560 <bitWidth>1</bitWidth>
23564 <description>Filter bits
</description>
23565 <bitOffset>20</bitOffset>
23566 <bitWidth>1</bitWidth>
23570 <description>Filter bits
</description>
23571 <bitOffset>21</bitOffset>
23572 <bitWidth>1</bitWidth>
23576 <description>Filter bits
</description>
23577 <bitOffset>22</bitOffset>
23578 <bitWidth>1</bitWidth>
23582 <description>Filter bits
</description>
23583 <bitOffset>23</bitOffset>
23584 <bitWidth>1</bitWidth>
23588 <description>Filter bits
</description>
23589 <bitOffset>24</bitOffset>
23590 <bitWidth>1</bitWidth>
23594 <description>Filter bits
</description>
23595 <bitOffset>25</bitOffset>
23596 <bitWidth>1</bitWidth>
23600 <description>Filter bits
</description>
23601 <bitOffset>26</bitOffset>
23602 <bitWidth>1</bitWidth>
23606 <description>Filter bits
</description>
23607 <bitOffset>27</bitOffset>
23608 <bitWidth>1</bitWidth>
23612 <description>Filter bits
</description>
23613 <bitOffset>28</bitOffset>
23614 <bitWidth>1</bitWidth>
23618 <description>Filter bits
</description>
23619 <bitOffset>29</bitOffset>
23620 <bitWidth>1</bitWidth>
23624 <description>Filter bits
</description>
23625 <bitOffset>30</bitOffset>
23626 <bitWidth>1</bitWidth>
23630 <description>Filter bits
</description>
23631 <bitOffset>31</bitOffset>
23632 <bitWidth>1</bitWidth>
23638 <displayName>F21R1
</displayName>
23639 <description>Filter bank
21 register
1</description>
23640 <addressOffset>0x2E8</addressOffset>
23642 <access>read-write
</access>
23643 <resetValue>0x00000000</resetValue>
23647 <description>Filter bits
</description>
23648 <bitOffset>0</bitOffset>
23649 <bitWidth>1</bitWidth>
23653 <description>Filter bits
</description>
23654 <bitOffset>1</bitOffset>
23655 <bitWidth>1</bitWidth>
23659 <description>Filter bits
</description>
23660 <bitOffset>2</bitOffset>
23661 <bitWidth>1</bitWidth>
23665 <description>Filter bits
</description>
23666 <bitOffset>3</bitOffset>
23667 <bitWidth>1</bitWidth>
23671 <description>Filter bits
</description>
23672 <bitOffset>4</bitOffset>
23673 <bitWidth>1</bitWidth>
23677 <description>Filter bits
</description>
23678 <bitOffset>5</bitOffset>
23679 <bitWidth>1</bitWidth>
23683 <description>Filter bits
</description>
23684 <bitOffset>6</bitOffset>
23685 <bitWidth>1</bitWidth>
23689 <description>Filter bits
</description>
23690 <bitOffset>7</bitOffset>
23691 <bitWidth>1</bitWidth>
23695 <description>Filter bits
</description>
23696 <bitOffset>8</bitOffset>
23697 <bitWidth>1</bitWidth>
23701 <description>Filter bits
</description>
23702 <bitOffset>9</bitOffset>
23703 <bitWidth>1</bitWidth>
23707 <description>Filter bits
</description>
23708 <bitOffset>10</bitOffset>
23709 <bitWidth>1</bitWidth>
23713 <description>Filter bits
</description>
23714 <bitOffset>11</bitOffset>
23715 <bitWidth>1</bitWidth>
23719 <description>Filter bits
</description>
23720 <bitOffset>12</bitOffset>
23721 <bitWidth>1</bitWidth>
23725 <description>Filter bits
</description>
23726 <bitOffset>13</bitOffset>
23727 <bitWidth>1</bitWidth>
23731 <description>Filter bits
</description>
23732 <bitOffset>14</bitOffset>
23733 <bitWidth>1</bitWidth>
23737 <description>Filter bits
</description>
23738 <bitOffset>15</bitOffset>
23739 <bitWidth>1</bitWidth>
23743 <description>Filter bits
</description>
23744 <bitOffset>16</bitOffset>
23745 <bitWidth>1</bitWidth>
23749 <description>Filter bits
</description>
23750 <bitOffset>17</bitOffset>
23751 <bitWidth>1</bitWidth>
23755 <description>Filter bits
</description>
23756 <bitOffset>18</bitOffset>
23757 <bitWidth>1</bitWidth>
23761 <description>Filter bits
</description>
23762 <bitOffset>19</bitOffset>
23763 <bitWidth>1</bitWidth>
23767 <description>Filter bits
</description>
23768 <bitOffset>20</bitOffset>
23769 <bitWidth>1</bitWidth>
23773 <description>Filter bits
</description>
23774 <bitOffset>21</bitOffset>
23775 <bitWidth>1</bitWidth>
23779 <description>Filter bits
</description>
23780 <bitOffset>22</bitOffset>
23781 <bitWidth>1</bitWidth>
23785 <description>Filter bits
</description>
23786 <bitOffset>23</bitOffset>
23787 <bitWidth>1</bitWidth>
23791 <description>Filter bits
</description>
23792 <bitOffset>24</bitOffset>
23793 <bitWidth>1</bitWidth>
23797 <description>Filter bits
</description>
23798 <bitOffset>25</bitOffset>
23799 <bitWidth>1</bitWidth>
23803 <description>Filter bits
</description>
23804 <bitOffset>26</bitOffset>
23805 <bitWidth>1</bitWidth>
23809 <description>Filter bits
</description>
23810 <bitOffset>27</bitOffset>
23811 <bitWidth>1</bitWidth>
23815 <description>Filter bits
</description>
23816 <bitOffset>28</bitOffset>
23817 <bitWidth>1</bitWidth>
23821 <description>Filter bits
</description>
23822 <bitOffset>29</bitOffset>
23823 <bitWidth>1</bitWidth>
23827 <description>Filter bits
</description>
23828 <bitOffset>30</bitOffset>
23829 <bitWidth>1</bitWidth>
23833 <description>Filter bits
</description>
23834 <bitOffset>31</bitOffset>
23835 <bitWidth>1</bitWidth>
23841 <displayName>F21R2
</displayName>
23842 <description>Filter bank
21 register
2</description>
23843 <addressOffset>0x2EC</addressOffset>
23845 <access>read-write
</access>
23846 <resetValue>0x00000000</resetValue>
23850 <description>Filter bits
</description>
23851 <bitOffset>0</bitOffset>
23852 <bitWidth>1</bitWidth>
23856 <description>Filter bits
</description>
23857 <bitOffset>1</bitOffset>
23858 <bitWidth>1</bitWidth>
23862 <description>Filter bits
</description>
23863 <bitOffset>2</bitOffset>
23864 <bitWidth>1</bitWidth>
23868 <description>Filter bits
</description>
23869 <bitOffset>3</bitOffset>
23870 <bitWidth>1</bitWidth>
23874 <description>Filter bits
</description>
23875 <bitOffset>4</bitOffset>
23876 <bitWidth>1</bitWidth>
23880 <description>Filter bits
</description>
23881 <bitOffset>5</bitOffset>
23882 <bitWidth>1</bitWidth>
23886 <description>Filter bits
</description>
23887 <bitOffset>6</bitOffset>
23888 <bitWidth>1</bitWidth>
23892 <description>Filter bits
</description>
23893 <bitOffset>7</bitOffset>
23894 <bitWidth>1</bitWidth>
23898 <description>Filter bits
</description>
23899 <bitOffset>8</bitOffset>
23900 <bitWidth>1</bitWidth>
23904 <description>Filter bits
</description>
23905 <bitOffset>9</bitOffset>
23906 <bitWidth>1</bitWidth>
23910 <description>Filter bits
</description>
23911 <bitOffset>10</bitOffset>
23912 <bitWidth>1</bitWidth>
23916 <description>Filter bits
</description>
23917 <bitOffset>11</bitOffset>
23918 <bitWidth>1</bitWidth>
23922 <description>Filter bits
</description>
23923 <bitOffset>12</bitOffset>
23924 <bitWidth>1</bitWidth>
23928 <description>Filter bits
</description>
23929 <bitOffset>13</bitOffset>
23930 <bitWidth>1</bitWidth>
23934 <description>Filter bits
</description>
23935 <bitOffset>14</bitOffset>
23936 <bitWidth>1</bitWidth>
23940 <description>Filter bits
</description>
23941 <bitOffset>15</bitOffset>
23942 <bitWidth>1</bitWidth>
23946 <description>Filter bits
</description>
23947 <bitOffset>16</bitOffset>
23948 <bitWidth>1</bitWidth>
23952 <description>Filter bits
</description>
23953 <bitOffset>17</bitOffset>
23954 <bitWidth>1</bitWidth>
23958 <description>Filter bits
</description>
23959 <bitOffset>18</bitOffset>
23960 <bitWidth>1</bitWidth>
23964 <description>Filter bits
</description>
23965 <bitOffset>19</bitOffset>
23966 <bitWidth>1</bitWidth>
23970 <description>Filter bits
</description>
23971 <bitOffset>20</bitOffset>
23972 <bitWidth>1</bitWidth>
23976 <description>Filter bits
</description>
23977 <bitOffset>21</bitOffset>
23978 <bitWidth>1</bitWidth>
23982 <description>Filter bits
</description>
23983 <bitOffset>22</bitOffset>
23984 <bitWidth>1</bitWidth>
23988 <description>Filter bits
</description>
23989 <bitOffset>23</bitOffset>
23990 <bitWidth>1</bitWidth>
23994 <description>Filter bits
</description>
23995 <bitOffset>24</bitOffset>
23996 <bitWidth>1</bitWidth>
24000 <description>Filter bits
</description>
24001 <bitOffset>25</bitOffset>
24002 <bitWidth>1</bitWidth>
24006 <description>Filter bits
</description>
24007 <bitOffset>26</bitOffset>
24008 <bitWidth>1</bitWidth>
24012 <description>Filter bits
</description>
24013 <bitOffset>27</bitOffset>
24014 <bitWidth>1</bitWidth>
24018 <description>Filter bits
</description>
24019 <bitOffset>28</bitOffset>
24020 <bitWidth>1</bitWidth>
24024 <description>Filter bits
</description>
24025 <bitOffset>29</bitOffset>
24026 <bitWidth>1</bitWidth>
24030 <description>Filter bits
</description>
24031 <bitOffset>30</bitOffset>
24032 <bitWidth>1</bitWidth>
24036 <description>Filter bits
</description>
24037 <bitOffset>31</bitOffset>
24038 <bitWidth>1</bitWidth>
24044 <displayName>F22R1
</displayName>
24045 <description>Filter bank
22 register
1</description>
24046 <addressOffset>0x2F0</addressOffset>
24048 <access>read-write
</access>
24049 <resetValue>0x00000000</resetValue>
24053 <description>Filter bits
</description>
24054 <bitOffset>0</bitOffset>
24055 <bitWidth>1</bitWidth>
24059 <description>Filter bits
</description>
24060 <bitOffset>1</bitOffset>
24061 <bitWidth>1</bitWidth>
24065 <description>Filter bits
</description>
24066 <bitOffset>2</bitOffset>
24067 <bitWidth>1</bitWidth>
24071 <description>Filter bits
</description>
24072 <bitOffset>3</bitOffset>
24073 <bitWidth>1</bitWidth>
24077 <description>Filter bits
</description>
24078 <bitOffset>4</bitOffset>
24079 <bitWidth>1</bitWidth>
24083 <description>Filter bits
</description>
24084 <bitOffset>5</bitOffset>
24085 <bitWidth>1</bitWidth>
24089 <description>Filter bits
</description>
24090 <bitOffset>6</bitOffset>
24091 <bitWidth>1</bitWidth>
24095 <description>Filter bits
</description>
24096 <bitOffset>7</bitOffset>
24097 <bitWidth>1</bitWidth>
24101 <description>Filter bits
</description>
24102 <bitOffset>8</bitOffset>
24103 <bitWidth>1</bitWidth>
24107 <description>Filter bits
</description>
24108 <bitOffset>9</bitOffset>
24109 <bitWidth>1</bitWidth>
24113 <description>Filter bits
</description>
24114 <bitOffset>10</bitOffset>
24115 <bitWidth>1</bitWidth>
24119 <description>Filter bits
</description>
24120 <bitOffset>11</bitOffset>
24121 <bitWidth>1</bitWidth>
24125 <description>Filter bits
</description>
24126 <bitOffset>12</bitOffset>
24127 <bitWidth>1</bitWidth>
24131 <description>Filter bits
</description>
24132 <bitOffset>13</bitOffset>
24133 <bitWidth>1</bitWidth>
24137 <description>Filter bits
</description>
24138 <bitOffset>14</bitOffset>
24139 <bitWidth>1</bitWidth>
24143 <description>Filter bits
</description>
24144 <bitOffset>15</bitOffset>
24145 <bitWidth>1</bitWidth>
24149 <description>Filter bits
</description>
24150 <bitOffset>16</bitOffset>
24151 <bitWidth>1</bitWidth>
24155 <description>Filter bits
</description>
24156 <bitOffset>17</bitOffset>
24157 <bitWidth>1</bitWidth>
24161 <description>Filter bits
</description>
24162 <bitOffset>18</bitOffset>
24163 <bitWidth>1</bitWidth>
24167 <description>Filter bits
</description>
24168 <bitOffset>19</bitOffset>
24169 <bitWidth>1</bitWidth>
24173 <description>Filter bits
</description>
24174 <bitOffset>20</bitOffset>
24175 <bitWidth>1</bitWidth>
24179 <description>Filter bits
</description>
24180 <bitOffset>21</bitOffset>
24181 <bitWidth>1</bitWidth>
24185 <description>Filter bits
</description>
24186 <bitOffset>22</bitOffset>
24187 <bitWidth>1</bitWidth>
24191 <description>Filter bits
</description>
24192 <bitOffset>23</bitOffset>
24193 <bitWidth>1</bitWidth>
24197 <description>Filter bits
</description>
24198 <bitOffset>24</bitOffset>
24199 <bitWidth>1</bitWidth>
24203 <description>Filter bits
</description>
24204 <bitOffset>25</bitOffset>
24205 <bitWidth>1</bitWidth>
24209 <description>Filter bits
</description>
24210 <bitOffset>26</bitOffset>
24211 <bitWidth>1</bitWidth>
24215 <description>Filter bits
</description>
24216 <bitOffset>27</bitOffset>
24217 <bitWidth>1</bitWidth>
24221 <description>Filter bits
</description>
24222 <bitOffset>28</bitOffset>
24223 <bitWidth>1</bitWidth>
24227 <description>Filter bits
</description>
24228 <bitOffset>29</bitOffset>
24229 <bitWidth>1</bitWidth>
24233 <description>Filter bits
</description>
24234 <bitOffset>30</bitOffset>
24235 <bitWidth>1</bitWidth>
24239 <description>Filter bits
</description>
24240 <bitOffset>31</bitOffset>
24241 <bitWidth>1</bitWidth>
24247 <displayName>F22R2
</displayName>
24248 <description>Filter bank
22 register
2</description>
24249 <addressOffset>0x2F4</addressOffset>
24251 <access>read-write
</access>
24252 <resetValue>0x00000000</resetValue>
24256 <description>Filter bits
</description>
24257 <bitOffset>0</bitOffset>
24258 <bitWidth>1</bitWidth>
24262 <description>Filter bits
</description>
24263 <bitOffset>1</bitOffset>
24264 <bitWidth>1</bitWidth>
24268 <description>Filter bits
</description>
24269 <bitOffset>2</bitOffset>
24270 <bitWidth>1</bitWidth>
24274 <description>Filter bits
</description>
24275 <bitOffset>3</bitOffset>
24276 <bitWidth>1</bitWidth>
24280 <description>Filter bits
</description>
24281 <bitOffset>4</bitOffset>
24282 <bitWidth>1</bitWidth>
24286 <description>Filter bits
</description>
24287 <bitOffset>5</bitOffset>
24288 <bitWidth>1</bitWidth>
24292 <description>Filter bits
</description>
24293 <bitOffset>6</bitOffset>
24294 <bitWidth>1</bitWidth>
24298 <description>Filter bits
</description>
24299 <bitOffset>7</bitOffset>
24300 <bitWidth>1</bitWidth>
24304 <description>Filter bits
</description>
24305 <bitOffset>8</bitOffset>
24306 <bitWidth>1</bitWidth>
24310 <description>Filter bits
</description>
24311 <bitOffset>9</bitOffset>
24312 <bitWidth>1</bitWidth>
24316 <description>Filter bits
</description>
24317 <bitOffset>10</bitOffset>
24318 <bitWidth>1</bitWidth>
24322 <description>Filter bits
</description>
24323 <bitOffset>11</bitOffset>
24324 <bitWidth>1</bitWidth>
24328 <description>Filter bits
</description>
24329 <bitOffset>12</bitOffset>
24330 <bitWidth>1</bitWidth>
24334 <description>Filter bits
</description>
24335 <bitOffset>13</bitOffset>
24336 <bitWidth>1</bitWidth>
24340 <description>Filter bits
</description>
24341 <bitOffset>14</bitOffset>
24342 <bitWidth>1</bitWidth>
24346 <description>Filter bits
</description>
24347 <bitOffset>15</bitOffset>
24348 <bitWidth>1</bitWidth>
24352 <description>Filter bits
</description>
24353 <bitOffset>16</bitOffset>
24354 <bitWidth>1</bitWidth>
24358 <description>Filter bits
</description>
24359 <bitOffset>17</bitOffset>
24360 <bitWidth>1</bitWidth>
24364 <description>Filter bits
</description>
24365 <bitOffset>18</bitOffset>
24366 <bitWidth>1</bitWidth>
24370 <description>Filter bits
</description>
24371 <bitOffset>19</bitOffset>
24372 <bitWidth>1</bitWidth>
24376 <description>Filter bits
</description>
24377 <bitOffset>20</bitOffset>
24378 <bitWidth>1</bitWidth>
24382 <description>Filter bits
</description>
24383 <bitOffset>21</bitOffset>
24384 <bitWidth>1</bitWidth>
24388 <description>Filter bits
</description>
24389 <bitOffset>22</bitOffset>
24390 <bitWidth>1</bitWidth>
24394 <description>Filter bits
</description>
24395 <bitOffset>23</bitOffset>
24396 <bitWidth>1</bitWidth>
24400 <description>Filter bits
</description>
24401 <bitOffset>24</bitOffset>
24402 <bitWidth>1</bitWidth>
24406 <description>Filter bits
</description>
24407 <bitOffset>25</bitOffset>
24408 <bitWidth>1</bitWidth>
24412 <description>Filter bits
</description>
24413 <bitOffset>26</bitOffset>
24414 <bitWidth>1</bitWidth>
24418 <description>Filter bits
</description>
24419 <bitOffset>27</bitOffset>
24420 <bitWidth>1</bitWidth>
24424 <description>Filter bits
</description>
24425 <bitOffset>28</bitOffset>
24426 <bitWidth>1</bitWidth>
24430 <description>Filter bits
</description>
24431 <bitOffset>29</bitOffset>
24432 <bitWidth>1</bitWidth>
24436 <description>Filter bits
</description>
24437 <bitOffset>30</bitOffset>
24438 <bitWidth>1</bitWidth>
24442 <description>Filter bits
</description>
24443 <bitOffset>31</bitOffset>
24444 <bitWidth>1</bitWidth>
24450 <displayName>F23R1
</displayName>
24451 <description>Filter bank
23 register
1</description>
24452 <addressOffset>0x2F8</addressOffset>
24454 <access>read-write
</access>
24455 <resetValue>0x00000000</resetValue>
24459 <description>Filter bits
</description>
24460 <bitOffset>0</bitOffset>
24461 <bitWidth>1</bitWidth>
24465 <description>Filter bits
</description>
24466 <bitOffset>1</bitOffset>
24467 <bitWidth>1</bitWidth>
24471 <description>Filter bits
</description>
24472 <bitOffset>2</bitOffset>
24473 <bitWidth>1</bitWidth>
24477 <description>Filter bits
</description>
24478 <bitOffset>3</bitOffset>
24479 <bitWidth>1</bitWidth>
24483 <description>Filter bits
</description>
24484 <bitOffset>4</bitOffset>
24485 <bitWidth>1</bitWidth>
24489 <description>Filter bits
</description>
24490 <bitOffset>5</bitOffset>
24491 <bitWidth>1</bitWidth>
24495 <description>Filter bits
</description>
24496 <bitOffset>6</bitOffset>
24497 <bitWidth>1</bitWidth>
24501 <description>Filter bits
</description>
24502 <bitOffset>7</bitOffset>
24503 <bitWidth>1</bitWidth>
24507 <description>Filter bits
</description>
24508 <bitOffset>8</bitOffset>
24509 <bitWidth>1</bitWidth>
24513 <description>Filter bits
</description>
24514 <bitOffset>9</bitOffset>
24515 <bitWidth>1</bitWidth>
24519 <description>Filter bits
</description>
24520 <bitOffset>10</bitOffset>
24521 <bitWidth>1</bitWidth>
24525 <description>Filter bits
</description>
24526 <bitOffset>11</bitOffset>
24527 <bitWidth>1</bitWidth>
24531 <description>Filter bits
</description>
24532 <bitOffset>12</bitOffset>
24533 <bitWidth>1</bitWidth>
24537 <description>Filter bits
</description>
24538 <bitOffset>13</bitOffset>
24539 <bitWidth>1</bitWidth>
24543 <description>Filter bits
</description>
24544 <bitOffset>14</bitOffset>
24545 <bitWidth>1</bitWidth>
24549 <description>Filter bits
</description>
24550 <bitOffset>15</bitOffset>
24551 <bitWidth>1</bitWidth>
24555 <description>Filter bits
</description>
24556 <bitOffset>16</bitOffset>
24557 <bitWidth>1</bitWidth>
24561 <description>Filter bits
</description>
24562 <bitOffset>17</bitOffset>
24563 <bitWidth>1</bitWidth>
24567 <description>Filter bits
</description>
24568 <bitOffset>18</bitOffset>
24569 <bitWidth>1</bitWidth>
24573 <description>Filter bits
</description>
24574 <bitOffset>19</bitOffset>
24575 <bitWidth>1</bitWidth>
24579 <description>Filter bits
</description>
24580 <bitOffset>20</bitOffset>
24581 <bitWidth>1</bitWidth>
24585 <description>Filter bits
</description>
24586 <bitOffset>21</bitOffset>
24587 <bitWidth>1</bitWidth>
24591 <description>Filter bits
</description>
24592 <bitOffset>22</bitOffset>
24593 <bitWidth>1</bitWidth>
24597 <description>Filter bits
</description>
24598 <bitOffset>23</bitOffset>
24599 <bitWidth>1</bitWidth>
24603 <description>Filter bits
</description>
24604 <bitOffset>24</bitOffset>
24605 <bitWidth>1</bitWidth>
24609 <description>Filter bits
</description>
24610 <bitOffset>25</bitOffset>
24611 <bitWidth>1</bitWidth>
24615 <description>Filter bits
</description>
24616 <bitOffset>26</bitOffset>
24617 <bitWidth>1</bitWidth>
24621 <description>Filter bits
</description>
24622 <bitOffset>27</bitOffset>
24623 <bitWidth>1</bitWidth>
24627 <description>Filter bits
</description>
24628 <bitOffset>28</bitOffset>
24629 <bitWidth>1</bitWidth>
24633 <description>Filter bits
</description>
24634 <bitOffset>29</bitOffset>
24635 <bitWidth>1</bitWidth>
24639 <description>Filter bits
</description>
24640 <bitOffset>30</bitOffset>
24641 <bitWidth>1</bitWidth>
24645 <description>Filter bits
</description>
24646 <bitOffset>31</bitOffset>
24647 <bitWidth>1</bitWidth>
24653 <displayName>F23R2
</displayName>
24654 <description>Filter bank
23 register
2</description>
24655 <addressOffset>0x2FC</addressOffset>
24657 <access>read-write
</access>
24658 <resetValue>0x00000000</resetValue>
24662 <description>Filter bits
</description>
24663 <bitOffset>0</bitOffset>
24664 <bitWidth>1</bitWidth>
24668 <description>Filter bits
</description>
24669 <bitOffset>1</bitOffset>
24670 <bitWidth>1</bitWidth>
24674 <description>Filter bits
</description>
24675 <bitOffset>2</bitOffset>
24676 <bitWidth>1</bitWidth>
24680 <description>Filter bits
</description>
24681 <bitOffset>3</bitOffset>
24682 <bitWidth>1</bitWidth>
24686 <description>Filter bits
</description>
24687 <bitOffset>4</bitOffset>
24688 <bitWidth>1</bitWidth>
24692 <description>Filter bits
</description>
24693 <bitOffset>5</bitOffset>
24694 <bitWidth>1</bitWidth>
24698 <description>Filter bits
</description>
24699 <bitOffset>6</bitOffset>
24700 <bitWidth>1</bitWidth>
24704 <description>Filter bits
</description>
24705 <bitOffset>7</bitOffset>
24706 <bitWidth>1</bitWidth>
24710 <description>Filter bits
</description>
24711 <bitOffset>8</bitOffset>
24712 <bitWidth>1</bitWidth>
24716 <description>Filter bits
</description>
24717 <bitOffset>9</bitOffset>
24718 <bitWidth>1</bitWidth>
24722 <description>Filter bits
</description>
24723 <bitOffset>10</bitOffset>
24724 <bitWidth>1</bitWidth>
24728 <description>Filter bits
</description>
24729 <bitOffset>11</bitOffset>
24730 <bitWidth>1</bitWidth>
24734 <description>Filter bits
</description>
24735 <bitOffset>12</bitOffset>
24736 <bitWidth>1</bitWidth>
24740 <description>Filter bits
</description>
24741 <bitOffset>13</bitOffset>
24742 <bitWidth>1</bitWidth>
24746 <description>Filter bits
</description>
24747 <bitOffset>14</bitOffset>
24748 <bitWidth>1</bitWidth>
24752 <description>Filter bits
</description>
24753 <bitOffset>15</bitOffset>
24754 <bitWidth>1</bitWidth>
24758 <description>Filter bits
</description>
24759 <bitOffset>16</bitOffset>
24760 <bitWidth>1</bitWidth>
24764 <description>Filter bits
</description>
24765 <bitOffset>17</bitOffset>
24766 <bitWidth>1</bitWidth>
24770 <description>Filter bits
</description>
24771 <bitOffset>18</bitOffset>
24772 <bitWidth>1</bitWidth>
24776 <description>Filter bits
</description>
24777 <bitOffset>19</bitOffset>
24778 <bitWidth>1</bitWidth>
24782 <description>Filter bits
</description>
24783 <bitOffset>20</bitOffset>
24784 <bitWidth>1</bitWidth>
24788 <description>Filter bits
</description>
24789 <bitOffset>21</bitOffset>
24790 <bitWidth>1</bitWidth>
24794 <description>Filter bits
</description>
24795 <bitOffset>22</bitOffset>
24796 <bitWidth>1</bitWidth>
24800 <description>Filter bits
</description>
24801 <bitOffset>23</bitOffset>
24802 <bitWidth>1</bitWidth>
24806 <description>Filter bits
</description>
24807 <bitOffset>24</bitOffset>
24808 <bitWidth>1</bitWidth>
24812 <description>Filter bits
</description>
24813 <bitOffset>25</bitOffset>
24814 <bitWidth>1</bitWidth>
24818 <description>Filter bits
</description>
24819 <bitOffset>26</bitOffset>
24820 <bitWidth>1</bitWidth>
24824 <description>Filter bits
</description>
24825 <bitOffset>27</bitOffset>
24826 <bitWidth>1</bitWidth>
24830 <description>Filter bits
</description>
24831 <bitOffset>28</bitOffset>
24832 <bitWidth>1</bitWidth>
24836 <description>Filter bits
</description>
24837 <bitOffset>29</bitOffset>
24838 <bitWidth>1</bitWidth>
24842 <description>Filter bits
</description>
24843 <bitOffset>30</bitOffset>
24844 <bitWidth>1</bitWidth>
24848 <description>Filter bits
</description>
24849 <bitOffset>31</bitOffset>
24850 <bitWidth>1</bitWidth>
24856 <displayName>F24R1
</displayName>
24857 <description>Filter bank
24 register
1</description>
24858 <addressOffset>0x300</addressOffset>
24860 <access>read-write
</access>
24861 <resetValue>0x00000000</resetValue>
24865 <description>Filter bits
</description>
24866 <bitOffset>0</bitOffset>
24867 <bitWidth>1</bitWidth>
24871 <description>Filter bits
</description>
24872 <bitOffset>1</bitOffset>
24873 <bitWidth>1</bitWidth>
24877 <description>Filter bits
</description>
24878 <bitOffset>2</bitOffset>
24879 <bitWidth>1</bitWidth>
24883 <description>Filter bits
</description>
24884 <bitOffset>3</bitOffset>
24885 <bitWidth>1</bitWidth>
24889 <description>Filter bits
</description>
24890 <bitOffset>4</bitOffset>
24891 <bitWidth>1</bitWidth>
24895 <description>Filter bits
</description>
24896 <bitOffset>5</bitOffset>
24897 <bitWidth>1</bitWidth>
24901 <description>Filter bits
</description>
24902 <bitOffset>6</bitOffset>
24903 <bitWidth>1</bitWidth>
24907 <description>Filter bits
</description>
24908 <bitOffset>7</bitOffset>
24909 <bitWidth>1</bitWidth>
24913 <description>Filter bits
</description>
24914 <bitOffset>8</bitOffset>
24915 <bitWidth>1</bitWidth>
24919 <description>Filter bits
</description>
24920 <bitOffset>9</bitOffset>
24921 <bitWidth>1</bitWidth>
24925 <description>Filter bits
</description>
24926 <bitOffset>10</bitOffset>
24927 <bitWidth>1</bitWidth>
24931 <description>Filter bits
</description>
24932 <bitOffset>11</bitOffset>
24933 <bitWidth>1</bitWidth>
24937 <description>Filter bits
</description>
24938 <bitOffset>12</bitOffset>
24939 <bitWidth>1</bitWidth>
24943 <description>Filter bits
</description>
24944 <bitOffset>13</bitOffset>
24945 <bitWidth>1</bitWidth>
24949 <description>Filter bits
</description>
24950 <bitOffset>14</bitOffset>
24951 <bitWidth>1</bitWidth>
24955 <description>Filter bits
</description>
24956 <bitOffset>15</bitOffset>
24957 <bitWidth>1</bitWidth>
24961 <description>Filter bits
</description>
24962 <bitOffset>16</bitOffset>
24963 <bitWidth>1</bitWidth>
24967 <description>Filter bits
</description>
24968 <bitOffset>17</bitOffset>
24969 <bitWidth>1</bitWidth>
24973 <description>Filter bits
</description>
24974 <bitOffset>18</bitOffset>
24975 <bitWidth>1</bitWidth>
24979 <description>Filter bits
</description>
24980 <bitOffset>19</bitOffset>
24981 <bitWidth>1</bitWidth>
24985 <description>Filter bits
</description>
24986 <bitOffset>20</bitOffset>
24987 <bitWidth>1</bitWidth>
24991 <description>Filter bits
</description>
24992 <bitOffset>21</bitOffset>
24993 <bitWidth>1</bitWidth>
24997 <description>Filter bits
</description>
24998 <bitOffset>22</bitOffset>
24999 <bitWidth>1</bitWidth>
25003 <description>Filter bits
</description>
25004 <bitOffset>23</bitOffset>
25005 <bitWidth>1</bitWidth>
25009 <description>Filter bits
</description>
25010 <bitOffset>24</bitOffset>
25011 <bitWidth>1</bitWidth>
25015 <description>Filter bits
</description>
25016 <bitOffset>25</bitOffset>
25017 <bitWidth>1</bitWidth>
25021 <description>Filter bits
</description>
25022 <bitOffset>26</bitOffset>
25023 <bitWidth>1</bitWidth>
25027 <description>Filter bits
</description>
25028 <bitOffset>27</bitOffset>
25029 <bitWidth>1</bitWidth>
25033 <description>Filter bits
</description>
25034 <bitOffset>28</bitOffset>
25035 <bitWidth>1</bitWidth>
25039 <description>Filter bits
</description>
25040 <bitOffset>29</bitOffset>
25041 <bitWidth>1</bitWidth>
25045 <description>Filter bits
</description>
25046 <bitOffset>30</bitOffset>
25047 <bitWidth>1</bitWidth>
25051 <description>Filter bits
</description>
25052 <bitOffset>31</bitOffset>
25053 <bitWidth>1</bitWidth>
25059 <displayName>F24R2
</displayName>
25060 <description>Filter bank
24 register
2</description>
25061 <addressOffset>0x304</addressOffset>
25063 <access>read-write
</access>
25064 <resetValue>0x00000000</resetValue>
25068 <description>Filter bits
</description>
25069 <bitOffset>0</bitOffset>
25070 <bitWidth>1</bitWidth>
25074 <description>Filter bits
</description>
25075 <bitOffset>1</bitOffset>
25076 <bitWidth>1</bitWidth>
25080 <description>Filter bits
</description>
25081 <bitOffset>2</bitOffset>
25082 <bitWidth>1</bitWidth>
25086 <description>Filter bits
</description>
25087 <bitOffset>3</bitOffset>
25088 <bitWidth>1</bitWidth>
25092 <description>Filter bits
</description>
25093 <bitOffset>4</bitOffset>
25094 <bitWidth>1</bitWidth>
25098 <description>Filter bits
</description>
25099 <bitOffset>5</bitOffset>
25100 <bitWidth>1</bitWidth>
25104 <description>Filter bits
</description>
25105 <bitOffset>6</bitOffset>
25106 <bitWidth>1</bitWidth>
25110 <description>Filter bits
</description>
25111 <bitOffset>7</bitOffset>
25112 <bitWidth>1</bitWidth>
25116 <description>Filter bits
</description>
25117 <bitOffset>8</bitOffset>
25118 <bitWidth>1</bitWidth>
25122 <description>Filter bits
</description>
25123 <bitOffset>9</bitOffset>
25124 <bitWidth>1</bitWidth>
25128 <description>Filter bits
</description>
25129 <bitOffset>10</bitOffset>
25130 <bitWidth>1</bitWidth>
25134 <description>Filter bits
</description>
25135 <bitOffset>11</bitOffset>
25136 <bitWidth>1</bitWidth>
25140 <description>Filter bits
</description>
25141 <bitOffset>12</bitOffset>
25142 <bitWidth>1</bitWidth>
25146 <description>Filter bits
</description>
25147 <bitOffset>13</bitOffset>
25148 <bitWidth>1</bitWidth>
25152 <description>Filter bits
</description>
25153 <bitOffset>14</bitOffset>
25154 <bitWidth>1</bitWidth>
25158 <description>Filter bits
</description>
25159 <bitOffset>15</bitOffset>
25160 <bitWidth>1</bitWidth>
25164 <description>Filter bits
</description>
25165 <bitOffset>16</bitOffset>
25166 <bitWidth>1</bitWidth>
25170 <description>Filter bits
</description>
25171 <bitOffset>17</bitOffset>
25172 <bitWidth>1</bitWidth>
25176 <description>Filter bits
</description>
25177 <bitOffset>18</bitOffset>
25178 <bitWidth>1</bitWidth>
25182 <description>Filter bits
</description>
25183 <bitOffset>19</bitOffset>
25184 <bitWidth>1</bitWidth>
25188 <description>Filter bits
</description>
25189 <bitOffset>20</bitOffset>
25190 <bitWidth>1</bitWidth>
25194 <description>Filter bits
</description>
25195 <bitOffset>21</bitOffset>
25196 <bitWidth>1</bitWidth>
25200 <description>Filter bits
</description>
25201 <bitOffset>22</bitOffset>
25202 <bitWidth>1</bitWidth>
25206 <description>Filter bits
</description>
25207 <bitOffset>23</bitOffset>
25208 <bitWidth>1</bitWidth>
25212 <description>Filter bits
</description>
25213 <bitOffset>24</bitOffset>
25214 <bitWidth>1</bitWidth>
25218 <description>Filter bits
</description>
25219 <bitOffset>25</bitOffset>
25220 <bitWidth>1</bitWidth>
25224 <description>Filter bits
</description>
25225 <bitOffset>26</bitOffset>
25226 <bitWidth>1</bitWidth>
25230 <description>Filter bits
</description>
25231 <bitOffset>27</bitOffset>
25232 <bitWidth>1</bitWidth>
25236 <description>Filter bits
</description>
25237 <bitOffset>28</bitOffset>
25238 <bitWidth>1</bitWidth>
25242 <description>Filter bits
</description>
25243 <bitOffset>29</bitOffset>
25244 <bitWidth>1</bitWidth>
25248 <description>Filter bits
</description>
25249 <bitOffset>30</bitOffset>
25250 <bitWidth>1</bitWidth>
25254 <description>Filter bits
</description>
25255 <bitOffset>31</bitOffset>
25256 <bitWidth>1</bitWidth>
25262 <displayName>F25R1
</displayName>
25263 <description>Filter bank
25 register
1</description>
25264 <addressOffset>0x308</addressOffset>
25266 <access>read-write
</access>
25267 <resetValue>0x00000000</resetValue>
25271 <description>Filter bits
</description>
25272 <bitOffset>0</bitOffset>
25273 <bitWidth>1</bitWidth>
25277 <description>Filter bits
</description>
25278 <bitOffset>1</bitOffset>
25279 <bitWidth>1</bitWidth>
25283 <description>Filter bits
</description>
25284 <bitOffset>2</bitOffset>
25285 <bitWidth>1</bitWidth>
25289 <description>Filter bits
</description>
25290 <bitOffset>3</bitOffset>
25291 <bitWidth>1</bitWidth>
25295 <description>Filter bits
</description>
25296 <bitOffset>4</bitOffset>
25297 <bitWidth>1</bitWidth>
25301 <description>Filter bits
</description>
25302 <bitOffset>5</bitOffset>
25303 <bitWidth>1</bitWidth>
25307 <description>Filter bits
</description>
25308 <bitOffset>6</bitOffset>
25309 <bitWidth>1</bitWidth>
25313 <description>Filter bits
</description>
25314 <bitOffset>7</bitOffset>
25315 <bitWidth>1</bitWidth>
25319 <description>Filter bits
</description>
25320 <bitOffset>8</bitOffset>
25321 <bitWidth>1</bitWidth>
25325 <description>Filter bits
</description>
25326 <bitOffset>9</bitOffset>
25327 <bitWidth>1</bitWidth>
25331 <description>Filter bits
</description>
25332 <bitOffset>10</bitOffset>
25333 <bitWidth>1</bitWidth>
25337 <description>Filter bits
</description>
25338 <bitOffset>11</bitOffset>
25339 <bitWidth>1</bitWidth>
25343 <description>Filter bits
</description>
25344 <bitOffset>12</bitOffset>
25345 <bitWidth>1</bitWidth>
25349 <description>Filter bits
</description>
25350 <bitOffset>13</bitOffset>
25351 <bitWidth>1</bitWidth>
25355 <description>Filter bits
</description>
25356 <bitOffset>14</bitOffset>
25357 <bitWidth>1</bitWidth>
25361 <description>Filter bits
</description>
25362 <bitOffset>15</bitOffset>
25363 <bitWidth>1</bitWidth>
25367 <description>Filter bits
</description>
25368 <bitOffset>16</bitOffset>
25369 <bitWidth>1</bitWidth>
25373 <description>Filter bits
</description>
25374 <bitOffset>17</bitOffset>
25375 <bitWidth>1</bitWidth>
25379 <description>Filter bits
</description>
25380 <bitOffset>18</bitOffset>
25381 <bitWidth>1</bitWidth>
25385 <description>Filter bits
</description>
25386 <bitOffset>19</bitOffset>
25387 <bitWidth>1</bitWidth>
25391 <description>Filter bits
</description>
25392 <bitOffset>20</bitOffset>
25393 <bitWidth>1</bitWidth>
25397 <description>Filter bits
</description>
25398 <bitOffset>21</bitOffset>
25399 <bitWidth>1</bitWidth>
25403 <description>Filter bits
</description>
25404 <bitOffset>22</bitOffset>
25405 <bitWidth>1</bitWidth>
25409 <description>Filter bits
</description>
25410 <bitOffset>23</bitOffset>
25411 <bitWidth>1</bitWidth>
25415 <description>Filter bits
</description>
25416 <bitOffset>24</bitOffset>
25417 <bitWidth>1</bitWidth>
25421 <description>Filter bits
</description>
25422 <bitOffset>25</bitOffset>
25423 <bitWidth>1</bitWidth>
25427 <description>Filter bits
</description>
25428 <bitOffset>26</bitOffset>
25429 <bitWidth>1</bitWidth>
25433 <description>Filter bits
</description>
25434 <bitOffset>27</bitOffset>
25435 <bitWidth>1</bitWidth>
25439 <description>Filter bits
</description>
25440 <bitOffset>28</bitOffset>
25441 <bitWidth>1</bitWidth>
25445 <description>Filter bits
</description>
25446 <bitOffset>29</bitOffset>
25447 <bitWidth>1</bitWidth>
25451 <description>Filter bits
</description>
25452 <bitOffset>30</bitOffset>
25453 <bitWidth>1</bitWidth>
25457 <description>Filter bits
</description>
25458 <bitOffset>31</bitOffset>
25459 <bitWidth>1</bitWidth>
25465 <displayName>F25R2
</displayName>
25466 <description>Filter bank
25 register
2</description>
25467 <addressOffset>0x30C</addressOffset>
25469 <access>read-write
</access>
25470 <resetValue>0x00000000</resetValue>
25474 <description>Filter bits
</description>
25475 <bitOffset>0</bitOffset>
25476 <bitWidth>1</bitWidth>
25480 <description>Filter bits
</description>
25481 <bitOffset>1</bitOffset>
25482 <bitWidth>1</bitWidth>
25486 <description>Filter bits
</description>
25487 <bitOffset>2</bitOffset>
25488 <bitWidth>1</bitWidth>
25492 <description>Filter bits
</description>
25493 <bitOffset>3</bitOffset>
25494 <bitWidth>1</bitWidth>
25498 <description>Filter bits
</description>
25499 <bitOffset>4</bitOffset>
25500 <bitWidth>1</bitWidth>
25504 <description>Filter bits
</description>
25505 <bitOffset>5</bitOffset>
25506 <bitWidth>1</bitWidth>
25510 <description>Filter bits
</description>
25511 <bitOffset>6</bitOffset>
25512 <bitWidth>1</bitWidth>
25516 <description>Filter bits
</description>
25517 <bitOffset>7</bitOffset>
25518 <bitWidth>1</bitWidth>
25522 <description>Filter bits
</description>
25523 <bitOffset>8</bitOffset>
25524 <bitWidth>1</bitWidth>
25528 <description>Filter bits
</description>
25529 <bitOffset>9</bitOffset>
25530 <bitWidth>1</bitWidth>
25534 <description>Filter bits
</description>
25535 <bitOffset>10</bitOffset>
25536 <bitWidth>1</bitWidth>
25540 <description>Filter bits
</description>
25541 <bitOffset>11</bitOffset>
25542 <bitWidth>1</bitWidth>
25546 <description>Filter bits
</description>
25547 <bitOffset>12</bitOffset>
25548 <bitWidth>1</bitWidth>
25552 <description>Filter bits
</description>
25553 <bitOffset>13</bitOffset>
25554 <bitWidth>1</bitWidth>
25558 <description>Filter bits
</description>
25559 <bitOffset>14</bitOffset>
25560 <bitWidth>1</bitWidth>
25564 <description>Filter bits
</description>
25565 <bitOffset>15</bitOffset>
25566 <bitWidth>1</bitWidth>
25570 <description>Filter bits
</description>
25571 <bitOffset>16</bitOffset>
25572 <bitWidth>1</bitWidth>
25576 <description>Filter bits
</description>
25577 <bitOffset>17</bitOffset>
25578 <bitWidth>1</bitWidth>
25582 <description>Filter bits
</description>
25583 <bitOffset>18</bitOffset>
25584 <bitWidth>1</bitWidth>
25588 <description>Filter bits
</description>
25589 <bitOffset>19</bitOffset>
25590 <bitWidth>1</bitWidth>
25594 <description>Filter bits
</description>
25595 <bitOffset>20</bitOffset>
25596 <bitWidth>1</bitWidth>
25600 <description>Filter bits
</description>
25601 <bitOffset>21</bitOffset>
25602 <bitWidth>1</bitWidth>
25606 <description>Filter bits
</description>
25607 <bitOffset>22</bitOffset>
25608 <bitWidth>1</bitWidth>
25612 <description>Filter bits
</description>
25613 <bitOffset>23</bitOffset>
25614 <bitWidth>1</bitWidth>
25618 <description>Filter bits
</description>
25619 <bitOffset>24</bitOffset>
25620 <bitWidth>1</bitWidth>
25624 <description>Filter bits
</description>
25625 <bitOffset>25</bitOffset>
25626 <bitWidth>1</bitWidth>
25630 <description>Filter bits
</description>
25631 <bitOffset>26</bitOffset>
25632 <bitWidth>1</bitWidth>
25636 <description>Filter bits
</description>
25637 <bitOffset>27</bitOffset>
25638 <bitWidth>1</bitWidth>
25642 <description>Filter bits
</description>
25643 <bitOffset>28</bitOffset>
25644 <bitWidth>1</bitWidth>
25648 <description>Filter bits
</description>
25649 <bitOffset>29</bitOffset>
25650 <bitWidth>1</bitWidth>
25654 <description>Filter bits
</description>
25655 <bitOffset>30</bitOffset>
25656 <bitWidth>1</bitWidth>
25660 <description>Filter bits
</description>
25661 <bitOffset>31</bitOffset>
25662 <bitWidth>1</bitWidth>
25668 <displayName>F26R1
</displayName>
25669 <description>Filter bank
26 register
1</description>
25670 <addressOffset>0x310</addressOffset>
25672 <access>read-write
</access>
25673 <resetValue>0x00000000</resetValue>
25677 <description>Filter bits
</description>
25678 <bitOffset>0</bitOffset>
25679 <bitWidth>1</bitWidth>
25683 <description>Filter bits
</description>
25684 <bitOffset>1</bitOffset>
25685 <bitWidth>1</bitWidth>
25689 <description>Filter bits
</description>
25690 <bitOffset>2</bitOffset>
25691 <bitWidth>1</bitWidth>
25695 <description>Filter bits
</description>
25696 <bitOffset>3</bitOffset>
25697 <bitWidth>1</bitWidth>
25701 <description>Filter bits
</description>
25702 <bitOffset>4</bitOffset>
25703 <bitWidth>1</bitWidth>
25707 <description>Filter bits
</description>
25708 <bitOffset>5</bitOffset>
25709 <bitWidth>1</bitWidth>
25713 <description>Filter bits
</description>
25714 <bitOffset>6</bitOffset>
25715 <bitWidth>1</bitWidth>
25719 <description>Filter bits
</description>
25720 <bitOffset>7</bitOffset>
25721 <bitWidth>1</bitWidth>
25725 <description>Filter bits
</description>
25726 <bitOffset>8</bitOffset>
25727 <bitWidth>1</bitWidth>
25731 <description>Filter bits
</description>
25732 <bitOffset>9</bitOffset>
25733 <bitWidth>1</bitWidth>
25737 <description>Filter bits
</description>
25738 <bitOffset>10</bitOffset>
25739 <bitWidth>1</bitWidth>
25743 <description>Filter bits
</description>
25744 <bitOffset>11</bitOffset>
25745 <bitWidth>1</bitWidth>
25749 <description>Filter bits
</description>
25750 <bitOffset>12</bitOffset>
25751 <bitWidth>1</bitWidth>
25755 <description>Filter bits
</description>
25756 <bitOffset>13</bitOffset>
25757 <bitWidth>1</bitWidth>
25761 <description>Filter bits
</description>
25762 <bitOffset>14</bitOffset>
25763 <bitWidth>1</bitWidth>
25767 <description>Filter bits
</description>
25768 <bitOffset>15</bitOffset>
25769 <bitWidth>1</bitWidth>
25773 <description>Filter bits
</description>
25774 <bitOffset>16</bitOffset>
25775 <bitWidth>1</bitWidth>
25779 <description>Filter bits
</description>
25780 <bitOffset>17</bitOffset>
25781 <bitWidth>1</bitWidth>
25785 <description>Filter bits
</description>
25786 <bitOffset>18</bitOffset>
25787 <bitWidth>1</bitWidth>
25791 <description>Filter bits
</description>
25792 <bitOffset>19</bitOffset>
25793 <bitWidth>1</bitWidth>
25797 <description>Filter bits
</description>
25798 <bitOffset>20</bitOffset>
25799 <bitWidth>1</bitWidth>
25803 <description>Filter bits
</description>
25804 <bitOffset>21</bitOffset>
25805 <bitWidth>1</bitWidth>
25809 <description>Filter bits
</description>
25810 <bitOffset>22</bitOffset>
25811 <bitWidth>1</bitWidth>
25815 <description>Filter bits
</description>
25816 <bitOffset>23</bitOffset>
25817 <bitWidth>1</bitWidth>
25821 <description>Filter bits
</description>
25822 <bitOffset>24</bitOffset>
25823 <bitWidth>1</bitWidth>
25827 <description>Filter bits
</description>
25828 <bitOffset>25</bitOffset>
25829 <bitWidth>1</bitWidth>
25833 <description>Filter bits
</description>
25834 <bitOffset>26</bitOffset>
25835 <bitWidth>1</bitWidth>
25839 <description>Filter bits
</description>
25840 <bitOffset>27</bitOffset>
25841 <bitWidth>1</bitWidth>
25845 <description>Filter bits
</description>
25846 <bitOffset>28</bitOffset>
25847 <bitWidth>1</bitWidth>
25851 <description>Filter bits
</description>
25852 <bitOffset>29</bitOffset>
25853 <bitWidth>1</bitWidth>
25857 <description>Filter bits
</description>
25858 <bitOffset>30</bitOffset>
25859 <bitWidth>1</bitWidth>
25863 <description>Filter bits
</description>
25864 <bitOffset>31</bitOffset>
25865 <bitWidth>1</bitWidth>
25871 <displayName>F26R2
</displayName>
25872 <description>Filter bank
26 register
2</description>
25873 <addressOffset>0x314</addressOffset>
25875 <access>read-write
</access>
25876 <resetValue>0x00000000</resetValue>
25880 <description>Filter bits
</description>
25881 <bitOffset>0</bitOffset>
25882 <bitWidth>1</bitWidth>
25886 <description>Filter bits
</description>
25887 <bitOffset>1</bitOffset>
25888 <bitWidth>1</bitWidth>
25892 <description>Filter bits
</description>
25893 <bitOffset>2</bitOffset>
25894 <bitWidth>1</bitWidth>
25898 <description>Filter bits
</description>
25899 <bitOffset>3</bitOffset>
25900 <bitWidth>1</bitWidth>
25904 <description>Filter bits
</description>
25905 <bitOffset>4</bitOffset>
25906 <bitWidth>1</bitWidth>
25910 <description>Filter bits
</description>
25911 <bitOffset>5</bitOffset>
25912 <bitWidth>1</bitWidth>
25916 <description>Filter bits
</description>
25917 <bitOffset>6</bitOffset>
25918 <bitWidth>1</bitWidth>
25922 <description>Filter bits
</description>
25923 <bitOffset>7</bitOffset>
25924 <bitWidth>1</bitWidth>
25928 <description>Filter bits
</description>
25929 <bitOffset>8</bitOffset>
25930 <bitWidth>1</bitWidth>
25934 <description>Filter bits
</description>
25935 <bitOffset>9</bitOffset>
25936 <bitWidth>1</bitWidth>
25940 <description>Filter bits
</description>
25941 <bitOffset>10</bitOffset>
25942 <bitWidth>1</bitWidth>
25946 <description>Filter bits
</description>
25947 <bitOffset>11</bitOffset>
25948 <bitWidth>1</bitWidth>
25952 <description>Filter bits
</description>
25953 <bitOffset>12</bitOffset>
25954 <bitWidth>1</bitWidth>
25958 <description>Filter bits
</description>
25959 <bitOffset>13</bitOffset>
25960 <bitWidth>1</bitWidth>
25964 <description>Filter bits
</description>
25965 <bitOffset>14</bitOffset>
25966 <bitWidth>1</bitWidth>
25970 <description>Filter bits
</description>
25971 <bitOffset>15</bitOffset>
25972 <bitWidth>1</bitWidth>
25976 <description>Filter bits
</description>
25977 <bitOffset>16</bitOffset>
25978 <bitWidth>1</bitWidth>
25982 <description>Filter bits
</description>
25983 <bitOffset>17</bitOffset>
25984 <bitWidth>1</bitWidth>
25988 <description>Filter bits
</description>
25989 <bitOffset>18</bitOffset>
25990 <bitWidth>1</bitWidth>
25994 <description>Filter bits
</description>
25995 <bitOffset>19</bitOffset>
25996 <bitWidth>1</bitWidth>
26000 <description>Filter bits
</description>
26001 <bitOffset>20</bitOffset>
26002 <bitWidth>1</bitWidth>
26006 <description>Filter bits
</description>
26007 <bitOffset>21</bitOffset>
26008 <bitWidth>1</bitWidth>
26012 <description>Filter bits
</description>
26013 <bitOffset>22</bitOffset>
26014 <bitWidth>1</bitWidth>
26018 <description>Filter bits
</description>
26019 <bitOffset>23</bitOffset>
26020 <bitWidth>1</bitWidth>
26024 <description>Filter bits
</description>
26025 <bitOffset>24</bitOffset>
26026 <bitWidth>1</bitWidth>
26030 <description>Filter bits
</description>
26031 <bitOffset>25</bitOffset>
26032 <bitWidth>1</bitWidth>
26036 <description>Filter bits
</description>
26037 <bitOffset>26</bitOffset>
26038 <bitWidth>1</bitWidth>
26042 <description>Filter bits
</description>
26043 <bitOffset>27</bitOffset>
26044 <bitWidth>1</bitWidth>
26048 <description>Filter bits
</description>
26049 <bitOffset>28</bitOffset>
26050 <bitWidth>1</bitWidth>
26054 <description>Filter bits
</description>
26055 <bitOffset>29</bitOffset>
26056 <bitWidth>1</bitWidth>
26060 <description>Filter bits
</description>
26061 <bitOffset>30</bitOffset>
26062 <bitWidth>1</bitWidth>
26066 <description>Filter bits
</description>
26067 <bitOffset>31</bitOffset>
26068 <bitWidth>1</bitWidth>
26074 <displayName>F27R1
</displayName>
26075 <description>Filter bank
27 register
1</description>
26076 <addressOffset>0x318</addressOffset>
26078 <access>read-write
</access>
26079 <resetValue>0x00000000</resetValue>
26083 <description>Filter bits
</description>
26084 <bitOffset>0</bitOffset>
26085 <bitWidth>1</bitWidth>
26089 <description>Filter bits
</description>
26090 <bitOffset>1</bitOffset>
26091 <bitWidth>1</bitWidth>
26095 <description>Filter bits
</description>
26096 <bitOffset>2</bitOffset>
26097 <bitWidth>1</bitWidth>
26101 <description>Filter bits
</description>
26102 <bitOffset>3</bitOffset>
26103 <bitWidth>1</bitWidth>
26107 <description>Filter bits
</description>
26108 <bitOffset>4</bitOffset>
26109 <bitWidth>1</bitWidth>
26113 <description>Filter bits
</description>
26114 <bitOffset>5</bitOffset>
26115 <bitWidth>1</bitWidth>
26119 <description>Filter bits
</description>
26120 <bitOffset>6</bitOffset>
26121 <bitWidth>1</bitWidth>
26125 <description>Filter bits
</description>
26126 <bitOffset>7</bitOffset>
26127 <bitWidth>1</bitWidth>
26131 <description>Filter bits
</description>
26132 <bitOffset>8</bitOffset>
26133 <bitWidth>1</bitWidth>
26137 <description>Filter bits
</description>
26138 <bitOffset>9</bitOffset>
26139 <bitWidth>1</bitWidth>
26143 <description>Filter bits
</description>
26144 <bitOffset>10</bitOffset>
26145 <bitWidth>1</bitWidth>
26149 <description>Filter bits
</description>
26150 <bitOffset>11</bitOffset>
26151 <bitWidth>1</bitWidth>
26155 <description>Filter bits
</description>
26156 <bitOffset>12</bitOffset>
26157 <bitWidth>1</bitWidth>
26161 <description>Filter bits
</description>
26162 <bitOffset>13</bitOffset>
26163 <bitWidth>1</bitWidth>
26167 <description>Filter bits
</description>
26168 <bitOffset>14</bitOffset>
26169 <bitWidth>1</bitWidth>
26173 <description>Filter bits
</description>
26174 <bitOffset>15</bitOffset>
26175 <bitWidth>1</bitWidth>
26179 <description>Filter bits
</description>
26180 <bitOffset>16</bitOffset>
26181 <bitWidth>1</bitWidth>
26185 <description>Filter bits
</description>
26186 <bitOffset>17</bitOffset>
26187 <bitWidth>1</bitWidth>
26191 <description>Filter bits
</description>
26192 <bitOffset>18</bitOffset>
26193 <bitWidth>1</bitWidth>
26197 <description>Filter bits
</description>
26198 <bitOffset>19</bitOffset>
26199 <bitWidth>1</bitWidth>
26203 <description>Filter bits
</description>
26204 <bitOffset>20</bitOffset>
26205 <bitWidth>1</bitWidth>
26209 <description>Filter bits
</description>
26210 <bitOffset>21</bitOffset>
26211 <bitWidth>1</bitWidth>
26215 <description>Filter bits
</description>
26216 <bitOffset>22</bitOffset>
26217 <bitWidth>1</bitWidth>
26221 <description>Filter bits
</description>
26222 <bitOffset>23</bitOffset>
26223 <bitWidth>1</bitWidth>
26227 <description>Filter bits
</description>
26228 <bitOffset>24</bitOffset>
26229 <bitWidth>1</bitWidth>
26233 <description>Filter bits
</description>
26234 <bitOffset>25</bitOffset>
26235 <bitWidth>1</bitWidth>
26239 <description>Filter bits
</description>
26240 <bitOffset>26</bitOffset>
26241 <bitWidth>1</bitWidth>
26245 <description>Filter bits
</description>
26246 <bitOffset>27</bitOffset>
26247 <bitWidth>1</bitWidth>
26251 <description>Filter bits
</description>
26252 <bitOffset>28</bitOffset>
26253 <bitWidth>1</bitWidth>
26257 <description>Filter bits
</description>
26258 <bitOffset>29</bitOffset>
26259 <bitWidth>1</bitWidth>
26263 <description>Filter bits
</description>
26264 <bitOffset>30</bitOffset>
26265 <bitWidth>1</bitWidth>
26269 <description>Filter bits
</description>
26270 <bitOffset>31</bitOffset>
26271 <bitWidth>1</bitWidth>
26277 <displayName>F27R2
</displayName>
26278 <description>Filter bank
27 register
2</description>
26279 <addressOffset>0x31C</addressOffset>
26281 <access>read-write
</access>
26282 <resetValue>0x00000000</resetValue>
26286 <description>Filter bits
</description>
26287 <bitOffset>0</bitOffset>
26288 <bitWidth>1</bitWidth>
26292 <description>Filter bits
</description>
26293 <bitOffset>1</bitOffset>
26294 <bitWidth>1</bitWidth>
26298 <description>Filter bits
</description>
26299 <bitOffset>2</bitOffset>
26300 <bitWidth>1</bitWidth>
26304 <description>Filter bits
</description>
26305 <bitOffset>3</bitOffset>
26306 <bitWidth>1</bitWidth>
26310 <description>Filter bits
</description>
26311 <bitOffset>4</bitOffset>
26312 <bitWidth>1</bitWidth>
26316 <description>Filter bits
</description>
26317 <bitOffset>5</bitOffset>
26318 <bitWidth>1</bitWidth>
26322 <description>Filter bits
</description>
26323 <bitOffset>6</bitOffset>
26324 <bitWidth>1</bitWidth>
26328 <description>Filter bits
</description>
26329 <bitOffset>7</bitOffset>
26330 <bitWidth>1</bitWidth>
26334 <description>Filter bits
</description>
26335 <bitOffset>8</bitOffset>
26336 <bitWidth>1</bitWidth>
26340 <description>Filter bits
</description>
26341 <bitOffset>9</bitOffset>
26342 <bitWidth>1</bitWidth>
26346 <description>Filter bits
</description>
26347 <bitOffset>10</bitOffset>
26348 <bitWidth>1</bitWidth>
26352 <description>Filter bits
</description>
26353 <bitOffset>11</bitOffset>
26354 <bitWidth>1</bitWidth>
26358 <description>Filter bits
</description>
26359 <bitOffset>12</bitOffset>
26360 <bitWidth>1</bitWidth>
26364 <description>Filter bits
</description>
26365 <bitOffset>13</bitOffset>
26366 <bitWidth>1</bitWidth>
26370 <description>Filter bits
</description>
26371 <bitOffset>14</bitOffset>
26372 <bitWidth>1</bitWidth>
26376 <description>Filter bits
</description>
26377 <bitOffset>15</bitOffset>
26378 <bitWidth>1</bitWidth>
26382 <description>Filter bits
</description>
26383 <bitOffset>16</bitOffset>
26384 <bitWidth>1</bitWidth>
26388 <description>Filter bits
</description>
26389 <bitOffset>17</bitOffset>
26390 <bitWidth>1</bitWidth>
26394 <description>Filter bits
</description>
26395 <bitOffset>18</bitOffset>
26396 <bitWidth>1</bitWidth>
26400 <description>Filter bits
</description>
26401 <bitOffset>19</bitOffset>
26402 <bitWidth>1</bitWidth>
26406 <description>Filter bits
</description>
26407 <bitOffset>20</bitOffset>
26408 <bitWidth>1</bitWidth>
26412 <description>Filter bits
</description>
26413 <bitOffset>21</bitOffset>
26414 <bitWidth>1</bitWidth>
26418 <description>Filter bits
</description>
26419 <bitOffset>22</bitOffset>
26420 <bitWidth>1</bitWidth>
26424 <description>Filter bits
</description>
26425 <bitOffset>23</bitOffset>
26426 <bitWidth>1</bitWidth>
26430 <description>Filter bits
</description>
26431 <bitOffset>24</bitOffset>
26432 <bitWidth>1</bitWidth>
26436 <description>Filter bits
</description>
26437 <bitOffset>25</bitOffset>
26438 <bitWidth>1</bitWidth>
26442 <description>Filter bits
</description>
26443 <bitOffset>26</bitOffset>
26444 <bitWidth>1</bitWidth>
26448 <description>Filter bits
</description>
26449 <bitOffset>27</bitOffset>
26450 <bitWidth>1</bitWidth>
26454 <description>Filter bits
</description>
26455 <bitOffset>28</bitOffset>
26456 <bitWidth>1</bitWidth>
26460 <description>Filter bits
</description>
26461 <bitOffset>29</bitOffset>
26462 <bitWidth>1</bitWidth>
26466 <description>Filter bits
</description>
26467 <bitOffset>30</bitOffset>
26468 <bitWidth>1</bitWidth>
26472 <description>Filter bits
</description>
26473 <bitOffset>31</bitOffset>
26474 <bitWidth>1</bitWidth>
26481 <name>USB_FS
</name>
26482 <description>Universal serial bus full-speed device
26483 interface
</description>
26484 <groupName>USB_FS
</groupName>
26485 <baseAddress>0x40005C00</baseAddress>
26487 <offset>0x0</offset>
26489 <usage>registers
</usage>
26492 <name>USB_WKUP
</name>
26493 <description>USB wakeup from Suspend
</description>
26497 <name>USB_HP
</name>
26498 <description>USB High priority interrupt
</description>
26502 <name>USB_LP
</name>
26503 <description>USB Low priority interrupt
</description>
26508 <name>USB_EP0R
</name>
26509 <displayName>USB_EP0R
</displayName>
26510 <description>endpoint
0 register
</description>
26511 <addressOffset>0x0</addressOffset>
26513 <resetValue>0x00000000</resetValue>
26517 <description>Endpoint address
</description>
26518 <bitOffset>0</bitOffset>
26519 <bitWidth>4</bitWidth>
26520 <access>read-write
</access>
26523 <name>STAT_TX
</name>
26524 <description>Status bits, for transmission
26525 transfers
</description>
26526 <bitOffset>4</bitOffset>
26527 <bitWidth>2</bitWidth>
26528 <access>read-write
</access>
26531 <name>DTOG_TX
</name>
26532 <description>Data Toggle, for transmission
26533 transfers
</description>
26534 <bitOffset>6</bitOffset>
26535 <bitWidth>1</bitWidth>
26536 <access>read-write
</access>
26539 <name>CTR_TX
</name>
26540 <description>Correct Transfer for
26541 transmission
</description>
26542 <bitOffset>7</bitOffset>
26543 <bitWidth>1</bitWidth>
26544 <access>read-write
</access>
26547 <name>EP_KIND
</name>
26548 <description>Endpoint kind
</description>
26549 <bitOffset>8</bitOffset>
26550 <bitWidth>1</bitWidth>
26551 <access>read-write
</access>
26554 <name>EP_TYPE
</name>
26555 <description>Endpoint type
</description>
26556 <bitOffset>9</bitOffset>
26557 <bitWidth>2</bitWidth>
26558 <access>read-write
</access>
26562 <description>Setup transaction
26563 completed
</description>
26564 <bitOffset>11</bitOffset>
26565 <bitWidth>1</bitWidth>
26566 <access>read-only
</access>
26569 <name>STAT_RX
</name>
26570 <description>Status bits, for reception
26571 transfers
</description>
26572 <bitOffset>12</bitOffset>
26573 <bitWidth>2</bitWidth>
26574 <access>read-write
</access>
26577 <name>DTOG_RX
</name>
26578 <description>Data Toggle, for reception
26579 transfers
</description>
26580 <bitOffset>14</bitOffset>
26581 <bitWidth>1</bitWidth>
26582 <access>read-write
</access>
26585 <name>CTR_RX
</name>
26586 <description>Correct transfer for
26587 reception
</description>
26588 <bitOffset>15</bitOffset>
26589 <bitWidth>1</bitWidth>
26590 <access>read-write
</access>
26595 <name>USB_EP1R
</name>
26596 <displayName>USB_EP1R
</displayName>
26597 <description>endpoint
1 register
</description>
26598 <addressOffset>0x4</addressOffset>
26600 <resetValue>0x00000000</resetValue>
26604 <description>Endpoint address
</description>
26605 <bitOffset>0</bitOffset>
26606 <bitWidth>4</bitWidth>
26607 <access>read-write
</access>
26610 <name>STAT_TX
</name>
26611 <description>Status bits, for transmission
26612 transfers
</description>
26613 <bitOffset>4</bitOffset>
26614 <bitWidth>2</bitWidth>
26615 <access>read-write
</access>
26618 <name>DTOG_TX
</name>
26619 <description>Data Toggle, for transmission
26620 transfers
</description>
26621 <bitOffset>6</bitOffset>
26622 <bitWidth>1</bitWidth>
26623 <access>read-write
</access>
26626 <name>CTR_TX
</name>
26627 <description>Correct Transfer for
26628 transmission
</description>
26629 <bitOffset>7</bitOffset>
26630 <bitWidth>1</bitWidth>
26631 <access>read-write
</access>
26634 <name>EP_KIND
</name>
26635 <description>Endpoint kind
</description>
26636 <bitOffset>8</bitOffset>
26637 <bitWidth>1</bitWidth>
26638 <access>read-write
</access>
26641 <name>EP_TYPE
</name>
26642 <description>Endpoint type
</description>
26643 <bitOffset>9</bitOffset>
26644 <bitWidth>2</bitWidth>
26645 <access>read-write
</access>
26649 <description>Setup transaction
26650 completed
</description>
26651 <bitOffset>11</bitOffset>
26652 <bitWidth>1</bitWidth>
26653 <access>read-only
</access>
26656 <name>STAT_RX
</name>
26657 <description>Status bits, for reception
26658 transfers
</description>
26659 <bitOffset>12</bitOffset>
26660 <bitWidth>2</bitWidth>
26661 <access>read-write
</access>
26664 <name>DTOG_RX
</name>
26665 <description>Data Toggle, for reception
26666 transfers
</description>
26667 <bitOffset>14</bitOffset>
26668 <bitWidth>1</bitWidth>
26669 <access>read-write
</access>
26672 <name>CTR_RX
</name>
26673 <description>Correct transfer for
26674 reception
</description>
26675 <bitOffset>15</bitOffset>
26676 <bitWidth>1</bitWidth>
26677 <access>read-write
</access>
26682 <name>USB_EP2R
</name>
26683 <displayName>USB_EP2R
</displayName>
26684 <description>endpoint
2 register
</description>
26685 <addressOffset>0x8</addressOffset>
26687 <resetValue>0x00000000</resetValue>
26691 <description>Endpoint address
</description>
26692 <bitOffset>0</bitOffset>
26693 <bitWidth>4</bitWidth>
26694 <access>read-write
</access>
26697 <name>STAT_TX
</name>
26698 <description>Status bits, for transmission
26699 transfers
</description>
26700 <bitOffset>4</bitOffset>
26701 <bitWidth>2</bitWidth>
26702 <access>read-write
</access>
26705 <name>DTOG_TX
</name>
26706 <description>Data Toggle, for transmission
26707 transfers
</description>
26708 <bitOffset>6</bitOffset>
26709 <bitWidth>1</bitWidth>
26710 <access>read-write
</access>
26713 <name>CTR_TX
</name>
26714 <description>Correct Transfer for
26715 transmission
</description>
26716 <bitOffset>7</bitOffset>
26717 <bitWidth>1</bitWidth>
26718 <access>read-write
</access>
26721 <name>EP_KIND
</name>
26722 <description>Endpoint kind
</description>
26723 <bitOffset>8</bitOffset>
26724 <bitWidth>1</bitWidth>
26725 <access>read-write
</access>
26728 <name>EP_TYPE
</name>
26729 <description>Endpoint type
</description>
26730 <bitOffset>9</bitOffset>
26731 <bitWidth>2</bitWidth>
26732 <access>read-write
</access>
26736 <description>Setup transaction
26737 completed
</description>
26738 <bitOffset>11</bitOffset>
26739 <bitWidth>1</bitWidth>
26740 <access>read-only
</access>
26743 <name>STAT_RX
</name>
26744 <description>Status bits, for reception
26745 transfers
</description>
26746 <bitOffset>12</bitOffset>
26747 <bitWidth>2</bitWidth>
26748 <access>read-write
</access>
26751 <name>DTOG_RX
</name>
26752 <description>Data Toggle, for reception
26753 transfers
</description>
26754 <bitOffset>14</bitOffset>
26755 <bitWidth>1</bitWidth>
26756 <access>read-write
</access>
26759 <name>CTR_RX
</name>
26760 <description>Correct transfer for
26761 reception
</description>
26762 <bitOffset>15</bitOffset>
26763 <bitWidth>1</bitWidth>
26764 <access>read-write
</access>
26769 <name>USB_EP3R
</name>
26770 <displayName>USB_EP3R
</displayName>
26771 <description>endpoint
3 register
</description>
26772 <addressOffset>0xC</addressOffset>
26774 <resetValue>0x00000000</resetValue>
26778 <description>Endpoint address
</description>
26779 <bitOffset>0</bitOffset>
26780 <bitWidth>4</bitWidth>
26781 <access>read-write
</access>
26784 <name>STAT_TX
</name>
26785 <description>Status bits, for transmission
26786 transfers
</description>
26787 <bitOffset>4</bitOffset>
26788 <bitWidth>2</bitWidth>
26789 <access>read-write
</access>
26792 <name>DTOG_TX
</name>
26793 <description>Data Toggle, for transmission
26794 transfers
</description>
26795 <bitOffset>6</bitOffset>
26796 <bitWidth>1</bitWidth>
26797 <access>read-write
</access>
26800 <name>CTR_TX
</name>
26801 <description>Correct Transfer for
26802 transmission
</description>
26803 <bitOffset>7</bitOffset>
26804 <bitWidth>1</bitWidth>
26805 <access>read-write
</access>
26808 <name>EP_KIND
</name>
26809 <description>Endpoint kind
</description>
26810 <bitOffset>8</bitOffset>
26811 <bitWidth>1</bitWidth>
26812 <access>read-write
</access>
26815 <name>EP_TYPE
</name>
26816 <description>Endpoint type
</description>
26817 <bitOffset>9</bitOffset>
26818 <bitWidth>2</bitWidth>
26819 <access>read-write
</access>
26823 <description>Setup transaction
26824 completed
</description>
26825 <bitOffset>11</bitOffset>
26826 <bitWidth>1</bitWidth>
26827 <access>read-only
</access>
26830 <name>STAT_RX
</name>
26831 <description>Status bits, for reception
26832 transfers
</description>
26833 <bitOffset>12</bitOffset>
26834 <bitWidth>2</bitWidth>
26835 <access>read-write
</access>
26838 <name>DTOG_RX
</name>
26839 <description>Data Toggle, for reception
26840 transfers
</description>
26841 <bitOffset>14</bitOffset>
26842 <bitWidth>1</bitWidth>
26843 <access>read-write
</access>
26846 <name>CTR_RX
</name>
26847 <description>Correct transfer for
26848 reception
</description>
26849 <bitOffset>15</bitOffset>
26850 <bitWidth>1</bitWidth>
26851 <access>read-write
</access>
26856 <name>USB_EP4R
</name>
26857 <displayName>USB_EP4R
</displayName>
26858 <description>endpoint
4 register
</description>
26859 <addressOffset>0x10</addressOffset>
26861 <resetValue>0x00000000</resetValue>
26865 <description>Endpoint address
</description>
26866 <bitOffset>0</bitOffset>
26867 <bitWidth>4</bitWidth>
26868 <access>read-write
</access>
26871 <name>STAT_TX
</name>
26872 <description>Status bits, for transmission
26873 transfers
</description>
26874 <bitOffset>4</bitOffset>
26875 <bitWidth>2</bitWidth>
26876 <access>read-write
</access>
26879 <name>DTOG_TX
</name>
26880 <description>Data Toggle, for transmission
26881 transfers
</description>
26882 <bitOffset>6</bitOffset>
26883 <bitWidth>1</bitWidth>
26884 <access>read-write
</access>
26887 <name>CTR_TX
</name>
26888 <description>Correct Transfer for
26889 transmission
</description>
26890 <bitOffset>7</bitOffset>
26891 <bitWidth>1</bitWidth>
26892 <access>read-write
</access>
26895 <name>EP_KIND
</name>
26896 <description>Endpoint kind
</description>
26897 <bitOffset>8</bitOffset>
26898 <bitWidth>1</bitWidth>
26899 <access>read-write
</access>
26902 <name>EP_TYPE
</name>
26903 <description>Endpoint type
</description>
26904 <bitOffset>9</bitOffset>
26905 <bitWidth>2</bitWidth>
26906 <access>read-write
</access>
26910 <description>Setup transaction
26911 completed
</description>
26912 <bitOffset>11</bitOffset>
26913 <bitWidth>1</bitWidth>
26914 <access>read-only
</access>
26917 <name>STAT_RX
</name>
26918 <description>Status bits, for reception
26919 transfers
</description>
26920 <bitOffset>12</bitOffset>
26921 <bitWidth>2</bitWidth>
26922 <access>read-write
</access>
26925 <name>DTOG_RX
</name>
26926 <description>Data Toggle, for reception
26927 transfers
</description>
26928 <bitOffset>14</bitOffset>
26929 <bitWidth>1</bitWidth>
26930 <access>read-write
</access>
26933 <name>CTR_RX
</name>
26934 <description>Correct transfer for
26935 reception
</description>
26936 <bitOffset>15</bitOffset>
26937 <bitWidth>1</bitWidth>
26938 <access>read-write
</access>
26943 <name>USB_EP5R
</name>
26944 <displayName>USB_EP5R
</displayName>
26945 <description>endpoint
5 register
</description>
26946 <addressOffset>0x14</addressOffset>
26948 <resetValue>0x00000000</resetValue>
26952 <description>Endpoint address
</description>
26953 <bitOffset>0</bitOffset>
26954 <bitWidth>4</bitWidth>
26955 <access>read-write
</access>
26958 <name>STAT_TX
</name>
26959 <description>Status bits, for transmission
26960 transfers
</description>
26961 <bitOffset>4</bitOffset>
26962 <bitWidth>2</bitWidth>
26963 <access>read-write
</access>
26966 <name>DTOG_TX
</name>
26967 <description>Data Toggle, for transmission
26968 transfers
</description>
26969 <bitOffset>6</bitOffset>
26970 <bitWidth>1</bitWidth>
26971 <access>read-write
</access>
26974 <name>CTR_TX
</name>
26975 <description>Correct Transfer for
26976 transmission
</description>
26977 <bitOffset>7</bitOffset>
26978 <bitWidth>1</bitWidth>
26979 <access>read-write
</access>
26982 <name>EP_KIND
</name>
26983 <description>Endpoint kind
</description>
26984 <bitOffset>8</bitOffset>
26985 <bitWidth>1</bitWidth>
26986 <access>read-write
</access>
26989 <name>EP_TYPE
</name>
26990 <description>Endpoint type
</description>
26991 <bitOffset>9</bitOffset>
26992 <bitWidth>2</bitWidth>
26993 <access>read-write
</access>
26997 <description>Setup transaction
26998 completed
</description>
26999 <bitOffset>11</bitOffset>
27000 <bitWidth>1</bitWidth>
27001 <access>read-only
</access>
27004 <name>STAT_RX
</name>
27005 <description>Status bits, for reception
27006 transfers
</description>
27007 <bitOffset>12</bitOffset>
27008 <bitWidth>2</bitWidth>
27009 <access>read-write
</access>
27012 <name>DTOG_RX
</name>
27013 <description>Data Toggle, for reception
27014 transfers
</description>
27015 <bitOffset>14</bitOffset>
27016 <bitWidth>1</bitWidth>
27017 <access>read-write
</access>
27020 <name>CTR_RX
</name>
27021 <description>Correct transfer for
27022 reception
</description>
27023 <bitOffset>15</bitOffset>
27024 <bitWidth>1</bitWidth>
27025 <access>read-write
</access>
27030 <name>USB_EP6R
</name>
27031 <displayName>USB_EP6R
</displayName>
27032 <description>endpoint
6 register
</description>
27033 <addressOffset>0x18</addressOffset>
27035 <resetValue>0x00000000</resetValue>
27039 <description>Endpoint address
</description>
27040 <bitOffset>0</bitOffset>
27041 <bitWidth>4</bitWidth>
27042 <access>read-write
</access>
27045 <name>STAT_TX
</name>
27046 <description>Status bits, for transmission
27047 transfers
</description>
27048 <bitOffset>4</bitOffset>
27049 <bitWidth>2</bitWidth>
27050 <access>read-write
</access>
27053 <name>DTOG_TX
</name>
27054 <description>Data Toggle, for transmission
27055 transfers
</description>
27056 <bitOffset>6</bitOffset>
27057 <bitWidth>1</bitWidth>
27058 <access>read-write
</access>
27061 <name>CTR_TX
</name>
27062 <description>Correct Transfer for
27063 transmission
</description>
27064 <bitOffset>7</bitOffset>
27065 <bitWidth>1</bitWidth>
27066 <access>read-write
</access>
27069 <name>EP_KIND
</name>
27070 <description>Endpoint kind
</description>
27071 <bitOffset>8</bitOffset>
27072 <bitWidth>1</bitWidth>
27073 <access>read-write
</access>
27076 <name>EP_TYPE
</name>
27077 <description>Endpoint type
</description>
27078 <bitOffset>9</bitOffset>
27079 <bitWidth>2</bitWidth>
27080 <access>read-write
</access>
27084 <description>Setup transaction
27085 completed
</description>
27086 <bitOffset>11</bitOffset>
27087 <bitWidth>1</bitWidth>
27088 <access>read-only
</access>
27091 <name>STAT_RX
</name>
27092 <description>Status bits, for reception
27093 transfers
</description>
27094 <bitOffset>12</bitOffset>
27095 <bitWidth>2</bitWidth>
27096 <access>read-write
</access>
27099 <name>DTOG_RX
</name>
27100 <description>Data Toggle, for reception
27101 transfers
</description>
27102 <bitOffset>14</bitOffset>
27103 <bitWidth>1</bitWidth>
27104 <access>read-write
</access>
27107 <name>CTR_RX
</name>
27108 <description>Correct transfer for
27109 reception
</description>
27110 <bitOffset>15</bitOffset>
27111 <bitWidth>1</bitWidth>
27112 <access>read-write
</access>
27117 <name>USB_EP7R
</name>
27118 <displayName>USB_EP7R
</displayName>
27119 <description>endpoint
7 register
</description>
27120 <addressOffset>0x1C</addressOffset>
27122 <resetValue>0x00000000</resetValue>
27126 <description>Endpoint address
</description>
27127 <bitOffset>0</bitOffset>
27128 <bitWidth>4</bitWidth>
27129 <access>read-write
</access>
27132 <name>STAT_TX
</name>
27133 <description>Status bits, for transmission
27134 transfers
</description>
27135 <bitOffset>4</bitOffset>
27136 <bitWidth>2</bitWidth>
27137 <access>read-write
</access>
27140 <name>DTOG_TX
</name>
27141 <description>Data Toggle, for transmission
27142 transfers
</description>
27143 <bitOffset>6</bitOffset>
27144 <bitWidth>1</bitWidth>
27145 <access>read-write
</access>
27148 <name>CTR_TX
</name>
27149 <description>Correct Transfer for
27150 transmission
</description>
27151 <bitOffset>7</bitOffset>
27152 <bitWidth>1</bitWidth>
27153 <access>read-write
</access>
27156 <name>EP_KIND
</name>
27157 <description>Endpoint kind
</description>
27158 <bitOffset>8</bitOffset>
27159 <bitWidth>1</bitWidth>
27160 <access>read-write
</access>
27163 <name>EP_TYPE
</name>
27164 <description>Endpoint type
</description>
27165 <bitOffset>9</bitOffset>
27166 <bitWidth>2</bitWidth>
27167 <access>read-write
</access>
27171 <description>Setup transaction
27172 completed
</description>
27173 <bitOffset>11</bitOffset>
27174 <bitWidth>1</bitWidth>
27175 <access>read-only
</access>
27178 <name>STAT_RX
</name>
27179 <description>Status bits, for reception
27180 transfers
</description>
27181 <bitOffset>12</bitOffset>
27182 <bitWidth>2</bitWidth>
27183 <access>read-write
</access>
27186 <name>DTOG_RX
</name>
27187 <description>Data Toggle, for reception
27188 transfers
</description>
27189 <bitOffset>14</bitOffset>
27190 <bitWidth>1</bitWidth>
27191 <access>read-write
</access>
27194 <name>CTR_RX
</name>
27195 <description>Correct transfer for
27196 reception
</description>
27197 <bitOffset>15</bitOffset>
27198 <bitWidth>1</bitWidth>
27199 <access>read-write
</access>
27204 <name>USB_CNTR
</name>
27205 <displayName>USB_CNTR
</displayName>
27206 <description>control register
</description>
27207 <addressOffset>0x40</addressOffset>
27209 <access>read-write
</access>
27210 <resetValue>0x00000003</resetValue>
27214 <description>Force USB Reset
</description>
27215 <bitOffset>0</bitOffset>
27216 <bitWidth>1</bitWidth>
27220 <description>Power down
</description>
27221 <bitOffset>1</bitOffset>
27222 <bitWidth>1</bitWidth>
27225 <name>LPMODE
</name>
27226 <description>Low-power mode
</description>
27227 <bitOffset>2</bitOffset>
27228 <bitWidth>1</bitWidth>
27232 <description>Force suspend
</description>
27233 <bitOffset>3</bitOffset>
27234 <bitWidth>1</bitWidth>
27237 <name>RESUME
</name>
27238 <description>Resume request
</description>
27239 <bitOffset>4</bitOffset>
27240 <bitWidth>1</bitWidth>
27244 <description>Expected start of frame interrupt
27246 <bitOffset>8</bitOffset>
27247 <bitWidth>1</bitWidth>
27251 <description>Start of frame interrupt
27253 <bitOffset>9</bitOffset>
27254 <bitWidth>1</bitWidth>
27257 <name>RESETM
</name>
27258 <description>USB reset interrupt mask
</description>
27259 <bitOffset>10</bitOffset>
27260 <bitWidth>1</bitWidth>
27264 <description>Suspend mode interrupt
27266 <bitOffset>11</bitOffset>
27267 <bitWidth>1</bitWidth>
27271 <description>Wakeup interrupt mask
</description>
27272 <bitOffset>12</bitOffset>
27273 <bitWidth>1</bitWidth>
27277 <description>Error interrupt mask
</description>
27278 <bitOffset>13</bitOffset>
27279 <bitWidth>1</bitWidth>
27282 <name>PMAOVRM
</name>
27283 <description>Packet memory area over / underrun
27284 interrupt mask
</description>
27285 <bitOffset>14</bitOffset>
27286 <bitWidth>1</bitWidth>
27290 <description>Correct transfer interrupt
27292 <bitOffset>15</bitOffset>
27293 <bitWidth>1</bitWidth>
27299 <displayName>ISTR
</displayName>
27300 <description>interrupt status register
</description>
27301 <addressOffset>0x44</addressOffset>
27303 <resetValue>0x00000000</resetValue>
27307 <description>Endpoint Identifier
</description>
27308 <bitOffset>0</bitOffset>
27309 <bitWidth>4</bitWidth>
27310 <access>read-only
</access>
27314 <description>Direction of transaction
</description>
27315 <bitOffset>4</bitOffset>
27316 <bitWidth>1</bitWidth>
27317 <access>read-only
</access>
27321 <description>Expected start frame
</description>
27322 <bitOffset>8</bitOffset>
27323 <bitWidth>1</bitWidth>
27324 <access>read-write
</access>
27328 <description>start of frame
</description>
27329 <bitOffset>9</bitOffset>
27330 <bitWidth>1</bitWidth>
27331 <access>read-write
</access>
27335 <description>reset request
</description>
27336 <bitOffset>10</bitOffset>
27337 <bitWidth>1</bitWidth>
27338 <access>read-write
</access>
27342 <description>Suspend mode request
</description>
27343 <bitOffset>11</bitOffset>
27344 <bitWidth>1</bitWidth>
27345 <access>read-write
</access>
27349 <description>Wakeup
</description>
27350 <bitOffset>12</bitOffset>
27351 <bitWidth>1</bitWidth>
27352 <access>read-write
</access>
27356 <description>Error
</description>
27357 <bitOffset>13</bitOffset>
27358 <bitWidth>1</bitWidth>
27359 <access>read-write
</access>
27362 <name>PMAOVR
</name>
27363 <description>Packet memory area over /
27364 underrun
</description>
27365 <bitOffset>14</bitOffset>
27366 <bitWidth>1</bitWidth>
27367 <access>read-write
</access>
27371 <description>Correct transfer
</description>
27372 <bitOffset>15</bitOffset>
27373 <bitWidth>1</bitWidth>
27374 <access>read-only
</access>
27380 <displayName>FNR
</displayName>
27381 <description>frame number register
</description>
27382 <addressOffset>0x48</addressOffset>
27384 <access>read-only
</access>
27385 <resetValue>0x0000</resetValue>
27389 <description>Frame number
</description>
27390 <bitOffset>0</bitOffset>
27391 <bitWidth>11</bitWidth>
27395 <description>Lost SOF
</description>
27396 <bitOffset>11</bitOffset>
27397 <bitWidth>2</bitWidth>
27401 <description>Locked
</description>
27402 <bitOffset>13</bitOffset>
27403 <bitWidth>1</bitWidth>
27407 <description>Receive data - line status
</description>
27408 <bitOffset>14</bitOffset>
27409 <bitWidth>1</bitWidth>
27413 <description>Receive data + line status
</description>
27414 <bitOffset>15</bitOffset>
27415 <bitWidth>1</bitWidth>
27421 <displayName>DADDR
</displayName>
27422 <description>device address
</description>
27423 <addressOffset>0x4C</addressOffset>
27425 <access>read-write
</access>
27426 <resetValue>0x0000</resetValue>
27430 <description>Device address
</description>
27431 <bitOffset>0</bitOffset>
27432 <bitWidth>1</bitWidth>
27436 <description>Device address
</description>
27437 <bitOffset>1</bitOffset>
27438 <bitWidth>1</bitWidth>
27442 <description>Device address
</description>
27443 <bitOffset>2</bitOffset>
27444 <bitWidth>1</bitWidth>
27448 <description>Device address
</description>
27449 <bitOffset>3</bitOffset>
27450 <bitWidth>1</bitWidth>
27454 <description>Device address
</description>
27455 <bitOffset>4</bitOffset>
27456 <bitWidth>1</bitWidth>
27460 <description>Device address
</description>
27461 <bitOffset>5</bitOffset>
27462 <bitWidth>1</bitWidth>
27466 <description>Device address
</description>
27467 <bitOffset>6</bitOffset>
27468 <bitWidth>1</bitWidth>
27472 <description>Enable function
</description>
27473 <bitOffset>7</bitOffset>
27474 <bitWidth>1</bitWidth>
27479 <name>BTABLE
</name>
27480 <displayName>BTABLE
</displayName>
27481 <description>Buffer table address
</description>
27482 <addressOffset>0x50</addressOffset>
27484 <access>read-write
</access>
27485 <resetValue>0x0000</resetValue>
27488 <name>BTABLE
</name>
27489 <description>Buffer table
</description>
27490 <bitOffset>3</bitOffset>
27491 <bitWidth>13</bitWidth>
27499 <description>Inter-integrated circuit
</description>
27500 <groupName>I2C
</groupName>
27501 <baseAddress>0x40005400</baseAddress>
27503 <offset>0x0</offset>
27505 <usage>registers
</usage>
27508 <name>I2C1_EV_EXTI23
</name>
27509 <description>I2C1 event interrupt and EXTI Line23
27510 interrupt
</description>
27514 <name>I2C1_ER
</name>
27515 <description>I2C1 error interrupt
</description>
27521 <displayName>CR1
</displayName>
27522 <description>Control register
1</description>
27523 <addressOffset>0x0</addressOffset>
27525 <resetValue>0x00000000</resetValue>
27529 <description>Peripheral enable
</description>
27530 <bitOffset>0</bitOffset>
27531 <bitWidth>1</bitWidth>
27532 <access>read-write
</access>
27536 <description>TX Interrupt enable
</description>
27537 <bitOffset>1</bitOffset>
27538 <bitWidth>1</bitWidth>
27539 <access>read-write
</access>
27543 <description>RX Interrupt enable
</description>
27544 <bitOffset>2</bitOffset>
27545 <bitWidth>1</bitWidth>
27546 <access>read-write
</access>
27549 <name>ADDRIE
</name>
27550 <description>Address match interrupt enable (slave
27551 only)
</description>
27552 <bitOffset>3</bitOffset>
27553 <bitWidth>1</bitWidth>
27554 <access>read-write
</access>
27557 <name>NACKIE
</name>
27558 <description>Not acknowledge received interrupt
27559 enable
</description>
27560 <bitOffset>4</bitOffset>
27561 <bitWidth>1</bitWidth>
27562 <access>read-write
</access>
27565 <name>STOPIE
</name>
27566 <description>STOP detection Interrupt
27567 enable
</description>
27568 <bitOffset>5</bitOffset>
27569 <bitWidth>1</bitWidth>
27570 <access>read-write
</access>
27574 <description>Transfer Complete interrupt
27575 enable
</description>
27576 <bitOffset>6</bitOffset>
27577 <bitWidth>1</bitWidth>
27578 <access>read-write
</access>
27582 <description>Error interrupts enable
</description>
27583 <bitOffset>7</bitOffset>
27584 <bitWidth>1</bitWidth>
27585 <access>read-write
</access>
27589 <description>Digital noise filter
</description>
27590 <bitOffset>8</bitOffset>
27591 <bitWidth>4</bitWidth>
27592 <access>read-write
</access>
27595 <name>ANFOFF
</name>
27596 <description>Analog noise filter OFF
</description>
27597 <bitOffset>12</bitOffset>
27598 <bitWidth>1</bitWidth>
27599 <access>read-write
</access>
27603 <description>Software reset
</description>
27604 <bitOffset>13</bitOffset>
27605 <bitWidth>1</bitWidth>
27606 <access>write-only
</access>
27609 <name>TXDMAEN
</name>
27610 <description>DMA transmission requests
27611 enable
</description>
27612 <bitOffset>14</bitOffset>
27613 <bitWidth>1</bitWidth>
27614 <access>read-write
</access>
27617 <name>RXDMAEN
</name>
27618 <description>DMA reception requests
27619 enable
</description>
27620 <bitOffset>15</bitOffset>
27621 <bitWidth>1</bitWidth>
27622 <access>read-write
</access>
27626 <description>Slave byte control
</description>
27627 <bitOffset>16</bitOffset>
27628 <bitWidth>1</bitWidth>
27629 <access>read-write
</access>
27632 <name>NOSTRETCH
</name>
27633 <description>Clock stretching disable
</description>
27634 <bitOffset>17</bitOffset>
27635 <bitWidth>1</bitWidth>
27636 <access>read-write
</access>
27640 <description>Wakeup from STOP enable
</description>
27641 <bitOffset>18</bitOffset>
27642 <bitWidth>1</bitWidth>
27643 <access>read-write
</access>
27647 <description>General call enable
</description>
27648 <bitOffset>19</bitOffset>
27649 <bitWidth>1</bitWidth>
27650 <access>read-write
</access>
27653 <name>SMBHEN
</name>
27654 <description>SMBus Host address enable
</description>
27655 <bitOffset>20</bitOffset>
27656 <bitWidth>1</bitWidth>
27657 <access>read-write
</access>
27660 <name>SMBDEN
</name>
27661 <description>SMBus Device Default address
27662 enable
</description>
27663 <bitOffset>21</bitOffset>
27664 <bitWidth>1</bitWidth>
27665 <access>read-write
</access>
27668 <name>ALERTEN
</name>
27669 <description>SMBUS alert enable
</description>
27670 <bitOffset>22</bitOffset>
27671 <bitWidth>1</bitWidth>
27672 <access>read-write
</access>
27676 <description>PEC enable
</description>
27677 <bitOffset>23</bitOffset>
27678 <bitWidth>1</bitWidth>
27679 <access>read-write
</access>
27685 <displayName>CR2
</displayName>
27686 <description>Control register
2</description>
27687 <addressOffset>0x4</addressOffset>
27689 <access>read-write
</access>
27690 <resetValue>0x00000000</resetValue>
27693 <name>PECBYTE
</name>
27694 <description>Packet error checking byte
</description>
27695 <bitOffset>26</bitOffset>
27696 <bitWidth>1</bitWidth>
27699 <name>AUTOEND
</name>
27700 <description>Automatic end mode (master
27701 mode)
</description>
27702 <bitOffset>25</bitOffset>
27703 <bitWidth>1</bitWidth>
27706 <name>RELOAD
</name>
27707 <description>NBYTES reload mode
</description>
27708 <bitOffset>24</bitOffset>
27709 <bitWidth>1</bitWidth>
27712 <name>NBYTES
</name>
27713 <description>Number of bytes
</description>
27714 <bitOffset>16</bitOffset>
27715 <bitWidth>8</bitWidth>
27719 <description>NACK generation (slave
27720 mode)
</description>
27721 <bitOffset>15</bitOffset>
27722 <bitWidth>1</bitWidth>
27726 <description>Stop generation (master
27727 mode)
</description>
27728 <bitOffset>14</bitOffset>
27729 <bitWidth>1</bitWidth>
27733 <description>Start generation
</description>
27734 <bitOffset>13</bitOffset>
27735 <bitWidth>1</bitWidth>
27738 <name>HEAD10R
</name>
27739 <description>10-bit address header only read
27740 direction (master receiver mode)
</description>
27741 <bitOffset>12</bitOffset>
27742 <bitWidth>1</bitWidth>
27746 <description>10-bit addressing mode (master
27747 mode)
</description>
27748 <bitOffset>11</bitOffset>
27749 <bitWidth>1</bitWidth>
27752 <name>RD_WRN
</name>
27753 <description>Transfer direction (master
27754 mode)
</description>
27755 <bitOffset>10</bitOffset>
27756 <bitWidth>1</bitWidth>
27760 <description>Slave address bit
9:
8 (master
27761 mode)
</description>
27762 <bitOffset>8</bitOffset>
27763 <bitWidth>2</bitWidth>
27767 <description>Slave address bit
7:
1 (master
27768 mode)
</description>
27769 <bitOffset>1</bitOffset>
27770 <bitWidth>7</bitWidth>
27774 <description>Slave address bit
0 (master
27775 mode)
</description>
27776 <bitOffset>0</bitOffset>
27777 <bitWidth>1</bitWidth>
27783 <displayName>OAR1
</displayName>
27784 <description>Own address register
1</description>
27785 <addressOffset>0x8</addressOffset>
27787 <access>read-write
</access>
27788 <resetValue>0x00000000</resetValue>
27792 <description>Interface address
</description>
27793 <bitOffset>0</bitOffset>
27794 <bitWidth>1</bitWidth>
27798 <description>Interface address
</description>
27799 <bitOffset>1</bitOffset>
27800 <bitWidth>7</bitWidth>
27804 <description>Interface address
</description>
27805 <bitOffset>8</bitOffset>
27806 <bitWidth>2</bitWidth>
27809 <name>OA1MODE
</name>
27810 <description>Own Address
1 10-bit mode
</description>
27811 <bitOffset>10</bitOffset>
27812 <bitWidth>1</bitWidth>
27816 <description>Own Address
1 enable
</description>
27817 <bitOffset>15</bitOffset>
27818 <bitWidth>1</bitWidth>
27824 <displayName>OAR2
</displayName>
27825 <description>Own address register
2</description>
27826 <addressOffset>0xC</addressOffset>
27828 <access>read-write
</access>
27829 <resetValue>0x00000000</resetValue>
27833 <description>Interface address
</description>
27834 <bitOffset>1</bitOffset>
27835 <bitWidth>7</bitWidth>
27838 <name>OA2MSK
</name>
27839 <description>Own Address
2 masks
</description>
27840 <bitOffset>8</bitOffset>
27841 <bitWidth>3</bitWidth>
27845 <description>Own Address
2 enable
</description>
27846 <bitOffset>15</bitOffset>
27847 <bitWidth>1</bitWidth>
27852 <name>TIMINGR
</name>
27853 <displayName>TIMINGR
</displayName>
27854 <description>Timing register
</description>
27855 <addressOffset>0x10</addressOffset>
27857 <access>read-write
</access>
27858 <resetValue>0x00000000</resetValue>
27862 <description>SCL low period (master
27863 mode)
</description>
27864 <bitOffset>0</bitOffset>
27865 <bitWidth>8</bitWidth>
27869 <description>SCL high period (master
27870 mode)
</description>
27871 <bitOffset>8</bitOffset>
27872 <bitWidth>8</bitWidth>
27875 <name>SDADEL
</name>
27876 <description>Data hold time
</description>
27877 <bitOffset>16</bitOffset>
27878 <bitWidth>4</bitWidth>
27881 <name>SCLDEL
</name>
27882 <description>Data setup time
</description>
27883 <bitOffset>20</bitOffset>
27884 <bitWidth>4</bitWidth>
27888 <description>Timing prescaler
</description>
27889 <bitOffset>28</bitOffset>
27890 <bitWidth>4</bitWidth>
27895 <name>TIMEOUTR
</name>
27896 <displayName>TIMEOUTR
</displayName>
27897 <description>Status register
1</description>
27898 <addressOffset>0x14</addressOffset>
27900 <access>read-write
</access>
27901 <resetValue>0x00000000</resetValue>
27904 <name>TIMEOUTA
</name>
27905 <description>Bus timeout A
</description>
27906 <bitOffset>0</bitOffset>
27907 <bitWidth>12</bitWidth>
27911 <description>Idle clock timeout
27912 detection
</description>
27913 <bitOffset>12</bitOffset>
27914 <bitWidth>1</bitWidth>
27917 <name>TIMOUTEN
</name>
27918 <description>Clock timeout enable
</description>
27919 <bitOffset>15</bitOffset>
27920 <bitWidth>1</bitWidth>
27923 <name>TIMEOUTB
</name>
27924 <description>Bus timeout B
</description>
27925 <bitOffset>16</bitOffset>
27926 <bitWidth>12</bitWidth>
27929 <name>TEXTEN
</name>
27930 <description>Extended clock timeout
27931 enable
</description>
27932 <bitOffset>31</bitOffset>
27933 <bitWidth>1</bitWidth>
27939 <displayName>ISR
</displayName>
27940 <description>Interrupt and Status register
</description>
27941 <addressOffset>0x18</addressOffset>
27943 <resetValue>0x00000001</resetValue>
27946 <name>ADDCODE
</name>
27947 <description>Address match code (Slave
27948 mode)
</description>
27949 <bitOffset>17</bitOffset>
27950 <bitWidth>7</bitWidth>
27951 <access>read-only
</access>
27955 <description>Transfer direction (Slave
27956 mode)
</description>
27957 <bitOffset>16</bitOffset>
27958 <bitWidth>1</bitWidth>
27959 <access>read-only
</access>
27963 <description>Bus busy
</description>
27964 <bitOffset>15</bitOffset>
27965 <bitWidth>1</bitWidth>
27966 <access>read-only
</access>
27970 <description>SMBus alert
</description>
27971 <bitOffset>13</bitOffset>
27972 <bitWidth>1</bitWidth>
27973 <access>read-only
</access>
27976 <name>TIMEOUT
</name>
27977 <description>Timeout or t_low detection
27979 <bitOffset>12</bitOffset>
27980 <bitWidth>1</bitWidth>
27981 <access>read-only
</access>
27984 <name>PECERR
</name>
27985 <description>PEC Error in reception
</description>
27986 <bitOffset>11</bitOffset>
27987 <bitWidth>1</bitWidth>
27988 <access>read-only
</access>
27992 <description>Overrun/Underrun (slave
27993 mode)
</description>
27994 <bitOffset>10</bitOffset>
27995 <bitWidth>1</bitWidth>
27996 <access>read-only
</access>
28000 <description>Arbitration lost
</description>
28001 <bitOffset>9</bitOffset>
28002 <bitWidth>1</bitWidth>
28003 <access>read-only
</access>
28007 <description>Bus error
</description>
28008 <bitOffset>8</bitOffset>
28009 <bitWidth>1</bitWidth>
28010 <access>read-only
</access>
28014 <description>Transfer Complete Reload
</description>
28015 <bitOffset>7</bitOffset>
28016 <bitWidth>1</bitWidth>
28017 <access>read-only
</access>
28021 <description>Transfer Complete (master
28022 mode)
</description>
28023 <bitOffset>6</bitOffset>
28024 <bitWidth>1</bitWidth>
28025 <access>read-only
</access>
28029 <description>Stop detection flag
</description>
28030 <bitOffset>5</bitOffset>
28031 <bitWidth>1</bitWidth>
28032 <access>read-only
</access>
28036 <description>Not acknowledge received
28038 <bitOffset>4</bitOffset>
28039 <bitWidth>1</bitWidth>
28040 <access>read-only
</access>
28044 <description>Address matched (slave
28045 mode)
</description>
28046 <bitOffset>3</bitOffset>
28047 <bitWidth>1</bitWidth>
28048 <access>read-only
</access>
28052 <description>Receive data register not empty
28053 (receivers)
</description>
28054 <bitOffset>2</bitOffset>
28055 <bitWidth>1</bitWidth>
28056 <access>read-only
</access>
28060 <description>Transmit interrupt status
28061 (transmitters)
</description>
28062 <bitOffset>1</bitOffset>
28063 <bitWidth>1</bitWidth>
28064 <access>read-write
</access>
28068 <description>Transmit data register empty
28069 (transmitters)
</description>
28070 <bitOffset>0</bitOffset>
28071 <bitWidth>1</bitWidth>
28072 <access>read-write
</access>
28078 <displayName>ICR
</displayName>
28079 <description>Interrupt clear register
</description>
28080 <addressOffset>0x1C</addressOffset>
28082 <access>write-only
</access>
28083 <resetValue>0x00000000</resetValue>
28086 <name>ALERTCF
</name>
28087 <description>Alert flag clear
</description>
28088 <bitOffset>13</bitOffset>
28089 <bitWidth>1</bitWidth>
28092 <name>TIMOUTCF
</name>
28093 <description>Timeout detection flag
28094 clear
</description>
28095 <bitOffset>12</bitOffset>
28096 <bitWidth>1</bitWidth>
28100 <description>PEC Error flag clear
</description>
28101 <bitOffset>11</bitOffset>
28102 <bitWidth>1</bitWidth>
28106 <description>Overrun/Underrun flag
28107 clear
</description>
28108 <bitOffset>10</bitOffset>
28109 <bitWidth>1</bitWidth>
28112 <name>ARLOCF
</name>
28113 <description>Arbitration lost flag
28114 clear
</description>
28115 <bitOffset>9</bitOffset>
28116 <bitWidth>1</bitWidth>
28119 <name>BERRCF
</name>
28120 <description>Bus error flag clear
</description>
28121 <bitOffset>8</bitOffset>
28122 <bitWidth>1</bitWidth>
28125 <name>STOPCF
</name>
28126 <description>Stop detection flag clear
</description>
28127 <bitOffset>5</bitOffset>
28128 <bitWidth>1</bitWidth>
28131 <name>NACKCF
</name>
28132 <description>Not Acknowledge flag clear
</description>
28133 <bitOffset>4</bitOffset>
28134 <bitWidth>1</bitWidth>
28137 <name>ADDRCF
</name>
28138 <description>Address Matched flag clear
</description>
28139 <bitOffset>3</bitOffset>
28140 <bitWidth>1</bitWidth>
28146 <displayName>PECR
</displayName>
28147 <description>PEC register
</description>
28148 <addressOffset>0x20</addressOffset>
28150 <access>read-only
</access>
28151 <resetValue>0x00000000</resetValue>
28155 <description>Packet error checking
28156 register
</description>
28157 <bitOffset>0</bitOffset>
28158 <bitWidth>8</bitWidth>
28164 <displayName>RXDR
</displayName>
28165 <description>Receive data register
</description>
28166 <addressOffset>0x24</addressOffset>
28168 <access>read-only
</access>
28169 <resetValue>0x00000000</resetValue>
28172 <name>RXDATA
</name>
28173 <description>8-bit receive data
</description>
28174 <bitOffset>0</bitOffset>
28175 <bitWidth>8</bitWidth>
28181 <displayName>TXDR
</displayName>
28182 <description>Transmit data register
</description>
28183 <addressOffset>0x28</addressOffset>
28185 <access>read-write
</access>
28186 <resetValue>0x00000000</resetValue>
28189 <name>TXDATA
</name>
28190 <description>8-bit transmit data
</description>
28191 <bitOffset>0</bitOffset>
28192 <bitWidth>8</bitWidth>
28198 <peripheral derivedFrom=
"I2C1">
28200 <baseAddress>0x40005800</baseAddress>
28202 <name>I2C2_EV_EXTI24
</name>
28203 <description>I2C2 event interrupt
& EXTI Line24
28204 interrupt
</description>
28208 <name>I2C2_ER
</name>
28209 <description>I2C2 error interrupt
</description>
28213 <peripheral derivedFrom=
"I2C1">
28215 <baseAddress>0x40007800</baseAddress>
28217 <name>I2C2_EV_EXTI24
</name>
28218 <description>I2C2 event interrupt
& EXTI Line24
28219 interrupt
</description>
28223 <name>I2C2_ER
</name>
28224 <description>I2C2 error interrupt
</description>
28228 <name>I2C3_EV
</name>
28229 <description>I2C3 Event interrupt
</description>
28233 <name>I2C3_ER
</name>
28234 <description>I2C3 Error interrupt
</description>
28240 <description>Independent watchdog
</description>
28241 <groupName>IWDG
</groupName>
28242 <baseAddress>0x40003000</baseAddress>
28244 <offset>0x0</offset>
28246 <usage>registers
</usage>
28251 <displayName>KR
</displayName>
28252 <description>Key register
</description>
28253 <addressOffset>0x0</addressOffset>
28255 <access>write-only
</access>
28256 <resetValue>0x00000000</resetValue>
28260 <description>Key value
</description>
28261 <bitOffset>0</bitOffset>
28262 <bitWidth>16</bitWidth>
28268 <displayName>PR
</displayName>
28269 <description>Prescaler register
</description>
28270 <addressOffset>0x4</addressOffset>
28272 <access>read-write
</access>
28273 <resetValue>0x00000000</resetValue>
28277 <description>Prescaler divider
</description>
28278 <bitOffset>0</bitOffset>
28279 <bitWidth>3</bitWidth>
28285 <displayName>RLR
</displayName>
28286 <description>Reload register
</description>
28287 <addressOffset>0x8</addressOffset>
28289 <access>read-write
</access>
28290 <resetValue>0x00000FFF</resetValue>
28294 <description>Watchdog counter reload
28295 value
</description>
28296 <bitOffset>0</bitOffset>
28297 <bitWidth>12</bitWidth>
28303 <displayName>SR
</displayName>
28304 <description>Status register
</description>
28305 <addressOffset>0xC</addressOffset>
28307 <access>read-only
</access>
28308 <resetValue>0x00000000</resetValue>
28312 <description>Watchdog prescaler value
28313 update
</description>
28314 <bitOffset>0</bitOffset>
28315 <bitWidth>1</bitWidth>
28319 <description>Watchdog counter reload value
28320 update
</description>
28321 <bitOffset>1</bitOffset>
28322 <bitWidth>1</bitWidth>
28326 <description>Watchdog counter window value
28327 update
</description>
28328 <bitOffset>2</bitOffset>
28329 <bitWidth>1</bitWidth>
28335 <displayName>WINR
</displayName>
28336 <description>Window register
</description>
28337 <addressOffset>0x10</addressOffset>
28339 <access>read-write
</access>
28340 <resetValue>0x00000FFF</resetValue>
28344 <description>Watchdog counter window
28345 value
</description>
28346 <bitOffset>0</bitOffset>
28347 <bitWidth>12</bitWidth>
28355 <description>Window watchdog
</description>
28356 <groupName>WWDG
</groupName>
28357 <baseAddress>0x40002C00</baseAddress>
28359 <offset>0x0</offset>
28361 <usage>registers
</usage>
28365 <description>Window Watchdog interrupt
</description>
28371 <displayName>CR
</displayName>
28372 <description>Control register
</description>
28373 <addressOffset>0x0</addressOffset>
28375 <access>read-write
</access>
28376 <resetValue>0x0000007F</resetValue>
28380 <description>7-bit counter
</description>
28381 <bitOffset>0</bitOffset>
28382 <bitWidth>7</bitWidth>
28386 <description>Activation bit
</description>
28387 <bitOffset>7</bitOffset>
28388 <bitWidth>1</bitWidth>
28394 <displayName>CFR
</displayName>
28395 <description>Configuration register
</description>
28396 <addressOffset>0x4</addressOffset>
28398 <access>read-write
</access>
28399 <resetValue>0x0000007F</resetValue>
28403 <description>Early wakeup interrupt
</description>
28404 <bitOffset>9</bitOffset>
28405 <bitWidth>1</bitWidth>
28409 <description>Timer base
</description>
28410 <bitOffset>7</bitOffset>
28411 <bitWidth>2</bitWidth>
28415 <description>7-bit window value
</description>
28416 <bitOffset>0</bitOffset>
28417 <bitWidth>7</bitWidth>
28423 <displayName>SR
</displayName>
28424 <description>Status register
</description>
28425 <addressOffset>0x8</addressOffset>
28427 <access>read-write
</access>
28428 <resetValue>0x00000000</resetValue>
28432 <description>Early wakeup interrupt
28434 <bitOffset>0</bitOffset>
28435 <bitWidth>1</bitWidth>
28443 <description>Real-time clock
</description>
28444 <groupName>RTC
</groupName>
28445 <baseAddress>0x40002800</baseAddress>
28447 <offset>0x0</offset>
28449 <usage>registers
</usage>
28452 <name>RTC_WKUP
</name>
28453 <description>RTC Wakeup interrupt through the EXTI
28458 <name>RTCAlarm
</name>
28459 <description>RTC alarm interrupt
</description>
28465 <displayName>TR
</displayName>
28466 <description>time register
</description>
28467 <addressOffset>0x0</addressOffset>
28469 <access>read-write
</access>
28470 <resetValue>0x00000000</resetValue>
28474 <description>AM/PM notation
</description>
28475 <bitOffset>22</bitOffset>
28476 <bitWidth>1</bitWidth>
28480 <description>Hour tens in BCD format
</description>
28481 <bitOffset>20</bitOffset>
28482 <bitWidth>2</bitWidth>
28486 <description>Hour units in BCD format
</description>
28487 <bitOffset>16</bitOffset>
28488 <bitWidth>4</bitWidth>
28492 <description>Minute tens in BCD format
</description>
28493 <bitOffset>12</bitOffset>
28494 <bitWidth>3</bitWidth>
28498 <description>Minute units in BCD format
</description>
28499 <bitOffset>8</bitOffset>
28500 <bitWidth>4</bitWidth>
28504 <description>Second tens in BCD format
</description>
28505 <bitOffset>4</bitOffset>
28506 <bitWidth>3</bitWidth>
28510 <description>Second units in BCD format
</description>
28511 <bitOffset>0</bitOffset>
28512 <bitWidth>4</bitWidth>
28518 <displayName>DR
</displayName>
28519 <description>date register
</description>
28520 <addressOffset>0x4</addressOffset>
28522 <access>read-write
</access>
28523 <resetValue>0x00002101</resetValue>
28527 <description>Year tens in BCD format
</description>
28528 <bitOffset>20</bitOffset>
28529 <bitWidth>4</bitWidth>
28533 <description>Year units in BCD format
</description>
28534 <bitOffset>16</bitOffset>
28535 <bitWidth>4</bitWidth>
28539 <description>Week day units
</description>
28540 <bitOffset>13</bitOffset>
28541 <bitWidth>3</bitWidth>
28545 <description>Month tens in BCD format
</description>
28546 <bitOffset>12</bitOffset>
28547 <bitWidth>1</bitWidth>
28551 <description>Month units in BCD format
</description>
28552 <bitOffset>8</bitOffset>
28553 <bitWidth>4</bitWidth>
28557 <description>Date tens in BCD format
</description>
28558 <bitOffset>4</bitOffset>
28559 <bitWidth>2</bitWidth>
28563 <description>Date units in BCD format
</description>
28564 <bitOffset>0</bitOffset>
28565 <bitWidth>4</bitWidth>
28571 <displayName>CR
</displayName>
28572 <description>control register
</description>
28573 <addressOffset>0x8</addressOffset>
28575 <access>read-write
</access>
28576 <resetValue>0x00000000</resetValue>
28579 <name>WCKSEL
</name>
28580 <description>Wakeup clock selection
</description>
28581 <bitOffset>0</bitOffset>
28582 <bitWidth>3</bitWidth>
28585 <name>TSEDGE
</name>
28586 <description>Time-stamp event active
28588 <bitOffset>3</bitOffset>
28589 <bitWidth>1</bitWidth>
28592 <name>REFCKON
</name>
28593 <description>Reference clock detection enable (
50 or
28594 60 Hz)
</description>
28595 <bitOffset>4</bitOffset>
28596 <bitWidth>1</bitWidth>
28599 <name>BYPSHAD
</name>
28600 <description>Bypass the shadow
28601 registers
</description>
28602 <bitOffset>5</bitOffset>
28603 <bitWidth>1</bitWidth>
28607 <description>Hour format
</description>
28608 <bitOffset>6</bitOffset>
28609 <bitWidth>1</bitWidth>
28613 <description>Alarm A enable
</description>
28614 <bitOffset>8</bitOffset>
28615 <bitWidth>1</bitWidth>
28619 <description>Alarm B enable
</description>
28620 <bitOffset>9</bitOffset>
28621 <bitWidth>1</bitWidth>
28625 <description>Wakeup timer enable
</description>
28626 <bitOffset>10</bitOffset>
28627 <bitWidth>1</bitWidth>
28631 <description>Time stamp enable
</description>
28632 <bitOffset>11</bitOffset>
28633 <bitWidth>1</bitWidth>
28636 <name>ALRAIE
</name>
28637 <description>Alarm A interrupt enable
</description>
28638 <bitOffset>12</bitOffset>
28639 <bitWidth>1</bitWidth>
28642 <name>ALRBIE
</name>
28643 <description>Alarm B interrupt enable
</description>
28644 <bitOffset>13</bitOffset>
28645 <bitWidth>1</bitWidth>
28649 <description>Wakeup timer interrupt
28650 enable
</description>
28651 <bitOffset>14</bitOffset>
28652 <bitWidth>1</bitWidth>
28656 <description>Time-stamp interrupt
28657 enable
</description>
28658 <bitOffset>15</bitOffset>
28659 <bitWidth>1</bitWidth>
28663 <description>Add
1 hour (summer time
28664 change)
</description>
28665 <bitOffset>16</bitOffset>
28666 <bitWidth>1</bitWidth>
28670 <description>Subtract
1 hour (winter time
28671 change)
</description>
28672 <bitOffset>17</bitOffset>
28673 <bitWidth>1</bitWidth>
28677 <description>Backup
</description>
28678 <bitOffset>18</bitOffset>
28679 <bitWidth>1</bitWidth>
28683 <description>Calibration output
28684 selection
</description>
28685 <bitOffset>19</bitOffset>
28686 <bitWidth>1</bitWidth>
28690 <description>Output polarity
</description>
28691 <bitOffset>20</bitOffset>
28692 <bitWidth>1</bitWidth>
28696 <description>Output selection
</description>
28697 <bitOffset>21</bitOffset>
28698 <bitWidth>2</bitWidth>
28702 <description>Calibration output enable
</description>
28703 <bitOffset>23</bitOffset>
28704 <bitWidth>1</bitWidth>
28710 <displayName>ISR
</displayName>
28711 <description>initialization and status
28712 register
</description>
28713 <addressOffset>0xC</addressOffset>
28715 <resetValue>0x00000007</resetValue>
28718 <name>ALRAWF
</name>
28719 <description>Alarm A write flag
</description>
28720 <bitOffset>0</bitOffset>
28721 <bitWidth>1</bitWidth>
28722 <access>read-only
</access>
28725 <name>ALRBWF
</name>
28726 <description>Alarm B write flag
</description>
28727 <bitOffset>1</bitOffset>
28728 <bitWidth>1</bitWidth>
28729 <access>read-only
</access>
28733 <description>Wakeup timer write flag
</description>
28734 <bitOffset>2</bitOffset>
28735 <bitWidth>1</bitWidth>
28736 <access>read-only
</access>
28740 <description>Shift operation pending
</description>
28741 <bitOffset>3</bitOffset>
28742 <bitWidth>1</bitWidth>
28743 <access>read-write
</access>
28747 <description>Initialization status flag
</description>
28748 <bitOffset>4</bitOffset>
28749 <bitWidth>1</bitWidth>
28750 <access>read-only
</access>
28754 <description>Registers synchronization
28756 <bitOffset>5</bitOffset>
28757 <bitWidth>1</bitWidth>
28758 <access>read-write
</access>
28762 <description>Initialization flag
</description>
28763 <bitOffset>6</bitOffset>
28764 <bitWidth>1</bitWidth>
28765 <access>read-only
</access>
28769 <description>Initialization mode
</description>
28770 <bitOffset>7</bitOffset>
28771 <bitWidth>1</bitWidth>
28772 <access>read-write
</access>
28776 <description>Alarm A flag
</description>
28777 <bitOffset>8</bitOffset>
28778 <bitWidth>1</bitWidth>
28779 <access>read-write
</access>
28783 <description>Alarm B flag
</description>
28784 <bitOffset>9</bitOffset>
28785 <bitWidth>1</bitWidth>
28786 <access>read-write
</access>
28790 <description>Wakeup timer flag
</description>
28791 <bitOffset>10</bitOffset>
28792 <bitWidth>1</bitWidth>
28793 <access>read-write
</access>
28797 <description>Time-stamp flag
</description>
28798 <bitOffset>11</bitOffset>
28799 <bitWidth>1</bitWidth>
28800 <access>read-write
</access>
28804 <description>Time-stamp overflow flag
</description>
28805 <bitOffset>12</bitOffset>
28806 <bitWidth>1</bitWidth>
28807 <access>read-write
</access>
28810 <name>TAMP1F
</name>
28811 <description>Tamper detection flag
</description>
28812 <bitOffset>13</bitOffset>
28813 <bitWidth>1</bitWidth>
28814 <access>read-write
</access>
28817 <name>TAMP2F
</name>
28818 <description>RTC_TAMP2 detection flag
</description>
28819 <bitOffset>14</bitOffset>
28820 <bitWidth>1</bitWidth>
28821 <access>read-write
</access>
28824 <name>TAMP3F
</name>
28825 <description>RTC_TAMP3 detection flag
</description>
28826 <bitOffset>15</bitOffset>
28827 <bitWidth>1</bitWidth>
28828 <access>read-write
</access>
28831 <name>RECALPF
</name>
28832 <description>Recalibration pending Flag
</description>
28833 <bitOffset>16</bitOffset>
28834 <bitWidth>1</bitWidth>
28835 <access>read-only
</access>
28841 <displayName>PRER
</displayName>
28842 <description>prescaler register
</description>
28843 <addressOffset>0x10</addressOffset>
28845 <access>read-write
</access>
28846 <resetValue>0x007F00FF</resetValue>
28849 <name>PREDIV_A
</name>
28850 <description>Asynchronous prescaler
28851 factor
</description>
28852 <bitOffset>16</bitOffset>
28853 <bitWidth>7</bitWidth>
28856 <name>PREDIV_S
</name>
28857 <description>Synchronous prescaler
28858 factor
</description>
28859 <bitOffset>0</bitOffset>
28860 <bitWidth>15</bitWidth>
28866 <displayName>WUTR
</displayName>
28867 <description>wakeup timer register
</description>
28868 <addressOffset>0x14</addressOffset>
28870 <access>read-write
</access>
28871 <resetValue>0x0000FFFF</resetValue>
28875 <description>Wakeup auto-reload value
28877 <bitOffset>0</bitOffset>
28878 <bitWidth>16</bitWidth>
28883 <name>ALRMAR
</name>
28884 <displayName>ALRMAR
</displayName>
28885 <description>alarm A register
</description>
28886 <addressOffset>0x1C</addressOffset>
28888 <access>read-write
</access>
28889 <resetValue>0x00000000</resetValue>
28893 <description>Alarm A date mask
</description>
28894 <bitOffset>31</bitOffset>
28895 <bitWidth>1</bitWidth>
28899 <description>Week day selection
</description>
28900 <bitOffset>30</bitOffset>
28901 <bitWidth>1</bitWidth>
28905 <description>Date tens in BCD format
</description>
28906 <bitOffset>28</bitOffset>
28907 <bitWidth>2</bitWidth>
28911 <description>Date units or day in BCD
28912 format
</description>
28913 <bitOffset>24</bitOffset>
28914 <bitWidth>4</bitWidth>
28918 <description>Alarm A hours mask
</description>
28919 <bitOffset>23</bitOffset>
28920 <bitWidth>1</bitWidth>
28924 <description>AM/PM notation
</description>
28925 <bitOffset>22</bitOffset>
28926 <bitWidth>1</bitWidth>
28930 <description>Hour tens in BCD format
</description>
28931 <bitOffset>20</bitOffset>
28932 <bitWidth>2</bitWidth>
28936 <description>Hour units in BCD format
</description>
28937 <bitOffset>16</bitOffset>
28938 <bitWidth>4</bitWidth>
28942 <description>Alarm A minutes mask
</description>
28943 <bitOffset>15</bitOffset>
28944 <bitWidth>1</bitWidth>
28948 <description>Minute tens in BCD format
</description>
28949 <bitOffset>12</bitOffset>
28950 <bitWidth>3</bitWidth>
28954 <description>Minute units in BCD format
</description>
28955 <bitOffset>8</bitOffset>
28956 <bitWidth>4</bitWidth>
28960 <description>Alarm A seconds mask
</description>
28961 <bitOffset>7</bitOffset>
28962 <bitWidth>1</bitWidth>
28966 <description>Second tens in BCD format
</description>
28967 <bitOffset>4</bitOffset>
28968 <bitWidth>3</bitWidth>
28972 <description>Second units in BCD format
</description>
28973 <bitOffset>0</bitOffset>
28974 <bitWidth>4</bitWidth>
28979 <name>ALRMBR
</name>
28980 <displayName>ALRMBR
</displayName>
28981 <description>alarm B register
</description>
28982 <addressOffset>0x20</addressOffset>
28984 <access>read-write
</access>
28985 <resetValue>0x00000000</resetValue>
28989 <description>Alarm B date mask
</description>
28990 <bitOffset>31</bitOffset>
28991 <bitWidth>1</bitWidth>
28995 <description>Week day selection
</description>
28996 <bitOffset>30</bitOffset>
28997 <bitWidth>1</bitWidth>
29001 <description>Date tens in BCD format
</description>
29002 <bitOffset>28</bitOffset>
29003 <bitWidth>2</bitWidth>
29007 <description>Date units or day in BCD
29008 format
</description>
29009 <bitOffset>24</bitOffset>
29010 <bitWidth>4</bitWidth>
29014 <description>Alarm B hours mask
</description>
29015 <bitOffset>23</bitOffset>
29016 <bitWidth>1</bitWidth>
29020 <description>AM/PM notation
</description>
29021 <bitOffset>22</bitOffset>
29022 <bitWidth>1</bitWidth>
29026 <description>Hour tens in BCD format
</description>
29027 <bitOffset>20</bitOffset>
29028 <bitWidth>2</bitWidth>
29032 <description>Hour units in BCD format
</description>
29033 <bitOffset>16</bitOffset>
29034 <bitWidth>4</bitWidth>
29038 <description>Alarm B minutes mask
</description>
29039 <bitOffset>15</bitOffset>
29040 <bitWidth>1</bitWidth>
29044 <description>Minute tens in BCD format
</description>
29045 <bitOffset>12</bitOffset>
29046 <bitWidth>3</bitWidth>
29050 <description>Minute units in BCD format
</description>
29051 <bitOffset>8</bitOffset>
29052 <bitWidth>4</bitWidth>
29056 <description>Alarm B seconds mask
</description>
29057 <bitOffset>7</bitOffset>
29058 <bitWidth>1</bitWidth>
29062 <description>Second tens in BCD format
</description>
29063 <bitOffset>4</bitOffset>
29064 <bitWidth>3</bitWidth>
29068 <description>Second units in BCD format
</description>
29069 <bitOffset>0</bitOffset>
29070 <bitWidth>4</bitWidth>
29076 <displayName>WPR
</displayName>
29077 <description>write protection register
</description>
29078 <addressOffset>0x24</addressOffset>
29080 <access>write-only
</access>
29081 <resetValue>0x00000000</resetValue>
29085 <description>Write protection key
</description>
29086 <bitOffset>0</bitOffset>
29087 <bitWidth>8</bitWidth>
29093 <displayName>SSR
</displayName>
29094 <description>sub second register
</description>
29095 <addressOffset>0x28</addressOffset>
29097 <access>read-only
</access>
29098 <resetValue>0x00000000</resetValue>
29102 <description>Sub second value
</description>
29103 <bitOffset>0</bitOffset>
29104 <bitWidth>16</bitWidth>
29109 <name>SHIFTR
</name>
29110 <displayName>SHIFTR
</displayName>
29111 <description>shift control register
</description>
29112 <addressOffset>0x2C</addressOffset>
29114 <access>write-only
</access>
29115 <resetValue>0x00000000</resetValue>
29119 <description>Add one second
</description>
29120 <bitOffset>31</bitOffset>
29121 <bitWidth>1</bitWidth>
29125 <description>Subtract a fraction of a
29126 second
</description>
29127 <bitOffset>0</bitOffset>
29128 <bitWidth>15</bitWidth>
29134 <displayName>TSTR
</displayName>
29135 <description>time stamp time register
</description>
29136 <addressOffset>0x30</addressOffset>
29138 <access>read-only
</access>
29139 <resetValue>0x00000000</resetValue>
29143 <description>Second units in BCD format
</description>
29144 <bitOffset>0</bitOffset>
29145 <bitWidth>4</bitWidth>
29149 <description>Second tens in BCD format
</description>
29150 <bitOffset>4</bitOffset>
29151 <bitWidth>3</bitWidth>
29155 <description>Minute units in BCD format
</description>
29156 <bitOffset>8</bitOffset>
29157 <bitWidth>4</bitWidth>
29161 <description>Minute tens in BCD format
</description>
29162 <bitOffset>12</bitOffset>
29163 <bitWidth>3</bitWidth>
29167 <description>Hour units in BCD format
</description>
29168 <bitOffset>16</bitOffset>
29169 <bitWidth>4</bitWidth>
29173 <description>Hour tens in BCD format
</description>
29174 <bitOffset>20</bitOffset>
29175 <bitWidth>2</bitWidth>
29179 <description>AM/PM notation
</description>
29180 <bitOffset>22</bitOffset>
29181 <bitWidth>1</bitWidth>
29187 <displayName>TSDR
</displayName>
29188 <description>time stamp date register
</description>
29189 <addressOffset>0x34</addressOffset>
29191 <access>read-only
</access>
29192 <resetValue>0x00000000</resetValue>
29196 <description>Week day units
</description>
29197 <bitOffset>13</bitOffset>
29198 <bitWidth>3</bitWidth>
29202 <description>Month tens in BCD format
</description>
29203 <bitOffset>12</bitOffset>
29204 <bitWidth>1</bitWidth>
29208 <description>Month units in BCD format
</description>
29209 <bitOffset>8</bitOffset>
29210 <bitWidth>4</bitWidth>
29214 <description>Date tens in BCD format
</description>
29215 <bitOffset>4</bitOffset>
29216 <bitWidth>2</bitWidth>
29220 <description>Date units in BCD format
</description>
29221 <bitOffset>0</bitOffset>
29222 <bitWidth>4</bitWidth>
29228 <displayName>TSSSR
</displayName>
29229 <description>timestamp sub second register
</description>
29230 <addressOffset>0x38</addressOffset>
29232 <access>read-only
</access>
29233 <resetValue>0x00000000</resetValue>
29237 <description>Sub second value
</description>
29238 <bitOffset>0</bitOffset>
29239 <bitWidth>16</bitWidth>
29245 <displayName>CALR
</displayName>
29246 <description>calibration register
</description>
29247 <addressOffset>0x3C</addressOffset>
29249 <access>read-write
</access>
29250 <resetValue>0x00000000</resetValue>
29254 <description>Increase frequency of RTC by
488.5
29256 <bitOffset>15</bitOffset>
29257 <bitWidth>1</bitWidth>
29261 <description>Use an
8-second calibration cycle
29262 period
</description>
29263 <bitOffset>14</bitOffset>
29264 <bitWidth>1</bitWidth>
29267 <name>CALW16
</name>
29268 <description>Use a
16-second calibration cycle
29269 period
</description>
29270 <bitOffset>13</bitOffset>
29271 <bitWidth>1</bitWidth>
29275 <description>Calibration minus
</description>
29276 <bitOffset>0</bitOffset>
29277 <bitWidth>9</bitWidth>
29283 <displayName>TAFCR
</displayName>
29284 <description>tamper and alternate function configuration
29285 register
</description>
29286 <addressOffset>0x40</addressOffset>
29288 <access>read-write
</access>
29289 <resetValue>0x00000000</resetValue>
29292 <name>TAMP1E
</name>
29293 <description>Tamper
1 detection enable
</description>
29294 <bitOffset>0</bitOffset>
29295 <bitWidth>1</bitWidth>
29298 <name>TAMP1TRG
</name>
29299 <description>Active level for tamper
1</description>
29300 <bitOffset>1</bitOffset>
29301 <bitWidth>1</bitWidth>
29304 <name>TAMPIE
</name>
29305 <description>Tamper interrupt enable
</description>
29306 <bitOffset>2</bitOffset>
29307 <bitWidth>1</bitWidth>
29310 <name>TAMP2E
</name>
29311 <description>Tamper
2 detection enable
</description>
29312 <bitOffset>3</bitOffset>
29313 <bitWidth>1</bitWidth>
29316 <name>TAMP2TRG
</name>
29317 <description>Active level for tamper
2</description>
29318 <bitOffset>4</bitOffset>
29319 <bitWidth>1</bitWidth>
29322 <name>TAMP3E
</name>
29323 <description>Tamper
3 detection enable
</description>
29324 <bitOffset>5</bitOffset>
29325 <bitWidth>1</bitWidth>
29328 <name>TAMP3TRG
</name>
29329 <description>Active level for tamper
3</description>
29330 <bitOffset>6</bitOffset>
29331 <bitWidth>1</bitWidth>
29334 <name>TAMPTS
</name>
29335 <description>Activate timestamp on tamper detection
29336 event
</description>
29337 <bitOffset>7</bitOffset>
29338 <bitWidth>1</bitWidth>
29341 <name>TAMPFREQ
</name>
29342 <description>Tamper sampling frequency
</description>
29343 <bitOffset>8</bitOffset>
29344 <bitWidth>3</bitWidth>
29347 <name>TAMPFLT
</name>
29348 <description>Tamper filter count
</description>
29349 <bitOffset>11</bitOffset>
29350 <bitWidth>2</bitWidth>
29353 <name>TAMPPRCH
</name>
29354 <description>Tamper precharge duration
</description>
29355 <bitOffset>13</bitOffset>
29356 <bitWidth>2</bitWidth>
29359 <name>TAMPPUDIS
</name>
29360 <description>TAMPER pull-up disable
</description>
29361 <bitOffset>15</bitOffset>
29362 <bitWidth>1</bitWidth>
29365 <name>PC13VALUE
</name>
29366 <description>PC13 value
</description>
29367 <bitOffset>18</bitOffset>
29368 <bitWidth>1</bitWidth>
29371 <name>PC13MODE
</name>
29372 <description>PC13 mode
</description>
29373 <bitOffset>19</bitOffset>
29374 <bitWidth>1</bitWidth>
29377 <name>PC14VALUE
</name>
29378 <description>PC14 value
</description>
29379 <bitOffset>20</bitOffset>
29380 <bitWidth>1</bitWidth>
29383 <name>PC14MODE
</name>
29384 <description>PC
14 mode
</description>
29385 <bitOffset>21</bitOffset>
29386 <bitWidth>1</bitWidth>
29389 <name>PC15VALUE
</name>
29390 <description>PC15 value
</description>
29391 <bitOffset>22</bitOffset>
29392 <bitWidth>1</bitWidth>
29395 <name>PC15MODE
</name>
29396 <description>PC15 mode
</description>
29397 <bitOffset>23</bitOffset>
29398 <bitWidth>1</bitWidth>
29403 <name>ALRMASSR
</name>
29404 <displayName>ALRMASSR
</displayName>
29405 <description>alarm A sub second register
</description>
29406 <addressOffset>0x44</addressOffset>
29408 <access>read-write
</access>
29409 <resetValue>0x00000000</resetValue>
29412 <name>MASKSS
</name>
29413 <description>Mask the most-significant bits starting
29414 at this bit
</description>
29415 <bitOffset>24</bitOffset>
29416 <bitWidth>4</bitWidth>
29420 <description>Sub seconds value
</description>
29421 <bitOffset>0</bitOffset>
29422 <bitWidth>15</bitWidth>
29427 <name>ALRMBSSR
</name>
29428 <displayName>ALRMBSSR
</displayName>
29429 <description>alarm B sub second register
</description>
29430 <addressOffset>0x48</addressOffset>
29432 <access>read-write
</access>
29433 <resetValue>0x00000000</resetValue>
29436 <name>MASKSS
</name>
29437 <description>Mask the most-significant bits starting
29438 at this bit
</description>
29439 <bitOffset>24</bitOffset>
29440 <bitWidth>4</bitWidth>
29444 <description>Sub seconds value
</description>
29445 <bitOffset>0</bitOffset>
29446 <bitWidth>15</bitWidth>
29452 <displayName>BKP0R
</displayName>
29453 <description>backup register
</description>
29454 <addressOffset>0x50</addressOffset>
29456 <access>read-write
</access>
29457 <resetValue>0x00000000</resetValue>
29461 <description>BKP
</description>
29462 <bitOffset>0</bitOffset>
29463 <bitWidth>32</bitWidth>
29469 <displayName>BKP1R
</displayName>
29470 <description>backup register
</description>
29471 <addressOffset>0x54</addressOffset>
29473 <access>read-write
</access>
29474 <resetValue>0x00000000</resetValue>
29478 <description>BKP
</description>
29479 <bitOffset>0</bitOffset>
29480 <bitWidth>32</bitWidth>
29486 <displayName>BKP2R
</displayName>
29487 <description>backup register
</description>
29488 <addressOffset>0x58</addressOffset>
29490 <access>read-write
</access>
29491 <resetValue>0x00000000</resetValue>
29495 <description>BKP
</description>
29496 <bitOffset>0</bitOffset>
29497 <bitWidth>32</bitWidth>
29503 <displayName>BKP3R
</displayName>
29504 <description>backup register
</description>
29505 <addressOffset>0x5C</addressOffset>
29507 <access>read-write
</access>
29508 <resetValue>0x00000000</resetValue>
29512 <description>BKP
</description>
29513 <bitOffset>0</bitOffset>
29514 <bitWidth>32</bitWidth>
29520 <displayName>BKP4R
</displayName>
29521 <description>backup register
</description>
29522 <addressOffset>0x60</addressOffset>
29524 <access>read-write
</access>
29525 <resetValue>0x00000000</resetValue>
29529 <description>BKP
</description>
29530 <bitOffset>0</bitOffset>
29531 <bitWidth>32</bitWidth>
29537 <displayName>BKP5R
</displayName>
29538 <description>backup register
</description>
29539 <addressOffset>0x64</addressOffset>
29541 <access>read-write
</access>
29542 <resetValue>0x00000000</resetValue>
29546 <description>BKP
</description>
29547 <bitOffset>0</bitOffset>
29548 <bitWidth>32</bitWidth>
29554 <displayName>BKP6R
</displayName>
29555 <description>backup register
</description>
29556 <addressOffset>0x68</addressOffset>
29558 <access>read-write
</access>
29559 <resetValue>0x00000000</resetValue>
29563 <description>BKP
</description>
29564 <bitOffset>0</bitOffset>
29565 <bitWidth>32</bitWidth>
29571 <displayName>BKP7R
</displayName>
29572 <description>backup register
</description>
29573 <addressOffset>0x6C</addressOffset>
29575 <access>read-write
</access>
29576 <resetValue>0x00000000</resetValue>
29580 <description>BKP
</description>
29581 <bitOffset>0</bitOffset>
29582 <bitWidth>32</bitWidth>
29588 <displayName>BKP8R
</displayName>
29589 <description>backup register
</description>
29590 <addressOffset>0x70</addressOffset>
29592 <access>read-write
</access>
29593 <resetValue>0x00000000</resetValue>
29597 <description>BKP
</description>
29598 <bitOffset>0</bitOffset>
29599 <bitWidth>32</bitWidth>
29605 <displayName>BKP9R
</displayName>
29606 <description>backup register
</description>
29607 <addressOffset>0x74</addressOffset>
29609 <access>read-write
</access>
29610 <resetValue>0x00000000</resetValue>
29614 <description>BKP
</description>
29615 <bitOffset>0</bitOffset>
29616 <bitWidth>32</bitWidth>
29621 <name>BKP10R
</name>
29622 <displayName>BKP10R
</displayName>
29623 <description>backup register
</description>
29624 <addressOffset>0x78</addressOffset>
29626 <access>read-write
</access>
29627 <resetValue>0x00000000</resetValue>
29631 <description>BKP
</description>
29632 <bitOffset>0</bitOffset>
29633 <bitWidth>32</bitWidth>
29638 <name>BKP11R
</name>
29639 <displayName>BKP11R
</displayName>
29640 <description>backup register
</description>
29641 <addressOffset>0x7C</addressOffset>
29643 <access>read-write
</access>
29644 <resetValue>0x00000000</resetValue>
29648 <description>BKP
</description>
29649 <bitOffset>0</bitOffset>
29650 <bitWidth>32</bitWidth>
29655 <name>BKP12R
</name>
29656 <displayName>BKP12R
</displayName>
29657 <description>backup register
</description>
29658 <addressOffset>0x80</addressOffset>
29660 <access>read-write
</access>
29661 <resetValue>0x00000000</resetValue>
29665 <description>BKP
</description>
29666 <bitOffset>0</bitOffset>
29667 <bitWidth>32</bitWidth>
29672 <name>BKP13R
</name>
29673 <displayName>BKP13R
</displayName>
29674 <description>backup register
</description>
29675 <addressOffset>0x84</addressOffset>
29677 <access>read-write
</access>
29678 <resetValue>0x00000000</resetValue>
29682 <description>BKP
</description>
29683 <bitOffset>0</bitOffset>
29684 <bitWidth>32</bitWidth>
29689 <name>BKP14R
</name>
29690 <displayName>BKP14R
</displayName>
29691 <description>backup register
</description>
29692 <addressOffset>0x88</addressOffset>
29694 <access>read-write
</access>
29695 <resetValue>0x00000000</resetValue>
29699 <description>BKP
</description>
29700 <bitOffset>0</bitOffset>
29701 <bitWidth>32</bitWidth>
29706 <name>BKP15R
</name>
29707 <displayName>BKP15R
</displayName>
29708 <description>backup register
</description>
29709 <addressOffset>0x8C</addressOffset>
29711 <access>read-write
</access>
29712 <resetValue>0x00000000</resetValue>
29716 <description>BKP
</description>
29717 <bitOffset>0</bitOffset>
29718 <bitWidth>32</bitWidth>
29723 <name>BKP16R
</name>
29724 <displayName>BKP16R
</displayName>
29725 <description>backup register
</description>
29726 <addressOffset>0x90</addressOffset>
29728 <access>read-write
</access>
29729 <resetValue>0x00000000</resetValue>
29733 <description>BKP
</description>
29734 <bitOffset>0</bitOffset>
29735 <bitWidth>32</bitWidth>
29740 <name>BKP17R
</name>
29741 <displayName>BKP17R
</displayName>
29742 <description>backup register
</description>
29743 <addressOffset>0x94</addressOffset>
29745 <access>read-write
</access>
29746 <resetValue>0x00000000</resetValue>
29750 <description>BKP
</description>
29751 <bitOffset>0</bitOffset>
29752 <bitWidth>32</bitWidth>
29757 <name>BKP18R
</name>
29758 <displayName>BKP18R
</displayName>
29759 <description>backup register
</description>
29760 <addressOffset>0x98</addressOffset>
29762 <access>read-write
</access>
29763 <resetValue>0x00000000</resetValue>
29767 <description>BKP
</description>
29768 <bitOffset>0</bitOffset>
29769 <bitWidth>32</bitWidth>
29774 <name>BKP19R
</name>
29775 <displayName>BKP19R
</displayName>
29776 <description>backup register
</description>
29777 <addressOffset>0x9C</addressOffset>
29779 <access>read-write
</access>
29780 <resetValue>0x00000000</resetValue>
29784 <description>BKP
</description>
29785 <bitOffset>0</bitOffset>
29786 <bitWidth>32</bitWidth>
29791 <name>BKP20R
</name>
29792 <displayName>BKP20R
</displayName>
29793 <description>backup register
</description>
29794 <addressOffset>0xA0</addressOffset>
29796 <access>read-write
</access>
29797 <resetValue>0x00000000</resetValue>
29801 <description>BKP
</description>
29802 <bitOffset>0</bitOffset>
29803 <bitWidth>32</bitWidth>
29808 <name>BKP21R
</name>
29809 <displayName>BKP21R
</displayName>
29810 <description>backup register
</description>
29811 <addressOffset>0xA4</addressOffset>
29813 <access>read-write
</access>
29814 <resetValue>0x00000000</resetValue>
29818 <description>BKP
</description>
29819 <bitOffset>0</bitOffset>
29820 <bitWidth>32</bitWidth>
29825 <name>BKP22R
</name>
29826 <displayName>BKP22R
</displayName>
29827 <description>backup register
</description>
29828 <addressOffset>0xA8</addressOffset>
29830 <access>read-write
</access>
29831 <resetValue>0x00000000</resetValue>
29835 <description>BKP
</description>
29836 <bitOffset>0</bitOffset>
29837 <bitWidth>32</bitWidth>
29842 <name>BKP23R
</name>
29843 <displayName>BKP23R
</displayName>
29844 <description>backup register
</description>
29845 <addressOffset>0xAC</addressOffset>
29847 <access>read-write
</access>
29848 <resetValue>0x00000000</resetValue>
29852 <description>BKP
</description>
29853 <bitOffset>0</bitOffset>
29854 <bitWidth>32</bitWidth>
29859 <name>BKP24R
</name>
29860 <displayName>BKP24R
</displayName>
29861 <description>backup register
</description>
29862 <addressOffset>0xB0</addressOffset>
29864 <access>read-write
</access>
29865 <resetValue>0x00000000</resetValue>
29869 <description>BKP
</description>
29870 <bitOffset>0</bitOffset>
29871 <bitWidth>32</bitWidth>
29876 <name>BKP25R
</name>
29877 <displayName>BKP25R
</displayName>
29878 <description>backup register
</description>
29879 <addressOffset>0xB4</addressOffset>
29881 <access>read-write
</access>
29882 <resetValue>0x00000000</resetValue>
29886 <description>BKP
</description>
29887 <bitOffset>0</bitOffset>
29888 <bitWidth>32</bitWidth>
29893 <name>BKP26R
</name>
29894 <displayName>BKP26R
</displayName>
29895 <description>backup register
</description>
29896 <addressOffset>0xB8</addressOffset>
29898 <access>read-write
</access>
29899 <resetValue>0x00000000</resetValue>
29903 <description>BKP
</description>
29904 <bitOffset>0</bitOffset>
29905 <bitWidth>32</bitWidth>
29910 <name>BKP27R
</name>
29911 <displayName>BKP27R
</displayName>
29912 <description>backup register
</description>
29913 <addressOffset>0xBC</addressOffset>
29915 <access>read-write
</access>
29916 <resetValue>0x00000000</resetValue>
29920 <description>BKP
</description>
29921 <bitOffset>0</bitOffset>
29922 <bitWidth>32</bitWidth>
29927 <name>BKP28R
</name>
29928 <displayName>BKP28R
</displayName>
29929 <description>backup register
</description>
29930 <addressOffset>0xC0</addressOffset>
29932 <access>read-write
</access>
29933 <resetValue>0x00000000</resetValue>
29937 <description>BKP
</description>
29938 <bitOffset>0</bitOffset>
29939 <bitWidth>32</bitWidth>
29944 <name>BKP29R
</name>
29945 <displayName>BKP29R
</displayName>
29946 <description>backup register
</description>
29947 <addressOffset>0xC4</addressOffset>
29949 <access>read-write
</access>
29950 <resetValue>0x00000000</resetValue>
29954 <description>BKP
</description>
29955 <bitOffset>0</bitOffset>
29956 <bitWidth>32</bitWidth>
29961 <name>BKP30R
</name>
29962 <displayName>BKP30R
</displayName>
29963 <description>backup register
</description>
29964 <addressOffset>0xC8</addressOffset>
29966 <access>read-write
</access>
29967 <resetValue>0x00000000</resetValue>
29971 <description>BKP
</description>
29972 <bitOffset>0</bitOffset>
29973 <bitWidth>32</bitWidth>
29978 <name>BKP31R
</name>
29979 <displayName>BKP31R
</displayName>
29980 <description>backup register
</description>
29981 <addressOffset>0xCC</addressOffset>
29983 <access>read-write
</access>
29984 <resetValue>0x00000000</resetValue>
29988 <description>BKP
</description>
29989 <bitOffset>0</bitOffset>
29990 <bitWidth>32</bitWidth>
29998 <description>Basic timers
</description>
29999 <groupName>TIMs
</groupName>
30000 <baseAddress>0x40001000</baseAddress>
30002 <offset>0x0</offset>
30004 <usage>registers
</usage>
30007 <name>TIM6_DACUNDER
</name>
30008 <description>TIM6 global and DAC12 underrun
30009 interrupts
</description>
30015 <displayName>CR1
</displayName>
30016 <description>control register
1</description>
30017 <addressOffset>0x0</addressOffset>
30019 <access>read-write
</access>
30020 <resetValue>0x0000</resetValue>
30024 <description>Counter enable
</description>
30025 <bitOffset>0</bitOffset>
30026 <bitWidth>1</bitWidth>
30030 <description>Update disable
</description>
30031 <bitOffset>1</bitOffset>
30032 <bitWidth>1</bitWidth>
30036 <description>Update request source
</description>
30037 <bitOffset>2</bitOffset>
30038 <bitWidth>1</bitWidth>
30042 <description>One-pulse mode
</description>
30043 <bitOffset>3</bitOffset>
30044 <bitWidth>1</bitWidth>
30048 <description>Auto-reload preload enable
</description>
30049 <bitOffset>7</bitOffset>
30050 <bitWidth>1</bitWidth>
30053 <name>UIFREMAP
</name>
30054 <description>UIF status bit remapping
</description>
30055 <bitOffset>11</bitOffset>
30056 <bitWidth>1</bitWidth>
30062 <displayName>CR2
</displayName>
30063 <description>control register
2</description>
30064 <addressOffset>0x4</addressOffset>
30066 <access>read-write
</access>
30067 <resetValue>0x0000</resetValue>
30071 <description>Master mode selection
</description>
30072 <bitOffset>4</bitOffset>
30073 <bitWidth>3</bitWidth>
30079 <displayName>DIER
</displayName>
30080 <description>DMA/Interrupt enable register
</description>
30081 <addressOffset>0xC</addressOffset>
30083 <access>read-write
</access>
30084 <resetValue>0x0000</resetValue>
30088 <description>Update DMA request enable
</description>
30089 <bitOffset>8</bitOffset>
30090 <bitWidth>1</bitWidth>
30094 <description>Update interrupt enable
</description>
30095 <bitOffset>0</bitOffset>
30096 <bitWidth>1</bitWidth>
30102 <displayName>SR
</displayName>
30103 <description>status register
</description>
30104 <addressOffset>0x10</addressOffset>
30106 <access>read-write
</access>
30107 <resetValue>0x0000</resetValue>
30111 <description>Update interrupt flag
</description>
30112 <bitOffset>0</bitOffset>
30113 <bitWidth>1</bitWidth>
30119 <displayName>EGR
</displayName>
30120 <description>event generation register
</description>
30121 <addressOffset>0x14</addressOffset>
30123 <access>write-only
</access>
30124 <resetValue>0x0000</resetValue>
30128 <description>Update generation
</description>
30129 <bitOffset>0</bitOffset>
30130 <bitWidth>1</bitWidth>
30136 <displayName>CNT
</displayName>
30137 <description>counter
</description>
30138 <addressOffset>0x24</addressOffset>
30140 <resetValue>0x00000000</resetValue>
30144 <description>Low counter value
</description>
30145 <bitOffset>0</bitOffset>
30146 <bitWidth>16</bitWidth>
30147 <access>read-write
</access>
30150 <name>UIFCPY
</name>
30151 <description>UIF Copy
</description>
30152 <bitOffset>31</bitOffset>
30153 <bitWidth>1</bitWidth>
30154 <access>read-only
</access>
30160 <displayName>PSC
</displayName>
30161 <description>prescaler
</description>
30162 <addressOffset>0x28</addressOffset>
30164 <access>read-write
</access>
30165 <resetValue>0x0000</resetValue>
30169 <description>Prescaler value
</description>
30170 <bitOffset>0</bitOffset>
30171 <bitWidth>16</bitWidth>
30177 <displayName>ARR
</displayName>
30178 <description>auto-reload register
</description>
30179 <addressOffset>0x2C</addressOffset>
30181 <access>read-write
</access>
30182 <resetValue>0x00000000</resetValue>
30186 <description>Low Auto-reload value
</description>
30187 <bitOffset>0</bitOffset>
30188 <bitWidth>16</bitWidth>
30194 <peripheral derivedFrom=
"TIM6">
30196 <baseAddress>0x40001400</baseAddress>
30199 <description>TIM7 global interrupt
</description>
30205 <description>Digital-to-analog converter
</description>
30206 <groupName>DAC
</groupName>
30207 <baseAddress>0x40007400</baseAddress>
30209 <offset>0x0</offset>
30211 <usage>registers
</usage>
30214 <name>TIM6_DACUNDER
</name>
30215 <description>TIM6 global and DAC12 underrun
30216 interrupts
</description>
30222 <displayName>CR
</displayName>
30223 <description>control register
</description>
30224 <addressOffset>0x0</addressOffset>
30226 <access>read-write
</access>
30227 <resetValue>0x00000000</resetValue>
30230 <name>DMAUDRIE2
</name>
30231 <description>DAC channel2 DMA underrun interrupt
30232 enable
</description>
30233 <bitOffset>29</bitOffset>
30234 <bitWidth>1</bitWidth>
30237 <name>DMAEN2
</name>
30238 <description>DAC channel2 DMA enable
</description>
30239 <bitOffset>28</bitOffset>
30240 <bitWidth>1</bitWidth>
30244 <description>DAC channel2 mask/amplitude
30245 selector
</description>
30246 <bitOffset>24</bitOffset>
30247 <bitWidth>4</bitWidth>
30251 <description>DAC channel2 noise/triangle wave
30252 generation enable
</description>
30253 <bitOffset>22</bitOffset>
30254 <bitWidth>2</bitWidth>
30258 <description>DAC channel2 trigger
30259 selection
</description>
30260 <bitOffset>19</bitOffset>
30261 <bitWidth>3</bitWidth>
30265 <description>DAC channel2 trigger
30266 enable
</description>
30267 <bitOffset>18</bitOffset>
30268 <bitWidth>1</bitWidth>
30272 <description>DAC channel2 output buffer
30273 disable
</description>
30274 <bitOffset>17</bitOffset>
30275 <bitWidth>1</bitWidth>
30279 <description>DAC channel2 enable
</description>
30280 <bitOffset>16</bitOffset>
30281 <bitWidth>1</bitWidth>
30284 <name>DMAUDRIE1
</name>
30285 <description>DAC channel1 DMA Underrun Interrupt
30286 enable
</description>
30287 <bitOffset>13</bitOffset>
30288 <bitWidth>1</bitWidth>
30291 <name>DMAEN1
</name>
30292 <description>DAC channel1 DMA enable
</description>
30293 <bitOffset>12</bitOffset>
30294 <bitWidth>1</bitWidth>
30298 <description>DAC channel1 mask/amplitude
30299 selector
</description>
30300 <bitOffset>8</bitOffset>
30301 <bitWidth>4</bitWidth>
30305 <description>DAC channel1 noise/triangle wave
30306 generation enable
</description>
30307 <bitOffset>6</bitOffset>
30308 <bitWidth>2</bitWidth>
30312 <description>DAC channel1 trigger
30313 selection
</description>
30314 <bitOffset>3</bitOffset>
30315 <bitWidth>3</bitWidth>
30319 <description>DAC channel1 trigger
30320 enable
</description>
30321 <bitOffset>2</bitOffset>
30322 <bitWidth>1</bitWidth>
30326 <description>DAC channel1 output buffer
30327 disable
</description>
30328 <bitOffset>1</bitOffset>
30329 <bitWidth>1</bitWidth>
30333 <description>DAC channel1 enable
</description>
30334 <bitOffset>0</bitOffset>
30335 <bitWidth>1</bitWidth>
30340 <name>SWTRIGR
</name>
30341 <displayName>SWTRIGR
</displayName>
30342 <description>software trigger register
</description>
30343 <addressOffset>0x4</addressOffset>
30345 <access>write-only
</access>
30346 <resetValue>0x00000000</resetValue>
30349 <name>SWTRIG2
</name>
30350 <description>DAC channel2 software
30351 trigger
</description>
30352 <bitOffset>1</bitOffset>
30353 <bitWidth>1</bitWidth>
30356 <name>SWTRIG1
</name>
30357 <description>DAC channel1 software
30358 trigger
</description>
30359 <bitOffset>0</bitOffset>
30360 <bitWidth>1</bitWidth>
30365 <name>DHR12R1
</name>
30366 <displayName>DHR12R1
</displayName>
30367 <description>channel1
12-bit right-aligned data holding
30368 register
</description>
30369 <addressOffset>0x8</addressOffset>
30371 <access>read-write
</access>
30372 <resetValue>0x00000000</resetValue>
30375 <name>DACC1DHR
</name>
30376 <description>DAC channel1
12-bit right-aligned
30378 <bitOffset>0</bitOffset>
30379 <bitWidth>12</bitWidth>
30384 <name>DHR12L1
</name>
30385 <displayName>DHR12L1
</displayName>
30386 <description>channel1
12-bit left aligned data holding
30387 register
</description>
30388 <addressOffset>0xC</addressOffset>
30390 <access>read-write
</access>
30391 <resetValue>0x00000000</resetValue>
30394 <name>DACC1DHR
</name>
30395 <description>DAC channel1
12-bit left-aligned
30397 <bitOffset>4</bitOffset>
30398 <bitWidth>12</bitWidth>
30403 <name>DHR8R1
</name>
30404 <displayName>DHR8R1
</displayName>
30405 <description>channel1
8-bit right aligned data holding
30406 register
</description>
30407 <addressOffset>0x10</addressOffset>
30409 <access>read-write
</access>
30410 <resetValue>0x00000000</resetValue>
30413 <name>DACC1DHR
</name>
30414 <description>DAC channel1
8-bit right-aligned
30416 <bitOffset>0</bitOffset>
30417 <bitWidth>8</bitWidth>
30422 <name>DHR12R2
</name>
30423 <displayName>DHR12R2
</displayName>
30424 <description>channel2
12-bit right aligned data holding
30425 register
</description>
30426 <addressOffset>0x14</addressOffset>
30428 <access>read-write
</access>
30429 <resetValue>0x00000000</resetValue>
30432 <name>DACC2DHR
</name>
30433 <description>DAC channel2
12-bit right-aligned
30435 <bitOffset>0</bitOffset>
30436 <bitWidth>12</bitWidth>
30441 <name>DHR12L2
</name>
30442 <displayName>DHR12L2
</displayName>
30443 <description>channel2
12-bit left aligned data holding
30444 register
</description>
30445 <addressOffset>0x18</addressOffset>
30447 <access>read-write
</access>
30448 <resetValue>0x00000000</resetValue>
30451 <name>DACC2DHR
</name>
30452 <description>DAC channel2
12-bit left-aligned
30454 <bitOffset>4</bitOffset>
30455 <bitWidth>12</bitWidth>
30460 <name>DHR8R2
</name>
30461 <displayName>DHR8R2
</displayName>
30462 <description>channel2
8-bit right-aligned data holding
30463 register
</description>
30464 <addressOffset>0x1C</addressOffset>
30466 <access>read-write
</access>
30467 <resetValue>0x00000000</resetValue>
30470 <name>DACC2DHR
</name>
30471 <description>DAC channel2
8-bit right-aligned
30473 <bitOffset>0</bitOffset>
30474 <bitWidth>8</bitWidth>
30479 <name>DHR12RD
</name>
30480 <displayName>DHR12RD
</displayName>
30481 <description>Dual DAC
12-bit right-aligned data holding
30482 register
</description>
30483 <addressOffset>0x20</addressOffset>
30485 <access>read-write
</access>
30486 <resetValue>0x00000000</resetValue>
30489 <name>DACC2DHR
</name>
30490 <description>DAC channel2
12-bit right-aligned
30492 <bitOffset>16</bitOffset>
30493 <bitWidth>12</bitWidth>
30496 <name>DACC1DHR
</name>
30497 <description>DAC channel1
12-bit right-aligned
30499 <bitOffset>0</bitOffset>
30500 <bitWidth>12</bitWidth>
30505 <name>DHR12LD
</name>
30506 <displayName>DHR12LD
</displayName>
30507 <description>DUAL DAC
12-bit left aligned data holding
30508 register
</description>
30509 <addressOffset>0x24</addressOffset>
30511 <access>read-write
</access>
30512 <resetValue>0x00000000</resetValue>
30515 <name>DACC2DHR
</name>
30516 <description>DAC channel2
12-bit left-aligned
30518 <bitOffset>20</bitOffset>
30519 <bitWidth>12</bitWidth>
30522 <name>DACC1DHR
</name>
30523 <description>DAC channel1
12-bit left-aligned
30525 <bitOffset>4</bitOffset>
30526 <bitWidth>12</bitWidth>
30531 <name>DHR8RD
</name>
30532 <displayName>DHR8RD
</displayName>
30533 <description>DUAL DAC
8-bit right aligned data holding
30534 register
</description>
30535 <addressOffset>0x28</addressOffset>
30537 <access>read-write
</access>
30538 <resetValue>0x00000000</resetValue>
30541 <name>DACC2DHR
</name>
30542 <description>DAC channel2
8-bit right-aligned
30544 <bitOffset>8</bitOffset>
30545 <bitWidth>8</bitWidth>
30548 <name>DACC1DHR
</name>
30549 <description>DAC channel1
8-bit right-aligned
30551 <bitOffset>0</bitOffset>
30552 <bitWidth>8</bitWidth>
30558 <displayName>DOR1
</displayName>
30559 <description>channel1 data output register
</description>
30560 <addressOffset>0x2C</addressOffset>
30562 <access>read-only
</access>
30563 <resetValue>0x00000000</resetValue>
30566 <name>DACC1DOR
</name>
30567 <description>DAC channel1 data output
</description>
30568 <bitOffset>0</bitOffset>
30569 <bitWidth>12</bitWidth>
30575 <displayName>DOR2
</displayName>
30576 <description>channel2 data output register
</description>
30577 <addressOffset>0x30</addressOffset>
30579 <access>read-only
</access>
30580 <resetValue>0x00000000</resetValue>
30583 <name>DACC2DOR
</name>
30584 <description>DAC channel2 data output
</description>
30585 <bitOffset>0</bitOffset>
30586 <bitWidth>12</bitWidth>
30592 <displayName>SR
</displayName>
30593 <description>status register
</description>
30594 <addressOffset>0x34</addressOffset>
30596 <access>read-write
</access>
30597 <resetValue>0x00000000</resetValue>
30600 <name>DMAUDR2
</name>
30601 <description>DAC channel2 DMA underrun
30603 <bitOffset>29</bitOffset>
30604 <bitWidth>1</bitWidth>
30607 <name>DMAUDR1
</name>
30608 <description>DAC channel1 DMA underrun
30610 <bitOffset>13</bitOffset>
30611 <bitWidth>1</bitWidth>
30618 <name>DBGMCU
</name>
30619 <description>Debug support
</description>
30620 <groupName>DBGMCU
</groupName>
30621 <baseAddress>0xE0042000</baseAddress>
30623 <offset>0x0</offset>
30625 <usage>registers
</usage>
30629 <name>IDCODE
</name>
30630 <displayName>IDCODE
</displayName>
30631 <description>MCU Device ID Code Register
</description>
30632 <addressOffset>0x0</addressOffset>
30634 <access>read-only
</access>
30635 <resetValue>0x0</resetValue>
30638 <name>DEV_ID
</name>
30639 <description>Device Identifier
</description>
30640 <bitOffset>0</bitOffset>
30641 <bitWidth>12</bitWidth>
30644 <name>REV_ID
</name>
30645 <description>Revision Identifier
</description>
30646 <bitOffset>16</bitOffset>
30647 <bitWidth>16</bitWidth>
30653 <displayName>CR
</displayName>
30654 <description>Debug MCU Configuration
30655 Register
</description>
30656 <addressOffset>0x4</addressOffset>
30658 <access>read-write
</access>
30659 <resetValue>0x0</resetValue>
30662 <name>DBG_SLEEP
</name>
30663 <description>Debug Sleep mode
</description>
30664 <bitOffset>0</bitOffset>
30665 <bitWidth>1</bitWidth>
30668 <name>DBG_STOP
</name>
30669 <description>Debug Stop Mode
</description>
30670 <bitOffset>1</bitOffset>
30671 <bitWidth>1</bitWidth>
30674 <name>DBG_STANDBY
</name>
30675 <description>Debug Standby Mode
</description>
30676 <bitOffset>2</bitOffset>
30677 <bitWidth>1</bitWidth>
30680 <name>TRACE_IOEN
</name>
30681 <description>Trace pin assignment
30682 control
</description>
30683 <bitOffset>5</bitOffset>
30684 <bitWidth>1</bitWidth>
30687 <name>TRACE_MODE
</name>
30688 <description>Trace pin assignment
30689 control
</description>
30690 <bitOffset>6</bitOffset>
30691 <bitWidth>2</bitWidth>
30696 <name>APB1FZ
</name>
30697 <displayName>APB1FZ
</displayName>
30698 <description>APB Low Freeze Register
</description>
30699 <addressOffset>0x8</addressOffset>
30701 <access>read-write
</access>
30702 <resetValue>0x0</resetValue>
30705 <name>DBG_TIM2_STOP
</name>
30706 <description>Debug Timer
2 stopped when Core is
30707 halted
</description>
30708 <bitOffset>0</bitOffset>
30709 <bitWidth>1</bitWidth>
30712 <name>DBG_TIM3_STOP
</name>
30713 <description>Debug Timer
3 stopped when Core is
30714 halted
</description>
30715 <bitOffset>1</bitOffset>
30716 <bitWidth>1</bitWidth>
30719 <name>DBG_TIM4_STOP
</name>
30720 <description>Debug Timer
4 stopped when Core is
30721 halted
</description>
30722 <bitOffset>2</bitOffset>
30723 <bitWidth>1</bitWidth>
30726 <name>DBG_TIM5_STOP
</name>
30727 <description>Debug Timer
5 stopped when Core is
30728 halted
</description>
30729 <bitOffset>3</bitOffset>
30730 <bitWidth>1</bitWidth>
30733 <name>DBG_TIM6_STOP
</name>
30734 <description>Debug Timer
6 stopped when Core is
30735 halted
</description>
30736 <bitOffset>4</bitOffset>
30737 <bitWidth>1</bitWidth>
30740 <name>DBG_TIM7_STOP
</name>
30741 <description>Debug Timer
7 stopped when Core is
30742 halted
</description>
30743 <bitOffset>5</bitOffset>
30744 <bitWidth>1</bitWidth>
30747 <name>DBG_TIM12_STOP
</name>
30748 <description>Debug Timer
12 stopped when Core is
30749 halted
</description>
30750 <bitOffset>6</bitOffset>
30751 <bitWidth>1</bitWidth>
30754 <name>DBG_TIM13_STOP
</name>
30755 <description>Debug Timer
13 stopped when Core is
30756 halted
</description>
30757 <bitOffset>7</bitOffset>
30758 <bitWidth>1</bitWidth>
30761 <name>DBG_TIMER14_STOP
</name>
30762 <description>Debug Timer
14 stopped when Core is
30763 halted
</description>
30764 <bitOffset>8</bitOffset>
30765 <bitWidth>1</bitWidth>
30768 <name>DBG_TIM18_STOP
</name>
30769 <description>Debug Timer
18 stopped when Core is
30770 halted
</description>
30771 <bitOffset>9</bitOffset>
30772 <bitWidth>1</bitWidth>
30775 <name>DBG_RTC_STOP
</name>
30776 <description>Debug RTC stopped when Core is
30777 halted
</description>
30778 <bitOffset>10</bitOffset>
30779 <bitWidth>1</bitWidth>
30782 <name>DBG_WWDG_STOP
</name>
30783 <description>Debug Window Wachdog stopped when Core
30784 is halted
</description>
30785 <bitOffset>11</bitOffset>
30786 <bitWidth>1</bitWidth>
30789 <name>DBG_IWDG_STOP
</name>
30790 <description>Debug Independent Wachdog stopped when
30791 Core is halted
</description>
30792 <bitOffset>12</bitOffset>
30793 <bitWidth>1</bitWidth>
30796 <name>I2C1_SMBUS_TIMEOUT
</name>
30797 <description>SMBUS timeout mode stopped when Core is
30798 halted
</description>
30799 <bitOffset>21</bitOffset>
30800 <bitWidth>1</bitWidth>
30803 <name>I2C2_SMBUS_TIMEOUT
</name>
30804 <description>SMBUS timeout mode stopped when Core is
30805 halted
</description>
30806 <bitOffset>22</bitOffset>
30807 <bitWidth>1</bitWidth>
30810 <name>DBG_CAN_STOP
</name>
30811 <description>Debug CAN stopped when core is
30812 halted
</description>
30813 <bitOffset>25</bitOffset>
30814 <bitWidth>1</bitWidth>
30819 <name>APB2FZ
</name>
30820 <displayName>APB2FZ
</displayName>
30821 <description>APB High Freeze Register
</description>
30822 <addressOffset>0xC</addressOffset>
30824 <access>read-write
</access>
30825 <resetValue>0x0</resetValue>
30828 <name>DBG_TIM15_STOP
</name>
30829 <description>Debug Timer
15 stopped when Core is
30830 halted
</description>
30831 <bitOffset>2</bitOffset>
30832 <bitWidth>1</bitWidth>
30835 <name>DBG_TIM16_STOP
</name>
30836 <description>Debug Timer
16 stopped when Core is
30837 halted
</description>
30838 <bitOffset>3</bitOffset>
30839 <bitWidth>1</bitWidth>
30842 <name>DBG_TIM17_STO
</name>
30843 <description>Debug Timer
17 stopped when Core is
30844 halted
</description>
30845 <bitOffset>4</bitOffset>
30846 <bitWidth>1</bitWidth>
30849 <name>DBG_TIM19_STOP
</name>
30850 <description>Debug Timer
19 stopped when Core is
30851 halted
</description>
30852 <bitOffset>5</bitOffset>
30853 <bitWidth>1</bitWidth>
30861 <description>Advanced timer
</description>
30862 <groupName>TIMs
</groupName>
30863 <baseAddress>0x40012C00</baseAddress>
30865 <offset>0x0</offset>
30867 <usage>registers
</usage>
30870 <name>TIM1_CC
</name>
30871 <description>TIM1 capture compare interrupt
</description>
30877 <displayName>CR1
</displayName>
30878 <description>control register
1</description>
30879 <addressOffset>0x0</addressOffset>
30881 <access>read-write
</access>
30882 <resetValue>0x0000</resetValue>
30886 <description>Counter enable
</description>
30887 <bitOffset>0</bitOffset>
30888 <bitWidth>1</bitWidth>
30892 <description>Update disable
</description>
30893 <bitOffset>1</bitOffset>
30894 <bitWidth>1</bitWidth>
30898 <description>Update request source
</description>
30899 <bitOffset>2</bitOffset>
30900 <bitWidth>1</bitWidth>
30904 <description>One-pulse mode
</description>
30905 <bitOffset>3</bitOffset>
30906 <bitWidth>1</bitWidth>
30910 <description>Direction
</description>
30911 <bitOffset>4</bitOffset>
30912 <bitWidth>1</bitWidth>
30916 <description>Center-aligned mode
30917 selection
</description>
30918 <bitOffset>5</bitOffset>
30919 <bitWidth>2</bitWidth>
30923 <description>Auto-reload preload enable
</description>
30924 <bitOffset>7</bitOffset>
30925 <bitWidth>1</bitWidth>
30929 <description>Clock division
</description>
30930 <bitOffset>8</bitOffset>
30931 <bitWidth>2</bitWidth>
30934 <name>UIFREMAP
</name>
30935 <description>UIF status bit remapping
</description>
30936 <bitOffset>11</bitOffset>
30937 <bitWidth>1</bitWidth>
30943 <displayName>CR2
</displayName>
30944 <description>control register
2</description>
30945 <addressOffset>0x4</addressOffset>
30947 <access>read-write
</access>
30948 <resetValue>0x0000</resetValue>
30952 <description>Capture/compare preloaded
30953 control
</description>
30954 <bitOffset>0</bitOffset>
30955 <bitWidth>1</bitWidth>
30959 <description>Capture/compare control update
30960 selection
</description>
30961 <bitOffset>2</bitOffset>
30962 <bitWidth>1</bitWidth>
30966 <description>Capture/compare DMA
30967 selection
</description>
30968 <bitOffset>3</bitOffset>
30969 <bitWidth>1</bitWidth>
30973 <description>Master mode selection
</description>
30974 <bitOffset>4</bitOffset>
30975 <bitWidth>3</bitWidth>
30979 <description>TI1 selection
</description>
30980 <bitOffset>7</bitOffset>
30981 <bitWidth>1</bitWidth>
30985 <description>Output Idle state
1</description>
30986 <bitOffset>8</bitOffset>
30987 <bitWidth>1</bitWidth>
30991 <description>Output Idle state
1</description>
30992 <bitOffset>9</bitOffset>
30993 <bitWidth>1</bitWidth>
30997 <description>Output Idle state
2</description>
30998 <bitOffset>10</bitOffset>
30999 <bitWidth>1</bitWidth>
31003 <description>Output Idle state
2</description>
31004 <bitOffset>11</bitOffset>
31005 <bitWidth>1</bitWidth>
31009 <description>Output Idle state
3</description>
31010 <bitOffset>12</bitOffset>
31011 <bitWidth>1</bitWidth>
31015 <description>Output Idle state
3</description>
31016 <bitOffset>13</bitOffset>
31017 <bitWidth>1</bitWidth>
31021 <description>Output Idle state
4</description>
31022 <bitOffset>14</bitOffset>
31023 <bitWidth>1</bitWidth>
31027 <description>Output Idle state
5</description>
31028 <bitOffset>16</bitOffset>
31029 <bitWidth>1</bitWidth>
31033 <description>Output Idle state
6</description>
31034 <bitOffset>18</bitOffset>
31035 <bitWidth>1</bitWidth>
31039 <description>Master mode selection
2</description>
31040 <bitOffset>20</bitOffset>
31041 <bitWidth>4</bitWidth>
31047 <displayName>SMCR
</displayName>
31048 <description>slave mode control register
</description>
31049 <addressOffset>0x8</addressOffset>
31051 <access>read-write
</access>
31052 <resetValue>0x0000</resetValue>
31056 <description>Slave mode selection
</description>
31057 <bitOffset>0</bitOffset>
31058 <bitWidth>3</bitWidth>
31062 <description>OCREF clear selection
</description>
31063 <bitOffset>3</bitOffset>
31064 <bitWidth>1</bitWidth>
31068 <description>Trigger selection
</description>
31069 <bitOffset>4</bitOffset>
31070 <bitWidth>3</bitWidth>
31074 <description>Master/Slave mode
</description>
31075 <bitOffset>7</bitOffset>
31076 <bitWidth>1</bitWidth>
31080 <description>External trigger filter
</description>
31081 <bitOffset>8</bitOffset>
31082 <bitWidth>4</bitWidth>
31086 <description>External trigger prescaler
</description>
31087 <bitOffset>12</bitOffset>
31088 <bitWidth>2</bitWidth>
31092 <description>External clock enable
</description>
31093 <bitOffset>14</bitOffset>
31094 <bitWidth>1</bitWidth>
31098 <description>External trigger polarity
</description>
31099 <bitOffset>15</bitOffset>
31100 <bitWidth>1</bitWidth>
31104 <description>Slave mode selection bit
3</description>
31105 <bitOffset>16</bitOffset>
31106 <bitWidth>1</bitWidth>
31112 <displayName>DIER
</displayName>
31113 <description>DMA/Interrupt enable register
</description>
31114 <addressOffset>0xC</addressOffset>
31116 <access>read-write
</access>
31117 <resetValue>0x0000</resetValue>
31121 <description>Trigger DMA request enable
</description>
31122 <bitOffset>14</bitOffset>
31123 <bitWidth>1</bitWidth>
31127 <description>COM DMA request enable
</description>
31128 <bitOffset>13</bitOffset>
31129 <bitWidth>1</bitWidth>
31133 <description>Capture/Compare
4 DMA request
31134 enable
</description>
31135 <bitOffset>12</bitOffset>
31136 <bitWidth>1</bitWidth>
31140 <description>Capture/Compare
3 DMA request
31141 enable
</description>
31142 <bitOffset>11</bitOffset>
31143 <bitWidth>1</bitWidth>
31147 <description>Capture/Compare
2 DMA request
31148 enable
</description>
31149 <bitOffset>10</bitOffset>
31150 <bitWidth>1</bitWidth>
31154 <description>Capture/Compare
1 DMA request
31155 enable
</description>
31156 <bitOffset>9</bitOffset>
31157 <bitWidth>1</bitWidth>
31161 <description>Update DMA request enable
</description>
31162 <bitOffset>8</bitOffset>
31163 <bitWidth>1</bitWidth>
31167 <description>Break interrupt enable
</description>
31168 <bitOffset>7</bitOffset>
31169 <bitWidth>1</bitWidth>
31173 <description>Trigger interrupt enable
</description>
31174 <bitOffset>6</bitOffset>
31175 <bitWidth>1</bitWidth>
31179 <description>COM interrupt enable
</description>
31180 <bitOffset>5</bitOffset>
31181 <bitWidth>1</bitWidth>
31185 <description>Capture/Compare
4 interrupt
31186 enable
</description>
31187 <bitOffset>4</bitOffset>
31188 <bitWidth>1</bitWidth>
31192 <description>Capture/Compare
3 interrupt
31193 enable
</description>
31194 <bitOffset>3</bitOffset>
31195 <bitWidth>1</bitWidth>
31199 <description>Capture/Compare
2 interrupt
31200 enable
</description>
31201 <bitOffset>2</bitOffset>
31202 <bitWidth>1</bitWidth>
31206 <description>Capture/Compare
1 interrupt
31207 enable
</description>
31208 <bitOffset>1</bitOffset>
31209 <bitWidth>1</bitWidth>
31213 <description>Update interrupt enable
</description>
31214 <bitOffset>0</bitOffset>
31215 <bitWidth>1</bitWidth>
31221 <displayName>SR
</displayName>
31222 <description>status register
</description>
31223 <addressOffset>0x10</addressOffset>
31225 <access>read-write
</access>
31226 <resetValue>0x0000</resetValue>
31230 <description>Update interrupt flag
</description>
31231 <bitOffset>0</bitOffset>
31232 <bitWidth>1</bitWidth>
31236 <description>Capture/compare
1 interrupt
31238 <bitOffset>1</bitOffset>
31239 <bitWidth>1</bitWidth>
31243 <description>Capture/Compare
2 interrupt
31245 <bitOffset>2</bitOffset>
31246 <bitWidth>1</bitWidth>
31250 <description>Capture/Compare
3 interrupt
31252 <bitOffset>3</bitOffset>
31253 <bitWidth>1</bitWidth>
31257 <description>Capture/Compare
4 interrupt
31259 <bitOffset>4</bitOffset>
31260 <bitWidth>1</bitWidth>
31264 <description>COM interrupt flag
</description>
31265 <bitOffset>5</bitOffset>
31266 <bitWidth>1</bitWidth>
31270 <description>Trigger interrupt flag
</description>
31271 <bitOffset>6</bitOffset>
31272 <bitWidth>1</bitWidth>
31276 <description>Break interrupt flag
</description>
31277 <bitOffset>7</bitOffset>
31278 <bitWidth>1</bitWidth>
31282 <description>Break
2 interrupt flag
</description>
31283 <bitOffset>8</bitOffset>
31284 <bitWidth>1</bitWidth>
31288 <description>Capture/Compare
1 overcapture
31290 <bitOffset>9</bitOffset>
31291 <bitWidth>1</bitWidth>
31295 <description>Capture/compare
2 overcapture
31297 <bitOffset>10</bitOffset>
31298 <bitWidth>1</bitWidth>
31302 <description>Capture/Compare
3 overcapture
31304 <bitOffset>11</bitOffset>
31305 <bitWidth>1</bitWidth>
31309 <description>Capture/Compare
4 overcapture
31311 <bitOffset>12</bitOffset>
31312 <bitWidth>1</bitWidth>
31316 <description>Capture/Compare
5 interrupt
31318 <bitOffset>16</bitOffset>
31319 <bitWidth>1</bitWidth>
31323 <description>Capture/Compare
6 interrupt
31325 <bitOffset>17</bitOffset>
31326 <bitWidth>1</bitWidth>
31332 <displayName>EGR
</displayName>
31333 <description>event generation register
</description>
31334 <addressOffset>0x14</addressOffset>
31336 <access>write-only
</access>
31337 <resetValue>0x0000</resetValue>
31341 <description>Update generation
</description>
31342 <bitOffset>0</bitOffset>
31343 <bitWidth>1</bitWidth>
31347 <description>Capture/compare
1
31348 generation
</description>
31349 <bitOffset>1</bitOffset>
31350 <bitWidth>1</bitWidth>
31354 <description>Capture/compare
2
31355 generation
</description>
31356 <bitOffset>2</bitOffset>
31357 <bitWidth>1</bitWidth>
31361 <description>Capture/compare
3
31362 generation
</description>
31363 <bitOffset>3</bitOffset>
31364 <bitWidth>1</bitWidth>
31368 <description>Capture/compare
4
31369 generation
</description>
31370 <bitOffset>4</bitOffset>
31371 <bitWidth>1</bitWidth>
31375 <description>Capture/Compare control update
31376 generation
</description>
31377 <bitOffset>5</bitOffset>
31378 <bitWidth>1</bitWidth>
31382 <description>Trigger generation
</description>
31383 <bitOffset>6</bitOffset>
31384 <bitWidth>1</bitWidth>
31388 <description>Break generation
</description>
31389 <bitOffset>7</bitOffset>
31390 <bitWidth>1</bitWidth>
31394 <description>Break
2 generation
</description>
31395 <bitOffset>8</bitOffset>
31396 <bitWidth>1</bitWidth>
31401 <name>CCMR1_Output
</name>
31402 <displayName>CCMR1_Output
</displayName>
31403 <description>capture/compare mode register (output
31404 mode)
</description>
31405 <addressOffset>0x18</addressOffset>
31407 <access>read-write
</access>
31408 <resetValue>0x00000000</resetValue>
31412 <description>Output Compare
2 clear
31413 enable
</description>
31414 <bitOffset>15</bitOffset>
31415 <bitWidth>1</bitWidth>
31419 <description>Output Compare
2 mode
</description>
31420 <bitOffset>12</bitOffset>
31421 <bitWidth>3</bitWidth>
31425 <description>Output Compare
2 preload
31426 enable
</description>
31427 <bitOffset>11</bitOffset>
31428 <bitWidth>1</bitWidth>
31432 <description>Output Compare
2 fast
31433 enable
</description>
31434 <bitOffset>10</bitOffset>
31435 <bitWidth>1</bitWidth>
31439 <description>Capture/Compare
2
31440 selection
</description>
31441 <bitOffset>8</bitOffset>
31442 <bitWidth>2</bitWidth>
31446 <description>Output Compare
1 clear
31447 enable
</description>
31448 <bitOffset>7</bitOffset>
31449 <bitWidth>1</bitWidth>
31453 <description>Output Compare
1 mode
</description>
31454 <bitOffset>4</bitOffset>
31455 <bitWidth>3</bitWidth>
31459 <description>Output Compare
1 preload
31460 enable
</description>
31461 <bitOffset>3</bitOffset>
31462 <bitWidth>1</bitWidth>
31466 <description>Output Compare
1 fast
31467 enable
</description>
31468 <bitOffset>2</bitOffset>
31469 <bitWidth>1</bitWidth>
31473 <description>Capture/Compare
1
31474 selection
</description>
31475 <bitOffset>0</bitOffset>
31476 <bitWidth>2</bitWidth>
31479 <name>OC1M_3
</name>
31480 <description>Output Compare
1 mode bit
31482 <bitOffset>16</bitOffset>
31483 <bitWidth>1</bitWidth>
31486 <name>OC2M_3
</name>
31487 <description>Output Compare
2 mode bit
31489 <bitOffset>24</bitOffset>
31490 <bitWidth>1</bitWidth>
31495 <name>CCMR1_Input
</name>
31496 <displayName>CCMR1_Input
</displayName>
31497 <description>capture/compare mode register
1 (input
31498 mode)
</description>
31499 <alternateRegister>CCMR1_Output
</alternateRegister>
31500 <addressOffset>0x18</addressOffset>
31502 <access>read-write
</access>
31503 <resetValue>0x00000000</resetValue>
31507 <description>Input capture
2 filter
</description>
31508 <bitOffset>12</bitOffset>
31509 <bitWidth>4</bitWidth>
31512 <name>IC2PCS
</name>
31513 <description>Input capture
2 prescaler
</description>
31514 <bitOffset>10</bitOffset>
31515 <bitWidth>2</bitWidth>
31519 <description>Capture/Compare
2
31520 selection
</description>
31521 <bitOffset>8</bitOffset>
31522 <bitWidth>2</bitWidth>
31526 <description>Input capture
1 filter
</description>
31527 <bitOffset>4</bitOffset>
31528 <bitWidth>4</bitWidth>
31531 <name>IC1PCS
</name>
31532 <description>Input capture
1 prescaler
</description>
31533 <bitOffset>2</bitOffset>
31534 <bitWidth>2</bitWidth>
31538 <description>Capture/Compare
1
31539 selection
</description>
31540 <bitOffset>0</bitOffset>
31541 <bitWidth>2</bitWidth>
31546 <name>CCMR2_Output
</name>
31547 <displayName>CCMR2_Output
</displayName>
31548 <description>capture/compare mode register (output
31549 mode)
</description>
31550 <addressOffset>0x1C</addressOffset>
31552 <access>read-write
</access>
31553 <resetValue>0x00000000</resetValue>
31557 <description>Output compare
4 clear
31558 enable
</description>
31559 <bitOffset>15</bitOffset>
31560 <bitWidth>1</bitWidth>
31564 <description>Output compare
4 mode
</description>
31565 <bitOffset>12</bitOffset>
31566 <bitWidth>3</bitWidth>
31570 <description>Output compare
4 preload
31571 enable
</description>
31572 <bitOffset>11</bitOffset>
31573 <bitWidth>1</bitWidth>
31577 <description>Output compare
4 fast
31578 enable
</description>
31579 <bitOffset>10</bitOffset>
31580 <bitWidth>1</bitWidth>
31584 <description>Capture/Compare
4
31585 selection
</description>
31586 <bitOffset>8</bitOffset>
31587 <bitWidth>2</bitWidth>
31591 <description>Output compare
3 clear
31592 enable
</description>
31593 <bitOffset>7</bitOffset>
31594 <bitWidth>1</bitWidth>
31598 <description>Output compare
3 mode
</description>
31599 <bitOffset>4</bitOffset>
31600 <bitWidth>3</bitWidth>
31604 <description>Output compare
3 preload
31605 enable
</description>
31606 <bitOffset>3</bitOffset>
31607 <bitWidth>1</bitWidth>
31611 <description>Output compare
3 fast
31612 enable
</description>
31613 <bitOffset>2</bitOffset>
31614 <bitWidth>1</bitWidth>
31618 <description>Capture/Compare
3
31619 selection
</description>
31620 <bitOffset>0</bitOffset>
31621 <bitWidth>2</bitWidth>
31624 <name>OC3M_3
</name>
31625 <description>Output Compare
3 mode bit
31627 <bitOffset>16</bitOffset>
31628 <bitWidth>1</bitWidth>
31631 <name>OC4M_3
</name>
31632 <description>Output Compare
4 mode bit
31634 <bitOffset>24</bitOffset>
31635 <bitWidth>1</bitWidth>
31640 <name>CCMR2_Input
</name>
31641 <displayName>CCMR2_Input
</displayName>
31642 <description>capture/compare mode register
2 (input
31643 mode)
</description>
31644 <alternateRegister>CCMR2_Output
</alternateRegister>
31645 <addressOffset>0x1C</addressOffset>
31647 <access>read-write
</access>
31648 <resetValue>0x00000000</resetValue>
31652 <description>Input capture
4 filter
</description>
31653 <bitOffset>12</bitOffset>
31654 <bitWidth>4</bitWidth>
31657 <name>IC4PSC
</name>
31658 <description>Input capture
4 prescaler
</description>
31659 <bitOffset>10</bitOffset>
31660 <bitWidth>2</bitWidth>
31664 <description>Capture/Compare
4
31665 selection
</description>
31666 <bitOffset>8</bitOffset>
31667 <bitWidth>2</bitWidth>
31671 <description>Input capture
3 filter
</description>
31672 <bitOffset>4</bitOffset>
31673 <bitWidth>4</bitWidth>
31676 <name>IC3PSC
</name>
31677 <description>Input capture
3 prescaler
</description>
31678 <bitOffset>2</bitOffset>
31679 <bitWidth>2</bitWidth>
31683 <description>Capture/compare
3
31684 selection
</description>
31685 <bitOffset>0</bitOffset>
31686 <bitWidth>2</bitWidth>
31692 <displayName>CCER
</displayName>
31693 <description>capture/compare enable
31694 register
</description>
31695 <addressOffset>0x20</addressOffset>
31697 <access>read-write
</access>
31698 <resetValue>0x0000</resetValue>
31702 <description>Capture/Compare
1 output
31703 enable
</description>
31704 <bitOffset>0</bitOffset>
31705 <bitWidth>1</bitWidth>
31709 <description>Capture/Compare
1 output
31710 Polarity
</description>
31711 <bitOffset>1</bitOffset>
31712 <bitWidth>1</bitWidth>
31716 <description>Capture/Compare
1 complementary output
31717 enable
</description>
31718 <bitOffset>2</bitOffset>
31719 <bitWidth>1</bitWidth>
31723 <description>Capture/Compare
1 output
31724 Polarity
</description>
31725 <bitOffset>3</bitOffset>
31726 <bitWidth>1</bitWidth>
31730 <description>Capture/Compare
2 output
31731 enable
</description>
31732 <bitOffset>4</bitOffset>
31733 <bitWidth>1</bitWidth>
31737 <description>Capture/Compare
2 output
31738 Polarity
</description>
31739 <bitOffset>5</bitOffset>
31740 <bitWidth>1</bitWidth>
31744 <description>Capture/Compare
2 complementary output
31745 enable
</description>
31746 <bitOffset>6</bitOffset>
31747 <bitWidth>1</bitWidth>
31751 <description>Capture/Compare
2 output
31752 Polarity
</description>
31753 <bitOffset>7</bitOffset>
31754 <bitWidth>1</bitWidth>
31758 <description>Capture/Compare
3 output
31759 enable
</description>
31760 <bitOffset>8</bitOffset>
31761 <bitWidth>1</bitWidth>
31765 <description>Capture/Compare
3 output
31766 Polarity
</description>
31767 <bitOffset>9</bitOffset>
31768 <bitWidth>1</bitWidth>
31772 <description>Capture/Compare
3 complementary output
31773 enable
</description>
31774 <bitOffset>10</bitOffset>
31775 <bitWidth>1</bitWidth>
31779 <description>Capture/Compare
3 output
31780 Polarity
</description>
31781 <bitOffset>11</bitOffset>
31782 <bitWidth>1</bitWidth>
31786 <description>Capture/Compare
4 output
31787 enable
</description>
31788 <bitOffset>12</bitOffset>
31789 <bitWidth>1</bitWidth>
31793 <description>Capture/Compare
3 output
31794 Polarity
</description>
31795 <bitOffset>13</bitOffset>
31796 <bitWidth>1</bitWidth>
31800 <description>Capture/Compare
4 output
31801 Polarity
</description>
31802 <bitOffset>15</bitOffset>
31803 <bitWidth>1</bitWidth>
31807 <description>Capture/Compare
5 output
31808 enable
</description>
31809 <bitOffset>16</bitOffset>
31810 <bitWidth>1</bitWidth>
31814 <description>Capture/Compare
5 output
31815 Polarity
</description>
31816 <bitOffset>17</bitOffset>
31817 <bitWidth>1</bitWidth>
31821 <description>Capture/Compare
6 output
31822 enable
</description>
31823 <bitOffset>20</bitOffset>
31824 <bitWidth>1</bitWidth>
31828 <description>Capture/Compare
6 output
31829 Polarity
</description>
31830 <bitOffset>21</bitOffset>
31831 <bitWidth>1</bitWidth>
31837 <displayName>CNT
</displayName>
31838 <description>counter
</description>
31839 <addressOffset>0x24</addressOffset>
31841 <resetValue>0x00000000</resetValue>
31845 <description>counter value
</description>
31846 <bitOffset>0</bitOffset>
31847 <bitWidth>16</bitWidth>
31848 <access>read-write
</access>
31851 <name>UIFCPY
</name>
31852 <description>UIF copy
</description>
31853 <bitOffset>31</bitOffset>
31854 <bitWidth>1</bitWidth>
31855 <access>read-only
</access>
31861 <displayName>PSC
</displayName>
31862 <description>prescaler
</description>
31863 <addressOffset>0x28</addressOffset>
31865 <access>read-write
</access>
31866 <resetValue>0x0000</resetValue>
31870 <description>Prescaler value
</description>
31871 <bitOffset>0</bitOffset>
31872 <bitWidth>16</bitWidth>
31878 <displayName>ARR
</displayName>
31879 <description>auto-reload register
</description>
31880 <addressOffset>0x2C</addressOffset>
31882 <access>read-write
</access>
31883 <resetValue>0x00000000</resetValue>
31887 <description>Auto-reload value
</description>
31888 <bitOffset>0</bitOffset>
31889 <bitWidth>16</bitWidth>
31895 <displayName>RCR
</displayName>
31896 <description>repetition counter register
</description>
31897 <addressOffset>0x30</addressOffset>
31899 <access>read-write
</access>
31900 <resetValue>0x0000</resetValue>
31904 <description>Repetition counter value
</description>
31905 <bitOffset>0</bitOffset>
31906 <bitWidth>16</bitWidth>
31912 <displayName>CCR1
</displayName>
31913 <description>capture/compare register
1</description>
31914 <addressOffset>0x34</addressOffset>
31916 <access>read-write
</access>
31917 <resetValue>0x00000000</resetValue>
31921 <description>Capture/Compare
1 value
</description>
31922 <bitOffset>0</bitOffset>
31923 <bitWidth>16</bitWidth>
31929 <displayName>CCR2
</displayName>
31930 <description>capture/compare register
2</description>
31931 <addressOffset>0x38</addressOffset>
31933 <access>read-write
</access>
31934 <resetValue>0x00000000</resetValue>
31938 <description>Capture/Compare
2 value
</description>
31939 <bitOffset>0</bitOffset>
31940 <bitWidth>16</bitWidth>
31946 <displayName>CCR3
</displayName>
31947 <description>capture/compare register
3</description>
31948 <addressOffset>0x3C</addressOffset>
31950 <access>read-write
</access>
31951 <resetValue>0x00000000</resetValue>
31955 <description>Capture/Compare
3 value
</description>
31956 <bitOffset>0</bitOffset>
31957 <bitWidth>16</bitWidth>
31963 <displayName>CCR4
</displayName>
31964 <description>capture/compare register
4</description>
31965 <addressOffset>0x40</addressOffset>
31967 <access>read-write
</access>
31968 <resetValue>0x00000000</resetValue>
31972 <description>Capture/Compare
3 value
</description>
31973 <bitOffset>0</bitOffset>
31974 <bitWidth>16</bitWidth>
31980 <displayName>BDTR
</displayName>
31981 <description>break and dead-time register
</description>
31982 <addressOffset>0x44</addressOffset>
31984 <access>read-write
</access>
31985 <resetValue>0x00000000</resetValue>
31989 <description>Dead-time generator setup
</description>
31990 <bitOffset>0</bitOffset>
31991 <bitWidth>8</bitWidth>
31995 <description>Lock configuration
</description>
31996 <bitOffset>8</bitOffset>
31997 <bitWidth>2</bitWidth>
32001 <description>Off-state selection for Idle
32003 <bitOffset>10</bitOffset>
32004 <bitWidth>1</bitWidth>
32008 <description>Off-state selection for Run
32010 <bitOffset>11</bitOffset>
32011 <bitWidth>1</bitWidth>
32015 <description>Break enable
</description>
32016 <bitOffset>12</bitOffset>
32017 <bitWidth>1</bitWidth>
32021 <description>Break polarity
</description>
32022 <bitOffset>13</bitOffset>
32023 <bitWidth>1</bitWidth>
32027 <description>Automatic output enable
</description>
32028 <bitOffset>14</bitOffset>
32029 <bitWidth>1</bitWidth>
32033 <description>Main output enable
</description>
32034 <bitOffset>15</bitOffset>
32035 <bitWidth>1</bitWidth>
32039 <description>Break filter
</description>
32040 <bitOffset>16</bitOffset>
32041 <bitWidth>4</bitWidth>
32045 <description>Break
2 filter
</description>
32046 <bitOffset>20</bitOffset>
32047 <bitWidth>4</bitWidth>
32051 <description>Break
2 enable
</description>
32052 <bitOffset>24</bitOffset>
32053 <bitWidth>1</bitWidth>
32057 <description>Break
2 polarity
</description>
32058 <bitOffset>25</bitOffset>
32059 <bitWidth>1</bitWidth>
32065 <displayName>DCR
</displayName>
32066 <description>DMA control register
</description>
32067 <addressOffset>0x48</addressOffset>
32069 <access>read-write
</access>
32070 <resetValue>0x00000000</resetValue>
32074 <description>DMA burst length
</description>
32075 <bitOffset>8</bitOffset>
32076 <bitWidth>5</bitWidth>
32080 <description>DMA base address
</description>
32081 <bitOffset>0</bitOffset>
32082 <bitWidth>5</bitWidth>
32088 <displayName>DMAR
</displayName>
32089 <description>DMA address for full transfer
</description>
32090 <addressOffset>0x4C</addressOffset>
32092 <access>read-write
</access>
32093 <resetValue>0x00000000</resetValue>
32097 <description>DMA register for burst
32098 accesses
</description>
32099 <bitOffset>0</bitOffset>
32100 <bitWidth>16</bitWidth>
32105 <name>CCMR3_Output
</name>
32106 <displayName>CCMR3_Output
</displayName>
32107 <description>capture/compare mode register
3 (output
32108 mode)
</description>
32109 <addressOffset>0x54</addressOffset>
32111 <access>read-write
</access>
32112 <resetValue>0x00000000</resetValue>
32116 <description>Output compare
5 fast
32117 enable
</description>
32118 <bitOffset>2</bitOffset>
32119 <bitWidth>1</bitWidth>
32123 <description>Output compare
5 preload
32124 enable
</description>
32125 <bitOffset>3</bitOffset>
32126 <bitWidth>1</bitWidth>
32130 <description>Output compare
5 mode
</description>
32131 <bitOffset>4</bitOffset>
32132 <bitWidth>3</bitWidth>
32136 <description>Output compare
5 clear
32137 enable
</description>
32138 <bitOffset>7</bitOffset>
32139 <bitWidth>1</bitWidth>
32143 <description>Output compare
6 fast
32144 enable
</description>
32145 <bitOffset>10</bitOffset>
32146 <bitWidth>1</bitWidth>
32150 <description>Output compare
6 preload
32151 enable
</description>
32152 <bitOffset>11</bitOffset>
32153 <bitWidth>1</bitWidth>
32157 <description>Output compare
6 mode
</description>
32158 <bitOffset>12</bitOffset>
32159 <bitWidth>3</bitWidth>
32163 <description>Output compare
6 clear
32164 enable
</description>
32165 <bitOffset>15</bitOffset>
32166 <bitWidth>1</bitWidth>
32169 <name>OC5M_3
</name>
32170 <description>Outout Compare
5 mode bit
32172 <bitOffset>16</bitOffset>
32173 <bitWidth>1</bitWidth>
32176 <name>OC6M_3
</name>
32177 <description>Outout Compare
6 mode bit
32179 <bitOffset>24</bitOffset>
32180 <bitWidth>1</bitWidth>
32186 <displayName>CCR5
</displayName>
32187 <description>capture/compare register
5</description>
32188 <addressOffset>0x58</addressOffset>
32190 <access>read-write
</access>
32191 <resetValue>0x00000000</resetValue>
32195 <description>Capture/Compare
5 value
</description>
32196 <bitOffset>0</bitOffset>
32197 <bitWidth>16</bitWidth>
32201 <description>Group Channel
5 and Channel
32203 <bitOffset>29</bitOffset>
32204 <bitWidth>1</bitWidth>
32208 <description>Group Channel
5 and Channel
32210 <bitOffset>30</bitOffset>
32211 <bitWidth>1</bitWidth>
32215 <description>Group Channel
5 and Channel
32217 <bitOffset>31</bitOffset>
32218 <bitWidth>1</bitWidth>
32224 <displayName>CCR6
</displayName>
32225 <description>capture/compare register
6</description>
32226 <addressOffset>0x5C</addressOffset>
32228 <access>read-write
</access>
32229 <resetValue>0x00000000</resetValue>
32233 <description>Capture/Compare
6 value
</description>
32234 <bitOffset>0</bitOffset>
32235 <bitWidth>16</bitWidth>
32241 <displayName>OR
</displayName>
32242 <description>option registers
</description>
32243 <addressOffset>0x60</addressOffset>
32245 <access>read-write
</access>
32246 <resetValue>0x00000000</resetValue>
32249 <name>TIM1_ETR_ADC1_RMP
</name>
32250 <description>TIM1_ETR_ADC1 remapping
32251 capability
</description>
32252 <bitOffset>0</bitOffset>
32253 <bitWidth>2</bitWidth>
32256 <name>TIM1_ETR_ADC4_RMP
</name>
32257 <description>TIM1_ETR_ADC4 remapping
32258 capability
</description>
32259 <bitOffset>2</bitOffset>
32260 <bitWidth>2</bitWidth>
32266 <peripheral derivedFrom=
"TIM1">
32268 <baseAddress>0x40015000</baseAddress>
32270 <name>TIM1_CC
</name>
32271 <description>TIM1 capture compare interrupt
</description>
32275 <name>TIM20_BRK
</name>
32276 <description>TIM20 Break interrupt
</description>
32280 <name>TIM20_UP
</name>
32281 <description>TIM20 Upgrade interrupt
</description>
32285 <name>TIM20_TRG_COM
</name>
32286 <description>TIM20 Trigger and Commutation
32287 interrupt
</description>
32291 <name>TIM20_CC
</name>
32292 <description>TIM20 Capture Compare interrupt
</description>
32298 <description>Advanced-timers
</description>
32299 <groupName>TIMs
</groupName>
32300 <baseAddress>0x40013400</baseAddress>
32302 <offset>0x0</offset>
32304 <usage>registers
</usage>
32307 <name>TIM8_BRK
</name>
32308 <description>TIM8 break interrupt
</description>
32312 <name>TIM8_UP
</name>
32313 <description>TIM8 update interrupt
</description>
32317 <name>TIM8_TRG_COM
</name>
32318 <description>TIM8 Trigger and commutation
32319 interrupts
</description>
32323 <name>TIM8_CC
</name>
32324 <description>TIM8 capture compare interrupt
</description>
32330 <displayName>CR1
</displayName>
32331 <description>control register
1</description>
32332 <addressOffset>0x0</addressOffset>
32334 <access>read-write
</access>
32335 <resetValue>0x0000</resetValue>
32339 <description>Counter enable
</description>
32340 <bitOffset>0</bitOffset>
32341 <bitWidth>1</bitWidth>
32345 <description>Update disable
</description>
32346 <bitOffset>1</bitOffset>
32347 <bitWidth>1</bitWidth>
32351 <description>Update request source
</description>
32352 <bitOffset>2</bitOffset>
32353 <bitWidth>1</bitWidth>
32357 <description>One-pulse mode
</description>
32358 <bitOffset>3</bitOffset>
32359 <bitWidth>1</bitWidth>
32363 <description>Direction
</description>
32364 <bitOffset>4</bitOffset>
32365 <bitWidth>1</bitWidth>
32369 <description>Center-aligned mode
32370 selection
</description>
32371 <bitOffset>5</bitOffset>
32372 <bitWidth>2</bitWidth>
32376 <description>Auto-reload preload enable
</description>
32377 <bitOffset>7</bitOffset>
32378 <bitWidth>1</bitWidth>
32382 <description>Clock division
</description>
32383 <bitOffset>8</bitOffset>
32384 <bitWidth>2</bitWidth>
32387 <name>UIFREMAP
</name>
32388 <description>UIF status bit remapping
</description>
32389 <bitOffset>11</bitOffset>
32390 <bitWidth>1</bitWidth>
32396 <displayName>CR2
</displayName>
32397 <description>control register
2</description>
32398 <addressOffset>0x4</addressOffset>
32400 <access>read-write
</access>
32401 <resetValue>0x0000</resetValue>
32405 <description>Capture/compare preloaded
32406 control
</description>
32407 <bitOffset>0</bitOffset>
32408 <bitWidth>1</bitWidth>
32412 <description>Capture/compare control update
32413 selection
</description>
32414 <bitOffset>2</bitOffset>
32415 <bitWidth>1</bitWidth>
32419 <description>Capture/compare DMA
32420 selection
</description>
32421 <bitOffset>3</bitOffset>
32422 <bitWidth>1</bitWidth>
32426 <description>Master mode selection
</description>
32427 <bitOffset>4</bitOffset>
32428 <bitWidth>3</bitWidth>
32432 <description>TI1 selection
</description>
32433 <bitOffset>7</bitOffset>
32434 <bitWidth>1</bitWidth>
32438 <description>Output Idle state
1</description>
32439 <bitOffset>8</bitOffset>
32440 <bitWidth>1</bitWidth>
32444 <description>Output Idle state
1</description>
32445 <bitOffset>9</bitOffset>
32446 <bitWidth>1</bitWidth>
32450 <description>Output Idle state
2</description>
32451 <bitOffset>10</bitOffset>
32452 <bitWidth>1</bitWidth>
32456 <description>Output Idle state
2</description>
32457 <bitOffset>11</bitOffset>
32458 <bitWidth>1</bitWidth>
32462 <description>Output Idle state
3</description>
32463 <bitOffset>12</bitOffset>
32464 <bitWidth>1</bitWidth>
32468 <description>Output Idle state
3</description>
32469 <bitOffset>13</bitOffset>
32470 <bitWidth>1</bitWidth>
32474 <description>Output Idle state
4</description>
32475 <bitOffset>14</bitOffset>
32476 <bitWidth>1</bitWidth>
32480 <description>Output Idle state
5</description>
32481 <bitOffset>16</bitOffset>
32482 <bitWidth>1</bitWidth>
32486 <description>Output Idle state
6</description>
32487 <bitOffset>18</bitOffset>
32488 <bitWidth>1</bitWidth>
32492 <description>Master mode selection
2</description>
32493 <bitOffset>20</bitOffset>
32494 <bitWidth>4</bitWidth>
32500 <displayName>SMCR
</displayName>
32501 <description>slave mode control register
</description>
32502 <addressOffset>0x8</addressOffset>
32504 <access>read-write
</access>
32505 <resetValue>0x0000</resetValue>
32509 <description>Slave mode selection
</description>
32510 <bitOffset>0</bitOffset>
32511 <bitWidth>3</bitWidth>
32515 <description>OCREF clear selection
</description>
32516 <bitOffset>3</bitOffset>
32517 <bitWidth>1</bitWidth>
32521 <description>Trigger selection
</description>
32522 <bitOffset>4</bitOffset>
32523 <bitWidth>3</bitWidth>
32527 <description>Master/Slave mode
</description>
32528 <bitOffset>7</bitOffset>
32529 <bitWidth>1</bitWidth>
32533 <description>External trigger filter
</description>
32534 <bitOffset>8</bitOffset>
32535 <bitWidth>4</bitWidth>
32539 <description>External trigger prescaler
</description>
32540 <bitOffset>12</bitOffset>
32541 <bitWidth>2</bitWidth>
32545 <description>External clock enable
</description>
32546 <bitOffset>14</bitOffset>
32547 <bitWidth>1</bitWidth>
32551 <description>External trigger polarity
</description>
32552 <bitOffset>15</bitOffset>
32553 <bitWidth>1</bitWidth>
32557 <description>Slave mode selection bit
3</description>
32558 <bitOffset>16</bitOffset>
32559 <bitWidth>1</bitWidth>
32565 <displayName>DIER
</displayName>
32566 <description>DMA/Interrupt enable register
</description>
32567 <addressOffset>0xC</addressOffset>
32569 <access>read-write
</access>
32570 <resetValue>0x0000</resetValue>
32574 <description>Trigger DMA request enable
</description>
32575 <bitOffset>14</bitOffset>
32576 <bitWidth>1</bitWidth>
32580 <description>COM DMA request enable
</description>
32581 <bitOffset>13</bitOffset>
32582 <bitWidth>1</bitWidth>
32586 <description>Capture/Compare
4 DMA request
32587 enable
</description>
32588 <bitOffset>12</bitOffset>
32589 <bitWidth>1</bitWidth>
32593 <description>Capture/Compare
3 DMA request
32594 enable
</description>
32595 <bitOffset>11</bitOffset>
32596 <bitWidth>1</bitWidth>
32600 <description>Capture/Compare
2 DMA request
32601 enable
</description>
32602 <bitOffset>10</bitOffset>
32603 <bitWidth>1</bitWidth>
32607 <description>Capture/Compare
1 DMA request
32608 enable
</description>
32609 <bitOffset>9</bitOffset>
32610 <bitWidth>1</bitWidth>
32614 <description>Update DMA request enable
</description>
32615 <bitOffset>8</bitOffset>
32616 <bitWidth>1</bitWidth>
32620 <description>Break interrupt enable
</description>
32621 <bitOffset>7</bitOffset>
32622 <bitWidth>1</bitWidth>
32626 <description>Trigger interrupt enable
</description>
32627 <bitOffset>6</bitOffset>
32628 <bitWidth>1</bitWidth>
32632 <description>COM interrupt enable
</description>
32633 <bitOffset>5</bitOffset>
32634 <bitWidth>1</bitWidth>
32638 <description>Capture/Compare
4 interrupt
32639 enable
</description>
32640 <bitOffset>4</bitOffset>
32641 <bitWidth>1</bitWidth>
32645 <description>Capture/Compare
3 interrupt
32646 enable
</description>
32647 <bitOffset>3</bitOffset>
32648 <bitWidth>1</bitWidth>
32652 <description>Capture/Compare
2 interrupt
32653 enable
</description>
32654 <bitOffset>2</bitOffset>
32655 <bitWidth>1</bitWidth>
32659 <description>Capture/Compare
1 interrupt
32660 enable
</description>
32661 <bitOffset>1</bitOffset>
32662 <bitWidth>1</bitWidth>
32666 <description>Update interrupt enable
</description>
32667 <bitOffset>0</bitOffset>
32668 <bitWidth>1</bitWidth>
32674 <displayName>SR
</displayName>
32675 <description>status register
</description>
32676 <addressOffset>0x10</addressOffset>
32678 <access>read-write
</access>
32679 <resetValue>0x0000</resetValue>
32683 <description>Update interrupt flag
</description>
32684 <bitOffset>0</bitOffset>
32685 <bitWidth>1</bitWidth>
32689 <description>Capture/compare
1 interrupt
32691 <bitOffset>1</bitOffset>
32692 <bitWidth>1</bitWidth>
32696 <description>Capture/Compare
2 interrupt
32698 <bitOffset>2</bitOffset>
32699 <bitWidth>1</bitWidth>
32703 <description>Capture/Compare
3 interrupt
32705 <bitOffset>3</bitOffset>
32706 <bitWidth>1</bitWidth>
32710 <description>Capture/Compare
4 interrupt
32712 <bitOffset>4</bitOffset>
32713 <bitWidth>1</bitWidth>
32717 <description>COM interrupt flag
</description>
32718 <bitOffset>5</bitOffset>
32719 <bitWidth>1</bitWidth>
32723 <description>Trigger interrupt flag
</description>
32724 <bitOffset>6</bitOffset>
32725 <bitWidth>1</bitWidth>
32729 <description>Break interrupt flag
</description>
32730 <bitOffset>7</bitOffset>
32731 <bitWidth>1</bitWidth>
32735 <description>Break
2 interrupt flag
</description>
32736 <bitOffset>8</bitOffset>
32737 <bitWidth>1</bitWidth>
32741 <description>Capture/Compare
1 overcapture
32743 <bitOffset>9</bitOffset>
32744 <bitWidth>1</bitWidth>
32748 <description>Capture/compare
2 overcapture
32750 <bitOffset>10</bitOffset>
32751 <bitWidth>1</bitWidth>
32755 <description>Capture/Compare
3 overcapture
32757 <bitOffset>11</bitOffset>
32758 <bitWidth>1</bitWidth>
32762 <description>Capture/Compare
4 overcapture
32764 <bitOffset>12</bitOffset>
32765 <bitWidth>1</bitWidth>
32769 <description>Capture/Compare
5 interrupt
32771 <bitOffset>16</bitOffset>
32772 <bitWidth>1</bitWidth>
32776 <description>Capture/Compare
6 interrupt
32778 <bitOffset>17</bitOffset>
32779 <bitWidth>1</bitWidth>
32785 <displayName>EGR
</displayName>
32786 <description>event generation register
</description>
32787 <addressOffset>0x14</addressOffset>
32789 <access>write-only
</access>
32790 <resetValue>0x0000</resetValue>
32794 <description>Update generation
</description>
32795 <bitOffset>0</bitOffset>
32796 <bitWidth>1</bitWidth>
32800 <description>Capture/compare
1
32801 generation
</description>
32802 <bitOffset>1</bitOffset>
32803 <bitWidth>1</bitWidth>
32807 <description>Capture/compare
2
32808 generation
</description>
32809 <bitOffset>2</bitOffset>
32810 <bitWidth>1</bitWidth>
32814 <description>Capture/compare
3
32815 generation
</description>
32816 <bitOffset>3</bitOffset>
32817 <bitWidth>1</bitWidth>
32821 <description>Capture/compare
4
32822 generation
</description>
32823 <bitOffset>4</bitOffset>
32824 <bitWidth>1</bitWidth>
32828 <description>Capture/Compare control update
32829 generation
</description>
32830 <bitOffset>5</bitOffset>
32831 <bitWidth>1</bitWidth>
32835 <description>Trigger generation
</description>
32836 <bitOffset>6</bitOffset>
32837 <bitWidth>1</bitWidth>
32841 <description>Break generation
</description>
32842 <bitOffset>7</bitOffset>
32843 <bitWidth>1</bitWidth>
32847 <description>Break
2 generation
</description>
32848 <bitOffset>8</bitOffset>
32849 <bitWidth>1</bitWidth>
32854 <name>CCMR1_Output
</name>
32855 <displayName>CCMR1_Output
</displayName>
32856 <description>capture/compare mode register (output
32857 mode)
</description>
32858 <addressOffset>0x18</addressOffset>
32860 <access>read-write
</access>
32861 <resetValue>0x00000000</resetValue>
32865 <description>Output Compare
2 clear
32866 enable
</description>
32867 <bitOffset>15</bitOffset>
32868 <bitWidth>1</bitWidth>
32872 <description>Output Compare
2 mode
</description>
32873 <bitOffset>12</bitOffset>
32874 <bitWidth>3</bitWidth>
32878 <description>Output Compare
2 preload
32879 enable
</description>
32880 <bitOffset>11</bitOffset>
32881 <bitWidth>1</bitWidth>
32885 <description>Output Compare
2 fast
32886 enable
</description>
32887 <bitOffset>10</bitOffset>
32888 <bitWidth>1</bitWidth>
32892 <description>Capture/Compare
2
32893 selection
</description>
32894 <bitOffset>8</bitOffset>
32895 <bitWidth>2</bitWidth>
32899 <description>Output Compare
1 clear
32900 enable
</description>
32901 <bitOffset>7</bitOffset>
32902 <bitWidth>1</bitWidth>
32906 <description>Output Compare
1 mode
</description>
32907 <bitOffset>4</bitOffset>
32908 <bitWidth>3</bitWidth>
32912 <description>Output Compare
1 preload
32913 enable
</description>
32914 <bitOffset>3</bitOffset>
32915 <bitWidth>1</bitWidth>
32919 <description>Output Compare
1 fast
32920 enable
</description>
32921 <bitOffset>2</bitOffset>
32922 <bitWidth>1</bitWidth>
32926 <description>Capture/Compare
1
32927 selection
</description>
32928 <bitOffset>0</bitOffset>
32929 <bitWidth>2</bitWidth>
32932 <name>OC1M_3
</name>
32933 <description>Output Compare
1 mode bit
32935 <bitOffset>16</bitOffset>
32936 <bitWidth>1</bitWidth>
32939 <name>OC2M_3
</name>
32940 <description>Output Compare
2 mode bit
32942 <bitOffset>24</bitOffset>
32943 <bitWidth>1</bitWidth>
32948 <name>CCMR1_Input
</name>
32949 <displayName>CCMR1_Input
</displayName>
32950 <description>capture/compare mode register
1 (input
32951 mode)
</description>
32952 <alternateRegister>CCMR1_Output
</alternateRegister>
32953 <addressOffset>0x18</addressOffset>
32955 <access>read-write
</access>
32956 <resetValue>0x00000000</resetValue>
32960 <description>Input capture
2 filter
</description>
32961 <bitOffset>12</bitOffset>
32962 <bitWidth>4</bitWidth>
32965 <name>IC2PCS
</name>
32966 <description>Input capture
2 prescaler
</description>
32967 <bitOffset>10</bitOffset>
32968 <bitWidth>2</bitWidth>
32972 <description>Capture/Compare
2
32973 selection
</description>
32974 <bitOffset>8</bitOffset>
32975 <bitWidth>2</bitWidth>
32979 <description>Input capture
1 filter
</description>
32980 <bitOffset>4</bitOffset>
32981 <bitWidth>4</bitWidth>
32984 <name>IC1PCS
</name>
32985 <description>Input capture
1 prescaler
</description>
32986 <bitOffset>2</bitOffset>
32987 <bitWidth>2</bitWidth>
32991 <description>Capture/Compare
1
32992 selection
</description>
32993 <bitOffset>0</bitOffset>
32994 <bitWidth>2</bitWidth>
32999 <name>CCMR2_Output
</name>
33000 <displayName>CCMR2_Output
</displayName>
33001 <description>capture/compare mode register (output
33002 mode)
</description>
33003 <addressOffset>0x1C</addressOffset>
33005 <access>read-write
</access>
33006 <resetValue>0x00000000</resetValue>
33010 <description>Output compare
4 clear
33011 enable
</description>
33012 <bitOffset>15</bitOffset>
33013 <bitWidth>1</bitWidth>
33017 <description>Output compare
4 mode
</description>
33018 <bitOffset>12</bitOffset>
33019 <bitWidth>3</bitWidth>
33023 <description>Output compare
4 preload
33024 enable
</description>
33025 <bitOffset>11</bitOffset>
33026 <bitWidth>1</bitWidth>
33030 <description>Output compare
4 fast
33031 enable
</description>
33032 <bitOffset>10</bitOffset>
33033 <bitWidth>1</bitWidth>
33037 <description>Capture/Compare
4
33038 selection
</description>
33039 <bitOffset>8</bitOffset>
33040 <bitWidth>2</bitWidth>
33044 <description>Output compare
3 clear
33045 enable
</description>
33046 <bitOffset>7</bitOffset>
33047 <bitWidth>1</bitWidth>
33051 <description>Output compare
3 mode
</description>
33052 <bitOffset>4</bitOffset>
33053 <bitWidth>3</bitWidth>
33057 <description>Output compare
3 preload
33058 enable
</description>
33059 <bitOffset>3</bitOffset>
33060 <bitWidth>1</bitWidth>
33064 <description>Output compare
3 fast
33065 enable
</description>
33066 <bitOffset>2</bitOffset>
33067 <bitWidth>1</bitWidth>
33071 <description>Capture/Compare
3
33072 selection
</description>
33073 <bitOffset>0</bitOffset>
33074 <bitWidth>2</bitWidth>
33077 <name>OC3M_3
</name>
33078 <description>Output Compare
3 mode bit
33080 <bitOffset>16</bitOffset>
33081 <bitWidth>1</bitWidth>
33084 <name>OC4M_3
</name>
33085 <description>Output Compare
4 mode bit
33087 <bitOffset>24</bitOffset>
33088 <bitWidth>1</bitWidth>
33093 <name>CCMR2_Input
</name>
33094 <displayName>CCMR2_Input
</displayName>
33095 <description>capture/compare mode register
2 (input
33096 mode)
</description>
33097 <alternateRegister>CCMR2_Output
</alternateRegister>
33098 <addressOffset>0x1C</addressOffset>
33100 <access>read-write
</access>
33101 <resetValue>0x00000000</resetValue>
33105 <description>Input capture
4 filter
</description>
33106 <bitOffset>12</bitOffset>
33107 <bitWidth>4</bitWidth>
33110 <name>IC4PSC
</name>
33111 <description>Input capture
4 prescaler
</description>
33112 <bitOffset>10</bitOffset>
33113 <bitWidth>2</bitWidth>
33117 <description>Capture/Compare
4
33118 selection
</description>
33119 <bitOffset>8</bitOffset>
33120 <bitWidth>2</bitWidth>
33124 <description>Input capture
3 filter
</description>
33125 <bitOffset>4</bitOffset>
33126 <bitWidth>4</bitWidth>
33129 <name>IC3PSC
</name>
33130 <description>Input capture
3 prescaler
</description>
33131 <bitOffset>2</bitOffset>
33132 <bitWidth>2</bitWidth>
33136 <description>Capture/compare
3
33137 selection
</description>
33138 <bitOffset>0</bitOffset>
33139 <bitWidth>2</bitWidth>
33145 <displayName>CCER
</displayName>
33146 <description>capture/compare enable
33147 register
</description>
33148 <addressOffset>0x20</addressOffset>
33150 <access>read-write
</access>
33151 <resetValue>0x0000</resetValue>
33155 <description>Capture/Compare
1 output
33156 enable
</description>
33157 <bitOffset>0</bitOffset>
33158 <bitWidth>1</bitWidth>
33162 <description>Capture/Compare
1 output
33163 Polarity
</description>
33164 <bitOffset>1</bitOffset>
33165 <bitWidth>1</bitWidth>
33169 <description>Capture/Compare
1 complementary output
33170 enable
</description>
33171 <bitOffset>2</bitOffset>
33172 <bitWidth>1</bitWidth>
33176 <description>Capture/Compare
1 output
33177 Polarity
</description>
33178 <bitOffset>3</bitOffset>
33179 <bitWidth>1</bitWidth>
33183 <description>Capture/Compare
2 output
33184 enable
</description>
33185 <bitOffset>4</bitOffset>
33186 <bitWidth>1</bitWidth>
33190 <description>Capture/Compare
2 output
33191 Polarity
</description>
33192 <bitOffset>5</bitOffset>
33193 <bitWidth>1</bitWidth>
33197 <description>Capture/Compare
2 complementary output
33198 enable
</description>
33199 <bitOffset>6</bitOffset>
33200 <bitWidth>1</bitWidth>
33204 <description>Capture/Compare
2 output
33205 Polarity
</description>
33206 <bitOffset>7</bitOffset>
33207 <bitWidth>1</bitWidth>
33211 <description>Capture/Compare
3 output
33212 enable
</description>
33213 <bitOffset>8</bitOffset>
33214 <bitWidth>1</bitWidth>
33218 <description>Capture/Compare
3 output
33219 Polarity
</description>
33220 <bitOffset>9</bitOffset>
33221 <bitWidth>1</bitWidth>
33225 <description>Capture/Compare
3 complementary output
33226 enable
</description>
33227 <bitOffset>10</bitOffset>
33228 <bitWidth>1</bitWidth>
33232 <description>Capture/Compare
3 output
33233 Polarity
</description>
33234 <bitOffset>11</bitOffset>
33235 <bitWidth>1</bitWidth>
33239 <description>Capture/Compare
4 output
33240 enable
</description>
33241 <bitOffset>12</bitOffset>
33242 <bitWidth>1</bitWidth>
33246 <description>Capture/Compare
3 output
33247 Polarity
</description>
33248 <bitOffset>13</bitOffset>
33249 <bitWidth>1</bitWidth>
33253 <description>Capture/Compare
4 output
33254 Polarity
</description>
33255 <bitOffset>15</bitOffset>
33256 <bitWidth>1</bitWidth>
33260 <description>Capture/Compare
5 output
33261 enable
</description>
33262 <bitOffset>16</bitOffset>
33263 <bitWidth>1</bitWidth>
33267 <description>Capture/Compare
5 output
33268 Polarity
</description>
33269 <bitOffset>17</bitOffset>
33270 <bitWidth>1</bitWidth>
33274 <description>Capture/Compare
6 output
33275 enable
</description>
33276 <bitOffset>20</bitOffset>
33277 <bitWidth>1</bitWidth>
33281 <description>Capture/Compare
6 output
33282 Polarity
</description>
33283 <bitOffset>21</bitOffset>
33284 <bitWidth>1</bitWidth>
33290 <displayName>CNT
</displayName>
33291 <description>counter
</description>
33292 <addressOffset>0x24</addressOffset>
33294 <resetValue>0x00000000</resetValue>
33298 <description>counter value
</description>
33299 <bitOffset>0</bitOffset>
33300 <bitWidth>16</bitWidth>
33301 <access>read-write
</access>
33304 <name>UIFCPY
</name>
33305 <description>UIF copy
</description>
33306 <bitOffset>31</bitOffset>
33307 <bitWidth>1</bitWidth>
33308 <access>read-only
</access>
33314 <displayName>PSC
</displayName>
33315 <description>prescaler
</description>
33316 <addressOffset>0x28</addressOffset>
33318 <access>read-write
</access>
33319 <resetValue>0x0000</resetValue>
33323 <description>Prescaler value
</description>
33324 <bitOffset>0</bitOffset>
33325 <bitWidth>16</bitWidth>
33331 <displayName>ARR
</displayName>
33332 <description>auto-reload register
</description>
33333 <addressOffset>0x2C</addressOffset>
33335 <access>read-write
</access>
33336 <resetValue>0x00000000</resetValue>
33340 <description>Auto-reload value
</description>
33341 <bitOffset>0</bitOffset>
33342 <bitWidth>16</bitWidth>
33348 <displayName>RCR
</displayName>
33349 <description>repetition counter register
</description>
33350 <addressOffset>0x30</addressOffset>
33352 <access>read-write
</access>
33353 <resetValue>0x0000</resetValue>
33357 <description>Repetition counter value
</description>
33358 <bitOffset>0</bitOffset>
33359 <bitWidth>16</bitWidth>
33365 <displayName>CCR1
</displayName>
33366 <description>capture/compare register
1</description>
33367 <addressOffset>0x34</addressOffset>
33369 <access>read-write
</access>
33370 <resetValue>0x00000000</resetValue>
33374 <description>Capture/Compare
1 value
</description>
33375 <bitOffset>0</bitOffset>
33376 <bitWidth>16</bitWidth>
33382 <displayName>CCR2
</displayName>
33383 <description>capture/compare register
2</description>
33384 <addressOffset>0x38</addressOffset>
33386 <access>read-write
</access>
33387 <resetValue>0x00000000</resetValue>
33391 <description>Capture/Compare
2 value
</description>
33392 <bitOffset>0</bitOffset>
33393 <bitWidth>16</bitWidth>
33399 <displayName>CCR3
</displayName>
33400 <description>capture/compare register
3</description>
33401 <addressOffset>0x3C</addressOffset>
33403 <access>read-write
</access>
33404 <resetValue>0x00000000</resetValue>
33408 <description>Capture/Compare
3 value
</description>
33409 <bitOffset>0</bitOffset>
33410 <bitWidth>16</bitWidth>
33416 <displayName>CCR4
</displayName>
33417 <description>capture/compare register
4</description>
33418 <addressOffset>0x40</addressOffset>
33420 <access>read-write
</access>
33421 <resetValue>0x00000000</resetValue>
33425 <description>Capture/Compare
3 value
</description>
33426 <bitOffset>0</bitOffset>
33427 <bitWidth>16</bitWidth>
33433 <displayName>BDTR
</displayName>
33434 <description>break and dead-time register
</description>
33435 <addressOffset>0x44</addressOffset>
33437 <access>read-write
</access>
33438 <resetValue>0x00000000</resetValue>
33442 <description>Dead-time generator setup
</description>
33443 <bitOffset>0</bitOffset>
33444 <bitWidth>8</bitWidth>
33448 <description>Lock configuration
</description>
33449 <bitOffset>8</bitOffset>
33450 <bitWidth>2</bitWidth>
33454 <description>Off-state selection for Idle
33456 <bitOffset>10</bitOffset>
33457 <bitWidth>1</bitWidth>
33461 <description>Off-state selection for Run
33463 <bitOffset>11</bitOffset>
33464 <bitWidth>1</bitWidth>
33468 <description>Break enable
</description>
33469 <bitOffset>12</bitOffset>
33470 <bitWidth>1</bitWidth>
33474 <description>Break polarity
</description>
33475 <bitOffset>13</bitOffset>
33476 <bitWidth>1</bitWidth>
33480 <description>Automatic output enable
</description>
33481 <bitOffset>14</bitOffset>
33482 <bitWidth>1</bitWidth>
33486 <description>Main output enable
</description>
33487 <bitOffset>15</bitOffset>
33488 <bitWidth>1</bitWidth>
33492 <description>Break filter
</description>
33493 <bitOffset>16</bitOffset>
33494 <bitWidth>4</bitWidth>
33498 <description>Break
2 filter
</description>
33499 <bitOffset>20</bitOffset>
33500 <bitWidth>4</bitWidth>
33504 <description>Break
2 enable
</description>
33505 <bitOffset>24</bitOffset>
33506 <bitWidth>1</bitWidth>
33510 <description>Break
2 polarity
</description>
33511 <bitOffset>25</bitOffset>
33512 <bitWidth>1</bitWidth>
33518 <displayName>DCR
</displayName>
33519 <description>DMA control register
</description>
33520 <addressOffset>0x48</addressOffset>
33522 <access>read-write
</access>
33523 <resetValue>0x00000000</resetValue>
33527 <description>DMA burst length
</description>
33528 <bitOffset>8</bitOffset>
33529 <bitWidth>5</bitWidth>
33533 <description>DMA base address
</description>
33534 <bitOffset>0</bitOffset>
33535 <bitWidth>5</bitWidth>
33541 <displayName>DMAR
</displayName>
33542 <description>DMA address for full transfer
</description>
33543 <addressOffset>0x4C</addressOffset>
33545 <access>read-write
</access>
33546 <resetValue>0x00000000</resetValue>
33550 <description>DMA register for burst
33551 accesses
</description>
33552 <bitOffset>0</bitOffset>
33553 <bitWidth>16</bitWidth>
33558 <name>CCMR3_Output
</name>
33559 <displayName>CCMR3_Output
</displayName>
33560 <description>capture/compare mode register
3 (output
33561 mode)
</description>
33562 <addressOffset>0x54</addressOffset>
33564 <access>read-write
</access>
33565 <resetValue>0x00000000</resetValue>
33569 <description>Output compare
5 fast
33570 enable
</description>
33571 <bitOffset>2</bitOffset>
33572 <bitWidth>1</bitWidth>
33576 <description>Output compare
5 preload
33577 enable
</description>
33578 <bitOffset>3</bitOffset>
33579 <bitWidth>1</bitWidth>
33583 <description>Output compare
5 mode
</description>
33584 <bitOffset>4</bitOffset>
33585 <bitWidth>3</bitWidth>
33589 <description>Output compare
5 clear
33590 enable
</description>
33591 <bitOffset>7</bitOffset>
33592 <bitWidth>1</bitWidth>
33596 <description>Output compare
6 fast
33597 enable
</description>
33598 <bitOffset>10</bitOffset>
33599 <bitWidth>1</bitWidth>
33603 <description>Output compare
6 preload
33604 enable
</description>
33605 <bitOffset>11</bitOffset>
33606 <bitWidth>1</bitWidth>
33610 <description>Output compare
6 mode
</description>
33611 <bitOffset>12</bitOffset>
33612 <bitWidth>3</bitWidth>
33616 <description>Output compare
6 clear
33617 enable
</description>
33618 <bitOffset>15</bitOffset>
33619 <bitWidth>1</bitWidth>
33622 <name>OC5M_3
</name>
33623 <description>Outout Compare
5 mode bit
33625 <bitOffset>16</bitOffset>
33626 <bitWidth>1</bitWidth>
33629 <name>OC6M_3
</name>
33630 <description>Outout Compare
6 mode bit
33632 <bitOffset>24</bitOffset>
33633 <bitWidth>1</bitWidth>
33639 <displayName>CCR5
</displayName>
33640 <description>capture/compare register
5</description>
33641 <addressOffset>0x58</addressOffset>
33643 <access>read-write
</access>
33644 <resetValue>0x00000000</resetValue>
33648 <description>Capture/Compare
5 value
</description>
33649 <bitOffset>0</bitOffset>
33650 <bitWidth>16</bitWidth>
33654 <description>Group Channel
5 and Channel
33656 <bitOffset>29</bitOffset>
33657 <bitWidth>1</bitWidth>
33661 <description>Group Channel
5 and Channel
33663 <bitOffset>30</bitOffset>
33664 <bitWidth>1</bitWidth>
33668 <description>Group Channel
5 and Channel
33670 <bitOffset>31</bitOffset>
33671 <bitWidth>1</bitWidth>
33677 <displayName>CCR6
</displayName>
33678 <description>capture/compare register
6</description>
33679 <addressOffset>0x5C</addressOffset>
33681 <access>read-write
</access>
33682 <resetValue>0x00000000</resetValue>
33686 <description>Capture/Compare
6 value
</description>
33687 <bitOffset>0</bitOffset>
33688 <bitWidth>16</bitWidth>
33694 <displayName>OR
</displayName>
33695 <description>option registers
</description>
33696 <addressOffset>0x60</addressOffset>
33698 <access>read-write
</access>
33699 <resetValue>0x00000000</resetValue>
33702 <name>TIM8_ETR_ADC2_RMP
</name>
33703 <description>TIM8_ETR_ADC2 remapping
33704 capability
</description>
33705 <bitOffset>0</bitOffset>
33706 <bitWidth>2</bitWidth>
33709 <name>TIM8_ETR_ADC3_RMP
</name>
33710 <description>TIM8_ETR_ADC3 remapping
33711 capability
</description>
33712 <bitOffset>2</bitOffset>
33713 <bitWidth>2</bitWidth>
33721 <description>Analog-to-Digital Converter
</description>
33722 <groupName>ADC
</groupName>
33723 <baseAddress>0x50000000</baseAddress>
33725 <offset>0x0</offset>
33727 <usage>registers
</usage>
33730 <name>ADC1_2
</name>
33731 <description>ADC1 and ADC2 global interrupt
</description>
33737 <displayName>ISR
</displayName>
33738 <description>interrupt and status register
</description>
33739 <addressOffset>0x0</addressOffset>
33741 <access>read-write
</access>
33742 <resetValue>0x00000000</resetValue>
33746 <description>JQOVF
</description>
33747 <bitOffset>10</bitOffset>
33748 <bitWidth>1</bitWidth>
33752 <description>AWD3
</description>
33753 <bitOffset>9</bitOffset>
33754 <bitWidth>1</bitWidth>
33758 <description>AWD2
</description>
33759 <bitOffset>8</bitOffset>
33760 <bitWidth>1</bitWidth>
33764 <description>AWD1
</description>
33765 <bitOffset>7</bitOffset>
33766 <bitWidth>1</bitWidth>
33770 <description>JEOS
</description>
33771 <bitOffset>6</bitOffset>
33772 <bitWidth>1</bitWidth>
33776 <description>JEOC
</description>
33777 <bitOffset>5</bitOffset>
33778 <bitWidth>1</bitWidth>
33782 <description>OVR
</description>
33783 <bitOffset>4</bitOffset>
33784 <bitWidth>1</bitWidth>
33788 <description>EOS
</description>
33789 <bitOffset>3</bitOffset>
33790 <bitWidth>1</bitWidth>
33794 <description>EOC
</description>
33795 <bitOffset>2</bitOffset>
33796 <bitWidth>1</bitWidth>
33800 <description>EOSMP
</description>
33801 <bitOffset>1</bitOffset>
33802 <bitWidth>1</bitWidth>
33806 <description>ADRDY
</description>
33807 <bitOffset>0</bitOffset>
33808 <bitWidth>1</bitWidth>
33814 <displayName>IER
</displayName>
33815 <description>interrupt enable register
</description>
33816 <addressOffset>0x4</addressOffset>
33818 <access>read-write
</access>
33819 <resetValue>0x00000000</resetValue>
33822 <name>JQOVFIE
</name>
33823 <description>JQOVFIE
</description>
33824 <bitOffset>10</bitOffset>
33825 <bitWidth>1</bitWidth>
33828 <name>AWD3IE
</name>
33829 <description>AWD3IE
</description>
33830 <bitOffset>9</bitOffset>
33831 <bitWidth>1</bitWidth>
33834 <name>AWD2IE
</name>
33835 <description>AWD2IE
</description>
33836 <bitOffset>8</bitOffset>
33837 <bitWidth>1</bitWidth>
33840 <name>AWD1IE
</name>
33841 <description>AWD1IE
</description>
33842 <bitOffset>7</bitOffset>
33843 <bitWidth>1</bitWidth>
33846 <name>JEOSIE
</name>
33847 <description>JEOSIE
</description>
33848 <bitOffset>6</bitOffset>
33849 <bitWidth>1</bitWidth>
33852 <name>JEOCIE
</name>
33853 <description>JEOCIE
</description>
33854 <bitOffset>5</bitOffset>
33855 <bitWidth>1</bitWidth>
33859 <description>OVRIE
</description>
33860 <bitOffset>4</bitOffset>
33861 <bitWidth>1</bitWidth>
33865 <description>EOSIE
</description>
33866 <bitOffset>3</bitOffset>
33867 <bitWidth>1</bitWidth>
33871 <description>EOCIE
</description>
33872 <bitOffset>2</bitOffset>
33873 <bitWidth>1</bitWidth>
33876 <name>EOSMPIE
</name>
33877 <description>EOSMPIE
</description>
33878 <bitOffset>1</bitOffset>
33879 <bitWidth>1</bitWidth>
33882 <name>ADRDYIE
</name>
33883 <description>ADRDYIE
</description>
33884 <bitOffset>0</bitOffset>
33885 <bitWidth>1</bitWidth>
33891 <displayName>CR
</displayName>
33892 <description>control register
</description>
33893 <addressOffset>0x8</addressOffset>
33895 <access>read-write
</access>
33896 <resetValue>0x00000000</resetValue>
33900 <description>ADCAL
</description>
33901 <bitOffset>31</bitOffset>
33902 <bitWidth>1</bitWidth>
33905 <name>ADCALDIF
</name>
33906 <description>ADCALDIF
</description>
33907 <bitOffset>30</bitOffset>
33908 <bitWidth>1</bitWidth>
33911 <name>DEEPPWD
</name>
33912 <description>DEEPPWD
</description>
33913 <bitOffset>29</bitOffset>
33914 <bitWidth>1</bitWidth>
33917 <name>ADVREGEN
</name>
33918 <description>ADVREGEN
</description>
33919 <bitOffset>28</bitOffset>
33920 <bitWidth>1</bitWidth>
33923 <name>JADSTP
</name>
33924 <description>JADSTP
</description>
33925 <bitOffset>5</bitOffset>
33926 <bitWidth>1</bitWidth>
33930 <description>ADSTP
</description>
33931 <bitOffset>4</bitOffset>
33932 <bitWidth>1</bitWidth>
33935 <name>JADSTART
</name>
33936 <description>JADSTART
</description>
33937 <bitOffset>3</bitOffset>
33938 <bitWidth>1</bitWidth>
33941 <name>ADSTART
</name>
33942 <description>ADSTART
</description>
33943 <bitOffset>2</bitOffset>
33944 <bitWidth>1</bitWidth>
33948 <description>ADDIS
</description>
33949 <bitOffset>1</bitOffset>
33950 <bitWidth>1</bitWidth>
33954 <description>ADEN
</description>
33955 <bitOffset>0</bitOffset>
33956 <bitWidth>1</bitWidth>
33962 <displayName>CFGR
</displayName>
33963 <description>configuration register
</description>
33964 <addressOffset>0xC</addressOffset>
33966 <access>read-write
</access>
33967 <resetValue>0x00000000</resetValue>
33970 <name>AWDCH1CH
</name>
33971 <description>AWDCH1CH
</description>
33972 <bitOffset>26</bitOffset>
33973 <bitWidth>5</bitWidth>
33977 <description>JAUTO
</description>
33978 <bitOffset>25</bitOffset>
33979 <bitWidth>1</bitWidth>
33982 <name>JAWD1EN
</name>
33983 <description>JAWD1EN
</description>
33984 <bitOffset>24</bitOffset>
33985 <bitWidth>1</bitWidth>
33988 <name>AWD1EN
</name>
33989 <description>AWD1EN
</description>
33990 <bitOffset>23</bitOffset>
33991 <bitWidth>1</bitWidth>
33994 <name>AWD1SGL
</name>
33995 <description>AWD1SGL
</description>
33996 <bitOffset>22</bitOffset>
33997 <bitWidth>1</bitWidth>
34001 <description>JQM
</description>
34002 <bitOffset>21</bitOffset>
34003 <bitWidth>1</bitWidth>
34006 <name>JDISCEN
</name>
34007 <description>JDISCEN
</description>
34008 <bitOffset>20</bitOffset>
34009 <bitWidth>1</bitWidth>
34012 <name>DISCNUM
</name>
34013 <description>DISCNUM
</description>
34014 <bitOffset>17</bitOffset>
34015 <bitWidth>3</bitWidth>
34018 <name>DISCEN
</name>
34019 <description>DISCEN
</description>
34020 <bitOffset>16</bitOffset>
34021 <bitWidth>1</bitWidth>
34024 <name>AUTOFF
</name>
34025 <description>AUTOFF
</description>
34026 <bitOffset>15</bitOffset>
34027 <bitWidth>1</bitWidth>
34030 <name>AUTDLY
</name>
34031 <description>AUTDLY
</description>
34032 <bitOffset>14</bitOffset>
34033 <bitWidth>1</bitWidth>
34037 <description>CONT
</description>
34038 <bitOffset>13</bitOffset>
34039 <bitWidth>1</bitWidth>
34042 <name>OVRMOD
</name>
34043 <description>OVRMOD
</description>
34044 <bitOffset>12</bitOffset>
34045 <bitWidth>1</bitWidth>
34049 <description>EXTEN
</description>
34050 <bitOffset>10</bitOffset>
34051 <bitWidth>2</bitWidth>
34054 <name>EXTSEL
</name>
34055 <description>EXTSEL
</description>
34056 <bitOffset>6</bitOffset>
34057 <bitWidth>4</bitWidth>
34061 <description>ALIGN
</description>
34062 <bitOffset>5</bitOffset>
34063 <bitWidth>1</bitWidth>
34067 <description>RES
</description>
34068 <bitOffset>3</bitOffset>
34069 <bitWidth>2</bitWidth>
34072 <name>DMACFG
</name>
34073 <description>DMACFG
</description>
34074 <bitOffset>1</bitOffset>
34075 <bitWidth>1</bitWidth>
34079 <description>DMAEN
</description>
34080 <bitOffset>0</bitOffset>
34081 <bitWidth>1</bitWidth>
34087 <displayName>SMPR1
</displayName>
34088 <description>sample time register
1</description>
34089 <addressOffset>0x14</addressOffset>
34091 <access>read-write
</access>
34092 <resetValue>0x00000000</resetValue>
34096 <description>SMP9
</description>
34097 <bitOffset>27</bitOffset>
34098 <bitWidth>3</bitWidth>
34102 <description>SMP8
</description>
34103 <bitOffset>24</bitOffset>
34104 <bitWidth>3</bitWidth>
34108 <description>SMP7
</description>
34109 <bitOffset>21</bitOffset>
34110 <bitWidth>3</bitWidth>
34114 <description>SMP6
</description>
34115 <bitOffset>18</bitOffset>
34116 <bitWidth>3</bitWidth>
34120 <description>SMP5
</description>
34121 <bitOffset>15</bitOffset>
34122 <bitWidth>3</bitWidth>
34126 <description>SMP4
</description>
34127 <bitOffset>12</bitOffset>
34128 <bitWidth>3</bitWidth>
34132 <description>SMP3
</description>
34133 <bitOffset>9</bitOffset>
34134 <bitWidth>3</bitWidth>
34138 <description>SMP2
</description>
34139 <bitOffset>6</bitOffset>
34140 <bitWidth>3</bitWidth>
34144 <description>SMP1
</description>
34145 <bitOffset>3</bitOffset>
34146 <bitWidth>3</bitWidth>
34152 <displayName>SMPR2
</displayName>
34153 <description>sample time register
2</description>
34154 <addressOffset>0x18</addressOffset>
34156 <access>read-write
</access>
34157 <resetValue>0x00000000</resetValue>
34161 <description>SMP18
</description>
34162 <bitOffset>24</bitOffset>
34163 <bitWidth>3</bitWidth>
34167 <description>SMP17
</description>
34168 <bitOffset>21</bitOffset>
34169 <bitWidth>3</bitWidth>
34173 <description>SMP16
</description>
34174 <bitOffset>18</bitOffset>
34175 <bitWidth>3</bitWidth>
34179 <description>SMP15
</description>
34180 <bitOffset>15</bitOffset>
34181 <bitWidth>3</bitWidth>
34185 <description>SMP14
</description>
34186 <bitOffset>12</bitOffset>
34187 <bitWidth>3</bitWidth>
34191 <description>SMP13
</description>
34192 <bitOffset>9</bitOffset>
34193 <bitWidth>3</bitWidth>
34197 <description>SMP12
</description>
34198 <bitOffset>6</bitOffset>
34199 <bitWidth>3</bitWidth>
34203 <description>SMP11
</description>
34204 <bitOffset>3</bitOffset>
34205 <bitWidth>3</bitWidth>
34209 <description>SMP10
</description>
34210 <bitOffset>0</bitOffset>
34211 <bitWidth>3</bitWidth>
34217 <displayName>TR1
</displayName>
34218 <description>watchdog threshold register
1</description>
34219 <addressOffset>0x20</addressOffset>
34221 <access>read-write
</access>
34222 <resetValue>0x0FFF0000</resetValue>
34226 <description>HT1
</description>
34227 <bitOffset>16</bitOffset>
34228 <bitWidth>12</bitWidth>
34232 <description>LT1
</description>
34233 <bitOffset>0</bitOffset>
34234 <bitWidth>12</bitWidth>
34240 <displayName>TR2
</displayName>
34241 <description>watchdog threshold register
</description>
34242 <addressOffset>0x24</addressOffset>
34244 <access>read-write
</access>
34245 <resetValue>0x0FFF0000</resetValue>
34249 <description>HT2
</description>
34250 <bitOffset>16</bitOffset>
34251 <bitWidth>8</bitWidth>
34255 <description>LT2
</description>
34256 <bitOffset>0</bitOffset>
34257 <bitWidth>8</bitWidth>
34263 <displayName>TR3
</displayName>
34264 <description>watchdog threshold register
3</description>
34265 <addressOffset>0x28</addressOffset>
34267 <access>read-write
</access>
34268 <resetValue>0x0FFF0000</resetValue>
34272 <description>HT3
</description>
34273 <bitOffset>16</bitOffset>
34274 <bitWidth>8</bitWidth>
34278 <description>LT3
</description>
34279 <bitOffset>0</bitOffset>
34280 <bitWidth>8</bitWidth>
34286 <displayName>SQR1
</displayName>
34287 <description>regular sequence register
1</description>
34288 <addressOffset>0x30</addressOffset>
34290 <access>read-write
</access>
34291 <resetValue>0x00000000</resetValue>
34295 <description>SQ4
</description>
34296 <bitOffset>24</bitOffset>
34297 <bitWidth>5</bitWidth>
34301 <description>SQ3
</description>
34302 <bitOffset>18</bitOffset>
34303 <bitWidth>5</bitWidth>
34307 <description>SQ2
</description>
34308 <bitOffset>12</bitOffset>
34309 <bitWidth>5</bitWidth>
34313 <description>SQ1
</description>
34314 <bitOffset>6</bitOffset>
34315 <bitWidth>5</bitWidth>
34319 <description>L3
</description>
34320 <bitOffset>0</bitOffset>
34321 <bitWidth>4</bitWidth>
34327 <displayName>SQR2
</displayName>
34328 <description>regular sequence register
2</description>
34329 <addressOffset>0x34</addressOffset>
34331 <access>read-write
</access>
34332 <resetValue>0x00000000</resetValue>
34336 <description>SQ9
</description>
34337 <bitOffset>24</bitOffset>
34338 <bitWidth>5</bitWidth>
34342 <description>SQ8
</description>
34343 <bitOffset>18</bitOffset>
34344 <bitWidth>5</bitWidth>
34348 <description>SQ7
</description>
34349 <bitOffset>12</bitOffset>
34350 <bitWidth>5</bitWidth>
34354 <description>SQ6
</description>
34355 <bitOffset>6</bitOffset>
34356 <bitWidth>5</bitWidth>
34360 <description>SQ5
</description>
34361 <bitOffset>0</bitOffset>
34362 <bitWidth>5</bitWidth>
34368 <displayName>SQR3
</displayName>
34369 <description>regular sequence register
3</description>
34370 <addressOffset>0x38</addressOffset>
34372 <access>read-write
</access>
34373 <resetValue>0x00000000</resetValue>
34377 <description>SQ14
</description>
34378 <bitOffset>24</bitOffset>
34379 <bitWidth>5</bitWidth>
34383 <description>SQ13
</description>
34384 <bitOffset>18</bitOffset>
34385 <bitWidth>5</bitWidth>
34389 <description>SQ12
</description>
34390 <bitOffset>12</bitOffset>
34391 <bitWidth>5</bitWidth>
34395 <description>SQ11
</description>
34396 <bitOffset>6</bitOffset>
34397 <bitWidth>5</bitWidth>
34401 <description>SQ10
</description>
34402 <bitOffset>0</bitOffset>
34403 <bitWidth>5</bitWidth>
34409 <displayName>SQR4
</displayName>
34410 <description>regular sequence register
4</description>
34411 <addressOffset>0x3C</addressOffset>
34413 <access>read-write
</access>
34414 <resetValue>0x00000000</resetValue>
34418 <description>SQ16
</description>
34419 <bitOffset>6</bitOffset>
34420 <bitWidth>5</bitWidth>
34424 <description>SQ15
</description>
34425 <bitOffset>0</bitOffset>
34426 <bitWidth>5</bitWidth>
34432 <displayName>DR
</displayName>
34433 <description>regular Data Register
</description>
34434 <addressOffset>0x40</addressOffset>
34436 <access>read-only
</access>
34437 <resetValue>0x00000000</resetValue>
34440 <name>regularDATA
</name>
34441 <description>regularDATA
</description>
34442 <bitOffset>0</bitOffset>
34443 <bitWidth>16</bitWidth>
34449 <displayName>JSQR
</displayName>
34450 <description>injected sequence register
</description>
34451 <addressOffset>0x4C</addressOffset>
34453 <access>read-write
</access>
34454 <resetValue>0x00000000</resetValue>
34458 <description>JSQ4
</description>
34459 <bitOffset>26</bitOffset>
34460 <bitWidth>5</bitWidth>
34464 <description>JSQ3
</description>
34465 <bitOffset>20</bitOffset>
34466 <bitWidth>5</bitWidth>
34470 <description>JSQ2
</description>
34471 <bitOffset>14</bitOffset>
34472 <bitWidth>5</bitWidth>
34476 <description>JSQ1
</description>
34477 <bitOffset>8</bitOffset>
34478 <bitWidth>5</bitWidth>
34481 <name>JEXTEN
</name>
34482 <description>JEXTEN
</description>
34483 <bitOffset>6</bitOffset>
34484 <bitWidth>2</bitWidth>
34487 <name>JEXTSEL
</name>
34488 <description>JEXTSEL
</description>
34489 <bitOffset>2</bitOffset>
34490 <bitWidth>4</bitWidth>
34494 <description>JL
</description>
34495 <bitOffset>0</bitOffset>
34496 <bitWidth>2</bitWidth>
34502 <displayName>OFR1
</displayName>
34503 <description>offset register
1</description>
34504 <addressOffset>0x60</addressOffset>
34506 <access>read-write
</access>
34507 <resetValue>0x00000000</resetValue>
34510 <name>OFFSET1_EN
</name>
34511 <description>OFFSET1_EN
</description>
34512 <bitOffset>31</bitOffset>
34513 <bitWidth>1</bitWidth>
34516 <name>OFFSET1_CH
</name>
34517 <description>OFFSET1_CH
</description>
34518 <bitOffset>26</bitOffset>
34519 <bitWidth>5</bitWidth>
34522 <name>OFFSET1
</name>
34523 <description>OFFSET1
</description>
34524 <bitOffset>0</bitOffset>
34525 <bitWidth>12</bitWidth>
34531 <displayName>OFR2
</displayName>
34532 <description>offset register
2</description>
34533 <addressOffset>0x64</addressOffset>
34535 <access>read-write
</access>
34536 <resetValue>0x00000000</resetValue>
34539 <name>OFFSET2_EN
</name>
34540 <description>OFFSET2_EN
</description>
34541 <bitOffset>31</bitOffset>
34542 <bitWidth>1</bitWidth>
34545 <name>OFFSET2_CH
</name>
34546 <description>OFFSET2_CH
</description>
34547 <bitOffset>26</bitOffset>
34548 <bitWidth>5</bitWidth>
34551 <name>OFFSET2
</name>
34552 <description>OFFSET2
</description>
34553 <bitOffset>0</bitOffset>
34554 <bitWidth>12</bitWidth>
34560 <displayName>OFR3
</displayName>
34561 <description>offset register
3</description>
34562 <addressOffset>0x68</addressOffset>
34564 <access>read-write
</access>
34565 <resetValue>0x00000000</resetValue>
34568 <name>OFFSET3_EN
</name>
34569 <description>OFFSET3_EN
</description>
34570 <bitOffset>31</bitOffset>
34571 <bitWidth>1</bitWidth>
34574 <name>OFFSET3_CH
</name>
34575 <description>OFFSET3_CH
</description>
34576 <bitOffset>26</bitOffset>
34577 <bitWidth>5</bitWidth>
34580 <name>OFFSET3
</name>
34581 <description>OFFSET3
</description>
34582 <bitOffset>0</bitOffset>
34583 <bitWidth>12</bitWidth>
34589 <displayName>OFR4
</displayName>
34590 <description>offset register
4</description>
34591 <addressOffset>0x6C</addressOffset>
34593 <access>read-write
</access>
34594 <resetValue>0x00000000</resetValue>
34597 <name>OFFSET4_EN
</name>
34598 <description>OFFSET4_EN
</description>
34599 <bitOffset>31</bitOffset>
34600 <bitWidth>1</bitWidth>
34603 <name>OFFSET4_CH
</name>
34604 <description>OFFSET4_CH
</description>
34605 <bitOffset>26</bitOffset>
34606 <bitWidth>5</bitWidth>
34609 <name>OFFSET4
</name>
34610 <description>OFFSET4
</description>
34611 <bitOffset>0</bitOffset>
34612 <bitWidth>12</bitWidth>
34618 <displayName>JDR1
</displayName>
34619 <description>injected data register
1</description>
34620 <addressOffset>0x80</addressOffset>
34622 <access>read-only
</access>
34623 <resetValue>0x00000000</resetValue>
34626 <name>JDATA1
</name>
34627 <description>JDATA1
</description>
34628 <bitOffset>0</bitOffset>
34629 <bitWidth>16</bitWidth>
34635 <displayName>JDR2
</displayName>
34636 <description>injected data register
2</description>
34637 <addressOffset>0x84</addressOffset>
34639 <access>read-only
</access>
34640 <resetValue>0x00000000</resetValue>
34643 <name>JDATA2
</name>
34644 <description>JDATA2
</description>
34645 <bitOffset>0</bitOffset>
34646 <bitWidth>16</bitWidth>
34652 <displayName>JDR3
</displayName>
34653 <description>injected data register
3</description>
34654 <addressOffset>0x88</addressOffset>
34656 <access>read-only
</access>
34657 <resetValue>0x00000000</resetValue>
34660 <name>JDATA3
</name>
34661 <description>JDATA3
</description>
34662 <bitOffset>0</bitOffset>
34663 <bitWidth>16</bitWidth>
34669 <displayName>JDR4
</displayName>
34670 <description>injected data register
4</description>
34671 <addressOffset>0x8C</addressOffset>
34673 <access>read-only
</access>
34674 <resetValue>0x00000000</resetValue>
34677 <name>JDATA4
</name>
34678 <description>JDATA4
</description>
34679 <bitOffset>0</bitOffset>
34680 <bitWidth>16</bitWidth>
34685 <name>AWD2CR
</name>
34686 <displayName>AWD2CR
</displayName>
34687 <description>Analog Watchdog
2 Configuration
34688 Register
</description>
34689 <addressOffset>0xA0</addressOffset>
34691 <access>read-write
</access>
34692 <resetValue>0x00000000</resetValue>
34695 <name>AWD2CH
</name>
34696 <description>AWD2CH
</description>
34697 <bitOffset>1</bitOffset>
34698 <bitWidth>18</bitWidth>
34703 <name>AWD3CR
</name>
34704 <displayName>AWD3CR
</displayName>
34705 <description>Analog Watchdog
3 Configuration
34706 Register
</description>
34707 <addressOffset>0xA4</addressOffset>
34709 <access>read-write
</access>
34710 <resetValue>0x00000000</resetValue>
34713 <name>AWD3CH
</name>
34714 <description>AWD3CH
</description>
34715 <bitOffset>1</bitOffset>
34716 <bitWidth>18</bitWidth>
34721 <name>DIFSEL
</name>
34722 <displayName>DIFSEL
</displayName>
34723 <description>Differential Mode Selection Register
34725 <addressOffset>0xB0</addressOffset>
34727 <resetValue>0x00000000</resetValue>
34730 <name>DIFSEL_1_15
</name>
34731 <description>Differential mode for channels
15 to
34733 <bitOffset>1</bitOffset>
34734 <bitWidth>15</bitWidth>
34735 <access>read-write
</access>
34738 <name>DIFSEL_16_18
</name>
34739 <description>Differential mode for channels
18 to
34741 <bitOffset>16</bitOffset>
34742 <bitWidth>3</bitWidth>
34743 <access>read-only
</access>
34748 <name>CALFACT
</name>
34749 <displayName>CALFACT
</displayName>
34750 <description>Calibration Factors
</description>
34751 <addressOffset>0xB4</addressOffset>
34753 <access>read-write
</access>
34754 <resetValue>0x00000000</resetValue>
34757 <name>CALFACT_D
</name>
34758 <description>CALFACT_D
</description>
34759 <bitOffset>16</bitOffset>
34760 <bitWidth>7</bitWidth>
34763 <name>CALFACT_S
</name>
34764 <description>CALFACT_S
</description>
34765 <bitOffset>0</bitOffset>
34766 <bitWidth>7</bitWidth>
34772 <peripheral derivedFrom=
"ADC1">
34774 <baseAddress>0x50000100</baseAddress>
34776 <name>ADC1_2
</name>
34777 <description>ADC1 and ADC2 global interrupt
</description>
34781 <peripheral derivedFrom=
"ADC1">
34783 <baseAddress>0x50000400</baseAddress>
34786 <description>ADC3 global interrupt
</description>
34790 <peripheral derivedFrom=
"ADC1">
34792 <baseAddress>0x50000500</baseAddress>
34795 <description>ADC4 global interrupt
</description>
34800 <name>ADC1_2
</name>
34801 <description>Analog-to-Digital Converter
</description>
34802 <groupName>ADC
</groupName>
34803 <baseAddress>0x50000300</baseAddress>
34805 <offset>0x0</offset>
34807 <usage>registers
</usage>
34812 <displayName>CSR
</displayName>
34813 <description>ADC Common status register
</description>
34814 <addressOffset>0x0</addressOffset>
34816 <access>read-only
</access>
34817 <resetValue>0x00000000</resetValue>
34820 <name>ADDRDY_MST
</name>
34821 <description>ADDRDY_MST
</description>
34822 <bitOffset>0</bitOffset>
34823 <bitWidth>1</bitWidth>
34826 <name>EOSMP_MST
</name>
34827 <description>EOSMP_MST
</description>
34828 <bitOffset>1</bitOffset>
34829 <bitWidth>1</bitWidth>
34832 <name>EOC_MST
</name>
34833 <description>EOC_MST
</description>
34834 <bitOffset>2</bitOffset>
34835 <bitWidth>1</bitWidth>
34838 <name>EOS_MST
</name>
34839 <description>EOS_MST
</description>
34840 <bitOffset>3</bitOffset>
34841 <bitWidth>1</bitWidth>
34844 <name>OVR_MST
</name>
34845 <description>OVR_MST
</description>
34846 <bitOffset>4</bitOffset>
34847 <bitWidth>1</bitWidth>
34850 <name>JEOC_MST
</name>
34851 <description>JEOC_MST
</description>
34852 <bitOffset>5</bitOffset>
34853 <bitWidth>1</bitWidth>
34856 <name>JEOS_MST
</name>
34857 <description>JEOS_MST
</description>
34858 <bitOffset>6</bitOffset>
34859 <bitWidth>1</bitWidth>
34862 <name>AWD1_MST
</name>
34863 <description>AWD1_MST
</description>
34864 <bitOffset>7</bitOffset>
34865 <bitWidth>1</bitWidth>
34868 <name>AWD2_MST
</name>
34869 <description>AWD2_MST
</description>
34870 <bitOffset>8</bitOffset>
34871 <bitWidth>1</bitWidth>
34874 <name>AWD3_MST
</name>
34875 <description>AWD3_MST
</description>
34876 <bitOffset>9</bitOffset>
34877 <bitWidth>1</bitWidth>
34880 <name>JQOVF_MST
</name>
34881 <description>JQOVF_MST
</description>
34882 <bitOffset>10</bitOffset>
34883 <bitWidth>1</bitWidth>
34886 <name>ADRDY_SLV
</name>
34887 <description>ADRDY_SLV
</description>
34888 <bitOffset>16</bitOffset>
34889 <bitWidth>1</bitWidth>
34892 <name>EOSMP_SLV
</name>
34893 <description>EOSMP_SLV
</description>
34894 <bitOffset>17</bitOffset>
34895 <bitWidth>1</bitWidth>
34898 <name>EOC_SLV
</name>
34899 <description>End of regular conversion of the slave
34901 <bitOffset>18</bitOffset>
34902 <bitWidth>1</bitWidth>
34905 <name>EOS_SLV
</name>
34906 <description>End of regular sequence flag of the
34907 slave ADC
</description>
34908 <bitOffset>19</bitOffset>
34909 <bitWidth>1</bitWidth>
34912 <name>OVR_SLV
</name>
34913 <description>Overrun flag of the slave
34915 <bitOffset>20</bitOffset>
34916 <bitWidth>1</bitWidth>
34919 <name>JEOC_SLV
</name>
34920 <description>End of injected conversion flag of the
34921 slave ADC
</description>
34922 <bitOffset>21</bitOffset>
34923 <bitWidth>1</bitWidth>
34926 <name>JEOS_SLV
</name>
34927 <description>End of injected sequence flag of the
34928 slave ADC
</description>
34929 <bitOffset>22</bitOffset>
34930 <bitWidth>1</bitWidth>
34933 <name>AWD1_SLV
</name>
34934 <description>Analog watchdog
1 flag of the slave
34936 <bitOffset>23</bitOffset>
34937 <bitWidth>1</bitWidth>
34940 <name>AWD2_SLV
</name>
34941 <description>Analog watchdog
2 flag of the slave
34943 <bitOffset>24</bitOffset>
34944 <bitWidth>1</bitWidth>
34947 <name>AWD3_SLV
</name>
34948 <description>Analog watchdog
3 flag of the slave
34950 <bitOffset>25</bitOffset>
34951 <bitWidth>1</bitWidth>
34954 <name>JQOVF_SLV
</name>
34955 <description>Injected Context Queue Overflow flag of
34956 the slave ADC
</description>
34957 <bitOffset>26</bitOffset>
34958 <bitWidth>1</bitWidth>
34964 <displayName>CCR
</displayName>
34965 <description>ADC common control register
</description>
34966 <addressOffset>0x8</addressOffset>
34968 <access>read-write
</access>
34969 <resetValue>0x00000000</resetValue>
34973 <description>Multi ADC mode selection
</description>
34974 <bitOffset>0</bitOffset>
34975 <bitWidth>5</bitWidth>
34979 <description>Delay between
2 sampling
34980 phases
</description>
34981 <bitOffset>8</bitOffset>
34982 <bitWidth>4</bitWidth>
34985 <name>DMACFG
</name>
34986 <description>DMA configuration (for multi-ADC
34987 mode)
</description>
34988 <bitOffset>13</bitOffset>
34989 <bitWidth>1</bitWidth>
34993 <description>Direct memory access mode for multi ADC
34995 <bitOffset>14</bitOffset>
34996 <bitWidth>2</bitWidth>
34999 <name>CKMODE
</name>
35000 <description>ADC clock mode
</description>
35001 <bitOffset>16</bitOffset>
35002 <bitWidth>2</bitWidth>
35005 <name>VREFEN
</name>
35006 <description>VREFINT enable
</description>
35007 <bitOffset>22</bitOffset>
35008 <bitWidth>1</bitWidth>
35012 <description>Temperature sensor enable
</description>
35013 <bitOffset>23</bitOffset>
35014 <bitWidth>1</bitWidth>
35017 <name>VBATEN
</name>
35018 <description>VBAT enable
</description>
35019 <bitOffset>24</bitOffset>
35020 <bitWidth>1</bitWidth>
35026 <displayName>CDR
</displayName>
35027 <description>ADC common regular data register for dual
35028 and triple modes
</description>
35029 <addressOffset>0xC</addressOffset>
35031 <access>read-only
</access>
35032 <resetValue>0x00000000</resetValue>
35035 <name>RDATA_SLV
</name>
35036 <description>Regular data of the slave
35038 <bitOffset>16</bitOffset>
35039 <bitWidth>16</bitWidth>
35042 <name>RDATA_MST
</name>
35043 <description>Regular data of the master
35045 <bitOffset>0</bitOffset>
35046 <bitWidth>16</bitWidth>
35052 <peripheral derivedFrom=
"ADC1_2">
35053 <name>ADC3_4
</name>
35054 <baseAddress>0x50000700</baseAddress>
35057 <name>SYSCFG_COMP_OPAMP
</name>
35058 <description>System configuration controller _Comparator and
35059 Operational amplifier
</description>
35060 <groupName>SYSCFG_COMP_OPAMP
</groupName>
35061 <baseAddress>0x40010000</baseAddress>
35063 <offset>0x0</offset>
35065 <usage>registers
</usage>
35068 <name>COMP123
</name>
35069 <description>COMP1
& COMP2
& COMP3 interrupts
35070 combined with EXTI Lines
21,
22 and
29
35071 interrupts
</description>
35075 <name>COMP456
</name>
35076 <description>COMP4
& COMP5
& COMP6 interrupts
35077 combined with EXTI Lines
30,
31 and
32
35078 interrupts
</description>
35083 <description>COMP7 interrupt combined with EXTI Line
33
35084 interrupt
</description>
35089 <name>SYSCFG_CFGR1
</name>
35090 <displayName>SYSCFG_CFGR1
</displayName>
35091 <description>configuration register
1</description>
35092 <addressOffset>0x0</addressOffset>
35094 <access>read-write
</access>
35095 <resetValue>0x00000000</resetValue>
35098 <name>MEM_MODE
</name>
35099 <description>Memory mapping selection
35101 <bitOffset>0</bitOffset>
35102 <bitWidth>2</bitWidth>
35105 <name>USB_IT_RMP
</name>
35106 <description>USB interrupt remap
</description>
35107 <bitOffset>5</bitOffset>
35108 <bitWidth>1</bitWidth>
35111 <name>TIM1_ITR_RMP
</name>
35112 <description>Timer
1 ITR3 selection
</description>
35113 <bitOffset>6</bitOffset>
35114 <bitWidth>1</bitWidth>
35117 <name>DAC_TRIG_RMP
</name>
35118 <description>DAC trigger remap (when TSEL =
35120 <bitOffset>7</bitOffset>
35121 <bitWidth>1</bitWidth>
35124 <name>ADC24_DMA_RMP
</name>
35125 <description>ADC24 DMA remapping bit
</description>
35126 <bitOffset>8</bitOffset>
35127 <bitWidth>1</bitWidth>
35130 <name>TIM16_DMA_RMP
</name>
35131 <description>TIM16 DMA request remapping
35133 <bitOffset>11</bitOffset>
35134 <bitWidth>1</bitWidth>
35137 <name>TIM17_DMA_RMP
</name>
35138 <description>TIM17 DMA request remapping
35140 <bitOffset>12</bitOffset>
35141 <bitWidth>1</bitWidth>
35144 <name>TIM6_DAC1_DMA_RMP
</name>
35145 <description>TIM6 and DAC1 DMA request remapping
35147 <bitOffset>13</bitOffset>
35148 <bitWidth>1</bitWidth>
35151 <name>TIM7_DAC2_DMA_RMP
</name>
35152 <description>TIM7 and DAC2 DMA request remapping
35154 <bitOffset>14</bitOffset>
35155 <bitWidth>1</bitWidth>
35158 <name>I2C_PB6_FM
</name>
35159 <description>Fast Mode Plus (FM+) driving capability
35160 activation bits.
</description>
35161 <bitOffset>16</bitOffset>
35162 <bitWidth>1</bitWidth>
35165 <name>I2C_PB7_FM
</name>
35166 <description>Fast Mode Plus (FM+) driving capability
35167 activation bits.
</description>
35168 <bitOffset>17</bitOffset>
35169 <bitWidth>1</bitWidth>
35172 <name>I2C_PB8_FM
</name>
35173 <description>Fast Mode Plus (FM+) driving capability
35174 activation bits.
</description>
35175 <bitOffset>18</bitOffset>
35176 <bitWidth>1</bitWidth>
35179 <name>I2C_PB9_FM
</name>
35180 <description>Fast Mode Plus (FM+) driving capability
35181 activation bits.
</description>
35182 <bitOffset>19</bitOffset>
35183 <bitWidth>1</bitWidth>
35186 <name>I2C1_FM
</name>
35187 <description>I2C1 Fast Mode Plus
</description>
35188 <bitOffset>20</bitOffset>
35189 <bitWidth>1</bitWidth>
35192 <name>I2C2_FM
</name>
35193 <description>I2C2 Fast Mode Plus
</description>
35194 <bitOffset>21</bitOffset>
35195 <bitWidth>1</bitWidth>
35198 <name>ENCODER_MODE
</name>
35199 <description>Encoder mode
</description>
35200 <bitOffset>22</bitOffset>
35201 <bitWidth>2</bitWidth>
35204 <name>FPU_IT
</name>
35205 <description>Interrupt enable bits from
35207 <bitOffset>26</bitOffset>
35208 <bitWidth>6</bitWidth>
35213 <name>SYSCFG_EXTICR1
</name>
35214 <displayName>SYSCFG_EXTICR1
</displayName>
35215 <description>external interrupt configuration register
35217 <addressOffset>0x8</addressOffset>
35219 <access>read-write
</access>
35220 <resetValue>0x0000</resetValue>
35224 <description>EXTI
3 configuration bits
</description>
35225 <bitOffset>12</bitOffset>
35226 <bitWidth>4</bitWidth>
35230 <description>EXTI
2 configuration bits
</description>
35231 <bitOffset>8</bitOffset>
35232 <bitWidth>4</bitWidth>
35236 <description>EXTI
1 configuration bits
</description>
35237 <bitOffset>4</bitOffset>
35238 <bitWidth>4</bitWidth>
35242 <description>EXTI
0 configuration bits
</description>
35243 <bitOffset>0</bitOffset>
35244 <bitWidth>4</bitWidth>
35249 <name>SYSCFG_EXTICR2
</name>
35250 <displayName>SYSCFG_EXTICR2
</displayName>
35251 <description>external interrupt configuration register
35253 <addressOffset>0xC</addressOffset>
35255 <access>read-write
</access>
35256 <resetValue>0x0000</resetValue>
35260 <description>EXTI
7 configuration bits
</description>
35261 <bitOffset>12</bitOffset>
35262 <bitWidth>4</bitWidth>
35266 <description>EXTI
6 configuration bits
</description>
35267 <bitOffset>8</bitOffset>
35268 <bitWidth>4</bitWidth>
35272 <description>EXTI
5 configuration bits
</description>
35273 <bitOffset>4</bitOffset>
35274 <bitWidth>4</bitWidth>
35278 <description>EXTI
4 configuration bits
</description>
35279 <bitOffset>0</bitOffset>
35280 <bitWidth>4</bitWidth>
35285 <name>SYSCFG_EXTICR3
</name>
35286 <displayName>SYSCFG_EXTICR3
</displayName>
35287 <description>external interrupt configuration register
35289 <addressOffset>0x10</addressOffset>
35291 <access>read-write
</access>
35292 <resetValue>0x0000</resetValue>
35295 <name>EXTI11
</name>
35296 <description>EXTI
11 configuration bits
</description>
35297 <bitOffset>12</bitOffset>
35298 <bitWidth>4</bitWidth>
35301 <name>EXTI10
</name>
35302 <description>EXTI
10 configuration bits
</description>
35303 <bitOffset>8</bitOffset>
35304 <bitWidth>4</bitWidth>
35308 <description>EXTI
9 configuration bits
</description>
35309 <bitOffset>4</bitOffset>
35310 <bitWidth>4</bitWidth>
35314 <description>EXTI
8 configuration bits
</description>
35315 <bitOffset>0</bitOffset>
35316 <bitWidth>4</bitWidth>
35321 <name>SYSCFG_EXTICR4
</name>
35322 <displayName>SYSCFG_EXTICR4
</displayName>
35323 <description>external interrupt configuration register
35325 <addressOffset>0x14</addressOffset>
35327 <access>read-write
</access>
35328 <resetValue>0x0000</resetValue>
35331 <name>EXTI15
</name>
35332 <description>EXTI
15 configuration bits
</description>
35333 <bitOffset>12</bitOffset>
35334 <bitWidth>4</bitWidth>
35337 <name>EXTI14
</name>
35338 <description>EXTI
14 configuration bits
</description>
35339 <bitOffset>8</bitOffset>
35340 <bitWidth>4</bitWidth>
35343 <name>EXTI13
</name>
35344 <description>EXTI
13 configuration bits
</description>
35345 <bitOffset>4</bitOffset>
35346 <bitWidth>4</bitWidth>
35349 <name>EXTI12
</name>
35350 <description>EXTI
12 configuration bits
</description>
35351 <bitOffset>0</bitOffset>
35352 <bitWidth>4</bitWidth>
35357 <name>SYSCFG_CFGR2
</name>
35358 <displayName>SYSCFG_CFGR2
</displayName>
35359 <description>configuration register
2</description>
35360 <addressOffset>0x18</addressOffset>
35362 <access>read-write
</access>
35363 <resetValue>0x0000</resetValue>
35366 <name>LOCUP_LOCK
</name>
35367 <description>Cortex-M0 LOCKUP bit enable
35369 <bitOffset>0</bitOffset>
35370 <bitWidth>1</bitWidth>
35373 <name>SRAM_PARITY_LOCK
</name>
35374 <description>SRAM parity lock bit
</description>
35375 <bitOffset>1</bitOffset>
35376 <bitWidth>1</bitWidth>
35379 <name>PVD_LOCK
</name>
35380 <description>PVD lock enable bit
</description>
35381 <bitOffset>2</bitOffset>
35382 <bitWidth>1</bitWidth>
35385 <name>BYP_ADD_PAR
</name>
35386 <description>Bypass address bit
29 in parity
35387 calculation
</description>
35388 <bitOffset>4</bitOffset>
35389 <bitWidth>1</bitWidth>
35392 <name>SRAM_PEF
</name>
35393 <description>SRAM parity flag
</description>
35394 <bitOffset>8</bitOffset>
35395 <bitWidth>1</bitWidth>
35400 <name>SYSCFG_RCR
</name>
35401 <displayName>SYSCFG_RCR
</displayName>
35402 <description>CCM SRAM protection register
</description>
35403 <addressOffset>0x4</addressOffset>
35405 <access>read-write
</access>
35406 <resetValue>0x0000</resetValue>
35409 <name>PAGE0_WP
</name>
35410 <description>CCM SRAM page write protection
35412 <bitOffset>0</bitOffset>
35413 <bitWidth>1</bitWidth>
35416 <name>PAGE1_WP
</name>
35417 <description>CCM SRAM page write protection
35419 <bitOffset>1</bitOffset>
35420 <bitWidth>1</bitWidth>
35423 <name>PAGE2_WP
</name>
35424 <description>CCM SRAM page write protection
35426 <bitOffset>2</bitOffset>
35427 <bitWidth>1</bitWidth>
35430 <name>PAGE3_WP
</name>
35431 <description>CCM SRAM page write protection
35433 <bitOffset>3</bitOffset>
35434 <bitWidth>1</bitWidth>
35437 <name>PAGE4_WP
</name>
35438 <description>CCM SRAM page write protection
35440 <bitOffset>4</bitOffset>
35441 <bitWidth>1</bitWidth>
35444 <name>PAGE5_WP
</name>
35445 <description>CCM SRAM page write protection
35447 <bitOffset>5</bitOffset>
35448 <bitWidth>1</bitWidth>
35451 <name>PAGE6_WP
</name>
35452 <description>CCM SRAM page write protection
35454 <bitOffset>6</bitOffset>
35455 <bitWidth>1</bitWidth>
35458 <name>PAGE7_WP
</name>
35459 <description>CCM SRAM page write protection
35461 <bitOffset>7</bitOffset>
35462 <bitWidth>1</bitWidth>
35467 <name>COMP1_CSR
</name>
35468 <displayName>COMP1_CSR
</displayName>
35469 <description>control and status register
</description>
35470 <addressOffset>0x1C</addressOffset>
35472 <resetValue>0x0000</resetValue>
35475 <name>COMP1EN
</name>
35476 <description>Comparator
1 enable
</description>
35477 <bitOffset>0</bitOffset>
35478 <bitWidth>1</bitWidth>
35479 <access>read-write
</access>
35482 <name>COMP1_INP_DAC
</name>
35483 <description>COMP1_INP_DAC
</description>
35484 <bitOffset>1</bitOffset>
35485 <bitWidth>1</bitWidth>
35486 <access>read-write
</access>
35489 <name>COMP1MODE
</name>
35490 <description>Comparator
1 mode
</description>
35491 <bitOffset>2</bitOffset>
35492 <bitWidth>2</bitWidth>
35493 <access>read-write
</access>
35496 <name>COMP1INSEL
</name>
35497 <description>Comparator
1 inverting input
35498 selection
</description>
35499 <bitOffset>4</bitOffset>
35500 <bitWidth>3</bitWidth>
35501 <access>read-write
</access>
35504 <name>COMP1_OUT_SEL
</name>
35505 <description>Comparator
1 output
35506 selection
</description>
35507 <bitOffset>10</bitOffset>
35508 <bitWidth>4</bitWidth>
35509 <access>read-write
</access>
35512 <name>COMP1POL
</name>
35513 <description>Comparator
1 output
35514 polarity
</description>
35515 <bitOffset>15</bitOffset>
35516 <bitWidth>1</bitWidth>
35517 <access>read-write
</access>
35520 <name>COMP1HYST
</name>
35521 <description>Comparator
1 hysteresis
</description>
35522 <bitOffset>16</bitOffset>
35523 <bitWidth>2</bitWidth>
35524 <access>read-write
</access>
35527 <name>COMP1_BLANKING
</name>
35528 <description>Comparator
1 blanking
35529 source
</description>
35530 <bitOffset>18</bitOffset>
35531 <bitWidth>3</bitWidth>
35532 <access>read-write
</access>
35535 <name>COMP1OUT
</name>
35536 <description>Comparator
1 output
</description>
35537 <bitOffset>30</bitOffset>
35538 <bitWidth>1</bitWidth>
35539 <access>read-only
</access>
35542 <name>COMP1LOCK
</name>
35543 <description>Comparator
1 lock
</description>
35544 <bitOffset>31</bitOffset>
35545 <bitWidth>1</bitWidth>
35546 <access>read-write
</access>
35551 <name>COMP2_CSR
</name>
35552 <displayName>COMP2_CSR
</displayName>
35553 <description>control and status register
</description>
35554 <addressOffset>0x20</addressOffset>
35556 <access>read-write
</access>
35557 <resetValue>0x0000</resetValue>
35560 <name>COMP2EN
</name>
35561 <description>Comparator
2 enable
</description>
35562 <bitOffset>0</bitOffset>
35563 <bitWidth>1</bitWidth>
35566 <name>COMP2MODE
</name>
35567 <description>Comparator
2 mode
</description>
35568 <bitOffset>2</bitOffset>
35569 <bitWidth>2</bitWidth>
35572 <name>COMP2INSEL
</name>
35573 <description>Comparator
2 inverting input
35574 selection
</description>
35575 <bitOffset>4</bitOffset>
35576 <bitWidth>3</bitWidth>
35579 <name>COMP2INPSEL
</name>
35580 <description>Comparator
2 non inverted input
35581 selection
</description>
35582 <bitOffset>7</bitOffset>
35583 <bitWidth>1</bitWidth>
35586 <name>COMP2INMSEL
</name>
35587 <description>Comparator
1inverting input
35588 selection
</description>
35589 <bitOffset>9</bitOffset>
35590 <bitWidth>1</bitWidth>
35593 <name>COMP2_OUT_SEL
</name>
35594 <description>Comparator
2 output
35595 selection
</description>
35596 <bitOffset>10</bitOffset>
35597 <bitWidth>4</bitWidth>
35600 <name>COMP2POL
</name>
35601 <description>Comparator
2 output
35602 polarity
</description>
35603 <bitOffset>15</bitOffset>
35604 <bitWidth>1</bitWidth>
35607 <name>COMP2HYST
</name>
35608 <description>Comparator
2 hysteresis
</description>
35609 <bitOffset>16</bitOffset>
35610 <bitWidth>2</bitWidth>
35613 <name>COMP2_BLANKING
</name>
35614 <description>Comparator
2 blanking
35615 source
</description>
35616 <bitOffset>18</bitOffset>
35617 <bitWidth>3</bitWidth>
35620 <name>COMP2LOCK
</name>
35621 <description>Comparator
2 lock
</description>
35622 <bitOffset>31</bitOffset>
35623 <bitWidth>1</bitWidth>
35628 <name>COMP3_CSR
</name>
35629 <displayName>COMP3_CSR
</displayName>
35630 <description>control and status register
</description>
35631 <addressOffset>0x24</addressOffset>
35633 <resetValue>0x0000</resetValue>
35636 <name>COMP3EN
</name>
35637 <description>Comparator
3 enable
</description>
35638 <bitOffset>0</bitOffset>
35639 <bitWidth>1</bitWidth>
35640 <access>read-write
</access>
35643 <name>COMP3MODE
</name>
35644 <description>Comparator
3 mode
</description>
35645 <bitOffset>2</bitOffset>
35646 <bitWidth>2</bitWidth>
35647 <access>read-write
</access>
35650 <name>COMP3INSEL
</name>
35651 <description>Comparator
3 inverting input
35652 selection
</description>
35653 <bitOffset>4</bitOffset>
35654 <bitWidth>3</bitWidth>
35655 <access>read-write
</access>
35658 <name>COMP3INPSEL
</name>
35659 <description>Comparator
3 non inverted input
35660 selection
</description>
35661 <bitOffset>7</bitOffset>
35662 <bitWidth>1</bitWidth>
35663 <access>read-write
</access>
35666 <name>COMP3_OUT_SEL
</name>
35667 <description>Comparator
3 output
35668 selection
</description>
35669 <bitOffset>10</bitOffset>
35670 <bitWidth>4</bitWidth>
35671 <access>read-write
</access>
35674 <name>COMP3POL
</name>
35675 <description>Comparator
3 output
35676 polarity
</description>
35677 <bitOffset>15</bitOffset>
35678 <bitWidth>1</bitWidth>
35679 <access>read-write
</access>
35682 <name>COMP3HYST
</name>
35683 <description>Comparator
3 hysteresis
</description>
35684 <bitOffset>16</bitOffset>
35685 <bitWidth>2</bitWidth>
35686 <access>read-write
</access>
35689 <name>COMP3_BLANKING
</name>
35690 <description>Comparator
3 blanking
35691 source
</description>
35692 <bitOffset>18</bitOffset>
35693 <bitWidth>3</bitWidth>
35694 <access>read-write
</access>
35697 <name>COMP3OUT
</name>
35698 <description>Comparator
3 output
</description>
35699 <bitOffset>30</bitOffset>
35700 <bitWidth>1</bitWidth>
35701 <access>read-only
</access>
35704 <name>COMP3LOCK
</name>
35705 <description>Comparator
3 lock
</description>
35706 <bitOffset>31</bitOffset>
35707 <bitWidth>1</bitWidth>
35708 <access>read-write
</access>
35713 <name>COMP4_CSR
</name>
35714 <displayName>COMP4_CSR
</displayName>
35715 <description>control and status register
</description>
35716 <addressOffset>0x28</addressOffset>
35718 <resetValue>0x0000</resetValue>
35721 <name>COMP4EN
</name>
35722 <description>Comparator
4 enable
</description>
35723 <bitOffset>0</bitOffset>
35724 <bitWidth>1</bitWidth>
35725 <access>read-write
</access>
35728 <name>COMP4MODE
</name>
35729 <description>Comparator
4 mode
</description>
35730 <bitOffset>2</bitOffset>
35731 <bitWidth>2</bitWidth>
35732 <access>read-write
</access>
35735 <name>COMP4INSEL
</name>
35736 <description>Comparator
4 inverting input
35737 selection
</description>
35738 <bitOffset>4</bitOffset>
35739 <bitWidth>3</bitWidth>
35740 <access>read-write
</access>
35743 <name>COMP4INPSEL
</name>
35744 <description>Comparator
4 non inverted input
35745 selection
</description>
35746 <bitOffset>7</bitOffset>
35747 <bitWidth>1</bitWidth>
35748 <access>read-write
</access>
35751 <name>COM4WINMODE
</name>
35752 <description>Comparator
4 window mode
</description>
35753 <bitOffset>9</bitOffset>
35754 <bitWidth>1</bitWidth>
35755 <access>read-write
</access>
35758 <name>COMP4_OUT_SEL
</name>
35759 <description>Comparator
4 output
35760 selection
</description>
35761 <bitOffset>10</bitOffset>
35762 <bitWidth>4</bitWidth>
35763 <access>read-write
</access>
35766 <name>COMP4POL
</name>
35767 <description>Comparator
4 output
35768 polarity
</description>
35769 <bitOffset>15</bitOffset>
35770 <bitWidth>1</bitWidth>
35771 <access>read-write
</access>
35774 <name>COMP4HYST
</name>
35775 <description>Comparator
4 hysteresis
</description>
35776 <bitOffset>16</bitOffset>
35777 <bitWidth>2</bitWidth>
35778 <access>read-write
</access>
35781 <name>COMP4_BLANKING
</name>
35782 <description>Comparator
4 blanking
35783 source
</description>
35784 <bitOffset>18</bitOffset>
35785 <bitWidth>3</bitWidth>
35786 <access>read-write
</access>
35789 <name>COMP4OUT
</name>
35790 <description>Comparator
4 output
</description>
35791 <bitOffset>30</bitOffset>
35792 <bitWidth>1</bitWidth>
35793 <access>read-only
</access>
35796 <name>COMP4LOCK
</name>
35797 <description>Comparator
4 lock
</description>
35798 <bitOffset>31</bitOffset>
35799 <bitWidth>1</bitWidth>
35800 <access>read-write
</access>
35805 <name>COMP5_CSR
</name>
35806 <displayName>COMP5_CSR
</displayName>
35807 <description>control and status register
</description>
35808 <addressOffset>0x2C</addressOffset>
35810 <resetValue>0x0000</resetValue>
35813 <name>COMP5EN
</name>
35814 <description>Comparator
5 enable
</description>
35815 <bitOffset>0</bitOffset>
35816 <bitWidth>1</bitWidth>
35817 <access>read-write
</access>
35820 <name>COMP5MODE
</name>
35821 <description>Comparator
5 mode
</description>
35822 <bitOffset>2</bitOffset>
35823 <bitWidth>2</bitWidth>
35824 <access>read-write
</access>
35827 <name>COMP5INSEL
</name>
35828 <description>Comparator
5 inverting input
35829 selection
</description>
35830 <bitOffset>4</bitOffset>
35831 <bitWidth>3</bitWidth>
35832 <access>read-write
</access>
35835 <name>COMP5INPSEL
</name>
35836 <description>Comparator
5 non inverted input
35837 selection
</description>
35838 <bitOffset>7</bitOffset>
35839 <bitWidth>1</bitWidth>
35840 <access>read-write
</access>
35843 <name>COMP5_OUT_SEL
</name>
35844 <description>Comparator
5 output
35845 selection
</description>
35846 <bitOffset>10</bitOffset>
35847 <bitWidth>4</bitWidth>
35848 <access>read-write
</access>
35851 <name>COMP5POL
</name>
35852 <description>Comparator
5 output
35853 polarity
</description>
35854 <bitOffset>15</bitOffset>
35855 <bitWidth>1</bitWidth>
35856 <access>read-write
</access>
35859 <name>COMP5HYST
</name>
35860 <description>Comparator
5 hysteresis
</description>
35861 <bitOffset>16</bitOffset>
35862 <bitWidth>2</bitWidth>
35863 <access>read-write
</access>
35866 <name>COMP5_BLANKING
</name>
35867 <description>Comparator
5 blanking
35868 source
</description>
35869 <bitOffset>18</bitOffset>
35870 <bitWidth>3</bitWidth>
35871 <access>read-write
</access>
35874 <name>COMP5OUT
</name>
35875 <description>Comparator51 output
</description>
35876 <bitOffset>30</bitOffset>
35877 <bitWidth>1</bitWidth>
35878 <access>read-only
</access>
35881 <name>COMP5LOCK
</name>
35882 <description>Comparator
5 lock
</description>
35883 <bitOffset>31</bitOffset>
35884 <bitWidth>1</bitWidth>
35885 <access>read-write
</access>
35890 <name>COMP6_CSR
</name>
35891 <displayName>COMP6_CSR
</displayName>
35892 <description>control and status register
</description>
35893 <addressOffset>0x30</addressOffset>
35895 <resetValue>0x0000</resetValue>
35898 <name>COMP6EN
</name>
35899 <description>Comparator
6 enable
</description>
35900 <bitOffset>0</bitOffset>
35901 <bitWidth>1</bitWidth>
35902 <access>read-write
</access>
35905 <name>COMP6MODE
</name>
35906 <description>Comparator
6 mode
</description>
35907 <bitOffset>2</bitOffset>
35908 <bitWidth>2</bitWidth>
35909 <access>read-write
</access>
35912 <name>COMP6INSEL
</name>
35913 <description>Comparator
6 inverting input
35914 selection
</description>
35915 <bitOffset>4</bitOffset>
35916 <bitWidth>3</bitWidth>
35917 <access>read-write
</access>
35920 <name>COMP6INPSEL
</name>
35921 <description>Comparator
6 non inverted input
35922 selection
</description>
35923 <bitOffset>7</bitOffset>
35924 <bitWidth>1</bitWidth>
35925 <access>read-write
</access>
35928 <name>COM6WINMODE
</name>
35929 <description>Comparator
6 window mode
</description>
35930 <bitOffset>9</bitOffset>
35931 <bitWidth>1</bitWidth>
35932 <access>read-write
</access>
35935 <name>COMP6_OUT_SEL
</name>
35936 <description>Comparator
6 output
35937 selection
</description>
35938 <bitOffset>10</bitOffset>
35939 <bitWidth>4</bitWidth>
35940 <access>read-write
</access>
35943 <name>COMP6POL
</name>
35944 <description>Comparator
6 output
35945 polarity
</description>
35946 <bitOffset>15</bitOffset>
35947 <bitWidth>1</bitWidth>
35948 <access>read-write
</access>
35951 <name>COMP6HYST
</name>
35952 <description>Comparator
6 hysteresis
</description>
35953 <bitOffset>16</bitOffset>
35954 <bitWidth>2</bitWidth>
35955 <access>read-write
</access>
35958 <name>COMP6_BLANKING
</name>
35959 <description>Comparator
6 blanking
35960 source
</description>
35961 <bitOffset>18</bitOffset>
35962 <bitWidth>3</bitWidth>
35963 <access>read-write
</access>
35966 <name>COMP6OUT
</name>
35967 <description>Comparator
6 output
</description>
35968 <bitOffset>30</bitOffset>
35969 <bitWidth>1</bitWidth>
35970 <access>read-only
</access>
35973 <name>COMP6LOCK
</name>
35974 <description>Comparator
6 lock
</description>
35975 <bitOffset>31</bitOffset>
35976 <bitWidth>1</bitWidth>
35977 <access>read-write
</access>
35982 <name>COMP7_CSR
</name>
35983 <displayName>COMP7_CSR
</displayName>
35984 <description>control and status register
</description>
35985 <addressOffset>0x34</addressOffset>
35987 <resetValue>0x0000</resetValue>
35990 <name>COMP7EN
</name>
35991 <description>Comparator
7 enable
</description>
35992 <bitOffset>0</bitOffset>
35993 <bitWidth>1</bitWidth>
35994 <access>read-write
</access>
35997 <name>COMP7MODE
</name>
35998 <description>Comparator
7 mode
</description>
35999 <bitOffset>2</bitOffset>
36000 <bitWidth>2</bitWidth>
36001 <access>read-write
</access>
36004 <name>COMP7INSEL
</name>
36005 <description>Comparator
7 inverting input
36006 selection
</description>
36007 <bitOffset>4</bitOffset>
36008 <bitWidth>3</bitWidth>
36009 <access>read-write
</access>
36012 <name>COMP7INPSEL
</name>
36013 <description>Comparator
7 non inverted input
36014 selection
</description>
36015 <bitOffset>7</bitOffset>
36016 <bitWidth>1</bitWidth>
36017 <access>read-write
</access>
36020 <name>COMP7_OUT_SEL
</name>
36021 <description>Comparator
7 output
36022 selection
</description>
36023 <bitOffset>10</bitOffset>
36024 <bitWidth>4</bitWidth>
36025 <access>read-write
</access>
36028 <name>COMP7POL
</name>
36029 <description>Comparator
7 output
36030 polarity
</description>
36031 <bitOffset>15</bitOffset>
36032 <bitWidth>1</bitWidth>
36033 <access>read-write
</access>
36036 <name>COMP7HYST
</name>
36037 <description>Comparator
7 hysteresis
</description>
36038 <bitOffset>16</bitOffset>
36039 <bitWidth>2</bitWidth>
36040 <access>read-write
</access>
36043 <name>COMP7_BLANKING
</name>
36044 <description>Comparator
7 blanking
36045 source
</description>
36046 <bitOffset>18</bitOffset>
36047 <bitWidth>3</bitWidth>
36048 <access>read-write
</access>
36051 <name>COMP7OUT
</name>
36052 <description>Comparator
7 output
</description>
36053 <bitOffset>30</bitOffset>
36054 <bitWidth>1</bitWidth>
36055 <access>read-only
</access>
36058 <name>COMP7LOCK
</name>
36059 <description>Comparator
7 lock
</description>
36060 <bitOffset>31</bitOffset>
36061 <bitWidth>1</bitWidth>
36062 <access>read-write
</access>
36067 <name>OPAMP1_CSR
</name>
36068 <displayName>OPAMP1_CSR
</displayName>
36069 <description>control register
</description>
36070 <addressOffset>0x38</addressOffset>
36072 <resetValue>0x0000</resetValue>
36075 <name>OPAMP1_EN
</name>
36076 <description>OPAMP1 enable
</description>
36077 <bitOffset>0</bitOffset>
36078 <bitWidth>1</bitWidth>
36079 <access>read-write
</access>
36082 <name>FORCE_VP
</name>
36083 <description>FORCE_VP
</description>
36084 <bitOffset>1</bitOffset>
36085 <bitWidth>1</bitWidth>
36086 <access>read-write
</access>
36089 <name>VP_SEL
</name>
36090 <description>OPAMP1 Non inverting input
36091 selection
</description>
36092 <bitOffset>2</bitOffset>
36093 <bitWidth>2</bitWidth>
36094 <access>read-write
</access>
36097 <name>VM_SEL
</name>
36098 <description>OPAMP1 inverting input
36099 selection
</description>
36100 <bitOffset>5</bitOffset>
36101 <bitWidth>2</bitWidth>
36102 <access>read-write
</access>
36105 <name>TCM_EN
</name>
36106 <description>Timer controlled Mux mode
36107 enable
</description>
36108 <bitOffset>7</bitOffset>
36109 <bitWidth>1</bitWidth>
36110 <access>read-write
</access>
36113 <name>VMS_SEL
</name>
36114 <description>OPAMP1 inverting input secondary
36115 selection
</description>
36116 <bitOffset>8</bitOffset>
36117 <bitWidth>1</bitWidth>
36118 <access>read-write
</access>
36121 <name>VPS_SEL
</name>
36122 <description>OPAMP1 Non inverting input secondary
36123 selection
</description>
36124 <bitOffset>9</bitOffset>
36125 <bitWidth>2</bitWidth>
36126 <access>read-write
</access>
36130 <description>Calibration mode enable
</description>
36131 <bitOffset>11</bitOffset>
36132 <bitWidth>1</bitWidth>
36133 <access>read-write
</access>
36136 <name>CALSEL
</name>
36137 <description>Calibration selection
</description>
36138 <bitOffset>12</bitOffset>
36139 <bitWidth>2</bitWidth>
36140 <access>read-write
</access>
36143 <name>PGA_GAIN
</name>
36144 <description>Gain in PGA mode
</description>
36145 <bitOffset>14</bitOffset>
36146 <bitWidth>4</bitWidth>
36147 <access>read-write
</access>
36150 <name>USER_TRIM
</name>
36151 <description>User trimming enable
</description>
36152 <bitOffset>18</bitOffset>
36153 <bitWidth>1</bitWidth>
36154 <access>read-write
</access>
36157 <name>TRIMOFFSETP
</name>
36158 <description>Offset trimming value
36159 (PMOS)
</description>
36160 <bitOffset>19</bitOffset>
36161 <bitWidth>5</bitWidth>
36162 <access>read-write
</access>
36165 <name>TRIMOFFSETN
</name>
36166 <description>Offset trimming value
36167 (NMOS)
</description>
36168 <bitOffset>24</bitOffset>
36169 <bitWidth>5</bitWidth>
36170 <access>read-write
</access>
36173 <name>TSTREF
</name>
36174 <description>TSTREF
</description>
36175 <bitOffset>29</bitOffset>
36176 <bitWidth>1</bitWidth>
36177 <access>read-write
</access>
36180 <name>OUTCAL
</name>
36181 <description>OPAMP
1 ouput status flag
</description>
36182 <bitOffset>30</bitOffset>
36183 <bitWidth>1</bitWidth>
36184 <access>read-only
</access>
36188 <description>OPAMP
1 lock
</description>
36189 <bitOffset>31</bitOffset>
36190 <bitWidth>1</bitWidth>
36191 <access>read-write
</access>
36196 <name>OPAMP2_CSR
</name>
36197 <displayName>OPAMP2_CSR
</displayName>
36198 <description>control register
</description>
36199 <addressOffset>0x3C</addressOffset>
36201 <resetValue>0x0000</resetValue>
36204 <name>OPAMP2EN
</name>
36205 <description>OPAMP2 enable
</description>
36206 <bitOffset>0</bitOffset>
36207 <bitWidth>1</bitWidth>
36208 <access>read-write
</access>
36211 <name>FORCE_VP
</name>
36212 <description>FORCE_VP
</description>
36213 <bitOffset>1</bitOffset>
36214 <bitWidth>1</bitWidth>
36215 <access>read-write
</access>
36218 <name>VP_SEL
</name>
36219 <description>OPAMP2 Non inverting input
36220 selection
</description>
36221 <bitOffset>2</bitOffset>
36222 <bitWidth>2</bitWidth>
36223 <access>read-write
</access>
36226 <name>VM_SEL
</name>
36227 <description>OPAMP2 inverting input
36228 selection
</description>
36229 <bitOffset>5</bitOffset>
36230 <bitWidth>2</bitWidth>
36231 <access>read-write
</access>
36234 <name>TCM_EN
</name>
36235 <description>Timer controlled Mux mode
36236 enable
</description>
36237 <bitOffset>7</bitOffset>
36238 <bitWidth>1</bitWidth>
36239 <access>read-write
</access>
36242 <name>VMS_SEL
</name>
36243 <description>OPAMP2 inverting input secondary
36244 selection
</description>
36245 <bitOffset>8</bitOffset>
36246 <bitWidth>1</bitWidth>
36247 <access>read-write
</access>
36250 <name>VPS_SEL
</name>
36251 <description>OPAMP2 Non inverting input secondary
36252 selection
</description>
36253 <bitOffset>9</bitOffset>
36254 <bitWidth>2</bitWidth>
36255 <access>read-write
</access>
36259 <description>Calibration mode enable
</description>
36260 <bitOffset>11</bitOffset>
36261 <bitWidth>1</bitWidth>
36262 <access>read-write
</access>
36265 <name>CAL_SEL
</name>
36266 <description>Calibration selection
</description>
36267 <bitOffset>12</bitOffset>
36268 <bitWidth>2</bitWidth>
36269 <access>read-write
</access>
36272 <name>PGA_GAIN
</name>
36273 <description>Gain in PGA mode
</description>
36274 <bitOffset>14</bitOffset>
36275 <bitWidth>4</bitWidth>
36276 <access>read-write
</access>
36279 <name>USER_TRIM
</name>
36280 <description>User trimming enable
</description>
36281 <bitOffset>18</bitOffset>
36282 <bitWidth>1</bitWidth>
36283 <access>read-write
</access>
36286 <name>TRIMOFFSETP
</name>
36287 <description>Offset trimming value
36288 (PMOS)
</description>
36289 <bitOffset>19</bitOffset>
36290 <bitWidth>5</bitWidth>
36291 <access>read-write
</access>
36294 <name>TRIMOFFSETN
</name>
36295 <description>Offset trimming value
36296 (NMOS)
</description>
36297 <bitOffset>24</bitOffset>
36298 <bitWidth>5</bitWidth>
36299 <access>read-write
</access>
36302 <name>TSTREF
</name>
36303 <description>TSTREF
</description>
36304 <bitOffset>29</bitOffset>
36305 <bitWidth>1</bitWidth>
36306 <access>read-write
</access>
36309 <name>OUTCAL
</name>
36310 <description>OPAMP
2 ouput status flag
</description>
36311 <bitOffset>30</bitOffset>
36312 <bitWidth>1</bitWidth>
36313 <access>read-only
</access>
36317 <description>OPAMP
2 lock
</description>
36318 <bitOffset>31</bitOffset>
36319 <bitWidth>1</bitWidth>
36320 <access>read-write
</access>
36325 <name>OPAMP3_CSR
</name>
36326 <displayName>OPAMP3_CSR
</displayName>
36327 <description>control register
</description>
36328 <addressOffset>0x40</addressOffset>
36330 <resetValue>0x0000</resetValue>
36333 <name>OPAMP3EN
</name>
36334 <description>OPAMP3 enable
</description>
36335 <bitOffset>0</bitOffset>
36336 <bitWidth>1</bitWidth>
36337 <access>read-write
</access>
36340 <name>FORCE_VP
</name>
36341 <description>FORCE_VP
</description>
36342 <bitOffset>1</bitOffset>
36343 <bitWidth>1</bitWidth>
36344 <access>read-write
</access>
36347 <name>VP_SEL
</name>
36348 <description>OPAMP3 Non inverting input
36349 selection
</description>
36350 <bitOffset>2</bitOffset>
36351 <bitWidth>2</bitWidth>
36352 <access>read-write
</access>
36355 <name>VM_SEL
</name>
36356 <description>OPAMP3 inverting input
36357 selection
</description>
36358 <bitOffset>5</bitOffset>
36359 <bitWidth>2</bitWidth>
36360 <access>read-write
</access>
36363 <name>TCM_EN
</name>
36364 <description>Timer controlled Mux mode
36365 enable
</description>
36366 <bitOffset>7</bitOffset>
36367 <bitWidth>1</bitWidth>
36368 <access>read-write
</access>
36371 <name>VMS_SEL
</name>
36372 <description>OPAMP3 inverting input secondary
36373 selection
</description>
36374 <bitOffset>8</bitOffset>
36375 <bitWidth>1</bitWidth>
36376 <access>read-write
</access>
36379 <name>VPS_SEL
</name>
36380 <description>OPAMP3 Non inverting input secondary
36381 selection
</description>
36382 <bitOffset>9</bitOffset>
36383 <bitWidth>2</bitWidth>
36384 <access>read-write
</access>
36388 <description>Calibration mode enable
</description>
36389 <bitOffset>11</bitOffset>
36390 <bitWidth>1</bitWidth>
36391 <access>read-write
</access>
36394 <name>CALSEL
</name>
36395 <description>Calibration selection
</description>
36396 <bitOffset>12</bitOffset>
36397 <bitWidth>2</bitWidth>
36398 <access>read-write
</access>
36401 <name>PGA_GAIN
</name>
36402 <description>Gain in PGA mode
</description>
36403 <bitOffset>14</bitOffset>
36404 <bitWidth>4</bitWidth>
36405 <access>read-write
</access>
36408 <name>USER_TRIM
</name>
36409 <description>User trimming enable
</description>
36410 <bitOffset>18</bitOffset>
36411 <bitWidth>1</bitWidth>
36412 <access>read-write
</access>
36415 <name>TRIMOFFSETP
</name>
36416 <description>Offset trimming value
36417 (PMOS)
</description>
36418 <bitOffset>19</bitOffset>
36419 <bitWidth>5</bitWidth>
36420 <access>read-write
</access>
36423 <name>TRIMOFFSETN
</name>
36424 <description>Offset trimming value
36425 (NMOS)
</description>
36426 <bitOffset>24</bitOffset>
36427 <bitWidth>5</bitWidth>
36428 <access>read-write
</access>
36431 <name>TSTREF
</name>
36432 <description>TSTREF
</description>
36433 <bitOffset>29</bitOffset>
36434 <bitWidth>1</bitWidth>
36435 <access>read-write
</access>
36438 <name>OUTCAL
</name>
36439 <description>OPAMP
3 ouput status flag
</description>
36440 <bitOffset>30</bitOffset>
36441 <bitWidth>1</bitWidth>
36442 <access>read-only
</access>
36446 <description>OPAMP
3 lock
</description>
36447 <bitOffset>31</bitOffset>
36448 <bitWidth>1</bitWidth>
36449 <access>read-write
</access>
36454 <name>OPAMP4_CSR
</name>
36455 <displayName>OPAMP4_CSR
</displayName>
36456 <description>control register
</description>
36457 <addressOffset>0x44</addressOffset>
36459 <resetValue>0x0000</resetValue>
36462 <name>OPAMP4EN
</name>
36463 <description>OPAMP4 enable
</description>
36464 <bitOffset>0</bitOffset>
36465 <bitWidth>1</bitWidth>
36466 <access>read-write
</access>
36469 <name>FORCE_VP
</name>
36470 <description>FORCE_VP
</description>
36471 <bitOffset>1</bitOffset>
36472 <bitWidth>1</bitWidth>
36473 <access>read-write
</access>
36476 <name>VP_SEL
</name>
36477 <description>OPAMP4 Non inverting input
36478 selection
</description>
36479 <bitOffset>2</bitOffset>
36480 <bitWidth>2</bitWidth>
36481 <access>read-write
</access>
36484 <name>VM_SEL
</name>
36485 <description>OPAMP4 inverting input
36486 selection
</description>
36487 <bitOffset>5</bitOffset>
36488 <bitWidth>2</bitWidth>
36489 <access>read-write
</access>
36492 <name>TCM_EN
</name>
36493 <description>Timer controlled Mux mode
36494 enable
</description>
36495 <bitOffset>7</bitOffset>
36496 <bitWidth>1</bitWidth>
36497 <access>read-write
</access>
36500 <name>VMS_SEL
</name>
36501 <description>OPAMP4 inverting input secondary
36502 selection
</description>
36503 <bitOffset>8</bitOffset>
36504 <bitWidth>1</bitWidth>
36505 <access>read-write
</access>
36508 <name>VPS_SEL
</name>
36509 <description>OPAMP4 Non inverting input secondary
36510 selection
</description>
36511 <bitOffset>9</bitOffset>
36512 <bitWidth>2</bitWidth>
36513 <access>read-write
</access>
36517 <description>Calibration mode enable
</description>
36518 <bitOffset>11</bitOffset>
36519 <bitWidth>1</bitWidth>
36520 <access>read-write
</access>
36523 <name>CALSEL
</name>
36524 <description>Calibration selection
</description>
36525 <bitOffset>12</bitOffset>
36526 <bitWidth>2</bitWidth>
36527 <access>read-write
</access>
36530 <name>PGA_GAIN
</name>
36531 <description>Gain in PGA mode
</description>
36532 <bitOffset>14</bitOffset>
36533 <bitWidth>4</bitWidth>
36534 <access>read-write
</access>
36537 <name>USER_TRIM
</name>
36538 <description>User trimming enable
</description>
36539 <bitOffset>18</bitOffset>
36540 <bitWidth>1</bitWidth>
36541 <access>read-write
</access>
36544 <name>TRIMOFFSETP
</name>
36545 <description>Offset trimming value
36546 (PMOS)
</description>
36547 <bitOffset>19</bitOffset>
36548 <bitWidth>5</bitWidth>
36549 <access>read-write
</access>
36552 <name>TRIMOFFSETN
</name>
36553 <description>Offset trimming value
36554 (NMOS)
</description>
36555 <bitOffset>24</bitOffset>
36556 <bitWidth>5</bitWidth>
36557 <access>read-write
</access>
36560 <name>TSTREF
</name>
36561 <description>TSTREF
</description>
36562 <bitOffset>29</bitOffset>
36563 <bitWidth>1</bitWidth>
36564 <access>read-write
</access>
36567 <name>OUTCAL
</name>
36568 <description>OPAMP
4 ouput status flag
</description>
36569 <bitOffset>30</bitOffset>
36570 <bitWidth>1</bitWidth>
36571 <access>read-only
</access>
36575 <description>OPAMP
4 lock
</description>
36576 <bitOffset>31</bitOffset>
36577 <bitWidth>1</bitWidth>
36578 <access>read-write
</access>
36586 <description>Flexible memory controller
</description>
36587 <groupName>FMC
</groupName>
36588 <baseAddress>0xA0000400</baseAddress>
36590 <offset>0x0</offset>
36592 <usage>registers
</usage>
36596 <description>FSMC global interrupt
</description>
36602 <displayName>BCR1
</displayName>
36603 <description>SRAM/NOR-Flash chip-select control register
36605 <addressOffset>0x0</addressOffset>
36607 <access>read-write
</access>
36608 <resetValue>0x000030D0</resetValue>
36611 <name>CCLKEN
</name>
36612 <description>CCLKEN
</description>
36613 <bitOffset>20</bitOffset>
36614 <bitWidth>1</bitWidth>
36617 <name>CBURSTRW
</name>
36618 <description>CBURSTRW
</description>
36619 <bitOffset>19</bitOffset>
36620 <bitWidth>1</bitWidth>
36623 <name>ASYNCWAIT
</name>
36624 <description>ASYNCWAIT
</description>
36625 <bitOffset>15</bitOffset>
36626 <bitWidth>1</bitWidth>
36629 <name>EXTMOD
</name>
36630 <description>EXTMOD
</description>
36631 <bitOffset>14</bitOffset>
36632 <bitWidth>1</bitWidth>
36635 <name>WAITEN
</name>
36636 <description>WAITEN
</description>
36637 <bitOffset>13</bitOffset>
36638 <bitWidth>1</bitWidth>
36642 <description>WREN
</description>
36643 <bitOffset>12</bitOffset>
36644 <bitWidth>1</bitWidth>
36647 <name>WAITCFG
</name>
36648 <description>WAITCFG
</description>
36649 <bitOffset>11</bitOffset>
36650 <bitWidth>1</bitWidth>
36653 <name>WAITPOL
</name>
36654 <description>WAITPOL
</description>
36655 <bitOffset>9</bitOffset>
36656 <bitWidth>1</bitWidth>
36659 <name>BURSTEN
</name>
36660 <description>BURSTEN
</description>
36661 <bitOffset>8</bitOffset>
36662 <bitWidth>1</bitWidth>
36665 <name>FACCEN
</name>
36666 <description>FACCEN
</description>
36667 <bitOffset>6</bitOffset>
36668 <bitWidth>1</bitWidth>
36672 <description>MWID
</description>
36673 <bitOffset>4</bitOffset>
36674 <bitWidth>2</bitWidth>
36678 <description>MTYP
</description>
36679 <bitOffset>2</bitOffset>
36680 <bitWidth>2</bitWidth>
36684 <description>MUXEN
</description>
36685 <bitOffset>1</bitOffset>
36686 <bitWidth>1</bitWidth>
36690 <description>MBKEN
</description>
36691 <bitOffset>0</bitOffset>
36692 <bitWidth>1</bitWidth>
36698 <displayName>BTR1
</displayName>
36699 <description>SRAM/NOR-Flash chip-select timing register
36701 <addressOffset>0x4</addressOffset>
36703 <access>read-write
</access>
36704 <resetValue>0xFFFFFFFF</resetValue>
36707 <name>ACCMOD
</name>
36708 <description>ACCMOD
</description>
36709 <bitOffset>28</bitOffset>
36710 <bitWidth>2</bitWidth>
36713 <name>DATLAT
</name>
36714 <description>DATLAT
</description>
36715 <bitOffset>24</bitOffset>
36716 <bitWidth>4</bitWidth>
36719 <name>CLKDIV
</name>
36720 <description>CLKDIV
</description>
36721 <bitOffset>20</bitOffset>
36722 <bitWidth>4</bitWidth>
36725 <name>BUSTURN
</name>
36726 <description>BUSTURN
</description>
36727 <bitOffset>16</bitOffset>
36728 <bitWidth>4</bitWidth>
36731 <name>DATAST
</name>
36732 <description>DATAST
</description>
36733 <bitOffset>8</bitOffset>
36734 <bitWidth>8</bitWidth>
36737 <name>ADDHLD
</name>
36738 <description>ADDHLD
</description>
36739 <bitOffset>4</bitOffset>
36740 <bitWidth>4</bitWidth>
36743 <name>ADDSET
</name>
36744 <description>ADDSET
</description>
36745 <bitOffset>0</bitOffset>
36746 <bitWidth>4</bitWidth>
36752 <displayName>BCR2
</displayName>
36753 <description>SRAM/NOR-Flash chip-select control register
36755 <addressOffset>0x8</addressOffset>
36757 <access>read-write
</access>
36758 <resetValue>0x000030D0</resetValue>
36761 <name>CBURSTRW
</name>
36762 <description>CBURSTRW
</description>
36763 <bitOffset>19</bitOffset>
36764 <bitWidth>1</bitWidth>
36767 <name>ASYNCWAIT
</name>
36768 <description>ASYNCWAIT
</description>
36769 <bitOffset>15</bitOffset>
36770 <bitWidth>1</bitWidth>
36773 <name>EXTMOD
</name>
36774 <description>EXTMOD
</description>
36775 <bitOffset>14</bitOffset>
36776 <bitWidth>1</bitWidth>
36779 <name>WAITEN
</name>
36780 <description>WAITEN
</description>
36781 <bitOffset>13</bitOffset>
36782 <bitWidth>1</bitWidth>
36786 <description>WREN
</description>
36787 <bitOffset>12</bitOffset>
36788 <bitWidth>1</bitWidth>
36791 <name>WAITCFG
</name>
36792 <description>WAITCFG
</description>
36793 <bitOffset>11</bitOffset>
36794 <bitWidth>1</bitWidth>
36797 <name>WRAPMOD
</name>
36798 <description>WRAPMOD
</description>
36799 <bitOffset>10</bitOffset>
36800 <bitWidth>1</bitWidth>
36803 <name>WAITPOL
</name>
36804 <description>WAITPOL
</description>
36805 <bitOffset>9</bitOffset>
36806 <bitWidth>1</bitWidth>
36809 <name>BURSTEN
</name>
36810 <description>BURSTEN
</description>
36811 <bitOffset>8</bitOffset>
36812 <bitWidth>1</bitWidth>
36815 <name>FACCEN
</name>
36816 <description>FACCEN
</description>
36817 <bitOffset>6</bitOffset>
36818 <bitWidth>1</bitWidth>
36822 <description>MWID
</description>
36823 <bitOffset>4</bitOffset>
36824 <bitWidth>2</bitWidth>
36828 <description>MTYP
</description>
36829 <bitOffset>2</bitOffset>
36830 <bitWidth>2</bitWidth>
36834 <description>MUXEN
</description>
36835 <bitOffset>1</bitOffset>
36836 <bitWidth>1</bitWidth>
36840 <description>MBKEN
</description>
36841 <bitOffset>0</bitOffset>
36842 <bitWidth>1</bitWidth>
36848 <displayName>BTR2
</displayName>
36849 <description>SRAM/NOR-Flash chip-select timing register
36851 <addressOffset>0xC</addressOffset>
36853 <access>read-write
</access>
36854 <resetValue>0xFFFFFFFF</resetValue>
36857 <name>ACCMOD
</name>
36858 <description>ACCMOD
</description>
36859 <bitOffset>28</bitOffset>
36860 <bitWidth>2</bitWidth>
36863 <name>DATLAT
</name>
36864 <description>DATLAT
</description>
36865 <bitOffset>24</bitOffset>
36866 <bitWidth>4</bitWidth>
36869 <name>CLKDIV
</name>
36870 <description>CLKDIV
</description>
36871 <bitOffset>20</bitOffset>
36872 <bitWidth>4</bitWidth>
36875 <name>BUSTURN
</name>
36876 <description>BUSTURN
</description>
36877 <bitOffset>16</bitOffset>
36878 <bitWidth>4</bitWidth>
36881 <name>DATAST
</name>
36882 <description>DATAST
</description>
36883 <bitOffset>8</bitOffset>
36884 <bitWidth>8</bitWidth>
36887 <name>ADDHLD
</name>
36888 <description>ADDHLD
</description>
36889 <bitOffset>4</bitOffset>
36890 <bitWidth>4</bitWidth>
36893 <name>ADDSET
</name>
36894 <description>ADDSET
</description>
36895 <bitOffset>0</bitOffset>
36896 <bitWidth>4</bitWidth>
36902 <displayName>BCR3
</displayName>
36903 <description>SRAM/NOR-Flash chip-select control register
36905 <addressOffset>0x10</addressOffset>
36907 <access>read-write
</access>
36908 <resetValue>0x000030D0</resetValue>
36911 <name>CBURSTRW
</name>
36912 <description>CBURSTRW
</description>
36913 <bitOffset>19</bitOffset>
36914 <bitWidth>1</bitWidth>
36917 <name>ASYNCWAIT
</name>
36918 <description>ASYNCWAIT
</description>
36919 <bitOffset>15</bitOffset>
36920 <bitWidth>1</bitWidth>
36923 <name>EXTMOD
</name>
36924 <description>EXTMOD
</description>
36925 <bitOffset>14</bitOffset>
36926 <bitWidth>1</bitWidth>
36929 <name>WAITEN
</name>
36930 <description>WAITEN
</description>
36931 <bitOffset>13</bitOffset>
36932 <bitWidth>1</bitWidth>
36936 <description>WREN
</description>
36937 <bitOffset>12</bitOffset>
36938 <bitWidth>1</bitWidth>
36941 <name>WAITCFG
</name>
36942 <description>WAITCFG
</description>
36943 <bitOffset>11</bitOffset>
36944 <bitWidth>1</bitWidth>
36947 <name>WRAPMOD
</name>
36948 <description>WRAPMOD
</description>
36949 <bitOffset>10</bitOffset>
36950 <bitWidth>1</bitWidth>
36953 <name>WAITPOL
</name>
36954 <description>WAITPOL
</description>
36955 <bitOffset>9</bitOffset>
36956 <bitWidth>1</bitWidth>
36959 <name>BURSTEN
</name>
36960 <description>BURSTEN
</description>
36961 <bitOffset>8</bitOffset>
36962 <bitWidth>1</bitWidth>
36965 <name>FACCEN
</name>
36966 <description>FACCEN
</description>
36967 <bitOffset>6</bitOffset>
36968 <bitWidth>1</bitWidth>
36972 <description>MWID
</description>
36973 <bitOffset>4</bitOffset>
36974 <bitWidth>2</bitWidth>
36978 <description>MTYP
</description>
36979 <bitOffset>2</bitOffset>
36980 <bitWidth>2</bitWidth>
36984 <description>MUXEN
</description>
36985 <bitOffset>1</bitOffset>
36986 <bitWidth>1</bitWidth>
36990 <description>MBKEN
</description>
36991 <bitOffset>0</bitOffset>
36992 <bitWidth>1</bitWidth>
36998 <displayName>BTR3
</displayName>
36999 <description>SRAM/NOR-Flash chip-select timing register
37001 <addressOffset>0x14</addressOffset>
37003 <access>read-write
</access>
37004 <resetValue>0xFFFFFFFF</resetValue>
37007 <name>ACCMOD
</name>
37008 <description>ACCMOD
</description>
37009 <bitOffset>28</bitOffset>
37010 <bitWidth>2</bitWidth>
37013 <name>DATLAT
</name>
37014 <description>DATLAT
</description>
37015 <bitOffset>24</bitOffset>
37016 <bitWidth>4</bitWidth>
37019 <name>CLKDIV
</name>
37020 <description>CLKDIV
</description>
37021 <bitOffset>20</bitOffset>
37022 <bitWidth>4</bitWidth>
37025 <name>BUSTURN
</name>
37026 <description>BUSTURN
</description>
37027 <bitOffset>16</bitOffset>
37028 <bitWidth>4</bitWidth>
37031 <name>DATAST
</name>
37032 <description>DATAST
</description>
37033 <bitOffset>8</bitOffset>
37034 <bitWidth>8</bitWidth>
37037 <name>ADDHLD
</name>
37038 <description>ADDHLD
</description>
37039 <bitOffset>4</bitOffset>
37040 <bitWidth>4</bitWidth>
37043 <name>ADDSET
</name>
37044 <description>ADDSET
</description>
37045 <bitOffset>0</bitOffset>
37046 <bitWidth>4</bitWidth>
37052 <displayName>BCR4
</displayName>
37053 <description>SRAM/NOR-Flash chip-select control register
37055 <addressOffset>0x18</addressOffset>
37057 <access>read-write
</access>
37058 <resetValue>0x000030D0</resetValue>
37061 <name>CBURSTRW
</name>
37062 <description>CBURSTRW
</description>
37063 <bitOffset>19</bitOffset>
37064 <bitWidth>1</bitWidth>
37067 <name>ASYNCWAIT
</name>
37068 <description>ASYNCWAIT
</description>
37069 <bitOffset>15</bitOffset>
37070 <bitWidth>1</bitWidth>
37073 <name>EXTMOD
</name>
37074 <description>EXTMOD
</description>
37075 <bitOffset>14</bitOffset>
37076 <bitWidth>1</bitWidth>
37079 <name>WAITEN
</name>
37080 <description>WAITEN
</description>
37081 <bitOffset>13</bitOffset>
37082 <bitWidth>1</bitWidth>
37086 <description>WREN
</description>
37087 <bitOffset>12</bitOffset>
37088 <bitWidth>1</bitWidth>
37091 <name>WAITCFG
</name>
37092 <description>WAITCFG
</description>
37093 <bitOffset>11</bitOffset>
37094 <bitWidth>1</bitWidth>
37097 <name>WRAPMOD
</name>
37098 <description>WRAPMOD
</description>
37099 <bitOffset>10</bitOffset>
37100 <bitWidth>1</bitWidth>
37103 <name>WAITPOL
</name>
37104 <description>WAITPOL
</description>
37105 <bitOffset>9</bitOffset>
37106 <bitWidth>1</bitWidth>
37109 <name>BURSTEN
</name>
37110 <description>BURSTEN
</description>
37111 <bitOffset>8</bitOffset>
37112 <bitWidth>1</bitWidth>
37115 <name>FACCEN
</name>
37116 <description>FACCEN
</description>
37117 <bitOffset>6</bitOffset>
37118 <bitWidth>1</bitWidth>
37122 <description>MWID
</description>
37123 <bitOffset>4</bitOffset>
37124 <bitWidth>2</bitWidth>
37128 <description>MTYP
</description>
37129 <bitOffset>2</bitOffset>
37130 <bitWidth>2</bitWidth>
37134 <description>MUXEN
</description>
37135 <bitOffset>1</bitOffset>
37136 <bitWidth>1</bitWidth>
37140 <description>MBKEN
</description>
37141 <bitOffset>0</bitOffset>
37142 <bitWidth>1</bitWidth>
37148 <displayName>BTR4
</displayName>
37149 <description>SRAM/NOR-Flash chip-select timing register
37151 <addressOffset>0x1C</addressOffset>
37153 <access>read-write
</access>
37154 <resetValue>0xFFFFFFFF</resetValue>
37157 <name>ACCMOD
</name>
37158 <description>ACCMOD
</description>
37159 <bitOffset>28</bitOffset>
37160 <bitWidth>2</bitWidth>
37163 <name>DATLAT
</name>
37164 <description>DATLAT
</description>
37165 <bitOffset>24</bitOffset>
37166 <bitWidth>4</bitWidth>
37169 <name>CLKDIV
</name>
37170 <description>CLKDIV
</description>
37171 <bitOffset>20</bitOffset>
37172 <bitWidth>4</bitWidth>
37175 <name>BUSTURN
</name>
37176 <description>BUSTURN
</description>
37177 <bitOffset>16</bitOffset>
37178 <bitWidth>4</bitWidth>
37181 <name>DATAST
</name>
37182 <description>DATAST
</description>
37183 <bitOffset>8</bitOffset>
37184 <bitWidth>8</bitWidth>
37187 <name>ADDHLD
</name>
37188 <description>ADDHLD
</description>
37189 <bitOffset>4</bitOffset>
37190 <bitWidth>4</bitWidth>
37193 <name>ADDSET
</name>
37194 <description>ADDSET
</description>
37195 <bitOffset>0</bitOffset>
37196 <bitWidth>4</bitWidth>
37202 <displayName>PCR2
</displayName>
37203 <description>PC Card/NAND Flash control register
37205 <addressOffset>0x60</addressOffset>
37207 <access>read-write
</access>
37208 <resetValue>0x00000018</resetValue>
37212 <description>ECCPS
</description>
37213 <bitOffset>17</bitOffset>
37214 <bitWidth>3</bitWidth>
37218 <description>TAR
</description>
37219 <bitOffset>13</bitOffset>
37220 <bitWidth>4</bitWidth>
37224 <description>TCLR
</description>
37225 <bitOffset>9</bitOffset>
37226 <bitWidth>4</bitWidth>
37230 <description>ECCEN
</description>
37231 <bitOffset>6</bitOffset>
37232 <bitWidth>1</bitWidth>
37236 <description>PWID
</description>
37237 <bitOffset>4</bitOffset>
37238 <bitWidth>2</bitWidth>
37242 <description>PTYP
</description>
37243 <bitOffset>3</bitOffset>
37244 <bitWidth>1</bitWidth>
37248 <description>PBKEN
</description>
37249 <bitOffset>2</bitOffset>
37250 <bitWidth>1</bitWidth>
37253 <name>PWAITEN
</name>
37254 <description>PWAITEN
</description>
37255 <bitOffset>1</bitOffset>
37256 <bitWidth>1</bitWidth>
37262 <displayName>SR2
</displayName>
37263 <description>FIFO status and interrupt register
37265 <addressOffset>0x64</addressOffset>
37267 <resetValue>0x00000040</resetValue>
37271 <description>FEMPT
</description>
37272 <bitOffset>6</bitOffset>
37273 <bitWidth>1</bitWidth>
37274 <access>read-only
</access>
37278 <description>IFEN
</description>
37279 <bitOffset>5</bitOffset>
37280 <bitWidth>1</bitWidth>
37281 <access>read-write
</access>
37285 <description>ILEN
</description>
37286 <bitOffset>4</bitOffset>
37287 <bitWidth>1</bitWidth>
37288 <access>read-write
</access>
37292 <description>IREN
</description>
37293 <bitOffset>3</bitOffset>
37294 <bitWidth>1</bitWidth>
37295 <access>read-write
</access>
37299 <description>IFS
</description>
37300 <bitOffset>2</bitOffset>
37301 <bitWidth>1</bitWidth>
37302 <access>read-write
</access>
37306 <description>ILS
</description>
37307 <bitOffset>1</bitOffset>
37308 <bitWidth>1</bitWidth>
37309 <access>read-write
</access>
37313 <description>IRS
</description>
37314 <bitOffset>0</bitOffset>
37315 <bitWidth>1</bitWidth>
37316 <access>read-write
</access>
37322 <displayName>PMEM2
</displayName>
37323 <description>Common memory space timing register
37325 <addressOffset>0x68</addressOffset>
37327 <access>read-write
</access>
37328 <resetValue>0xFCFCFCFC</resetValue>
37331 <name>MEMHIZx
</name>
37332 <description>MEMHIZx
</description>
37333 <bitOffset>24</bitOffset>
37334 <bitWidth>8</bitWidth>
37337 <name>MEMHOLDx
</name>
37338 <description>MEMHOLDx
</description>
37339 <bitOffset>16</bitOffset>
37340 <bitWidth>8</bitWidth>
37343 <name>MEMWAITx
</name>
37344 <description>MEMWAITx
</description>
37345 <bitOffset>8</bitOffset>
37346 <bitWidth>8</bitWidth>
37349 <name>MEMSETx
</name>
37350 <description>MEMSETx
</description>
37351 <bitOffset>0</bitOffset>
37352 <bitWidth>8</bitWidth>
37358 <displayName>PATT2
</displayName>
37359 <description>Attribute memory space timing register
37361 <addressOffset>0x6C</addressOffset>
37363 <access>read-write
</access>
37364 <resetValue>0xFCFCFCFC</resetValue>
37367 <name>ATTHIZx
</name>
37368 <description>ATTHIZx
</description>
37369 <bitOffset>24</bitOffset>
37370 <bitWidth>8</bitWidth>
37373 <name>ATTHOLDx
</name>
37374 <description>ATTHOLDx
</description>
37375 <bitOffset>16</bitOffset>
37376 <bitWidth>8</bitWidth>
37379 <name>ATTWAITx
</name>
37380 <description>ATTWAITx
</description>
37381 <bitOffset>8</bitOffset>
37382 <bitWidth>8</bitWidth>
37385 <name>ATTSETx
</name>
37386 <description>ATTSETx
</description>
37387 <bitOffset>0</bitOffset>
37388 <bitWidth>8</bitWidth>
37394 <displayName>ECCR2
</displayName>
37395 <description>ECC result register
2</description>
37396 <addressOffset>0x74</addressOffset>
37398 <access>read-only
</access>
37399 <resetValue>0x00000000</resetValue>
37403 <description>ECCx
</description>
37404 <bitOffset>0</bitOffset>
37405 <bitWidth>32</bitWidth>
37411 <displayName>PCR3
</displayName>
37412 <description>PC Card/NAND Flash control register
37414 <addressOffset>0x80</addressOffset>
37416 <access>read-write
</access>
37417 <resetValue>0x00000018</resetValue>
37421 <description>ECCPS
</description>
37422 <bitOffset>17</bitOffset>
37423 <bitWidth>3</bitWidth>
37427 <description>TAR
</description>
37428 <bitOffset>13</bitOffset>
37429 <bitWidth>4</bitWidth>
37433 <description>TCLR
</description>
37434 <bitOffset>9</bitOffset>
37435 <bitWidth>4</bitWidth>
37439 <description>ECCEN
</description>
37440 <bitOffset>6</bitOffset>
37441 <bitWidth>1</bitWidth>
37445 <description>PWID
</description>
37446 <bitOffset>4</bitOffset>
37447 <bitWidth>2</bitWidth>
37451 <description>PTYP
</description>
37452 <bitOffset>3</bitOffset>
37453 <bitWidth>1</bitWidth>
37457 <description>PBKEN
</description>
37458 <bitOffset>2</bitOffset>
37459 <bitWidth>1</bitWidth>
37462 <name>PWAITEN
</name>
37463 <description>PWAITEN
</description>
37464 <bitOffset>1</bitOffset>
37465 <bitWidth>1</bitWidth>
37471 <displayName>SR3
</displayName>
37472 <description>FIFO status and interrupt register
37474 <addressOffset>0x84</addressOffset>
37476 <resetValue>0x00000040</resetValue>
37480 <description>FEMPT
</description>
37481 <bitOffset>6</bitOffset>
37482 <bitWidth>1</bitWidth>
37483 <access>read-only
</access>
37487 <description>IFEN
</description>
37488 <bitOffset>5</bitOffset>
37489 <bitWidth>1</bitWidth>
37490 <access>read-write
</access>
37494 <description>ILEN
</description>
37495 <bitOffset>4</bitOffset>
37496 <bitWidth>1</bitWidth>
37497 <access>read-write
</access>
37501 <description>IREN
</description>
37502 <bitOffset>3</bitOffset>
37503 <bitWidth>1</bitWidth>
37504 <access>read-write
</access>
37508 <description>IFS
</description>
37509 <bitOffset>2</bitOffset>
37510 <bitWidth>1</bitWidth>
37511 <access>read-write
</access>
37515 <description>ILS
</description>
37516 <bitOffset>1</bitOffset>
37517 <bitWidth>1</bitWidth>
37518 <access>read-write
</access>
37522 <description>IRS
</description>
37523 <bitOffset>0</bitOffset>
37524 <bitWidth>1</bitWidth>
37525 <access>read-write
</access>
37531 <displayName>PMEM3
</displayName>
37532 <description>Common memory space timing register
37534 <addressOffset>0x88</addressOffset>
37536 <access>read-write
</access>
37537 <resetValue>0xFCFCFCFC</resetValue>
37540 <name>MEMHIZx
</name>
37541 <description>MEMHIZx
</description>
37542 <bitOffset>24</bitOffset>
37543 <bitWidth>8</bitWidth>
37546 <name>MEMHOLDx
</name>
37547 <description>MEMHOLDx
</description>
37548 <bitOffset>16</bitOffset>
37549 <bitWidth>8</bitWidth>
37552 <name>MEMWAITx
</name>
37553 <description>MEMWAITx
</description>
37554 <bitOffset>8</bitOffset>
37555 <bitWidth>8</bitWidth>
37558 <name>MEMSETx
</name>
37559 <description>MEMSETx
</description>
37560 <bitOffset>0</bitOffset>
37561 <bitWidth>8</bitWidth>
37567 <displayName>PATT3
</displayName>
37568 <description>Attribute memory space timing register
37570 <addressOffset>0x8C</addressOffset>
37572 <access>read-write
</access>
37573 <resetValue>0xFCFCFCFC</resetValue>
37576 <name>ATTHIZx
</name>
37577 <description>ATTHIZx
</description>
37578 <bitOffset>24</bitOffset>
37579 <bitWidth>8</bitWidth>
37582 <name>ATTHOLDx
</name>
37583 <description>ATTHOLDx
</description>
37584 <bitOffset>16</bitOffset>
37585 <bitWidth>8</bitWidth>
37588 <name>ATTWAITx
</name>
37589 <description>ATTWAITx
</description>
37590 <bitOffset>8</bitOffset>
37591 <bitWidth>8</bitWidth>
37594 <name>ATTSETx
</name>
37595 <description>ATTSETx
</description>
37596 <bitOffset>0</bitOffset>
37597 <bitWidth>8</bitWidth>
37603 <displayName>ECCR3
</displayName>
37604 <description>ECC result register
3</description>
37605 <addressOffset>0x94</addressOffset>
37607 <access>read-only
</access>
37608 <resetValue>0x00000000</resetValue>
37612 <description>ECCx
</description>
37613 <bitOffset>0</bitOffset>
37614 <bitWidth>32</bitWidth>
37620 <displayName>PCR4
</displayName>
37621 <description>PC Card/NAND Flash control register
37623 <addressOffset>0xA0</addressOffset>
37625 <access>read-write
</access>
37626 <resetValue>0x00000018</resetValue>
37630 <description>ECCPS
</description>
37631 <bitOffset>17</bitOffset>
37632 <bitWidth>3</bitWidth>
37636 <description>TAR
</description>
37637 <bitOffset>13</bitOffset>
37638 <bitWidth>4</bitWidth>
37642 <description>TCLR
</description>
37643 <bitOffset>9</bitOffset>
37644 <bitWidth>4</bitWidth>
37648 <description>ECCEN
</description>
37649 <bitOffset>6</bitOffset>
37650 <bitWidth>1</bitWidth>
37654 <description>PWID
</description>
37655 <bitOffset>4</bitOffset>
37656 <bitWidth>2</bitWidth>
37660 <description>PTYP
</description>
37661 <bitOffset>3</bitOffset>
37662 <bitWidth>1</bitWidth>
37666 <description>PBKEN
</description>
37667 <bitOffset>2</bitOffset>
37668 <bitWidth>1</bitWidth>
37671 <name>PWAITEN
</name>
37672 <description>PWAITEN
</description>
37673 <bitOffset>1</bitOffset>
37674 <bitWidth>1</bitWidth>
37680 <displayName>SR4
</displayName>
37681 <description>FIFO status and interrupt register
37683 <addressOffset>0xA4</addressOffset>
37685 <resetValue>0x00000040</resetValue>
37689 <description>FEMPT
</description>
37690 <bitOffset>6</bitOffset>
37691 <bitWidth>1</bitWidth>
37692 <access>read-only
</access>
37696 <description>IFEN
</description>
37697 <bitOffset>5</bitOffset>
37698 <bitWidth>1</bitWidth>
37699 <access>read-write
</access>
37703 <description>ILEN
</description>
37704 <bitOffset>4</bitOffset>
37705 <bitWidth>1</bitWidth>
37706 <access>read-write
</access>
37710 <description>IREN
</description>
37711 <bitOffset>3</bitOffset>
37712 <bitWidth>1</bitWidth>
37713 <access>read-write
</access>
37717 <description>IFS
</description>
37718 <bitOffset>2</bitOffset>
37719 <bitWidth>1</bitWidth>
37720 <access>read-write
</access>
37724 <description>ILS
</description>
37725 <bitOffset>1</bitOffset>
37726 <bitWidth>1</bitWidth>
37727 <access>read-write
</access>
37731 <description>IRS
</description>
37732 <bitOffset>0</bitOffset>
37733 <bitWidth>1</bitWidth>
37734 <access>read-write
</access>
37740 <displayName>PMEM4
</displayName>
37741 <description>Common memory space timing register
37743 <addressOffset>0xA8</addressOffset>
37745 <access>read-write
</access>
37746 <resetValue>0xFCFCFCFC</resetValue>
37749 <name>MEMHIZx
</name>
37750 <description>MEMHIZx
</description>
37751 <bitOffset>24</bitOffset>
37752 <bitWidth>8</bitWidth>
37755 <name>MEMHOLDx
</name>
37756 <description>MEMHOLDx
</description>
37757 <bitOffset>16</bitOffset>
37758 <bitWidth>8</bitWidth>
37761 <name>MEMWAITx
</name>
37762 <description>MEMWAITx
</description>
37763 <bitOffset>8</bitOffset>
37764 <bitWidth>8</bitWidth>
37767 <name>MEMSETx
</name>
37768 <description>MEMSETx
</description>
37769 <bitOffset>0</bitOffset>
37770 <bitWidth>8</bitWidth>
37776 <displayName>PATT4
</displayName>
37777 <description>Attribute memory space timing register
37779 <addressOffset>0xAC</addressOffset>
37781 <access>read-write
</access>
37782 <resetValue>0xFCFCFCFC</resetValue>
37785 <name>ATTHIZx
</name>
37786 <description>ATTHIZx
</description>
37787 <bitOffset>24</bitOffset>
37788 <bitWidth>8</bitWidth>
37791 <name>ATTHOLDx
</name>
37792 <description>ATTHOLDx
</description>
37793 <bitOffset>16</bitOffset>
37794 <bitWidth>8</bitWidth>
37797 <name>ATTWAITx
</name>
37798 <description>ATTWAITx
</description>
37799 <bitOffset>8</bitOffset>
37800 <bitWidth>8</bitWidth>
37803 <name>ATTSETx
</name>
37804 <description>ATTSETx
</description>
37805 <bitOffset>0</bitOffset>
37806 <bitWidth>8</bitWidth>
37812 <displayName>PIO4
</displayName>
37813 <description>I/O space timing register
4</description>
37814 <addressOffset>0xB0</addressOffset>
37816 <access>read-write
</access>
37817 <resetValue>0xFCFCFCFC</resetValue>
37820 <name>IOHIZx
</name>
37821 <description>IOHIZx
</description>
37822 <bitOffset>24</bitOffset>
37823 <bitWidth>8</bitWidth>
37826 <name>IOHOLDx
</name>
37827 <description>IOHOLDx
</description>
37828 <bitOffset>16</bitOffset>
37829 <bitWidth>8</bitWidth>
37832 <name>IOWAITx
</name>
37833 <description>IOWAITx
</description>
37834 <bitOffset>8</bitOffset>
37835 <bitWidth>8</bitWidth>
37838 <name>IOSETx
</name>
37839 <description>IOSETx
</description>
37840 <bitOffset>0</bitOffset>
37841 <bitWidth>8</bitWidth>
37847 <displayName>BWTR1
</displayName>
37848 <description>SRAM/NOR-Flash write timing registers
37850 <addressOffset>0x104</addressOffset>
37852 <access>read-write
</access>
37853 <resetValue>0x0FFFFFFF</resetValue>
37856 <name>ACCMOD
</name>
37857 <description>ACCMOD
</description>
37858 <bitOffset>28</bitOffset>
37859 <bitWidth>2</bitWidth>
37862 <name>DATLAT
</name>
37863 <description>DATLAT
</description>
37864 <bitOffset>24</bitOffset>
37865 <bitWidth>4</bitWidth>
37868 <name>CLKDIV
</name>
37869 <description>CLKDIV
</description>
37870 <bitOffset>20</bitOffset>
37871 <bitWidth>4</bitWidth>
37874 <name>BUSTURN
</name>
37875 <description>Bus turnaround phase
37876 duration
</description>
37877 <bitOffset>16</bitOffset>
37878 <bitWidth>4</bitWidth>
37881 <name>DATAST
</name>
37882 <description>DATAST
</description>
37883 <bitOffset>8</bitOffset>
37884 <bitWidth>8</bitWidth>
37887 <name>ADDHLD
</name>
37888 <description>ADDHLD
</description>
37889 <bitOffset>4</bitOffset>
37890 <bitWidth>4</bitWidth>
37893 <name>ADDSET
</name>
37894 <description>ADDSET
</description>
37895 <bitOffset>0</bitOffset>
37896 <bitWidth>4</bitWidth>
37902 <displayName>BWTR2
</displayName>
37903 <description>SRAM/NOR-Flash write timing registers
37905 <addressOffset>0x10C</addressOffset>
37907 <access>read-write
</access>
37908 <resetValue>0x0FFFFFFF</resetValue>
37911 <name>ACCMOD
</name>
37912 <description>ACCMOD
</description>
37913 <bitOffset>28</bitOffset>
37914 <bitWidth>2</bitWidth>
37917 <name>DATLAT
</name>
37918 <description>DATLAT
</description>
37919 <bitOffset>24</bitOffset>
37920 <bitWidth>4</bitWidth>
37923 <name>CLKDIV
</name>
37924 <description>CLKDIV
</description>
37925 <bitOffset>20</bitOffset>
37926 <bitWidth>4</bitWidth>
37929 <name>BUSTURN
</name>
37930 <description>Bus turnaround phase
37931 duration
</description>
37932 <bitOffset>16</bitOffset>
37933 <bitWidth>4</bitWidth>
37936 <name>DATAST
</name>
37937 <description>DATAST
</description>
37938 <bitOffset>8</bitOffset>
37939 <bitWidth>8</bitWidth>
37942 <name>ADDHLD
</name>
37943 <description>ADDHLD
</description>
37944 <bitOffset>4</bitOffset>
37945 <bitWidth>4</bitWidth>
37948 <name>ADDSET
</name>
37949 <description>ADDSET
</description>
37950 <bitOffset>0</bitOffset>
37951 <bitWidth>4</bitWidth>
37957 <displayName>BWTR3
</displayName>
37958 <description>SRAM/NOR-Flash write timing registers
37960 <addressOffset>0x114</addressOffset>
37962 <access>read-write
</access>
37963 <resetValue>0x0FFFFFFF</resetValue>
37966 <name>ACCMOD
</name>
37967 <description>ACCMOD
</description>
37968 <bitOffset>28</bitOffset>
37969 <bitWidth>2</bitWidth>
37972 <name>DATLAT
</name>
37973 <description>DATLAT
</description>
37974 <bitOffset>24</bitOffset>
37975 <bitWidth>4</bitWidth>
37978 <name>CLKDIV
</name>
37979 <description>CLKDIV
</description>
37980 <bitOffset>20</bitOffset>
37981 <bitWidth>4</bitWidth>
37984 <name>BUSTURN
</name>
37985 <description>Bus turnaround phase
37986 duration
</description>
37987 <bitOffset>16</bitOffset>
37988 <bitWidth>4</bitWidth>
37991 <name>DATAST
</name>
37992 <description>DATAST
</description>
37993 <bitOffset>8</bitOffset>
37994 <bitWidth>8</bitWidth>
37997 <name>ADDHLD
</name>
37998 <description>ADDHLD
</description>
37999 <bitOffset>4</bitOffset>
38000 <bitWidth>4</bitWidth>
38003 <name>ADDSET
</name>
38004 <description>ADDSET
</description>
38005 <bitOffset>0</bitOffset>
38006 <bitWidth>4</bitWidth>
38012 <displayName>BWTR4
</displayName>
38013 <description>SRAM/NOR-Flash write timing registers
38015 <addressOffset>0x11C</addressOffset>
38017 <access>read-write
</access>
38018 <resetValue>0x0FFFFFFF</resetValue>
38021 <name>ACCMOD
</name>
38022 <description>ACCMOD
</description>
38023 <bitOffset>28</bitOffset>
38024 <bitWidth>2</bitWidth>
38027 <name>DATLAT
</name>
38028 <description>DATLAT
</description>
38029 <bitOffset>24</bitOffset>
38030 <bitWidth>4</bitWidth>
38033 <name>CLKDIV
</name>
38034 <description>CLKDIV
</description>
38035 <bitOffset>20</bitOffset>
38036 <bitWidth>4</bitWidth>
38039 <name>BUSTURN
</name>
38040 <description>Bus turnaround phase
38041 duration
</description>
38042 <bitOffset>16</bitOffset>
38043 <bitWidth>4</bitWidth>
38046 <name>DATAST
</name>
38047 <description>DATAST
</description>
38048 <bitOffset>8</bitOffset>
38049 <bitWidth>8</bitWidth>
38052 <name>ADDHLD
</name>
38053 <description>ADDHLD
</description>
38054 <bitOffset>4</bitOffset>
38055 <bitWidth>4</bitWidth>
38058 <name>ADDSET
</name>
38059 <description>ADDSET
</description>
38060 <bitOffset>0</bitOffset>
38061 <bitWidth>4</bitWidth>
38069 <description>Nested Vectored Interrupt
38070 Controller
</description>
38071 <groupName>NVIC
</groupName>
38072 <baseAddress>0xE000E100</baseAddress>
38074 <offset>0x0</offset>
38076 <usage>registers
</usage>
38081 <displayName>ISER0
</displayName>
38082 <description>Interrupt Set-Enable Register
</description>
38083 <addressOffset>0x0</addressOffset>
38085 <access>read-write
</access>
38086 <resetValue>0x00000000</resetValue>
38089 <name>SETENA
</name>
38090 <description>SETENA
</description>
38091 <bitOffset>0</bitOffset>
38092 <bitWidth>32</bitWidth>
38098 <displayName>ISER1
</displayName>
38099 <description>Interrupt Set-Enable Register
</description>
38100 <addressOffset>0x4</addressOffset>
38102 <access>read-write
</access>
38103 <resetValue>0x00000000</resetValue>
38106 <name>SETENA
</name>
38107 <description>SETENA
</description>
38108 <bitOffset>0</bitOffset>
38109 <bitWidth>32</bitWidth>
38115 <displayName>ISER2
</displayName>
38116 <description>Interrupt Set-Enable Register
</description>
38117 <addressOffset>0x8</addressOffset>
38119 <access>read-write
</access>
38120 <resetValue>0x00000000</resetValue>
38123 <name>SETENA
</name>
38124 <description>SETENA
</description>
38125 <bitOffset>0</bitOffset>
38126 <bitWidth>32</bitWidth>
38132 <displayName>ICER0
</displayName>
38133 <description>Interrupt Clear-Enable
38134 Register
</description>
38135 <addressOffset>0x80</addressOffset>
38137 <access>read-write
</access>
38138 <resetValue>0x00000000</resetValue>
38141 <name>CLRENA
</name>
38142 <description>CLRENA
</description>
38143 <bitOffset>0</bitOffset>
38144 <bitWidth>32</bitWidth>
38150 <displayName>ICER1
</displayName>
38151 <description>Interrupt Clear-Enable
38152 Register
</description>
38153 <addressOffset>0x84</addressOffset>
38155 <access>read-write
</access>
38156 <resetValue>0x00000000</resetValue>
38159 <name>CLRENA
</name>
38160 <description>CLRENA
</description>
38161 <bitOffset>0</bitOffset>
38162 <bitWidth>32</bitWidth>
38168 <displayName>ICER2
</displayName>
38169 <description>Interrupt Clear-Enable
38170 Register
</description>
38171 <addressOffset>0x88</addressOffset>
38173 <access>read-write
</access>
38174 <resetValue>0x00000000</resetValue>
38177 <name>CLRENA
</name>
38178 <description>CLRENA
</description>
38179 <bitOffset>0</bitOffset>
38180 <bitWidth>32</bitWidth>
38186 <displayName>ISPR0
</displayName>
38187 <description>Interrupt Set-Pending Register
</description>
38188 <addressOffset>0x100</addressOffset>
38190 <access>read-write
</access>
38191 <resetValue>0x00000000</resetValue>
38194 <name>SETPEND
</name>
38195 <description>SETPEND
</description>
38196 <bitOffset>0</bitOffset>
38197 <bitWidth>32</bitWidth>
38203 <displayName>ISPR1
</displayName>
38204 <description>Interrupt Set-Pending Register
</description>
38205 <addressOffset>0x104</addressOffset>
38207 <access>read-write
</access>
38208 <resetValue>0x00000000</resetValue>
38211 <name>SETPEND
</name>
38212 <description>SETPEND
</description>
38213 <bitOffset>0</bitOffset>
38214 <bitWidth>32</bitWidth>
38220 <displayName>ISPR2
</displayName>
38221 <description>Interrupt Set-Pending Register
</description>
38222 <addressOffset>0x108</addressOffset>
38224 <access>read-write
</access>
38225 <resetValue>0x00000000</resetValue>
38228 <name>SETPEND
</name>
38229 <description>SETPEND
</description>
38230 <bitOffset>0</bitOffset>
38231 <bitWidth>32</bitWidth>
38237 <displayName>ICPR0
</displayName>
38238 <description>Interrupt Clear-Pending
38239 Register
</description>
38240 <addressOffset>0x180</addressOffset>
38242 <access>read-write
</access>
38243 <resetValue>0x00000000</resetValue>
38246 <name>CLRPEND
</name>
38247 <description>CLRPEND
</description>
38248 <bitOffset>0</bitOffset>
38249 <bitWidth>32</bitWidth>
38255 <displayName>ICPR1
</displayName>
38256 <description>Interrupt Clear-Pending
38257 Register
</description>
38258 <addressOffset>0x184</addressOffset>
38260 <access>read-write
</access>
38261 <resetValue>0x00000000</resetValue>
38264 <name>CLRPEND
</name>
38265 <description>CLRPEND
</description>
38266 <bitOffset>0</bitOffset>
38267 <bitWidth>32</bitWidth>
38273 <displayName>ICPR2
</displayName>
38274 <description>Interrupt Clear-Pending
38275 Register
</description>
38276 <addressOffset>0x188</addressOffset>
38278 <access>read-write
</access>
38279 <resetValue>0x00000000</resetValue>
38282 <name>CLRPEND
</name>
38283 <description>CLRPEND
</description>
38284 <bitOffset>0</bitOffset>
38285 <bitWidth>32</bitWidth>
38291 <displayName>IABR0
</displayName>
38292 <description>Interrupt Active Bit Register
</description>
38293 <addressOffset>0x200</addressOffset>
38295 <access>read-only
</access>
38296 <resetValue>0x00000000</resetValue>
38299 <name>ACTIVE
</name>
38300 <description>ACTIVE
</description>
38301 <bitOffset>0</bitOffset>
38302 <bitWidth>32</bitWidth>
38308 <displayName>IABR1
</displayName>
38309 <description>Interrupt Active Bit Register
</description>
38310 <addressOffset>0x204</addressOffset>
38312 <access>read-only
</access>
38313 <resetValue>0x00000000</resetValue>
38316 <name>ACTIVE
</name>
38317 <description>ACTIVE
</description>
38318 <bitOffset>0</bitOffset>
38319 <bitWidth>32</bitWidth>
38325 <displayName>IABR2
</displayName>
38326 <description>Interrupt Active Bit Register
</description>
38327 <addressOffset>0x208</addressOffset>
38329 <access>read-only
</access>
38330 <resetValue>0x00000000</resetValue>
38333 <name>ACTIVE
</name>
38334 <description>ACTIVE
</description>
38335 <bitOffset>0</bitOffset>
38336 <bitWidth>32</bitWidth>
38342 <displayName>IPR0
</displayName>
38343 <description>Interrupt Priority Register
</description>
38344 <addressOffset>0x300</addressOffset>
38346 <access>read-write
</access>
38347 <resetValue>0x00000000</resetValue>
38350 <name>IPR_N0
</name>
38351 <description>IPR_N0
</description>
38352 <bitOffset>0</bitOffset>
38353 <bitWidth>8</bitWidth>
38356 <name>IPR_N1
</name>
38357 <description>IPR_N1
</description>
38358 <bitOffset>8</bitOffset>
38359 <bitWidth>8</bitWidth>
38362 <name>IPR_N2
</name>
38363 <description>IPR_N2
</description>
38364 <bitOffset>16</bitOffset>
38365 <bitWidth>8</bitWidth>
38368 <name>IPR_N3
</name>
38369 <description>IPR_N3
</description>
38370 <bitOffset>24</bitOffset>
38371 <bitWidth>8</bitWidth>
38377 <displayName>IPR1
</displayName>
38378 <description>Interrupt Priority Register
</description>
38379 <addressOffset>0x304</addressOffset>
38381 <access>read-write
</access>
38382 <resetValue>0x00000000</resetValue>
38385 <name>IPR_N0
</name>
38386 <description>IPR_N0
</description>
38387 <bitOffset>0</bitOffset>
38388 <bitWidth>8</bitWidth>
38391 <name>IPR_N1
</name>
38392 <description>IPR_N1
</description>
38393 <bitOffset>8</bitOffset>
38394 <bitWidth>8</bitWidth>
38397 <name>IPR_N2
</name>
38398 <description>IPR_N2
</description>
38399 <bitOffset>16</bitOffset>
38400 <bitWidth>8</bitWidth>
38403 <name>IPR_N3
</name>
38404 <description>IPR_N3
</description>
38405 <bitOffset>24</bitOffset>
38406 <bitWidth>8</bitWidth>
38412 <displayName>IPR2
</displayName>
38413 <description>Interrupt Priority Register
</description>
38414 <addressOffset>0x308</addressOffset>
38416 <access>read-write
</access>
38417 <resetValue>0x00000000</resetValue>
38420 <name>IPR_N0
</name>
38421 <description>IPR_N0
</description>
38422 <bitOffset>0</bitOffset>
38423 <bitWidth>8</bitWidth>
38426 <name>IPR_N1
</name>
38427 <description>IPR_N1
</description>
38428 <bitOffset>8</bitOffset>
38429 <bitWidth>8</bitWidth>
38432 <name>IPR_N2
</name>
38433 <description>IPR_N2
</description>
38434 <bitOffset>16</bitOffset>
38435 <bitWidth>8</bitWidth>
38438 <name>IPR_N3
</name>
38439 <description>IPR_N3
</description>
38440 <bitOffset>24</bitOffset>
38441 <bitWidth>8</bitWidth>
38447 <displayName>IPR3
</displayName>
38448 <description>Interrupt Priority Register
</description>
38449 <addressOffset>0x30C</addressOffset>
38451 <access>read-write
</access>
38452 <resetValue>0x00000000</resetValue>
38455 <name>IPR_N0
</name>
38456 <description>IPR_N0
</description>
38457 <bitOffset>0</bitOffset>
38458 <bitWidth>8</bitWidth>
38461 <name>IPR_N1
</name>
38462 <description>IPR_N1
</description>
38463 <bitOffset>8</bitOffset>
38464 <bitWidth>8</bitWidth>
38467 <name>IPR_N2
</name>
38468 <description>IPR_N2
</description>
38469 <bitOffset>16</bitOffset>
38470 <bitWidth>8</bitWidth>
38473 <name>IPR_N3
</name>
38474 <description>IPR_N3
</description>
38475 <bitOffset>24</bitOffset>
38476 <bitWidth>8</bitWidth>
38482 <displayName>IPR4
</displayName>
38483 <description>Interrupt Priority Register
</description>
38484 <addressOffset>0x310</addressOffset>
38486 <access>read-write
</access>
38487 <resetValue>0x00000000</resetValue>
38490 <name>IPR_N0
</name>
38491 <description>IPR_N0
</description>
38492 <bitOffset>0</bitOffset>
38493 <bitWidth>8</bitWidth>
38496 <name>IPR_N1
</name>
38497 <description>IPR_N1
</description>
38498 <bitOffset>8</bitOffset>
38499 <bitWidth>8</bitWidth>
38502 <name>IPR_N2
</name>
38503 <description>IPR_N2
</description>
38504 <bitOffset>16</bitOffset>
38505 <bitWidth>8</bitWidth>
38508 <name>IPR_N3
</name>
38509 <description>IPR_N3
</description>
38510 <bitOffset>24</bitOffset>
38511 <bitWidth>8</bitWidth>
38517 <displayName>IPR5
</displayName>
38518 <description>Interrupt Priority Register
</description>
38519 <addressOffset>0x314</addressOffset>
38521 <access>read-write
</access>
38522 <resetValue>0x00000000</resetValue>
38525 <name>IPR_N0
</name>
38526 <description>IPR_N0
</description>
38527 <bitOffset>0</bitOffset>
38528 <bitWidth>8</bitWidth>
38531 <name>IPR_N1
</name>
38532 <description>IPR_N1
</description>
38533 <bitOffset>8</bitOffset>
38534 <bitWidth>8</bitWidth>
38537 <name>IPR_N2
</name>
38538 <description>IPR_N2
</description>
38539 <bitOffset>16</bitOffset>
38540 <bitWidth>8</bitWidth>
38543 <name>IPR_N3
</name>
38544 <description>IPR_N3
</description>
38545 <bitOffset>24</bitOffset>
38546 <bitWidth>8</bitWidth>
38552 <displayName>IPR6
</displayName>
38553 <description>Interrupt Priority Register
</description>
38554 <addressOffset>0x318</addressOffset>
38556 <access>read-write
</access>
38557 <resetValue>0x00000000</resetValue>
38560 <name>IPR_N0
</name>
38561 <description>IPR_N0
</description>
38562 <bitOffset>0</bitOffset>
38563 <bitWidth>8</bitWidth>
38566 <name>IPR_N1
</name>
38567 <description>IPR_N1
</description>
38568 <bitOffset>8</bitOffset>
38569 <bitWidth>8</bitWidth>
38572 <name>IPR_N2
</name>
38573 <description>IPR_N2
</description>
38574 <bitOffset>16</bitOffset>
38575 <bitWidth>8</bitWidth>
38578 <name>IPR_N3
</name>
38579 <description>IPR_N3
</description>
38580 <bitOffset>24</bitOffset>
38581 <bitWidth>8</bitWidth>
38587 <displayName>IPR7
</displayName>
38588 <description>Interrupt Priority Register
</description>
38589 <addressOffset>0x31C</addressOffset>
38591 <access>read-write
</access>
38592 <resetValue>0x00000000</resetValue>
38595 <name>IPR_N0
</name>
38596 <description>IPR_N0
</description>
38597 <bitOffset>0</bitOffset>
38598 <bitWidth>8</bitWidth>
38601 <name>IPR_N1
</name>
38602 <description>IPR_N1
</description>
38603 <bitOffset>8</bitOffset>
38604 <bitWidth>8</bitWidth>
38607 <name>IPR_N2
</name>
38608 <description>IPR_N2
</description>
38609 <bitOffset>16</bitOffset>
38610 <bitWidth>8</bitWidth>
38613 <name>IPR_N3
</name>
38614 <description>IPR_N3
</description>
38615 <bitOffset>24</bitOffset>
38616 <bitWidth>8</bitWidth>
38622 <displayName>IPR8
</displayName>
38623 <description>Interrupt Priority Register
</description>
38624 <addressOffset>0x320</addressOffset>
38626 <access>read-write
</access>
38627 <resetValue>0x00000000</resetValue>
38630 <name>IPR_N0
</name>
38631 <description>IPR_N0
</description>
38632 <bitOffset>0</bitOffset>
38633 <bitWidth>8</bitWidth>
38636 <name>IPR_N1
</name>
38637 <description>IPR_N1
</description>
38638 <bitOffset>8</bitOffset>
38639 <bitWidth>8</bitWidth>
38642 <name>IPR_N2
</name>
38643 <description>IPR_N2
</description>
38644 <bitOffset>16</bitOffset>
38645 <bitWidth>8</bitWidth>
38648 <name>IPR_N3
</name>
38649 <description>IPR_N3
</description>
38650 <bitOffset>24</bitOffset>
38651 <bitWidth>8</bitWidth>
38657 <displayName>IPR9
</displayName>
38658 <description>Interrupt Priority Register
</description>
38659 <addressOffset>0x324</addressOffset>
38661 <access>read-write
</access>
38662 <resetValue>0x00000000</resetValue>
38665 <name>IPR_N0
</name>
38666 <description>IPR_N0
</description>
38667 <bitOffset>0</bitOffset>
38668 <bitWidth>8</bitWidth>
38671 <name>IPR_N1
</name>
38672 <description>IPR_N1
</description>
38673 <bitOffset>8</bitOffset>
38674 <bitWidth>8</bitWidth>
38677 <name>IPR_N2
</name>
38678 <description>IPR_N2
</description>
38679 <bitOffset>16</bitOffset>
38680 <bitWidth>8</bitWidth>
38683 <name>IPR_N3
</name>
38684 <description>IPR_N3
</description>
38685 <bitOffset>24</bitOffset>
38686 <bitWidth>8</bitWidth>
38692 <displayName>IPR10
</displayName>
38693 <description>Interrupt Priority Register
</description>
38694 <addressOffset>0x328</addressOffset>
38696 <access>read-write
</access>
38697 <resetValue>0x00000000</resetValue>
38700 <name>IPR_N0
</name>
38701 <description>IPR_N0
</description>
38702 <bitOffset>0</bitOffset>
38703 <bitWidth>8</bitWidth>
38706 <name>IPR_N1
</name>
38707 <description>IPR_N1
</description>
38708 <bitOffset>8</bitOffset>
38709 <bitWidth>8</bitWidth>
38712 <name>IPR_N2
</name>
38713 <description>IPR_N2
</description>
38714 <bitOffset>16</bitOffset>
38715 <bitWidth>8</bitWidth>
38718 <name>IPR_N3
</name>
38719 <description>IPR_N3
</description>
38720 <bitOffset>24</bitOffset>
38721 <bitWidth>8</bitWidth>
38727 <displayName>IPR11
</displayName>
38728 <description>Interrupt Priority Register
</description>
38729 <addressOffset>0x32C</addressOffset>
38731 <access>read-write
</access>
38732 <resetValue>0x00000000</resetValue>
38735 <name>IPR_N0
</name>
38736 <description>IPR_N0
</description>
38737 <bitOffset>0</bitOffset>
38738 <bitWidth>8</bitWidth>
38741 <name>IPR_N1
</name>
38742 <description>IPR_N1
</description>
38743 <bitOffset>8</bitOffset>
38744 <bitWidth>8</bitWidth>
38747 <name>IPR_N2
</name>
38748 <description>IPR_N2
</description>
38749 <bitOffset>16</bitOffset>
38750 <bitWidth>8</bitWidth>
38753 <name>IPR_N3
</name>
38754 <description>IPR_N3
</description>
38755 <bitOffset>24</bitOffset>
38756 <bitWidth>8</bitWidth>
38762 <displayName>IPR12
</displayName>
38763 <description>Interrupt Priority Register
</description>
38764 <addressOffset>0x330</addressOffset>
38766 <access>read-write
</access>
38767 <resetValue>0x00000000</resetValue>
38770 <name>IPR_N0
</name>
38771 <description>IPR_N0
</description>
38772 <bitOffset>0</bitOffset>
38773 <bitWidth>8</bitWidth>
38776 <name>IPR_N1
</name>
38777 <description>IPR_N1
</description>
38778 <bitOffset>8</bitOffset>
38779 <bitWidth>8</bitWidth>
38782 <name>IPR_N2
</name>
38783 <description>IPR_N2
</description>
38784 <bitOffset>16</bitOffset>
38785 <bitWidth>8</bitWidth>
38788 <name>IPR_N3
</name>
38789 <description>IPR_N3
</description>
38790 <bitOffset>24</bitOffset>
38791 <bitWidth>8</bitWidth>
38797 <displayName>IPR13
</displayName>
38798 <description>Interrupt Priority Register
</description>
38799 <addressOffset>0x334</addressOffset>
38801 <access>read-write
</access>
38802 <resetValue>0x00000000</resetValue>
38805 <name>IPR_N0
</name>
38806 <description>IPR_N0
</description>
38807 <bitOffset>0</bitOffset>
38808 <bitWidth>8</bitWidth>
38811 <name>IPR_N1
</name>
38812 <description>IPR_N1
</description>
38813 <bitOffset>8</bitOffset>
38814 <bitWidth>8</bitWidth>
38817 <name>IPR_N2
</name>
38818 <description>IPR_N2
</description>
38819 <bitOffset>16</bitOffset>
38820 <bitWidth>8</bitWidth>
38823 <name>IPR_N3
</name>
38824 <description>IPR_N3
</description>
38825 <bitOffset>24</bitOffset>
38826 <bitWidth>8</bitWidth>
38832 <displayName>IPR14
</displayName>
38833 <description>Interrupt Priority Register
</description>
38834 <addressOffset>0x338</addressOffset>
38836 <access>read-write
</access>
38837 <resetValue>0x00000000</resetValue>
38840 <name>IPR_N0
</name>
38841 <description>IPR_N0
</description>
38842 <bitOffset>0</bitOffset>
38843 <bitWidth>8</bitWidth>
38846 <name>IPR_N1
</name>
38847 <description>IPR_N1
</description>
38848 <bitOffset>8</bitOffset>
38849 <bitWidth>8</bitWidth>
38852 <name>IPR_N2
</name>
38853 <description>IPR_N2
</description>
38854 <bitOffset>16</bitOffset>
38855 <bitWidth>8</bitWidth>
38858 <name>IPR_N3
</name>
38859 <description>IPR_N3
</description>
38860 <bitOffset>24</bitOffset>
38861 <bitWidth>8</bitWidth>
38867 <displayName>IPR15
</displayName>
38868 <description>Interrupt Priority Register
</description>
38869 <addressOffset>0x33C</addressOffset>
38871 <access>read-write
</access>
38872 <resetValue>0x00000000</resetValue>
38875 <name>IPR_N0
</name>
38876 <description>IPR_N0
</description>
38877 <bitOffset>0</bitOffset>
38878 <bitWidth>8</bitWidth>
38881 <name>IPR_N1
</name>
38882 <description>IPR_N1
</description>
38883 <bitOffset>8</bitOffset>
38884 <bitWidth>8</bitWidth>
38887 <name>IPR_N2
</name>
38888 <description>IPR_N2
</description>
38889 <bitOffset>16</bitOffset>
38890 <bitWidth>8</bitWidth>
38893 <name>IPR_N3
</name>
38894 <description>IPR_N3
</description>
38895 <bitOffset>24</bitOffset>
38896 <bitWidth>8</bitWidth>
38902 <displayName>IPR16
</displayName>
38903 <description>Interrupt Priority Register
</description>
38904 <addressOffset>0x340</addressOffset>
38906 <access>read-write
</access>
38907 <resetValue>0x00000000</resetValue>
38910 <name>IPR_N0
</name>
38911 <description>IPR_N0
</description>
38912 <bitOffset>0</bitOffset>
38913 <bitWidth>8</bitWidth>
38916 <name>IPR_N1
</name>
38917 <description>IPR_N1
</description>
38918 <bitOffset>8</bitOffset>
38919 <bitWidth>8</bitWidth>
38922 <name>IPR_N2
</name>
38923 <description>IPR_N2
</description>
38924 <bitOffset>16</bitOffset>
38925 <bitWidth>8</bitWidth>
38928 <name>IPR_N3
</name>
38929 <description>IPR_N3
</description>
38930 <bitOffset>24</bitOffset>
38931 <bitWidth>8</bitWidth>
38937 <displayName>IPR17
</displayName>
38938 <description>Interrupt Priority Register
</description>
38939 <addressOffset>0x344</addressOffset>
38941 <access>read-write
</access>
38942 <resetValue>0x00000000</resetValue>
38945 <name>IPR_N0
</name>
38946 <description>IPR_N0
</description>
38947 <bitOffset>0</bitOffset>
38948 <bitWidth>8</bitWidth>
38951 <name>IPR_N1
</name>
38952 <description>IPR_N1
</description>
38953 <bitOffset>8</bitOffset>
38954 <bitWidth>8</bitWidth>
38957 <name>IPR_N2
</name>
38958 <description>IPR_N2
</description>
38959 <bitOffset>16</bitOffset>
38960 <bitWidth>8</bitWidth>
38963 <name>IPR_N3
</name>
38964 <description>IPR_N3
</description>
38965 <bitOffset>24</bitOffset>
38966 <bitWidth>8</bitWidth>
38972 <displayName>IPR18
</displayName>
38973 <description>Interrupt Priority Register
</description>
38974 <addressOffset>0x348</addressOffset>
38976 <access>read-write
</access>
38977 <resetValue>0x00000000</resetValue>
38980 <name>IPR_N0
</name>
38981 <description>IPR_N0
</description>
38982 <bitOffset>0</bitOffset>
38983 <bitWidth>8</bitWidth>
38986 <name>IPR_N1
</name>
38987 <description>IPR_N1
</description>
38988 <bitOffset>8</bitOffset>
38989 <bitWidth>8</bitWidth>
38992 <name>IPR_N2
</name>
38993 <description>IPR_N2
</description>
38994 <bitOffset>16</bitOffset>
38995 <bitWidth>8</bitWidth>
38998 <name>IPR_N3
</name>
38999 <description>IPR_N3
</description>
39000 <bitOffset>24</bitOffset>
39001 <bitWidth>8</bitWidth>
39007 <displayName>IPR19
</displayName>
39008 <description>Interrupt Priority Register
</description>
39009 <addressOffset>0x34C</addressOffset>
39011 <access>read-write
</access>
39012 <resetValue>0x00000000</resetValue>
39015 <name>IPR_N0
</name>
39016 <description>IPR_N0
</description>
39017 <bitOffset>0</bitOffset>
39018 <bitWidth>8</bitWidth>
39021 <name>IPR_N1
</name>
39022 <description>IPR_N1
</description>
39023 <bitOffset>8</bitOffset>
39024 <bitWidth>8</bitWidth>
39027 <name>IPR_N2
</name>
39028 <description>IPR_N2
</description>
39029 <bitOffset>16</bitOffset>
39030 <bitWidth>8</bitWidth>
39033 <name>IPR_N3
</name>
39034 <description>IPR_N3
</description>
39035 <bitOffset>24</bitOffset>
39036 <bitWidth>8</bitWidth>
39042 <displayName>IPR20
</displayName>
39043 <description>Interrupt Priority Register
</description>
39044 <addressOffset>0x350</addressOffset>
39046 <access>read-write
</access>
39047 <resetValue>0x00000000</resetValue>
39050 <name>IPR_N0
</name>
39051 <description>IPR_N0
</description>
39052 <bitOffset>0</bitOffset>
39053 <bitWidth>8</bitWidth>
39056 <name>IPR_N1
</name>
39057 <description>IPR_N1
</description>
39058 <bitOffset>8</bitOffset>
39059 <bitWidth>8</bitWidth>
39062 <name>IPR_N2
</name>
39063 <description>IPR_N2
</description>
39064 <bitOffset>16</bitOffset>
39065 <bitWidth>8</bitWidth>
39068 <name>IPR_N3
</name>
39069 <description>IPR_N3
</description>
39070 <bitOffset>24</bitOffset>
39071 <bitWidth>8</bitWidth>
39079 <description>Floting point unit
</description>
39080 <groupName>FPU
</groupName>
39081 <baseAddress>0xE000EF34</baseAddress>
39083 <offset>0x0</offset>
39085 <usage>registers
</usage>
39089 <description>Floating point unit interrupt
</description>
39094 <description>Floating point interrupt
</description>
39100 <displayName>FPCCR
</displayName>
39101 <description>Floating-point context control
39102 register
</description>
39103 <addressOffset>0x0</addressOffset>
39105 <access>read-write
</access>
39106 <resetValue>0x00000000</resetValue>
39109 <name>LSPACT
</name>
39110 <description>LSPACT
</description>
39111 <bitOffset>0</bitOffset>
39112 <bitWidth>1</bitWidth>
39116 <description>USER
</description>
39117 <bitOffset>1</bitOffset>
39118 <bitWidth>1</bitWidth>
39121 <name>THREAD
</name>
39122 <description>THREAD
</description>
39123 <bitOffset>3</bitOffset>
39124 <bitWidth>1</bitWidth>
39128 <description>HFRDY
</description>
39129 <bitOffset>4</bitOffset>
39130 <bitWidth>1</bitWidth>
39134 <description>MMRDY
</description>
39135 <bitOffset>5</bitOffset>
39136 <bitWidth>1</bitWidth>
39140 <description>BFRDY
</description>
39141 <bitOffset>6</bitOffset>
39142 <bitWidth>1</bitWidth>
39145 <name>MONRDY
</name>
39146 <description>MONRDY
</description>
39147 <bitOffset>8</bitOffset>
39148 <bitWidth>1</bitWidth>
39152 <description>LSPEN
</description>
39153 <bitOffset>30</bitOffset>
39154 <bitWidth>1</bitWidth>
39158 <description>ASPEN
</description>
39159 <bitOffset>31</bitOffset>
39160 <bitWidth>1</bitWidth>
39166 <displayName>FPCAR
</displayName>
39167 <description>Floating-point context address
39168 register
</description>
39169 <addressOffset>0x4</addressOffset>
39171 <access>read-write
</access>
39172 <resetValue>0x00000000</resetValue>
39175 <name>ADDRESS
</name>
39176 <description>Location of unpopulated
39177 floating-point
</description>
39178 <bitOffset>3</bitOffset>
39179 <bitWidth>29</bitWidth>
39185 <displayName>FPSCR
</displayName>
39186 <description>Floating-point status control
39187 register
</description>
39188 <addressOffset>0x8</addressOffset>
39190 <access>read-write
</access>
39191 <resetValue>0x00000000</resetValue>
39195 <description>Invalid operation cumulative exception
39197 <bitOffset>0</bitOffset>
39198 <bitWidth>1</bitWidth>
39202 <description>Division by zero cumulative exception
39204 <bitOffset>1</bitOffset>
39205 <bitWidth>1</bitWidth>
39209 <description>Overflow cumulative exception
39211 <bitOffset>2</bitOffset>
39212 <bitWidth>1</bitWidth>
39216 <description>Underflow cumulative exception
39218 <bitOffset>3</bitOffset>
39219 <bitWidth>1</bitWidth>
39223 <description>Inexact cumulative exception
39225 <bitOffset>4</bitOffset>
39226 <bitWidth>1</bitWidth>
39230 <description>Input denormal cumulative exception
39232 <bitOffset>7</bitOffset>
39233 <bitWidth>1</bitWidth>
39237 <description>Rounding Mode control
39238 field
</description>
39239 <bitOffset>22</bitOffset>
39240 <bitWidth>2</bitWidth>
39244 <description>Flush-to-zero mode control
39246 <bitOffset>24</bitOffset>
39247 <bitWidth>1</bitWidth>
39251 <description>Default NaN mode control
39253 <bitOffset>25</bitOffset>
39254 <bitWidth>1</bitWidth>
39258 <description>Alternative half-precision control
39260 <bitOffset>26</bitOffset>
39261 <bitWidth>1</bitWidth>
39265 <description>Overflow condition code
39267 <bitOffset>28</bitOffset>
39268 <bitWidth>1</bitWidth>
39272 <description>Carry condition code flag
</description>
39273 <bitOffset>29</bitOffset>
39274 <bitWidth>1</bitWidth>
39278 <description>Zero condition code flag
</description>
39279 <bitOffset>30</bitOffset>
39280 <bitWidth>1</bitWidth>
39284 <description>Negative condition code
39286 <bitOffset>31</bitOffset>
39287 <bitWidth>1</bitWidth>
39295 <description>Memory protection unit
</description>
39296 <groupName>MPU
</groupName>
39297 <baseAddress>0xE000ED90</baseAddress>
39299 <offset>0x0</offset>
39301 <usage>registers
</usage>
39305 <name>MPU_TYPER
</name>
39306 <displayName>MPU_TYPER
</displayName>
39307 <description>MPU type register
</description>
39308 <addressOffset>0x0</addressOffset>
39310 <access>read-only
</access>
39311 <resetValue>0X00000800</resetValue>
39314 <name>SEPARATE
</name>
39315 <description>Separate flag
</description>
39316 <bitOffset>0</bitOffset>
39317 <bitWidth>1</bitWidth>
39320 <name>DREGION
</name>
39321 <description>Number of MPU data regions
</description>
39322 <bitOffset>8</bitOffset>
39323 <bitWidth>8</bitWidth>
39326 <name>IREGION
</name>
39327 <description>Number of MPU instruction
39328 regions
</description>
39329 <bitOffset>16</bitOffset>
39330 <bitWidth>8</bitWidth>
39335 <name>MPU_CTRL
</name>
39336 <displayName>MPU_CTRL
</displayName>
39337 <description>MPU control register
</description>
39338 <addressOffset>0x4</addressOffset>
39340 <access>read-only
</access>
39341 <resetValue>0X00000000</resetValue>
39344 <name>ENABLE
</name>
39345 <description>Enables the MPU
</description>
39346 <bitOffset>0</bitOffset>
39347 <bitWidth>1</bitWidth>
39350 <name>HFNMIENA
</name>
39351 <description>Enables the operation of MPU during hard
39352 fault
</description>
39353 <bitOffset>1</bitOffset>
39354 <bitWidth>1</bitWidth>
39357 <name>PRIVDEFENA
</name>
39358 <description>Enable priviliged software access to
39359 default memory map
</description>
39360 <bitOffset>2</bitOffset>
39361 <bitWidth>1</bitWidth>
39366 <name>MPU_RNR
</name>
39367 <displayName>MPU_RNR
</displayName>
39368 <description>MPU region number register
</description>
39369 <addressOffset>0x8</addressOffset>
39371 <access>read-write
</access>
39372 <resetValue>0X00000000</resetValue>
39375 <name>REGION
</name>
39376 <description>MPU region
</description>
39377 <bitOffset>0</bitOffset>
39378 <bitWidth>8</bitWidth>
39383 <name>MPU_RBAR
</name>
39384 <displayName>MPU_RBAR
</displayName>
39385 <description>MPU region base address
39386 register
</description>
39387 <addressOffset>0xC</addressOffset>
39389 <access>read-write
</access>
39390 <resetValue>0X00000000</resetValue>
39393 <name>REGION
</name>
39394 <description>MPU region field
</description>
39395 <bitOffset>0</bitOffset>
39396 <bitWidth>4</bitWidth>
39400 <description>MPU region number valid
</description>
39401 <bitOffset>4</bitOffset>
39402 <bitWidth>1</bitWidth>
39406 <description>Region base address field
</description>
39407 <bitOffset>5</bitOffset>
39408 <bitWidth>27</bitWidth>
39413 <name>MPU_RASR
</name>
39414 <displayName>MPU_RASR
</displayName>
39415 <description>MPU region attribute and size
39416 register
</description>
39417 <addressOffset>0x10</addressOffset>
39419 <access>read-write
</access>
39420 <resetValue>0X00000000</resetValue>
39423 <name>ENABLE
</name>
39424 <description>Region enable bit.
</description>
39425 <bitOffset>0</bitOffset>
39426 <bitWidth>1</bitWidth>
39430 <description>Size of the MPU protection
39431 region
</description>
39432 <bitOffset>1</bitOffset>
39433 <bitWidth>5</bitWidth>
39437 <description>Subregion disable bits
</description>
39438 <bitOffset>8</bitOffset>
39439 <bitWidth>8</bitWidth>
39443 <description>memory attribute
</description>
39444 <bitOffset>16</bitOffset>
39445 <bitWidth>1</bitWidth>
39449 <description>memory attribute
</description>
39450 <bitOffset>17</bitOffset>
39451 <bitWidth>1</bitWidth>
39455 <description>Shareable memory attribute
</description>
39456 <bitOffset>18</bitOffset>
39457 <bitWidth>1</bitWidth>
39461 <description>memory attribute
</description>
39462 <bitOffset>19</bitOffset>
39463 <bitWidth>3</bitWidth>
39467 <description>Access permission
</description>
39468 <bitOffset>24</bitOffset>
39469 <bitWidth>3</bitWidth>
39473 <description>Instruction access disable
39475 <bitOffset>28</bitOffset>
39476 <bitWidth>1</bitWidth>
39484 <description>SysTick timer
</description>
39485 <groupName>STK
</groupName>
39486 <baseAddress>0xE000E010</baseAddress>
39488 <offset>0x0</offset>
39490 <usage>registers
</usage>
39495 <displayName>CTRL
</displayName>
39496 <description>SysTick control and status
39497 register
</description>
39498 <addressOffset>0x0</addressOffset>
39500 <access>read-write
</access>
39501 <resetValue>0X00000000</resetValue>
39504 <name>ENABLE
</name>
39505 <description>Counter enable
</description>
39506 <bitOffset>0</bitOffset>
39507 <bitWidth>1</bitWidth>
39510 <name>TICKINT
</name>
39511 <description>SysTick exception request
39512 enable
</description>
39513 <bitOffset>1</bitOffset>
39514 <bitWidth>1</bitWidth>
39517 <name>CLKSOURCE
</name>
39518 <description>Clock source selection
</description>
39519 <bitOffset>2</bitOffset>
39520 <bitWidth>1</bitWidth>
39523 <name>COUNTFLAG
</name>
39524 <description>COUNTFLAG
</description>
39525 <bitOffset>16</bitOffset>
39526 <bitWidth>1</bitWidth>
39532 <displayName>LOAD
</displayName>
39533 <description>SysTick reload value register
</description>
39534 <addressOffset>0x4</addressOffset>
39536 <access>read-write
</access>
39537 <resetValue>0X00000000</resetValue>
39540 <name>RELOAD
</name>
39541 <description>RELOAD value
</description>
39542 <bitOffset>0</bitOffset>
39543 <bitWidth>24</bitWidth>
39549 <displayName>VAL
</displayName>
39550 <description>SysTick current value register
</description>
39551 <addressOffset>0x8</addressOffset>
39553 <access>read-write
</access>
39554 <resetValue>0X00000000</resetValue>
39557 <name>CURRENT
</name>
39558 <description>Current counter value
</description>
39559 <bitOffset>0</bitOffset>
39560 <bitWidth>24</bitWidth>
39566 <displayName>CALIB
</displayName>
39567 <description>SysTick calibration value
39568 register
</description>
39569 <addressOffset>0xC</addressOffset>
39571 <access>read-write
</access>
39572 <resetValue>0X00000000</resetValue>
39576 <description>Calibration value
</description>
39577 <bitOffset>0</bitOffset>
39578 <bitWidth>24</bitWidth>
39582 <description>SKEW flag: Indicates whether the TENMS
39583 value is exact
</description>
39584 <bitOffset>30</bitOffset>
39585 <bitWidth>1</bitWidth>
39589 <description>NOREF flag. Reads as zero
</description>
39590 <bitOffset>31</bitOffset>
39591 <bitWidth>1</bitWidth>
39599 <description>System control block
</description>
39600 <groupName>SCB
</groupName>
39601 <baseAddress>0xE000ED00</baseAddress>
39603 <offset>0x0</offset>
39605 <usage>registers
</usage>
39610 <displayName>CPUID
</displayName>
39611 <description>CPUID base register
</description>
39612 <addressOffset>0x0</addressOffset>
39614 <access>read-only
</access>
39615 <resetValue>0x410FC241</resetValue>
39618 <name>Revision
</name>
39619 <description>Revision number
</description>
39620 <bitOffset>0</bitOffset>
39621 <bitWidth>4</bitWidth>
39624 <name>PartNo
</name>
39625 <description>Part number of the
39626 processor
</description>
39627 <bitOffset>4</bitOffset>
39628 <bitWidth>12</bitWidth>
39631 <name>Constant
</name>
39632 <description>Reads as
0xF</description>
39633 <bitOffset>16</bitOffset>
39634 <bitWidth>4</bitWidth>
39637 <name>Variant
</name>
39638 <description>Variant number
</description>
39639 <bitOffset>20</bitOffset>
39640 <bitWidth>4</bitWidth>
39643 <name>Implementer
</name>
39644 <description>Implementer code
</description>
39645 <bitOffset>24</bitOffset>
39646 <bitWidth>8</bitWidth>
39652 <displayName>ICSR
</displayName>
39653 <description>Interrupt control and state
39654 register
</description>
39655 <addressOffset>0x4</addressOffset>
39657 <access>read-write
</access>
39658 <resetValue>0x00000000</resetValue>
39661 <name>VECTACTIVE
</name>
39662 <description>Active vector
</description>
39663 <bitOffset>0</bitOffset>
39664 <bitWidth>9</bitWidth>
39667 <name>RETTOBASE
</name>
39668 <description>Return to base level
</description>
39669 <bitOffset>11</bitOffset>
39670 <bitWidth>1</bitWidth>
39673 <name>VECTPENDING
</name>
39674 <description>Pending vector
</description>
39675 <bitOffset>12</bitOffset>
39676 <bitWidth>7</bitWidth>
39679 <name>ISRPENDING
</name>
39680 <description>Interrupt pending flag
</description>
39681 <bitOffset>22</bitOffset>
39682 <bitWidth>1</bitWidth>
39685 <name>PENDSTCLR
</name>
39686 <description>SysTick exception clear-pending
39688 <bitOffset>25</bitOffset>
39689 <bitWidth>1</bitWidth>
39692 <name>PENDSTSET
</name>
39693 <description>SysTick exception set-pending
39695 <bitOffset>26</bitOffset>
39696 <bitWidth>1</bitWidth>
39699 <name>PENDSVCLR
</name>
39700 <description>PendSV clear-pending bit
</description>
39701 <bitOffset>27</bitOffset>
39702 <bitWidth>1</bitWidth>
39705 <name>PENDSVSET
</name>
39706 <description>PendSV set-pending bit
</description>
39707 <bitOffset>28</bitOffset>
39708 <bitWidth>1</bitWidth>
39711 <name>NMIPENDSET
</name>
39712 <description>NMI set-pending bit.
</description>
39713 <bitOffset>31</bitOffset>
39714 <bitWidth>1</bitWidth>
39720 <displayName>VTOR
</displayName>
39721 <description>Vector table offset register
</description>
39722 <addressOffset>0x8</addressOffset>
39724 <access>read-write
</access>
39725 <resetValue>0x00000000</resetValue>
39728 <name>TBLOFF
</name>
39729 <description>Vector table base offset
39730 field
</description>
39731 <bitOffset>9</bitOffset>
39732 <bitWidth>21</bitWidth>
39738 <displayName>AIRCR
</displayName>
39739 <description>Application interrupt and reset control
39740 register
</description>
39741 <addressOffset>0xC</addressOffset>
39743 <access>read-write
</access>
39744 <resetValue>0x00000000</resetValue>
39747 <name>VECTRESET
</name>
39748 <description>VECTRESET
</description>
39749 <bitOffset>0</bitOffset>
39750 <bitWidth>1</bitWidth>
39753 <name>VECTCLRACTIVE
</name>
39754 <description>VECTCLRACTIVE
</description>
39755 <bitOffset>1</bitOffset>
39756 <bitWidth>1</bitWidth>
39759 <name>SYSRESETREQ
</name>
39760 <description>SYSRESETREQ
</description>
39761 <bitOffset>2</bitOffset>
39762 <bitWidth>1</bitWidth>
39765 <name>PRIGROUP
</name>
39766 <description>PRIGROUP
</description>
39767 <bitOffset>8</bitOffset>
39768 <bitWidth>3</bitWidth>
39771 <name>ENDIANESS
</name>
39772 <description>ENDIANESS
</description>
39773 <bitOffset>15</bitOffset>
39774 <bitWidth>1</bitWidth>
39777 <name>VECTKEYSTAT
</name>
39778 <description>Register key
</description>
39779 <bitOffset>16</bitOffset>
39780 <bitWidth>16</bitWidth>
39786 <displayName>SCR
</displayName>
39787 <description>System control register
</description>
39788 <addressOffset>0x10</addressOffset>
39790 <access>read-write
</access>
39791 <resetValue>0x00000000</resetValue>
39794 <name>SLEEPONEXIT
</name>
39795 <description>SLEEPONEXIT
</description>
39796 <bitOffset>1</bitOffset>
39797 <bitWidth>1</bitWidth>
39800 <name>SLEEPDEEP
</name>
39801 <description>SLEEPDEEP
</description>
39802 <bitOffset>2</bitOffset>
39803 <bitWidth>1</bitWidth>
39806 <name>SEVEONPEND
</name>
39807 <description>Send Event on Pending bit
</description>
39808 <bitOffset>4</bitOffset>
39809 <bitWidth>1</bitWidth>
39815 <displayName>CCR
</displayName>
39816 <description>Configuration and control
39817 register
</description>
39818 <addressOffset>0x14</addressOffset>
39820 <access>read-write
</access>
39821 <resetValue>0x00000000</resetValue>
39824 <name>NONBASETHRDENA
</name>
39825 <description>Configures how the processor enters
39826 Thread mode
</description>
39827 <bitOffset>0</bitOffset>
39828 <bitWidth>1</bitWidth>
39831 <name>USERSETMPEND
</name>
39832 <description>USERSETMPEND
</description>
39833 <bitOffset>1</bitOffset>
39834 <bitWidth>1</bitWidth>
39837 <name>UNALIGN__TRP
</name>
39838 <description>UNALIGN_ TRP
</description>
39839 <bitOffset>3</bitOffset>
39840 <bitWidth>1</bitWidth>
39843 <name>DIV_0_TRP
</name>
39844 <description>DIV_0_TRP
</description>
39845 <bitOffset>4</bitOffset>
39846 <bitWidth>1</bitWidth>
39849 <name>BFHFNMIGN
</name>
39850 <description>BFHFNMIGN
</description>
39851 <bitOffset>8</bitOffset>
39852 <bitWidth>1</bitWidth>
39855 <name>STKALIGN
</name>
39856 <description>STKALIGN
</description>
39857 <bitOffset>9</bitOffset>
39858 <bitWidth>1</bitWidth>
39864 <displayName>SHPR1
</displayName>
39865 <description>System handler priority
39866 registers
</description>
39867 <addressOffset>0x18</addressOffset>
39869 <access>read-write
</access>
39870 <resetValue>0x00000000</resetValue>
39874 <description>Priority of system handler
39876 <bitOffset>0</bitOffset>
39877 <bitWidth>8</bitWidth>
39881 <description>Priority of system handler
39883 <bitOffset>8</bitOffset>
39884 <bitWidth>8</bitWidth>
39888 <description>Priority of system handler
39890 <bitOffset>16</bitOffset>
39891 <bitWidth>8</bitWidth>
39897 <displayName>SHPR2
</displayName>
39898 <description>System handler priority
39899 registers
</description>
39900 <addressOffset>0x1C</addressOffset>
39902 <access>read-write
</access>
39903 <resetValue>0x00000000</resetValue>
39906 <name>PRI_11
</name>
39907 <description>Priority of system handler
39909 <bitOffset>24</bitOffset>
39910 <bitWidth>8</bitWidth>
39916 <displayName>SHPR3
</displayName>
39917 <description>System handler priority
39918 registers
</description>
39919 <addressOffset>0x20</addressOffset>
39921 <access>read-write
</access>
39922 <resetValue>0x00000000</resetValue>
39925 <name>PRI_14
</name>
39926 <description>Priority of system handler
39928 <bitOffset>16</bitOffset>
39929 <bitWidth>8</bitWidth>
39932 <name>PRI_15
</name>
39933 <description>Priority of system handler
39935 <bitOffset>24</bitOffset>
39936 <bitWidth>8</bitWidth>
39942 <displayName>SHCRS
</displayName>
39943 <description>System handler control and state
39944 register
</description>
39945 <addressOffset>0x24</addressOffset>
39947 <access>read-write
</access>
39948 <resetValue>0x00000000</resetValue>
39951 <name>MEMFAULTACT
</name>
39952 <description>Memory management fault exception active
39954 <bitOffset>0</bitOffset>
39955 <bitWidth>1</bitWidth>
39958 <name>BUSFAULTACT
</name>
39959 <description>Bus fault exception active
39961 <bitOffset>1</bitOffset>
39962 <bitWidth>1</bitWidth>
39965 <name>USGFAULTACT
</name>
39966 <description>Usage fault exception active
39968 <bitOffset>3</bitOffset>
39969 <bitWidth>1</bitWidth>
39972 <name>SVCALLACT
</name>
39973 <description>SVC call active bit
</description>
39974 <bitOffset>7</bitOffset>
39975 <bitWidth>1</bitWidth>
39978 <name>MONITORACT
</name>
39979 <description>Debug monitor active bit
</description>
39980 <bitOffset>8</bitOffset>
39981 <bitWidth>1</bitWidth>
39984 <name>PENDSVACT
</name>
39985 <description>PendSV exception active
39987 <bitOffset>10</bitOffset>
39988 <bitWidth>1</bitWidth>
39991 <name>SYSTICKACT
</name>
39992 <description>SysTick exception active
39994 <bitOffset>11</bitOffset>
39995 <bitWidth>1</bitWidth>
39998 <name>USGFAULTPENDED
</name>
39999 <description>Usage fault exception pending
40001 <bitOffset>12</bitOffset>
40002 <bitWidth>1</bitWidth>
40005 <name>MEMFAULTPENDED
</name>
40006 <description>Memory management fault exception
40007 pending bit
</description>
40008 <bitOffset>13</bitOffset>
40009 <bitWidth>1</bitWidth>
40012 <name>BUSFAULTPENDED
</name>
40013 <description>Bus fault exception pending
40015 <bitOffset>14</bitOffset>
40016 <bitWidth>1</bitWidth>
40019 <name>SVCALLPENDED
</name>
40020 <description>SVC call pending bit
</description>
40021 <bitOffset>15</bitOffset>
40022 <bitWidth>1</bitWidth>
40025 <name>MEMFAULTENA
</name>
40026 <description>Memory management fault enable
40028 <bitOffset>16</bitOffset>
40029 <bitWidth>1</bitWidth>
40032 <name>BUSFAULTENA
</name>
40033 <description>Bus fault enable bit
</description>
40034 <bitOffset>17</bitOffset>
40035 <bitWidth>1</bitWidth>
40038 <name>USGFAULTENA
</name>
40039 <description>Usage fault enable bit
</description>
40040 <bitOffset>18</bitOffset>
40041 <bitWidth>1</bitWidth>
40046 <name>CFSR_UFSR_BFSR_MMFSR
</name>
40047 <displayName>CFSR_UFSR_BFSR_MMFSR
</displayName>
40048 <description>Configurable fault status
40049 register
</description>
40050 <addressOffset>0x28</addressOffset>
40052 <access>read-write
</access>
40053 <resetValue>0x00000000</resetValue>
40056 <name>IACCVIOL
</name>
40057 <description>Instruction access violation
40059 <bitOffset>1</bitOffset>
40060 <bitWidth>1</bitWidth>
40063 <name>MUNSTKERR
</name>
40064 <description>Memory manager fault on unstacking for a
40065 return from exception
</description>
40066 <bitOffset>3</bitOffset>
40067 <bitWidth>1</bitWidth>
40070 <name>MSTKERR
</name>
40071 <description>Memory manager fault on stacking for
40072 exception entry.
</description>
40073 <bitOffset>4</bitOffset>
40074 <bitWidth>1</bitWidth>
40077 <name>MLSPERR
</name>
40078 <description>MLSPERR
</description>
40079 <bitOffset>5</bitOffset>
40080 <bitWidth>1</bitWidth>
40083 <name>MMARVALID
</name>
40084 <description>Memory Management Fault Address Register
40085 (MMAR) valid flag
</description>
40086 <bitOffset>7</bitOffset>
40087 <bitWidth>1</bitWidth>
40090 <name>IBUSERR
</name>
40091 <description>Instruction bus error
</description>
40092 <bitOffset>8</bitOffset>
40093 <bitWidth>1</bitWidth>
40096 <name>PRECISERR
</name>
40097 <description>Precise data bus error
</description>
40098 <bitOffset>9</bitOffset>
40099 <bitWidth>1</bitWidth>
40102 <name>IMPRECISERR
</name>
40103 <description>Imprecise data bus error
</description>
40104 <bitOffset>10</bitOffset>
40105 <bitWidth>1</bitWidth>
40108 <name>UNSTKERR
</name>
40109 <description>Bus fault on unstacking for a return
40110 from exception
</description>
40111 <bitOffset>11</bitOffset>
40112 <bitWidth>1</bitWidth>
40115 <name>STKERR
</name>
40116 <description>Bus fault on stacking for exception
40117 entry
</description>
40118 <bitOffset>12</bitOffset>
40119 <bitWidth>1</bitWidth>
40122 <name>LSPERR
</name>
40123 <description>Bus fault on floating-point lazy state
40124 preservation
</description>
40125 <bitOffset>13</bitOffset>
40126 <bitWidth>1</bitWidth>
40129 <name>BFARVALID
</name>
40130 <description>Bus Fault Address Register (BFAR) valid
40132 <bitOffset>15</bitOffset>
40133 <bitWidth>1</bitWidth>
40136 <name>UNDEFINSTR
</name>
40137 <description>Undefined instruction usage
40138 fault
</description>
40139 <bitOffset>16</bitOffset>
40140 <bitWidth>1</bitWidth>
40143 <name>INVSTATE
</name>
40144 <description>Invalid state usage fault
</description>
40145 <bitOffset>17</bitOffset>
40146 <bitWidth>1</bitWidth>
40150 <description>Invalid PC load usage
40151 fault
</description>
40152 <bitOffset>18</bitOffset>
40153 <bitWidth>1</bitWidth>
40157 <description>No coprocessor usage
40158 fault.
</description>
40159 <bitOffset>19</bitOffset>
40160 <bitWidth>1</bitWidth>
40163 <name>UNALIGNED
</name>
40164 <description>Unaligned access usage
40165 fault
</description>
40166 <bitOffset>24</bitOffset>
40167 <bitWidth>1</bitWidth>
40170 <name>DIVBYZERO
</name>
40171 <description>Divide by zero usage fault
</description>
40172 <bitOffset>25</bitOffset>
40173 <bitWidth>1</bitWidth>
40179 <displayName>HFSR
</displayName>
40180 <description>Hard fault status register
</description>
40181 <addressOffset>0x2C</addressOffset>
40183 <access>read-write
</access>
40184 <resetValue>0x00000000</resetValue>
40187 <name>VECTTBL
</name>
40188 <description>Vector table hard fault
</description>
40189 <bitOffset>1</bitOffset>
40190 <bitWidth>1</bitWidth>
40193 <name>FORCED
</name>
40194 <description>Forced hard fault
</description>
40195 <bitOffset>30</bitOffset>
40196 <bitWidth>1</bitWidth>
40199 <name>DEBUG_VT
</name>
40200 <description>Reserved for Debug use
</description>
40201 <bitOffset>31</bitOffset>
40202 <bitWidth>1</bitWidth>
40208 <displayName>MMFAR
</displayName>
40209 <description>Memory management fault address
40210 register
</description>
40211 <addressOffset>0x34</addressOffset>
40213 <access>read-write
</access>
40214 <resetValue>0x00000000</resetValue>
40218 <description>Memory management fault
40219 address
</description>
40220 <bitOffset>0</bitOffset>
40221 <bitWidth>32</bitWidth>
40227 <displayName>BFAR
</displayName>
40228 <description>Bus fault address register
</description>
40229 <addressOffset>0x38</addressOffset>
40231 <access>read-write
</access>
40232 <resetValue>0x00000000</resetValue>
40236 <description>Bus fault address
</description>
40237 <bitOffset>0</bitOffset>
40238 <bitWidth>32</bitWidth>
40244 <displayName>AFSR
</displayName>
40245 <description>Auxiliary fault status
40246 register
</description>
40247 <addressOffset>0x3C</addressOffset>
40249 <access>read-write
</access>
40250 <resetValue>0x00000000</resetValue>
40253 <name>IMPDEF
</name>
40254 <description>Implementation defined
</description>
40255 <bitOffset>0</bitOffset>
40256 <bitWidth>32</bitWidth>
40263 <name>NVIC_STIR
</name>
40264 <description>Nested vectored interrupt
40265 controller
</description>
40266 <groupName>NVIC
</groupName>
40267 <baseAddress>0xE000EF00</baseAddress>
40269 <offset>0x0</offset>
40271 <usage>registers
</usage>
40276 <displayName>STIR
</displayName>
40277 <description>Software trigger interrupt
40278 register
</description>
40279 <addressOffset>0x0</addressOffset>
40281 <access>read-write
</access>
40282 <resetValue>0x00000000</resetValue>
40286 <description>Software generated interrupt
40288 <bitOffset>0</bitOffset>
40289 <bitWidth>9</bitWidth>
40296 <name>FPU_CPACR
</name>
40297 <description>Floating point unit CPACR
</description>
40298 <groupName>FPU
</groupName>
40299 <baseAddress>0xE000ED88</baseAddress>
40301 <offset>0x0</offset>
40303 <usage>registers
</usage>
40308 <displayName>CPACR
</displayName>
40309 <description>Coprocessor access control
40310 register
</description>
40311 <addressOffset>0x0</addressOffset>
40313 <access>read-write
</access>
40314 <resetValue>0x0000000</resetValue>
40318 <description>CP
</description>
40319 <bitOffset>20</bitOffset>
40320 <bitWidth>4</bitWidth>
40327 <name>SCB_ACTRL
</name>
40328 <description>System control block ACTLR
</description>
40329 <groupName>SCB
</groupName>
40330 <baseAddress>0xE000E008</baseAddress>
40332 <offset>0x0</offset>
40334 <usage>registers
</usage>
40339 <displayName>ACTRL
</displayName>
40340 <description>Auxiliary control register
</description>
40341 <addressOffset>0x0</addressOffset>
40343 <access>read-write
</access>
40344 <resetValue>0x00000000</resetValue>
40347 <name>DISMCYCINT
</name>
40348 <description>DISMCYCINT
</description>
40349 <bitOffset>0</bitOffset>
40350 <bitWidth>1</bitWidth>
40353 <name>DISDEFWBUF
</name>
40354 <description>DISDEFWBUF
</description>
40355 <bitOffset>1</bitOffset>
40356 <bitWidth>1</bitWidth>
40359 <name>DISFOLD
</name>
40360 <description>DISFOLD
</description>
40361 <bitOffset>2</bitOffset>
40362 <bitWidth>1</bitWidth>
40365 <name>DISFPCA
</name>
40366 <description>DISFPCA
</description>
40367 <bitOffset>8</bitOffset>
40368 <bitWidth>1</bitWidth>
40371 <name>DISOOFP
</name>
40372 <description>DISOOFP
</description>
40373 <bitOffset>9</bitOffset>
40374 <bitWidth>1</bitWidth>