src/main/drivers/dma_at32f43x.c

   1 /*
   2  * This file is part of Cleanflight.
   3  *
   4  * Cleanflight is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Cleanflight is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with Cleanflight.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <stdbool.h>
  19 #include <stdint.h>
  20 #include <string.h>
  21
  22 #include <platform.h>
  23
  24 #include "build/debug.h"
  25 #include "common/utils.h"
  26 #include "drivers/nvic.h"
  27 #include "drivers/dma.h"
  28 #include "drivers/rcc.h"
  29
  30 /*
  31  * DMA descriptors.
  32  */
  33 static dmaChannelDescriptor_t dmaDescriptors[] = {
  34     [0]  = DEFINE_DMA_CHANNEL(1, 1, 0),     // DMA1_ST1
  35     [1]  = DEFINE_DMA_CHANNEL(1, 2, 4),     // DMA1_ST2
  36     [2]  = DEFINE_DMA_CHANNEL(1, 3, 8),    // DMA1_ST3
  37     [3]  = DEFINE_DMA_CHANNEL(1, 4, 12),    // DMA1_ST4
  38     [4]  = DEFINE_DMA_CHANNEL(1, 5, 16),    // DMA1_ST5
  39     [5]  = DEFINE_DMA_CHANNEL(1, 6, 20),    // DMA1_ST6
  40     [6]  = DEFINE_DMA_CHANNEL(1, 7, 24),    // DMA1_ST7
  41
  42     [7]  = DEFINE_DMA_CHANNEL(2, 1, 0),     // DMA2_ST1
  43     [8] =  DEFINE_DMA_CHANNEL(2, 2, 4),    // DMA2_ST2
  44     [9] =  DEFINE_DMA_CHANNEL(2, 3, 8),    // DMA2_ST3
  45     [10] = DEFINE_DMA_CHANNEL(2, 4, 12),    // DMA2_ST4
  46     [11] = DEFINE_DMA_CHANNEL(2, 5, 16),    // DMA2_ST5
  47     [12] = DEFINE_DMA_CHANNEL(2, 6, 20),    // DMA2_ST6
  48     [13] = DEFINE_DMA_CHANNEL(2, 7, 24)     // DMA2_ST7
  49     /*
  50     //EDMA
  51     [14] = DEFINE_EDMA_CHANNEL(0, 1, 6),     // EDMA_1
  52     [15] = DEFINE_EDMA_CHANNEL(0, 2, 12),    // EDMA_2
  53     [16] = DEFINE_EDMA_CHANNEL(0, 3, 18),    // EDMA_3
  54     [17] = DEFINE_EDMA_CHANNEL(0, 4, 24),    // EDMA_4
  55     [18] = DEFINE_EDMA_CHANNEL(0, 5, 30),    // EDMA_5
  56     [19] = DEFINE_EDMA_CHANNEL(0, 6, 36),    // EDMA_6
  57     [20] = DEFINE_EDMA_CHANNEL(0, 7, 42)     // EDMA_7
  58     [21] = DEFINE_EDMA_CHANNEL(0, 8, 48)     // EDMA_8
  59     */
  60 };
  61
  62 /*
  63  * DMA IRQ Handlers
  64  */
  65
  66 DEFINE_DMA_IRQ_HANDLER(1, 1, 0)
  67 DEFINE_DMA_IRQ_HANDLER(1, 2, 1)
  68 DEFINE_DMA_IRQ_HANDLER(1, 3, 2)
  69 DEFINE_DMA_IRQ_HANDLER(1, 4, 3)
  70 DEFINE_DMA_IRQ_HANDLER(1, 5, 4)
  71 DEFINE_DMA_IRQ_HANDLER(1, 6, 5)
  72 DEFINE_DMA_IRQ_HANDLER(1, 7, 6)
  73
  74 DEFINE_DMA_IRQ_HANDLER(2, 1, 7)
  75 DEFINE_DMA_IRQ_HANDLER(2, 2, 8)
  76 DEFINE_DMA_IRQ_HANDLER(2, 3, 9)
  77 DEFINE_DMA_IRQ_HANDLER(2, 4, 10)
  78 DEFINE_DMA_IRQ_HANDLER(2, 5, 11)
  79 DEFINE_DMA_IRQ_HANDLER(2, 6, 12)
  80 DEFINE_DMA_IRQ_HANDLER(2, 7, 13)
  81 /*
  82 // edma
  83 DEFINE_EDMA_IRQ_HANDLER(0, 0, 16)
  84 DEFINE_EDMA_IRQ_HANDLER(0, 1, 17)
  85 DEFINE_EDMA_IRQ_HANDLER(0, 2, 18)
  86 DEFINE_EDMA_IRQ_HANDLER(0, 3, 19)
  87 DEFINE_EDMA_IRQ_HANDLER(0, 4, 20)
  88 DEFINE_EDMA_IRQ_HANDLER(0, 5, 21)
  89 DEFINE_EDMA_IRQ_HANDLER(0, 6, 22)
  90 DEFINE_EDMA_IRQ_HANDLER(0, 7, 23)
  91 DEFINE_EDMA_IRQ_HANDLER(0, 8, 24)
  92 */
  93 // Obtain DMA_t through DMA ID & DMA channel
  94 DMA_t dmaGetByTag(dmaTag_t tag)
  95 {
  96     for (unsigned i = 0; i < ARRAYLEN(dmaDescriptors); i++) {
  97         // On F4/F7 we match only DMA and Stream. Channel is needed when connecting DMA to peripheral
  98         if (DMATAG_GET_DMA(dmaDescriptors[i].tag) == DMATAG_GET_DMA(tag) && DMATAG_GET_STREAM(dmaDescriptors[i].tag) == DMATAG_GET_STREAM(tag)) {
  99             return (DMA_t)&dmaDescriptors[i];
 100         }
 101     }
 102
 103     return (DMA_t) NULL;
 104 }
 105
 106 void dmaEnableClock(DMA_t dma)
 107 {
 108     if (dma->dma == DMA1) {
 109         RCC_ClockCmd(RCC_AHB1(DMA1), ENABLE);
 110     }
 111     else {
 112         RCC_ClockCmd(RCC_AHB1(DMA2), ENABLE);
 113     }
 114     dmamux_enable(dma->dma,TRUE);
 115 }
 116
 117 void dmaMuxEnable(DMA_t dma, uint32_t dmaMuxid)
 118 {
 119         dmamux_init(dma->dmaMuxref, dmaMuxid);
 120 }
 121
 122 resourceOwner_e dmaGetOwner(DMA_t dma)
 123 {
 124     return dma->owner;
 125 }
 126
 127 void dmaInit(DMA_t dma, resourceOwner_e owner, uint8_t resourceIndex)
 128 {
 129     dmaEnableClock(dma);
 130     dma->owner = owner;
 131     dma->resourceIndex = resourceIndex;
 132 }
 133
 134 void dmaSetHandler(DMA_t dma, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
 135 {
 136     dmaEnableClock(dma);
 137
 138     dma->irqHandlerCallback = callback;
 139     dma->userParam = userParam;
 140         nvic_irq_enable(dma->irqNumber, priority,0);
 141
 142 }
 143 // This function is not used , use ChannelByTag instead
 144 uint32_t dmaGetChannelByTag(dmaTag_t tag)
 145 {
 146     static const dma_channel_type * dmaChannel[14] = { DMA1_CHANNEL1, DMA1_CHANNEL2, DMA1_CHANNEL3, DMA1_CHANNEL4, DMA1_CHANNEL5, DMA1_CHANNEL6, DMA1_CHANNEL7,
 147     DMA2_CHANNEL1, DMA2_CHANNEL2, DMA2_CHANNEL3, DMA2_CHANNEL4, DMA2_CHANNEL5, DMA2_CHANNEL6, DMA2_CHANNEL7,
 148      };
 149
 150     return (uint32_t) dmaChannel[(DMATAG_GET_DMA(tag)-1)*7 + DMATAG_GET_STREAM(tag)-1];
 151 }
 152
 153 // Obtain DMA_t through DMA channel
 154 DMA_t dmaGetByRef(const dma_channel_type* ref)
 155 {
 156     for (unsigned i = 0; i < ARRAYLEN(dmaDescriptors); i++) {
 157         if (ref == dmaDescriptors[i].ref) {
 158             return &dmaDescriptors[i];
 159         }
 160     }
 161     return NULL;
 162 }
 163
 164 /*
 165 DMA_t dmaGetByRef(const edma_stream_type* ref)
 166 {
 167     for (unsigned i = 0; i < ARRAYLEN(dmaDescriptors); i++) {
 168         if (ref == dmaDescriptors[i].sref) {
 169             return &dmaDescriptors[i];
 170         }
 171     }
 172     return NULL;
 173 }
 174 */