Blackbox device type 'file' (SITL) considered working when file handler is available
[inav.git] / src / main / drivers / dma_stm32h7xx.c
blob3c7c9d75fa96a57f1bc24987f18d88b41a2f6586
1 /*
2 * This file is part of Cleanflight and Betaflight.
4 * Cleanflight and Betaflight are free software. You can redistribute
5 * this software and/or modify this software under the terms of the
6 * GNU General Public License as published by the Free Software
7 * Foundation, either version 3 of the License, or (at your option)
8 * any later version.
10 * Cleanflight and Betaflight are distributed in the hope that they
11 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
12 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
13 * See the GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this software.
18 * If not, see <http://www.gnu.org/licenses/>.
21 #include <stdbool.h>
22 #include <stdint.h>
23 #include <string.h>
25 #include <platform.h>
27 #include "common/utils.h"
28 #include "drivers/nvic.h"
29 #include "drivers/dma.h"
30 #include "drivers/rcc.h"
33 * DMA descriptors.
35 static dmaChannelDescriptor_t dmaDescriptors[] = {
36 [0] = DEFINE_DMA_CHANNEL(1, 0, 0), // DMA1_ST0
37 [1] = DEFINE_DMA_CHANNEL(1, 1, 6), // DMA1_ST1
38 [2] = DEFINE_DMA_CHANNEL(1, 2, 16), // DMA1_ST2
39 [3] = DEFINE_DMA_CHANNEL(1, 3, 22), // DMA1_ST3
40 [4] = DEFINE_DMA_CHANNEL(1, 4, 32), // DMA1_ST4
41 [5] = DEFINE_DMA_CHANNEL(1, 5, 38), // DMA1_ST5
42 [6] = DEFINE_DMA_CHANNEL(1, 6, 48), // DMA1_ST6
43 [7] = DEFINE_DMA_CHANNEL(1, 7, 54), // DMA1_ST7
45 [8] = DEFINE_DMA_CHANNEL(2, 0, 0), // DMA2_ST0
46 [9] = DEFINE_DMA_CHANNEL(2, 1, 6), // DMA2_ST1
47 [10] = DEFINE_DMA_CHANNEL(2, 2, 16), // DMA2_ST2
48 [11] = DEFINE_DMA_CHANNEL(2, 3, 22), // DMA2_ST3
49 [12] = DEFINE_DMA_CHANNEL(2, 4, 32), // DMA2_ST4
50 [13] = DEFINE_DMA_CHANNEL(2, 5, 38), // DMA2_ST5
51 [14] = DEFINE_DMA_CHANNEL(2, 6, 48), // DMA2_ST6
52 [15] = DEFINE_DMA_CHANNEL(2, 7, 54), // DMA2_ST7
56 * DMA IRQ Handlers
58 DEFINE_DMA_IRQ_HANDLER(1, 0, 0) // DMA1_ST0
59 DEFINE_DMA_IRQ_HANDLER(1, 1, 1) // DMA1_ST1
60 DEFINE_DMA_IRQ_HANDLER(1, 2, 2) // DMA1_ST2
61 DEFINE_DMA_IRQ_HANDLER(1, 3, 3) // DMA1_ST3
62 DEFINE_DMA_IRQ_HANDLER(1, 4, 4) // DMA1_ST4
63 DEFINE_DMA_IRQ_HANDLER(1, 5, 5) // DMA1_ST5
64 DEFINE_DMA_IRQ_HANDLER(1, 6, 6) // DMA1_ST6
65 DEFINE_DMA_IRQ_HANDLER(1, 7, 7) // DMA1_ST7
66 DEFINE_DMA_IRQ_HANDLER(2, 0, 8) // DMA2_ST0
67 DEFINE_DMA_IRQ_HANDLER(2, 1, 9) // DMA2_ST1
68 DEFINE_DMA_IRQ_HANDLER(2, 2, 10) // DMA2_ST2
69 DEFINE_DMA_IRQ_HANDLER(2, 3, 11) // DMA2_ST3
70 DEFINE_DMA_IRQ_HANDLER(2, 4, 12) // DMA2_ST4
71 DEFINE_DMA_IRQ_HANDLER(2, 5, 13) // DMA2_ST5
72 DEFINE_DMA_IRQ_HANDLER(2, 6, 14) // DMA2_ST6
73 DEFINE_DMA_IRQ_HANDLER(2, 7, 15) // DMA2_ST7
75 DMA_t dmaGetByTag(dmaTag_t tag)
77 for (unsigned i = 0; i < ARRAYLEN(dmaDescriptors); i++) {
78 if (DMATAG_GET_DMA(dmaDescriptors[i].tag) == DMATAG_GET_DMA(tag) && DMATAG_GET_STREAM(dmaDescriptors[i].tag) == DMATAG_GET_STREAM(tag)) {
79 return (DMA_t)&dmaDescriptors[i];
83 return (DMA_t) NULL;
86 void dmaEnableClock(DMA_t dma)
88 if (dma->dma == DMA1) {
89 RCC_ClockCmd(RCC_AHB1(DMA1), ENABLE);
91 else {
92 RCC_ClockCmd(RCC_AHB1(DMA2), ENABLE);
96 resourceOwner_e dmaGetOwner(DMA_t dma)
98 return dma->owner;
101 void dmaInit(DMA_t dma, resourceOwner_e owner, uint8_t resourceIndex)
103 dmaEnableClock(dma);
104 dma->owner = owner;
105 dma->resourceIndex = resourceIndex;
108 void dmaSetHandler(DMA_t dma, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
110 dmaEnableClock(dma);
112 dma->irqHandlerCallback = callback;
113 dma->userParam = userParam;
115 HAL_NVIC_SetPriority(dma->irqNumber, priority, 0);
116 HAL_NVIC_EnableIRQ(dma->irqNumber);
119 DMA_t dmaGetByRef(const DMA_Stream_TypeDef* ref)
121 for (unsigned i = 0; i < ARRAYLEN(dmaDescriptors); i++) {
122 if (ref == dmaDescriptors[i].ref) {
123 return &dmaDescriptors[i];
127 return NULL;