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Blackbox device type 'file' (SITL) considered working when file handler is available
[inav.git] / src / main / drivers / i2c_application.c
blobada893d65f990776ca3143bfaacc6a6f72298640
1 /**
2 **************************************************************************
3 * @file i2c_application.c
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief the driver library of the i2c peripheral
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 #include "i2c_application.h"
28
29 /** @addtogroup AT32F435_437_middlewares_i2c_application_library
30 * @{
31 */
32
33 /**
34 * @brief get the dma transfer direction flag through the channel
35 */
36 #define DMA_GET_REQUEST(DMA_CHANNEL) \
37 (((uint32_t)(DMA_CHANNEL) == ((uint32_t)hi2c->dma_tx_channel)) ? I2C_DMA_REQUEST_TX : I2C_DMA_REQUEST_RX)
38
39 /**
40 * @brief get the dma transfer complete flag through the channel
41 */
42 #define DMA_GET_TC_FLAG(DMA_CHANNEL) \
43 (((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL1))? DMA1_FDT1_FLAG : \
44 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL2))? DMA1_FDT2_FLAG : \
45 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL3))? DMA1_FDT3_FLAG : \
46 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL4))? DMA1_FDT4_FLAG : \
47 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL5))? DMA1_FDT5_FLAG : \
48 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL6))? DMA1_FDT6_FLAG : \
49 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL7))? DMA1_FDT7_FLAG : \
50 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL1))? DMA2_FDT1_FLAG : \
51 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL2))? DMA2_FDT2_FLAG : \
52 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL3))? DMA2_FDT3_FLAG : \
53 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL4))? DMA2_FDT4_FLAG : \
54 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL5))? DMA2_FDT5_FLAG : \
55 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL6))? DMA2_FDT6_FLAG : \
56 DMA2_FDT7_FLAG)
57
58 /**
59 * @brief get the dma half transfer flag through the channel
60 */
61 #define DMA_GET_HT_FLAG(DMA_CHANNEL) \
62 (((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL1))? DMA1_HDT1_FLAG : \
63 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL2))? DMA1_HDT2_FLAG : \
64 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL3))? DMA1_HDT3_FLAG : \
65 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL4))? DMA1_HDT4_FLAG : \
66 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL5))? DMA1_HDT5_FLAG : \
67 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL6))? DMA1_HDT6_FLAG : \
68 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL7))? DMA1_HDT7_FLAG : \
69 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL1))? DMA2_HDT1_FLAG : \
70 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL2))? DMA2_HDT2_FLAG : \
71 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL3))? DMA2_HDT3_FLAG : \
72 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL4))? DMA2_HDT4_FLAG : \
73 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL5))? DMA2_HDT5_FLAG : \
74 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL6))? DMA2_HDT6_FLAG : \
75 DMA2_HDT7_FLAG)
76
77 /**
78 * @brief get the dma transfer error flag through the channel
79 */
80 #define DMA_GET_TERR_FLAG(DMA_CHANNEL) \
81 (((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL1))? DMA1_DTERR1_FLAG : \
82 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL2))? DMA1_DTERR2_FLAG : \
83 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL3))? DMA1_DTERR3_FLAG : \
84 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL4))? DMA1_DTERR4_FLAG : \
85 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL5))? DMA1_DTERR5_FLAG : \
86 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL6))? DMA1_DTERR6_FLAG : \
87 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA1_CHANNEL7))? DMA1_DTERR7_FLAG : \
88 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL1))? DMA2_DTERR1_FLAG : \
89 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL2))? DMA2_DTERR2_FLAG : \
90 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL3))? DMA2_DTERR3_FLAG : \
91 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL4))? DMA2_DTERR4_FLAG : \
92 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL5))? DMA2_DTERR5_FLAG : \
93 ((uint32_t)(DMA_CHANNEL) == ((uint32_t)DMA2_CHANNEL6))? DMA2_DTERR6_FLAG : \
94 DMA2_DTERR7_FLAG)
95
96 /**
97 * @brief i2c transmission status
98 */
99 #define I2C_START 0
100 #define I2C_END 1
101
102
103 /**
104 * @brief i2c peripheral initialization.
105 * @param hi2c: the handle points to the operation information.
106 * @retval none.
107 */
108 void i2c_config(i2c_handle_type* hi2c)
109 {
110 /* reset i2c peripheral */
111 i2c_reset(hi2c->i2cx);
112
113 /* i2c peripheral initialization */
114 i2c_lowlevel_init(hi2c);
115
116 /* i2c peripheral enable */
117 i2c_enable(hi2c->i2cx, TRUE);
118 }
119
120 /**
121 * @brief refresh i2c register.
122 * @param hi2c: the handle points to the operation information.
123 * @retval none.
124 */
125 void i2c_refresh_txdt_register(i2c_handle_type* hi2c)
126 {
127 /* clear tdis flag */
128 if (i2c_flag_get(hi2c->i2cx, I2C_TDIS_FLAG) != RESET)
129 {
130 hi2c->i2cx->txdt = 0x00;
131 }
132
133 /* refresh txdt register*/
134 if (i2c_flag_get(hi2c->i2cx, I2C_TDBE_FLAG) == RESET)
135 {
136 hi2c->i2cx->sts_bit.tdbe = 1;
137 }
138 }
139
140 /**
141 * @brief reset ctrl2 register.
142 * @param hi2c: the handle points to the operation information.
143 * @retval none.
144 */
145 void i2c_reset_ctrl2_register(i2c_handle_type* hi2c)
146 {
147 hi2c->i2cx->ctrl2_bit.saddr = 0;
148 hi2c->i2cx->ctrl2_bit.readh10 = 0;
149 hi2c->i2cx->ctrl2_bit.cnt = 0;
150 hi2c->i2cx->ctrl2_bit.rlden = 0;
151 hi2c->i2cx->ctrl2_bit.dir = 0;
152 }
153
154 /**
155 * @brief wait for the transfer to end.
156 * @param hi2c: the handle points to the operation information.
157 * @param timeout: maximum waiting time.
158 * @retval i2c status.
159 */
160 i2c_status_type i2c_wait_end(i2c_handle_type* hi2c, uint32_t timeout)
161 {
162 while(hi2c->status != I2C_END)
163 {
164 /* check timeout */
165 if((timeout--) == 0)
166 {
167 return I2C_ERR_TIMEOUT;
168 }
169 }
170
171 if(hi2c->error_code != I2C_OK)
172 {
173 return hi2c->error_code;
174 }
175
176 return I2C_OK;
177 }
178
179 /**
180 * @brief wait for the flag to be set or reset, only BUSYF flag
181 * is waiting to be reset, and other flags are waiting to be set
182 * @param hi2c: the handle points to the operation information.
183 * @param flag: specifies the flag to check.
184 * this parameter can be one of the following values:
185 * - I2C_TDBE_FLAG: transmit data buffer empty flag.
186 * - I2C_TDIS_FLAG: send interrupt status.
187 * - I2C_RDBF_FLAG: receive data buffer full flag.
188 * - I2C_ADDRF_FLAG: 0~7 bit address match flag.
189 * - I2C_ACKFAIL_FLAG: acknowledge failure flag.
190 * - I2C_STOPF_FLAG: stop condition generation complete flag.
191 * - I2C_TDC_FLAG: transmit data complete flag.
192 * - I2C_TCRLD_FLAG: transmission is complete, waiting to load data.
193 * - I2C_BUSERR_FLAG: bus error flag.
194 * - I2C_ARLOST_FLAG: arbitration lost flag.
195 * - I2C_OUF_FLAG: overflow or underflow flag.
196 * - I2C_PECERR_FLAG: pec receive error flag.
197 * - I2C_TMOUT_FLAG: smbus timeout flag.
198 * - I2C_ALERTF_FLAG: smbus alert flag.
199 * - I2C_BUSYF_FLAG: bus busy flag transmission mode.
200 * - I2C_SDIR_FLAG: slave data transmit direction.
201 * @param event_check: check other error flags while waiting for the flag.
202 * parameter as following values:
203 * - I2C_EVENT_CHECK_NONE
204 * - I2C_EVENT_CHECK_ACKFAIL
205 * - I2C_EVENT_CHECK_STOP
206 * @param timeout: maximum waiting time.
207 * @retval i2c status.
208 */
209 i2c_status_type i2c_wait_flag(i2c_handle_type* hi2c, uint32_t flag, uint32_t event_check, uint32_t timeout)
210 {
211 if(flag == I2C_BUSYF_FLAG)
212 {
213 while(i2c_flag_get(hi2c->i2cx, flag) != RESET)
214 {
215 /* check timeout */
216 if((timeout--) == 0)
217 {
218 hi2c->error_code = I2C_ERR_TIMEOUT;
219
220 return I2C_ERR_TIMEOUT;
221 }
222 }
223 }
224 else
225 {
226 while(i2c_flag_get(hi2c->i2cx, flag) == RESET)
227 {
228 /* check the ack fail flag */
229 if(event_check & I2C_EVENT_CHECK_ACKFAIL)
230 {
231 if(i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
232 {
233 /* clear ack fail flag */
234 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
235
236 hi2c->error_code = I2C_ERR_ACKFAIL;
237
238 return I2C_ERR_ACKFAIL;
239 }
240 }
241
242 /* check the stop flag */
243 if(event_check & I2C_EVENT_CHECK_STOP)
244 {
245 if(i2c_flag_get(hi2c->i2cx, I2C_STOPF_FLAG) != RESET)
246 {
247 /* clear stop flag */
248 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
249
250 i2c_reset_ctrl2_register(hi2c);
251
252 hi2c->error_code = I2C_ERR_STOP;
253
254 return I2C_ERR_STOP;
255 }
256 }
257
258 /* check timeout */
259 if((timeout--) == 0)
260 {
261 hi2c->error_code = I2C_ERR_TIMEOUT;
262
263 return I2C_ERR_TIMEOUT;
264 }
265 }
266 }
267
268 return I2C_OK;
269 }
270
271 /**
272 * @brief dma transfer cofiguration.
273 * @param hi2c: the handle points to the operation information.
274 * @param dma_channelx: dma channel to be cofigured.
275 * @param pdata: data buffer.
276 * @param size: data size.
277 * @retval none.
278 */
279 void i2c_dma_config(i2c_handle_type* hi2c, dma_channel_type* dma_channel, uint8_t* pdata, uint16_t size)
280 {
281 /* disable the dma channel */
282 dma_channel_enable(dma_channel, FALSE);
283
284 /* disable the transfer complete interrupt */
285 dma_interrupt_enable(dma_channel, DMA_FDT_INT, FALSE);
286
287 /* configure the dma channel with the buffer address and the buffer size */
288 hi2c->dma_init_struct.memory_base_addr = (uint32_t)pdata;
289 hi2c->dma_init_struct.direction = (dma_channel == hi2c->dma_tx_channel) ? DMA_DIR_MEMORY_TO_PERIPHERAL : DMA_DIR_PERIPHERAL_TO_MEMORY;
290 hi2c->dma_init_struct.peripheral_base_addr = (dma_channel == hi2c->dma_tx_channel) ? (uint32_t)&hi2c->i2cx->txdt : (uint32_t)&hi2c->i2cx->rxdt;
291 hi2c->dma_init_struct.buffer_size = (uint32_t)size;
292 dma_init(dma_channel, &hi2c->dma_init_struct);
293
294 /* enable the transfer complete interrupt */
295 dma_interrupt_enable(dma_channel, DMA_FDT_INT, TRUE);
296
297 /* enable the dma channel */
298 dma_channel_enable(dma_channel, TRUE);
299 }
300
301 /**
302 * @brief start transfer in poll mode or interrupt mode.
303 * @param hi2c: the handle points to the operation information.
304 * @param address: slave address.
305 * @param start: config gen start condition mode.
306 * parameter as following values:
307 * - I2C_WITHOUT_START: transfer data without start condition.
308 * - I2C_GEN_START_READ: read data and generate start.
309 * - I2C_GEN_START_WRITE: send data and generate start.
310 * @retval i2c status.
311 */
312 void i2c_start_transfer(i2c_handle_type* hi2c, uint16_t address, i2c_start_mode_type start)
313 {
314 if (hi2c->pcount > MAX_TRANSFER_CNT)
315 {
316 hi2c->psize = MAX_TRANSFER_CNT;
317
318 i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_RELOAD_MODE, start);
319 }
320 else
321 {
322 hi2c->psize = hi2c->pcount;
323
324 i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_AUTO_STOP_MODE, start);
325 }
326 }
327
328 /**
329 * @brief start transfer in dma mode.
330 * @param hi2c: the handle points to the operation information.
331 * @param address: slave address.
332 * @param start: config gen start condition mode.
333 * parameter as following values:
334 * - I2C_WITHOUT_START: transfer data without start condition.
335 * - I2C_GEN_START_READ: read data and generate start.
336 * - I2C_GEN_START_WRITE: send data and generate start.
337 * @retval i2c status.
338 */
339 void i2c_start_transfer_dma(i2c_handle_type* hi2c, dma_channel_type* dma_channelx, uint16_t address, i2c_start_mode_type start)
340 {
341 if (hi2c->pcount > MAX_TRANSFER_CNT)
342 {
343 hi2c->psize = MAX_TRANSFER_CNT;
344
345 /* config dma */
346 i2c_dma_config(hi2c, dma_channelx, hi2c->pbuff, hi2c->psize);
347
348 i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_RELOAD_MODE, start);
349 }
350 else
351 {
352 hi2c->psize = hi2c->pcount;
353
354 /* config dma */
355 i2c_dma_config(hi2c, dma_channelx, hi2c->pbuff, hi2c->psize);
356
357 i2c_transmit_set(hi2c->i2cx, address, hi2c->psize, I2C_AUTO_STOP_MODE, start);
358 }
359 }
360
361 /**
362 * @brief the master transmits data through polling mode.
363 * @param hi2c: the handle points to the operation information.
364 * @param address: slave address.
365 * @param pdata: data buffer.
366 * @param size: data size.
367 * @param timeout: maximum waiting time.
368 * @retval i2c status.
369 */
370 i2c_status_type i2c_master_transmit(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
371 {
372 /* initialization parameters */
373 hi2c->pbuff = pdata;
374 hi2c->pcount = size;
375
376 hi2c->error_code = I2C_OK;
377
378 /* wait for the busy flag to be reset */
379 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
380 {
381 return I2C_ERR_STEP_1;
382 }
383
384 /* start transfer */
385 i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
386
387 while (hi2c->pcount > 0)
388 {
389 /* wait for the tdis flag to be set */
390 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
391 {
392 return I2C_ERR_STEP_2;
393 }
394
395 /* send data */
396 i2c_data_send(hi2c->i2cx, *hi2c->pbuff++);
397 hi2c->psize--;
398 hi2c->pcount--;
399
400 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
401 {
402 /* wait for the tcrld flag to be set */
403 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
404 {
405 return I2C_ERR_STEP_3;
406 }
407
408 /* continue transfer */
409 i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
410 }
411 }
412
413 /* wait for the stop flag to be set */
414 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
415 {
416 return I2C_ERR_STEP_4;
417 }
418
419 /* clear stop flag */
420 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
421
422 /* reset ctrl2 register */
423 i2c_reset_ctrl2_register(hi2c);
424
425 return I2C_OK;
426 }
427
428 /**
429 * @brief the slave receive data through polling mode.
430 * @param hi2c: the handle points to the operation information.
431 * @param pdata: data buffer.
432 * @param size: data size.
433 * @param timeout: maximum waiting time.
434 * @retval i2c status.
435 */
436 i2c_status_type i2c_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
437 {
438 /* initialization parameters */
439 hi2c->pbuff = pdata;
440 hi2c->pcount = size;
441
442 hi2c->error_code = I2C_OK;
443
444 /* wait for the busy flag to be reset */
445 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
446 {
447 return I2C_ERR_STEP_1;
448 }
449
450 /* enable acknowledge */
451 i2c_ack_enable(hi2c->i2cx, TRUE);
452
453 /* wait for the addr flag to be set */
454 if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
455 {
456 return I2C_ERR_STEP_2;
457 }
458
459 /* clear addr flag */
460 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
461
462 while (hi2c->pcount > 0)
463 {
464 /* wait for the rdbf flag to be set */
465 if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_STOP, timeout) != I2C_OK)
466 {
467 /* disable acknowledge */
468 i2c_ack_enable(hi2c->i2cx, FALSE);
469
470 /* if data is received, read data */
471 if (i2c_flag_get(hi2c->i2cx, I2C_RDBF_FLAG) == SET)
472 {
473 /* read data */
474 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
475 hi2c->pcount--;
476 }
477
478 return I2C_ERR_STEP_4;
479 }
480
481 /* read data */
482 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
483 hi2c->pcount--;
484 }
485
486 /* wait for the stop flag to be set */
487 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
488 {
489 /* disable acknowledge */
490 i2c_ack_enable(hi2c->i2cx, FALSE);
491
492 return I2C_ERR_STEP_5;
493 }
494
495 /* clear stop flag */
496 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
497
498 /* wait for the busy flag to be reset */
499 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
500 {
501 /* disable acknowledge */
502 i2c_ack_enable(hi2c->i2cx, FALSE);
503
504 return I2C_ERR_STEP_6;
505 }
506
507 return I2C_OK;
508 }
509
510 /**
511 * @brief the master receive data through polling mode.
512 * @param hi2c: the handle points to the operation information.
513 * @param address: slave address.
514 * @param pdata: data buffer.
515 * @param size: data size.
516 * @param timeout: maximum waiting time.
517 * @retval i2c status.
518 */
519 i2c_status_type i2c_master_receive(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
520 {
521 /* initialization parameters */
522 hi2c->pbuff = pdata;
523 hi2c->pcount = size;
524
525 hi2c->error_code = I2C_OK;
526
527 /* wait for the busy flag to be reset */
528 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
529 {
530 return I2C_ERR_STEP_1;
531 }
532
533 /* start transfer */
534 i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
535
536 while (hi2c->pcount > 0)
537 {
538 /* wait for the rdbf flag to be set */
539 if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
540 {
541 return I2C_ERR_STEP_2;
542 }
543
544 /* read data */
545 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
546 hi2c->pcount--;
547 hi2c->psize--;
548
549 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
550 {
551 /* wait for the tcrld flag to be set */
552 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
553 {
554 return I2C_ERR_STEP_3;
555 }
556
557 /* continue transfer */
558 i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
559 }
560 }
561
562 /* wait for the stop flag to be set */
563 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
564 {
565 return I2C_ERR_STEP_4;
566 }
567
568 /* clear stop flag */
569 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
570
571 /* reset ctrl2 register */
572 i2c_reset_ctrl2_register(hi2c);
573
574 return I2C_OK;
575 }
576
577 /**
578 * @brief the slave transmits data through polling mode.
579 * @param hi2c: the handle points to the operation information.
580 * @param pdata: data buffer.
581 * @param size: data size.
582 * @param timeout: maximum waiting time.
583 * @retval i2c status.
584 */
585 i2c_status_type i2c_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
586 {
587 /* initialization parameters */
588 hi2c->pbuff = pdata;
589 hi2c->pcount = size;
590
591 hi2c->error_code = I2C_OK;
592
593 /* wait for the busy flag to be reset */
594 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
595 {
596 return I2C_ERR_STEP_1;
597 }
598
599 /* enable acknowledge */
600 i2c_ack_enable(hi2c->i2cx, TRUE);
601
602 /* wait for the addr flag to be set */
603 if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
604 {
605 /* disable acknowledge */
606 i2c_ack_enable(hi2c->i2cx, FALSE);
607 return I2C_ERR_STEP_2;
608 }
609
610 /* clear addr flag */
611 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
612
613 /* if 10-bit address mode is used */
614 if (hi2c->i2cx->ctrl2_bit.addr10 != RESET)
615 {
616 /* wait for the addr flag to be set */
617 if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
618 {
619 /* disable acknowledge */
620 i2c_ack_enable(hi2c->i2cx, FALSE);
621
622 return I2C_ERR_STEP_3;
623 }
624
625 /* clear addr flag */
626 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
627 }
628
629 while (hi2c->pcount > 0)
630 {
631 /* wait for the tdis flag to be set */
632 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
633 {
634 /* disable acknowledge */
635 i2c_ack_enable(hi2c->i2cx, FALSE);
636
637 return I2C_ERR_STEP_5;
638 }
639
640 /* send data */
641 i2c_data_send(hi2c->i2cx, *hi2c->pbuff++);
642 hi2c->pcount--;
643 }
644
645 /* wait for the ackfail flag to be set */
646 if(i2c_wait_flag(hi2c, I2C_ACKFAIL_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
647 {
648 return I2C_ERR_STEP_6;
649 }
650
651 /* clear ack fail flag */
652 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
653
654 /* wait for the stop flag to be set */
655 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
656 {
657 /* disable acknowledge */
658 i2c_ack_enable(hi2c->i2cx, FALSE);
659
660 return I2C_ERR_STEP_7;
661 }
662
663 /* clear stop flag */
664 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
665
666 /* wait for the busy flag to be reset */
667 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
668 {
669 /* disable acknowledge */
670 i2c_ack_enable(hi2c->i2cx, FALSE);
671
672 return I2C_ERR_STEP_8;
673 }
674
675 /* refresh tx dt register */
676 i2c_refresh_txdt_register(hi2c);
677
678 return I2C_OK;
679 }
680
681 /**
682 * @brief the master transmits data through interrupt mode.
683 * @param hi2c: the handle points to the operation information.
684 * @param address: slave address.
685 * @param pdata: data buffer.
686 * @param size: data size.
687 * @param timeout: maximum waiting time.
688 * @retval i2c status.
689 */
690 i2c_status_type i2c_master_transmit_int(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
691 {
692 /* initialization parameters */
693 hi2c->mode = I2C_INT_MA_TX;
694 hi2c->status = I2C_START;
695
696 hi2c->pbuff = pdata;
697 hi2c->pcount = size;
698
699 hi2c->error_code = I2C_OK;
700
701 /* wait for the busy flag to be reset */
702 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
703 {
704 return I2C_ERR_STEP_1;
705 }
706
707 /* start transfer */
708 i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
709
710 /* enable interrupt */
711 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT, TRUE);
712
713 return I2C_OK;
714 }
715
716 /**
717 * @brief the slave receive data through interrupt mode.
718 * @param hi2c: the handle points to the operation information.
719 * @param pdata: data buffer.
720 * @param size: data size.
721 * @param timeout: maximum waiting time.
722 * @retval i2c status.
723 */
724 i2c_status_type i2c_slave_receive_int(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
725 {
726 /* initialization parameters */
727 hi2c->mode = I2C_INT_SLA_RX;
728 hi2c->status = I2C_START;
729
730 hi2c->pbuff = pdata;
731 hi2c->pcount = size;
732
733 hi2c->error_code = I2C_OK;
734
735 /* wait for the busy flag to be reset */
736 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
737 {
738 return I2C_ERR_STEP_1;
739 }
740
741 /* enable acknowledge */
742 i2c_ack_enable(hi2c->i2cx, TRUE);
743
744 /* enable interrupt */
745 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_ADDR_INT | I2C_RD_INT, TRUE);
746
747 return I2C_OK;
748 }
749
750 /**
751 * @brief the master receive data through interrupt mode.
752 * @param hi2c: the handle points to the operation information.
753 * @param address: slave address.
754 * @param pdata: data buffer.
755 * @param size: data size.
756 * @param timeout: maximum waiting time.
757 * @retval i2c status.
758 */
759 i2c_status_type i2c_master_receive_int(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
760 {
761 /* initialization parameters */
762 hi2c->mode = I2C_INT_MA_RX;
763 hi2c->status = I2C_START;
764
765 hi2c->pbuff = pdata;
766 hi2c->pcount = size;
767
768 hi2c->error_code = I2C_OK;
769
770 /* wait for the busy flag to be reset */
771 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
772 {
773 return I2C_ERR_STEP_1;
774 }
775
776 /* start transfer */
777 i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
778
779 /* enable interrupt */
780 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_RD_INT, TRUE);
781
782 return I2C_OK;
783 }
784
785 /**
786 * @brief the slave transmits data through interrupt mode.
787 * @param hi2c: the handle points to the operation information.
788 * @param pdata: data buffer.
789 * @param size: data size.
790 * @param timeout: maximum waiting time.
791 * @retval i2c status.
792 */
793 i2c_status_type i2c_slave_transmit_int(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
794 {
795 /* initialization parameters */
796 hi2c->mode = I2C_INT_SLA_TX;
797 hi2c->status = I2C_START;
798
799 hi2c->pbuff = pdata;
800 hi2c->pcount = size;
801
802 hi2c->error_code = I2C_OK;
803
804 /* wait for the busy flag to be reset */
805 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
806 {
807 return I2C_ERR_STEP_1;
808 }
809
810 /* enable acknowledge */
811 i2c_ack_enable(hi2c->i2cx, TRUE);
812
813 /* enable interrupt */
814 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_ADDR_INT | I2C_TD_INT, TRUE);
815
816 i2c_refresh_txdt_register(hi2c);
817
818 return I2C_OK;
819 }
820
821 /**
822 * @brief the master transmits data through dma mode.
823 * @param hi2c: the handle points to the operation information.
824 * @param address: slave address.
825 * @param pdata: data buffer.
826 * @param size: data size.
827 * @param timeout: maximum waiting time.
828 * @retval i2c status.
829 */
830 i2c_status_type i2c_master_transmit_dma(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
831 {
832 /* initialization parameters */
833 hi2c->mode = I2C_DMA_MA_TX;
834 hi2c->status = I2C_START;
835
836 hi2c->pbuff = pdata;
837 hi2c->pcount = size;
838
839 hi2c->error_code = I2C_OK;
840
841 /* wait for the busy flag to be reset */
842 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
843 {
844 return I2C_ERR_STEP_1;
845 }
846
847 /* disable dma request */
848 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, FALSE);
849
850 /* start transfer */
851 i2c_start_transfer_dma(hi2c, hi2c->dma_tx_channel, address, I2C_GEN_START_WRITE);
852
853 /* enable i2c interrupt */
854 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE);
855
856 /* enable dma request */
857 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, TRUE);
858
859 return I2C_OK;
860 }
861
862 /**
863 * @brief the slave receive data through dma mode.
864 * @param hi2c: the handle points to the operation information.
865 * @param pdata: data buffer.
866 * @param size: data size.
867 * @param timeout: maximum waiting time.
868 * @retval i2c status.
869 */
870 i2c_status_type i2c_slave_receive_dma(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
871 {
872 /* initialization parameters */
873 hi2c->mode = I2C_DMA_SLA_RX;
874 hi2c->status = I2C_START;
875
876 hi2c->pbuff = pdata;
877 hi2c->pcount = size;
878
879 hi2c->error_code = I2C_OK;
880
881 /* wait for the busy flag to be reset */
882 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
883 {
884 return I2C_ERR_STEP_1;
885 }
886
887 /* disable dma request */
888 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, FALSE);
889
890 /* config dma */
891 i2c_dma_config(hi2c, hi2c->dma_rx_channel, hi2c->pbuff, size);
892
893 /* enable acknowledge */
894 i2c_ack_enable(hi2c->i2cx, TRUE);
895
896 /* enable i2c interrupt */
897 i2c_interrupt_enable(hi2c->i2cx, I2C_ADDR_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_ERR_INT, TRUE);
898
899 /* enable dma request */
900 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, TRUE);
901
902 return I2C_OK;
903 }
904
905 /**
906 * @brief the master receive data through dma mode.
907 * @param hi2c: the handle points to the operation information.
908 * @param address: slave address.
909 * @param pdata: data buffer.
910 * @param size: data size.
911 * @param timeout: maximum waiting time.
912 * @retval i2c status.
913 */
914 i2c_status_type i2c_master_receive_dma(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
915 {
916 /* initialization parameters */
917 hi2c->mode = I2C_DMA_MA_RX;
918 hi2c->status = I2C_START;
919
920 hi2c->pbuff = pdata;
921 hi2c->pcount = size;
922
923 hi2c->error_code = I2C_OK;
924
925 /* wait for the busy flag to be reset */
926 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
927 {
928 return I2C_ERR_STEP_1;
929 }
930
931 /* disable dma request */
932 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, FALSE);
933
934 /* start transfer */
935 i2c_start_transfer_dma(hi2c, hi2c->dma_rx_channel, address, I2C_GEN_START_READ);
936
937 /* enable i2c interrupt */
938 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE);
939
940 /* enable dma request */
941 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, TRUE);
942
943 return I2C_OK;
944 }
945
946 /**
947 * @brief the slave transmits data through dma mode.
948 * @param hi2c: the handle points to the operation information.
949 * @param pdata: data buffer.
950 * @param size: data size.
951 * @param timeout: maximum waiting time.
952 * @retval i2c status.
953 */
954 i2c_status_type i2c_slave_transmit_dma(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
955 {
956 /* initialization parameters */
957 hi2c->mode = I2C_DMA_SLA_TX;
958 hi2c->status = I2C_START;
959
960 hi2c->pbuff = pdata;
961 hi2c->pcount = size;
962
963 hi2c->error_code = I2C_OK;
964
965 /* wait for the busy flag to be reset */
966 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
967 {
968 return I2C_ERR_STEP_1;
969 }
970
971 /* disable dma request */
972 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, FALSE);
973
974 /* config dma */
975 i2c_dma_config(hi2c, hi2c->dma_tx_channel, hi2c->pbuff, size);
976
977 /* enable acknowledge */
978 i2c_ack_enable(hi2c->i2cx, TRUE);
979
980 /* enable i2c interrupt */
981 i2c_interrupt_enable(hi2c->i2cx, I2C_ADDR_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_ERR_INT, TRUE);
982
983 /* enable dma request */
984 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, TRUE);
985
986 return I2C_OK;
987 }
988
989 /**
990 * @brief send memory address.
991 * @param hi2c: the handle points to the operation information.
992 * @param mem_address_width: memory address width.
993 * this parameter can be one of the following values:
994 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
995 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
996 * @param address: memory device address.
997 * @param mem_address: memory address.
998 * @param timeout: maximum waiting time.
999 * @retval i2c status.
1000 */
1001 i2c_status_type i2c_memory_address_send(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t mem_address, int32_t timeout)
1002 {
1003 i2c_status_type err_code;
1004
1005 if(mem_address_width == I2C_MEM_ADDR_WIDIH_8)
1006 {
1007 /* send memory address */
1008 i2c_data_send(hi2c->i2cx, mem_address & 0xFF);
1009 }
1010 else
1011 {
1012 /* send memory address */
1013 i2c_data_send(hi2c->i2cx, (mem_address >> 8) & 0xFF);
1014
1015 /* wait for the tdis flag to be set */
1016 err_code = i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout);
1017
1018 if(err_code != I2C_OK)
1019 {
1020 return err_code;
1021 }
1022
1023 /* send memory address */
1024 i2c_data_send(hi2c->i2cx, mem_address & 0xFF);
1025 }
1026
1027 return I2C_OK;
1028 }
1029
1030 /**
1031 * @brief write data to the memory device through polling mode.
1032 * @param hi2c: the handle points to the operation information.
1033 * @param mem_address_width: memory address width.
1034 * this parameter can be one of the following values:
1035 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
1036 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
1037 * @param address: memory device address.
1038 * @param mem_address: memory address.
1039 * @param pdata: data buffer.
1040 * @param size: data size.
1041 * @param timeout: maximum waiting time.
1042 * @retval i2c status.
1043 */
1044 i2c_status_type i2c_memory_write(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1045 {
1046 /* initialization parameters */
1047 hi2c->pbuff = pdata;
1048 hi2c->pcount = size + mem_address_width;
1049
1050 hi2c->error_code = I2C_OK;
1051
1052 /* wait for the busy flag to be reset */
1053 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1054 {
1055 return I2C_ERR_STEP_1;
1056 }
1057
1058 /* start transfer */
1059 i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
1060
1061 /* wait for the tdis flag to be set */
1062 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1063 {
1064 return I2C_ERR_STEP_2;
1065 }
1066
1067 /* send memory address */
1068 if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
1069 {
1070 return I2C_ERR_STEP_3;
1071 }
1072
1073 hi2c->psize -= mem_address_width;
1074 hi2c->pcount -= mem_address_width;
1075
1076 while (hi2c->pcount > 0)
1077 {
1078 /* wait for the tdis flag to be set */
1079 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1080 {
1081 return I2C_ERR_STEP_4;
1082 }
1083
1084 /* send data */
1085 i2c_data_send(hi2c->i2cx, *hi2c->pbuff++);
1086 hi2c->psize--;
1087 hi2c->pcount--;
1088
1089 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
1090 {
1091 /* wait for the tcrld flag to be set */
1092 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1093 {
1094 return I2C_ERR_STEP_5;
1095 }
1096
1097 /* continue transfer */
1098 i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
1099 }
1100 }
1101
1102 /* wait for the stop flag to be set */
1103 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1104 {
1105 return I2C_ERR_STEP_6;
1106 }
1107
1108 /* clear stop flag */
1109 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1110
1111 /* reset ctrl2 register */
1112 i2c_reset_ctrl2_register(hi2c);
1113
1114 return I2C_OK;
1115 }
1116
1117 /**
1118 * @brief read data from memory device through polling mode.
1119 * @param hi2c: the handle points to the operation information.
1120 * @param mem_address_width: memory address width.
1121 * this parameter can be one of the following values:
1122 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
1123 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
1124 * @param address: memory device address.
1125 * @param mem_address: memory address.
1126 * @param pdata: data buffer.
1127 * @param size: data size.
1128 * @param timeout: maximum waiting time.
1129 * @retval i2c status.
1130 */
1131 i2c_status_type i2c_memory_read(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1132 {
1133 /* initialization parameters */
1134 hi2c->pbuff = pdata;
1135 hi2c->pcount = size;
1136
1137 hi2c->error_code = I2C_OK;
1138
1139 /* wait for the busy flag to be reset */
1140 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1141 {
1142 return I2C_ERR_STEP_1;
1143 }
1144
1145 /* start transfer */
1146 i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
1147
1148 /* wait for the tdis flag to be set */
1149 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1150 {
1151 return I2C_ERR_STEP_2;
1152 }
1153
1154 /* send memory address */
1155 if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
1156 {
1157 return I2C_ERR_STEP_3;
1158 }
1159
1160 /* wait for the tdc flag to be set */
1161 if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1162 {
1163 return I2C_ERR_STEP_4;
1164 }
1165
1166 /* start transfer */
1167 i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
1168
1169 while (hi2c->pcount > 0)
1170 {
1171 /* wait for the rdbf flag to be set */
1172 if (i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1173 {
1174 return I2C_ERR_STEP_5;
1175 }
1176
1177 /* read data */
1178 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1179 hi2c->pcount--;
1180 hi2c->psize--;
1181
1182 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
1183 {
1184 /* wait for the tcrld flag to be set */
1185 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1186 {
1187 return I2C_ERR_STEP_6;
1188 }
1189
1190 /* continue transfer */
1191 i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
1192 }
1193 }
1194
1195 /* wait for the stop flag to be set */
1196 if (i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1197 {
1198 return I2C_ERR_STEP_7;
1199 }
1200
1201 /* clear stop flag */
1202 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1203
1204 /* reset ctrl2 register */
1205 i2c_reset_ctrl2_register(hi2c);
1206
1207 return I2C_OK;
1208 }
1209
1210 /**
1211 * @brief write data to the memory device through interrupt mode.
1212 * @param hi2c: the handle points to the operation information.
1213 * @param mem_address_width: memory address width.
1214 * this parameter can be one of the following values:
1215 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
1216 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
1217 * @param address: memory device address.
1218 * @param mem_address: memory address.
1219 * @param pdata: data buffer.
1220 * @param size: data size.
1221 * @param timeout: maximum waiting time.
1222 * @retval i2c status.
1223 */
1224 i2c_status_type i2c_memory_write_int(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1225 {
1226 /* initialization parameters */
1227 hi2c->mode = I2C_INT_MA_TX;
1228 hi2c->status = I2C_START;
1229
1230 hi2c->pbuff = pdata;
1231 hi2c->pcount = size + mem_address_width;
1232
1233 hi2c->error_code = I2C_OK;
1234
1235 /* wait for the busy flag to be reset */
1236 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1237 {
1238 return I2C_ERR_STEP_1;
1239 }
1240
1241 /* start transfer */
1242 i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
1243
1244 /* wait for the tdis flag to be set */
1245 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1246 {
1247 return I2C_ERR_STEP_2;
1248 }
1249
1250 /* send memory address */
1251 if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
1252 {
1253 return I2C_ERR_STEP_3;
1254 }
1255
1256 hi2c->psize--;
1257 hi2c->pcount--;
1258
1259 /* enable interrupt */
1260 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT, TRUE);
1261
1262 return I2C_OK;
1263 }
1264
1265 /**
1266 * @brief read data from memory device through interrupt mode.
1267 * @param hi2c: the handle points to the operation information.
1268 * @param mem_address_width: memory address width.
1269 * this parameter can be one of the following values:
1270 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
1271 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
1272 * @param address: memory device address.
1273 * @param mem_address: memory address.
1274 * @param pdata: data buffer.
1275 * @param size: data size.
1276 * @param timeout: maximum waiting time.
1277 * @retval i2c status.
1278 */
1279 i2c_status_type i2c_memory_read_int(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1280 {
1281 /* initialization parameters */
1282 hi2c->mode = I2C_INT_MA_RX;
1283 hi2c->status = I2C_START;
1284
1285 hi2c->pbuff = pdata;
1286 hi2c->pcount = size;
1287
1288 hi2c->error_code = I2C_OK;
1289
1290 /* wait for the busy flag to be reset */
1291 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1292 {
1293 return I2C_ERR_STEP_1;
1294 }
1295
1296 /* start transfer */
1297 i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
1298
1299 /* wait for the tdis flag to be set */
1300 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1301 {
1302 return I2C_ERR_STEP_2;
1303 }
1304
1305 /* send memory address */
1306 if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
1307 {
1308 return I2C_ERR_STEP_3;
1309 }
1310
1311 /* wait for the tdc flag to be set */
1312 if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1313 {
1314 return I2C_ERR_STEP_4;
1315 }
1316
1317 /* start transfer */
1318 i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
1319
1320 /* enable i2c interrupt */
1321 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_RD_INT, TRUE);
1322
1323 return I2C_OK;
1324 }
1325
1326 /**
1327 * @brief write data to the memory device through dma mode.
1328 * @param hi2c: the handle points to the operation information.
1329 * @param mem_address_width: memory address width.
1330 * this parameter can be one of the following values:
1331 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
1332 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
1333 * @param address: memory device address.
1334 * @param mem_address: memory address.
1335 * @param pdata: data buffer.
1336 * @param size: data size.
1337 * @param timeout: maximum waiting time.
1338 * @retval i2c status.
1339 */
1340 i2c_status_type i2c_memory_write_dma(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1341 {
1342 /* initialization parameters */
1343 hi2c->mode = I2C_DMA_MA_TX;
1344 hi2c->status = I2C_START;
1345
1346 hi2c->pbuff = pdata;
1347 hi2c->pcount = size;
1348
1349 hi2c->error_code = I2C_OK;
1350
1351 /* disable dma request */
1352 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, FALSE);
1353
1354 /* wait for the busy flag to be reset */
1355 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1356 {
1357 return I2C_ERR_STEP_1;
1358 }
1359
1360 /* transfer config */
1361 i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_RELOAD_MODE, I2C_GEN_START_WRITE);
1362
1363 /* wait for the tdis flag to be set */
1364 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1365 {
1366 return I2C_ERR_STEP_2;
1367 }
1368
1369 /* send memory address */
1370 if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
1371 {
1372 return I2C_ERR_STEP_3;
1373 }
1374
1375 /* wait for the tcrld flag to be set */
1376 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1377 {
1378 return I2C_ERR_STEP_4;
1379 }
1380
1381 /* start transfer */
1382 i2c_start_transfer_dma(hi2c, hi2c->dma_tx_channel, address, I2C_WITHOUT_START);
1383
1384 /* enable i2c interrupt */
1385 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE);
1386
1387 /* enable dma request */
1388 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, TRUE);
1389
1390 return I2C_OK;
1391 }
1392
1393 /**
1394 * @brief read data from memory device through polling mode.
1395 * @param hi2c: the handle points to the operation information.
1396 * @param mem_address_width: memory address width.
1397 * this parameter can be one of the following values:
1398 * - I2C_MEM_ADDR_WIDIH_8: memory address is 8 bit
1399 * - I2C_MEM_ADDR_WIDIH_16: memory address is 16 bit
1400 * @param address: memory device address.
1401 * @param mem_address: memory address.
1402 * @param pdata: data buffer.
1403 * @param size: data size.
1404 * @param timeout: maximum waiting time.
1405 * @retval i2c status.
1406 */
1407 i2c_status_type i2c_memory_read_dma(i2c_handle_type* hi2c, i2c_mem_address_width_type mem_address_width, uint16_t address, uint16_t mem_address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1408 {
1409 /* initialization parameters */
1410 hi2c->mode = I2C_DMA_MA_RX;
1411 hi2c->status = I2C_START;
1412
1413 hi2c->pbuff = pdata;
1414 hi2c->pcount = size;
1415
1416 hi2c->error_code = I2C_OK;
1417
1418 /* wait for the busy flag to be reset */
1419 if(i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1420 {
1421 return I2C_ERR_STEP_1;
1422 }
1423
1424 /* start transfer */
1425 i2c_transmit_set(hi2c->i2cx, address, mem_address_width, I2C_SOFT_STOP_MODE, I2C_GEN_START_WRITE);
1426
1427 /* wait for the tdis flag to be set */
1428 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1429 {
1430 return I2C_ERR_STEP_2;
1431 }
1432
1433 /* send memory address */
1434 if(i2c_memory_address_send(hi2c, mem_address_width, mem_address, timeout) != I2C_OK)
1435 {
1436 return I2C_ERR_STEP_3;
1437 }
1438
1439 /* wait for the tdc flag to be set */
1440 if (i2c_wait_flag(hi2c, I2C_TDC_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1441 {
1442 return I2C_ERR_STEP_4;
1443 }
1444
1445 /* disable dma request */
1446 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, FALSE);
1447
1448 /* start transfer */
1449 i2c_start_transfer_dma(hi2c, hi2c->dma_rx_channel, address, I2C_GEN_START_READ);
1450
1451 /* enable i2c interrupt */
1452 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_ACKFIAL_INT, TRUE);
1453
1454 /* enable dma request */
1455 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, TRUE);
1456
1457 return I2C_OK;
1458 }
1459
1460 /**
1461 * @brief the master transmits data through SMBus mode.
1462 * @param hi2c: the handle points to the operation information.
1463 * @param address: slave address.
1464 * @param pdata: data buffer.
1465 * @param size: data size.
1466 * @param timeout: maximum waiting time.
1467 * @retval i2c status.
1468 */
1469 i2c_status_type i2c_smbus_master_transmit(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1470 {
1471 /* initialization parameters */
1472 hi2c->pbuff = pdata;
1473 hi2c->pcount = size;
1474
1475 hi2c->error_code = I2C_OK;
1476
1477 /* wait for the busy flag to be reset */
1478 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1479 {
1480 return I2C_ERR_STEP_1;
1481 }
1482
1483 /* enable pec calculation */
1484 i2c_pec_calculate_enable(hi2c->i2cx, TRUE);
1485
1486 /* enable pec transmit request */
1487 i2c_pec_transmit_enable(hi2c->i2cx, TRUE);
1488
1489 /* start transfer */
1490 i2c_start_transfer(hi2c, address, I2C_GEN_START_WRITE);
1491
1492 hi2c->pcount--;
1493
1494 while (hi2c->pcount > 0)
1495 {
1496 /* wait for the tdis flag to be set */
1497 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1498 {
1499 return I2C_ERR_STEP_2;
1500 }
1501
1502 /* send data */
1503 i2c_data_send(hi2c->i2cx, *hi2c->pbuff++);
1504 hi2c->psize--;
1505 hi2c->pcount--;
1506
1507 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
1508 {
1509 /* wait for the tcrld flag to be set */
1510 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1511 {
1512 return I2C_ERR_STEP_3;
1513 }
1514
1515 /* continue transfer */
1516 i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
1517 }
1518 }
1519
1520 /* wait for the stop flag to be set */
1521 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1522 {
1523 return I2C_ERR_STEP_4;
1524 }
1525
1526 /* clear stop flag */
1527 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1528
1529 /* reset ctrl2 register */
1530 i2c_reset_ctrl2_register(hi2c);
1531
1532 return I2C_OK;
1533 }
1534
1535 /**
1536 * @brief the slave receive data through SMBus mode.
1537 * @param hi2c: the handle points to the operation information.
1538 * @param pdata: data buffer.
1539 * @param size: data size.
1540 * @param timeout: maximum waiting time.
1541 * @retval i2c status.
1542 */
1543 i2c_status_type i2c_smbus_slave_receive(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
1544 {
1545 /* initialization parameters */
1546 hi2c->pbuff = pdata;
1547 hi2c->pcount = size;
1548
1549 hi2c->error_code = I2C_OK;
1550
1551 /* enable pec calculation */
1552 i2c_pec_calculate_enable(hi2c->i2cx, TRUE);
1553
1554 /* enable slave data control mode */
1555 i2c_slave_data_ctrl_enable(hi2c->i2cx, TRUE);
1556
1557 /* enable acknowledge */
1558 i2c_ack_enable(hi2c->i2cx, TRUE);
1559
1560 /* wait for the addr flag to be set */
1561 if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1562 {
1563 return I2C_ERR_STEP_1;
1564 }
1565
1566 /* enable pec transmit request */
1567 i2c_pec_transmit_enable(hi2c->i2cx, TRUE);
1568
1569 /* configure the number of bytes to be transmitted */
1570 i2c_cnt_set(hi2c->i2cx, hi2c->pcount);
1571
1572 /* clear addr flag */
1573 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
1574
1575 while (hi2c->pcount > 0)
1576 {
1577 /* wait for the rdbf flag to be set */
1578 if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_STOP, timeout) != I2C_OK)
1579 {
1580 /* disable acknowledge */
1581 i2c_ack_enable(hi2c->i2cx, FALSE);
1582
1583 /* if data is received, read data */
1584 if (i2c_flag_get(hi2c->i2cx, I2C_RDBF_FLAG) == SET)
1585 {
1586 /* read data */
1587 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1588 hi2c->pcount--;
1589 }
1590
1591 return I2C_ERR_STEP_3;
1592 }
1593
1594 /* read data */
1595 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1596 hi2c->pcount--;
1597 }
1598
1599 /* wait for the stop flag to be set */
1600 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1601 {
1602 /* disable acknowledge */
1603 i2c_ack_enable(hi2c->i2cx, FALSE);
1604
1605 return I2C_ERR_STEP_4;
1606 }
1607
1608 /* clear stop flag */
1609 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1610
1611 /* wait for the busy flag to be reset */
1612 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1613 {
1614 /* disable acknowledge */
1615 i2c_ack_enable(hi2c->i2cx, FALSE);
1616
1617 return I2C_ERR_STEP_5;
1618 }
1619
1620 /* disable slave data control mode */
1621 i2c_slave_data_ctrl_enable(hi2c->i2cx, FALSE);
1622
1623 return I2C_OK;
1624 }
1625
1626 /**
1627 * @brief the master receive data through SMBus mode.
1628 * @param hi2c: the handle points to the operation information.
1629 * @param address: slave address.
1630 * @param pdata: data buffer.
1631 * @param size: data size.
1632 * @param timeout: maximum waiting time.
1633 * @retval i2c status.
1634 */
1635 i2c_status_type i2c_smbus_master_receive(i2c_handle_type* hi2c, uint16_t address, uint8_t* pdata, uint16_t size, uint32_t timeout)
1636 {
1637 /* initialization parameters */
1638 hi2c->pbuff = pdata;
1639 hi2c->pcount = size;
1640
1641 hi2c->error_code = I2C_OK;
1642
1643 /* wait for the busy flag to be reset */
1644 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1645 {
1646 return I2C_ERR_STEP_1;
1647 }
1648
1649 /* enable pec calculation */
1650 i2c_pec_calculate_enable(hi2c->i2cx, TRUE);
1651
1652 /* enable pec transmit request */
1653 i2c_pec_transmit_enable(hi2c->i2cx, TRUE);
1654
1655 /* start transfer */
1656 i2c_start_transfer(hi2c, address, I2C_GEN_START_READ);
1657
1658 while (hi2c->pcount > 0)
1659 {
1660 /* wait for the rdbf flag to be set */
1661 if(i2c_wait_flag(hi2c, I2C_RDBF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1662 {
1663 return I2C_ERR_STEP_2;
1664 }
1665
1666 /* read data */
1667 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1668 hi2c->pcount--;
1669 hi2c->psize--;
1670
1671 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
1672 {
1673 /* wait for the tcrld flag to be set */
1674 if (i2c_wait_flag(hi2c, I2C_TCRLD_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1675 {
1676 return I2C_ERR_STEP_3;
1677 }
1678
1679 /* continue transfer */
1680 i2c_start_transfer(hi2c, address, I2C_WITHOUT_START);
1681 }
1682 }
1683
1684 /* wait for the stop flag to be set */
1685 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1686 {
1687 return I2C_ERR_STEP_4;
1688 }
1689
1690 /* clear stop flag */
1691 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1692
1693 /* reset ctrl2 register */
1694 i2c_reset_ctrl2_register(hi2c);
1695
1696 return I2C_OK;
1697 }
1698
1699 /**
1700 * @brief the slave transmits data through SMBus mode.
1701 * @param hi2c: the handle points to the operation information.
1702 * @param pdata: data buffer.
1703 * @param size: data size.
1704 * @param timeout: maximum waiting time.
1705 * @retval i2c status.
1706 */
1707 i2c_status_type i2c_smbus_slave_transmit(i2c_handle_type* hi2c, uint8_t* pdata, uint16_t size, uint32_t timeout)
1708 {
1709 /* initialization parameters */
1710 hi2c->pbuff = pdata;
1711 hi2c->pcount = size;
1712
1713 hi2c->error_code = I2C_OK;
1714
1715 /* enable pec calculation */
1716 i2c_pec_calculate_enable(hi2c->i2cx, TRUE);
1717
1718 /* enable slave data control mode */
1719 i2c_slave_data_ctrl_enable(hi2c->i2cx, TRUE);
1720
1721 /* enable acknowledge */
1722 i2c_ack_enable(hi2c->i2cx, TRUE);
1723
1724 /* wait for the addr flag to be set */
1725 if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1726 {
1727 /* disable acknowledge */
1728 i2c_ack_enable(hi2c->i2cx, FALSE);
1729 return I2C_ERR_STEP_1;
1730 }
1731
1732 /* if 7-bit address mode is selected */
1733 if (hi2c->i2cx->ctrl2_bit.addr10 == 0)
1734 {
1735 /* enable pec transmit request */
1736 i2c_pec_transmit_enable(hi2c->i2cx, TRUE);
1737
1738 /* configure the number of bytes to be transmitted */
1739 i2c_cnt_set(hi2c->i2cx, hi2c->pcount);
1740 }
1741
1742 /* clear addr flag */
1743 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
1744
1745 /* if 10-bit address mode is used */
1746 if (hi2c->i2cx->ctrl2_bit.addr10 != RESET)
1747 {
1748 /* wait for the addr flag to be set */
1749 if (i2c_wait_flag(hi2c, I2C_ADDRF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1750 {
1751 /* disable acknowledge */
1752 i2c_ack_enable(hi2c->i2cx, FALSE);
1753
1754 return I2C_ERR_STEP_2;
1755 }
1756
1757 /* enable pec transmit request */
1758 i2c_pec_transmit_enable(hi2c->i2cx, TRUE);
1759
1760 /* configure the number of bytes to be transmitted */
1761 i2c_cnt_set(hi2c->i2cx, hi2c->pcount);
1762
1763 /* clear addr flag */
1764 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
1765 }
1766
1767 hi2c->pcount--;
1768
1769 while (hi2c->pcount > 0)
1770 {
1771 /* wait for the tdis flag to be set */
1772 if(i2c_wait_flag(hi2c, I2C_TDIS_FLAG, I2C_EVENT_CHECK_ACKFAIL, timeout) != I2C_OK)
1773 {
1774 /* disable acknowledge */
1775 i2c_ack_enable(hi2c->i2cx, FALSE);
1776
1777 return I2C_ERR_STEP_4;
1778 }
1779
1780 /* send data */
1781 i2c_data_send(hi2c->i2cx, *hi2c->pbuff++);
1782 hi2c->pcount--;
1783 }
1784
1785 /* wait for the ackfail flag to be set */
1786 if(i2c_wait_flag(hi2c, I2C_ACKFAIL_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1787 {
1788 return I2C_ERR_STEP_5;
1789 }
1790
1791 /* clear ack fail flag */
1792 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
1793
1794 /* wait for the stop flag to be set */
1795 if(i2c_wait_flag(hi2c, I2C_STOPF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1796 {
1797 /* disable acknowledge */
1798 i2c_ack_enable(hi2c->i2cx, FALSE);
1799
1800 return I2C_ERR_STEP_6;
1801 }
1802
1803 /* clear stop flag */
1804 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1805
1806 /* wait for the busy flag to be reset */
1807 if (i2c_wait_flag(hi2c, I2C_BUSYF_FLAG, I2C_EVENT_CHECK_NONE, timeout) != I2C_OK)
1808 {
1809 /* disable acknowledge */
1810 i2c_ack_enable(hi2c->i2cx, FALSE);
1811
1812 return I2C_ERR_STEP_7;
1813 }
1814
1815 /* reset ctrl2 register */
1816 i2c_reset_ctrl2_register(hi2c);
1817
1818 /* refresh tx dt register */
1819 i2c_refresh_txdt_register(hi2c);
1820
1821 /* disable slave data control mode */
1822 i2c_slave_data_ctrl_enable(hi2c->i2cx, FALSE);
1823
1824 return I2C_OK;
1825 }
1826
1827 /**
1828 * @brief master interrupt processing function in interrupt mode.
1829 * @param hi2c: the handle points to the operation information.
1830 * @retval i2c status.
1831 */
1832 i2c_status_type i2c_master_irq_handler_int(i2c_handle_type* hi2c)
1833 {
1834 if (i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
1835 {
1836
1837 /* clear ackfail flag */
1838 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
1839
1840 /* refresh tx register */
1841 i2c_refresh_txdt_register(hi2c);
1842
1843 if(hi2c->pcount != 0)
1844 {
1845 hi2c->error_code = I2C_ERR_ACKFAIL;
1846 }
1847 }
1848 else if (i2c_flag_get(hi2c->i2cx, I2C_TDIS_FLAG) != RESET)
1849 {
1850 /* send data */
1851 i2c_data_send(hi2c->i2cx, *hi2c->pbuff++);
1852 hi2c->pcount--;
1853 hi2c->psize--;
1854 }
1855 else if (i2c_flag_get(hi2c->i2cx, I2C_TCRLD_FLAG) != RESET)
1856 {
1857 if ((hi2c->psize == 0) && (hi2c->pcount != 0))
1858 {
1859 /* continue transfer */
1860 i2c_start_transfer(hi2c, i2c_transfer_addr_get(hi2c->i2cx), I2C_WITHOUT_START);
1861 }
1862 else
1863 {
1864 return I2C_ERR_TCRLD;
1865 }
1866 }
1867 else if (i2c_flag_get(hi2c->i2cx, I2C_RDBF_FLAG) != RESET)
1868 {
1869 /* read data */
1870 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1871 hi2c->pcount--;
1872 hi2c->psize--;
1873 }
1874 else if (i2c_flag_get(hi2c->i2cx, I2C_TDC_FLAG) != RESET)
1875 {
1876 if (hi2c->pcount == 0)
1877 {
1878 if (hi2c->i2cx->ctrl2_bit.astopen == 0)
1879 {
1880 /* generate stop condtion */
1881 i2c_stop_generate(hi2c->i2cx);
1882 }
1883 }
1884 else
1885 {
1886 return I2C_ERR_TDC;
1887 }
1888 }
1889 else if (i2c_flag_get(hi2c->i2cx, I2C_STOPF_FLAG) != RESET)
1890 {
1891 /* clear stop flag */
1892 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1893
1894 /* reset ctrl2 register */
1895 i2c_reset_ctrl2_register(hi2c);
1896
1897 if (i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
1898 {
1899 /* clear ackfail flag */
1900 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
1901 }
1902
1903 /* refresh tx dt register */
1904 i2c_refresh_txdt_register(hi2c);
1905
1906 /* disable interrupts */
1907 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT | I2C_RD_INT, FALSE);
1908
1909 /* transfer complete */
1910 hi2c->status = I2C_END;
1911 }
1912
1913 return I2C_OK;
1914 }
1915
1916 /**
1917 * @brief slave interrupt processing function in interrupt mode.
1918 * @param hi2c: the handle points to the operation information.
1919 * @retval i2c status.
1920 */
1921 i2c_status_type i2c_slave_irq_handler_int(i2c_handle_type* hi2c)
1922 {
1923 if (i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
1924 {
1925 /* transfer complete */
1926 if (hi2c->pcount == 0)
1927 {
1928 i2c_refresh_txdt_register(hi2c);
1929
1930 /* clear ackfail flag */
1931 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
1932 }
1933 /* the transfer has not been completed */
1934 else
1935 {
1936 /* clear ackfail flag */
1937 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
1938 }
1939 }
1940 else if (i2c_flag_get(hi2c->i2cx, I2C_ADDRF_FLAG) != RESET)
1941 {
1942 /* clear addr flag */
1943 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
1944 }
1945 else if (i2c_flag_get(hi2c->i2cx, I2C_TDIS_FLAG) != RESET)
1946 {
1947 if (hi2c->pcount > 0)
1948 {
1949 /* send data */
1950 hi2c->i2cx->txdt = (*(hi2c->pbuff++));
1951 hi2c->psize--;
1952 hi2c->pcount--;
1953 }
1954 }
1955 else if (i2c_flag_get(hi2c->i2cx, I2C_RDBF_FLAG) != RESET)
1956 {
1957 if (hi2c->pcount > 0)
1958 {
1959 /* read data */
1960 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1961 hi2c->pcount--;
1962 hi2c->psize--;
1963 }
1964 }
1965 else if (i2c_flag_get(hi2c->i2cx, I2C_STOPF_FLAG) != RESET)
1966 {
1967 /* clear stop flag */
1968 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
1969
1970 /* disable interrupts */
1971 i2c_interrupt_enable(hi2c->i2cx, I2C_ADDR_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_ERR_INT | I2C_TDC_INT | I2C_TD_INT | I2C_RD_INT, FALSE);
1972
1973 /* reset ctrl2 register */
1974 i2c_reset_ctrl2_register(hi2c);
1975
1976 /* refresh tx dt register */
1977 i2c_refresh_txdt_register(hi2c);
1978
1979 /* if data is received, read data */
1980 if (i2c_flag_get(hi2c->i2cx, I2C_RDBF_FLAG) != RESET)
1981 {
1982 /* read data */
1983 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
1984
1985 if ((hi2c->psize > 0))
1986 {
1987 hi2c->pcount--;
1988 hi2c->psize--;
1989 }
1990 }
1991
1992 /* transfer complete */
1993 hi2c->status = I2C_END;
1994 }
1995
1996 return I2C_OK;
1997 }
1998
1999 /**
2000 * @brief master interrupt processing function in dma mode.
2001 * @param hi2c: the handle points to the operation information.
2002 * @retval i2c status.
2003 */
2004 i2c_status_type i2c_master_irq_handler_dma(i2c_handle_type* hi2c)
2005 {
2006 if (i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
2007 {
2008 /* clear ackfail flag */
2009 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
2010
2011 /* enable stop interrupt to wait for stop generate stop */
2012 i2c_interrupt_enable(hi2c->i2cx, I2C_STOP_INT, TRUE);
2013
2014 /* refresh tx dt register */
2015 i2c_refresh_txdt_register(hi2c);
2016
2017 if(hi2c->pcount != 0)
2018 {
2019 hi2c->error_code = I2C_ERR_ACKFAIL;
2020 }
2021 }
2022 else if (i2c_flag_get(hi2c->i2cx, I2C_TCRLD_FLAG) != RESET)
2023 {
2024 /* disable tdc interrupt */
2025 i2c_interrupt_enable(hi2c->i2cx, I2C_TDC_INT, FALSE);
2026
2027 if (hi2c->pcount != 0)
2028 {
2029 /* continue transfer */
2030 i2c_start_transfer(hi2c, i2c_transfer_addr_get(hi2c->i2cx), I2C_WITHOUT_START);
2031
2032 /* enable dma request */
2033 if (hi2c->dma_init_struct.direction == DMA_DIR_MEMORY_TO_PERIPHERAL)
2034 {
2035 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_TX, TRUE);
2036 }
2037 else
2038 {
2039 i2c_dma_enable(hi2c->i2cx, I2C_DMA_REQUEST_RX, TRUE);
2040 }
2041 }
2042 else
2043 {
2044 return I2C_ERR_TCRLD;
2045 }
2046 }
2047 else if (i2c_flag_get(hi2c->i2cx, I2C_STOPF_FLAG) != RESET)
2048 {
2049 /* clear stop flag */
2050 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
2051
2052 /* reset ctrl2 register */
2053 i2c_reset_ctrl2_register(hi2c);
2054
2055 if (i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
2056 {
2057 /* clear ackfail flag */
2058 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
2059 }
2060
2061 /* refresh tx dt register */
2062 i2c_refresh_txdt_register(hi2c);
2063
2064 /* disable interrupts */
2065 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT | I2C_TDC_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_TD_INT | I2C_RD_INT, FALSE);
2066
2067 /* transfer complete */
2068 hi2c->status = I2C_END;
2069 }
2070
2071 return I2C_OK;
2072 }
2073
2074 /**
2075 * @brief slave interrupt processing function in dma mode.
2076 * @param hi2c: the handle points to the operation information.
2077 * @retval i2c status.
2078 */
2079 i2c_status_type i2c_slave_irq_handler_dma(i2c_handle_type* hi2c)
2080 {
2081 if (i2c_flag_get(hi2c->i2cx, I2C_ACKFAIL_FLAG) != RESET)
2082 {
2083 /* clear ackfail flag */
2084 i2c_flag_clear(hi2c->i2cx, I2C_ACKFAIL_FLAG);
2085 }
2086 else if (i2c_flag_get(hi2c->i2cx, I2C_ADDRF_FLAG) != RESET)
2087 {
2088 /* clear addr flag */
2089 i2c_flag_clear(hi2c->i2cx, I2C_ADDRF_FLAG);
2090 }
2091 else if (i2c_flag_get(hi2c->i2cx, I2C_STOPF_FLAG) != RESET)
2092 {
2093 /* clear stop flag */
2094 i2c_flag_clear(hi2c->i2cx, I2C_STOPF_FLAG);
2095
2096 /* disable interrupts */
2097 i2c_interrupt_enable(hi2c->i2cx, I2C_ADDR_INT | I2C_STOP_INT | I2C_ACKFIAL_INT | I2C_ERR_INT | I2C_TDC_INT | I2C_TD_INT | I2C_RD_INT, FALSE);
2098
2099 /* reset ctrl2 register */
2100 i2c_reset_ctrl2_register(hi2c);
2101
2102 /* refresh tx dt register */
2103 i2c_refresh_txdt_register(hi2c);
2104
2105 /* if data is received, read data */
2106 if (i2c_flag_get(hi2c->i2cx, I2C_RDBF_FLAG) != RESET)
2107 {
2108 /* read data */
2109 (*hi2c->pbuff++) = i2c_data_receive(hi2c->i2cx);
2110
2111 if ((hi2c->psize > 0))
2112 {
2113 hi2c->pcount--;
2114 hi2c->psize--;
2115 }
2116 }
2117
2118 /* transfer complete */
2119 hi2c->status = I2C_END;
2120 }
2121
2122 return I2C_OK;
2123 }
2124
2125 /**
2126 * @brief dma processing function.
2127 * @param hi2c: the handle points to the operation information.
2128 * @retval none.
2129 */
2130 void i2c_dma_tx_rx_irq_handler(i2c_handle_type* hi2c, dma_channel_type* dma_channel)
2131 {
2132 /* transfer complete */
2133 if (dma_flag_get(DMA_GET_TC_FLAG(dma_channel)) != RESET)
2134 {
2135 /* disable the transfer complete interrupt */
2136 dma_interrupt_enable(dma_channel, DMA_FDT_INT, FALSE);
2137
2138 /* clear the transfer complete flag */
2139 dma_flag_clear(DMA_GET_TC_FLAG(dma_channel));
2140
2141 /* disable dma request */
2142 i2c_dma_enable(hi2c->i2cx, DMA_GET_REQUEST(dma_channel), FALSE);
2143
2144 /* disable dma channel */
2145 dma_channel_enable(dma_channel, FALSE);
2146
2147 switch(hi2c->mode)
2148 {
2149 case I2C_DMA_MA_TX:
2150 case I2C_DMA_MA_RX:
2151 {
2152 /* update the number of transfers */
2153 hi2c->pcount -= hi2c->psize;
2154
2155 /* transfer complete */
2156 if (hi2c->pcount == 0)
2157 {
2158 /* enable stop interrupt */
2159 i2c_interrupt_enable(hi2c->i2cx, I2C_STOP_INT, TRUE);
2160 }
2161 /* the transfer has not been completed */
2162 else
2163 {
2164 /* update the buffer pointer of transfers */
2165 hi2c->pbuff += hi2c->psize;
2166
2167 /* set the number to be transferred */
2168 if (hi2c->pcount > MAX_TRANSFER_CNT)
2169 {
2170 hi2c->psize = MAX_TRANSFER_CNT;
2171 }
2172 else
2173 {
2174 hi2c->psize = hi2c->pcount;
2175 }
2176
2177 /* config dma channel, continue to transfer data */
2178 i2c_dma_config(hi2c, dma_channel, hi2c->pbuff, hi2c->psize);
2179
2180 /* enable tdc interrupt */
2181 i2c_interrupt_enable(hi2c->i2cx, I2C_TDC_INT, TRUE);
2182 }
2183 }break;
2184 case I2C_DMA_SLA_TX:
2185 case I2C_DMA_SLA_RX:
2186 {
2187
2188 }break;
2189
2190 default:break;
2191 }
2192 }
2193 }
2194
2195 /**
2196 * @brief dma transmission complete interrupt function.
2197 * @param hi2c: the handle points to the operation information.
2198 * @retval none.
2199 */
2200 void i2c_dma_tx_irq_handler(i2c_handle_type* hi2c)
2201 {
2202 i2c_dma_tx_rx_irq_handler(hi2c, hi2c->dma_tx_channel);
2203 }
2204
2205 /**
2206 * @brief dma reveive complete interrupt function.
2207 * @param hi2c: the handle points to the operation information.
2208 * @retval none.
2209 */
2210 void i2c_dma_rx_irq_handler(i2c_handle_type* hi2c)
2211 {
2212 i2c_dma_tx_rx_irq_handler(hi2c, hi2c->dma_rx_channel);
2213 }
2214
2215 /**
2216 * @brief interrupt procession function.
2217 * @param hi2c: the handle points to the operation information.
2218 * @retval none.
2219 */
2220 void i2c_evt_irq_handler(i2c_handle_type* hi2c)
2221 {
2222 switch(hi2c->mode)
2223 {
2224 case I2C_INT_MA_TX:
2225 case I2C_INT_MA_RX:
2226 {
2227 i2c_master_irq_handler_int(hi2c);
2228 }break;
2229 case I2C_INT_SLA_TX:
2230 case I2C_INT_SLA_RX:
2231 {
2232 i2c_slave_irq_handler_int(hi2c);
2233 }break;
2234 case I2C_DMA_MA_TX:
2235 case I2C_DMA_MA_RX:
2236 {
2237 i2c_master_irq_handler_dma(hi2c);
2238 }break;
2239 case I2C_DMA_SLA_TX:
2240 case I2C_DMA_SLA_RX:
2241 {
2242 i2c_slave_irq_handler_dma(hi2c);
2243 }break;
2244
2245 default:break;
2246 }
2247 }
2248
2249 /**
2250 * @brief dma reveive complete interrupt function.
2251 * @param hi2c: the handle points to the operation information.
2252 * @retval none.
2253 */
2254 void i2c_err_irq_handler(i2c_handle_type* hi2c)
2255 {
2256 /* buserr */
2257 if (i2c_flag_get(hi2c->i2cx, I2C_BUSERR_FLAG) != RESET)
2258 {
2259 hi2c->error_code = I2C_ERR_INTERRUPT;
2260
2261 /* clear flag */
2262 i2c_flag_clear(hi2c->i2cx, I2C_BUSERR_FLAG);
2263
2264 /* disable interrupts */
2265 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
2266 }
2267
2268 /* arlost */
2269 if (i2c_flag_get(hi2c->i2cx, I2C_ARLOST_FLAG) != RESET)
2270 {
2271 hi2c->error_code = I2C_ERR_INTERRUPT;
2272
2273 /* clear flag */
2274 i2c_flag_clear(hi2c->i2cx, I2C_ARLOST_FLAG);
2275
2276 /* disable interrupts */
2277 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
2278 }
2279
2280 /* ouf */
2281 if (i2c_flag_get(hi2c->i2cx, I2C_OUF_FLAG) != RESET)
2282 {
2283 hi2c->error_code = I2C_ERR_INTERRUPT;
2284
2285 /* clear flag */
2286 i2c_flag_clear(hi2c->i2cx, I2C_OUF_FLAG);
2287
2288 /* disable interrupts */
2289 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
2290 }
2291
2292 /* pecerr */
2293 if (i2c_flag_get(hi2c->i2cx, I2C_PECERR_FLAG) != RESET)
2294 {
2295 hi2c->error_code = I2C_ERR_INTERRUPT;
2296
2297 /* clear flag */
2298 i2c_flag_clear(hi2c->i2cx, I2C_PECERR_FLAG);
2299
2300 /* disable interrupts */
2301 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
2302
2303 }
2304
2305 /* timeout */
2306 if (i2c_flag_get(hi2c->i2cx, I2C_TMOUT_FLAG) != RESET)
2307 {
2308 hi2c->error_code = I2C_ERR_INTERRUPT;
2309
2310 /* clear flag */
2311 i2c_flag_clear(hi2c->i2cx, I2C_TMOUT_FLAG);
2312
2313 /* disable interrupts */
2314 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
2315 }
2316
2317 /* alertf */
2318 if (i2c_flag_get(hi2c->i2cx, I2C_ALERTF_FLAG) != RESET)
2319 {
2320 hi2c->error_code = I2C_ERR_INTERRUPT;
2321
2322 /* clear flag */
2323 i2c_flag_clear(hi2c->i2cx, I2C_ALERTF_FLAG);
2324
2325 /* disable interrupts */
2326 i2c_interrupt_enable(hi2c->i2cx, I2C_ERR_INT, FALSE);
2327 }
2328 }
2329
2330 /**
2331 * @}
2332 */
INAV: Navigation-enabled flight control software