Blackbox device type 'file' (SITL) considered working when file handler is available
[inav.git] / src / main / drivers / timer_at32f43x.c
bloba49eba86f909d943c0d22f5b5908e4da01dc38ed
1 /*
2 * This file is part of INAV.
4 * INAV is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * INAV is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with INAV. If not, see <http://www.gnu.org/licenses/>.
18 #include <stdbool.h>
19 #include <stdint.h>
21 #include "platform.h"
23 #include "build/atomic.h"
25 #include "common/utils.h"
27 #include "drivers/io.h"
28 #include "drivers/rcc.h"
29 #include "drivers/time.h"
30 #include "drivers/nvic.h"
31 #include "drivers/timer.h"
32 #include "drivers/timer_impl.h"
33 #include "at32f435_437.h"
35 const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
36 #if defined(TMR1)
37 [0] = { .tim = TMR1, .rcc = RCC_APB2(TMR1), .irq = TMR1_CH_IRQn, .secondIrq = TMR1_OVF_TMR10_IRQn },
38 #endif
40 #if defined(TMR2)
41 [1] = { .tim = TMR2, .rcc = RCC_APB1(TMR2), .irq = TMR2_GLOBAL_IRQn},
42 #endif
44 #if defined(TMR3)
45 [2] = { .tim = TMR3, .rcc = RCC_APB1(TMR3), .irq = TMR3_GLOBAL_IRQn},
46 #endif
48 #if defined(TMR4)
49 [3] = { .tim = TMR4, .rcc = RCC_APB1(TMR4), .irq = TMR4_GLOBAL_IRQn},
50 #endif
52 #if defined(TMR5)
53 [4] = { .tim = TMR5, .rcc = RCC_APB1(TMR5), .irq = TMR5_GLOBAL_IRQn},
54 #endif
56 #if defined(TMR6)
57 [5] = { .tim = TMR6, .rcc = RCC_APB1(TMR6), .irq = 0},
58 #endif
60 #if defined(TMR7)
61 [6] = { .tim = TMR7, .rcc = RCC_APB1(TMR7), .irq = 0},
62 #endif
64 #if defined(TMR8)
65 [7] = { .tim = TMR8, .rcc = RCC_APB2(TMR8), .irq = TMR8_CH_IRQn, .secondIrq = TMR8_OVF_TMR13_IRQn },
66 #endif
68 #if defined(TMR9)
69 [8] = { .tim = TMR9, .rcc = RCC_APB2(TMR9), .irq = TMR1_BRK_TMR9_IRQn},
70 #endif
72 #if defined(TMR10)
73 [9] = { .tim = TMR10, .rcc = RCC_APB2(TMR10), .irq = TMR1_OVF_TMR10_IRQn},
74 #endif
76 #if defined(TMR11)
77 [10] = { .tim = TMR11, .rcc = RCC_APB2(TMR11), .irq = TMR1_TRG_HALL_TMR11_IRQn},
78 #endif
80 #if defined(TMR12)
81 [11] = { .tim = TMR12, .rcc = RCC_APB1(TMR12), .irq = TMR8_BRK_TMR12_IRQn},
82 #endif
84 #if defined(TMR13)
85 [12] = { .tim = TMR13, .rcc = RCC_APB1(TMR13), .irq = TMR8_OVF_TMR13_IRQn},
86 #endif
88 #if defined(TMR14)
89 [13] = { .tim = TMR14, .rcc = RCC_APB1(TMR14), .irq = TMR8_TRG_HALL_TMR14_IRQn},
90 #endif
92 #if defined(TMR20)
93 [14] = { .tim = TMR20, .rcc = RCC_APB2(TMR20), .irq = TMR20_CH_IRQn},
94 #endif
95 };
97 uint32_t timerClock(tmr_type *tim)
99 UNUSED(tim);
100 return SystemCoreClock;
103 // Timer IRQ handlers
104 _TIM_IRQ_HANDLER(TMR1_CH_IRQHandler, 1);
105 _TIM_IRQ_HANDLER2(TMR1_BRK_TMR9_IRQHandler, 1, 9);
106 _TIM_IRQ_HANDLER2(TMR1_OVF_TMR10_IRQHandler, 1, 10);
107 _TIM_IRQ_HANDLER2(TMR1_TRG_HALL_TMR11_IRQHandler, 1, 11);
108 _TIM_IRQ_HANDLER(TMR2_GLOBAL_IRQHandler, 2);
109 _TIM_IRQ_HANDLER(TMR3_GLOBAL_IRQHandler, 3);
110 _TIM_IRQ_HANDLER(TMR4_GLOBAL_IRQHandler, 4);
111 _TIM_IRQ_HANDLER(TMR5_GLOBAL_IRQHandler, 5);
112 _TIM_IRQ_HANDLER(TMR8_CH_IRQHandler, 8);
113 //_TIM_IRQ_HANDLER(TIM8_UP_IRQHandler, 8);
114 _TIM_IRQ_HANDLER2(TMR8_BRK_TMR12_IRQHandler, 8, 12);
115 _TIM_IRQ_HANDLER2(TMR8_OVF_TMR13_IRQHandler, 8, 13);
116 _TIM_IRQ_HANDLER2(TMR8_TRG_HALL_TMR14_IRQHandler, 8, 14);
117 _TIM_IRQ_HANDLER(TMR20_CH_IRQHandler, 20);