src/main/drivers/timer_def_stm32f4xx.h

   1 /*
   2  * This file is part of INAV.
   3  *
   4  * INAV is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * INAV is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with INAV.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #pragma once
  19
  20 #define timerDMASafeType_t  uint32_t
  21
  22 #define DEF_TIM_DMAMAP__D(dma, stream, channel)         DMA_TAG(dma, stream, channel)
  23 #define DEF_TIM_DMAMAP__NONE                            DMA_NONE
  24
  25 #define DEF_TIM(tim, ch, pin, usage, flags, dmavar)     { tim, IO_TAG(pin), DEF_TIM_CHNL_ ## ch, DEF_TIM_OUTPUT(ch) | flags, IOCFG_AF_PP, GPIO_AF_ ## tim, usage, DEF_TIM_DMAMAP(dmavar, tim ## _ ## ch) }
  26
  27 // AF mappings
  28 #define DEF_TIM_AF(timch, pin)                  CONCAT(DEF_TIM_AF__, DEF_TIM_AF__ ## pin ## __ ## timch)
  29 #define DEF_TIM_AF__D(af_n)                     GPIO_AF_ ## af_n
  30
  31 /* add the DMA mappings here */
  32
  33 #define DEF_TIM_DMA__BTCH_TIM1_CH1    D(2, 6, 0),D(2, 1, 6),D(2, 3, 6)
  34 #define DEF_TIM_DMA__BTCH_TIM1_CH2    D(2, 6, 0),D(2, 2, 6)
  35 #define DEF_TIM_DMA__BTCH_TIM1_CH3    D(2, 6, 0),D(2, 6, 6)
  36 #define DEF_TIM_DMA__BTCH_TIM1_CH4    D(2, 4, 6)
  37
  38 #define DEF_TIM_DMA__BTCH_TIM2_CH1    D(1, 5, 3)
  39 #define DEF_TIM_DMA__BTCH_TIM2_CH2    D(1, 6, 3)
  40 #define DEF_TIM_DMA__BTCH_TIM2_CH3    D(1, 1, 3)
  41 #define DEF_TIM_DMA__BTCH_TIM2_CH4    D(1, 7, 3),D(1, 6, 3)
  42
  43 #define DEF_TIM_DMA__BTCH_TIM3_CH1    D(1, 4, 5)
  44 #define DEF_TIM_DMA__BTCH_TIM3_CH2    D(1, 5, 5)
  45 #define DEF_TIM_DMA__BTCH_TIM3_CH3    D(1, 7, 5)
  46 #define DEF_TIM_DMA__BTCH_TIM3_CH4    D(1, 2, 5)
  47
  48 #define DEF_TIM_DMA__BTCH_TIM4_CH1    D(1, 0, 2)
  49 #define DEF_TIM_DMA__BTCH_TIM4_CH2    D(1, 3, 2)
  50 #define DEF_TIM_DMA__BTCH_TIM4_CH3    D(1, 7, 2)
  51
  52 #define DEF_TIM_DMA__BTCH_TIM5_CH1    D(1, 2, 6)
  53 #define DEF_TIM_DMA__BTCH_TIM5_CH2    D(1, 4, 6)
  54 #define DEF_TIM_DMA__BTCH_TIM5_CH3    D(1, 0, 6)
  55 #define DEF_TIM_DMA__BTCH_TIM5_CH4    D(1, 1, 6),D(1, 3, 6)
  56
  57 #define DEF_TIM_DMA__BTCH_TIM8_CH1    D(2, 2, 0),D(2, 2, 7)
  58 #define DEF_TIM_DMA__BTCH_TIM8_CH2    D(2, 2, 0),D(2, 3, 7)
  59 #define DEF_TIM_DMA__BTCH_TIM8_CH3    D(2, 2, 0),D(2, 4, 7)
  60 #define DEF_TIM_DMA__BTCH_TIM8_CH4    D(2, 7, 7)
  61
  62 #define DEF_TIM_DMA__BTCH_TIM4_CH4    NONE
  63
  64 #define DEF_TIM_DMA__BTCH_TIM9_CH1    NONE
  65 #define DEF_TIM_DMA__BTCH_TIM9_CH2    NONE
  66
  67 #define DEF_TIM_DMA__BTCH_TIM10_CH1   NONE
  68
  69 #define DEF_TIM_DMA__BTCH_TIM11_CH1   NONE
  70
  71 #define DEF_TIM_DMA__BTCH_TIM12_CH1   NONE
  72 #define DEF_TIM_DMA__BTCH_TIM12_CH2   NONE
  73
  74 #define DEF_TIM_DMA__BTCH_TIM13_CH1   NONE
  75
  76 #define DEF_TIM_DMA__BTCH_TIM14_CH1   NONE
  77