Blackbox device type 'file' (SITL) considered working when file handler is available
[inav.git] / src / main / startup / startup_stm32f446xx.s
blob4686636823539b5869a2901f53bf3933796b93fa
1 /**
2 ******************************************************************************
3 * @file startup_stm32f40_41xxx.s
4 * @author MCD Application Team
5 * @version V1.6.1
6 * @date 21-October-2015
7 * @brief STM32F40xxx/41xxx Devices vector table for Atollic TrueSTUDIO toolchain.
8 * Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
9 * This module performs:
10 * - Set the initial SP
11 * - Set the initial PC == Reset_Handler,
12 * - Set the vector table entries with the exceptions ISR address
13 * - Configure the clock system and the external SRAM mounted on
14 * STM324xG-EVAL board to be used as data memory (optional,
15 * to be enabled by user)
16 * - Branches to main in the C library (which eventually
17 * calls main()).
18 * After Reset the Cortex-M4 processor is in Thread mode,
19 * priority is Privileged, and the Stack is set to Main.
20 ******************************************************************************
21 * @attention
23 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
25 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
26 * You may not use this file except in compliance with the License.
27 * You may obtain a copy of the License at:
29 * http://www.st.com/software_license_agreement_liberty_v2
31 * Unless required by applicable law or agreed to in writing, software
32 * distributed under the License is distributed on an "AS IS" BASIS,
33 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34 * See the License for the specific language governing permissions and
35 * limitations under the License.
37 ******************************************************************************
40 .syntax unified
41 .cpu cortex-m4
42 .fpu softvfp
43 .thumb
45 .global g_pfnVectors
46 .global Default_Handler
48 /* start address for the initialization values of the .data section.
49 defined in linker script */
50 .word _sidata
51 /* start address for the .data section. defined in linker script */
52 .word _sdata
53 /* end address for the .data section. defined in linker script */
54 .word _edata
55 /* start address for the .bss section. defined in linker script */
56 .word _sbss
57 /* end address for the .bss section. defined in linker script */
58 .word _ebss
59 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
61 /**
62 * @brief This is the code that gets called when the processor first
63 * starts execution following a reset event. Only the absolutely
64 * necessary set is performed, after which the application
65 * supplied main() routine is called.
66 * @param None
67 * @retval : None
70 .section .text.Reset_Handler
71 .weak Reset_Handler
72 .type Reset_Handler, %function
74 Reset_Handler:
75 ldr sp, =_estack /* set stack pointer */
77 // Enable CCM
78 // RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN;
79 ldr r0, =0x40023800 // RCC_BASE
80 ldr r1, [r0, #0x30] // AHB1ENR
81 orr r1, r1, 0x00100000 // RCC_AHB1ENR_CCMDATARAMEN
82 str r1, [r0, #0x30]
83 dsb
85 // Defined in C code
86 bl persistentObjectInit
87 bl checkForBootLoaderRequest
89 /* Copy the data segment initializers from flash to SRAM */
90 movs r1, #0
91 b LoopCopyDataInit
93 CopyDataInit:
94 ldr r3, =_sidata
95 ldr r3, [r3, r1]
96 str r3, [r0, r1]
97 adds r1, r1, #4
99 LoopCopyDataInit:
100 ldr r0, =_sdata
101 ldr r3, =_edata
102 adds r2, r0, r1
103 cmp r2, r3
104 bcc CopyDataInit
105 ldr r2, =_sbss
106 b LoopFillZerobss
107 /* Zero fill the bss segment. */
108 FillZerobss:
109 movs r3, #0
110 str r3, [r2], #4
112 LoopFillZerobss:
113 ldr r3, = _ebss
114 cmp r2, r3
115 bcc FillZerobss
117 /* Zero fill FASTRAM */
118 ldr r2, =__fastram_bss_start__
119 b LoopFillZeroFASTRAM
121 FillZeroFASTRAM:
122 movs r3, #0
123 str r3, [r2], #4
125 LoopFillZeroFASTRAM:
126 ldr r3, = __fastram_bss_end__
127 cmp r2, r3
128 bcc FillZeroFASTRAM
130 /* Mark the heap and stack */
131 ldr r2, =_heap_stack_begin
132 b LoopMarkHeapStack
134 MarkHeapStack:
135 movs r3, 0xa5a5a5a5
136 str r3, [r2], #4
138 LoopMarkHeapStack:
139 ldr r3, = _heap_stack_end
140 cmp r2, r3
141 bcc MarkHeapStack
143 /*FPU settings*/
144 ldr r0, =0xE000ED88 /* Enable CP10,CP11 */
145 ldr r1,[r0]
146 orr r1,r1,#(0xF << 20)
147 str r1,[r0]
149 /* Call the clock system intitialization function.*/
150 bl SystemInit
152 /* Call the application entry point.*/
153 bl main
154 bx lr
156 LoopForever:
157 b LoopForever
159 Reboot_Loader: // mj666
161 // Reboot to ROM // mj666
162 ldr r0, =0x1FFF0000 // mj666
163 ldr sp,[r0, #0] // mj666
164 ldr r0,[r0, #4] // mj666
165 bx r0 // mj666
166 .size Reset_Handler, .-Reset_Handler
169 * @brief This is the code that gets called when the processor receives an
170 * unexpected interrupt. This simply enters an infinite loop, preserving
171 * the system state for examination by a debugger.
172 * @param None
173 * @retval None
175 .section .text.Default_Handler,"ax",%progbits
176 Default_Handler:
177 Infinite_Loop:
178 b Infinite_Loop
179 .size Default_Handler, .-Default_Handler
180 /******************************************************************************
182 * The minimal vector table for a Cortex M3. Note that the proper constructs
183 * must be placed on this to ensure that it ends up at physical address
184 * 0x0000.0000.
186 *******************************************************************************/
187 .section .isr_vector,"a",%progbits
188 .type g_pfnVectors, %object
189 .size g_pfnVectors, .-g_pfnVectors
192 g_pfnVectors:
193 .word _estack
194 .word Reset_Handler
196 .word NMI_Handler
197 .word HardFault_Handler
198 .word MemManage_Handler
199 .word BusFault_Handler
200 .word UsageFault_Handler
201 .word 0
202 .word 0
203 .word 0
204 .word 0
205 .word SVC_Handler
206 .word DebugMon_Handler
207 .word 0
208 .word PendSV_Handler
209 .word SysTick_Handler
211 /* External Interrupts */
212 .word WWDG_IRQHandler /* Window WatchDog */
213 .word PVD_IRQHandler /* PVD through EXTI Line detection */
214 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
215 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
216 .word FLASH_IRQHandler /* FLASH */
217 .word RCC_IRQHandler /* RCC */
218 .word EXTI0_IRQHandler /* EXTI Line0 */
219 .word EXTI1_IRQHandler /* EXTI Line1 */
220 .word EXTI2_IRQHandler /* EXTI Line2 */
221 .word EXTI3_IRQHandler /* EXTI Line3 */
222 .word EXTI4_IRQHandler /* EXTI Line4 */
223 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
224 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
225 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
226 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
227 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
228 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
229 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
230 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
231 .word CAN1_TX_IRQHandler /* CAN1 TX */
232 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
233 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
234 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
235 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
236 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
237 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
238 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
239 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
240 .word TIM2_IRQHandler /* TIM2 */
241 .word TIM3_IRQHandler /* TIM3 */
242 .word TIM4_IRQHandler /* TIM4 */
243 .word I2C1_EV_IRQHandler /* I2C1 Event */
244 .word I2C1_ER_IRQHandler /* I2C1 Error */
245 .word I2C2_EV_IRQHandler /* I2C2 Event */
246 .word I2C2_ER_IRQHandler /* I2C2 Error */
247 .word SPI1_IRQHandler /* SPI1 */
248 .word SPI2_IRQHandler /* SPI2 */
249 .word USART1_IRQHandler /* USART1 */
250 .word USART2_IRQHandler /* USART2 */
251 .word USART3_IRQHandler /* USART3 */
252 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
253 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
254 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
255 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
256 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
257 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
258 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
259 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
260 .word FMC_IRQHandler /* FMC */
261 .word SDIO_IRQHandler /* SDIO */
262 .word TIM5_IRQHandler /* TIM5 */
263 .word SPI3_IRQHandler /* SPI3 */
264 .word UART4_IRQHandler /* UART4 */
265 .word UART5_IRQHandler /* UART5 */
266 .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
267 .word TIM7_IRQHandler /* TIM7 */
268 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
269 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
270 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
271 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
272 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
273 .word 0 /* Reserved */
274 .word 0 /* Reserved */
275 .word CAN2_TX_IRQHandler /* CAN2 TX */
276 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
277 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
278 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
279 .word OTG_FS_IRQHandler /* USB OTG FS */
280 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
281 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
282 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
283 .word USART6_IRQHandler /* USART6 */
284 .word I2C3_EV_IRQHandler /* I2C3 event */
285 .word I2C3_ER_IRQHandler /* I2C3 error */
286 .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
287 .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
288 .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
289 .word OTG_HS_IRQHandler /* USB OTG HS */
290 .word DCMI_IRQHandler /* DCMI */
291 .word 0 /* Reserved */
292 .word 0 /* Reserved */
293 .word FPU_IRQHandler /* FPU */
294 .word 0 /* Reserved */
295 .word 0 /* Reserved */
296 .word SPI4_IRQHandler /* SPI4 */
297 .word 0 /* Reserved */
298 .word 0 /* Reserved */
299 .word SAI1_IRQHandler /* SAI1 */
300 .word 0 /* Reserved */
301 .word 0 /* Reserved */
302 .word 0 /* Reserved */
303 .word SAI2_IRQHandler /* SAI2 */
304 .word QUADSPI_IRQHandler /* QuadSPI */
305 .word CEC_IRQHandler /* CEC */
306 .word SPDIF_RX_IRQHandler /* SPDIF RX */
307 .word FMPI2C1_Event_IRQHandler /* FMPI2C 1 Event */
308 .word FMPI2C1_Error_IRQHandler /* FMPI2C 1 Error */
310 /*******************************************************************************
312 * Provide weak aliases for each Exception handler to the Default_Handler.
313 * As they are weak aliases, any function with the same name will override
314 * this definition.
316 *******************************************************************************/
317 .weak NMI_Handler
318 .thumb_set NMI_Handler,Default_Handler
320 .weak HardFault_Handler
321 .thumb_set HardFault_Handler,Default_Handler
323 .weak MemManage_Handler
324 .thumb_set MemManage_Handler,Default_Handler
326 .weak BusFault_Handler
327 .thumb_set BusFault_Handler,Default_Handler
329 .weak UsageFault_Handler
330 .thumb_set UsageFault_Handler,Default_Handler
332 .weak SVC_Handler
333 .thumb_set SVC_Handler,Default_Handler
335 .weak DebugMon_Handler
336 .thumb_set DebugMon_Handler,Default_Handler
338 .weak PendSV_Handler
339 .thumb_set PendSV_Handler,Default_Handler
341 .weak SysTick_Handler
342 .thumb_set SysTick_Handler,Default_Handler
344 .weak WWDG_IRQHandler
345 .thumb_set WWDG_IRQHandler,Default_Handler
347 .weak PVD_IRQHandler
348 .thumb_set PVD_IRQHandler,Default_Handler
350 .weak TAMP_STAMP_IRQHandler
351 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
353 .weak RTC_WKUP_IRQHandler
354 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
356 .weak FLASH_IRQHandler
357 .thumb_set FLASH_IRQHandler,Default_Handler
359 .weak RCC_IRQHandler
360 .thumb_set RCC_IRQHandler,Default_Handler
362 .weak EXTI0_IRQHandler
363 .thumb_set EXTI0_IRQHandler,Default_Handler
365 .weak EXTI1_IRQHandler
366 .thumb_set EXTI1_IRQHandler,Default_Handler
368 .weak EXTI2_IRQHandler
369 .thumb_set EXTI2_IRQHandler,Default_Handler
371 .weak EXTI3_IRQHandler
372 .thumb_set EXTI3_IRQHandler,Default_Handler
374 .weak EXTI4_IRQHandler
375 .thumb_set EXTI4_IRQHandler,Default_Handler
377 .weak DMA1_Stream0_IRQHandler
378 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
380 .weak DMA1_Stream1_IRQHandler
381 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
383 .weak DMA1_Stream2_IRQHandler
384 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
386 .weak DMA1_Stream3_IRQHandler
387 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
389 .weak DMA1_Stream4_IRQHandler
390 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
392 .weak DMA1_Stream5_IRQHandler
393 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
395 .weak DMA1_Stream6_IRQHandler
396 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
398 .weak ADC_IRQHandler
399 .thumb_set ADC_IRQHandler,Default_Handler
401 .weak CAN1_TX_IRQHandler
402 .thumb_set CAN1_TX_IRQHandler,Default_Handler
404 .weak CAN1_RX0_IRQHandler
405 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
407 .weak CAN1_RX1_IRQHandler
408 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
410 .weak CAN1_SCE_IRQHandler
411 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
413 .weak EXTI9_5_IRQHandler
414 .thumb_set EXTI9_5_IRQHandler,Default_Handler
416 .weak TIM1_BRK_TIM9_IRQHandler
417 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
419 .weak TIM1_UP_TIM10_IRQHandler
420 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
422 .weak TIM1_TRG_COM_TIM11_IRQHandler
423 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
425 .weak TIM1_CC_IRQHandler
426 .thumb_set TIM1_CC_IRQHandler,Default_Handler
428 .weak TIM2_IRQHandler
429 .thumb_set TIM2_IRQHandler,Default_Handler
431 .weak TIM3_IRQHandler
432 .thumb_set TIM3_IRQHandler,Default_Handler
434 .weak TIM4_IRQHandler
435 .thumb_set TIM4_IRQHandler,Default_Handler
437 .weak I2C1_EV_IRQHandler
438 .thumb_set I2C1_EV_IRQHandler,Default_Handler
440 .weak I2C1_ER_IRQHandler
441 .thumb_set I2C1_ER_IRQHandler,Default_Handler
443 .weak I2C2_EV_IRQHandler
444 .thumb_set I2C2_EV_IRQHandler,Default_Handler
446 .weak I2C2_ER_IRQHandler
447 .thumb_set I2C2_ER_IRQHandler,Default_Handler
449 .weak SPI1_IRQHandler
450 .thumb_set SPI1_IRQHandler,Default_Handler
452 .weak SPI2_IRQHandler
453 .thumb_set SPI2_IRQHandler,Default_Handler
455 .weak USART1_IRQHandler
456 .thumb_set USART1_IRQHandler,Default_Handler
458 .weak USART2_IRQHandler
459 .thumb_set USART2_IRQHandler,Default_Handler
461 .weak USART3_IRQHandler
462 .thumb_set USART3_IRQHandler,Default_Handler
464 .weak EXTI15_10_IRQHandler
465 .thumb_set EXTI15_10_IRQHandler,Default_Handler
467 .weak RTC_Alarm_IRQHandler
468 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
470 .weak OTG_FS_WKUP_IRQHandler
471 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
473 .weak TIM8_BRK_TIM12_IRQHandler
474 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
476 .weak TIM8_UP_TIM13_IRQHandler
477 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
479 .weak TIM8_TRG_COM_TIM14_IRQHandler
480 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
482 .weak TIM8_CC_IRQHandler
483 .thumb_set TIM8_CC_IRQHandler,Default_Handler
485 .weak DMA1_Stream7_IRQHandler
486 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
488 .weak FMC_IRQHandler
489 .thumb_set FMC_IRQHandler,Default_Handler
491 .weak SDIO_IRQHandler
492 .thumb_set SDIO_IRQHandler,Default_Handler
494 .weak TIM5_IRQHandler
495 .thumb_set TIM5_IRQHandler,Default_Handler
497 .weak SPI3_IRQHandler
498 .thumb_set SPI3_IRQHandler,Default_Handler
500 .weak UART4_IRQHandler
501 .thumb_set UART4_IRQHandler,Default_Handler
503 .weak UART5_IRQHandler
504 .thumb_set UART5_IRQHandler,Default_Handler
506 .weak TIM6_DAC_IRQHandler
507 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
509 .weak TIM7_IRQHandler
510 .thumb_set TIM7_IRQHandler,Default_Handler
512 .weak DMA2_Stream0_IRQHandler
513 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
515 .weak DMA2_Stream1_IRQHandler
516 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
518 .weak DMA2_Stream2_IRQHandler
519 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
521 .weak DMA2_Stream3_IRQHandler
522 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
524 .weak DMA2_Stream4_IRQHandler
525 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
527 .weak CAN2_TX_IRQHandler
528 .thumb_set CAN2_TX_IRQHandler,Default_Handler
530 .weak CAN2_RX0_IRQHandler
531 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
533 .weak CAN2_RX1_IRQHandler
534 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
536 .weak CAN2_SCE_IRQHandler
537 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
539 .weak OTG_FS_IRQHandler
540 .thumb_set OTG_FS_IRQHandler,Default_Handler
542 .weak DMA2_Stream5_IRQHandler
543 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
545 .weak DMA2_Stream6_IRQHandler
546 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
548 .weak DMA2_Stream7_IRQHandler
549 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
551 .weak USART6_IRQHandler
552 .thumb_set USART6_IRQHandler,Default_Handler
554 .weak I2C3_EV_IRQHandler
555 .thumb_set I2C3_EV_IRQHandler,Default_Handler
557 .weak I2C3_ER_IRQHandler
558 .thumb_set I2C3_ER_IRQHandler,Default_Handler
560 .weak OTG_HS_EP1_OUT_IRQHandler
561 .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
563 .weak OTG_HS_EP1_IN_IRQHandler
564 .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
566 .weak OTG_HS_WKUP_IRQHandler
567 .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
569 .weak OTG_HS_IRQHandler
570 .thumb_set OTG_HS_IRQHandler,Default_Handler
572 .weak DCMI_IRQHandler
573 .thumb_set DCMI_IRQHandler,Default_Handler
575 .weak FPU_IRQHandler
576 .thumb_set FPU_IRQHandler,Default_Handler
578 .weak SPI4_IRQHandler
579 .thumb_set SPI4_IRQHandler,Default_Handler
581 .weak SAI1_IRQHandler
582 .thumb_set SAI1_IRQHandler,Default_Handler
584 .weak SAI2_IRQHandler
585 .thumb_set SAI2_IRQHandler,Default_Handler
587 .weak QUADSPI_IRQHandler
588 .thumb_set QUADSPI_IRQHandler,Default_Handler
590 .weak CEC_IRQHandler
591 .thumb_set CEC_IRQHandler,Default_Handler
593 .weak SPDIF_RX_IRQHandler
594 .thumb_set SPDIF_RX_IRQHandler,Default_Handler
596 .weak FMPI2C1_Event_IRQHandler
597 .thumb_set FMPI2C1_Event_IRQHandler,Default_Handler
599 .weak FMPI2C1_Error_IRQHandler
600 .thumb_set FMPI2C1_Error_IRQHandler,Default_Handler
602 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/