src/main/startup/startup_stm32f765xx.s

   1 /**
   2   ******************************************************************************
   3   * @file      startup_stm32f765xx.s
   4   * @author    MCD Application Team
   5   * @version   V1.2.0
   6   * @date      30-December-2016
   7   * @brief     STM32F765xx Devices vector table for GCC based toolchain.
   8   *            This module performs:
   9   *                - Set the initial SP
  10   *                - Set the initial PC == Reset_Handler,
  11   *                - Set the vector table entries with the exceptions ISR address
  12   *                - Branches to main in the C library (which eventually
  13   *                  calls main()).
  14   *            After Reset the Cortex-M7 processor is in Thread mode,
  15   *            priority is Privileged, and the Stack is set to Main.
  16   ******************************************************************************
  17   * @attention
  18   *
  19   * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
  20   *
  21   * Redistribution and use in source and binary forms, with or without modification,
  22   * are permitted provided that the following conditions are met:
  23   *   1. Redistributions of source code must retain the above copyright notice,
  24   *      this list of conditions and the following disclaimer.
  25   *   2. Redistributions in binary form must reproduce the above copyright notice,
  26   *      this list of conditions and the following disclaimer in the documentation
  27   *      and/or other materials provided with the distribution.
  28   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  29   *      may be used to endorse or promote products derived from this software
  30   *      without specific prior written permission.
  31   *
  32   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  36   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  38   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  39   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  40   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42   *
  43   ******************************************************************************
  44   */
  45
  46   .syntax unified
  47   .cpu cortex-m7
  48   .fpu softvfp
  49   .thumb
  50
  51 .global  g_pfnVectors
  52 .global  Default_Handler
  53
  54 /* start address for the initialization values of the .data section.
  55 defined in linker script */
  56 .word  _sidata
  57 /* start address for the .data section. defined in linker script */
  58 .word  _sdata
  59 /* end address for the .data section. defined in linker script */
  60 .word  _edata
  61 /* start address for the .bss section. defined in linker script */
  62 .word  _sbss
  63 /* end address for the .bss section. defined in linker script */
  64 .word  _ebss
  65 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  66
  67 /**
  68  * @brief  This is the code that gets called when the processor first
  69  *          starts execution following a reset event. Only the absolutely
  70  *          necessary set is performed, after which the application
  71  *          supplied main() routine is called.
  72  * @param  None
  73  * @retval : None
  74 */
  75
  76   .section  .text.Reset_Handler
  77   .weak  Reset_Handler
  78   .type  Reset_Handler, %function
  79 Reset_Handler:
  80   ldr   sp, =_estack      /* set stack pointer */
  81
  82   bl persistentObjectInit
  83
  84 /* Copy the data segment initializers from flash to SRAM */
  85   movs  r1, #0
  86   b  LoopCopyDataInit
  87
  88 CopyDataInit:
  89   ldr  r3, =_sidata
  90   ldr  r3, [r3, r1]
  91   str  r3, [r0, r1]
  92   adds  r1, r1, #4
  93
  94 LoopCopyDataInit:
  95   ldr  r0, =_sdata
  96   ldr  r3, =_edata
  97   adds  r2, r0, r1
  98   cmp  r2, r3
  99   bcc  CopyDataInit
 100   ldr  r2, =_sbss
 101   b  LoopFillZerobss
 102
 103 /* Zero fill the bss segment. */
 104 FillZerobss:
 105   movs  r3, #0
 106   str  r3, [r2], #4
 107
 108 LoopFillZerobss:
 109   ldr  r3, = _ebss
 110   cmp  r2, r3
 111   bcc  FillZerobss
 112
 113 /* Zero fill FASTRAM */
 114   ldr  r2, =__fastram_bss_start__
 115   b  LoopFillZeroFASTRAM
 116
 117 FillZeroFASTRAM:
 118   movs  r3, #0
 119   str  r3, [r2], #4
 120
 121 LoopFillZeroFASTRAM:
 122   ldr  r3, = __fastram_bss_end__
 123   cmp  r2, r3
 124   bcc  FillZeroFASTRAM
 125
 126 /* Mark the heap and stack */
 127     ldr r2, =_heap_stack_begin
 128     b   LoopMarkHeapStack
 129
 130 MarkHeapStack:
 131         movs    r3, 0xa5a5a5a5
 132         str     r3, [r2], #4
 133
 134 LoopMarkHeapStack:
 135         ldr     r3, = _heap_stack_end
 136         cmp     r2, r3
 137         bcc     MarkHeapStack
 138
 139 /*FPU settings*/
 140   ldr  r0, =0xE000ED88           /* Enable CP10,CP11 */
 141   ldr  r1,[r0]
 142   orr  r1,r1,#(0xF << 20)
 143   str  r1,[r0]
 144
 145 /* Call the clock system initialization function.*/
 146   bl  SystemInit
 147 /* Call the application's entry point.*/
 148   bl  main
 149   bx  lr
 150
 151 LoopForever:
 152   b LoopForever
 153
 154 .size  Reset_Handler, .-Reset_Handler
 155
 156 /**
 157  * @brief  This is the code that gets called when the processor receives an
 158  *         unexpected interrupt.  This simply enters an infinite loop, preserving
 159  *         the system state for examination by a debugger.
 160  * @param  None
 161  * @retval None
 162 */
 163     .section  .text.Default_Handler,"ax",%progbits
 164 Default_Handler:
 165 Infinite_Loop:
 166   b  Infinite_Loop
 167   .size  Default_Handler, .-Default_Handler
 168
 169 /******************************************************************************
 170 *
 171 * The minimal vector table for a Cortex M7. Note that the proper constructs
 172 * must be placed on this to ensure that it ends up at physical address
 173 * 0x0000.0000.
 174 *
 175 *******************************************************************************/
 176    .section  .isr_vector,"a",%progbits
 177   .type  g_pfnVectors, %object
 178   .size  g_pfnVectors, .-g_pfnVectors
 179
 180
 181 g_pfnVectors:
 182   .word  _estack
 183   .word  Reset_Handler
 184
 185   .word  NMI_Handler
 186   .word  HardFault_Handler
 187   .word  MemManage_Handler
 188   .word  BusFault_Handler
 189   .word  UsageFault_Handler
 190   .word  0
 191   .word  0
 192   .word  0
 193   .word  0
 194   .word  SVC_Handler
 195   .word  DebugMon_Handler
 196   .word  0
 197   .word  PendSV_Handler
 198   .word  SysTick_Handler
 199
 200   /* External Interrupts */
 201   .word     WWDG_IRQHandler                   /* Window WatchDog              */
 202   .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
 203   .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
 204   .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
 205   .word     FLASH_IRQHandler                  /* FLASH                        */
 206   .word     RCC_IRQHandler                    /* RCC                          */
 207   .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
 208   .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
 209   .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
 210   .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
 211   .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
 212   .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
 213   .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
 214   .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
 215   .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
 216   .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
 217   .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
 218   .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
 219   .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
 220   .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
 221   .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
 222   .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
 223   .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
 224   .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
 225   .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
 226   .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
 227   .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
 228   .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
 229   .word     TIM2_IRQHandler                   /* TIM2                         */
 230   .word     TIM3_IRQHandler                   /* TIM3                         */
 231   .word     TIM4_IRQHandler                   /* TIM4                         */
 232   .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
 233   .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
 234   .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
 235   .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
 236   .word     SPI1_IRQHandler                   /* SPI1                         */
 237   .word     SPI2_IRQHandler                   /* SPI2                         */
 238   .word     USART1_IRQHandler                 /* USART1                       */
 239   .word     USART2_IRQHandler                 /* USART2                       */
 240   .word     USART3_IRQHandler                 /* USART3                       */
 241   .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
 242   .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
 243   .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
 244   .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
 245   .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
 246   .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
 247   .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
 248   .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
 249   .word     FMC_IRQHandler                    /* FMC                          */
 250   .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
 251   .word     TIM5_IRQHandler                   /* TIM5                         */
 252   .word     SPI3_IRQHandler                   /* SPI3                         */
 253   .word     UART4_IRQHandler                  /* UART4                        */
 254   .word     UART5_IRQHandler                  /* UART5                        */
 255   .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
 256   .word     TIM7_IRQHandler                   /* TIM7                         */
 257   .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
 258   .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
 259   .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
 260   .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
 261   .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
 262   .word     ETH_IRQHandler                    /* Ethernet                     */
 263   .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
 264   .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
 265   .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
 266   .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
 267   .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
 268   .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
 269   .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
 270   .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
 271   .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
 272   .word     USART6_IRQHandler                 /* USART6                       */
 273   .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
 274   .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
 275   .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
 276   .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
 277   .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
 278   .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
 279   .word     DCMI_IRQHandler                   /* DCMI                         */
 280   .word     0                                 /* Reserved                     */
 281   .word     RNG_IRQHandler                    /* RNG                          */
 282   .word     FPU_IRQHandler                    /* FPU                          */
 283   .word     UART7_IRQHandler                  /* UART7                        */
 284   .word     UART8_IRQHandler                  /* UART8                        */
 285   .word     SPI4_IRQHandler                   /* SPI4                         */
 286   .word     SPI5_IRQHandler                   /* SPI5                         */
 287   .word     SPI6_IRQHandler                   /* SPI6                         */
 288   .word     SAI1_IRQHandler                   /* SAI1                         */
 289   .word     0                                 /* Reserved                     */
 290   .word     0                                 /* Reserved                     */
 291   .word     DMA2D_IRQHandler                  /* DMA2D                        */
 292   .word     SAI2_IRQHandler                   /* SAI2                         */
 293   .word     QUADSPI_IRQHandler                /* QUADSPI                      */
 294   .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
 295   .word     CEC_IRQHandler                    /* HDMI_CEC                     */
 296   .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
 297   .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
 298   .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
 299   .word     0                                 /* Reserved                     */
 300   .word     DFSDM1_FLT0_IRQHandler            /* DFSDM1 Filter 0 global Interrupt */
 301   .word     DFSDM1_FLT1_IRQHandler            /* DFSDM1 Filter 1 global Interrupt */
 302   .word     DFSDM1_FLT2_IRQHandler            /* DFSDM1 Filter 2 global Interrupt */
 303   .word     DFSDM1_FLT3_IRQHandler            /* DFSDM1 Filter 3 global Interrupt */
 304   .word     SDMMC2_IRQHandler                 /* SDMMC2                       */
 305   .word     CAN3_TX_IRQHandler                /* CAN3 TX                      */
 306   .word     CAN3_RX0_IRQHandler               /* CAN3 RX0                     */
 307   .word     CAN3_RX1_IRQHandler               /* CAN3 RX1                     */
 308   .word     CAN3_SCE_IRQHandler               /* CAN3 SCE                     */
 309   .word     0                                 /* Reserved                     */
 310   .word     MDIOS_IRQHandler                  /* MDIOS                        */
 311
 312 /*******************************************************************************
 313 *
 314 * Provide weak aliases for each Exception handler to the Default_Handler.
 315 * As they are weak aliases, any function with the same name will override
 316 * this definition.
 317 *
 318 *******************************************************************************/
 319    .weak      NMI_Handler
 320    .thumb_set NMI_Handler,Default_Handler
 321
 322    .weak      HardFault_Handler
 323    .thumb_set HardFault_Handler,Default_Handler
 324
 325    .weak      MemManage_Handler
 326    .thumb_set MemManage_Handler,Default_Handler
 327
 328    .weak      BusFault_Handler
 329    .thumb_set BusFault_Handler,Default_Handler
 330
 331    .weak      UsageFault_Handler
 332    .thumb_set UsageFault_Handler,Default_Handler
 333
 334    .weak      SVC_Handler
 335    .thumb_set SVC_Handler,Default_Handler
 336
 337    .weak      DebugMon_Handler
 338    .thumb_set DebugMon_Handler,Default_Handler
 339
 340    .weak      PendSV_Handler
 341    .thumb_set PendSV_Handler,Default_Handler
 342
 343    .weak      SysTick_Handler
 344    .thumb_set SysTick_Handler,Default_Handler
 345
 346    .weak      WWDG_IRQHandler
 347    .thumb_set WWDG_IRQHandler,Default_Handler
 348
 349    .weak      PVD_IRQHandler
 350    .thumb_set PVD_IRQHandler,Default_Handler
 351
 352    .weak      TAMP_STAMP_IRQHandler
 353    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
 354
 355    .weak      RTC_WKUP_IRQHandler
 356    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
 357
 358    .weak      FLASH_IRQHandler
 359    .thumb_set FLASH_IRQHandler,Default_Handler
 360
 361    .weak      RCC_IRQHandler
 362    .thumb_set RCC_IRQHandler,Default_Handler
 363
 364    .weak      EXTI0_IRQHandler
 365    .thumb_set EXTI0_IRQHandler,Default_Handler
 366
 367    .weak      EXTI1_IRQHandler
 368    .thumb_set EXTI1_IRQHandler,Default_Handler
 369
 370    .weak      EXTI2_IRQHandler
 371    .thumb_set EXTI2_IRQHandler,Default_Handler
 372
 373    .weak      EXTI3_IRQHandler
 374    .thumb_set EXTI3_IRQHandler,Default_Handler
 375
 376    .weak      EXTI4_IRQHandler
 377    .thumb_set EXTI4_IRQHandler,Default_Handler
 378
 379    .weak      DMA1_Stream0_IRQHandler
 380    .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
 381
 382    .weak      DMA1_Stream1_IRQHandler
 383    .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
 384
 385    .weak      DMA1_Stream2_IRQHandler
 386    .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
 387
 388    .weak      DMA1_Stream3_IRQHandler
 389    .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
 390
 391    .weak      DMA1_Stream4_IRQHandler
 392    .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
 393
 394    .weak      DMA1_Stream5_IRQHandler
 395    .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
 396
 397    .weak      DMA1_Stream6_IRQHandler
 398    .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
 399
 400    .weak      ADC_IRQHandler
 401    .thumb_set ADC_IRQHandler,Default_Handler
 402
 403    .weak      CAN1_TX_IRQHandler
 404    .thumb_set CAN1_TX_IRQHandler,Default_Handler
 405
 406    .weak      CAN1_RX0_IRQHandler
 407    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
 408
 409    .weak      CAN1_RX1_IRQHandler
 410    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
 411
 412    .weak      CAN1_SCE_IRQHandler
 413    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
 414
 415    .weak      EXTI9_5_IRQHandler
 416    .thumb_set EXTI9_5_IRQHandler,Default_Handler
 417
 418    .weak      TIM1_BRK_TIM9_IRQHandler
 419    .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
 420
 421    .weak      TIM1_UP_TIM10_IRQHandler
 422    .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
 423
 424    .weak      TIM1_TRG_COM_TIM11_IRQHandler
 425    .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
 426
 427    .weak      TIM1_CC_IRQHandler
 428    .thumb_set TIM1_CC_IRQHandler,Default_Handler
 429
 430    .weak      TIM2_IRQHandler
 431    .thumb_set TIM2_IRQHandler,Default_Handler
 432
 433    .weak      TIM3_IRQHandler
 434    .thumb_set TIM3_IRQHandler,Default_Handler
 435
 436    .weak      TIM4_IRQHandler
 437    .thumb_set TIM4_IRQHandler,Default_Handler
 438
 439    .weak      I2C1_EV_IRQHandler
 440    .thumb_set I2C1_EV_IRQHandler,Default_Handler
 441
 442    .weak      I2C1_ER_IRQHandler
 443    .thumb_set I2C1_ER_IRQHandler,Default_Handler
 444
 445    .weak      I2C2_EV_IRQHandler
 446    .thumb_set I2C2_EV_IRQHandler,Default_Handler
 447
 448    .weak      I2C2_ER_IRQHandler
 449    .thumb_set I2C2_ER_IRQHandler,Default_Handler
 450
 451    .weak      SPI1_IRQHandler
 452    .thumb_set SPI1_IRQHandler,Default_Handler
 453
 454    .weak      SPI2_IRQHandler
 455    .thumb_set SPI2_IRQHandler,Default_Handler
 456
 457    .weak      USART1_IRQHandler
 458    .thumb_set USART1_IRQHandler,Default_Handler
 459
 460    .weak      USART2_IRQHandler
 461    .thumb_set USART2_IRQHandler,Default_Handler
 462
 463    .weak      USART3_IRQHandler
 464    .thumb_set USART3_IRQHandler,Default_Handler
 465
 466    .weak      EXTI15_10_IRQHandler
 467    .thumb_set EXTI15_10_IRQHandler,Default_Handler
 468
 469    .weak      RTC_Alarm_IRQHandler
 470    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
 471
 472    .weak      OTG_FS_WKUP_IRQHandler
 473    .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
 474
 475    .weak      TIM8_BRK_TIM12_IRQHandler
 476    .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
 477
 478    .weak      TIM8_UP_TIM13_IRQHandler
 479    .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
 480
 481    .weak      TIM8_TRG_COM_TIM14_IRQHandler
 482    .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
 483
 484    .weak      TIM8_CC_IRQHandler
 485    .thumb_set TIM8_CC_IRQHandler,Default_Handler
 486
 487    .weak      DMA1_Stream7_IRQHandler
 488    .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
 489
 490    .weak      FMC_IRQHandler
 491    .thumb_set FMC_IRQHandler,Default_Handler
 492
 493    .weak      SDMMC1_IRQHandler
 494    .thumb_set SDMMC1_IRQHandler,Default_Handler
 495
 496    .weak      TIM5_IRQHandler
 497    .thumb_set TIM5_IRQHandler,Default_Handler
 498
 499    .weak      SPI3_IRQHandler
 500    .thumb_set SPI3_IRQHandler,Default_Handler
 501
 502    .weak      UART4_IRQHandler
 503    .thumb_set UART4_IRQHandler,Default_Handler
 504
 505    .weak      UART5_IRQHandler
 506    .thumb_set UART5_IRQHandler,Default_Handler
 507
 508    .weak      TIM6_DAC_IRQHandler
 509    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
 510
 511    .weak      TIM7_IRQHandler
 512    .thumb_set TIM7_IRQHandler,Default_Handler
 513
 514    .weak      DMA2_Stream0_IRQHandler
 515    .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
 516
 517    .weak      DMA2_Stream1_IRQHandler
 518    .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
 519
 520    .weak      DMA2_Stream2_IRQHandler
 521    .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
 522
 523    .weak      DMA2_Stream3_IRQHandler
 524    .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
 525
 526    .weak      DMA2_Stream4_IRQHandler
 527    .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
 528
 529    .weak      DMA2_Stream4_IRQHandler
 530    .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
 531
 532    .weak      ETH_IRQHandler
 533    .thumb_set ETH_IRQHandler,Default_Handler
 534
 535    .weak      ETH_WKUP_IRQHandler
 536    .thumb_set ETH_WKUP_IRQHandler,Default_Handler
 537
 538    .weak      CAN2_TX_IRQHandler
 539    .thumb_set CAN2_TX_IRQHandler,Default_Handler
 540
 541    .weak      CAN2_RX0_IRQHandler
 542    .thumb_set CAN2_RX0_IRQHandler,Default_Handler
 543
 544    .weak      CAN2_RX1_IRQHandler
 545    .thumb_set CAN2_RX1_IRQHandler,Default_Handler
 546
 547    .weak      CAN2_SCE_IRQHandler
 548    .thumb_set CAN2_SCE_IRQHandler,Default_Handler
 549
 550    .weak      OTG_FS_IRQHandler
 551    .thumb_set OTG_FS_IRQHandler,Default_Handler
 552
 553    .weak      DMA2_Stream5_IRQHandler
 554    .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
 555
 556    .weak      DMA2_Stream6_IRQHandler
 557    .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
 558
 559    .weak      DMA2_Stream7_IRQHandler
 560    .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
 561
 562    .weak      USART6_IRQHandler
 563    .thumb_set USART6_IRQHandler,Default_Handler
 564
 565    .weak      I2C3_EV_IRQHandler
 566    .thumb_set I2C3_EV_IRQHandler,Default_Handler
 567
 568    .weak      I2C3_ER_IRQHandler
 569    .thumb_set I2C3_ER_IRQHandler,Default_Handler
 570
 571    .weak      OTG_HS_EP1_OUT_IRQHandler
 572    .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
 573
 574    .weak      OTG_HS_EP1_IN_IRQHandler
 575    .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
 576
 577    .weak      OTG_HS_WKUP_IRQHandler
 578    .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
 579
 580    .weak      OTG_HS_IRQHandler
 581    .thumb_set OTG_HS_IRQHandler,Default_Handler
 582
 583    .weak      DCMI_IRQHandler
 584    .thumb_set DCMI_IRQHandler,Default_Handler
 585
 586    .weak      RNG_IRQHandler
 587    .thumb_set RNG_IRQHandler,Default_Handler
 588
 589    .weak      FPU_IRQHandler
 590    .thumb_set FPU_IRQHandler,Default_Handler
 591
 592    .weak      UART7_IRQHandler
 593    .thumb_set UART7_IRQHandler,Default_Handler
 594
 595    .weak      UART8_IRQHandler
 596    .thumb_set UART8_IRQHandler,Default_Handler
 597
 598    .weak      SPI4_IRQHandler
 599    .thumb_set SPI4_IRQHandler,Default_Handler
 600
 601    .weak      SPI5_IRQHandler
 602    .thumb_set SPI5_IRQHandler,Default_Handler
 603
 604    .weak      SPI6_IRQHandler
 605    .thumb_set SPI6_IRQHandler,Default_Handler
 606
 607    .weak      SAI1_IRQHandler
 608    .thumb_set SAI1_IRQHandler,Default_Handler
 609
 610    .weak      DMA2D_IRQHandler
 611    .thumb_set DMA2D_IRQHandler,Default_Handler
 612
 613    .weak      SAI2_IRQHandler
 614    .thumb_set SAI2_IRQHandler,Default_Handler
 615
 616    .weak      QUADSPI_IRQHandler
 617    .thumb_set QUADSPI_IRQHandler,Default_Handler
 618
 619    .weak      LPTIM1_IRQHandler
 620    .thumb_set LPTIM1_IRQHandler,Default_Handler
 621
 622    .weak      CEC_IRQHandler
 623    .thumb_set CEC_IRQHandler,Default_Handler
 624
 625    .weak      I2C4_EV_IRQHandler
 626    .thumb_set I2C4_EV_IRQHandler,Default_Handler
 627
 628    .weak      I2C4_ER_IRQHandler
 629    .thumb_set I2C4_ER_IRQHandler,Default_Handler
 630
 631    .weak      SPDIF_RX_IRQHandler
 632    .thumb_set SPDIF_RX_IRQHandler,Default_Handler
 633
 634    .weak      DFSDM1_FLT0_IRQHandler
 635    .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
 636
 637    .weak      DFSDM1_FLT1_IRQHandler
 638    .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
 639
 640    .weak      DFSDM1_FLT2_IRQHandler
 641    .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
 642
 643    .weak      DFSDM1_FLT3_IRQHandler
 644    .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
 645
 646    .weak      SDMMC2_IRQHandler
 647    .thumb_set SDMMC2_IRQHandler,Default_Handler
 648
 649    .weak      CAN3_TX_IRQHandler
 650    .thumb_set CAN3_TX_IRQHandler,Default_Handler
 651
 652    .weak      CAN3_RX0_IRQHandler
 653    .thumb_set CAN3_RX0_IRQHandler,Default_Handler
 654
 655    .weak      CAN3_RX1_IRQHandler
 656    .thumb_set CAN3_RX1_IRQHandler,Default_Handler
 657
 658    .weak      CAN3_SCE_IRQHandler
 659    .thumb_set CAN3_SCE_IRQHandler,Default_Handler
 660
 661    .weak      MDIOS_IRQHandler
 662    .thumb_set MDIOS_IRQHandler,Default_Handler
 663
 664 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/