src/main/target/system_stm32f4xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f4xx.c
   4   * @author  MCD Application Team
   5   * @version V1.6.1
   6   * @date    21-October-2015
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *          This file contains the system clock configuration for STM32F4xx devices.
   9   *
  10   * 1.  This file provides two functions and one global variable to be called from
  11   *     user application:
  12   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  13   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  14   *                      depending on the configuration made in the clock xls tool.
  15   *                      This function is called at startup just after reset and
  16   *                      before branch to main program. This call is made inside
  17   *                      the "startup_stm32f4xx.s" file.
  18   *
  19   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  20   *                                  by the user application to setup the SysTick
  21   *                                  timer or configure other parameters.
  22   *
  23   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  24   *                                 be called whenever the core clock is changed
  25   *                                 during program execution.
  26   *
  27   * 2. After each device reset the HSI (16 MHz) is used as system clock source.
  28   *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
  29   *    configure the system clock before to branch to main program.
  30   *
  31   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  32   *    function will do nothing and HSI still used as system clock source. User can
  33   *    add some code to deal with this issue inside the SetSysClock() function.
  34   *
  35   * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
  36   *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
  37   *    through PLL, and you are using different crystal you have to adapt the HSE
  38   *    value to your own configuration.
  39   *
  40   * 5. This file configures the system clock as follows:
  41   *=============================================================================
  42   *=============================================================================
  43   *                    Supported STM32F40xxx/41xxx devices
  44   *-----------------------------------------------------------------------------
  45   *        System Clock source                    | PLL (HSE)
  46   *-----------------------------------------------------------------------------
  47   *        SYSCLK(Hz)                             | 168000000
  48   *-----------------------------------------------------------------------------
  49   *        HCLK(Hz)                               | 168000000
  50   *-----------------------------------------------------------------------------
  51   *        AHB Prescaler                          | 1
  52   *-----------------------------------------------------------------------------
  53   *        APB1 Prescaler                         | 4
  54   *-----------------------------------------------------------------------------
  55   *        APB2 Prescaler                         | 2
  56   *-----------------------------------------------------------------------------
  57   *        HSE Frequency(Hz)                      | 8000000
  58   *-----------------------------------------------------------------------------
  59   *        PLL_M                                  | 10
  60   *-----------------------------------------------------------------------------
  61   *        PLL_N                                  | 420
  62   *-----------------------------------------------------------------------------
  63   *        PLL_P                                  | 2
  64   *-----------------------------------------------------------------------------
  65   *        PLL_Q                                  | 7
  66   *-----------------------------------------------------------------------------
  67   *        PLLI2S_N                               | NA
  68   *-----------------------------------------------------------------------------
  69   *        PLLI2S_R                               | NA
  70   *-----------------------------------------------------------------------------
  71   *        I2S input clock                        | NA
  72   *-----------------------------------------------------------------------------
  73   *        VDD(V)                                 | 3.3
  74   *-----------------------------------------------------------------------------
  75   *        Main regulator output voltage          | Scale1 mode
  76   *-----------------------------------------------------------------------------
  77   *        Flash Latency(WS)                      | 5
  78   *-----------------------------------------------------------------------------
  79   *        Prefetch Buffer                        | ON
  80   *-----------------------------------------------------------------------------
  81   *        Instruction cache                      | ON
  82   *-----------------------------------------------------------------------------
  83   *        Data cache                             | ON
  84   *-----------------------------------------------------------------------------
  85   *        Require 48MHz for USB OTG FS,          | Disabled
  86   *        SDIO and RNG clock                     |
  87   *-----------------------------------------------------------------------------
  88   *=============================================================================
  89   *=============================================================================
  90   *                    Supported STM32F42xxx/43xxx devices
  91   *-----------------------------------------------------------------------------
  92   *        System Clock source                    | PLL (HSE)
  93   *-----------------------------------------------------------------------------
  94   *        SYSCLK(Hz)                             | 180000000
  95   *-----------------------------------------------------------------------------
  96   *        HCLK(Hz)                               | 180000000
  97   *-----------------------------------------------------------------------------
  98   *        AHB Prescaler                          | 1
  99   *-----------------------------------------------------------------------------
 100   *        APB1 Prescaler                         | 4
 101   *-----------------------------------------------------------------------------
 102   *        APB2 Prescaler                         | 2
 103   *-----------------------------------------------------------------------------
 104   *        HSE Frequency(Hz)                      | 25000000
 105   *-----------------------------------------------------------------------------
 106   *        PLL_M                                  | 25
 107   *-----------------------------------------------------------------------------
 108   *        PLL_N                                  | 360
 109   *-----------------------------------------------------------------------------
 110   *        PLL_P                                  | 2
 111   *-----------------------------------------------------------------------------
 112   *        PLL_Q                                  | 7
 113   *-----------------------------------------------------------------------------
 114   *        PLLI2S_N                               | NA
 115   *-----------------------------------------------------------------------------
 116   *        PLLI2S_R                               | NA
 117   *-----------------------------------------------------------------------------
 118   *        I2S input clock                        | NA
 119   *-----------------------------------------------------------------------------
 120   *        VDD(V)                                 | 3.3
 121   *-----------------------------------------------------------------------------
 122   *        Main regulator output voltage          | Scale1 mode
 123   *-----------------------------------------------------------------------------
 124   *        Flash Latency(WS)                      | 5
 125   *-----------------------------------------------------------------------------
 126   *        Prefetch Buffer                        | ON
 127   *-----------------------------------------------------------------------------
 128   *        Instruction cache                      | ON
 129   *-----------------------------------------------------------------------------
 130   *        Data cache                             | ON
 131   *-----------------------------------------------------------------------------
 132   *        Require 48MHz for USB OTG FS,          | Disabled
 133   *        SDIO and RNG clock                     |
 134   *-----------------------------------------------------------------------------
 135   *=============================================================================
 136   *=============================================================================
 137   *                         Supported STM32F401xx devices
 138   *-----------------------------------------------------------------------------
 139   *        System Clock source                    | PLL (HSE)
 140   *-----------------------------------------------------------------------------
 141   *        SYSCLK(Hz)                             | 84000000
 142   *-----------------------------------------------------------------------------
 143   *        HCLK(Hz)                               | 84000000
 144   *-----------------------------------------------------------------------------
 145   *        AHB Prescaler                          | 1
 146   *-----------------------------------------------------------------------------
 147   *        APB1 Prescaler                         | 2
 148   *-----------------------------------------------------------------------------
 149   *        APB2 Prescaler                         | 1
 150   *-----------------------------------------------------------------------------
 151   *        HSE Frequency(Hz)                      | 25000000
 152   *-----------------------------------------------------------------------------
 153   *        PLL_M                                  | 25
 154   *-----------------------------------------------------------------------------
 155   *        PLL_N                                  | 336
 156   *-----------------------------------------------------------------------------
 157   *        PLL_P                                  | 4
 158   *-----------------------------------------------------------------------------
 159   *        PLL_Q                                  | 7
 160   *-----------------------------------------------------------------------------
 161   *        PLLI2S_N                               | NA
 162   *-----------------------------------------------------------------------------
 163   *        PLLI2S_R                               | NA
 164   *-----------------------------------------------------------------------------
 165   *        I2S input clock                        | NA
 166   *-----------------------------------------------------------------------------
 167   *        VDD(V)                                 | 3.3
 168   *-----------------------------------------------------------------------------
 169   *        Main regulator output voltage          | Scale1 mode
 170   *-----------------------------------------------------------------------------
 171   *        Flash Latency(WS)                      | 2
 172   *-----------------------------------------------------------------------------
 173   *        Prefetch Buffer                        | ON
 174   *-----------------------------------------------------------------------------
 175   *        Instruction cache                      | ON
 176   *-----------------------------------------------------------------------------
 177   *        Data cache                             | ON
 178   *-----------------------------------------------------------------------------
 179   *        Require 48MHz for USB OTG FS,          | Disabled
 180   *        SDIO and RNG clock                     |
 181   *-----------------------------------------------------------------------------
 182   *=============================================================================
 183   *=============================================================================
 184   *                Supported STM32F411xx/STM32F410xx devices
 185   *-----------------------------------------------------------------------------
 186   *        System Clock source                    | PLL (HSI)
 187   *-----------------------------------------------------------------------------
 188   *        SYSCLK(Hz)                             | 100000000
 189   *-----------------------------------------------------------------------------
 190   *        HCLK(Hz)                               | 100000000
 191   *-----------------------------------------------------------------------------
 192   *        AHB Prescaler                          | 1
 193   *-----------------------------------------------------------------------------
 194   *        APB1 Prescaler                         | 2
 195   *-----------------------------------------------------------------------------
 196   *        APB2 Prescaler                         | 1
 197   *-----------------------------------------------------------------------------
 198   *        HSI Frequency(Hz)                      | 16000000
 199   *-----------------------------------------------------------------------------
 200   *        PLL_M                                  | 16
 201   *-----------------------------------------------------------------------------
 202   *        PLL_N                                  | 400
 203   *-----------------------------------------------------------------------------
 204   *        PLL_P                                  | 4
 205   *-----------------------------------------------------------------------------
 206   *        PLL_Q                                  | 7
 207   *-----------------------------------------------------------------------------
 208   *        PLLI2S_N                               | NA
 209   *-----------------------------------------------------------------------------
 210   *        PLLI2S_R                               | NA
 211   *-----------------------------------------------------------------------------
 212   *        I2S input clock                        | NA
 213   *-----------------------------------------------------------------------------
 214   *        VDD(V)                                 | 3.3
 215   *-----------------------------------------------------------------------------
 216   *        Main regulator output voltage          | Scale1 mode
 217   *-----------------------------------------------------------------------------
 218   *        Flash Latency(WS)                      | 3
 219   *-----------------------------------------------------------------------------
 220   *        Prefetch Buffer                        | ON
 221   *-----------------------------------------------------------------------------
 222   *        Instruction cache                      | ON
 223   *-----------------------------------------------------------------------------
 224   *        Data cache                             | ON
 225   *-----------------------------------------------------------------------------
 226   *        Require 48MHz for USB OTG FS,          | Disabled
 227   *        SDIO and RNG clock                     |
 228   *-----------------------------------------------------------------------------
 229   *=============================================================================
 230   *=============================================================================
 231   *                         Supported STM32F446xx devices
 232   *-----------------------------------------------------------------------------
 233   *        System Clock source                    | PLL (HSE)
 234   *-----------------------------------------------------------------------------
 235   *        SYSCLK(Hz)                             | 180000000
 236   *-----------------------------------------------------------------------------
 237   *        HCLK(Hz)                               | 180000000
 238   *-----------------------------------------------------------------------------
 239   *        AHB Prescaler                          | 1
 240   *-----------------------------------------------------------------------------
 241   *        APB1 Prescaler                         | 4
 242   *-----------------------------------------------------------------------------
 243   *        APB2 Prescaler                         | 2
 244   *-----------------------------------------------------------------------------
 245   *        HSE Frequency(Hz)                      | 8000000
 246   *-----------------------------------------------------------------------------
 247   *        PLL_M                                  | 8
 248   *-----------------------------------------------------------------------------
 249   *        PLL_N                                  | 360
 250   *-----------------------------------------------------------------------------
 251   *        PLL_P                                  | 2
 252   *-----------------------------------------------------------------------------
 253   *        PLL_Q                                  | 7
 254   *-----------------------------------------------------------------------------
 255   *        PLL_R                                  | NA
 256   *-----------------------------------------------------------------------------
 257   *        PLLI2S_M                               | NA
 258   *-----------------------------------------------------------------------------
 259   *        PLLI2S_N                               | NA
 260   *-----------------------------------------------------------------------------
 261   *        PLLI2S_P                               | NA
 262   *-----------------------------------------------------------------------------
 263   *        PLLI2S_Q                               | NA
 264   *-----------------------------------------------------------------------------
 265   *        PLLI2S_R                               | NA
 266   *-----------------------------------------------------------------------------
 267   *        I2S input clock                        | NA
 268   *-----------------------------------------------------------------------------
 269   *        VDD(V)                                 | 3.3
 270   *-----------------------------------------------------------------------------
 271   *        Main regulator output voltage          | Scale1 mode
 272   *-----------------------------------------------------------------------------
 273   *        Flash Latency(WS)                      | 5
 274   *-----------------------------------------------------------------------------
 275   *        Prefetch Buffer                        | ON
 276   *-----------------------------------------------------------------------------
 277   *        Instruction cache                      | ON
 278   *-----------------------------------------------------------------------------
 279   *        Data cache                             | ON
 280   *-----------------------------------------------------------------------------
 281   *        Require 48MHz for USB OTG FS,          | Disabled
 282   *        SDIO and RNG clock                     |
 283   *-----------------------------------------------------------------------------
 284   *=============================================================================
 285   ******************************************************************************
 286   * @attention
 287   *
 288   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
 289   *
 290   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 291   * You may not use this file except in compliance with the License.
 292   * You may obtain a copy of the License at:
 293   *
 294   *        http://www.st.com/software_license_agreement_liberty_v2
 295   *
 296   * Unless required by applicable law or agreed to in writing, software
 297   * distributed under the License is distributed on an "AS IS" BASIS,
 298   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 299   * See the License for the specific language governing permissions and
 300   * limitations under the License.
 301   *
 302   ******************************************************************************
 303   */
 304
 305 /** @addtogroup CMSIS
 306   * @{
 307   */
 308
 309 /** @addtogroup stm32f4xx_system
 310   * @{
 311   */
 312
 313 /** @addtogroup STM32F4xx_System_Private_Includes
 314   * @{
 315   */
 316
 317 #include "stm32f4xx.h"
 318 #include "system.h"
 319 #include "system_stm32f4xx.h"
 320 #include "drivers/system.h"
 321
 322 uint32_t hse_value = HSE_VALUE;
 323
 324 /**
 325   * @}
 326   */
 327
 328 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
 329   * @{
 330   */
 331
 332 /**
 333   * @}
 334   */
 335
 336 /** @addtogroup STM32F4xx_System_Private_Defines
 337   * @{
 338   */
 339
 340 /************************* Miscellaneous Configuration ************************/
 341 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
 342      on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory  */
 343 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
 344 /* #define DATA_IN_ExtSRAM */
 345 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
 346
 347 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 348 /* #define DATA_IN_ExtSDRAM */
 349 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 350
 351 #if defined(STM32F410xx) || defined(STM32F411xE)
 352 /*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass
 353      through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
 354      and is fixed at 8 MHz.
 355      Hardware configuration needed for Nucleo Board:
 356      - SB54, SB55 OFF
 357      - R35 removed
 358      - SB16, SB50 ON */
 359 /* #define USE_HSE_BYPASS */
 360
 361 #if defined(USE_HSE_BYPASS)
 362 #define HSE_BYPASS_INPUT_FREQUENCY   8000000
 363 #endif /* USE_HSE_BYPASS */
 364 #endif /* STM32F410xx || STM32F411xE */
 365
 366 /*!< Uncomment the following line if you need to relocate your vector Table in
 367      Internal SRAM. */
 368 /* #define VECT_TAB_SRAM */
 369 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
 370                                    This value must be a multiple of 0x200. */
 371 /******************************************************************************/
 372
 373 /************************* PLL Parameters *************************************/
 374 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx) || defined (STM32F446xx) || defined (STM32F410xx) || defined (STM32F411xE)
 375     #if HSE_VALUE == 25000000
 376         #define PLL_M   25
 377     #elif HSE_VALUE == 24000000
 378         #define PLL_M   24
 379     #elif HSE_VALUE == 16000000
 380         #define PLL_M   16
 381     #elif HSE_VALUE == 8000000
 382         #define PLL_M   8
 383     #else
 384         #error Invalid HSE_VALUE
 385     #endif
 386 #else
 387     #error Undefined CPU
 388 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
 389
 390 #if defined(STM32F446xx)
 391 /* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock =  PLL_VCO / PLLR */
 392 #define PLL_R      7
 393 #endif /* STM32F446xx */
 394
 395 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 396 #define PLL_N      336
 397 /* SYSCLK = PLL_VCO / PLL_P */
 398 #define PLL_P      2
 399 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 400 #define PLL_Q      7
 401 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 402
 403 #if defined (STM32F40_41xxx)
 404 #define PLL_N      336
 405 /* SYSCLK = PLL_VCO / PLL_P */
 406 #define PLL_P      2
 407 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 408 #define PLL_Q      7
 409 #endif /* STM32F40_41xxx */
 410
 411 #if defined(STM32F401xx)
 412 #define PLL_N      336
 413 /* SYSCLK = PLL_VCO / PLL_P */
 414 #define PLL_P      4
 415 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 416 #define PLL_Q      7
 417 #endif /* STM32F401xx */
 418
 419 #if defined(STM32F410xx) || defined(STM32F411xE)
 420 #define PLL_N      192
 421 /* SYSCLK = PLL_VCO / PLL_P */
 422 #define PLL_P      2
 423 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 424 #define PLL_Q      4
 425 #endif /* STM32F410xx || STM32F411xE */
 426
 427 /******************************************************************************/
 428
 429 /**
 430   * @}
 431   */
 432
 433 /** @addtogroup STM32F4xx_System_Private_Macros
 434   * @{
 435   */
 436
 437 /**
 438   * @}
 439   */
 440
 441 /** @addtogroup STM32F4xx_System_Private_Variables
 442   * @{
 443   */
 444
 445 /* core clock is simply a mhz of PLL_N / PLL_P */
 446 uint32_t SystemCoreClock = 1000000 * PLL_N / PLL_P;
 447
 448 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 449
 450 /**
 451   * @}
 452   */
 453
 454 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
 455   * @{
 456   */
 457
 458 void SetSysClock(void);
 459
 460 #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
 461 static void SystemInit_ExtMemCtl(void);
 462 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 463
 464 /**
 465   * @}
 466   */
 467
 468 /** @addtogroup STM32F4xx_System_Private_Functions
 469   * @{
 470   */
 471
 472 /**
 473   * @brief  Setup the microcontroller system
 474   *         Initialize the Embedded Flash Interface, the PLL and update the
 475   *         SystemFrequency variable.
 476   * @param  None
 477   * @retval None
 478   */
 479 void SystemInit(void)
 480 {
 481   initialiseMemorySections();
 482
 483   /* FPU settings ------------------------------------------------------------*/
 484   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 485     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 486   #endif
 487   /* Reset the RCC clock configuration to the default reset state ------------*/
 488   /* Set HSION bit */
 489   RCC->CR |= (uint32_t)0x00000001;
 490
 491   /* Reset CFGR register */
 492   RCC->CFGR = 0x00000000;
 493
 494   /* Reset HSEON, CSSON and PLLON bits */
 495   RCC->CR &= (uint32_t)0xFEF6FFFF;
 496
 497   /* Reset PLLCFGR register */
 498   RCC->PLLCFGR = 0x24003010;
 499
 500   /* Reset HSEBYP bit */
 501   RCC->CR &= (uint32_t)0xFFFBFFFF;
 502
 503   /* Disable all interrupts */
 504   RCC->CIR = 0x00000000;
 505
 506 #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
 507   SystemInit_ExtMemCtl();
 508 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 509
 510   /* Configure the System clock source, PLL Multiplier and Divider factors,
 511      AHB/APBx prescalers and Flash settings ----------------------------------*/
 512   // SetSysClock();
 513
 514   /* Configure the Vector Table location add offset address ------------------*/
 515 #ifdef VECT_TAB_SRAM
 516   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 517 #else
 518   SCB->VTOR = (uint32_t) &isr_vector_table_base; /* Vector Table Relocation in Internal FLASH */
 519 #endif
 520 }
 521
 522 /**
 523    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 524   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 525   *         be used by the user application to setup the SysTick timer or configure
 526   *         other parameters.
 527   *
 528   * @note   Each time the core clock (HCLK) changes, this function must be called
 529   *         to update SystemCoreClock variable value. Otherwise, any configuration
 530   *         based on this variable will be incorrect.
 531   *
 532   * @note   - The system frequency computed by this function is not the real
 533   *           frequency in the chip. It is calculated based on the predefined
 534   *           constant and the selected clock source:
 535   *
 536   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 537   *
 538   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 539   *
 540   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 541   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 542   *
 543   *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
 544   *             16 MHz) but the real value may vary depending on the variations
 545   *             in voltage and temperature.
 546   *
 547   *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
 548   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
 549   *              frequency of the crystal used. Otherwise, this function may
 550   *              have wrong result.
 551   *
 552   *         - The result of this function could be not correct when using fractional
 553   *           value for HSE crystal.
 554   *
 555   * @param  None
 556   * @retval None
 557   */
 558 void SystemCoreClockUpdate(void)
 559 {
 560   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 561 #if defined(STM32F446xx)
 562   uint32_t pllr = 2;
 563 #endif /* STM32F446xx */
 564   /* Get SYSCLK source -------------------------------------------------------*/
 565   tmp = RCC->CFGR & RCC_CFGR_SWS;
 566
 567   switch (tmp)
 568   {
 569     case 0x00:  /* HSI used as system clock source */
 570       SystemCoreClock = HSI_VALUE;
 571       break;
 572     case 0x04:  /* HSE used as system clock source */
 573       SystemCoreClock = HSE_VALUE;
 574       break;
 575     case 0x08:  /* PLL P used as system clock source */
 576        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 577          SYSCLK = PLL_VCO / PLL_P
 578          */
 579       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 580       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 581
 582       if (pllsource != 0)
 583       {
 584         /* HSE used as PLL clock source */
 585         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 586       }
 587       else
 588       {
 589         /* HSI used as PLL clock source */
 590         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 591       }
 592
 593       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 594       SystemCoreClock = pllvco/pllp;
 595       break;
 596 #if defined(STM32F446xx)
 597       case 0x0C:  /* PLL R used as system clock source */
 598        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 599          SYSCLK = PLL_VCO / PLL_R
 600          */
 601       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 602       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 603       if (pllsource != 0)
 604       {
 605         /* HSE used as PLL clock source */
 606         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 607       }
 608       else
 609       {
 610         /* HSI used as PLL clock source */
 611         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 612       }
 613
 614       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
 615       SystemCoreClock = pllvco/pllr;
 616       break;
 617 #endif /* STM32F446xx */
 618     default:
 619       SystemCoreClock = HSI_VALUE;
 620       break;
 621   }
 622   /* Compute HCLK frequency --------------------------------------------------*/
 623   /* Get HCLK prescaler */
 624   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 625   /* HCLK frequency */
 626   SystemCoreClock >>= tmp;
 627 }
 628
 629 /**
 630   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 631   *         AHB/APBx prescalers and Flash settings
 632   * @Note   This function should be called only once the RCC clock configuration
 633   *         is reset to the default reset state (done in SystemInit() function).
 634   * @param  None
 635   * @retval None
 636   */
 637 void SetSysClock(void)
 638 {
 639 /******************************************************************************/
 640 /*            PLL (clocked by HSE) used as System clock source                */
 641 /******************************************************************************/
 642   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 643
 644   /* Enable HSE */
 645   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 646
 647   /* Wait till HSE is ready and if Time out is reached exit */
 648   do
 649   {
 650     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 651     StartUpCounter++;
 652   } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 653
 654   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 655   {
 656     HSEStatus = (uint32_t)0x01;
 657   }
 658   else
 659   {
 660     HSEStatus = (uint32_t)0x00;
 661   }
 662
 663   if (HSEStatus == (uint32_t)0x01)
 664   {
 665     /* Select regulator voltage output Scale 1 mode */
 666     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 667     PWR->CR |= PWR_CR_VOS;
 668
 669     /* HCLK = SYSCLK / 1*/
 670     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
 671
 672 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 673     /* PCLK2 = HCLK / 2*/
 674     RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
 675
 676     /* PCLK1 = HCLK / 4*/
 677     RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
 678 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx  || STM32F446xx || STM32F469_479xx */
 679
 680 #if defined(STM32F401xx)
 681     /* PCLK2 = HCLK / 2*/
 682     RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
 683
 684     /* PCLK1 = HCLK / 4*/
 685     RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
 686 #endif /* STM32F401xx */
 687
 688 #if defined(STM32F410xx) || defined(STM32F411xE)
 689     /* PCLK2 = HCLK / 2*/
 690     RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
 691
 692     /* PCLK1 = HCLK / 4*/
 693     RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
 694 #endif /* STM32F410xx || STM32F411xE */
 695
 696 #if defined(STM32F446xx)
 697     /* Configure the main PLL */
 698     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 699                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
 700 #else
 701     /* Configure the main PLL */
 702     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 703                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
 704 #endif /* STM32F446xx */
 705
 706     /* Enable the main PLL */
 707     RCC->CR |= RCC_CR_PLLON;
 708
 709     /* Wait till the main PLL is ready */
 710     while ((RCC->CR & RCC_CR_PLLRDY) == 0)
 711     {
 712     }
 713
 714 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 715     /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
 716     PWR->CR |= PWR_CR_ODEN;
 717     while ((PWR->CSR & PWR_CSR_ODRDY) == 0)
 718     {
 719     }
 720     PWR->CR |= PWR_CR_ODSWEN;
 721     while ((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
 722     {
 723     }
 724 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 725
 726 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 727     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 728     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 729 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx  || STM32F446xx || STM32F469_479xx */
 730
 731 #if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE)
 732     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 733     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
 734 #endif /* STM32F401xx || STM32F410xx || STM32F411xE*/
 735
 736     /* Select the main PLL as system clock source */
 737     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 738     RCC->CFGR |= RCC_CFGR_SW_PLL;
 739
 740     /* Wait till the main PLL is used as system clock source */
 741     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL)
 742     {
 743     }
 744   }
 745   else
 746   { /* If HSE fails to start-up, the application will have wrong clock
 747          configuration. User can add here some code to deal with this error */
 748     while(1) { __NOP(); }
 749   }
 750
 751   SystemCoreClockUpdate();
 752 }
 753
 754 /**
 755   * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s
 756   *          before jump to __main
 757   * @param  None
 758   * @retval None
 759   */
 760 #ifdef DATA_IN_ExtSRAM
 761 /**
 762   * @brief  Setup the external memory controller.
 763   *         Called in startup_stm32f4xx.s before jump to main.
 764   *         This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
 765   *         This SRAM will be used as program data memory (including heap and stack).
 766   * @param  None
 767   * @retval None
 768   */
 769 void SystemInit_ExtMemCtl(void)
 770 {
 771 /*-- GPIOs Configuration -----------------------------------------------------*/
 772 /*
 773  +-------------------+--------------------+------------------+--------------+
 774  +                       SRAM pins assignment                               +
 775  +-------------------+--------------------+------------------+--------------+
 776  | PD0  <-> FMC_D2  | PE0  <-> FMC_NBL0 | PF0  <-> FMC_A0 | PG0 <-> FMC_A10 |
 777  | PD1  <-> FMC_D3  | PE1  <-> FMC_NBL1 | PF1  <-> FMC_A1 | PG1 <-> FMC_A11 |
 778  | PD4  <-> FMC_NOE | PE3  <-> FMC_A19  | PF2  <-> FMC_A2 | PG2 <-> FMC_A12 |
 779  | PD5  <-> FMC_NWE | PE4  <-> FMC_A20  | PF3  <-> FMC_A3 | PG3 <-> FMC_A13 |
 780  | PD8  <-> FMC_D13 | PE7  <-> FMC_D4   | PF4  <-> FMC_A4 | PG4 <-> FMC_A14 |
 781  | PD9  <-> FMC_D14 | PE8  <-> FMC_D5   | PF5  <-> FMC_A5 | PG5 <-> FMC_A15 |
 782  | PD10 <-> FMC_D15 | PE9  <-> FMC_D6   | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
 783  | PD11 <-> FMC_A16 | PE10 <-> FMC_D7   | PF13 <-> FMC_A7 |-----------------+
 784  | PD12 <-> FMC_A17 | PE11 <-> FMC_D8   | PF14 <-> FMC_A8 |
 785  | PD13 <-> FMC_A18 | PE12 <-> FMC_D9   | PF15 <-> FMC_A9 |
 786  | PD14 <-> FMC_D0  | PE13 <-> FMC_D10  |-----------------+
 787  | PD15 <-> FMC_D1  | PE14 <-> FMC_D11  |
 788  |                  | PE15 <-> FMC_D12  |
 789  +------------------+------------------+
 790 */
 791    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
 792   RCC->AHB1ENR   |= 0x00000078;
 793
 794   /* Connect PDx pins to FMC Alternate function */
 795   GPIOD->AFR[0]  = 0x00cc00cc;
 796   GPIOD->AFR[1]  = 0xcccccccc;
 797   /* Configure PDx pins in Alternate function mode */
 798   GPIOD->MODER   = 0xaaaa0a0a;
 799   /* Configure PDx pins speed to 100 MHz */
 800   GPIOD->OSPEEDR = 0xffff0f0f;
 801   /* Configure PDx pins Output type to push-pull */
 802   GPIOD->OTYPER  = 0x00000000;
 803   /* No pull-up, pull-down for PDx pins */
 804   GPIOD->PUPDR   = 0x00000000;
 805
 806   /* Connect PEx pins to FMC Alternate function */
 807   GPIOE->AFR[0]  = 0xcccccccc;
 808   GPIOE->AFR[1]  = 0xcccccccc;
 809   /* Configure PEx pins in Alternate function mode */
 810   GPIOE->MODER   = 0xaaaaaaaa;
 811   /* Configure PEx pins speed to 100 MHz */
 812   GPIOE->OSPEEDR = 0xffffffff;
 813   /* Configure PEx pins Output type to push-pull */
 814   GPIOE->OTYPER  = 0x00000000;
 815   /* No pull-up, pull-down for PEx pins */
 816   GPIOE->PUPDR   = 0x00000000;
 817
 818   /* Connect PFx pins to FMC Alternate function */
 819   GPIOF->AFR[0]  = 0x00cccccc;
 820   GPIOF->AFR[1]  = 0xcccc0000;
 821   /* Configure PFx pins in Alternate function mode */
 822   GPIOF->MODER   = 0xaa000aaa;
 823   /* Configure PFx pins speed to 100 MHz */
 824   GPIOF->OSPEEDR = 0xff000fff;
 825   /* Configure PFx pins Output type to push-pull */
 826   GPIOF->OTYPER  = 0x00000000;
 827   /* No pull-up, pull-down for PFx pins */
 828   GPIOF->PUPDR   = 0x00000000;
 829
 830   /* Connect PGx pins to FMC Alternate function */
 831   GPIOG->AFR[0]  = 0x00cccccc;
 832   GPIOG->AFR[1]  = 0x000000c0;
 833   /* Configure PGx pins in Alternate function mode */
 834   GPIOG->MODER   = 0x00080aaa;
 835   /* Configure PGx pins speed to 100 MHz */
 836   GPIOG->OSPEEDR = 0x000c0fff;
 837   /* Configure PGx pins Output type to push-pull */
 838   GPIOG->OTYPER  = 0x00000000;
 839   /* No pull-up, pull-down for PGx pins */
 840   GPIOG->PUPDR   = 0x00000000;
 841
 842 /*-- FMC Configuration ------------------------------------------------------*/
 843   /* Enable the FMC/FSMC interface clock */
 844   RCC->AHB3ENR         |= 0x00000001;
 845
 846 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 847   /* Configure and enable Bank1_SRAM2 */
 848   FMC_Bank1->BTCR[2]  = 0x00001011;
 849   FMC_Bank1->BTCR[3]  = 0x00000201;
 850   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 851 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 852
 853 #if defined(STM32F40_41xxx)
 854   /* Configure and enable Bank1_SRAM2 */
 855   FSMC_Bank1->BTCR[2]  = 0x00001011;
 856   FSMC_Bank1->BTCR[3]  = 0x00000201;
 857   FSMC_Bank1E->BWTR[2] = 0x0fffffff;
 858 #endif  /* STM32F40_41xxx */
 859
 860 /*
 861   Bank1_SRAM2 is configured as follow:
 862   In case of FSMC configuration
 863   NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
 864   NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
 865   NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
 866   NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
 867   NORSRAMTimingStructure.FSMC_CLKDivision = 0;
 868   NORSRAMTimingStructure.FSMC_DataLatency = 0;
 869   NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
 870
 871   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
 872   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
 873   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
 874   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
 875   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
 876   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
 877   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
 878   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
 879   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
 880   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
 881   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
 882   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
 883   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
 884   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
 885   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
 886
 887   In case of FMC configuration
 888   NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
 889   NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
 890   NORSRAMTimingStructure.FMC_DataSetupTime = 2;
 891   NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
 892   NORSRAMTimingStructure.FMC_CLKDivision = 0;
 893   NORSRAMTimingStructure.FMC_DataLatency = 0;
 894   NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
 895
 896   FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
 897   FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
 898   FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
 899   FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
 900   FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
 901   FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
 902   FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
 903   FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
 904   FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
 905   FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
 906   FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
 907   FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
 908   FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
 909   FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
 910   FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
 911   FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
 912 */
 913
 914 }
 915 #endif /* DATA_IN_ExtSRAM */
 916
 917 #ifdef DATA_IN_ExtSDRAM
 918 /**
 919   * @brief  Setup the external memory controller.
 920   *         Called in startup_stm32f4xx.s before jump to main.
 921   *         This function configures the external SDRAM mounted on STM324x9I_EVAL board
 922   *         This SDRAM will be used as program data memory (including heap and stack).
 923   * @param  None
 924   * @retval None
 925   */
 926 void SystemInit_ExtMemCtl(void)
 927 {
 928   register uint32_t tmpreg = 0, timeout = 0xFFFF;
 929   register uint32_t index;
 930
 931   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
 932       clock */
 933   RCC->AHB1ENR |= 0x000001FC;
 934
 935   /* Connect PCx pins to FMC Alternate function */
 936   GPIOC->AFR[0]  = 0x0000000c;
 937   GPIOC->AFR[1]  = 0x00007700;
 938   /* Configure PCx pins in Alternate function mode */
 939   GPIOC->MODER   = 0x00a00002;
 940   /* Configure PCx pins speed to 50 MHz */
 941   GPIOC->OSPEEDR = 0x00a00002;
 942   /* Configure PCx pins Output type to push-pull */
 943   GPIOC->OTYPER  = 0x00000000;
 944   /* No pull-up, pull-down for PCx pins */
 945   GPIOC->PUPDR   = 0x00500000;
 946
 947   /* Connect PDx pins to FMC Alternate function */
 948   GPIOD->AFR[0]  = 0x000000CC;
 949   GPIOD->AFR[1]  = 0xCC000CCC;
 950   /* Configure PDx pins in Alternate function mode */
 951   GPIOD->MODER   = 0xA02A000A;
 952   /* Configure PDx pins speed to 50 MHz */
 953   GPIOD->OSPEEDR = 0xA02A000A;
 954   /* Configure PDx pins Output type to push-pull */
 955   GPIOD->OTYPER  = 0x00000000;
 956   /* No pull-up, pull-down for PDx pins */
 957   GPIOD->PUPDR   = 0x00000000;
 958
 959   /* Connect PEx pins to FMC Alternate function */
 960   GPIOE->AFR[0]  = 0xC00000CC;
 961   GPIOE->AFR[1]  = 0xCCCCCCCC;
 962   /* Configure PEx pins in Alternate function mode */
 963   GPIOE->MODER   = 0xAAAA800A;
 964   /* Configure PEx pins speed to 50 MHz */
 965   GPIOE->OSPEEDR = 0xAAAA800A;
 966   /* Configure PEx pins Output type to push-pull */
 967   GPIOE->OTYPER  = 0x00000000;
 968   /* No pull-up, pull-down for PEx pins */
 969   GPIOE->PUPDR   = 0x00000000;
 970
 971   /* Connect PFx pins to FMC Alternate function */
 972   GPIOF->AFR[0]  = 0xcccccccc;
 973   GPIOF->AFR[1]  = 0xcccccccc;
 974   /* Configure PFx pins in Alternate function mode */
 975   GPIOF->MODER   = 0xAA800AAA;
 976   /* Configure PFx pins speed to 50 MHz */
 977   GPIOF->OSPEEDR = 0xAA800AAA;
 978   /* Configure PFx pins Output type to push-pull */
 979   GPIOF->OTYPER  = 0x00000000;
 980   /* No pull-up, pull-down for PFx pins */
 981   GPIOF->PUPDR   = 0x00000000;
 982
 983   /* Connect PGx pins to FMC Alternate function */
 984   GPIOG->AFR[0]  = 0xcccccccc;
 985   GPIOG->AFR[1]  = 0xcccccccc;
 986   /* Configure PGx pins in Alternate function mode */
 987   GPIOG->MODER   = 0xaaaaaaaa;
 988   /* Configure PGx pins speed to 50 MHz */
 989   GPIOG->OSPEEDR = 0xaaaaaaaa;
 990   /* Configure PGx pins Output type to push-pull */
 991   GPIOG->OTYPER  = 0x00000000;
 992   /* No pull-up, pull-down for PGx pins */
 993   GPIOG->PUPDR   = 0x00000000;
 994
 995   /* Connect PHx pins to FMC Alternate function */
 996   GPIOH->AFR[0]  = 0x00C0CC00;
 997   GPIOH->AFR[1]  = 0xCCCCCCCC;
 998   /* Configure PHx pins in Alternate function mode */
 999   GPIOH->MODER   = 0xAAAA08A0;
1000   /* Configure PHx pins speed to 50 MHz */
1001   GPIOH->OSPEEDR = 0xAAAA08A0;
1002   /* Configure PHx pins Output type to push-pull */
1003   GPIOH->OTYPER  = 0x00000000;
1004   /* No pull-up, pull-down for PHx pins */
1005   GPIOH->PUPDR   = 0x00000000;
1006
1007   /* Connect PIx pins to FMC Alternate function */
1008   GPIOI->AFR[0]  = 0xCCCCCCCC;
1009   GPIOI->AFR[1]  = 0x00000CC0;
1010   /* Configure PIx pins in Alternate function mode */
1011   GPIOI->MODER   = 0x0028AAAA;
1012   /* Configure PIx pins speed to 50 MHz */
1013   GPIOI->OSPEEDR = 0x0028AAAA;
1014   /* Configure PIx pins Output type to push-pull */
1015   GPIOI->OTYPER  = 0x00000000;
1016   /* No pull-up, pull-down for PIx pins */
1017   GPIOI->PUPDR   = 0x00000000;
1018
1019 /*-- FMC Configuration ------------------------------------------------------*/
1020   /* Enable the FMC interface clock */
1021   RCC->AHB3ENR |= 0x00000001;
1022
1023   /* Configure and enable SDRAM bank1 */
1024   FMC_Bank5_6->SDCR[0] = 0x000039D0;
1025   FMC_Bank5_6->SDTR[0] = 0x01115351;
1026
1027   /* SDRAM initialization sequence */
1028   /* Clock enable command */
1029   FMC_Bank5_6->SDCMR = 0x00000011;
1030   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1031   while((tmpreg != 0) & (timeout-- > 0))
1032   {
1033     tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1034   }
1035
1036   /* Delay */
1037   for (index = 0; index<1000; index++);
1038
1039   /* PALL command */
1040   FMC_Bank5_6->SDCMR = 0x00000012;
1041   timeout = 0xFFFF;
1042   while((tmpreg != 0) & (timeout-- > 0))
1043   {
1044   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1045   }
1046
1047   /* Auto refresh command */
1048   FMC_Bank5_6->SDCMR = 0x00000073;
1049   timeout = 0xFFFF;
1050   while((tmpreg != 0) & (timeout-- > 0))
1051   {
1052   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1053   }
1054
1055   /* MRD register program */
1056   FMC_Bank5_6->SDCMR = 0x00046014;
1057   timeout = 0xFFFF;
1058   while((tmpreg != 0) & (timeout-- > 0))
1059   {
1060   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1061   }
1062
1063   /* Set refresh count */
1064   tmpreg = FMC_Bank5_6->SDRTR;
1065   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
1066
1067   /* Disable write protection */
1068   tmpreg = FMC_Bank5_6->SDCR[0];
1069   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
1070
1071 /*
1072   Bank1_SDRAM is configured as follow:
1073
1074   FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
1075   FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
1076   FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
1077   FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
1078   FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
1079   FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
1080   FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
1081
1082   FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
1083   FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
1084   FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
1085   FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
1086   FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
1087   FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
1088   FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
1089   FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
1090   FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
1091   FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
1092   FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
1093 */
1094
1095 }
1096 #endif /* DATA_IN_ExtSDRAM */
1097
1098
1099 /**
1100   * @}
1101   */
1102
1103 /**
1104   * @}
1105   */
1106
1107 /**
1108   * @}
1109   */
1110 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/