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Merge pull request #10385 from iNavFlight/micoair-alt-compass
[inav.git] / dev / svd / STM32F7x6.svd
blobb1861ca89d6cbfd5e359951f654a975269fb0f85
1 <?xml version="1.0" encoding="utf-8" standalone="no"?>
2 <device schemaVersion="1.1"
3 xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
4 xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
5 <name>STM32F7x6</name>
6 <version>1.3</version>
7 <description>STM32F7x6</description>
8 <!-- details about the cpu embedded in the device -->
9 <cpu>
10 <name>CM7</name>
11 <revision>r0p0</revision>
12 <endian>little</endian>
13 <mpuPresent>false</mpuPresent>
14 <fpuPresent>false</fpuPresent>
15 <nvicPrioBits>3</nvicPrioBits>
16 <vendorSystickConfig>false</vendorSystickConfig>
17 </cpu>
18 <!--Bus Interface Properties-->
19 <!--Cortex-M3 is byte addressable-->
20 <addressUnitBits>8</addressUnitBits>
21 <!--the maximum data bit width accessible within a single transfer-->
22 <width>32</width>
23 <!--Register Default Properties-->
24 <size>0x20</size>
25 <resetValue>0x0</resetValue>
26 <resetMask>0xFFFFFFFF</resetMask>
27 <peripherals>
28 <peripheral>
29 <name>RNG</name>
30 <description>Random number generator</description>
31 <groupName>RNG</groupName>
32 <baseAddress>0x50060800</baseAddress>
33 <addressBlock>
34 <offset>0x0</offset>
35 <size>0x400</size>
36 <usage>registers</usage>
37 </addressBlock>
38 <interrupt>
39 <name>HASH_RNG</name>
40 <description>Hash and Rng global interrupt</description>
41 <value>80</value>
42 </interrupt>
43 <registers>
44 <register>
45 <name>CR</name>
46 <displayName>CR</displayName>
47 <description>control register</description>
48 <addressOffset>0x0</addressOffset>
49 <size>0x20</size>
50 <access>read-write</access>
51 <resetValue>0x00000000</resetValue>
52 <fields>
53 <field>
54 <name>IE</name>
55 <description>Interrupt enable</description>
56 <bitOffset>3</bitOffset>
57 <bitWidth>1</bitWidth>
58 </field>
59 <field>
60 <name>RNGEN</name>
61 <description>Random number generator
62 enable</description>
63 <bitOffset>2</bitOffset>
64 <bitWidth>1</bitWidth>
65 </field>
66 </fields>
67 </register>
68 <register>
69 <name>SR</name>
70 <displayName>SR</displayName>
71 <description>status register</description>
72 <addressOffset>0x4</addressOffset>
73 <size>0x20</size>
74 <resetValue>0x00000000</resetValue>
75 <fields>
76 <field>
77 <name>SEIS</name>
78 <description>Seed error interrupt
79 status</description>
80 <bitOffset>6</bitOffset>
81 <bitWidth>1</bitWidth>
82 <access>read-write</access>
83 </field>
84 <field>
85 <name>CEIS</name>
86 <description>Clock error interrupt
87 status</description>
88 <bitOffset>5</bitOffset>
89 <bitWidth>1</bitWidth>
90 <access>read-write</access>
91 </field>
92 <field>
93 <name>SECS</name>
94 <description>Seed error current status</description>
95 <bitOffset>2</bitOffset>
96 <bitWidth>1</bitWidth>
97 <access>read-only</access>
98 </field>
99 <field>
100 <name>CECS</name>
101 <description>Clock error current status</description>
102 <bitOffset>1</bitOffset>
103 <bitWidth>1</bitWidth>
104 <access>read-only</access>
105 </field>
106 <field>
107 <name>DRDY</name>
108 <description>Data ready</description>
109 <bitOffset>0</bitOffset>
110 <bitWidth>1</bitWidth>
111 <access>read-only</access>
112 </field>
113 </fields>
114 </register>
115 <register>
116 <name>DR</name>
117 <displayName>DR</displayName>
118 <description>data register</description>
119 <addressOffset>0x8</addressOffset>
120 <size>0x20</size>
121 <access>read-only</access>
122 <resetValue>0x00000000</resetValue>
123 <fields>
124 <field>
125 <name>RNDATA</name>
126 <description>Random data</description>
127 <bitOffset>0</bitOffset>
128 <bitWidth>32</bitWidth>
129 </field>
130 </fields>
131 </register>
132 </registers>
133 </peripheral>
134 <peripheral>
135 <name>HASH</name>
136 <description>Hash processor</description>
137 <groupName>HASH</groupName>
138 <baseAddress>0x50060400</baseAddress>
139 <addressBlock>
140 <offset>0x0</offset>
141 <size>0x400</size>
142 <usage>registers</usage>
143 </addressBlock>
144 <registers>
145 <register>
146 <name>CR</name>
147 <displayName>CR</displayName>
148 <description>control register</description>
149 <addressOffset>0x0</addressOffset>
150 <size>0x20</size>
151 <resetValue>0x00000000</resetValue>
152 <fields>
153 <field>
154 <name>INIT</name>
155 <description>Initialize message digest
156 calculation</description>
157 <bitOffset>2</bitOffset>
158 <bitWidth>1</bitWidth>
159 <access>write-only</access>
160 </field>
161 <field>
162 <name>DMAE</name>
163 <description>DMA enable</description>
164 <bitOffset>3</bitOffset>
165 <bitWidth>1</bitWidth>
166 <access>read-write</access>
167 </field>
168 <field>
169 <name>DATATYPE</name>
170 <description>Data type selection</description>
171 <bitOffset>4</bitOffset>
172 <bitWidth>2</bitWidth>
173 <access>read-write</access>
174 </field>
175 <field>
176 <name>MODE</name>
177 <description>Mode selection</description>
178 <bitOffset>6</bitOffset>
179 <bitWidth>1</bitWidth>
180 <access>read-write</access>
181 </field>
182 <field>
183 <name>ALGO0</name>
184 <description>Algorithm selection</description>
185 <bitOffset>7</bitOffset>
186 <bitWidth>1</bitWidth>
187 <access>read-write</access>
188 </field>
189 <field>
190 <name>NBW</name>
191 <description>Number of words already
192 pushed</description>
193 <bitOffset>8</bitOffset>
194 <bitWidth>4</bitWidth>
195 <access>read-only</access>
196 </field>
197 <field>
198 <name>DINNE</name>
199 <description>DIN not empty</description>
200 <bitOffset>12</bitOffset>
201 <bitWidth>1</bitWidth>
202 <access>read-only</access>
203 </field>
204 <field>
205 <name>MDMAT</name>
206 <description>Multiple DMA Transfers</description>
207 <bitOffset>13</bitOffset>
208 <bitWidth>1</bitWidth>
209 <access>read-write</access>
210 </field>
211 <field>
212 <name>LKEY</name>
213 <description>Long key selection</description>
214 <bitOffset>16</bitOffset>
215 <bitWidth>1</bitWidth>
216 <access>read-write</access>
217 </field>
218 <field>
219 <name>ALGO1</name>
220 <description>ALGO</description>
221 <bitOffset>18</bitOffset>
222 <bitWidth>1</bitWidth>
223 <access>read-write</access>
224 </field>
225 </fields>
226 </register>
227 <register>
228 <name>DIN</name>
229 <displayName>DIN</displayName>
230 <description>data input register</description>
231 <addressOffset>0x4</addressOffset>
232 <size>0x20</size>
233 <access>read-write</access>
234 <resetValue>0x00000000</resetValue>
235 <fields>
236 <field>
237 <name>DATAIN</name>
238 <description>Data input</description>
239 <bitOffset>0</bitOffset>
240 <bitWidth>32</bitWidth>
241 </field>
242 </fields>
243 </register>
244 <register>
245 <name>STR</name>
246 <displayName>STR</displayName>
247 <description>start register</description>
248 <addressOffset>0x8</addressOffset>
249 <size>0x20</size>
250 <resetValue>0x00000000</resetValue>
251 <fields>
252 <field>
253 <name>DCAL</name>
254 <description>Digest calculation</description>
255 <bitOffset>8</bitOffset>
256 <bitWidth>1</bitWidth>
257 <access>write-only</access>
258 </field>
259 <field>
260 <name>NBLW</name>
261 <description>Number of valid bits in the last word of
262 the message</description>
263 <bitOffset>0</bitOffset>
264 <bitWidth>5</bitWidth>
265 <access>read-write</access>
266 </field>
267 </fields>
268 </register>
269 <register>
270 <name>HR0</name>
271 <displayName>HR0</displayName>
272 <description>digest registers</description>
273 <addressOffset>0xC</addressOffset>
274 <size>0x20</size>
275 <access>read-only</access>
276 <resetValue>0x00000000</resetValue>
277 <fields>
278 <field>
279 <name>H0</name>
280 <description>H0</description>
281 <bitOffset>0</bitOffset>
282 <bitWidth>32</bitWidth>
283 </field>
284 </fields>
285 </register>
286 <register>
287 <name>HR1</name>
288 <displayName>HR1</displayName>
289 <description>digest registers</description>
290 <addressOffset>0x10</addressOffset>
291 <size>0x20</size>
292 <access>read-only</access>
293 <resetValue>0x00000000</resetValue>
294 <fields>
295 <field>
296 <name>H1</name>
297 <description>H1</description>
298 <bitOffset>0</bitOffset>
299 <bitWidth>32</bitWidth>
300 </field>
301 </fields>
302 </register>
303 <register>
304 <name>HR2</name>
305 <displayName>HR2</displayName>
306 <description>digest registers</description>
307 <addressOffset>0x14</addressOffset>
308 <size>0x20</size>
309 <access>read-only</access>
310 <resetValue>0x00000000</resetValue>
311 <fields>
312 <field>
313 <name>H2</name>
314 <description>H2</description>
315 <bitOffset>0</bitOffset>
316 <bitWidth>32</bitWidth>
317 </field>
318 </fields>
319 </register>
320 <register>
321 <name>HR3</name>
322 <displayName>HR3</displayName>
323 <description>digest registers</description>
324 <addressOffset>0x18</addressOffset>
325 <size>0x20</size>
326 <access>read-only</access>
327 <resetValue>0x00000000</resetValue>
328 <fields>
329 <field>
330 <name>H3</name>
331 <description>H3</description>
332 <bitOffset>0</bitOffset>
333 <bitWidth>32</bitWidth>
334 </field>
335 </fields>
336 </register>
337 <register>
338 <name>HR4</name>
339 <displayName>HR4</displayName>
340 <description>digest registers</description>
341 <addressOffset>0x1C</addressOffset>
342 <size>0x20</size>
343 <access>read-only</access>
344 <resetValue>0x00000000</resetValue>
345 <fields>
346 <field>
347 <name>H4</name>
348 <description>H4</description>
349 <bitOffset>0</bitOffset>
350 <bitWidth>32</bitWidth>
351 </field>
352 </fields>
353 </register>
354 <register>
355 <name>IMR</name>
356 <displayName>IMR</displayName>
357 <description>interrupt enable register</description>
358 <addressOffset>0x20</addressOffset>
359 <size>0x20</size>
360 <access>read-write</access>
361 <resetValue>0x00000000</resetValue>
362 <fields>
363 <field>
364 <name>DCIE</name>
365 <description>Digest calculation completion interrupt
366 enable</description>
367 <bitOffset>1</bitOffset>
368 <bitWidth>1</bitWidth>
369 </field>
370 <field>
371 <name>DINIE</name>
372 <description>Data input interrupt
373 enable</description>
374 <bitOffset>0</bitOffset>
375 <bitWidth>1</bitWidth>
376 </field>
377 </fields>
378 </register>
379 <register>
380 <name>SR</name>
381 <displayName>SR</displayName>
382 <description>status register</description>
383 <addressOffset>0x24</addressOffset>
384 <size>0x20</size>
385 <resetValue>0x00000001</resetValue>
386 <fields>
387 <field>
388 <name>BUSY</name>
389 <description>Busy bit</description>
390 <bitOffset>3</bitOffset>
391 <bitWidth>1</bitWidth>
392 <access>read-only</access>
393 </field>
394 <field>
395 <name>DMAS</name>
396 <description>DMA Status</description>
397 <bitOffset>2</bitOffset>
398 <bitWidth>1</bitWidth>
399 <access>read-only</access>
400 </field>
401 <field>
402 <name>DCIS</name>
403 <description>Digest calculation completion interrupt
404 status</description>
405 <bitOffset>1</bitOffset>
406 <bitWidth>1</bitWidth>
407 <access>read-write</access>
408 </field>
409 <field>
410 <name>DINIS</name>
411 <description>Data input interrupt
412 status</description>
413 <bitOffset>0</bitOffset>
414 <bitWidth>1</bitWidth>
415 <access>read-write</access>
416 </field>
417 </fields>
418 </register>
419 <register>
420 <name>CSR0</name>
421 <displayName>CSR0</displayName>
422 <description>context swap registers</description>
423 <addressOffset>0xF8</addressOffset>
424 <size>0x20</size>
425 <access>read-write</access>
426 <resetValue>0x00000000</resetValue>
427 <fields>
428 <field>
429 <name>CSR0</name>
430 <description>CSR0</description>
431 <bitOffset>0</bitOffset>
432 <bitWidth>32</bitWidth>
433 </field>
434 </fields>
435 </register>
436 <register>
437 <name>CSR1</name>
438 <displayName>CSR1</displayName>
439 <description>context swap registers</description>
440 <addressOffset>0xFC</addressOffset>
441 <size>0x20</size>
442 <access>read-write</access>
443 <resetValue>0x00000000</resetValue>
444 <fields>
445 <field>
446 <name>CSR1</name>
447 <description>CSR1</description>
448 <bitOffset>0</bitOffset>
449 <bitWidth>32</bitWidth>
450 </field>
451 </fields>
452 </register>
453 <register>
454 <name>CSR2</name>
455 <displayName>CSR2</displayName>
456 <description>context swap registers</description>
457 <addressOffset>0x100</addressOffset>
458 <size>0x20</size>
459 <access>read-write</access>
460 <resetValue>0x00000000</resetValue>
461 <fields>
462 <field>
463 <name>CSR2</name>
464 <description>CSR2</description>
465 <bitOffset>0</bitOffset>
466 <bitWidth>32</bitWidth>
467 </field>
468 </fields>
469 </register>
470 <register>
471 <name>CSR3</name>
472 <displayName>CSR3</displayName>
473 <description>context swap registers</description>
474 <addressOffset>0x104</addressOffset>
475 <size>0x20</size>
476 <access>read-write</access>
477 <resetValue>0x00000000</resetValue>
478 <fields>
479 <field>
480 <name>CSR3</name>
481 <description>CSR3</description>
482 <bitOffset>0</bitOffset>
483 <bitWidth>32</bitWidth>
484 </field>
485 </fields>
486 </register>
487 <register>
488 <name>CSR4</name>
489 <displayName>CSR4</displayName>
490 <description>context swap registers</description>
491 <addressOffset>0x108</addressOffset>
492 <size>0x20</size>
493 <access>read-write</access>
494 <resetValue>0x00000000</resetValue>
495 <fields>
496 <field>
497 <name>CSR4</name>
498 <description>CSR4</description>
499 <bitOffset>0</bitOffset>
500 <bitWidth>32</bitWidth>
501 </field>
502 </fields>
503 </register>
504 <register>
505 <name>CSR5</name>
506 <displayName>CSR5</displayName>
507 <description>context swap registers</description>
508 <addressOffset>0x10C</addressOffset>
509 <size>0x20</size>
510 <access>read-write</access>
511 <resetValue>0x00000000</resetValue>
512 <fields>
513 <field>
514 <name>CSR5</name>
515 <description>CSR5</description>
516 <bitOffset>0</bitOffset>
517 <bitWidth>32</bitWidth>
518 </field>
519 </fields>
520 </register>
521 <register>
522 <name>CSR6</name>
523 <displayName>CSR6</displayName>
524 <description>context swap registers</description>
525 <addressOffset>0x110</addressOffset>
526 <size>0x20</size>
527 <access>read-write</access>
528 <resetValue>0x00000000</resetValue>
529 <fields>
530 <field>
531 <name>CSR6</name>
532 <description>CSR6</description>
533 <bitOffset>0</bitOffset>
534 <bitWidth>32</bitWidth>
535 </field>
536 </fields>
537 </register>
538 <register>
539 <name>CSR7</name>
540 <displayName>CSR7</displayName>
541 <description>context swap registers</description>
542 <addressOffset>0x114</addressOffset>
543 <size>0x20</size>
544 <access>read-write</access>
545 <resetValue>0x00000000</resetValue>
546 <fields>
547 <field>
548 <name>CSR7</name>
549 <description>CSR7</description>
550 <bitOffset>0</bitOffset>
551 <bitWidth>32</bitWidth>
552 </field>
553 </fields>
554 </register>
555 <register>
556 <name>CSR8</name>
557 <displayName>CSR8</displayName>
558 <description>context swap registers</description>
559 <addressOffset>0x118</addressOffset>
560 <size>0x20</size>
561 <access>read-write</access>
562 <resetValue>0x00000000</resetValue>
563 <fields>
564 <field>
565 <name>CSR8</name>
566 <description>CSR8</description>
567 <bitOffset>0</bitOffset>
568 <bitWidth>32</bitWidth>
569 </field>
570 </fields>
571 </register>
572 <register>
573 <name>CSR9</name>
574 <displayName>CSR9</displayName>
575 <description>context swap registers</description>
576 <addressOffset>0x11C</addressOffset>
577 <size>0x20</size>
578 <access>read-write</access>
579 <resetValue>0x00000000</resetValue>
580 <fields>
581 <field>
582 <name>CSR9</name>
583 <description>CSR9</description>
584 <bitOffset>0</bitOffset>
585 <bitWidth>32</bitWidth>
586 </field>
587 </fields>
588 </register>
589 <register>
590 <name>CSR10</name>
591 <displayName>CSR10</displayName>
592 <description>context swap registers</description>
593 <addressOffset>0x120</addressOffset>
594 <size>0x20</size>
595 <access>read-write</access>
596 <resetValue>0x00000000</resetValue>
597 <fields>
598 <field>
599 <name>CSR10</name>
600 <description>CSR10</description>
601 <bitOffset>0</bitOffset>
602 <bitWidth>32</bitWidth>
603 </field>
604 </fields>
605 </register>
606 <register>
607 <name>CSR11</name>
608 <displayName>CSR11</displayName>
609 <description>context swap registers</description>
610 <addressOffset>0x124</addressOffset>
611 <size>0x20</size>
612 <access>read-write</access>
613 <resetValue>0x00000000</resetValue>
614 <fields>
615 <field>
616 <name>CSR11</name>
617 <description>CSR11</description>
618 <bitOffset>0</bitOffset>
619 <bitWidth>32</bitWidth>
620 </field>
621 </fields>
622 </register>
623 <register>
624 <name>CSR12</name>
625 <displayName>CSR12</displayName>
626 <description>context swap registers</description>
627 <addressOffset>0x128</addressOffset>
628 <size>0x20</size>
629 <access>read-write</access>
630 <resetValue>0x00000000</resetValue>
631 <fields>
632 <field>
633 <name>CSR12</name>
634 <description>CSR12</description>
635 <bitOffset>0</bitOffset>
636 <bitWidth>32</bitWidth>
637 </field>
638 </fields>
639 </register>
640 <register>
641 <name>CSR13</name>
642 <displayName>CSR13</displayName>
643 <description>context swap registers</description>
644 <addressOffset>0x12C</addressOffset>
645 <size>0x20</size>
646 <access>read-write</access>
647 <resetValue>0x00000000</resetValue>
648 <fields>
649 <field>
650 <name>CSR13</name>
651 <description>CSR13</description>
652 <bitOffset>0</bitOffset>
653 <bitWidth>32</bitWidth>
654 </field>
655 </fields>
656 </register>
657 <register>
658 <name>CSR14</name>
659 <displayName>CSR14</displayName>
660 <description>context swap registers</description>
661 <addressOffset>0x130</addressOffset>
662 <size>0x20</size>
663 <access>read-write</access>
664 <resetValue>0x00000000</resetValue>
665 <fields>
666 <field>
667 <name>CSR14</name>
668 <description>CSR14</description>
669 <bitOffset>0</bitOffset>
670 <bitWidth>32</bitWidth>
671 </field>
672 </fields>
673 </register>
674 <register>
675 <name>CSR15</name>
676 <displayName>CSR15</displayName>
677 <description>context swap registers</description>
678 <addressOffset>0x134</addressOffset>
679 <size>0x20</size>
680 <access>read-write</access>
681 <resetValue>0x00000000</resetValue>
682 <fields>
683 <field>
684 <name>CSR15</name>
685 <description>CSR15</description>
686 <bitOffset>0</bitOffset>
687 <bitWidth>32</bitWidth>
688 </field>
689 </fields>
690 </register>
691 <register>
692 <name>CSR16</name>
693 <displayName>CSR16</displayName>
694 <description>context swap registers</description>
695 <addressOffset>0x138</addressOffset>
696 <size>0x20</size>
697 <access>read-write</access>
698 <resetValue>0x00000000</resetValue>
699 <fields>
700 <field>
701 <name>CSR16</name>
702 <description>CSR16</description>
703 <bitOffset>0</bitOffset>
704 <bitWidth>32</bitWidth>
705 </field>
706 </fields>
707 </register>
708 <register>
709 <name>CSR17</name>
710 <displayName>CSR17</displayName>
711 <description>context swap registers</description>
712 <addressOffset>0x13C</addressOffset>
713 <size>0x20</size>
714 <access>read-write</access>
715 <resetValue>0x00000000</resetValue>
716 <fields>
717 <field>
718 <name>CSR17</name>
719 <description>CSR17</description>
720 <bitOffset>0</bitOffset>
721 <bitWidth>32</bitWidth>
722 </field>
723 </fields>
724 </register>
725 <register>
726 <name>CSR18</name>
727 <displayName>CSR18</displayName>
728 <description>context swap registers</description>
729 <addressOffset>0x140</addressOffset>
730 <size>0x20</size>
731 <access>read-write</access>
732 <resetValue>0x00000000</resetValue>
733 <fields>
734 <field>
735 <name>CSR18</name>
736 <description>CSR18</description>
737 <bitOffset>0</bitOffset>
738 <bitWidth>32</bitWidth>
739 </field>
740 </fields>
741 </register>
742 <register>
743 <name>CSR19</name>
744 <displayName>CSR19</displayName>
745 <description>context swap registers</description>
746 <addressOffset>0x144</addressOffset>
747 <size>0x20</size>
748 <access>read-write</access>
749 <resetValue>0x00000000</resetValue>
750 <fields>
751 <field>
752 <name>CSR19</name>
753 <description>CSR19</description>
754 <bitOffset>0</bitOffset>
755 <bitWidth>32</bitWidth>
756 </field>
757 </fields>
758 </register>
759 <register>
760 <name>CSR20</name>
761 <displayName>CSR20</displayName>
762 <description>context swap registers</description>
763 <addressOffset>0x148</addressOffset>
764 <size>0x20</size>
765 <access>read-write</access>
766 <resetValue>0x00000000</resetValue>
767 <fields>
768 <field>
769 <name>CSR20</name>
770 <description>CSR20</description>
771 <bitOffset>0</bitOffset>
772 <bitWidth>32</bitWidth>
773 </field>
774 </fields>
775 </register>
776 <register>
777 <name>CSR21</name>
778 <displayName>CSR21</displayName>
779 <description>context swap registers</description>
780 <addressOffset>0x14C</addressOffset>
781 <size>0x20</size>
782 <access>read-write</access>
783 <resetValue>0x00000000</resetValue>
784 <fields>
785 <field>
786 <name>CSR21</name>
787 <description>CSR21</description>
788 <bitOffset>0</bitOffset>
789 <bitWidth>32</bitWidth>
790 </field>
791 </fields>
792 </register>
793 <register>
794 <name>CSR22</name>
795 <displayName>CSR22</displayName>
796 <description>context swap registers</description>
797 <addressOffset>0x150</addressOffset>
798 <size>0x20</size>
799 <access>read-write</access>
800 <resetValue>0x00000000</resetValue>
801 <fields>
802 <field>
803 <name>CSR22</name>
804 <description>CSR22</description>
805 <bitOffset>0</bitOffset>
806 <bitWidth>32</bitWidth>
807 </field>
808 </fields>
809 </register>
810 <register>
811 <name>CSR23</name>
812 <displayName>CSR23</displayName>
813 <description>context swap registers</description>
814 <addressOffset>0x154</addressOffset>
815 <size>0x20</size>
816 <access>read-write</access>
817 <resetValue>0x00000000</resetValue>
818 <fields>
819 <field>
820 <name>CSR23</name>
821 <description>CSR23</description>
822 <bitOffset>0</bitOffset>
823 <bitWidth>32</bitWidth>
824 </field>
825 </fields>
826 </register>
827 <register>
828 <name>CSR24</name>
829 <displayName>CSR24</displayName>
830 <description>context swap registers</description>
831 <addressOffset>0x158</addressOffset>
832 <size>0x20</size>
833 <access>read-write</access>
834 <resetValue>0x00000000</resetValue>
835 <fields>
836 <field>
837 <name>CSR24</name>
838 <description>CSR24</description>
839 <bitOffset>0</bitOffset>
840 <bitWidth>32</bitWidth>
841 </field>
842 </fields>
843 </register>
844 <register>
845 <name>CSR25</name>
846 <displayName>CSR25</displayName>
847 <description>context swap registers</description>
848 <addressOffset>0x15C</addressOffset>
849 <size>0x20</size>
850 <access>read-write</access>
851 <resetValue>0x00000000</resetValue>
852 <fields>
853 <field>
854 <name>CSR25</name>
855 <description>CSR25</description>
856 <bitOffset>0</bitOffset>
857 <bitWidth>32</bitWidth>
858 </field>
859 </fields>
860 </register>
861 <register>
862 <name>CSR26</name>
863 <displayName>CSR26</displayName>
864 <description>context swap registers</description>
865 <addressOffset>0x160</addressOffset>
866 <size>0x20</size>
867 <access>read-write</access>
868 <resetValue>0x00000000</resetValue>
869 <fields>
870 <field>
871 <name>CSR26</name>
872 <description>CSR26</description>
873 <bitOffset>0</bitOffset>
874 <bitWidth>32</bitWidth>
875 </field>
876 </fields>
877 </register>
878 <register>
879 <name>CSR27</name>
880 <displayName>CSR27</displayName>
881 <description>context swap registers</description>
882 <addressOffset>0x164</addressOffset>
883 <size>0x20</size>
884 <access>read-write</access>
885 <resetValue>0x00000000</resetValue>
886 <fields>
887 <field>
888 <name>CSR27</name>
889 <description>CSR27</description>
890 <bitOffset>0</bitOffset>
891 <bitWidth>32</bitWidth>
892 </field>
893 </fields>
894 </register>
895 <register>
896 <name>CSR28</name>
897 <displayName>CSR28</displayName>
898 <description>context swap registers</description>
899 <addressOffset>0x168</addressOffset>
900 <size>0x20</size>
901 <access>read-write</access>
902 <resetValue>0x00000000</resetValue>
903 <fields>
904 <field>
905 <name>CSR28</name>
906 <description>CSR28</description>
907 <bitOffset>0</bitOffset>
908 <bitWidth>32</bitWidth>
909 </field>
910 </fields>
911 </register>
912 <register>
913 <name>CSR29</name>
914 <displayName>CSR29</displayName>
915 <description>context swap registers</description>
916 <addressOffset>0x16C</addressOffset>
917 <size>0x20</size>
918 <access>read-write</access>
919 <resetValue>0x00000000</resetValue>
920 <fields>
921 <field>
922 <name>CSR29</name>
923 <description>CSR29</description>
924 <bitOffset>0</bitOffset>
925 <bitWidth>32</bitWidth>
926 </field>
927 </fields>
928 </register>
929 <register>
930 <name>CSR30</name>
931 <displayName>CSR30</displayName>
932 <description>context swap registers</description>
933 <addressOffset>0x170</addressOffset>
934 <size>0x20</size>
935 <access>read-write</access>
936 <resetValue>0x00000000</resetValue>
937 <fields>
938 <field>
939 <name>CSR30</name>
940 <description>CSR30</description>
941 <bitOffset>0</bitOffset>
942 <bitWidth>32</bitWidth>
943 </field>
944 </fields>
945 </register>
946 <register>
947 <name>CSR31</name>
948 <displayName>CSR31</displayName>
949 <description>context swap registers</description>
950 <addressOffset>0x174</addressOffset>
951 <size>0x20</size>
952 <access>read-write</access>
953 <resetValue>0x00000000</resetValue>
954 <fields>
955 <field>
956 <name>CSR31</name>
957 <description>CSR31</description>
958 <bitOffset>0</bitOffset>
959 <bitWidth>32</bitWidth>
960 </field>
961 </fields>
962 </register>
963 <register>
964 <name>CSR32</name>
965 <displayName>CSR32</displayName>
966 <description>context swap registers</description>
967 <addressOffset>0x178</addressOffset>
968 <size>0x20</size>
969 <access>read-write</access>
970 <resetValue>0x00000000</resetValue>
971 <fields>
972 <field>
973 <name>CSR32</name>
974 <description>CSR32</description>
975 <bitOffset>0</bitOffset>
976 <bitWidth>32</bitWidth>
977 </field>
978 </fields>
979 </register>
980 <register>
981 <name>CSR33</name>
982 <displayName>CSR33</displayName>
983 <description>context swap registers</description>
984 <addressOffset>0x17C</addressOffset>
985 <size>0x20</size>
986 <access>read-write</access>
987 <resetValue>0x00000000</resetValue>
988 <fields>
989 <field>
990 <name>CSR33</name>
991 <description>CSR33</description>
992 <bitOffset>0</bitOffset>
993 <bitWidth>32</bitWidth>
994 </field>
995 </fields>
996 </register>
997 <register>
998 <name>CSR34</name>
999 <displayName>CSR34</displayName>
1000 <description>context swap registers</description>
1001 <addressOffset>0x180</addressOffset>
1002 <size>0x20</size>
1003 <access>read-write</access>
1004 <resetValue>0x00000000</resetValue>
1005 <fields>
1006 <field>
1007 <name>CSR34</name>
1008 <description>CSR34</description>
1009 <bitOffset>0</bitOffset>
1010 <bitWidth>32</bitWidth>
1011 </field>
1012 </fields>
1013 </register>
1014 <register>
1015 <name>CSR35</name>
1016 <displayName>CSR35</displayName>
1017 <description>context swap registers</description>
1018 <addressOffset>0x184</addressOffset>
1019 <size>0x20</size>
1020 <access>read-write</access>
1021 <resetValue>0x00000000</resetValue>
1022 <fields>
1023 <field>
1024 <name>CSR35</name>
1025 <description>CSR35</description>
1026 <bitOffset>0</bitOffset>
1027 <bitWidth>32</bitWidth>
1028 </field>
1029 </fields>
1030 </register>
1031 <register>
1032 <name>CSR36</name>
1033 <displayName>CSR36</displayName>
1034 <description>context swap registers</description>
1035 <addressOffset>0x188</addressOffset>
1036 <size>0x20</size>
1037 <access>read-write</access>
1038 <resetValue>0x00000000</resetValue>
1039 <fields>
1040 <field>
1041 <name>CSR36</name>
1042 <description>CSR36</description>
1043 <bitOffset>0</bitOffset>
1044 <bitWidth>32</bitWidth>
1045 </field>
1046 </fields>
1047 </register>
1048 <register>
1049 <name>CSR37</name>
1050 <displayName>CSR37</displayName>
1051 <description>context swap registers</description>
1052 <addressOffset>0x18C</addressOffset>
1053 <size>0x20</size>
1054 <access>read-write</access>
1055 <resetValue>0x00000000</resetValue>
1056 <fields>
1057 <field>
1058 <name>CSR37</name>
1059 <description>CSR37</description>
1060 <bitOffset>0</bitOffset>
1061 <bitWidth>32</bitWidth>
1062 </field>
1063 </fields>
1064 </register>
1065 <register>
1066 <name>CSR38</name>
1067 <displayName>CSR38</displayName>
1068 <description>context swap registers</description>
1069 <addressOffset>0x190</addressOffset>
1070 <size>0x20</size>
1071 <access>read-write</access>
1072 <resetValue>0x00000000</resetValue>
1073 <fields>
1074 <field>
1075 <name>CSR38</name>
1076 <description>CSR38</description>
1077 <bitOffset>0</bitOffset>
1078 <bitWidth>32</bitWidth>
1079 </field>
1080 </fields>
1081 </register>
1082 <register>
1083 <name>CSR39</name>
1084 <displayName>CSR39</displayName>
1085 <description>context swap registers</description>
1086 <addressOffset>0x194</addressOffset>
1087 <size>0x20</size>
1088 <access>read-write</access>
1089 <resetValue>0x00000000</resetValue>
1090 <fields>
1091 <field>
1092 <name>CSR39</name>
1093 <description>CSR39</description>
1094 <bitOffset>0</bitOffset>
1095 <bitWidth>32</bitWidth>
1096 </field>
1097 </fields>
1098 </register>
1099 <register>
1100 <name>CSR40</name>
1101 <displayName>CSR40</displayName>
1102 <description>context swap registers</description>
1103 <addressOffset>0x198</addressOffset>
1104 <size>0x20</size>
1105 <access>read-write</access>
1106 <resetValue>0x00000000</resetValue>
1107 <fields>
1108 <field>
1109 <name>CSR40</name>
1110 <description>CSR40</description>
1111 <bitOffset>0</bitOffset>
1112 <bitWidth>32</bitWidth>
1113 </field>
1114 </fields>
1115 </register>
1116 <register>
1117 <name>CSR41</name>
1118 <displayName>CSR41</displayName>
1119 <description>context swap registers</description>
1120 <addressOffset>0x19C</addressOffset>
1121 <size>0x20</size>
1122 <access>read-write</access>
1123 <resetValue>0x00000000</resetValue>
1124 <fields>
1125 <field>
1126 <name>CSR41</name>
1127 <description>CSR41</description>
1128 <bitOffset>0</bitOffset>
1129 <bitWidth>32</bitWidth>
1130 </field>
1131 </fields>
1132 </register>
1133 <register>
1134 <name>CSR42</name>
1135 <displayName>CSR42</displayName>
1136 <description>context swap registers</description>
1137 <addressOffset>0x1A0</addressOffset>
1138 <size>0x20</size>
1139 <access>read-write</access>
1140 <resetValue>0x00000000</resetValue>
1141 <fields>
1142 <field>
1143 <name>CSR42</name>
1144 <description>CSR42</description>
1145 <bitOffset>0</bitOffset>
1146 <bitWidth>32</bitWidth>
1147 </field>
1148 </fields>
1149 </register>
1150 <register>
1151 <name>CSR43</name>
1152 <displayName>CSR43</displayName>
1153 <description>context swap registers</description>
1154 <addressOffset>0x1A4</addressOffset>
1155 <size>0x20</size>
1156 <access>read-write</access>
1157 <resetValue>0x00000000</resetValue>
1158 <fields>
1159 <field>
1160 <name>CSR43</name>
1161 <description>CSR43</description>
1162 <bitOffset>0</bitOffset>
1163 <bitWidth>32</bitWidth>
1164 </field>
1165 </fields>
1166 </register>
1167 <register>
1168 <name>CSR44</name>
1169 <displayName>CSR44</displayName>
1170 <description>context swap registers</description>
1171 <addressOffset>0x1A8</addressOffset>
1172 <size>0x20</size>
1173 <access>read-write</access>
1174 <resetValue>0x00000000</resetValue>
1175 <fields>
1176 <field>
1177 <name>CSR44</name>
1178 <description>CSR44</description>
1179 <bitOffset>0</bitOffset>
1180 <bitWidth>32</bitWidth>
1181 </field>
1182 </fields>
1183 </register>
1184 <register>
1185 <name>CSR45</name>
1186 <displayName>CSR45</displayName>
1187 <description>context swap registers</description>
1188 <addressOffset>0x1AC</addressOffset>
1189 <size>0x20</size>
1190 <access>read-write</access>
1191 <resetValue>0x00000000</resetValue>
1192 <fields>
1193 <field>
1194 <name>CSR45</name>
1195 <description>CSR45</description>
1196 <bitOffset>0</bitOffset>
1197 <bitWidth>32</bitWidth>
1198 </field>
1199 </fields>
1200 </register>
1201 <register>
1202 <name>CSR46</name>
1203 <displayName>CSR46</displayName>
1204 <description>context swap registers</description>
1205 <addressOffset>0x1B0</addressOffset>
1206 <size>0x20</size>
1207 <access>read-write</access>
1208 <resetValue>0x00000000</resetValue>
1209 <fields>
1210 <field>
1211 <name>CSR46</name>
1212 <description>CSR46</description>
1213 <bitOffset>0</bitOffset>
1214 <bitWidth>32</bitWidth>
1215 </field>
1216 </fields>
1217 </register>
1218 <register>
1219 <name>CSR47</name>
1220 <displayName>CSR47</displayName>
1221 <description>context swap registers</description>
1222 <addressOffset>0x1B4</addressOffset>
1223 <size>0x20</size>
1224 <access>read-write</access>
1225 <resetValue>0x00000000</resetValue>
1226 <fields>
1227 <field>
1228 <name>CSR47</name>
1229 <description>CSR47</description>
1230 <bitOffset>0</bitOffset>
1231 <bitWidth>32</bitWidth>
1232 </field>
1233 </fields>
1234 </register>
1235 <register>
1236 <name>CSR48</name>
1237 <displayName>CSR48</displayName>
1238 <description>context swap registers</description>
1239 <addressOffset>0x1B8</addressOffset>
1240 <size>0x20</size>
1241 <access>read-write</access>
1242 <resetValue>0x00000000</resetValue>
1243 <fields>
1244 <field>
1245 <name>CSR48</name>
1246 <description>CSR48</description>
1247 <bitOffset>0</bitOffset>
1248 <bitWidth>32</bitWidth>
1249 </field>
1250 </fields>
1251 </register>
1252 <register>
1253 <name>CSR49</name>
1254 <displayName>CSR49</displayName>
1255 <description>context swap registers</description>
1256 <addressOffset>0x1BC</addressOffset>
1257 <size>0x20</size>
1258 <access>read-write</access>
1259 <resetValue>0x00000000</resetValue>
1260 <fields>
1261 <field>
1262 <name>CSR49</name>
1263 <description>CSR49</description>
1264 <bitOffset>0</bitOffset>
1265 <bitWidth>32</bitWidth>
1266 </field>
1267 </fields>
1268 </register>
1269 <register>
1270 <name>CSR50</name>
1271 <displayName>CSR50</displayName>
1272 <description>context swap registers</description>
1273 <addressOffset>0x1C0</addressOffset>
1274 <size>0x20</size>
1275 <access>read-write</access>
1276 <resetValue>0x00000000</resetValue>
1277 <fields>
1278 <field>
1279 <name>CSR50</name>
1280 <description>CSR50</description>
1281 <bitOffset>0</bitOffset>
1282 <bitWidth>32</bitWidth>
1283 </field>
1284 </fields>
1285 </register>
1286 <register>
1287 <name>CSR51</name>
1288 <displayName>CSR51</displayName>
1289 <description>context swap registers</description>
1290 <addressOffset>0x1C4</addressOffset>
1291 <size>0x20</size>
1292 <access>read-write</access>
1293 <resetValue>0x00000000</resetValue>
1294 <fields>
1295 <field>
1296 <name>CSR51</name>
1297 <description>CSR51</description>
1298 <bitOffset>0</bitOffset>
1299 <bitWidth>32</bitWidth>
1300 </field>
1301 </fields>
1302 </register>
1303 <register>
1304 <name>CSR52</name>
1305 <displayName>CSR52</displayName>
1306 <description>context swap registers</description>
1307 <addressOffset>0x1C8</addressOffset>
1308 <size>0x20</size>
1309 <access>read-write</access>
1310 <resetValue>0x00000000</resetValue>
1311 <fields>
1312 <field>
1313 <name>CSR52</name>
1314 <description>CSR52</description>
1315 <bitOffset>0</bitOffset>
1316 <bitWidth>32</bitWidth>
1317 </field>
1318 </fields>
1319 </register>
1320 <register>
1321 <name>CSR53</name>
1322 <displayName>CSR53</displayName>
1323 <description>context swap registers</description>
1324 <addressOffset>0x1CC</addressOffset>
1325 <size>0x20</size>
1326 <access>read-write</access>
1327 <resetValue>0x00000000</resetValue>
1328 <fields>
1329 <field>
1330 <name>CSR53</name>
1331 <description>CSR53</description>
1332 <bitOffset>0</bitOffset>
1333 <bitWidth>32</bitWidth>
1334 </field>
1335 </fields>
1336 </register>
1337 <register>
1338 <name>HASH_HR0</name>
1339 <displayName>HASH_HR0</displayName>
1340 <description>HASH digest register</description>
1341 <addressOffset>0x310</addressOffset>
1342 <size>0x20</size>
1343 <access>read-only</access>
1344 <resetValue>0x00000000</resetValue>
1345 <fields>
1346 <field>
1347 <name>H0</name>
1348 <description>H0</description>
1349 <bitOffset>0</bitOffset>
1350 <bitWidth>32</bitWidth>
1351 </field>
1352 </fields>
1353 </register>
1354 <register>
1355 <name>HASH_HR1</name>
1356 <displayName>HASH_HR1</displayName>
1357 <description>read-only</description>
1358 <addressOffset>0x314</addressOffset>
1359 <size>0x20</size>
1360 <access>read-only</access>
1361 <resetValue>0x00000000</resetValue>
1362 <fields>
1363 <field>
1364 <name>H1</name>
1365 <description>H1</description>
1366 <bitOffset>0</bitOffset>
1367 <bitWidth>32</bitWidth>
1368 </field>
1369 </fields>
1370 </register>
1371 <register>
1372 <name>HASH_HR2</name>
1373 <displayName>HASH_HR2</displayName>
1374 <description>read-only</description>
1375 <addressOffset>0x318</addressOffset>
1376 <size>0x20</size>
1377 <access>read-only</access>
1378 <resetValue>0x00000000</resetValue>
1379 <fields>
1380 <field>
1381 <name>H2</name>
1382 <description>H2</description>
1383 <bitOffset>0</bitOffset>
1384 <bitWidth>32</bitWidth>
1385 </field>
1386 </fields>
1387 </register>
1388 <register>
1389 <name>HASH_HR3</name>
1390 <displayName>HASH_HR3</displayName>
1391 <description>read-only</description>
1392 <addressOffset>0x31C</addressOffset>
1393 <size>0x20</size>
1394 <access>read-only</access>
1395 <resetValue>0x00000000</resetValue>
1396 <fields>
1397 <field>
1398 <name>H3</name>
1399 <description>H3</description>
1400 <bitOffset>0</bitOffset>
1401 <bitWidth>32</bitWidth>
1402 </field>
1403 </fields>
1404 </register>
1405 <register>
1406 <name>HASH_HR4</name>
1407 <displayName>HASH_HR4</displayName>
1408 <description>read-only</description>
1409 <addressOffset>0x320</addressOffset>
1410 <size>0x20</size>
1411 <access>read-only</access>
1412 <resetValue>0x00000000</resetValue>
1413 <fields>
1414 <field>
1415 <name>H4</name>
1416 <description>H4</description>
1417 <bitOffset>0</bitOffset>
1418 <bitWidth>32</bitWidth>
1419 </field>
1420 </fields>
1421 </register>
1422 <register>
1423 <name>HASH_HR5</name>
1424 <displayName>HASH_HR5</displayName>
1425 <description>read-only</description>
1426 <addressOffset>0x324</addressOffset>
1427 <size>0x20</size>
1428 <access>read-only</access>
1429 <resetValue>0x00000000</resetValue>
1430 <fields>
1431 <field>
1432 <name>H5</name>
1433 <description>H5</description>
1434 <bitOffset>0</bitOffset>
1435 <bitWidth>32</bitWidth>
1436 </field>
1437 </fields>
1438 </register>
1439 <register>
1440 <name>HASH_HR6</name>
1441 <displayName>HASH_HR6</displayName>
1442 <description>read-only</description>
1443 <addressOffset>0x328</addressOffset>
1444 <size>0x20</size>
1445 <access>read-only</access>
1446 <resetValue>0x00000000</resetValue>
1447 <fields>
1448 <field>
1449 <name>H6</name>
1450 <description>H6</description>
1451 <bitOffset>0</bitOffset>
1452 <bitWidth>32</bitWidth>
1453 </field>
1454 </fields>
1455 </register>
1456 <register>
1457 <name>HASH_HR7</name>
1458 <displayName>HASH_HR7</displayName>
1459 <description>read-only</description>
1460 <addressOffset>0x32C</addressOffset>
1461 <size>0x20</size>
1462 <access>read-only</access>
1463 <resetValue>0x00000000</resetValue>
1464 <fields>
1465 <field>
1466 <name>H7</name>
1467 <description>H7</description>
1468 <bitOffset>0</bitOffset>
1469 <bitWidth>32</bitWidth>
1470 </field>
1471 </fields>
1472 </register>
1473 </registers>
1474 </peripheral>
1475 <peripheral>
1476 <name>CRYP</name>
1477 <description>Cryptographic processor</description>
1478 <groupName>CRYP</groupName>
1479 <baseAddress>0x50060000</baseAddress>
1480 <addressBlock>
1481 <offset>0x0</offset>
1482 <size>0x400</size>
1483 <usage>registers</usage>
1484 </addressBlock>
1485 <registers>
1486 <register>
1487 <name>CR</name>
1488 <displayName>CR</displayName>
1489 <description>control register</description>
1490 <addressOffset>0x0</addressOffset>
1491 <size>0x20</size>
1492 <resetValue>0x00000000</resetValue>
1493 <fields>
1494 <field>
1495 <name>ALGODIR</name>
1496 <description>Algorithm direction</description>
1497 <bitOffset>2</bitOffset>
1498 <bitWidth>1</bitWidth>
1499 <access>read-write</access>
1500 </field>
1501 <field>
1502 <name>ALGOMODE0</name>
1503 <description>Algorithm mode</description>
1504 <bitOffset>3</bitOffset>
1505 <bitWidth>3</bitWidth>
1506 <access>read-write</access>
1507 </field>
1508 <field>
1509 <name>DATATYPE</name>
1510 <description>Data type selection</description>
1511 <bitOffset>6</bitOffset>
1512 <bitWidth>2</bitWidth>
1513 <access>read-write</access>
1514 </field>
1515 <field>
1516 <name>KEYSIZE</name>
1517 <description>Key size selection (AES mode
1518 only)</description>
1519 <bitOffset>8</bitOffset>
1520 <bitWidth>2</bitWidth>
1521 <access>read-write</access>
1522 </field>
1523 <field>
1524 <name>FFLUSH</name>
1525 <description>FIFO flush</description>
1526 <bitOffset>14</bitOffset>
1527 <bitWidth>1</bitWidth>
1528 <access>write-only</access>
1529 </field>
1530 <field>
1531 <name>CRYPEN</name>
1532 <description>Cryptographic processor
1533 enable</description>
1534 <bitOffset>15</bitOffset>
1535 <bitWidth>1</bitWidth>
1536 <access>read-write</access>
1537 </field>
1538 <field>
1539 <name>GCM_CCMPH</name>
1540 <description>GCM_CCMPH</description>
1541 <bitOffset>16</bitOffset>
1542 <bitWidth>2</bitWidth>
1543 <access>read-write</access>
1544 </field>
1545 <field>
1546 <name>ALGOMODE3</name>
1547 <description>ALGOMODE</description>
1548 <bitOffset>19</bitOffset>
1549 <bitWidth>1</bitWidth>
1550 <access>read-write</access>
1551 </field>
1552 </fields>
1553 </register>
1554 <register>
1555 <name>SR</name>
1556 <displayName>SR</displayName>
1557 <description>status register</description>
1558 <addressOffset>0x4</addressOffset>
1559 <size>0x20</size>
1560 <access>read-only</access>
1561 <resetValue>0x00000003</resetValue>
1562 <fields>
1563 <field>
1564 <name>BUSY</name>
1565 <description>Busy bit</description>
1566 <bitOffset>4</bitOffset>
1567 <bitWidth>1</bitWidth>
1568 </field>
1569 <field>
1570 <name>OFFU</name>
1571 <description>Output FIFO full</description>
1572 <bitOffset>3</bitOffset>
1573 <bitWidth>1</bitWidth>
1574 </field>
1575 <field>
1576 <name>OFNE</name>
1577 <description>Output FIFO not empty</description>
1578 <bitOffset>2</bitOffset>
1579 <bitWidth>1</bitWidth>
1580 </field>
1581 <field>
1582 <name>IFNF</name>
1583 <description>Input FIFO not full</description>
1584 <bitOffset>1</bitOffset>
1585 <bitWidth>1</bitWidth>
1586 </field>
1587 <field>
1588 <name>IFEM</name>
1589 <description>Input FIFO empty</description>
1590 <bitOffset>0</bitOffset>
1591 <bitWidth>1</bitWidth>
1592 </field>
1593 </fields>
1594 </register>
1595 <register>
1596 <name>DIN</name>
1597 <displayName>DIN</displayName>
1598 <description>data input register</description>
1599 <addressOffset>0x8</addressOffset>
1600 <size>0x20</size>
1601 <access>read-write</access>
1602 <resetValue>0x00000000</resetValue>
1603 <fields>
1604 <field>
1605 <name>DATAIN</name>
1606 <description>Data input</description>
1607 <bitOffset>0</bitOffset>
1608 <bitWidth>32</bitWidth>
1609 </field>
1610 </fields>
1611 </register>
1612 <register>
1613 <name>DOUT</name>
1614 <displayName>DOUT</displayName>
1615 <description>data output register</description>
1616 <addressOffset>0xC</addressOffset>
1617 <size>0x20</size>
1618 <access>read-only</access>
1619 <resetValue>0x00000000</resetValue>
1620 <fields>
1621 <field>
1622 <name>DATAOUT</name>
1623 <description>Data output</description>
1624 <bitOffset>0</bitOffset>
1625 <bitWidth>32</bitWidth>
1626 </field>
1627 </fields>
1628 </register>
1629 <register>
1630 <name>DMACR</name>
1631 <displayName>DMACR</displayName>
1632 <description>DMA control register</description>
1633 <addressOffset>0x10</addressOffset>
1634 <size>0x20</size>
1635 <access>read-write</access>
1636 <resetValue>0x00000000</resetValue>
1637 <fields>
1638 <field>
1639 <name>DOEN</name>
1640 <description>DMA output enable</description>
1641 <bitOffset>1</bitOffset>
1642 <bitWidth>1</bitWidth>
1643 </field>
1644 <field>
1645 <name>DIEN</name>
1646 <description>DMA input enable</description>
1647 <bitOffset>0</bitOffset>
1648 <bitWidth>1</bitWidth>
1649 </field>
1650 </fields>
1651 </register>
1652 <register>
1653 <name>IMSCR</name>
1654 <displayName>IMSCR</displayName>
1655 <description>interrupt mask set/clear
1656 register</description>
1657 <addressOffset>0x14</addressOffset>
1658 <size>0x20</size>
1659 <access>read-write</access>
1660 <resetValue>0x00000000</resetValue>
1661 <fields>
1662 <field>
1663 <name>OUTIM</name>
1664 <description>Output FIFO service interrupt
1665 mask</description>
1666 <bitOffset>1</bitOffset>
1667 <bitWidth>1</bitWidth>
1668 </field>
1669 <field>
1670 <name>INIM</name>
1671 <description>Input FIFO service interrupt
1672 mask</description>
1673 <bitOffset>0</bitOffset>
1674 <bitWidth>1</bitWidth>
1675 </field>
1676 </fields>
1677 </register>
1678 <register>
1679 <name>RISR</name>
1680 <displayName>RISR</displayName>
1681 <description>raw interrupt status register</description>
1682 <addressOffset>0x18</addressOffset>
1683 <size>0x20</size>
1684 <access>read-only</access>
1685 <resetValue>0x00000001</resetValue>
1686 <fields>
1687 <field>
1688 <name>OUTRIS</name>
1689 <description>Output FIFO service raw interrupt
1690 status</description>
1691 <bitOffset>1</bitOffset>
1692 <bitWidth>1</bitWidth>
1693 </field>
1694 <field>
1695 <name>INRIS</name>
1696 <description>Input FIFO service raw interrupt
1697 status</description>
1698 <bitOffset>0</bitOffset>
1699 <bitWidth>1</bitWidth>
1700 </field>
1701 </fields>
1702 </register>
1703 <register>
1704 <name>MISR</name>
1705 <displayName>MISR</displayName>
1706 <description>masked interrupt status
1707 register</description>
1708 <addressOffset>0x1C</addressOffset>
1709 <size>0x20</size>
1710 <access>read-only</access>
1711 <resetValue>0x00000000</resetValue>
1712 <fields>
1713 <field>
1714 <name>OUTMIS</name>
1715 <description>Output FIFO service masked interrupt
1716 status</description>
1717 <bitOffset>1</bitOffset>
1718 <bitWidth>1</bitWidth>
1719 </field>
1720 <field>
1721 <name>INMIS</name>
1722 <description>Input FIFO service masked interrupt
1723 status</description>
1724 <bitOffset>0</bitOffset>
1725 <bitWidth>1</bitWidth>
1726 </field>
1727 </fields>
1728 </register>
1729 <register>
1730 <name>K0LR</name>
1731 <displayName>K0LR</displayName>
1732 <description>key registers</description>
1733 <addressOffset>0x20</addressOffset>
1734 <size>0x20</size>
1735 <access>write-only</access>
1736 <resetValue>0x00000000</resetValue>
1737 <fields>
1738 <field>
1739 <name>b224</name>
1740 <description>b224</description>
1741 <bitOffset>0</bitOffset>
1742 <bitWidth>1</bitWidth>
1743 </field>
1744 <field>
1745 <name>b225</name>
1746 <description>b225</description>
1747 <bitOffset>1</bitOffset>
1748 <bitWidth>1</bitWidth>
1749 </field>
1750 <field>
1751 <name>b226</name>
1752 <description>b226</description>
1753 <bitOffset>2</bitOffset>
1754 <bitWidth>1</bitWidth>
1755 </field>
1756 <field>
1757 <name>b227</name>
1758 <description>b227</description>
1759 <bitOffset>3</bitOffset>
1760 <bitWidth>1</bitWidth>
1761 </field>
1762 <field>
1763 <name>b228</name>
1764 <description>b228</description>
1765 <bitOffset>4</bitOffset>
1766 <bitWidth>1</bitWidth>
1767 </field>
1768 <field>
1769 <name>b229</name>
1770 <description>b229</description>
1771 <bitOffset>5</bitOffset>
1772 <bitWidth>1</bitWidth>
1773 </field>
1774 <field>
1775 <name>b230</name>
1776 <description>b230</description>
1777 <bitOffset>6</bitOffset>
1778 <bitWidth>1</bitWidth>
1779 </field>
1780 <field>
1781 <name>b231</name>
1782 <description>b231</description>
1783 <bitOffset>7</bitOffset>
1784 <bitWidth>1</bitWidth>
1785 </field>
1786 <field>
1787 <name>b232</name>
1788 <description>b232</description>
1789 <bitOffset>8</bitOffset>
1790 <bitWidth>1</bitWidth>
1791 </field>
1792 <field>
1793 <name>b233</name>
1794 <description>b233</description>
1795 <bitOffset>9</bitOffset>
1796 <bitWidth>1</bitWidth>
1797 </field>
1798 <field>
1799 <name>b234</name>
1800 <description>b234</description>
1801 <bitOffset>10</bitOffset>
1802 <bitWidth>1</bitWidth>
1803 </field>
1804 <field>
1805 <name>b235</name>
1806 <description>b235</description>
1807 <bitOffset>11</bitOffset>
1808 <bitWidth>1</bitWidth>
1809 </field>
1810 <field>
1811 <name>b236</name>
1812 <description>b236</description>
1813 <bitOffset>12</bitOffset>
1814 <bitWidth>1</bitWidth>
1815 </field>
1816 <field>
1817 <name>b237</name>
1818 <description>b237</description>
1819 <bitOffset>13</bitOffset>
1820 <bitWidth>1</bitWidth>
1821 </field>
1822 <field>
1823 <name>b238</name>
1824 <description>b238</description>
1825 <bitOffset>14</bitOffset>
1826 <bitWidth>1</bitWidth>
1827 </field>
1828 <field>
1829 <name>b239</name>
1830 <description>b239</description>
1831 <bitOffset>15</bitOffset>
1832 <bitWidth>1</bitWidth>
1833 </field>
1834 <field>
1835 <name>b240</name>
1836 <description>b240</description>
1837 <bitOffset>16</bitOffset>
1838 <bitWidth>1</bitWidth>
1839 </field>
1840 <field>
1841 <name>b241</name>
1842 <description>b241</description>
1843 <bitOffset>17</bitOffset>
1844 <bitWidth>1</bitWidth>
1845 </field>
1846 <field>
1847 <name>b242</name>
1848 <description>b242</description>
1849 <bitOffset>18</bitOffset>
1850 <bitWidth>1</bitWidth>
1851 </field>
1852 <field>
1853 <name>b243</name>
1854 <description>b243</description>
1855 <bitOffset>19</bitOffset>
1856 <bitWidth>1</bitWidth>
1857 </field>
1858 <field>
1859 <name>b244</name>
1860 <description>b244</description>
1861 <bitOffset>20</bitOffset>
1862 <bitWidth>1</bitWidth>
1863 </field>
1864 <field>
1865 <name>b245</name>
1866 <description>b245</description>
1867 <bitOffset>21</bitOffset>
1868 <bitWidth>1</bitWidth>
1869 </field>
1870 <field>
1871 <name>b246</name>
1872 <description>b246</description>
1873 <bitOffset>22</bitOffset>
1874 <bitWidth>1</bitWidth>
1875 </field>
1876 <field>
1877 <name>b247</name>
1878 <description>b247</description>
1879 <bitOffset>23</bitOffset>
1880 <bitWidth>1</bitWidth>
1881 </field>
1882 <field>
1883 <name>b248</name>
1884 <description>b248</description>
1885 <bitOffset>24</bitOffset>
1886 <bitWidth>1</bitWidth>
1887 </field>
1888 <field>
1889 <name>b249</name>
1890 <description>b249</description>
1891 <bitOffset>25</bitOffset>
1892 <bitWidth>1</bitWidth>
1893 </field>
1894 <field>
1895 <name>b250</name>
1896 <description>b250</description>
1897 <bitOffset>26</bitOffset>
1898 <bitWidth>1</bitWidth>
1899 </field>
1900 <field>
1901 <name>b251</name>
1902 <description>b251</description>
1903 <bitOffset>27</bitOffset>
1904 <bitWidth>1</bitWidth>
1905 </field>
1906 <field>
1907 <name>b252</name>
1908 <description>b252</description>
1909 <bitOffset>28</bitOffset>
1910 <bitWidth>1</bitWidth>
1911 </field>
1912 <field>
1913 <name>b253</name>
1914 <description>b253</description>
1915 <bitOffset>29</bitOffset>
1916 <bitWidth>1</bitWidth>
1917 </field>
1918 <field>
1919 <name>b254</name>
1920 <description>b254</description>
1921 <bitOffset>30</bitOffset>
1922 <bitWidth>1</bitWidth>
1923 </field>
1924 <field>
1925 <name>b255</name>
1926 <description>b255</description>
1927 <bitOffset>31</bitOffset>
1928 <bitWidth>1</bitWidth>
1929 </field>
1930 </fields>
1931 </register>
1932 <register>
1933 <name>K0RR</name>
1934 <displayName>K0RR</displayName>
1935 <description>key registers</description>
1936 <addressOffset>0x24</addressOffset>
1937 <size>0x20</size>
1938 <access>write-only</access>
1939 <resetValue>0x00000000</resetValue>
1940 <fields>
1941 <field>
1942 <name>b192</name>
1943 <description>b192</description>
1944 <bitOffset>0</bitOffset>
1945 <bitWidth>1</bitWidth>
1946 </field>
1947 <field>
1948 <name>b193</name>
1949 <description>b193</description>
1950 <bitOffset>1</bitOffset>
1951 <bitWidth>1</bitWidth>
1952 </field>
1953 <field>
1954 <name>b194</name>
1955 <description>b194</description>
1956 <bitOffset>2</bitOffset>
1957 <bitWidth>1</bitWidth>
1958 </field>
1959 <field>
1960 <name>b195</name>
1961 <description>b195</description>
1962 <bitOffset>3</bitOffset>
1963 <bitWidth>1</bitWidth>
1964 </field>
1965 <field>
1966 <name>b196</name>
1967 <description>b196</description>
1968 <bitOffset>4</bitOffset>
1969 <bitWidth>1</bitWidth>
1970 </field>
1971 <field>
1972 <name>b197</name>
1973 <description>b197</description>
1974 <bitOffset>5</bitOffset>
1975 <bitWidth>1</bitWidth>
1976 </field>
1977 <field>
1978 <name>b198</name>
1979 <description>b198</description>
1980 <bitOffset>6</bitOffset>
1981 <bitWidth>1</bitWidth>
1982 </field>
1983 <field>
1984 <name>b199</name>
1985 <description>b199</description>
1986 <bitOffset>7</bitOffset>
1987 <bitWidth>1</bitWidth>
1988 </field>
1989 <field>
1990 <name>b200</name>
1991 <description>b200</description>
1992 <bitOffset>8</bitOffset>
1993 <bitWidth>1</bitWidth>
1994 </field>
1995 <field>
1996 <name>b201</name>
1997 <description>b201</description>
1998 <bitOffset>9</bitOffset>
1999 <bitWidth>1</bitWidth>
2000 </field>
2001 <field>
2002 <name>b202</name>
2003 <description>b202</description>
2004 <bitOffset>10</bitOffset>
2005 <bitWidth>1</bitWidth>
2006 </field>
2007 <field>
2008 <name>b203</name>
2009 <description>b203</description>
2010 <bitOffset>11</bitOffset>
2011 <bitWidth>1</bitWidth>
2012 </field>
2013 <field>
2014 <name>b204</name>
2015 <description>b204</description>
2016 <bitOffset>12</bitOffset>
2017 <bitWidth>1</bitWidth>
2018 </field>
2019 <field>
2020 <name>b205</name>
2021 <description>b205</description>
2022 <bitOffset>13</bitOffset>
2023 <bitWidth>1</bitWidth>
2024 </field>
2025 <field>
2026 <name>b206</name>
2027 <description>b206</description>
2028 <bitOffset>14</bitOffset>
2029 <bitWidth>1</bitWidth>
2030 </field>
2031 <field>
2032 <name>b207</name>
2033 <description>b207</description>
2034 <bitOffset>15</bitOffset>
2035 <bitWidth>1</bitWidth>
2036 </field>
2037 <field>
2038 <name>b208</name>
2039 <description>b208</description>
2040 <bitOffset>16</bitOffset>
2041 <bitWidth>1</bitWidth>
2042 </field>
2043 <field>
2044 <name>b209</name>
2045 <description>b209</description>
2046 <bitOffset>17</bitOffset>
2047 <bitWidth>1</bitWidth>
2048 </field>
2049 <field>
2050 <name>b210</name>
2051 <description>b210</description>
2052 <bitOffset>18</bitOffset>
2053 <bitWidth>1</bitWidth>
2054 </field>
2055 <field>
2056 <name>b211</name>
2057 <description>b211</description>
2058 <bitOffset>19</bitOffset>
2059 <bitWidth>1</bitWidth>
2060 </field>
2061 <field>
2062 <name>b212</name>
2063 <description>b212</description>
2064 <bitOffset>20</bitOffset>
2065 <bitWidth>1</bitWidth>
2066 </field>
2067 <field>
2068 <name>b213</name>
2069 <description>b213</description>
2070 <bitOffset>21</bitOffset>
2071 <bitWidth>1</bitWidth>
2072 </field>
2073 <field>
2074 <name>b214</name>
2075 <description>b214</description>
2076 <bitOffset>22</bitOffset>
2077 <bitWidth>1</bitWidth>
2078 </field>
2079 <field>
2080 <name>b215</name>
2081 <description>b215</description>
2082 <bitOffset>23</bitOffset>
2083 <bitWidth>1</bitWidth>
2084 </field>
2085 <field>
2086 <name>b216</name>
2087 <description>b216</description>
2088 <bitOffset>24</bitOffset>
2089 <bitWidth>1</bitWidth>
2090 </field>
2091 <field>
2092 <name>b217</name>
2093 <description>b217</description>
2094 <bitOffset>25</bitOffset>
2095 <bitWidth>1</bitWidth>
2096 </field>
2097 <field>
2098 <name>b218</name>
2099 <description>b218</description>
2100 <bitOffset>26</bitOffset>
2101 <bitWidth>1</bitWidth>
2102 </field>
2103 <field>
2104 <name>b219</name>
2105 <description>b219</description>
2106 <bitOffset>27</bitOffset>
2107 <bitWidth>1</bitWidth>
2108 </field>
2109 <field>
2110 <name>b220</name>
2111 <description>b220</description>
2112 <bitOffset>28</bitOffset>
2113 <bitWidth>1</bitWidth>
2114 </field>
2115 <field>
2116 <name>b221</name>
2117 <description>b221</description>
2118 <bitOffset>29</bitOffset>
2119 <bitWidth>1</bitWidth>
2120 </field>
2121 <field>
2122 <name>b222</name>
2123 <description>b222</description>
2124 <bitOffset>30</bitOffset>
2125 <bitWidth>1</bitWidth>
2126 </field>
2127 <field>
2128 <name>b223</name>
2129 <description>b223</description>
2130 <bitOffset>31</bitOffset>
2131 <bitWidth>1</bitWidth>
2132 </field>
2133 </fields>
2134 </register>
2135 <register>
2136 <name>K1LR</name>
2137 <displayName>K1LR</displayName>
2138 <description>key registers</description>
2139 <addressOffset>0x28</addressOffset>
2140 <size>0x20</size>
2141 <access>write-only</access>
2142 <resetValue>0x00000000</resetValue>
2143 <fields>
2144 <field>
2145 <name>b160</name>
2146 <description>b160</description>
2147 <bitOffset>0</bitOffset>
2148 <bitWidth>1</bitWidth>
2149 </field>
2150 <field>
2151 <name>b161</name>
2152 <description>b161</description>
2153 <bitOffset>1</bitOffset>
2154 <bitWidth>1</bitWidth>
2155 </field>
2156 <field>
2157 <name>b162</name>
2158 <description>b162</description>
2159 <bitOffset>2</bitOffset>
2160 <bitWidth>1</bitWidth>
2161 </field>
2162 <field>
2163 <name>b163</name>
2164 <description>b163</description>
2165 <bitOffset>3</bitOffset>
2166 <bitWidth>1</bitWidth>
2167 </field>
2168 <field>
2169 <name>b164</name>
2170 <description>b164</description>
2171 <bitOffset>4</bitOffset>
2172 <bitWidth>1</bitWidth>
2173 </field>
2174 <field>
2175 <name>b165</name>
2176 <description>b165</description>
2177 <bitOffset>5</bitOffset>
2178 <bitWidth>1</bitWidth>
2179 </field>
2180 <field>
2181 <name>b166</name>
2182 <description>b166</description>
2183 <bitOffset>6</bitOffset>
2184 <bitWidth>1</bitWidth>
2185 </field>
2186 <field>
2187 <name>b167</name>
2188 <description>b167</description>
2189 <bitOffset>7</bitOffset>
2190 <bitWidth>1</bitWidth>
2191 </field>
2192 <field>
2193 <name>b168</name>
2194 <description>b168</description>
2195 <bitOffset>8</bitOffset>
2196 <bitWidth>1</bitWidth>
2197 </field>
2198 <field>
2199 <name>b169</name>
2200 <description>b169</description>
2201 <bitOffset>9</bitOffset>
2202 <bitWidth>1</bitWidth>
2203 </field>
2204 <field>
2205 <name>b170</name>
2206 <description>b170</description>
2207 <bitOffset>10</bitOffset>
2208 <bitWidth>1</bitWidth>
2209 </field>
2210 <field>
2211 <name>b171</name>
2212 <description>b171</description>
2213 <bitOffset>11</bitOffset>
2214 <bitWidth>1</bitWidth>
2215 </field>
2216 <field>
2217 <name>b172</name>
2218 <description>b172</description>
2219 <bitOffset>12</bitOffset>
2220 <bitWidth>1</bitWidth>
2221 </field>
2222 <field>
2223 <name>b173</name>
2224 <description>b173</description>
2225 <bitOffset>13</bitOffset>
2226 <bitWidth>1</bitWidth>
2227 </field>
2228 <field>
2229 <name>b174</name>
2230 <description>b174</description>
2231 <bitOffset>14</bitOffset>
2232 <bitWidth>1</bitWidth>
2233 </field>
2234 <field>
2235 <name>b175</name>
2236 <description>b175</description>
2237 <bitOffset>15</bitOffset>
2238 <bitWidth>1</bitWidth>
2239 </field>
2240 <field>
2241 <name>b176</name>
2242 <description>b176</description>
2243 <bitOffset>16</bitOffset>
2244 <bitWidth>1</bitWidth>
2245 </field>
2246 <field>
2247 <name>b177</name>
2248 <description>b177</description>
2249 <bitOffset>17</bitOffset>
2250 <bitWidth>1</bitWidth>
2251 </field>
2252 <field>
2253 <name>b178</name>
2254 <description>b178</description>
2255 <bitOffset>18</bitOffset>
2256 <bitWidth>1</bitWidth>
2257 </field>
2258 <field>
2259 <name>b179</name>
2260 <description>b179</description>
2261 <bitOffset>19</bitOffset>
2262 <bitWidth>1</bitWidth>
2263 </field>
2264 <field>
2265 <name>b180</name>
2266 <description>b180</description>
2267 <bitOffset>20</bitOffset>
2268 <bitWidth>1</bitWidth>
2269 </field>
2270 <field>
2271 <name>b181</name>
2272 <description>b181</description>
2273 <bitOffset>21</bitOffset>
2274 <bitWidth>1</bitWidth>
2275 </field>
2276 <field>
2277 <name>b182</name>
2278 <description>b182</description>
2279 <bitOffset>22</bitOffset>
2280 <bitWidth>1</bitWidth>
2281 </field>
2282 <field>
2283 <name>b183</name>
2284 <description>b183</description>
2285 <bitOffset>23</bitOffset>
2286 <bitWidth>1</bitWidth>
2287 </field>
2288 <field>
2289 <name>b184</name>
2290 <description>b184</description>
2291 <bitOffset>24</bitOffset>
2292 <bitWidth>1</bitWidth>
2293 </field>
2294 <field>
2295 <name>b185</name>
2296 <description>b185</description>
2297 <bitOffset>25</bitOffset>
2298 <bitWidth>1</bitWidth>
2299 </field>
2300 <field>
2301 <name>b186</name>
2302 <description>b186</description>
2303 <bitOffset>26</bitOffset>
2304 <bitWidth>1</bitWidth>
2305 </field>
2306 <field>
2307 <name>b187</name>
2308 <description>b187</description>
2309 <bitOffset>27</bitOffset>
2310 <bitWidth>1</bitWidth>
2311 </field>
2312 <field>
2313 <name>b188</name>
2314 <description>b188</description>
2315 <bitOffset>28</bitOffset>
2316 <bitWidth>1</bitWidth>
2317 </field>
2318 <field>
2319 <name>b189</name>
2320 <description>b189</description>
2321 <bitOffset>29</bitOffset>
2322 <bitWidth>1</bitWidth>
2323 </field>
2324 <field>
2325 <name>b190</name>
2326 <description>b190</description>
2327 <bitOffset>30</bitOffset>
2328 <bitWidth>1</bitWidth>
2329 </field>
2330 <field>
2331 <name>b191</name>
2332 <description>b191</description>
2333 <bitOffset>31</bitOffset>
2334 <bitWidth>1</bitWidth>
2335 </field>
2336 </fields>
2337 </register>
2338 <register>
2339 <name>K1RR</name>
2340 <displayName>K1RR</displayName>
2341 <description>key registers</description>
2342 <addressOffset>0x2C</addressOffset>
2343 <size>0x20</size>
2344 <access>write-only</access>
2345 <resetValue>0x00000000</resetValue>
2346 <fields>
2347 <field>
2348 <name>b128</name>
2349 <description>b128</description>
2350 <bitOffset>0</bitOffset>
2351 <bitWidth>1</bitWidth>
2352 </field>
2353 <field>
2354 <name>b129</name>
2355 <description>b129</description>
2356 <bitOffset>1</bitOffset>
2357 <bitWidth>1</bitWidth>
2358 </field>
2359 <field>
2360 <name>b130</name>
2361 <description>b130</description>
2362 <bitOffset>2</bitOffset>
2363 <bitWidth>1</bitWidth>
2364 </field>
2365 <field>
2366 <name>b131</name>
2367 <description>b131</description>
2368 <bitOffset>3</bitOffset>
2369 <bitWidth>1</bitWidth>
2370 </field>
2371 <field>
2372 <name>b132</name>
2373 <description>b132</description>
2374 <bitOffset>4</bitOffset>
2375 <bitWidth>1</bitWidth>
2376 </field>
2377 <field>
2378 <name>b133</name>
2379 <description>b133</description>
2380 <bitOffset>5</bitOffset>
2381 <bitWidth>1</bitWidth>
2382 </field>
2383 <field>
2384 <name>b134</name>
2385 <description>b134</description>
2386 <bitOffset>6</bitOffset>
2387 <bitWidth>1</bitWidth>
2388 </field>
2389 <field>
2390 <name>b135</name>
2391 <description>b135</description>
2392 <bitOffset>7</bitOffset>
2393 <bitWidth>1</bitWidth>
2394 </field>
2395 <field>
2396 <name>b136</name>
2397 <description>b136</description>
2398 <bitOffset>8</bitOffset>
2399 <bitWidth>1</bitWidth>
2400 </field>
2401 <field>
2402 <name>b137</name>
2403 <description>b137</description>
2404 <bitOffset>9</bitOffset>
2405 <bitWidth>1</bitWidth>
2406 </field>
2407 <field>
2408 <name>b138</name>
2409 <description>b138</description>
2410 <bitOffset>10</bitOffset>
2411 <bitWidth>1</bitWidth>
2412 </field>
2413 <field>
2414 <name>b139</name>
2415 <description>b139</description>
2416 <bitOffset>11</bitOffset>
2417 <bitWidth>1</bitWidth>
2418 </field>
2419 <field>
2420 <name>b140</name>
2421 <description>b140</description>
2422 <bitOffset>12</bitOffset>
2423 <bitWidth>1</bitWidth>
2424 </field>
2425 <field>
2426 <name>b141</name>
2427 <description>b141</description>
2428 <bitOffset>13</bitOffset>
2429 <bitWidth>1</bitWidth>
2430 </field>
2431 <field>
2432 <name>b142</name>
2433 <description>b142</description>
2434 <bitOffset>14</bitOffset>
2435 <bitWidth>1</bitWidth>
2436 </field>
2437 <field>
2438 <name>b143</name>
2439 <description>b143</description>
2440 <bitOffset>15</bitOffset>
2441 <bitWidth>1</bitWidth>
2442 </field>
2443 <field>
2444 <name>b144</name>
2445 <description>b144</description>
2446 <bitOffset>16</bitOffset>
2447 <bitWidth>1</bitWidth>
2448 </field>
2449 <field>
2450 <name>b145</name>
2451 <description>b145</description>
2452 <bitOffset>17</bitOffset>
2453 <bitWidth>1</bitWidth>
2454 </field>
2455 <field>
2456 <name>b146</name>
2457 <description>b146</description>
2458 <bitOffset>18</bitOffset>
2459 <bitWidth>1</bitWidth>
2460 </field>
2461 <field>
2462 <name>b147</name>
2463 <description>b147</description>
2464 <bitOffset>19</bitOffset>
2465 <bitWidth>1</bitWidth>
2466 </field>
2467 <field>
2468 <name>b148</name>
2469 <description>b148</description>
2470 <bitOffset>20</bitOffset>
2471 <bitWidth>1</bitWidth>
2472 </field>
2473 <field>
2474 <name>b149</name>
2475 <description>b149</description>
2476 <bitOffset>21</bitOffset>
2477 <bitWidth>1</bitWidth>
2478 </field>
2479 <field>
2480 <name>b150</name>
2481 <description>b150</description>
2482 <bitOffset>22</bitOffset>
2483 <bitWidth>1</bitWidth>
2484 </field>
2485 <field>
2486 <name>b151</name>
2487 <description>b151</description>
2488 <bitOffset>23</bitOffset>
2489 <bitWidth>1</bitWidth>
2490 </field>
2491 <field>
2492 <name>b152</name>
2493 <description>b152</description>
2494 <bitOffset>24</bitOffset>
2495 <bitWidth>1</bitWidth>
2496 </field>
2497 <field>
2498 <name>b153</name>
2499 <description>b153</description>
2500 <bitOffset>25</bitOffset>
2501 <bitWidth>1</bitWidth>
2502 </field>
2503 <field>
2504 <name>b154</name>
2505 <description>b154</description>
2506 <bitOffset>26</bitOffset>
2507 <bitWidth>1</bitWidth>
2508 </field>
2509 <field>
2510 <name>b155</name>
2511 <description>b155</description>
2512 <bitOffset>27</bitOffset>
2513 <bitWidth>1</bitWidth>
2514 </field>
2515 <field>
2516 <name>b156</name>
2517 <description>b156</description>
2518 <bitOffset>28</bitOffset>
2519 <bitWidth>1</bitWidth>
2520 </field>
2521 <field>
2522 <name>b157</name>
2523 <description>b157</description>
2524 <bitOffset>29</bitOffset>
2525 <bitWidth>1</bitWidth>
2526 </field>
2527 <field>
2528 <name>b158</name>
2529 <description>b158</description>
2530 <bitOffset>30</bitOffset>
2531 <bitWidth>1</bitWidth>
2532 </field>
2533 <field>
2534 <name>b159</name>
2535 <description>b159</description>
2536 <bitOffset>31</bitOffset>
2537 <bitWidth>1</bitWidth>
2538 </field>
2539 </fields>
2540 </register>
2541 <register>
2542 <name>K2LR</name>
2543 <displayName>K2LR</displayName>
2544 <description>key registers</description>
2545 <addressOffset>0x30</addressOffset>
2546 <size>0x20</size>
2547 <access>write-only</access>
2548 <resetValue>0x00000000</resetValue>
2549 <fields>
2550 <field>
2551 <name>b96</name>
2552 <description>b96</description>
2553 <bitOffset>0</bitOffset>
2554 <bitWidth>1</bitWidth>
2555 </field>
2556 <field>
2557 <name>b97</name>
2558 <description>b97</description>
2559 <bitOffset>1</bitOffset>
2560 <bitWidth>1</bitWidth>
2561 </field>
2562 <field>
2563 <name>b98</name>
2564 <description>b98</description>
2565 <bitOffset>2</bitOffset>
2566 <bitWidth>1</bitWidth>
2567 </field>
2568 <field>
2569 <name>b99</name>
2570 <description>b99</description>
2571 <bitOffset>3</bitOffset>
2572 <bitWidth>1</bitWidth>
2573 </field>
2574 <field>
2575 <name>b100</name>
2576 <description>b100</description>
2577 <bitOffset>4</bitOffset>
2578 <bitWidth>1</bitWidth>
2579 </field>
2580 <field>
2581 <name>b101</name>
2582 <description>b101</description>
2583 <bitOffset>5</bitOffset>
2584 <bitWidth>1</bitWidth>
2585 </field>
2586 <field>
2587 <name>b102</name>
2588 <description>b102</description>
2589 <bitOffset>6</bitOffset>
2590 <bitWidth>1</bitWidth>
2591 </field>
2592 <field>
2593 <name>b103</name>
2594 <description>b103</description>
2595 <bitOffset>7</bitOffset>
2596 <bitWidth>1</bitWidth>
2597 </field>
2598 <field>
2599 <name>b104</name>
2600 <description>b104</description>
2601 <bitOffset>8</bitOffset>
2602 <bitWidth>1</bitWidth>
2603 </field>
2604 <field>
2605 <name>b105</name>
2606 <description>b105</description>
2607 <bitOffset>9</bitOffset>
2608 <bitWidth>1</bitWidth>
2609 </field>
2610 <field>
2611 <name>b106</name>
2612 <description>b106</description>
2613 <bitOffset>10</bitOffset>
2614 <bitWidth>1</bitWidth>
2615 </field>
2616 <field>
2617 <name>b107</name>
2618 <description>b107</description>
2619 <bitOffset>11</bitOffset>
2620 <bitWidth>1</bitWidth>
2621 </field>
2622 <field>
2623 <name>b108</name>
2624 <description>b108</description>
2625 <bitOffset>12</bitOffset>
2626 <bitWidth>1</bitWidth>
2627 </field>
2628 <field>
2629 <name>b109</name>
2630 <description>b109</description>
2631 <bitOffset>13</bitOffset>
2632 <bitWidth>1</bitWidth>
2633 </field>
2634 <field>
2635 <name>b110</name>
2636 <description>b110</description>
2637 <bitOffset>14</bitOffset>
2638 <bitWidth>1</bitWidth>
2639 </field>
2640 <field>
2641 <name>b111</name>
2642 <description>b111</description>
2643 <bitOffset>15</bitOffset>
2644 <bitWidth>1</bitWidth>
2645 </field>
2646 <field>
2647 <name>b112</name>
2648 <description>b112</description>
2649 <bitOffset>16</bitOffset>
2650 <bitWidth>1</bitWidth>
2651 </field>
2652 <field>
2653 <name>b113</name>
2654 <description>b113</description>
2655 <bitOffset>17</bitOffset>
2656 <bitWidth>1</bitWidth>
2657 </field>
2658 <field>
2659 <name>b114</name>
2660 <description>b114</description>
2661 <bitOffset>18</bitOffset>
2662 <bitWidth>1</bitWidth>
2663 </field>
2664 <field>
2665 <name>b115</name>
2666 <description>b115</description>
2667 <bitOffset>19</bitOffset>
2668 <bitWidth>1</bitWidth>
2669 </field>
2670 <field>
2671 <name>b116</name>
2672 <description>b116</description>
2673 <bitOffset>20</bitOffset>
2674 <bitWidth>1</bitWidth>
2675 </field>
2676 <field>
2677 <name>b117</name>
2678 <description>b117</description>
2679 <bitOffset>21</bitOffset>
2680 <bitWidth>1</bitWidth>
2681 </field>
2682 <field>
2683 <name>b118</name>
2684 <description>b118</description>
2685 <bitOffset>22</bitOffset>
2686 <bitWidth>1</bitWidth>
2687 </field>
2688 <field>
2689 <name>b119</name>
2690 <description>b119</description>
2691 <bitOffset>23</bitOffset>
2692 <bitWidth>1</bitWidth>
2693 </field>
2694 <field>
2695 <name>b120</name>
2696 <description>b120</description>
2697 <bitOffset>24</bitOffset>
2698 <bitWidth>1</bitWidth>
2699 </field>
2700 <field>
2701 <name>b121</name>
2702 <description>b121</description>
2703 <bitOffset>25</bitOffset>
2704 <bitWidth>1</bitWidth>
2705 </field>
2706 <field>
2707 <name>b122</name>
2708 <description>b122</description>
2709 <bitOffset>26</bitOffset>
2710 <bitWidth>1</bitWidth>
2711 </field>
2712 <field>
2713 <name>b123</name>
2714 <description>b123</description>
2715 <bitOffset>27</bitOffset>
2716 <bitWidth>1</bitWidth>
2717 </field>
2718 <field>
2719 <name>b124</name>
2720 <description>b124</description>
2721 <bitOffset>28</bitOffset>
2722 <bitWidth>1</bitWidth>
2723 </field>
2724 <field>
2725 <name>b125</name>
2726 <description>b125</description>
2727 <bitOffset>29</bitOffset>
2728 <bitWidth>1</bitWidth>
2729 </field>
2730 <field>
2731 <name>b126</name>
2732 <description>b126</description>
2733 <bitOffset>30</bitOffset>
2734 <bitWidth>1</bitWidth>
2735 </field>
2736 <field>
2737 <name>b127</name>
2738 <description>b127</description>
2739 <bitOffset>31</bitOffset>
2740 <bitWidth>1</bitWidth>
2741 </field>
2742 </fields>
2743 </register>
2744 <register>
2745 <name>K2RR</name>
2746 <displayName>K2RR</displayName>
2747 <description>key registers</description>
2748 <addressOffset>0x34</addressOffset>
2749 <size>0x20</size>
2750 <access>write-only</access>
2751 <resetValue>0x00000000</resetValue>
2752 <fields>
2753 <field>
2754 <name>b64</name>
2755 <description>b64</description>
2756 <bitOffset>0</bitOffset>
2757 <bitWidth>1</bitWidth>
2758 </field>
2759 <field>
2760 <name>b65</name>
2761 <description>b65</description>
2762 <bitOffset>1</bitOffset>
2763 <bitWidth>1</bitWidth>
2764 </field>
2765 <field>
2766 <name>b66</name>
2767 <description>b66</description>
2768 <bitOffset>2</bitOffset>
2769 <bitWidth>1</bitWidth>
2770 </field>
2771 <field>
2772 <name>b67</name>
2773 <description>b67</description>
2774 <bitOffset>3</bitOffset>
2775 <bitWidth>1</bitWidth>
2776 </field>
2777 <field>
2778 <name>b68</name>
2779 <description>b68</description>
2780 <bitOffset>4</bitOffset>
2781 <bitWidth>1</bitWidth>
2782 </field>
2783 <field>
2784 <name>b69</name>
2785 <description>b69</description>
2786 <bitOffset>5</bitOffset>
2787 <bitWidth>1</bitWidth>
2788 </field>
2789 <field>
2790 <name>b70</name>
2791 <description>b70</description>
2792 <bitOffset>6</bitOffset>
2793 <bitWidth>1</bitWidth>
2794 </field>
2795 <field>
2796 <name>b71</name>
2797 <description>b71</description>
2798 <bitOffset>7</bitOffset>
2799 <bitWidth>1</bitWidth>
2800 </field>
2801 <field>
2802 <name>b72</name>
2803 <description>b72</description>
2804 <bitOffset>8</bitOffset>
2805 <bitWidth>1</bitWidth>
2806 </field>
2807 <field>
2808 <name>b73</name>
2809 <description>b73</description>
2810 <bitOffset>9</bitOffset>
2811 <bitWidth>1</bitWidth>
2812 </field>
2813 <field>
2814 <name>b74</name>
2815 <description>b74</description>
2816 <bitOffset>10</bitOffset>
2817 <bitWidth>1</bitWidth>
2818 </field>
2819 <field>
2820 <name>b75</name>
2821 <description>b75</description>
2822 <bitOffset>11</bitOffset>
2823 <bitWidth>1</bitWidth>
2824 </field>
2825 <field>
2826 <name>b76</name>
2827 <description>b76</description>
2828 <bitOffset>12</bitOffset>
2829 <bitWidth>1</bitWidth>
2830 </field>
2831 <field>
2832 <name>b77</name>
2833 <description>b77</description>
2834 <bitOffset>13</bitOffset>
2835 <bitWidth>1</bitWidth>
2836 </field>
2837 <field>
2838 <name>b78</name>
2839 <description>b78</description>
2840 <bitOffset>14</bitOffset>
2841 <bitWidth>1</bitWidth>
2842 </field>
2843 <field>
2844 <name>b79</name>
2845 <description>b79</description>
2846 <bitOffset>15</bitOffset>
2847 <bitWidth>1</bitWidth>
2848 </field>
2849 <field>
2850 <name>b80</name>
2851 <description>b80</description>
2852 <bitOffset>16</bitOffset>
2853 <bitWidth>1</bitWidth>
2854 </field>
2855 <field>
2856 <name>b81</name>
2857 <description>b81</description>
2858 <bitOffset>17</bitOffset>
2859 <bitWidth>1</bitWidth>
2860 </field>
2861 <field>
2862 <name>b82</name>
2863 <description>b82</description>
2864 <bitOffset>18</bitOffset>
2865 <bitWidth>1</bitWidth>
2866 </field>
2867 <field>
2868 <name>b83</name>
2869 <description>b83</description>
2870 <bitOffset>19</bitOffset>
2871 <bitWidth>1</bitWidth>
2872 </field>
2873 <field>
2874 <name>b84</name>
2875 <description>b84</description>
2876 <bitOffset>20</bitOffset>
2877 <bitWidth>1</bitWidth>
2878 </field>
2879 <field>
2880 <name>b85</name>
2881 <description>b85</description>
2882 <bitOffset>21</bitOffset>
2883 <bitWidth>1</bitWidth>
2884 </field>
2885 <field>
2886 <name>b86</name>
2887 <description>b86</description>
2888 <bitOffset>22</bitOffset>
2889 <bitWidth>1</bitWidth>
2890 </field>
2891 <field>
2892 <name>b87</name>
2893 <description>b87</description>
2894 <bitOffset>23</bitOffset>
2895 <bitWidth>1</bitWidth>
2896 </field>
2897 <field>
2898 <name>b88</name>
2899 <description>b88</description>
2900 <bitOffset>24</bitOffset>
2901 <bitWidth>1</bitWidth>
2902 </field>
2903 <field>
2904 <name>b89</name>
2905 <description>b89</description>
2906 <bitOffset>25</bitOffset>
2907 <bitWidth>1</bitWidth>
2908 </field>
2909 <field>
2910 <name>b90</name>
2911 <description>b90</description>
2912 <bitOffset>26</bitOffset>
2913 <bitWidth>1</bitWidth>
2914 </field>
2915 <field>
2916 <name>b91</name>
2917 <description>b91</description>
2918 <bitOffset>27</bitOffset>
2919 <bitWidth>1</bitWidth>
2920 </field>
2921 <field>
2922 <name>b92</name>
2923 <description>b92</description>
2924 <bitOffset>28</bitOffset>
2925 <bitWidth>1</bitWidth>
2926 </field>
2927 <field>
2928 <name>b93</name>
2929 <description>b93</description>
2930 <bitOffset>29</bitOffset>
2931 <bitWidth>1</bitWidth>
2932 </field>
2933 <field>
2934 <name>b94</name>
2935 <description>b94</description>
2936 <bitOffset>30</bitOffset>
2937 <bitWidth>1</bitWidth>
2938 </field>
2939 <field>
2940 <name>b95</name>
2941 <description>b95</description>
2942 <bitOffset>31</bitOffset>
2943 <bitWidth>1</bitWidth>
2944 </field>
2945 </fields>
2946 </register>
2947 <register>
2948 <name>K3LR</name>
2949 <displayName>K3LR</displayName>
2950 <description>key registers</description>
2951 <addressOffset>0x38</addressOffset>
2952 <size>0x20</size>
2953 <access>write-only</access>
2954 <resetValue>0x00000000</resetValue>
2955 <fields>
2956 <field>
2957 <name>b32</name>
2958 <description>b32</description>
2959 <bitOffset>0</bitOffset>
2960 <bitWidth>1</bitWidth>
2961 </field>
2962 <field>
2963 <name>b33</name>
2964 <description>b33</description>
2965 <bitOffset>1</bitOffset>
2966 <bitWidth>1</bitWidth>
2967 </field>
2968 <field>
2969 <name>b34</name>
2970 <description>b34</description>
2971 <bitOffset>2</bitOffset>
2972 <bitWidth>1</bitWidth>
2973 </field>
2974 <field>
2975 <name>b35</name>
2976 <description>b35</description>
2977 <bitOffset>3</bitOffset>
2978 <bitWidth>1</bitWidth>
2979 </field>
2980 <field>
2981 <name>b36</name>
2982 <description>b36</description>
2983 <bitOffset>4</bitOffset>
2984 <bitWidth>1</bitWidth>
2985 </field>
2986 <field>
2987 <name>b37</name>
2988 <description>b37</description>
2989 <bitOffset>5</bitOffset>
2990 <bitWidth>1</bitWidth>
2991 </field>
2992 <field>
2993 <name>b38</name>
2994 <description>b38</description>
2995 <bitOffset>6</bitOffset>
2996 <bitWidth>1</bitWidth>
2997 </field>
2998 <field>
2999 <name>b39</name>
3000 <description>b39</description>
3001 <bitOffset>7</bitOffset>
3002 <bitWidth>1</bitWidth>
3003 </field>
3004 <field>
3005 <name>b40</name>
3006 <description>b40</description>
3007 <bitOffset>8</bitOffset>
3008 <bitWidth>1</bitWidth>
3009 </field>
3010 <field>
3011 <name>b41</name>
3012 <description>b41</description>
3013 <bitOffset>9</bitOffset>
3014 <bitWidth>1</bitWidth>
3015 </field>
3016 <field>
3017 <name>b42</name>
3018 <description>b42</description>
3019 <bitOffset>10</bitOffset>
3020 <bitWidth>1</bitWidth>
3021 </field>
3022 <field>
3023 <name>b43</name>
3024 <description>b43</description>
3025 <bitOffset>11</bitOffset>
3026 <bitWidth>1</bitWidth>
3027 </field>
3028 <field>
3029 <name>b44</name>
3030 <description>b44</description>
3031 <bitOffset>12</bitOffset>
3032 <bitWidth>1</bitWidth>
3033 </field>
3034 <field>
3035 <name>b45</name>
3036 <description>b45</description>
3037 <bitOffset>13</bitOffset>
3038 <bitWidth>1</bitWidth>
3039 </field>
3040 <field>
3041 <name>b46</name>
3042 <description>b46</description>
3043 <bitOffset>14</bitOffset>
3044 <bitWidth>1</bitWidth>
3045 </field>
3046 <field>
3047 <name>b47</name>
3048 <description>b47</description>
3049 <bitOffset>15</bitOffset>
3050 <bitWidth>1</bitWidth>
3051 </field>
3052 <field>
3053 <name>b48</name>
3054 <description>b48</description>
3055 <bitOffset>16</bitOffset>
3056 <bitWidth>1</bitWidth>
3057 </field>
3058 <field>
3059 <name>b49</name>
3060 <description>b49</description>
3061 <bitOffset>17</bitOffset>
3062 <bitWidth>1</bitWidth>
3063 </field>
3064 <field>
3065 <name>b50</name>
3066 <description>b50</description>
3067 <bitOffset>18</bitOffset>
3068 <bitWidth>1</bitWidth>
3069 </field>
3070 <field>
3071 <name>b51</name>
3072 <description>b51</description>
3073 <bitOffset>19</bitOffset>
3074 <bitWidth>1</bitWidth>
3075 </field>
3076 <field>
3077 <name>b52</name>
3078 <description>b52</description>
3079 <bitOffset>20</bitOffset>
3080 <bitWidth>1</bitWidth>
3081 </field>
3082 <field>
3083 <name>b53</name>
3084 <description>b53</description>
3085 <bitOffset>21</bitOffset>
3086 <bitWidth>1</bitWidth>
3087 </field>
3088 <field>
3089 <name>b54</name>
3090 <description>b54</description>
3091 <bitOffset>22</bitOffset>
3092 <bitWidth>1</bitWidth>
3093 </field>
3094 <field>
3095 <name>b55</name>
3096 <description>b55</description>
3097 <bitOffset>23</bitOffset>
3098 <bitWidth>1</bitWidth>
3099 </field>
3100 <field>
3101 <name>b56</name>
3102 <description>b56</description>
3103 <bitOffset>24</bitOffset>
3104 <bitWidth>1</bitWidth>
3105 </field>
3106 <field>
3107 <name>b57</name>
3108 <description>b57</description>
3109 <bitOffset>25</bitOffset>
3110 <bitWidth>1</bitWidth>
3111 </field>
3112 <field>
3113 <name>b58</name>
3114 <description>b58</description>
3115 <bitOffset>26</bitOffset>
3116 <bitWidth>1</bitWidth>
3117 </field>
3118 <field>
3119 <name>b59</name>
3120 <description>b59</description>
3121 <bitOffset>27</bitOffset>
3122 <bitWidth>1</bitWidth>
3123 </field>
3124 <field>
3125 <name>b60</name>
3126 <description>b60</description>
3127 <bitOffset>28</bitOffset>
3128 <bitWidth>1</bitWidth>
3129 </field>
3130 <field>
3131 <name>b61</name>
3132 <description>b61</description>
3133 <bitOffset>29</bitOffset>
3134 <bitWidth>1</bitWidth>
3135 </field>
3136 <field>
3137 <name>b62</name>
3138 <description>b62</description>
3139 <bitOffset>30</bitOffset>
3140 <bitWidth>1</bitWidth>
3141 </field>
3142 <field>
3143 <name>b63</name>
3144 <description>b63</description>
3145 <bitOffset>31</bitOffset>
3146 <bitWidth>1</bitWidth>
3147 </field>
3148 </fields>
3149 </register>
3150 <register>
3151 <name>K3RR</name>
3152 <displayName>K3RR</displayName>
3153 <description>key registers</description>
3154 <addressOffset>0x3C</addressOffset>
3155 <size>0x20</size>
3156 <access>write-only</access>
3157 <resetValue>0x00000000</resetValue>
3158 <fields>
3159 <field>
3160 <name>b0</name>
3161 <description>b0</description>
3162 <bitOffset>0</bitOffset>
3163 <bitWidth>1</bitWidth>
3164 </field>
3165 <field>
3166 <name>b1</name>
3167 <description>b1</description>
3168 <bitOffset>1</bitOffset>
3169 <bitWidth>1</bitWidth>
3170 </field>
3171 <field>
3172 <name>b2</name>
3173 <description>b2</description>
3174 <bitOffset>2</bitOffset>
3175 <bitWidth>1</bitWidth>
3176 </field>
3177 <field>
3178 <name>b3</name>
3179 <description>b3</description>
3180 <bitOffset>3</bitOffset>
3181 <bitWidth>1</bitWidth>
3182 </field>
3183 <field>
3184 <name>b4</name>
3185 <description>b4</description>
3186 <bitOffset>4</bitOffset>
3187 <bitWidth>1</bitWidth>
3188 </field>
3189 <field>
3190 <name>b5</name>
3191 <description>b5</description>
3192 <bitOffset>5</bitOffset>
3193 <bitWidth>1</bitWidth>
3194 </field>
3195 <field>
3196 <name>b6</name>
3197 <description>b6</description>
3198 <bitOffset>6</bitOffset>
3199 <bitWidth>1</bitWidth>
3200 </field>
3201 <field>
3202 <name>b7</name>
3203 <description>b7</description>
3204 <bitOffset>7</bitOffset>
3205 <bitWidth>1</bitWidth>
3206 </field>
3207 <field>
3208 <name>b8</name>
3209 <description>b8</description>
3210 <bitOffset>8</bitOffset>
3211 <bitWidth>1</bitWidth>
3212 </field>
3213 <field>
3214 <name>b9</name>
3215 <description>b9</description>
3216 <bitOffset>9</bitOffset>
3217 <bitWidth>1</bitWidth>
3218 </field>
3219 <field>
3220 <name>b10</name>
3221 <description>b10</description>
3222 <bitOffset>10</bitOffset>
3223 <bitWidth>1</bitWidth>
3224 </field>
3225 <field>
3226 <name>b11</name>
3227 <description>b11</description>
3228 <bitOffset>11</bitOffset>
3229 <bitWidth>1</bitWidth>
3230 </field>
3231 <field>
3232 <name>b12</name>
3233 <description>b12</description>
3234 <bitOffset>12</bitOffset>
3235 <bitWidth>1</bitWidth>
3236 </field>
3237 <field>
3238 <name>b13</name>
3239 <description>b13</description>
3240 <bitOffset>13</bitOffset>
3241 <bitWidth>1</bitWidth>
3242 </field>
3243 <field>
3244 <name>b14</name>
3245 <description>b14</description>
3246 <bitOffset>14</bitOffset>
3247 <bitWidth>1</bitWidth>
3248 </field>
3249 <field>
3250 <name>b15</name>
3251 <description>b15</description>
3252 <bitOffset>15</bitOffset>
3253 <bitWidth>1</bitWidth>
3254 </field>
3255 <field>
3256 <name>b16</name>
3257 <description>b16</description>
3258 <bitOffset>16</bitOffset>
3259 <bitWidth>1</bitWidth>
3260 </field>
3261 <field>
3262 <name>b17</name>
3263 <description>b17</description>
3264 <bitOffset>17</bitOffset>
3265 <bitWidth>1</bitWidth>
3266 </field>
3267 <field>
3268 <name>b18</name>
3269 <description>b18</description>
3270 <bitOffset>18</bitOffset>
3271 <bitWidth>1</bitWidth>
3272 </field>
3273 <field>
3274 <name>b19</name>
3275 <description>b19</description>
3276 <bitOffset>19</bitOffset>
3277 <bitWidth>1</bitWidth>
3278 </field>
3279 <field>
3280 <name>b20</name>
3281 <description>b20</description>
3282 <bitOffset>20</bitOffset>
3283 <bitWidth>1</bitWidth>
3284 </field>
3285 <field>
3286 <name>b21</name>
3287 <description>b21</description>
3288 <bitOffset>21</bitOffset>
3289 <bitWidth>1</bitWidth>
3290 </field>
3291 <field>
3292 <name>b22</name>
3293 <description>b22</description>
3294 <bitOffset>22</bitOffset>
3295 <bitWidth>1</bitWidth>
3296 </field>
3297 <field>
3298 <name>b23</name>
3299 <description>b23</description>
3300 <bitOffset>23</bitOffset>
3301 <bitWidth>1</bitWidth>
3302 </field>
3303 <field>
3304 <name>b24</name>
3305 <description>b24</description>
3306 <bitOffset>24</bitOffset>
3307 <bitWidth>1</bitWidth>
3308 </field>
3309 <field>
3310 <name>b25</name>
3311 <description>b25</description>
3312 <bitOffset>25</bitOffset>
3313 <bitWidth>1</bitWidth>
3314 </field>
3315 <field>
3316 <name>b26</name>
3317 <description>b26</description>
3318 <bitOffset>26</bitOffset>
3319 <bitWidth>1</bitWidth>
3320 </field>
3321 <field>
3322 <name>b27</name>
3323 <description>b27</description>
3324 <bitOffset>27</bitOffset>
3325 <bitWidth>1</bitWidth>
3326 </field>
3327 <field>
3328 <name>b28</name>
3329 <description>b28</description>
3330 <bitOffset>28</bitOffset>
3331 <bitWidth>1</bitWidth>
3332 </field>
3333 <field>
3334 <name>b29</name>
3335 <description>b29</description>
3336 <bitOffset>29</bitOffset>
3337 <bitWidth>1</bitWidth>
3338 </field>
3339 <field>
3340 <name>b30</name>
3341 <description>b30</description>
3342 <bitOffset>30</bitOffset>
3343 <bitWidth>1</bitWidth>
3344 </field>
3345 <field>
3346 <name>b31</name>
3347 <description>b31</description>
3348 <bitOffset>31</bitOffset>
3349 <bitWidth>1</bitWidth>
3350 </field>
3351 </fields>
3352 </register>
3353 <register>
3354 <name>IV0LR</name>
3355 <displayName>IV0LR</displayName>
3356 <description>initialization vector
3357 registers</description>
3358 <addressOffset>0x40</addressOffset>
3359 <size>0x20</size>
3360 <access>read-write</access>
3361 <resetValue>0x00000000</resetValue>
3362 <fields>
3363 <field>
3364 <name>IV31</name>
3365 <description>IV31</description>
3366 <bitOffset>0</bitOffset>
3367 <bitWidth>1</bitWidth>
3368 </field>
3369 <field>
3370 <name>IV30</name>
3371 <description>IV30</description>
3372 <bitOffset>1</bitOffset>
3373 <bitWidth>1</bitWidth>
3374 </field>
3375 <field>
3376 <name>IV29</name>
3377 <description>IV29</description>
3378 <bitOffset>2</bitOffset>
3379 <bitWidth>1</bitWidth>
3380 </field>
3381 <field>
3382 <name>IV28</name>
3383 <description>IV28</description>
3384 <bitOffset>3</bitOffset>
3385 <bitWidth>1</bitWidth>
3386 </field>
3387 <field>
3388 <name>IV27</name>
3389 <description>IV27</description>
3390 <bitOffset>4</bitOffset>
3391 <bitWidth>1</bitWidth>
3392 </field>
3393 <field>
3394 <name>IV26</name>
3395 <description>IV26</description>
3396 <bitOffset>5</bitOffset>
3397 <bitWidth>1</bitWidth>
3398 </field>
3399 <field>
3400 <name>IV25</name>
3401 <description>IV25</description>
3402 <bitOffset>6</bitOffset>
3403 <bitWidth>1</bitWidth>
3404 </field>
3405 <field>
3406 <name>IV24</name>
3407 <description>IV24</description>
3408 <bitOffset>7</bitOffset>
3409 <bitWidth>1</bitWidth>
3410 </field>
3411 <field>
3412 <name>IV23</name>
3413 <description>IV23</description>
3414 <bitOffset>8</bitOffset>
3415 <bitWidth>1</bitWidth>
3416 </field>
3417 <field>
3418 <name>IV22</name>
3419 <description>IV22</description>
3420 <bitOffset>9</bitOffset>
3421 <bitWidth>1</bitWidth>
3422 </field>
3423 <field>
3424 <name>IV21</name>
3425 <description>IV21</description>
3426 <bitOffset>10</bitOffset>
3427 <bitWidth>1</bitWidth>
3428 </field>
3429 <field>
3430 <name>IV20</name>
3431 <description>IV20</description>
3432 <bitOffset>11</bitOffset>
3433 <bitWidth>1</bitWidth>
3434 </field>
3435 <field>
3436 <name>IV19</name>
3437 <description>IV19</description>
3438 <bitOffset>12</bitOffset>
3439 <bitWidth>1</bitWidth>
3440 </field>
3441 <field>
3442 <name>IV18</name>
3443 <description>IV18</description>
3444 <bitOffset>13</bitOffset>
3445 <bitWidth>1</bitWidth>
3446 </field>
3447 <field>
3448 <name>IV17</name>
3449 <description>IV17</description>
3450 <bitOffset>14</bitOffset>
3451 <bitWidth>1</bitWidth>
3452 </field>
3453 <field>
3454 <name>IV16</name>
3455 <description>IV16</description>
3456 <bitOffset>15</bitOffset>
3457 <bitWidth>1</bitWidth>
3458 </field>
3459 <field>
3460 <name>IV15</name>
3461 <description>IV15</description>
3462 <bitOffset>16</bitOffset>
3463 <bitWidth>1</bitWidth>
3464 </field>
3465 <field>
3466 <name>IV14</name>
3467 <description>IV14</description>
3468 <bitOffset>17</bitOffset>
3469 <bitWidth>1</bitWidth>
3470 </field>
3471 <field>
3472 <name>IV13</name>
3473 <description>IV13</description>
3474 <bitOffset>18</bitOffset>
3475 <bitWidth>1</bitWidth>
3476 </field>
3477 <field>
3478 <name>IV12</name>
3479 <description>IV12</description>
3480 <bitOffset>19</bitOffset>
3481 <bitWidth>1</bitWidth>
3482 </field>
3483 <field>
3484 <name>IV11</name>
3485 <description>IV11</description>
3486 <bitOffset>20</bitOffset>
3487 <bitWidth>1</bitWidth>
3488 </field>
3489 <field>
3490 <name>IV10</name>
3491 <description>IV10</description>
3492 <bitOffset>21</bitOffset>
3493 <bitWidth>1</bitWidth>
3494 </field>
3495 <field>
3496 <name>IV9</name>
3497 <description>IV9</description>
3498 <bitOffset>22</bitOffset>
3499 <bitWidth>1</bitWidth>
3500 </field>
3501 <field>
3502 <name>IV8</name>
3503 <description>IV8</description>
3504 <bitOffset>23</bitOffset>
3505 <bitWidth>1</bitWidth>
3506 </field>
3507 <field>
3508 <name>IV7</name>
3509 <description>IV7</description>
3510 <bitOffset>24</bitOffset>
3511 <bitWidth>1</bitWidth>
3512 </field>
3513 <field>
3514 <name>IV6</name>
3515 <description>IV6</description>
3516 <bitOffset>25</bitOffset>
3517 <bitWidth>1</bitWidth>
3518 </field>
3519 <field>
3520 <name>IV5</name>
3521 <description>IV5</description>
3522 <bitOffset>26</bitOffset>
3523 <bitWidth>1</bitWidth>
3524 </field>
3525 <field>
3526 <name>IV4</name>
3527 <description>IV4</description>
3528 <bitOffset>27</bitOffset>
3529 <bitWidth>1</bitWidth>
3530 </field>
3531 <field>
3532 <name>IV3</name>
3533 <description>IV3</description>
3534 <bitOffset>28</bitOffset>
3535 <bitWidth>1</bitWidth>
3536 </field>
3537 <field>
3538 <name>IV2</name>
3539 <description>IV2</description>
3540 <bitOffset>29</bitOffset>
3541 <bitWidth>1</bitWidth>
3542 </field>
3543 <field>
3544 <name>IV1</name>
3545 <description>IV1</description>
3546 <bitOffset>30</bitOffset>
3547 <bitWidth>1</bitWidth>
3548 </field>
3549 <field>
3550 <name>IV0</name>
3551 <description>IV0</description>
3552 <bitOffset>31</bitOffset>
3553 <bitWidth>1</bitWidth>
3554 </field>
3555 </fields>
3556 </register>
3557 <register>
3558 <name>IV0RR</name>
3559 <displayName>IV0RR</displayName>
3560 <description>initialization vector
3561 registers</description>
3562 <addressOffset>0x44</addressOffset>
3563 <size>0x20</size>
3564 <access>read-write</access>
3565 <resetValue>0x00000000</resetValue>
3566 <fields>
3567 <field>
3568 <name>IV63</name>
3569 <description>IV63</description>
3570 <bitOffset>0</bitOffset>
3571 <bitWidth>1</bitWidth>
3572 </field>
3573 <field>
3574 <name>IV62</name>
3575 <description>IV62</description>
3576 <bitOffset>1</bitOffset>
3577 <bitWidth>1</bitWidth>
3578 </field>
3579 <field>
3580 <name>IV61</name>
3581 <description>IV61</description>
3582 <bitOffset>2</bitOffset>
3583 <bitWidth>1</bitWidth>
3584 </field>
3585 <field>
3586 <name>IV60</name>
3587 <description>IV60</description>
3588 <bitOffset>3</bitOffset>
3589 <bitWidth>1</bitWidth>
3590 </field>
3591 <field>
3592 <name>IV59</name>
3593 <description>IV59</description>
3594 <bitOffset>4</bitOffset>
3595 <bitWidth>1</bitWidth>
3596 </field>
3597 <field>
3598 <name>IV58</name>
3599 <description>IV58</description>
3600 <bitOffset>5</bitOffset>
3601 <bitWidth>1</bitWidth>
3602 </field>
3603 <field>
3604 <name>IV57</name>
3605 <description>IV57</description>
3606 <bitOffset>6</bitOffset>
3607 <bitWidth>1</bitWidth>
3608 </field>
3609 <field>
3610 <name>IV56</name>
3611 <description>IV56</description>
3612 <bitOffset>7</bitOffset>
3613 <bitWidth>1</bitWidth>
3614 </field>
3615 <field>
3616 <name>IV55</name>
3617 <description>IV55</description>
3618 <bitOffset>8</bitOffset>
3619 <bitWidth>1</bitWidth>
3620 </field>
3621 <field>
3622 <name>IV54</name>
3623 <description>IV54</description>
3624 <bitOffset>9</bitOffset>
3625 <bitWidth>1</bitWidth>
3626 </field>
3627 <field>
3628 <name>IV53</name>
3629 <description>IV53</description>
3630 <bitOffset>10</bitOffset>
3631 <bitWidth>1</bitWidth>
3632 </field>
3633 <field>
3634 <name>IV52</name>
3635 <description>IV52</description>
3636 <bitOffset>11</bitOffset>
3637 <bitWidth>1</bitWidth>
3638 </field>
3639 <field>
3640 <name>IV51</name>
3641 <description>IV51</description>
3642 <bitOffset>12</bitOffset>
3643 <bitWidth>1</bitWidth>
3644 </field>
3645 <field>
3646 <name>IV50</name>
3647 <description>IV50</description>
3648 <bitOffset>13</bitOffset>
3649 <bitWidth>1</bitWidth>
3650 </field>
3651 <field>
3652 <name>IV49</name>
3653 <description>IV49</description>
3654 <bitOffset>14</bitOffset>
3655 <bitWidth>1</bitWidth>
3656 </field>
3657 <field>
3658 <name>IV48</name>
3659 <description>IV48</description>
3660 <bitOffset>15</bitOffset>
3661 <bitWidth>1</bitWidth>
3662 </field>
3663 <field>
3664 <name>IV47</name>
3665 <description>IV47</description>
3666 <bitOffset>16</bitOffset>
3667 <bitWidth>1</bitWidth>
3668 </field>
3669 <field>
3670 <name>IV46</name>
3671 <description>IV46</description>
3672 <bitOffset>17</bitOffset>
3673 <bitWidth>1</bitWidth>
3674 </field>
3675 <field>
3676 <name>IV45</name>
3677 <description>IV45</description>
3678 <bitOffset>18</bitOffset>
3679 <bitWidth>1</bitWidth>
3680 </field>
3681 <field>
3682 <name>IV44</name>
3683 <description>IV44</description>
3684 <bitOffset>19</bitOffset>
3685 <bitWidth>1</bitWidth>
3686 </field>
3687 <field>
3688 <name>IV43</name>
3689 <description>IV43</description>
3690 <bitOffset>20</bitOffset>
3691 <bitWidth>1</bitWidth>
3692 </field>
3693 <field>
3694 <name>IV42</name>
3695 <description>IV42</description>
3696 <bitOffset>21</bitOffset>
3697 <bitWidth>1</bitWidth>
3698 </field>
3699 <field>
3700 <name>IV41</name>
3701 <description>IV41</description>
3702 <bitOffset>22</bitOffset>
3703 <bitWidth>1</bitWidth>
3704 </field>
3705 <field>
3706 <name>IV40</name>
3707 <description>IV40</description>
3708 <bitOffset>23</bitOffset>
3709 <bitWidth>1</bitWidth>
3710 </field>
3711 <field>
3712 <name>IV39</name>
3713 <description>IV39</description>
3714 <bitOffset>24</bitOffset>
3715 <bitWidth>1</bitWidth>
3716 </field>
3717 <field>
3718 <name>IV38</name>
3719 <description>IV38</description>
3720 <bitOffset>25</bitOffset>
3721 <bitWidth>1</bitWidth>
3722 </field>
3723 <field>
3724 <name>IV37</name>
3725 <description>IV37</description>
3726 <bitOffset>26</bitOffset>
3727 <bitWidth>1</bitWidth>
3728 </field>
3729 <field>
3730 <name>IV36</name>
3731 <description>IV36</description>
3732 <bitOffset>27</bitOffset>
3733 <bitWidth>1</bitWidth>
3734 </field>
3735 <field>
3736 <name>IV35</name>
3737 <description>IV35</description>
3738 <bitOffset>28</bitOffset>
3739 <bitWidth>1</bitWidth>
3740 </field>
3741 <field>
3742 <name>IV34</name>
3743 <description>IV34</description>
3744 <bitOffset>29</bitOffset>
3745 <bitWidth>1</bitWidth>
3746 </field>
3747 <field>
3748 <name>IV33</name>
3749 <description>IV33</description>
3750 <bitOffset>30</bitOffset>
3751 <bitWidth>1</bitWidth>
3752 </field>
3753 <field>
3754 <name>IV32</name>
3755 <description>IV32</description>
3756 <bitOffset>31</bitOffset>
3757 <bitWidth>1</bitWidth>
3758 </field>
3759 </fields>
3760 </register>
3761 <register>
3762 <name>IV1LR</name>
3763 <displayName>IV1LR</displayName>
3764 <description>initialization vector
3765 registers</description>
3766 <addressOffset>0x48</addressOffset>
3767 <size>0x20</size>
3768 <access>read-write</access>
3769 <resetValue>0x00000000</resetValue>
3770 <fields>
3771 <field>
3772 <name>IV95</name>
3773 <description>IV95</description>
3774 <bitOffset>0</bitOffset>
3775 <bitWidth>1</bitWidth>
3776 </field>
3777 <field>
3778 <name>IV94</name>
3779 <description>IV94</description>
3780 <bitOffset>1</bitOffset>
3781 <bitWidth>1</bitWidth>
3782 </field>
3783 <field>
3784 <name>IV93</name>
3785 <description>IV93</description>
3786 <bitOffset>2</bitOffset>
3787 <bitWidth>1</bitWidth>
3788 </field>
3789 <field>
3790 <name>IV92</name>
3791 <description>IV92</description>
3792 <bitOffset>3</bitOffset>
3793 <bitWidth>1</bitWidth>
3794 </field>
3795 <field>
3796 <name>IV91</name>
3797 <description>IV91</description>
3798 <bitOffset>4</bitOffset>
3799 <bitWidth>1</bitWidth>
3800 </field>
3801 <field>
3802 <name>IV90</name>
3803 <description>IV90</description>
3804 <bitOffset>5</bitOffset>
3805 <bitWidth>1</bitWidth>
3806 </field>
3807 <field>
3808 <name>IV89</name>
3809 <description>IV89</description>
3810 <bitOffset>6</bitOffset>
3811 <bitWidth>1</bitWidth>
3812 </field>
3813 <field>
3814 <name>IV88</name>
3815 <description>IV88</description>
3816 <bitOffset>7</bitOffset>
3817 <bitWidth>1</bitWidth>
3818 </field>
3819 <field>
3820 <name>IV87</name>
3821 <description>IV87</description>
3822 <bitOffset>8</bitOffset>
3823 <bitWidth>1</bitWidth>
3824 </field>
3825 <field>
3826 <name>IV86</name>
3827 <description>IV86</description>
3828 <bitOffset>9</bitOffset>
3829 <bitWidth>1</bitWidth>
3830 </field>
3831 <field>
3832 <name>IV85</name>
3833 <description>IV85</description>
3834 <bitOffset>10</bitOffset>
3835 <bitWidth>1</bitWidth>
3836 </field>
3837 <field>
3838 <name>IV84</name>
3839 <description>IV84</description>
3840 <bitOffset>11</bitOffset>
3841 <bitWidth>1</bitWidth>
3842 </field>
3843 <field>
3844 <name>IV83</name>
3845 <description>IV83</description>
3846 <bitOffset>12</bitOffset>
3847 <bitWidth>1</bitWidth>
3848 </field>
3849 <field>
3850 <name>IV82</name>
3851 <description>IV82</description>
3852 <bitOffset>13</bitOffset>
3853 <bitWidth>1</bitWidth>
3854 </field>
3855 <field>
3856 <name>IV81</name>
3857 <description>IV81</description>
3858 <bitOffset>14</bitOffset>
3859 <bitWidth>1</bitWidth>
3860 </field>
3861 <field>
3862 <name>IV80</name>
3863 <description>IV80</description>
3864 <bitOffset>15</bitOffset>
3865 <bitWidth>1</bitWidth>
3866 </field>
3867 <field>
3868 <name>IV79</name>
3869 <description>IV79</description>
3870 <bitOffset>16</bitOffset>
3871 <bitWidth>1</bitWidth>
3872 </field>
3873 <field>
3874 <name>IV78</name>
3875 <description>IV78</description>
3876 <bitOffset>17</bitOffset>
3877 <bitWidth>1</bitWidth>
3878 </field>
3879 <field>
3880 <name>IV77</name>
3881 <description>IV77</description>
3882 <bitOffset>18</bitOffset>
3883 <bitWidth>1</bitWidth>
3884 </field>
3885 <field>
3886 <name>IV76</name>
3887 <description>IV76</description>
3888 <bitOffset>19</bitOffset>
3889 <bitWidth>1</bitWidth>
3890 </field>
3891 <field>
3892 <name>IV75</name>
3893 <description>IV75</description>
3894 <bitOffset>20</bitOffset>
3895 <bitWidth>1</bitWidth>
3896 </field>
3897 <field>
3898 <name>IV74</name>
3899 <description>IV74</description>
3900 <bitOffset>21</bitOffset>
3901 <bitWidth>1</bitWidth>
3902 </field>
3903 <field>
3904 <name>IV73</name>
3905 <description>IV73</description>
3906 <bitOffset>22</bitOffset>
3907 <bitWidth>1</bitWidth>
3908 </field>
3909 <field>
3910 <name>IV72</name>
3911 <description>IV72</description>
3912 <bitOffset>23</bitOffset>
3913 <bitWidth>1</bitWidth>
3914 </field>
3915 <field>
3916 <name>IV71</name>
3917 <description>IV71</description>
3918 <bitOffset>24</bitOffset>
3919 <bitWidth>1</bitWidth>
3920 </field>
3921 <field>
3922 <name>IV70</name>
3923 <description>IV70</description>
3924 <bitOffset>25</bitOffset>
3925 <bitWidth>1</bitWidth>
3926 </field>
3927 <field>
3928 <name>IV69</name>
3929 <description>IV69</description>
3930 <bitOffset>26</bitOffset>
3931 <bitWidth>1</bitWidth>
3932 </field>
3933 <field>
3934 <name>IV68</name>
3935 <description>IV68</description>
3936 <bitOffset>27</bitOffset>
3937 <bitWidth>1</bitWidth>
3938 </field>
3939 <field>
3940 <name>IV67</name>
3941 <description>IV67</description>
3942 <bitOffset>28</bitOffset>
3943 <bitWidth>1</bitWidth>
3944 </field>
3945 <field>
3946 <name>IV66</name>
3947 <description>IV66</description>
3948 <bitOffset>29</bitOffset>
3949 <bitWidth>1</bitWidth>
3950 </field>
3951 <field>
3952 <name>IV65</name>
3953 <description>IV65</description>
3954 <bitOffset>30</bitOffset>
3955 <bitWidth>1</bitWidth>
3956 </field>
3957 <field>
3958 <name>IV64</name>
3959 <description>IV64</description>
3960 <bitOffset>31</bitOffset>
3961 <bitWidth>1</bitWidth>
3962 </field>
3963 </fields>
3964 </register>
3965 <register>
3966 <name>IV1RR</name>
3967 <displayName>IV1RR</displayName>
3968 <description>initialization vector
3969 registers</description>
3970 <addressOffset>0x4C</addressOffset>
3971 <size>0x20</size>
3972 <access>read-write</access>
3973 <resetValue>0x00000000</resetValue>
3974 <fields>
3975 <field>
3976 <name>IV127</name>
3977 <description>IV127</description>
3978 <bitOffset>0</bitOffset>
3979 <bitWidth>1</bitWidth>
3980 </field>
3981 <field>
3982 <name>IV126</name>
3983 <description>IV126</description>
3984 <bitOffset>1</bitOffset>
3985 <bitWidth>1</bitWidth>
3986 </field>
3987 <field>
3988 <name>IV125</name>
3989 <description>IV125</description>
3990 <bitOffset>2</bitOffset>
3991 <bitWidth>1</bitWidth>
3992 </field>
3993 <field>
3994 <name>IV124</name>
3995 <description>IV124</description>
3996 <bitOffset>3</bitOffset>
3997 <bitWidth>1</bitWidth>
3998 </field>
3999 <field>
4000 <name>IV123</name>
4001 <description>IV123</description>
4002 <bitOffset>4</bitOffset>
4003 <bitWidth>1</bitWidth>
4004 </field>
4005 <field>
4006 <name>IV122</name>
4007 <description>IV122</description>
4008 <bitOffset>5</bitOffset>
4009 <bitWidth>1</bitWidth>
4010 </field>
4011 <field>
4012 <name>IV121</name>
4013 <description>IV121</description>
4014 <bitOffset>6</bitOffset>
4015 <bitWidth>1</bitWidth>
4016 </field>
4017 <field>
4018 <name>IV120</name>
4019 <description>IV120</description>
4020 <bitOffset>7</bitOffset>
4021 <bitWidth>1</bitWidth>
4022 </field>
4023 <field>
4024 <name>IV119</name>
4025 <description>IV119</description>
4026 <bitOffset>8</bitOffset>
4027 <bitWidth>1</bitWidth>
4028 </field>
4029 <field>
4030 <name>IV118</name>
4031 <description>IV118</description>
4032 <bitOffset>9</bitOffset>
4033 <bitWidth>1</bitWidth>
4034 </field>
4035 <field>
4036 <name>IV117</name>
4037 <description>IV117</description>
4038 <bitOffset>10</bitOffset>
4039 <bitWidth>1</bitWidth>
4040 </field>
4041 <field>
4042 <name>IV116</name>
4043 <description>IV116</description>
4044 <bitOffset>11</bitOffset>
4045 <bitWidth>1</bitWidth>
4046 </field>
4047 <field>
4048 <name>IV115</name>
4049 <description>IV115</description>
4050 <bitOffset>12</bitOffset>
4051 <bitWidth>1</bitWidth>
4052 </field>
4053 <field>
4054 <name>IV114</name>
4055 <description>IV114</description>
4056 <bitOffset>13</bitOffset>
4057 <bitWidth>1</bitWidth>
4058 </field>
4059 <field>
4060 <name>IV113</name>
4061 <description>IV113</description>
4062 <bitOffset>14</bitOffset>
4063 <bitWidth>1</bitWidth>
4064 </field>
4065 <field>
4066 <name>IV112</name>
4067 <description>IV112</description>
4068 <bitOffset>15</bitOffset>
4069 <bitWidth>1</bitWidth>
4070 </field>
4071 <field>
4072 <name>IV111</name>
4073 <description>IV111</description>
4074 <bitOffset>16</bitOffset>
4075 <bitWidth>1</bitWidth>
4076 </field>
4077 <field>
4078 <name>IV110</name>
4079 <description>IV110</description>
4080 <bitOffset>17</bitOffset>
4081 <bitWidth>1</bitWidth>
4082 </field>
4083 <field>
4084 <name>IV109</name>
4085 <description>IV109</description>
4086 <bitOffset>18</bitOffset>
4087 <bitWidth>1</bitWidth>
4088 </field>
4089 <field>
4090 <name>IV108</name>
4091 <description>IV108</description>
4092 <bitOffset>19</bitOffset>
4093 <bitWidth>1</bitWidth>
4094 </field>
4095 <field>
4096 <name>IV107</name>
4097 <description>IV107</description>
4098 <bitOffset>20</bitOffset>
4099 <bitWidth>1</bitWidth>
4100 </field>
4101 <field>
4102 <name>IV106</name>
4103 <description>IV106</description>
4104 <bitOffset>21</bitOffset>
4105 <bitWidth>1</bitWidth>
4106 </field>
4107 <field>
4108 <name>IV105</name>
4109 <description>IV105</description>
4110 <bitOffset>22</bitOffset>
4111 <bitWidth>1</bitWidth>
4112 </field>
4113 <field>
4114 <name>IV104</name>
4115 <description>IV104</description>
4116 <bitOffset>23</bitOffset>
4117 <bitWidth>1</bitWidth>
4118 </field>
4119 <field>
4120 <name>IV103</name>
4121 <description>IV103</description>
4122 <bitOffset>24</bitOffset>
4123 <bitWidth>1</bitWidth>
4124 </field>
4125 <field>
4126 <name>IV102</name>
4127 <description>IV102</description>
4128 <bitOffset>25</bitOffset>
4129 <bitWidth>1</bitWidth>
4130 </field>
4131 <field>
4132 <name>IV101</name>
4133 <description>IV101</description>
4134 <bitOffset>26</bitOffset>
4135 <bitWidth>1</bitWidth>
4136 </field>
4137 <field>
4138 <name>IV100</name>
4139 <description>IV100</description>
4140 <bitOffset>27</bitOffset>
4141 <bitWidth>1</bitWidth>
4142 </field>
4143 <field>
4144 <name>IV99</name>
4145 <description>IV99</description>
4146 <bitOffset>28</bitOffset>
4147 <bitWidth>1</bitWidth>
4148 </field>
4149 <field>
4150 <name>IV98</name>
4151 <description>IV98</description>
4152 <bitOffset>29</bitOffset>
4153 <bitWidth>1</bitWidth>
4154 </field>
4155 <field>
4156 <name>IV97</name>
4157 <description>IV97</description>
4158 <bitOffset>30</bitOffset>
4159 <bitWidth>1</bitWidth>
4160 </field>
4161 <field>
4162 <name>IV96</name>
4163 <description>IV96</description>
4164 <bitOffset>31</bitOffset>
4165 <bitWidth>1</bitWidth>
4166 </field>
4167 </fields>
4168 </register>
4169 <register>
4170 <name>CSGCMCCM0R</name>
4171 <displayName>CSGCMCCM0R</displayName>
4172 <description>context swap register</description>
4173 <addressOffset>0x50</addressOffset>
4174 <size>0x20</size>
4175 <access>read-write</access>
4176 <resetValue>0x00000000</resetValue>
4177 <fields>
4178 <field>
4179 <name>CSGCMCCM0R</name>
4180 <description>CSGCMCCM0R</description>
4181 <bitOffset>0</bitOffset>
4182 <bitWidth>32</bitWidth>
4183 </field>
4184 </fields>
4185 </register>
4186 <register>
4187 <name>CSGCMCCM1R</name>
4188 <displayName>CSGCMCCM1R</displayName>
4189 <description>context swap register</description>
4190 <addressOffset>0x54</addressOffset>
4191 <size>0x20</size>
4192 <access>read-write</access>
4193 <resetValue>0x00000000</resetValue>
4194 <fields>
4195 <field>
4196 <name>CSGCMCCM1R</name>
4197 <description>CSGCMCCM1R</description>
4198 <bitOffset>0</bitOffset>
4199 <bitWidth>32</bitWidth>
4200 </field>
4201 </fields>
4202 </register>
4203 <register>
4204 <name>CSGCMCCM2R</name>
4205 <displayName>CSGCMCCM2R</displayName>
4206 <description>context swap register</description>
4207 <addressOffset>0x58</addressOffset>
4208 <size>0x20</size>
4209 <access>read-write</access>
4210 <resetValue>0x00000000</resetValue>
4211 <fields>
4212 <field>
4213 <name>CSGCMCCM2R</name>
4214 <description>CSGCMCCM2R</description>
4215 <bitOffset>0</bitOffset>
4216 <bitWidth>32</bitWidth>
4217 </field>
4218 </fields>
4219 </register>
4220 <register>
4221 <name>CSGCMCCM3R</name>
4222 <displayName>CSGCMCCM3R</displayName>
4223 <description>context swap register</description>
4224 <addressOffset>0x5C</addressOffset>
4225 <size>0x20</size>
4226 <access>read-write</access>
4227 <resetValue>0x00000000</resetValue>
4228 <fields>
4229 <field>
4230 <name>CSGCMCCM3R</name>
4231 <description>CSGCMCCM3R</description>
4232 <bitOffset>0</bitOffset>
4233 <bitWidth>32</bitWidth>
4234 </field>
4235 </fields>
4236 </register>
4237 <register>
4238 <name>CSGCMCCM4R</name>
4239 <displayName>CSGCMCCM4R</displayName>
4240 <description>context swap register</description>
4241 <addressOffset>0x60</addressOffset>
4242 <size>0x20</size>
4243 <access>read-write</access>
4244 <resetValue>0x00000000</resetValue>
4245 <fields>
4246 <field>
4247 <name>CSGCMCCM4R</name>
4248 <description>CSGCMCCM4R</description>
4249 <bitOffset>0</bitOffset>
4250 <bitWidth>32</bitWidth>
4251 </field>
4252 </fields>
4253 </register>
4254 <register>
4255 <name>CSGCMCCM5R</name>
4256 <displayName>CSGCMCCM5R</displayName>
4257 <description>context swap register</description>
4258 <addressOffset>0x64</addressOffset>
4259 <size>0x20</size>
4260 <access>read-write</access>
4261 <resetValue>0x00000000</resetValue>
4262 <fields>
4263 <field>
4264 <name>CSGCMCCM5R</name>
4265 <description>CSGCMCCM5R</description>
4266 <bitOffset>0</bitOffset>
4267 <bitWidth>32</bitWidth>
4268 </field>
4269 </fields>
4270 </register>
4271 <register>
4272 <name>CSGCMCCM6R</name>
4273 <displayName>CSGCMCCM6R</displayName>
4274 <description>context swap register</description>
4275 <addressOffset>0x68</addressOffset>
4276 <size>0x20</size>
4277 <access>read-write</access>
4278 <resetValue>0x00000000</resetValue>
4279 <fields>
4280 <field>
4281 <name>CSGCMCCM6R</name>
4282 <description>CSGCMCCM6R</description>
4283 <bitOffset>0</bitOffset>
4284 <bitWidth>32</bitWidth>
4285 </field>
4286 </fields>
4287 </register>
4288 <register>
4289 <name>CSGCMCCM7R</name>
4290 <displayName>CSGCMCCM7R</displayName>
4291 <description>context swap register</description>
4292 <addressOffset>0x6C</addressOffset>
4293 <size>0x20</size>
4294 <access>read-write</access>
4295 <resetValue>0x00000000</resetValue>
4296 <fields>
4297 <field>
4298 <name>CSGCMCCM7R</name>
4299 <description>CSGCMCCM7R</description>
4300 <bitOffset>0</bitOffset>
4301 <bitWidth>32</bitWidth>
4302 </field>
4303 </fields>
4304 </register>
4305 <register>
4306 <name>CSGCM0R</name>
4307 <displayName>CSGCM0R</displayName>
4308 <description>context swap register</description>
4309 <addressOffset>0x70</addressOffset>
4310 <size>0x20</size>
4311 <access>read-write</access>
4312 <resetValue>0x00000000</resetValue>
4313 <fields>
4314 <field>
4315 <name>CSGCM0R</name>
4316 <description>CSGCM0R</description>
4317 <bitOffset>0</bitOffset>
4318 <bitWidth>32</bitWidth>
4319 </field>
4320 </fields>
4321 </register>
4322 <register>
4323 <name>CSGCM1R</name>
4324 <displayName>CSGCM1R</displayName>
4325 <description>context swap register</description>
4326 <addressOffset>0x74</addressOffset>
4327 <size>0x20</size>
4328 <access>read-write</access>
4329 <resetValue>0x00000000</resetValue>
4330 <fields>
4331 <field>
4332 <name>CSGCM1R</name>
4333 <description>CSGCM1R</description>
4334 <bitOffset>0</bitOffset>
4335 <bitWidth>32</bitWidth>
4336 </field>
4337 </fields>
4338 </register>
4339 <register>
4340 <name>CSGCM2R</name>
4341 <displayName>CSGCM2R</displayName>
4342 <description>context swap register</description>
4343 <addressOffset>0x78</addressOffset>
4344 <size>0x20</size>
4345 <access>read-write</access>
4346 <resetValue>0x00000000</resetValue>
4347 <fields>
4348 <field>
4349 <name>CSGCM2R</name>
4350 <description>CSGCM2R</description>
4351 <bitOffset>0</bitOffset>
4352 <bitWidth>32</bitWidth>
4353 </field>
4354 </fields>
4355 </register>
4356 <register>
4357 <name>CSGCM3R</name>
4358 <displayName>CSGCM3R</displayName>
4359 <description>context swap register</description>
4360 <addressOffset>0x7C</addressOffset>
4361 <size>0x20</size>
4362 <access>read-write</access>
4363 <resetValue>0x00000000</resetValue>
4364 <fields>
4365 <field>
4366 <name>CSGCM3R</name>
4367 <description>CSGCM3R</description>
4368 <bitOffset>0</bitOffset>
4369 <bitWidth>32</bitWidth>
4370 </field>
4371 </fields>
4372 </register>
4373 <register>
4374 <name>CSGCM4R</name>
4375 <displayName>CSGCM4R</displayName>
4376 <description>context swap register</description>
4377 <addressOffset>0x80</addressOffset>
4378 <size>0x20</size>
4379 <access>read-write</access>
4380 <resetValue>0x00000000</resetValue>
4381 <fields>
4382 <field>
4383 <name>CSGCM4R</name>
4384 <description>CSGCM4R</description>
4385 <bitOffset>0</bitOffset>
4386 <bitWidth>32</bitWidth>
4387 </field>
4388 </fields>
4389 </register>
4390 <register>
4391 <name>CSGCM5R</name>
4392 <displayName>CSGCM5R</displayName>
4393 <description>context swap register</description>
4394 <addressOffset>0x84</addressOffset>
4395 <size>0x20</size>
4396 <access>read-write</access>
4397 <resetValue>0x00000000</resetValue>
4398 <fields>
4399 <field>
4400 <name>CSGCM5R</name>
4401 <description>CSGCM5R</description>
4402 <bitOffset>0</bitOffset>
4403 <bitWidth>32</bitWidth>
4404 </field>
4405 </fields>
4406 </register>
4407 <register>
4408 <name>CSGCM6R</name>
4409 <displayName>CSGCM6R</displayName>
4410 <description>context swap register</description>
4411 <addressOffset>0x88</addressOffset>
4412 <size>0x20</size>
4413 <access>read-write</access>
4414 <resetValue>0x00000000</resetValue>
4415 <fields>
4416 <field>
4417 <name>CSGCM6R</name>
4418 <description>CSGCM6R</description>
4419 <bitOffset>0</bitOffset>
4420 <bitWidth>32</bitWidth>
4421 </field>
4422 </fields>
4423 </register>
4424 <register>
4425 <name>CSGCM7R</name>
4426 <displayName>CSGCM7R</displayName>
4427 <description>context swap register</description>
4428 <addressOffset>0x8C</addressOffset>
4429 <size>0x20</size>
4430 <access>read-write</access>
4431 <resetValue>0x00000000</resetValue>
4432 <fields>
4433 <field>
4434 <name>CSGCM7R</name>
4435 <description>CSGCM7R</description>
4436 <bitOffset>0</bitOffset>
4437 <bitWidth>32</bitWidth>
4438 </field>
4439 </fields>
4440 </register>
4441 </registers>
4442 </peripheral>
4443 <peripheral>
4444 <name>DCMI</name>
4445 <description>Digital camera interface</description>
4446 <groupName>DCMI</groupName>
4447 <baseAddress>0x50050000</baseAddress>
4448 <addressBlock>
4449 <offset>0x0</offset>
4450 <size>0x400</size>
4451 <usage>registers</usage>
4452 </addressBlock>
4453 <interrupt>
4454 <name>DCMI</name>
4455 <description>DCMI global interrupt</description>
4456 <value>78</value>
4457 </interrupt>
4458 <registers>
4459 <register>
4460 <name>CR</name>
4461 <displayName>CR</displayName>
4462 <description>control register 1</description>
4463 <addressOffset>0x0</addressOffset>
4464 <size>0x20</size>
4465 <access>read-write</access>
4466 <resetValue>0x0000</resetValue>
4467 <fields>
4468 <field>
4469 <name>ENABLE</name>
4470 <description>DCMI enable</description>
4471 <bitOffset>14</bitOffset>
4472 <bitWidth>1</bitWidth>
4473 </field>
4474 <field>
4475 <name>EDM</name>
4476 <description>Extended data mode</description>
4477 <bitOffset>10</bitOffset>
4478 <bitWidth>2</bitWidth>
4479 </field>
4480 <field>
4481 <name>FCRC</name>
4482 <description>Frame capture rate control</description>
4483 <bitOffset>8</bitOffset>
4484 <bitWidth>2</bitWidth>
4485 </field>
4486 <field>
4487 <name>VSPOL</name>
4488 <description>Vertical synchronization
4489 polarity</description>
4490 <bitOffset>7</bitOffset>
4491 <bitWidth>1</bitWidth>
4492 </field>
4493 <field>
4494 <name>HSPOL</name>
4495 <description>Horizontal synchronization
4496 polarity</description>
4497 <bitOffset>6</bitOffset>
4498 <bitWidth>1</bitWidth>
4499 </field>
4500 <field>
4501 <name>PCKPOL</name>
4502 <description>Pixel clock polarity</description>
4503 <bitOffset>5</bitOffset>
4504 <bitWidth>1</bitWidth>
4505 </field>
4506 <field>
4507 <name>ESS</name>
4508 <description>Embedded synchronization
4509 select</description>
4510 <bitOffset>4</bitOffset>
4511 <bitWidth>1</bitWidth>
4512 </field>
4513 <field>
4514 <name>JPEG</name>
4515 <description>JPEG format</description>
4516 <bitOffset>3</bitOffset>
4517 <bitWidth>1</bitWidth>
4518 </field>
4519 <field>
4520 <name>CROP</name>
4521 <description>Crop feature</description>
4522 <bitOffset>2</bitOffset>
4523 <bitWidth>1</bitWidth>
4524 </field>
4525 <field>
4526 <name>CM</name>
4527 <description>Capture mode</description>
4528 <bitOffset>1</bitOffset>
4529 <bitWidth>1</bitWidth>
4530 </field>
4531 <field>
4532 <name>CAPTURE</name>
4533 <description>Capture enable</description>
4534 <bitOffset>0</bitOffset>
4535 <bitWidth>1</bitWidth>
4536 </field>
4537 </fields>
4538 </register>
4539 <register>
4540 <name>SR</name>
4541 <displayName>SR</displayName>
4542 <description>status register</description>
4543 <addressOffset>0x4</addressOffset>
4544 <size>0x20</size>
4545 <access>read-only</access>
4546 <resetValue>0x0000</resetValue>
4547 <fields>
4548 <field>
4549 <name>FNE</name>
4550 <description>FIFO not empty</description>
4551 <bitOffset>2</bitOffset>
4552 <bitWidth>1</bitWidth>
4553 </field>
4554 <field>
4555 <name>VSYNC</name>
4556 <description>VSYNC</description>
4557 <bitOffset>1</bitOffset>
4558 <bitWidth>1</bitWidth>
4559 </field>
4560 <field>
4561 <name>HSYNC</name>
4562 <description>HSYNC</description>
4563 <bitOffset>0</bitOffset>
4564 <bitWidth>1</bitWidth>
4565 </field>
4566 </fields>
4567 </register>
4568 <register>
4569 <name>RIS</name>
4570 <displayName>RIS</displayName>
4571 <description>raw interrupt status register</description>
4572 <addressOffset>0x8</addressOffset>
4573 <size>0x20</size>
4574 <access>read-only</access>
4575 <resetValue>0x0000</resetValue>
4576 <fields>
4577 <field>
4578 <name>LINE_RIS</name>
4579 <description>Line raw interrupt status</description>
4580 <bitOffset>4</bitOffset>
4581 <bitWidth>1</bitWidth>
4582 </field>
4583 <field>
4584 <name>VSYNC_RIS</name>
4585 <description>VSYNC raw interrupt status</description>
4586 <bitOffset>3</bitOffset>
4587 <bitWidth>1</bitWidth>
4588 </field>
4589 <field>
4590 <name>ERR_RIS</name>
4591 <description>Synchronization error raw interrupt
4592 status</description>
4593 <bitOffset>2</bitOffset>
4594 <bitWidth>1</bitWidth>
4595 </field>
4596 <field>
4597 <name>OVR_RIS</name>
4598 <description>Overrun raw interrupt
4599 status</description>
4600 <bitOffset>1</bitOffset>
4601 <bitWidth>1</bitWidth>
4602 </field>
4603 <field>
4604 <name>FRAME_RIS</name>
4605 <description>Capture complete raw interrupt
4606 status</description>
4607 <bitOffset>0</bitOffset>
4608 <bitWidth>1</bitWidth>
4609 </field>
4610 </fields>
4611 </register>
4612 <register>
4613 <name>IER</name>
4614 <displayName>IER</displayName>
4615 <description>interrupt enable register</description>
4616 <addressOffset>0xC</addressOffset>
4617 <size>0x20</size>
4618 <access>read-write</access>
4619 <resetValue>0x0000</resetValue>
4620 <fields>
4621 <field>
4622 <name>LINE_IE</name>
4623 <description>Line interrupt enable</description>
4624 <bitOffset>4</bitOffset>
4625 <bitWidth>1</bitWidth>
4626 </field>
4627 <field>
4628 <name>VSYNC_IE</name>
4629 <description>VSYNC interrupt enable</description>
4630 <bitOffset>3</bitOffset>
4631 <bitWidth>1</bitWidth>
4632 </field>
4633 <field>
4634 <name>ERR_IE</name>
4635 <description>Synchronization error interrupt
4636 enable</description>
4637 <bitOffset>2</bitOffset>
4638 <bitWidth>1</bitWidth>
4639 </field>
4640 <field>
4641 <name>OVR_IE</name>
4642 <description>Overrun interrupt enable</description>
4643 <bitOffset>1</bitOffset>
4644 <bitWidth>1</bitWidth>
4645 </field>
4646 <field>
4647 <name>FRAME_IE</name>
4648 <description>Capture complete interrupt
4649 enable</description>
4650 <bitOffset>0</bitOffset>
4651 <bitWidth>1</bitWidth>
4652 </field>
4653 </fields>
4654 </register>
4655 <register>
4656 <name>MIS</name>
4657 <displayName>MIS</displayName>
4658 <description>masked interrupt status
4659 register</description>
4660 <addressOffset>0x10</addressOffset>
4661 <size>0x20</size>
4662 <access>read-only</access>
4663 <resetValue>0x0000</resetValue>
4664 <fields>
4665 <field>
4666 <name>LINE_MIS</name>
4667 <description>Line masked interrupt
4668 status</description>
4669 <bitOffset>4</bitOffset>
4670 <bitWidth>1</bitWidth>
4671 </field>
4672 <field>
4673 <name>VSYNC_MIS</name>
4674 <description>VSYNC masked interrupt
4675 status</description>
4676 <bitOffset>3</bitOffset>
4677 <bitWidth>1</bitWidth>
4678 </field>
4679 <field>
4680 <name>ERR_MIS</name>
4681 <description>Synchronization error masked interrupt
4682 status</description>
4683 <bitOffset>2</bitOffset>
4684 <bitWidth>1</bitWidth>
4685 </field>
4686 <field>
4687 <name>OVR_MIS</name>
4688 <description>Overrun masked interrupt
4689 status</description>
4690 <bitOffset>1</bitOffset>
4691 <bitWidth>1</bitWidth>
4692 </field>
4693 <field>
4694 <name>FRAME_MIS</name>
4695 <description>Capture complete masked interrupt
4696 status</description>
4697 <bitOffset>0</bitOffset>
4698 <bitWidth>1</bitWidth>
4699 </field>
4700 </fields>
4701 </register>
4702 <register>
4703 <name>ICR</name>
4704 <displayName>ICR</displayName>
4705 <description>interrupt clear register</description>
4706 <addressOffset>0x14</addressOffset>
4707 <size>0x20</size>
4708 <access>write-only</access>
4709 <resetValue>0x0000</resetValue>
4710 <fields>
4711 <field>
4712 <name>LINE_ISC</name>
4713 <description>line interrupt status
4714 clear</description>
4715 <bitOffset>4</bitOffset>
4716 <bitWidth>1</bitWidth>
4717 </field>
4718 <field>
4719 <name>VSYNC_ISC</name>
4720 <description>Vertical synch interrupt status
4721 clear</description>
4722 <bitOffset>3</bitOffset>
4723 <bitWidth>1</bitWidth>
4724 </field>
4725 <field>
4726 <name>ERR_ISC</name>
4727 <description>Synchronization error interrupt status
4728 clear</description>
4729 <bitOffset>2</bitOffset>
4730 <bitWidth>1</bitWidth>
4731 </field>
4732 <field>
4733 <name>OVR_ISC</name>
4734 <description>Overrun interrupt status
4735 clear</description>
4736 <bitOffset>1</bitOffset>
4737 <bitWidth>1</bitWidth>
4738 </field>
4739 <field>
4740 <name>FRAME_ISC</name>
4741 <description>Capture complete interrupt status
4742 clear</description>
4743 <bitOffset>0</bitOffset>
4744 <bitWidth>1</bitWidth>
4745 </field>
4746 </fields>
4747 </register>
4748 <register>
4749 <name>ESCR</name>
4750 <displayName>ESCR</displayName>
4751 <description>embedded synchronization code
4752 register</description>
4753 <addressOffset>0x18</addressOffset>
4754 <size>0x20</size>
4755 <access>read-write</access>
4756 <resetValue>0x0000</resetValue>
4757 <fields>
4758 <field>
4759 <name>FEC</name>
4760 <description>Frame end delimiter code</description>
4761 <bitOffset>24</bitOffset>
4762 <bitWidth>8</bitWidth>
4763 </field>
4764 <field>
4765 <name>LEC</name>
4766 <description>Line end delimiter code</description>
4767 <bitOffset>16</bitOffset>
4768 <bitWidth>8</bitWidth>
4769 </field>
4770 <field>
4771 <name>LSC</name>
4772 <description>Line start delimiter code</description>
4773 <bitOffset>8</bitOffset>
4774 <bitWidth>8</bitWidth>
4775 </field>
4776 <field>
4777 <name>FSC</name>
4778 <description>Frame start delimiter code</description>
4779 <bitOffset>0</bitOffset>
4780 <bitWidth>8</bitWidth>
4781 </field>
4782 </fields>
4783 </register>
4784 <register>
4785 <name>ESUR</name>
4786 <displayName>ESUR</displayName>
4787 <description>embedded synchronization unmask
4788 register</description>
4789 <addressOffset>0x1C</addressOffset>
4790 <size>0x20</size>
4791 <access>read-write</access>
4792 <resetValue>0x0000</resetValue>
4793 <fields>
4794 <field>
4795 <name>FEU</name>
4796 <description>Frame end delimiter unmask</description>
4797 <bitOffset>24</bitOffset>
4798 <bitWidth>8</bitWidth>
4799 </field>
4800 <field>
4801 <name>LEU</name>
4802 <description>Line end delimiter unmask</description>
4803 <bitOffset>16</bitOffset>
4804 <bitWidth>8</bitWidth>
4805 </field>
4806 <field>
4807 <name>LSU</name>
4808 <description>Line start delimiter
4809 unmask</description>
4810 <bitOffset>8</bitOffset>
4811 <bitWidth>8</bitWidth>
4812 </field>
4813 <field>
4814 <name>FSU</name>
4815 <description>Frame start delimiter
4816 unmask</description>
4817 <bitOffset>0</bitOffset>
4818 <bitWidth>8</bitWidth>
4819 </field>
4820 </fields>
4821 </register>
4822 <register>
4823 <name>CWSTRT</name>
4824 <displayName>CWSTRT</displayName>
4825 <description>crop window start</description>
4826 <addressOffset>0x20</addressOffset>
4827 <size>0x20</size>
4828 <access>read-write</access>
4829 <resetValue>0x0000</resetValue>
4830 <fields>
4831 <field>
4832 <name>VST</name>
4833 <description>Vertical start line count</description>
4834 <bitOffset>16</bitOffset>
4835 <bitWidth>13</bitWidth>
4836 </field>
4837 <field>
4838 <name>HOFFCNT</name>
4839 <description>Horizontal offset count</description>
4840 <bitOffset>0</bitOffset>
4841 <bitWidth>14</bitWidth>
4842 </field>
4843 </fields>
4844 </register>
4845 <register>
4846 <name>CWSIZE</name>
4847 <displayName>CWSIZE</displayName>
4848 <description>crop window size</description>
4849 <addressOffset>0x24</addressOffset>
4850 <size>0x20</size>
4851 <access>read-write</access>
4852 <resetValue>0x0000</resetValue>
4853 <fields>
4854 <field>
4855 <name>VLINE</name>
4856 <description>Vertical line count</description>
4857 <bitOffset>16</bitOffset>
4858 <bitWidth>14</bitWidth>
4859 </field>
4860 <field>
4861 <name>CAPCNT</name>
4862 <description>Capture count</description>
4863 <bitOffset>0</bitOffset>
4864 <bitWidth>14</bitWidth>
4865 </field>
4866 </fields>
4867 </register>
4868 <register>
4869 <name>DR</name>
4870 <displayName>DR</displayName>
4871 <description>data register</description>
4872 <addressOffset>0x28</addressOffset>
4873 <size>0x20</size>
4874 <access>read-only</access>
4875 <resetValue>0x0000</resetValue>
4876 <fields>
4877 <field>
4878 <name>Byte3</name>
4879 <description>Data byte 3</description>
4880 <bitOffset>24</bitOffset>
4881 <bitWidth>8</bitWidth>
4882 </field>
4883 <field>
4884 <name>Byte2</name>
4885 <description>Data byte 2</description>
4886 <bitOffset>16</bitOffset>
4887 <bitWidth>8</bitWidth>
4888 </field>
4889 <field>
4890 <name>Byte1</name>
4891 <description>Data byte 1</description>
4892 <bitOffset>8</bitOffset>
4893 <bitWidth>8</bitWidth>
4894 </field>
4895 <field>
4896 <name>Byte0</name>
4897 <description>Data byte 0</description>
4898 <bitOffset>0</bitOffset>
4899 <bitWidth>8</bitWidth>
4900 </field>
4901 </fields>
4902 </register>
4903 </registers>
4904 </peripheral>
4905 <peripheral>
4906 <name>FMC</name>
4907 <description>Flexible memory controller</description>
4908 <groupName>FSMC</groupName>
4909 <baseAddress>0xA0000000</baseAddress>
4910 <addressBlock>
4911 <offset>0x0</offset>
4912 <size>0x1000</size>
4913 <usage>registers</usage>
4914 </addressBlock>
4915 <interrupt>
4916 <name>FMC</name>
4917 <description>FMC global interrupt</description>
4918 <value>48</value>
4919 </interrupt>
4920 <registers>
4921 <register>
4922 <name>BCR1</name>
4923 <displayName>BCR1</displayName>
4924 <description>SRAM/NOR-Flash chip-select control register
4925 1</description>
4926 <addressOffset>0x0</addressOffset>
4927 <size>0x20</size>
4928 <access>read-write</access>
4929 <resetValue>0x000030D0</resetValue>
4930 <fields>
4931 <field>
4932 <name>CCLKEN</name>
4933 <description>CCLKEN</description>
4934 <bitOffset>20</bitOffset>
4935 <bitWidth>1</bitWidth>
4936 </field>
4937 <field>
4938 <name>CBURSTRW</name>
4939 <description>CBURSTRW</description>
4940 <bitOffset>19</bitOffset>
4941 <bitWidth>1</bitWidth>
4942 </field>
4943 <field>
4944 <name>ASYNCWAIT</name>
4945 <description>ASYNCWAIT</description>
4946 <bitOffset>15</bitOffset>
4947 <bitWidth>1</bitWidth>
4948 </field>
4949 <field>
4950 <name>EXTMOD</name>
4951 <description>EXTMOD</description>
4952 <bitOffset>14</bitOffset>
4953 <bitWidth>1</bitWidth>
4954 </field>
4955 <field>
4956 <name>WAITEN</name>
4957 <description>WAITEN</description>
4958 <bitOffset>13</bitOffset>
4959 <bitWidth>1</bitWidth>
4960 </field>
4961 <field>
4962 <name>WREN</name>
4963 <description>WREN</description>
4964 <bitOffset>12</bitOffset>
4965 <bitWidth>1</bitWidth>
4966 </field>
4967 <field>
4968 <name>WAITCFG</name>
4969 <description>WAITCFG</description>
4970 <bitOffset>11</bitOffset>
4971 <bitWidth>1</bitWidth>
4972 </field>
4973 <field>
4974 <name>WAITPOL</name>
4975 <description>WAITPOL</description>
4976 <bitOffset>9</bitOffset>
4977 <bitWidth>1</bitWidth>
4978 </field>
4979 <field>
4980 <name>BURSTEN</name>
4981 <description>BURSTEN</description>
4982 <bitOffset>8</bitOffset>
4983 <bitWidth>1</bitWidth>
4984 </field>
4985 <field>
4986 <name>FACCEN</name>
4987 <description>FACCEN</description>
4988 <bitOffset>6</bitOffset>
4989 <bitWidth>1</bitWidth>
4990 </field>
4991 <field>
4992 <name>MWID</name>
4993 <description>MWID</description>
4994 <bitOffset>4</bitOffset>
4995 <bitWidth>2</bitWidth>
4996 </field>
4997 <field>
4998 <name>MTYP</name>
4999 <description>MTYP</description>
5000 <bitOffset>2</bitOffset>
5001 <bitWidth>2</bitWidth>
5002 </field>
5003 <field>
5004 <name>MUXEN</name>
5005 <description>MUXEN</description>
5006 <bitOffset>1</bitOffset>
5007 <bitWidth>1</bitWidth>
5008 </field>
5009 <field>
5010 <name>MBKEN</name>
5011 <description>MBKEN</description>
5012 <bitOffset>0</bitOffset>
5013 <bitWidth>1</bitWidth>
5014 </field>
5015 </fields>
5016 </register>
5017 <register>
5018 <name>BTR1</name>
5019 <displayName>BTR1</displayName>
5020 <description>SRAM/NOR-Flash chip-select timing register
5021 1</description>
5022 <addressOffset>0x4</addressOffset>
5023 <size>0x20</size>
5024 <access>read-write</access>
5025 <resetValue>0xFFFFFFFF</resetValue>
5026 <fields>
5027 <field>
5028 <name>ACCMOD</name>
5029 <description>ACCMOD</description>
5030 <bitOffset>28</bitOffset>
5031 <bitWidth>2</bitWidth>
5032 </field>
5033 <field>
5034 <name>DATLAT</name>
5035 <description>DATLAT</description>
5036 <bitOffset>24</bitOffset>
5037 <bitWidth>4</bitWidth>
5038 </field>
5039 <field>
5040 <name>CLKDIV</name>
5041 <description>CLKDIV</description>
5042 <bitOffset>20</bitOffset>
5043 <bitWidth>4</bitWidth>
5044 </field>
5045 <field>
5046 <name>BUSTURN</name>
5047 <description>BUSTURN</description>
5048 <bitOffset>16</bitOffset>
5049 <bitWidth>4</bitWidth>
5050 </field>
5051 <field>
5052 <name>DATAST</name>
5053 <description>DATAST</description>
5054 <bitOffset>8</bitOffset>
5055 <bitWidth>8</bitWidth>
5056 </field>
5057 <field>
5058 <name>ADDHLD</name>
5059 <description>ADDHLD</description>
5060 <bitOffset>4</bitOffset>
5061 <bitWidth>4</bitWidth>
5062 </field>
5063 <field>
5064 <name>ADDSET</name>
5065 <description>ADDSET</description>
5066 <bitOffset>0</bitOffset>
5067 <bitWidth>4</bitWidth>
5068 </field>
5069 </fields>
5070 </register>
5071 <register>
5072 <name>BCR2</name>
5073 <displayName>BCR2</displayName>
5074 <description>SRAM/NOR-Flash chip-select control register
5075 2</description>
5076 <addressOffset>0x8</addressOffset>
5077 <size>0x20</size>
5078 <access>read-write</access>
5079 <resetValue>0x000030D0</resetValue>
5080 <fields>
5081 <field>
5082 <name>CBURSTRW</name>
5083 <description>CBURSTRW</description>
5084 <bitOffset>19</bitOffset>
5085 <bitWidth>1</bitWidth>
5086 </field>
5087 <field>
5088 <name>ASYNCWAIT</name>
5089 <description>ASYNCWAIT</description>
5090 <bitOffset>15</bitOffset>
5091 <bitWidth>1</bitWidth>
5092 </field>
5093 <field>
5094 <name>EXTMOD</name>
5095 <description>EXTMOD</description>
5096 <bitOffset>14</bitOffset>
5097 <bitWidth>1</bitWidth>
5098 </field>
5099 <field>
5100 <name>WAITEN</name>
5101 <description>WAITEN</description>
5102 <bitOffset>13</bitOffset>
5103 <bitWidth>1</bitWidth>
5104 </field>
5105 <field>
5106 <name>WREN</name>
5107 <description>WREN</description>
5108 <bitOffset>12</bitOffset>
5109 <bitWidth>1</bitWidth>
5110 </field>
5111 <field>
5112 <name>WAITCFG</name>
5113 <description>WAITCFG</description>
5114 <bitOffset>11</bitOffset>
5115 <bitWidth>1</bitWidth>
5116 </field>
5117 <field>
5118 <name>WRAPMOD</name>
5119 <description>WRAPMOD</description>
5120 <bitOffset>10</bitOffset>
5121 <bitWidth>1</bitWidth>
5122 </field>
5123 <field>
5124 <name>WAITPOL</name>
5125 <description>WAITPOL</description>
5126 <bitOffset>9</bitOffset>
5127 <bitWidth>1</bitWidth>
5128 </field>
5129 <field>
5130 <name>BURSTEN</name>
5131 <description>BURSTEN</description>
5132 <bitOffset>8</bitOffset>
5133 <bitWidth>1</bitWidth>
5134 </field>
5135 <field>
5136 <name>FACCEN</name>
5137 <description>FACCEN</description>
5138 <bitOffset>6</bitOffset>
5139 <bitWidth>1</bitWidth>
5140 </field>
5141 <field>
5142 <name>MWID</name>
5143 <description>MWID</description>
5144 <bitOffset>4</bitOffset>
5145 <bitWidth>2</bitWidth>
5146 </field>
5147 <field>
5148 <name>MTYP</name>
5149 <description>MTYP</description>
5150 <bitOffset>2</bitOffset>
5151 <bitWidth>2</bitWidth>
5152 </field>
5153 <field>
5154 <name>MUXEN</name>
5155 <description>MUXEN</description>
5156 <bitOffset>1</bitOffset>
5157 <bitWidth>1</bitWidth>
5158 </field>
5159 <field>
5160 <name>MBKEN</name>
5161 <description>MBKEN</description>
5162 <bitOffset>0</bitOffset>
5163 <bitWidth>1</bitWidth>
5164 </field>
5165 </fields>
5166 </register>
5167 <register>
5168 <name>BTR2</name>
5169 <displayName>BTR2</displayName>
5170 <description>SRAM/NOR-Flash chip-select timing register
5171 2</description>
5172 <addressOffset>0xC</addressOffset>
5173 <size>0x20</size>
5174 <access>read-write</access>
5175 <resetValue>0xFFFFFFFF</resetValue>
5176 <fields>
5177 <field>
5178 <name>ACCMOD</name>
5179 <description>ACCMOD</description>
5180 <bitOffset>28</bitOffset>
5181 <bitWidth>2</bitWidth>
5182 </field>
5183 <field>
5184 <name>DATLAT</name>
5185 <description>DATLAT</description>
5186 <bitOffset>24</bitOffset>
5187 <bitWidth>4</bitWidth>
5188 </field>
5189 <field>
5190 <name>CLKDIV</name>
5191 <description>CLKDIV</description>
5192 <bitOffset>20</bitOffset>
5193 <bitWidth>4</bitWidth>
5194 </field>
5195 <field>
5196 <name>BUSTURN</name>
5197 <description>BUSTURN</description>
5198 <bitOffset>16</bitOffset>
5199 <bitWidth>4</bitWidth>
5200 </field>
5201 <field>
5202 <name>DATAST</name>
5203 <description>DATAST</description>
5204 <bitOffset>8</bitOffset>
5205 <bitWidth>8</bitWidth>
5206 </field>
5207 <field>
5208 <name>ADDHLD</name>
5209 <description>ADDHLD</description>
5210 <bitOffset>4</bitOffset>
5211 <bitWidth>4</bitWidth>
5212 </field>
5213 <field>
5214 <name>ADDSET</name>
5215 <description>ADDSET</description>
5216 <bitOffset>0</bitOffset>
5217 <bitWidth>4</bitWidth>
5218 </field>
5219 </fields>
5220 </register>
5221 <register>
5222 <name>BCR3</name>
5223 <displayName>BCR3</displayName>
5224 <description>SRAM/NOR-Flash chip-select control register
5225 3</description>
5226 <addressOffset>0x10</addressOffset>
5227 <size>0x20</size>
5228 <access>read-write</access>
5229 <resetValue>0x000030D0</resetValue>
5230 <fields>
5231 <field>
5232 <name>CBURSTRW</name>
5233 <description>CBURSTRW</description>
5234 <bitOffset>19</bitOffset>
5235 <bitWidth>1</bitWidth>
5236 </field>
5237 <field>
5238 <name>ASYNCWAIT</name>
5239 <description>ASYNCWAIT</description>
5240 <bitOffset>15</bitOffset>
5241 <bitWidth>1</bitWidth>
5242 </field>
5243 <field>
5244 <name>EXTMOD</name>
5245 <description>EXTMOD</description>
5246 <bitOffset>14</bitOffset>
5247 <bitWidth>1</bitWidth>
5248 </field>
5249 <field>
5250 <name>WAITEN</name>
5251 <description>WAITEN</description>
5252 <bitOffset>13</bitOffset>
5253 <bitWidth>1</bitWidth>
5254 </field>
5255 <field>
5256 <name>WREN</name>
5257 <description>WREN</description>
5258 <bitOffset>12</bitOffset>
5259 <bitWidth>1</bitWidth>
5260 </field>
5261 <field>
5262 <name>WAITCFG</name>
5263 <description>WAITCFG</description>
5264 <bitOffset>11</bitOffset>
5265 <bitWidth>1</bitWidth>
5266 </field>
5267 <field>
5268 <name>WRAPMOD</name>
5269 <description>WRAPMOD</description>
5270 <bitOffset>10</bitOffset>
5271 <bitWidth>1</bitWidth>
5272 </field>
5273 <field>
5274 <name>WAITPOL</name>
5275 <description>WAITPOL</description>
5276 <bitOffset>9</bitOffset>
5277 <bitWidth>1</bitWidth>
5278 </field>
5279 <field>
5280 <name>BURSTEN</name>
5281 <description>BURSTEN</description>
5282 <bitOffset>8</bitOffset>
5283 <bitWidth>1</bitWidth>
5284 </field>
5285 <field>
5286 <name>FACCEN</name>
5287 <description>FACCEN</description>
5288 <bitOffset>6</bitOffset>
5289 <bitWidth>1</bitWidth>
5290 </field>
5291 <field>
5292 <name>MWID</name>
5293 <description>MWID</description>
5294 <bitOffset>4</bitOffset>
5295 <bitWidth>2</bitWidth>
5296 </field>
5297 <field>
5298 <name>MTYP</name>
5299 <description>MTYP</description>
5300 <bitOffset>2</bitOffset>
5301 <bitWidth>2</bitWidth>
5302 </field>
5303 <field>
5304 <name>MUXEN</name>
5305 <description>MUXEN</description>
5306 <bitOffset>1</bitOffset>
5307 <bitWidth>1</bitWidth>
5308 </field>
5309 <field>
5310 <name>MBKEN</name>
5311 <description>MBKEN</description>
5312 <bitOffset>0</bitOffset>
5313 <bitWidth>1</bitWidth>
5314 </field>
5315 </fields>
5316 </register>
5317 <register>
5318 <name>BTR3</name>
5319 <displayName>BTR3</displayName>
5320 <description>SRAM/NOR-Flash chip-select timing register
5321 3</description>
5322 <addressOffset>0x14</addressOffset>
5323 <size>0x20</size>
5324 <access>read-write</access>
5325 <resetValue>0xFFFFFFFF</resetValue>
5326 <fields>
5327 <field>
5328 <name>ACCMOD</name>
5329 <description>ACCMOD</description>
5330 <bitOffset>28</bitOffset>
5331 <bitWidth>2</bitWidth>
5332 </field>
5333 <field>
5334 <name>DATLAT</name>
5335 <description>DATLAT</description>
5336 <bitOffset>24</bitOffset>
5337 <bitWidth>4</bitWidth>
5338 </field>
5339 <field>
5340 <name>CLKDIV</name>
5341 <description>CLKDIV</description>
5342 <bitOffset>20</bitOffset>
5343 <bitWidth>4</bitWidth>
5344 </field>
5345 <field>
5346 <name>BUSTURN</name>
5347 <description>BUSTURN</description>
5348 <bitOffset>16</bitOffset>
5349 <bitWidth>4</bitWidth>
5350 </field>
5351 <field>
5352 <name>DATAST</name>
5353 <description>DATAST</description>
5354 <bitOffset>8</bitOffset>
5355 <bitWidth>8</bitWidth>
5356 </field>
5357 <field>
5358 <name>ADDHLD</name>
5359 <description>ADDHLD</description>
5360 <bitOffset>4</bitOffset>
5361 <bitWidth>4</bitWidth>
5362 </field>
5363 <field>
5364 <name>ADDSET</name>
5365 <description>ADDSET</description>
5366 <bitOffset>0</bitOffset>
5367 <bitWidth>4</bitWidth>
5368 </field>
5369 </fields>
5370 </register>
5371 <register>
5372 <name>BCR4</name>
5373 <displayName>BCR4</displayName>
5374 <description>SRAM/NOR-Flash chip-select control register
5375 4</description>
5376 <addressOffset>0x18</addressOffset>
5377 <size>0x20</size>
5378 <access>read-write</access>
5379 <resetValue>0x000030D0</resetValue>
5380 <fields>
5381 <field>
5382 <name>CBURSTRW</name>
5383 <description>CBURSTRW</description>
5384 <bitOffset>19</bitOffset>
5385 <bitWidth>1</bitWidth>
5386 </field>
5387 <field>
5388 <name>ASYNCWAIT</name>
5389 <description>ASYNCWAIT</description>
5390 <bitOffset>15</bitOffset>
5391 <bitWidth>1</bitWidth>
5392 </field>
5393 <field>
5394 <name>EXTMOD</name>
5395 <description>EXTMOD</description>
5396 <bitOffset>14</bitOffset>
5397 <bitWidth>1</bitWidth>
5398 </field>
5399 <field>
5400 <name>WAITEN</name>
5401 <description>WAITEN</description>
5402 <bitOffset>13</bitOffset>
5403 <bitWidth>1</bitWidth>
5404 </field>
5405 <field>
5406 <name>WREN</name>
5407 <description>WREN</description>
5408 <bitOffset>12</bitOffset>
5409 <bitWidth>1</bitWidth>
5410 </field>
5411 <field>
5412 <name>WAITCFG</name>
5413 <description>WAITCFG</description>
5414 <bitOffset>11</bitOffset>
5415 <bitWidth>1</bitWidth>
5416 </field>
5417 <field>
5418 <name>WRAPMOD</name>
5419 <description>WRAPMOD</description>
5420 <bitOffset>10</bitOffset>
5421 <bitWidth>1</bitWidth>
5422 </field>
5423 <field>
5424 <name>WAITPOL</name>
5425 <description>WAITPOL</description>
5426 <bitOffset>9</bitOffset>
5427 <bitWidth>1</bitWidth>
5428 </field>
5429 <field>
5430 <name>BURSTEN</name>
5431 <description>BURSTEN</description>
5432 <bitOffset>8</bitOffset>
5433 <bitWidth>1</bitWidth>
5434 </field>
5435 <field>
5436 <name>FACCEN</name>
5437 <description>FACCEN</description>
5438 <bitOffset>6</bitOffset>
5439 <bitWidth>1</bitWidth>
5440 </field>
5441 <field>
5442 <name>MWID</name>
5443 <description>MWID</description>
5444 <bitOffset>4</bitOffset>
5445 <bitWidth>2</bitWidth>
5446 </field>
5447 <field>
5448 <name>MTYP</name>
5449 <description>MTYP</description>
5450 <bitOffset>2</bitOffset>
5451 <bitWidth>2</bitWidth>
5452 </field>
5453 <field>
5454 <name>MUXEN</name>
5455 <description>MUXEN</description>
5456 <bitOffset>1</bitOffset>
5457 <bitWidth>1</bitWidth>
5458 </field>
5459 <field>
5460 <name>MBKEN</name>
5461 <description>MBKEN</description>
5462 <bitOffset>0</bitOffset>
5463 <bitWidth>1</bitWidth>
5464 </field>
5465 </fields>
5466 </register>
5467 <register>
5468 <name>BTR4</name>
5469 <displayName>BTR4</displayName>
5470 <description>SRAM/NOR-Flash chip-select timing register
5471 4</description>
5472 <addressOffset>0x1C</addressOffset>
5473 <size>0x20</size>
5474 <access>read-write</access>
5475 <resetValue>0xFFFFFFFF</resetValue>
5476 <fields>
5477 <field>
5478 <name>ACCMOD</name>
5479 <description>ACCMOD</description>
5480 <bitOffset>28</bitOffset>
5481 <bitWidth>2</bitWidth>
5482 </field>
5483 <field>
5484 <name>DATLAT</name>
5485 <description>DATLAT</description>
5486 <bitOffset>24</bitOffset>
5487 <bitWidth>4</bitWidth>
5488 </field>
5489 <field>
5490 <name>CLKDIV</name>
5491 <description>CLKDIV</description>
5492 <bitOffset>20</bitOffset>
5493 <bitWidth>4</bitWidth>
5494 </field>
5495 <field>
5496 <name>BUSTURN</name>
5497 <description>BUSTURN</description>
5498 <bitOffset>16</bitOffset>
5499 <bitWidth>4</bitWidth>
5500 </field>
5501 <field>
5502 <name>DATAST</name>
5503 <description>DATAST</description>
5504 <bitOffset>8</bitOffset>
5505 <bitWidth>8</bitWidth>
5506 </field>
5507 <field>
5508 <name>ADDHLD</name>
5509 <description>ADDHLD</description>
5510 <bitOffset>4</bitOffset>
5511 <bitWidth>4</bitWidth>
5512 </field>
5513 <field>
5514 <name>ADDSET</name>
5515 <description>ADDSET</description>
5516 <bitOffset>0</bitOffset>
5517 <bitWidth>4</bitWidth>
5518 </field>
5519 </fields>
5520 </register>
5521 <register>
5522 <name>PCR</name>
5523 <displayName>PCR</displayName>
5524 <description>PC Card/NAND Flash control
5525 register</description>
5526 <addressOffset>0x80</addressOffset>
5527 <size>0x20</size>
5528 <access>read-write</access>
5529 <resetValue>0x00000018</resetValue>
5530 <fields>
5531 <field>
5532 <name>ECCPS</name>
5533 <description>ECCPS</description>
5534 <bitOffset>17</bitOffset>
5535 <bitWidth>3</bitWidth>
5536 </field>
5537 <field>
5538 <name>TAR</name>
5539 <description>TAR</description>
5540 <bitOffset>13</bitOffset>
5541 <bitWidth>4</bitWidth>
5542 </field>
5543 <field>
5544 <name>TCLR</name>
5545 <description>TCLR</description>
5546 <bitOffset>9</bitOffset>
5547 <bitWidth>4</bitWidth>
5548 </field>
5549 <field>
5550 <name>ECCEN</name>
5551 <description>ECCEN</description>
5552 <bitOffset>6</bitOffset>
5553 <bitWidth>1</bitWidth>
5554 </field>
5555 <field>
5556 <name>PWID</name>
5557 <description>PWID</description>
5558 <bitOffset>4</bitOffset>
5559 <bitWidth>2</bitWidth>
5560 </field>
5561 <field>
5562 <name>PTYP</name>
5563 <description>PTYP</description>
5564 <bitOffset>3</bitOffset>
5565 <bitWidth>1</bitWidth>
5566 </field>
5567 <field>
5568 <name>PBKEN</name>
5569 <description>PBKEN</description>
5570 <bitOffset>2</bitOffset>
5571 <bitWidth>1</bitWidth>
5572 </field>
5573 <field>
5574 <name>PWAITEN</name>
5575 <description>PWAITEN</description>
5576 <bitOffset>1</bitOffset>
5577 <bitWidth>1</bitWidth>
5578 </field>
5579 </fields>
5580 </register>
5581 <register>
5582 <name>SR</name>
5583 <displayName>SR</displayName>
5584 <description>FIFO status and interrupt
5585 register</description>
5586 <addressOffset>0x84</addressOffset>
5587 <size>0x20</size>
5588 <resetValue>0x00000040</resetValue>
5589 <fields>
5590 <field>
5591 <name>FEMPT</name>
5592 <description>FEMPT</description>
5593 <bitOffset>6</bitOffset>
5594 <bitWidth>1</bitWidth>
5595 <access>read-only</access>
5596 </field>
5597 <field>
5598 <name>IFEN</name>
5599 <description>IFEN</description>
5600 <bitOffset>5</bitOffset>
5601 <bitWidth>1</bitWidth>
5602 <access>read-write</access>
5603 </field>
5604 <field>
5605 <name>ILEN</name>
5606 <description>ILEN</description>
5607 <bitOffset>4</bitOffset>
5608 <bitWidth>1</bitWidth>
5609 <access>read-write</access>
5610 </field>
5611 <field>
5612 <name>IREN</name>
5613 <description>IREN</description>
5614 <bitOffset>3</bitOffset>
5615 <bitWidth>1</bitWidth>
5616 <access>read-write</access>
5617 </field>
5618 <field>
5619 <name>IFS</name>
5620 <description>IFS</description>
5621 <bitOffset>2</bitOffset>
5622 <bitWidth>1</bitWidth>
5623 <access>read-write</access>
5624 </field>
5625 <field>
5626 <name>ILS</name>
5627 <description>ILS</description>
5628 <bitOffset>1</bitOffset>
5629 <bitWidth>1</bitWidth>
5630 <access>read-write</access>
5631 </field>
5632 <field>
5633 <name>IRS</name>
5634 <description>IRS</description>
5635 <bitOffset>0</bitOffset>
5636 <bitWidth>1</bitWidth>
5637 <access>read-write</access>
5638 </field>
5639 </fields>
5640 </register>
5641 <register>
5642 <name>PMEM</name>
5643 <displayName>PMEM</displayName>
5644 <description>Common memory space timing
5645 register</description>
5646 <addressOffset>0x88</addressOffset>
5647 <size>0x20</size>
5648 <access>read-write</access>
5649 <resetValue>0xFCFCFCFC</resetValue>
5650 <fields>
5651 <field>
5652 <name>MEMHIZx</name>
5653 <description>MEMHIZx</description>
5654 <bitOffset>24</bitOffset>
5655 <bitWidth>8</bitWidth>
5656 </field>
5657 <field>
5658 <name>MEMHOLDx</name>
5659 <description>MEMHOLDx</description>
5660 <bitOffset>16</bitOffset>
5661 <bitWidth>8</bitWidth>
5662 </field>
5663 <field>
5664 <name>MEMWAITx</name>
5665 <description>MEMWAITx</description>
5666 <bitOffset>8</bitOffset>
5667 <bitWidth>8</bitWidth>
5668 </field>
5669 <field>
5670 <name>MEMSETx</name>
5671 <description>MEMSETx</description>
5672 <bitOffset>0</bitOffset>
5673 <bitWidth>8</bitWidth>
5674 </field>
5675 </fields>
5676 </register>
5677 <register>
5678 <name>PATT</name>
5679 <displayName>PATT</displayName>
5680 <description>Attribute memory space timing
5681 register</description>
5682 <addressOffset>0x8C</addressOffset>
5683 <size>0x20</size>
5684 <access>read-write</access>
5685 <resetValue>0xFCFCFCFC</resetValue>
5686 <fields>
5687 <field>
5688 <name>ATTHIZx</name>
5689 <description>ATTHIZx</description>
5690 <bitOffset>24</bitOffset>
5691 <bitWidth>8</bitWidth>
5692 </field>
5693 <field>
5694 <name>ATTHOLDx</name>
5695 <description>ATTHOLDx</description>
5696 <bitOffset>16</bitOffset>
5697 <bitWidth>8</bitWidth>
5698 </field>
5699 <field>
5700 <name>ATTWAITx</name>
5701 <description>ATTWAITx</description>
5702 <bitOffset>8</bitOffset>
5703 <bitWidth>8</bitWidth>
5704 </field>
5705 <field>
5706 <name>ATTSETx</name>
5707 <description>ATTSETx</description>
5708 <bitOffset>0</bitOffset>
5709 <bitWidth>8</bitWidth>
5710 </field>
5711 </fields>
5712 </register>
5713 <register>
5714 <name>ECCR</name>
5715 <displayName>ECCR</displayName>
5716 <description>ECC result register</description>
5717 <addressOffset>0x94</addressOffset>
5718 <size>0x20</size>
5719 <access>read-only</access>
5720 <resetValue>0x00000000</resetValue>
5721 <fields>
5722 <field>
5723 <name>ECCx</name>
5724 <description>ECCx</description>
5725 <bitOffset>0</bitOffset>
5726 <bitWidth>32</bitWidth>
5727 </field>
5728 </fields>
5729 </register>
5730 <register>
5731 <name>BWTR1</name>
5732 <displayName>BWTR1</displayName>
5733 <description>SRAM/NOR-Flash write timing registers
5734 1</description>
5735 <addressOffset>0x104</addressOffset>
5736 <size>0x20</size>
5737 <access>read-write</access>
5738 <resetValue>0x0FFFFFFF</resetValue>
5739 <fields>
5740 <field>
5741 <name>ACCMOD</name>
5742 <description>ACCMOD</description>
5743 <bitOffset>28</bitOffset>
5744 <bitWidth>2</bitWidth>
5745 </field>
5746 <field>
5747 <name>DATLAT</name>
5748 <description>DATLAT</description>
5749 <bitOffset>24</bitOffset>
5750 <bitWidth>4</bitWidth>
5751 </field>
5752 <field>
5753 <name>CLKDIV</name>
5754 <description>CLKDIV</description>
5755 <bitOffset>20</bitOffset>
5756 <bitWidth>4</bitWidth>
5757 </field>
5758 <field>
5759 <name>DATAST</name>
5760 <description>DATAST</description>
5761 <bitOffset>8</bitOffset>
5762 <bitWidth>8</bitWidth>
5763 </field>
5764 <field>
5765 <name>ADDHLD</name>
5766 <description>ADDHLD</description>
5767 <bitOffset>4</bitOffset>
5768 <bitWidth>4</bitWidth>
5769 </field>
5770 <field>
5771 <name>ADDSET</name>
5772 <description>ADDSET</description>
5773 <bitOffset>0</bitOffset>
5774 <bitWidth>4</bitWidth>
5775 </field>
5776 </fields>
5777 </register>
5778 <register>
5779 <name>BWTR2</name>
5780 <displayName>BWTR2</displayName>
5781 <description>SRAM/NOR-Flash write timing registers
5782 2</description>
5783 <addressOffset>0x10C</addressOffset>
5784 <size>0x20</size>
5785 <access>read-write</access>
5786 <resetValue>0x0FFFFFFF</resetValue>
5787 <fields>
5788 <field>
5789 <name>ACCMOD</name>
5790 <description>ACCMOD</description>
5791 <bitOffset>28</bitOffset>
5792 <bitWidth>2</bitWidth>
5793 </field>
5794 <field>
5795 <name>DATLAT</name>
5796 <description>DATLAT</description>
5797 <bitOffset>24</bitOffset>
5798 <bitWidth>4</bitWidth>
5799 </field>
5800 <field>
5801 <name>CLKDIV</name>
5802 <description>CLKDIV</description>
5803 <bitOffset>20</bitOffset>
5804 <bitWidth>4</bitWidth>
5805 </field>
5806 <field>
5807 <name>DATAST</name>
5808 <description>DATAST</description>
5809 <bitOffset>8</bitOffset>
5810 <bitWidth>8</bitWidth>
5811 </field>
5812 <field>
5813 <name>ADDHLD</name>
5814 <description>ADDHLD</description>
5815 <bitOffset>4</bitOffset>
5816 <bitWidth>4</bitWidth>
5817 </field>
5818 <field>
5819 <name>ADDSET</name>
5820 <description>ADDSET</description>
5821 <bitOffset>0</bitOffset>
5822 <bitWidth>4</bitWidth>
5823 </field>
5824 </fields>
5825 </register>
5826 <register>
5827 <name>BWTR3</name>
5828 <displayName>BWTR3</displayName>
5829 <description>SRAM/NOR-Flash write timing registers
5830 3</description>
5831 <addressOffset>0x114</addressOffset>
5832 <size>0x20</size>
5833 <access>read-write</access>
5834 <resetValue>0x0FFFFFFF</resetValue>
5835 <fields>
5836 <field>
5837 <name>ACCMOD</name>
5838 <description>ACCMOD</description>
5839 <bitOffset>28</bitOffset>
5840 <bitWidth>2</bitWidth>
5841 </field>
5842 <field>
5843 <name>DATLAT</name>
5844 <description>DATLAT</description>
5845 <bitOffset>24</bitOffset>
5846 <bitWidth>4</bitWidth>
5847 </field>
5848 <field>
5849 <name>CLKDIV</name>
5850 <description>CLKDIV</description>
5851 <bitOffset>20</bitOffset>
5852 <bitWidth>4</bitWidth>
5853 </field>
5854 <field>
5855 <name>DATAST</name>
5856 <description>DATAST</description>
5857 <bitOffset>8</bitOffset>
5858 <bitWidth>8</bitWidth>
5859 </field>
5860 <field>
5861 <name>ADDHLD</name>
5862 <description>ADDHLD</description>
5863 <bitOffset>4</bitOffset>
5864 <bitWidth>4</bitWidth>
5865 </field>
5866 <field>
5867 <name>ADDSET</name>
5868 <description>ADDSET</description>
5869 <bitOffset>0</bitOffset>
5870 <bitWidth>4</bitWidth>
5871 </field>
5872 </fields>
5873 </register>
5874 <register>
5875 <name>BWTR4</name>
5876 <displayName>BWTR4</displayName>
5877 <description>SRAM/NOR-Flash write timing registers
5878 4</description>
5879 <addressOffset>0x11C</addressOffset>
5880 <size>0x20</size>
5881 <access>read-write</access>
5882 <resetValue>0x0FFFFFFF</resetValue>
5883 <fields>
5884 <field>
5885 <name>ACCMOD</name>
5886 <description>ACCMOD</description>
5887 <bitOffset>28</bitOffset>
5888 <bitWidth>2</bitWidth>
5889 </field>
5890 <field>
5891 <name>DATLAT</name>
5892 <description>DATLAT</description>
5893 <bitOffset>24</bitOffset>
5894 <bitWidth>4</bitWidth>
5895 </field>
5896 <field>
5897 <name>CLKDIV</name>
5898 <description>CLKDIV</description>
5899 <bitOffset>20</bitOffset>
5900 <bitWidth>4</bitWidth>
5901 </field>
5902 <field>
5903 <name>DATAST</name>
5904 <description>DATAST</description>
5905 <bitOffset>8</bitOffset>
5906 <bitWidth>8</bitWidth>
5907 </field>
5908 <field>
5909 <name>ADDHLD</name>
5910 <description>ADDHLD</description>
5911 <bitOffset>4</bitOffset>
5912 <bitWidth>4</bitWidth>
5913 </field>
5914 <field>
5915 <name>ADDSET</name>
5916 <description>ADDSET</description>
5917 <bitOffset>0</bitOffset>
5918 <bitWidth>4</bitWidth>
5919 </field>
5920 </fields>
5921 </register>
5922 <register>
5923 <name>SDCR1</name>
5924 <displayName>SDCR1</displayName>
5925 <description>SDRAM Control Register 1</description>
5926 <addressOffset>0x140</addressOffset>
5927 <size>0x20</size>
5928 <access>read-write</access>
5929 <resetValue>0x000002D0</resetValue>
5930 <fields>
5931 <field>
5932 <name>NC</name>
5933 <description>Number of column address
5934 bits</description>
5935 <bitOffset>0</bitOffset>
5936 <bitWidth>2</bitWidth>
5937 </field>
5938 <field>
5939 <name>NR</name>
5940 <description>Number of row address bits</description>
5941 <bitOffset>2</bitOffset>
5942 <bitWidth>2</bitWidth>
5943 </field>
5944 <field>
5945 <name>MWID</name>
5946 <description>Memory data bus width</description>
5947 <bitOffset>4</bitOffset>
5948 <bitWidth>2</bitWidth>
5949 </field>
5950 <field>
5951 <name>NB</name>
5952 <description>Number of internal banks</description>
5953 <bitOffset>6</bitOffset>
5954 <bitWidth>1</bitWidth>
5955 </field>
5956 <field>
5957 <name>CAS</name>
5958 <description>CAS latency</description>
5959 <bitOffset>7</bitOffset>
5960 <bitWidth>2</bitWidth>
5961 </field>
5962 <field>
5963 <name>WP</name>
5964 <description>Write protection</description>
5965 <bitOffset>9</bitOffset>
5966 <bitWidth>1</bitWidth>
5967 </field>
5968 <field>
5969 <name>SDCLK</name>
5970 <description>SDRAM clock configuration</description>
5971 <bitOffset>10</bitOffset>
5972 <bitWidth>2</bitWidth>
5973 </field>
5974 <field>
5975 <name>RBURST</name>
5976 <description>Burst read</description>
5977 <bitOffset>12</bitOffset>
5978 <bitWidth>1</bitWidth>
5979 </field>
5980 <field>
5981 <name>RPIPE</name>
5982 <description>Read pipe</description>
5983 <bitOffset>13</bitOffset>
5984 <bitWidth>2</bitWidth>
5985 </field>
5986 </fields>
5987 </register>
5988 <register>
5989 <name>SDCR2</name>
5990 <displayName>SDCR2</displayName>
5991 <description>SDRAM Control Register 2</description>
5992 <addressOffset>0x144</addressOffset>
5993 <size>0x20</size>
5994 <access>read-write</access>
5995 <resetValue>0x000002D0</resetValue>
5996 <fields>
5997 <field>
5998 <name>NC</name>
5999 <description>Number of column address
6000 bits</description>
6001 <bitOffset>0</bitOffset>
6002 <bitWidth>2</bitWidth>
6003 </field>
6004 <field>
6005 <name>NR</name>
6006 <description>Number of row address bits</description>
6007 <bitOffset>2</bitOffset>
6008 <bitWidth>2</bitWidth>
6009 </field>
6010 <field>
6011 <name>MWID</name>
6012 <description>Memory data bus width</description>
6013 <bitOffset>4</bitOffset>
6014 <bitWidth>2</bitWidth>
6015 </field>
6016 <field>
6017 <name>NB</name>
6018 <description>Number of internal banks</description>
6019 <bitOffset>6</bitOffset>
6020 <bitWidth>1</bitWidth>
6021 </field>
6022 <field>
6023 <name>CAS</name>
6024 <description>CAS latency</description>
6025 <bitOffset>7</bitOffset>
6026 <bitWidth>2</bitWidth>
6027 </field>
6028 <field>
6029 <name>WP</name>
6030 <description>Write protection</description>
6031 <bitOffset>9</bitOffset>
6032 <bitWidth>1</bitWidth>
6033 </field>
6034 <field>
6035 <name>SDCLK</name>
6036 <description>SDRAM clock configuration</description>
6037 <bitOffset>10</bitOffset>
6038 <bitWidth>2</bitWidth>
6039 </field>
6040 <field>
6041 <name>RBURST</name>
6042 <description>Burst read</description>
6043 <bitOffset>12</bitOffset>
6044 <bitWidth>1</bitWidth>
6045 </field>
6046 <field>
6047 <name>RPIPE</name>
6048 <description>Read pipe</description>
6049 <bitOffset>13</bitOffset>
6050 <bitWidth>2</bitWidth>
6051 </field>
6052 </fields>
6053 </register>
6054 <register>
6055 <name>SDTR1</name>
6056 <displayName>SDTR1</displayName>
6057 <description>SDRAM Timing register 1</description>
6058 <addressOffset>0x148</addressOffset>
6059 <size>0x20</size>
6060 <access>read-write</access>
6061 <resetValue>0x0FFFFFFF</resetValue>
6062 <fields>
6063 <field>
6064 <name>TMRD</name>
6065 <description>Load Mode Register to
6066 Active</description>
6067 <bitOffset>0</bitOffset>
6068 <bitWidth>4</bitWidth>
6069 </field>
6070 <field>
6071 <name>TXSR</name>
6072 <description>Exit self-refresh delay</description>
6073 <bitOffset>4</bitOffset>
6074 <bitWidth>4</bitWidth>
6075 </field>
6076 <field>
6077 <name>TRAS</name>
6078 <description>Self refresh time</description>
6079 <bitOffset>8</bitOffset>
6080 <bitWidth>4</bitWidth>
6081 </field>
6082 <field>
6083 <name>TRC</name>
6084 <description>Row cycle delay</description>
6085 <bitOffset>12</bitOffset>
6086 <bitWidth>4</bitWidth>
6087 </field>
6088 <field>
6089 <name>TWR</name>
6090 <description>Recovery delay</description>
6091 <bitOffset>16</bitOffset>
6092 <bitWidth>4</bitWidth>
6093 </field>
6094 <field>
6095 <name>TRP</name>
6096 <description>Row precharge delay</description>
6097 <bitOffset>20</bitOffset>
6098 <bitWidth>4</bitWidth>
6099 </field>
6100 <field>
6101 <name>TRCD</name>
6102 <description>Row to column delay</description>
6103 <bitOffset>24</bitOffset>
6104 <bitWidth>4</bitWidth>
6105 </field>
6106 </fields>
6107 </register>
6108 <register>
6109 <name>SDTR2</name>
6110 <displayName>SDTR2</displayName>
6111 <description>SDRAM Timing register 2</description>
6112 <addressOffset>0x14C</addressOffset>
6113 <size>0x20</size>
6114 <access>read-write</access>
6115 <resetValue>0x0FFFFFFF</resetValue>
6116 <fields>
6117 <field>
6118 <name>TMRD</name>
6119 <description>Load Mode Register to
6120 Active</description>
6121 <bitOffset>0</bitOffset>
6122 <bitWidth>4</bitWidth>
6123 </field>
6124 <field>
6125 <name>TXSR</name>
6126 <description>Exit self-refresh delay</description>
6127 <bitOffset>4</bitOffset>
6128 <bitWidth>4</bitWidth>
6129 </field>
6130 <field>
6131 <name>TRAS</name>
6132 <description>Self refresh time</description>
6133 <bitOffset>8</bitOffset>
6134 <bitWidth>4</bitWidth>
6135 </field>
6136 <field>
6137 <name>TRC</name>
6138 <description>Row cycle delay</description>
6139 <bitOffset>12</bitOffset>
6140 <bitWidth>4</bitWidth>
6141 </field>
6142 <field>
6143 <name>TWR</name>
6144 <description>Recovery delay</description>
6145 <bitOffset>16</bitOffset>
6146 <bitWidth>4</bitWidth>
6147 </field>
6148 <field>
6149 <name>TRP</name>
6150 <description>Row precharge delay</description>
6151 <bitOffset>20</bitOffset>
6152 <bitWidth>4</bitWidth>
6153 </field>
6154 <field>
6155 <name>TRCD</name>
6156 <description>Row to column delay</description>
6157 <bitOffset>24</bitOffset>
6158 <bitWidth>4</bitWidth>
6159 </field>
6160 </fields>
6161 </register>
6162 <register>
6163 <name>SDCMR</name>
6164 <displayName>SDCMR</displayName>
6165 <description>SDRAM Command Mode register</description>
6166 <addressOffset>0x150</addressOffset>
6167 <size>0x20</size>
6168 <resetValue>0x00000000</resetValue>
6169 <fields>
6170 <field>
6171 <name>MODE</name>
6172 <description>Command mode</description>
6173 <bitOffset>0</bitOffset>
6174 <bitWidth>3</bitWidth>
6175 <access>write-only</access>
6176 </field>
6177 <field>
6178 <name>CTB2</name>
6179 <description>Command target bank 2</description>
6180 <bitOffset>3</bitOffset>
6181 <bitWidth>1</bitWidth>
6182 <access>write-only</access>
6183 </field>
6184 <field>
6185 <name>CTB1</name>
6186 <description>Command target bank 1</description>
6187 <bitOffset>4</bitOffset>
6188 <bitWidth>1</bitWidth>
6189 <access>write-only</access>
6190 </field>
6191 <field>
6192 <name>NRFS</name>
6193 <description>Number of Auto-refresh</description>
6194 <bitOffset>5</bitOffset>
6195 <bitWidth>4</bitWidth>
6196 <access>read-write</access>
6197 </field>
6198 <field>
6199 <name>MRD</name>
6200 <description>Mode Register definition</description>
6201 <bitOffset>9</bitOffset>
6202 <bitWidth>13</bitWidth>
6203 <access>read-write</access>
6204 </field>
6205 </fields>
6206 </register>
6207 <register>
6208 <name>SDRTR</name>
6209 <displayName>SDRTR</displayName>
6210 <description>SDRAM Refresh Timer register</description>
6211 <addressOffset>0x154</addressOffset>
6212 <size>0x20</size>
6213 <resetValue>0x00000000</resetValue>
6214 <fields>
6215 <field>
6216 <name>CRE</name>
6217 <description>Clear Refresh error flag</description>
6218 <bitOffset>0</bitOffset>
6219 <bitWidth>1</bitWidth>
6220 <access>write-only</access>
6221 </field>
6222 <field>
6223 <name>COUNT</name>
6224 <description>Refresh Timer Count</description>
6225 <bitOffset>1</bitOffset>
6226 <bitWidth>13</bitWidth>
6227 <access>read-write</access>
6228 </field>
6229 <field>
6230 <name>REIE</name>
6231 <description>RES Interrupt Enable</description>
6232 <bitOffset>14</bitOffset>
6233 <bitWidth>1</bitWidth>
6234 <access>read-write</access>
6235 </field>
6236 </fields>
6237 </register>
6238 <register>
6239 <name>SDSR</name>
6240 <displayName>SDSR</displayName>
6241 <description>SDRAM Status register</description>
6242 <addressOffset>0x158</addressOffset>
6243 <size>0x20</size>
6244 <access>read-only</access>
6245 <resetValue>0x00000000</resetValue>
6246 <fields>
6247 <field>
6248 <name>RE</name>
6249 <description>Refresh error flag</description>
6250 <bitOffset>0</bitOffset>
6251 <bitWidth>1</bitWidth>
6252 </field>
6253 <field>
6254 <name>MODES1</name>
6255 <description>Status Mode for Bank 1</description>
6256 <bitOffset>1</bitOffset>
6257 <bitWidth>2</bitWidth>
6258 </field>
6259 <field>
6260 <name>MODES2</name>
6261 <description>Status Mode for Bank 2</description>
6262 <bitOffset>3</bitOffset>
6263 <bitWidth>2</bitWidth>
6264 </field>
6265 <field>
6266 <name>BUSY</name>
6267 <description>Busy status</description>
6268 <bitOffset>5</bitOffset>
6269 <bitWidth>1</bitWidth>
6270 </field>
6271 </fields>
6272 </register>
6273 </registers>
6274 </peripheral>
6275 <peripheral>
6276 <name>DBG</name>
6277 <description>Debug support</description>
6278 <groupName>DBG</groupName>
6279 <baseAddress>0xE0042000</baseAddress>
6280 <addressBlock>
6281 <offset>0x0</offset>
6282 <size>0x400</size>
6283 <usage>registers</usage>
6284 </addressBlock>
6285 <registers>
6286 <register>
6287 <name>DBGMCU_IDCODE</name>
6288 <displayName>DBGMCU_IDCODE</displayName>
6289 <description>IDCODE</description>
6290 <addressOffset>0x0</addressOffset>
6291 <size>0x20</size>
6292 <access>read-only</access>
6293 <resetValue>0x10006411</resetValue>
6294 <fields>
6295 <field>
6296 <name>DEV_ID</name>
6297 <description>DEV_ID</description>
6298 <bitOffset>0</bitOffset>
6299 <bitWidth>12</bitWidth>
6300 </field>
6301 <field>
6302 <name>REV_ID</name>
6303 <description>REV_ID</description>
6304 <bitOffset>16</bitOffset>
6305 <bitWidth>16</bitWidth>
6306 </field>
6307 </fields>
6308 </register>
6309 <register>
6310 <name>DBGMCU_CR</name>
6311 <displayName>DBGMCU_CR</displayName>
6312 <description>Control Register</description>
6313 <addressOffset>0x4</addressOffset>
6314 <size>0x20</size>
6315 <access>read-write</access>
6316 <resetValue>0x00000000</resetValue>
6317 <fields>
6318 <field>
6319 <name>DBG_SLEEP</name>
6320 <description>DBG_SLEEP</description>
6321 <bitOffset>0</bitOffset>
6322 <bitWidth>1</bitWidth>
6323 </field>
6324 <field>
6325 <name>DBG_STOP</name>
6326 <description>DBG_STOP</description>
6327 <bitOffset>1</bitOffset>
6328 <bitWidth>1</bitWidth>
6329 </field>
6330 <field>
6331 <name>DBG_STANDBY</name>
6332 <description>DBG_STANDBY</description>
6333 <bitOffset>2</bitOffset>
6334 <bitWidth>1</bitWidth>
6335 </field>
6336 <field>
6337 <name>TRACE_IOEN</name>
6338 <description>TRACE_IOEN</description>
6339 <bitOffset>5</bitOffset>
6340 <bitWidth>1</bitWidth>
6341 </field>
6342 <field>
6343 <name>TRACE_MODE</name>
6344 <description>TRACE_MODE</description>
6345 <bitOffset>6</bitOffset>
6346 <bitWidth>2</bitWidth>
6347 </field>
6348 </fields>
6349 </register>
6350 <register>
6351 <name>DBGMCU_APB1_FZ</name>
6352 <displayName>DBGMCU_APB1_FZ</displayName>
6353 <description>Debug MCU APB1 Freeze registe</description>
6354 <addressOffset>0x8</addressOffset>
6355 <size>0x20</size>
6356 <access>read-write</access>
6357 <resetValue>0x00000000</resetValue>
6358 <fields>
6359 <field>
6360 <name>DBG_TIM2_STOP</name>
6361 <description>DBG_TIM2_STOP</description>
6362 <bitOffset>0</bitOffset>
6363 <bitWidth>1</bitWidth>
6364 </field>
6365 <field>
6366 <name>DBG_TIM3_STOP</name>
6367 <description>DBG_TIM3 _STOP</description>
6368 <bitOffset>1</bitOffset>
6369 <bitWidth>1</bitWidth>
6370 </field>
6371 <field>
6372 <name>DBG_TIM4_STOP</name>
6373 <description>DBG_TIM4_STOP</description>
6374 <bitOffset>2</bitOffset>
6375 <bitWidth>1</bitWidth>
6376 </field>
6377 <field>
6378 <name>DBG_TIM5_STOP</name>
6379 <description>DBG_TIM5_STOP</description>
6380 <bitOffset>3</bitOffset>
6381 <bitWidth>1</bitWidth>
6382 </field>
6383 <field>
6384 <name>DBG_TIM6_STOP</name>
6385 <description>DBG_TIM6_STOP</description>
6386 <bitOffset>4</bitOffset>
6387 <bitWidth>1</bitWidth>
6388 </field>
6389 <field>
6390 <name>DBG_TIM7_STOP</name>
6391 <description>DBG_TIM7_STOP</description>
6392 <bitOffset>5</bitOffset>
6393 <bitWidth>1</bitWidth>
6394 </field>
6395 <field>
6396 <name>DBG_TIM12_STOP</name>
6397 <description>DBG_TIM12_STOP</description>
6398 <bitOffset>6</bitOffset>
6399 <bitWidth>1</bitWidth>
6400 </field>
6401 <field>
6402 <name>DBG_TIM13_STOP</name>
6403 <description>DBG_TIM13_STOP</description>
6404 <bitOffset>7</bitOffset>
6405 <bitWidth>1</bitWidth>
6406 </field>
6407 <field>
6408 <name>DBG_TIM14_STOP</name>
6409 <description>DBG_TIM14_STOP</description>
6410 <bitOffset>8</bitOffset>
6411 <bitWidth>1</bitWidth>
6412 </field>
6413 <field>
6414 <name>DBG_WWDG_STOP</name>
6415 <description>DBG_WWDG_STOP</description>
6416 <bitOffset>11</bitOffset>
6417 <bitWidth>1</bitWidth>
6418 </field>
6419 <field>
6420 <name>DBG_IWDEG_STOP</name>
6421 <description>DBG_IWDEG_STOP</description>
6422 <bitOffset>12</bitOffset>
6423 <bitWidth>1</bitWidth>
6424 </field>
6425 <field>
6426 <name>DBG_J2C1_SMBUS_TIMEOUT</name>
6427 <description>DBG_J2C1_SMBUS_TIMEOUT</description>
6428 <bitOffset>21</bitOffset>
6429 <bitWidth>1</bitWidth>
6430 </field>
6431 <field>
6432 <name>DBG_J2C2_SMBUS_TIMEOUT</name>
6433 <description>DBG_J2C2_SMBUS_TIMEOUT</description>
6434 <bitOffset>22</bitOffset>
6435 <bitWidth>1</bitWidth>
6436 </field>
6437 <field>
6438 <name>DBG_J2C3SMBUS_TIMEOUT</name>
6439 <description>DBG_J2C3SMBUS_TIMEOUT</description>
6440 <bitOffset>23</bitOffset>
6441 <bitWidth>1</bitWidth>
6442 </field>
6443 <field>
6444 <name>DBG_CAN1_STOP</name>
6445 <description>DBG_CAN1_STOP</description>
6446 <bitOffset>25</bitOffset>
6447 <bitWidth>1</bitWidth>
6448 </field>
6449 <field>
6450 <name>DBG_CAN2_STOP</name>
6451 <description>DBG_CAN2_STOP</description>
6452 <bitOffset>26</bitOffset>
6453 <bitWidth>1</bitWidth>
6454 </field>
6455 </fields>
6456 </register>
6457 <register>
6458 <name>DBGMCU_APB2_FZ</name>
6459 <displayName>DBGMCU_APB2_FZ</displayName>
6460 <description>Debug MCU APB2 Freeze registe</description>
6461 <addressOffset>0xC</addressOffset>
6462 <size>0x20</size>
6463 <access>read-write</access>
6464 <resetValue>0x00000000</resetValue>
6465 <fields>
6466 <field>
6467 <name>DBG_TIM1_STOP</name>
6468 <description>TIM1 counter stopped when core is
6469 halted</description>
6470 <bitOffset>0</bitOffset>
6471 <bitWidth>1</bitWidth>
6472 </field>
6473 <field>
6474 <name>DBG_TIM8_STOP</name>
6475 <description>TIM8 counter stopped when core is
6476 halted</description>
6477 <bitOffset>1</bitOffset>
6478 <bitWidth>1</bitWidth>
6479 </field>
6480 <field>
6481 <name>DBG_TIM9_STOP</name>
6482 <description>TIM9 counter stopped when core is
6483 halted</description>
6484 <bitOffset>16</bitOffset>
6485 <bitWidth>1</bitWidth>
6486 </field>
6487 <field>
6488 <name>DBG_TIM10_STOP</name>
6489 <description>TIM10 counter stopped when core is
6490 halted</description>
6491 <bitOffset>17</bitOffset>
6492 <bitWidth>1</bitWidth>
6493 </field>
6494 <field>
6495 <name>DBG_TIM11_STOP</name>
6496 <description>TIM11 counter stopped when core is
6497 halted</description>
6498 <bitOffset>18</bitOffset>
6499 <bitWidth>1</bitWidth>
6500 </field>
6501 </fields>
6502 </register>
6503 </registers>
6504 </peripheral>
6505 <peripheral>
6506 <name>DMA2</name>
6507 <description>DMA controller</description>
6508 <groupName>DMA</groupName>
6509 <baseAddress>0x40026400</baseAddress>
6510 <addressBlock>
6511 <offset>0x0</offset>
6512 <size>0x400</size>
6513 <usage>registers</usage>
6514 </addressBlock>
6515 <interrupt>
6516 <name>DMA2_Stream0</name>
6517 <description>DMA2 Stream0 global interrupt</description>
6518 <value>56</value>
6519 </interrupt>
6520 <interrupt>
6521 <name>DMA2_Stream1</name>
6522 <description>DMA2 Stream1 global interrupt</description>
6523 <value>57</value>
6524 </interrupt>
6525 <interrupt>
6526 <name>DMA2_Stream2</name>
6527 <description>DMA2 Stream2 global interrupt</description>
6528 <value>58</value>
6529 </interrupt>
6530 <interrupt>
6531 <name>DMA2_Stream3</name>
6532 <description>DMA2 Stream3 global interrupt</description>
6533 <value>59</value>
6534 </interrupt>
6535 <interrupt>
6536 <name>DMA2_Stream4</name>
6537 <description>DMA2 Stream4 global interrupt</description>
6538 <value>60</value>
6539 </interrupt>
6540 <interrupt>
6541 <name>DMA2_Stream5</name>
6542 <description>DMA2 Stream5 global interrupt</description>
6543 <value>68</value>
6544 </interrupt>
6545 <interrupt>
6546 <name>DMA2_Stream6</name>
6547 <description>DMA2 Stream6 global interrupt</description>
6548 <value>69</value>
6549 </interrupt>
6550 <interrupt>
6551 <name>DMA2_Stream7</name>
6552 <description>DMA2 Stream7 global interrupt</description>
6553 <value>70</value>
6554 </interrupt>
6555 <registers>
6556 <register>
6557 <name>LISR</name>
6558 <displayName>LISR</displayName>
6559 <description>low interrupt status register</description>
6560 <addressOffset>0x0</addressOffset>
6561 <size>0x20</size>
6562 <access>read-only</access>
6563 <resetValue>0x00000000</resetValue>
6564 <fields>
6565 <field>
6566 <name>TCIF3</name>
6567 <description>Stream x transfer complete interrupt
6568 flag (x = 3..0)</description>
6569 <bitOffset>27</bitOffset>
6570 <bitWidth>1</bitWidth>
6571 </field>
6572 <field>
6573 <name>HTIF3</name>
6574 <description>Stream x half transfer interrupt flag
6575 (x=3..0)</description>
6576 <bitOffset>26</bitOffset>
6577 <bitWidth>1</bitWidth>
6578 </field>
6579 <field>
6580 <name>TEIF3</name>
6581 <description>Stream x transfer error interrupt flag
6582 (x=3..0)</description>
6583 <bitOffset>25</bitOffset>
6584 <bitWidth>1</bitWidth>
6585 </field>
6586 <field>
6587 <name>DMEIF3</name>
6588 <description>Stream x direct mode error interrupt
6589 flag (x=3..0)</description>
6590 <bitOffset>24</bitOffset>
6591 <bitWidth>1</bitWidth>
6592 </field>
6593 <field>
6594 <name>FEIF3</name>
6595 <description>Stream x FIFO error interrupt flag
6596 (x=3..0)</description>
6597 <bitOffset>22</bitOffset>
6598 <bitWidth>1</bitWidth>
6599 </field>
6600 <field>
6601 <name>TCIF2</name>
6602 <description>Stream x transfer complete interrupt
6603 flag (x = 3..0)</description>
6604 <bitOffset>21</bitOffset>
6605 <bitWidth>1</bitWidth>
6606 </field>
6607 <field>
6608 <name>HTIF2</name>
6609 <description>Stream x half transfer interrupt flag
6610 (x=3..0)</description>
6611 <bitOffset>20</bitOffset>
6612 <bitWidth>1</bitWidth>
6613 </field>
6614 <field>
6615 <name>TEIF2</name>
6616 <description>Stream x transfer error interrupt flag
6617 (x=3..0)</description>
6618 <bitOffset>19</bitOffset>
6619 <bitWidth>1</bitWidth>
6620 </field>
6621 <field>
6622 <name>DMEIF2</name>
6623 <description>Stream x direct mode error interrupt
6624 flag (x=3..0)</description>
6625 <bitOffset>18</bitOffset>
6626 <bitWidth>1</bitWidth>
6627 </field>
6628 <field>
6629 <name>FEIF2</name>
6630 <description>Stream x FIFO error interrupt flag
6631 (x=3..0)</description>
6632 <bitOffset>16</bitOffset>
6633 <bitWidth>1</bitWidth>
6634 </field>
6635 <field>
6636 <name>TCIF1</name>
6637 <description>Stream x transfer complete interrupt
6638 flag (x = 3..0)</description>
6639 <bitOffset>11</bitOffset>
6640 <bitWidth>1</bitWidth>
6641 </field>
6642 <field>
6643 <name>HTIF1</name>
6644 <description>Stream x half transfer interrupt flag
6645 (x=3..0)</description>
6646 <bitOffset>10</bitOffset>
6647 <bitWidth>1</bitWidth>
6648 </field>
6649 <field>
6650 <name>TEIF1</name>
6651 <description>Stream x transfer error interrupt flag
6652 (x=3..0)</description>
6653 <bitOffset>9</bitOffset>
6654 <bitWidth>1</bitWidth>
6655 </field>
6656 <field>
6657 <name>DMEIF1</name>
6658 <description>Stream x direct mode error interrupt
6659 flag (x=3..0)</description>
6660 <bitOffset>8</bitOffset>
6661 <bitWidth>1</bitWidth>
6662 </field>
6663 <field>
6664 <name>FEIF1</name>
6665 <description>Stream x FIFO error interrupt flag
6666 (x=3..0)</description>
6667 <bitOffset>6</bitOffset>
6668 <bitWidth>1</bitWidth>
6669 </field>
6670 <field>
6671 <name>TCIF0</name>
6672 <description>Stream x transfer complete interrupt
6673 flag (x = 3..0)</description>
6674 <bitOffset>5</bitOffset>
6675 <bitWidth>1</bitWidth>
6676 </field>
6677 <field>
6678 <name>HTIF0</name>
6679 <description>Stream x half transfer interrupt flag
6680 (x=3..0)</description>
6681 <bitOffset>4</bitOffset>
6682 <bitWidth>1</bitWidth>
6683 </field>
6684 <field>
6685 <name>TEIF0</name>
6686 <description>Stream x transfer error interrupt flag
6687 (x=3..0)</description>
6688 <bitOffset>3</bitOffset>
6689 <bitWidth>1</bitWidth>
6690 </field>
6691 <field>
6692 <name>DMEIF0</name>
6693 <description>Stream x direct mode error interrupt
6694 flag (x=3..0)</description>
6695 <bitOffset>2</bitOffset>
6696 <bitWidth>1</bitWidth>
6697 </field>
6698 <field>
6699 <name>FEIF0</name>
6700 <description>Stream x FIFO error interrupt flag
6701 (x=3..0)</description>
6702 <bitOffset>0</bitOffset>
6703 <bitWidth>1</bitWidth>
6704 </field>
6705 </fields>
6706 </register>
6707 <register>
6708 <name>HISR</name>
6709 <displayName>HISR</displayName>
6710 <description>high interrupt status register</description>
6711 <addressOffset>0x4</addressOffset>
6712 <size>0x20</size>
6713 <access>read-only</access>
6714 <resetValue>0x00000000</resetValue>
6715 <fields>
6716 <field>
6717 <name>TCIF7</name>
6718 <description>Stream x transfer complete interrupt
6719 flag (x=7..4)</description>
6720 <bitOffset>27</bitOffset>
6721 <bitWidth>1</bitWidth>
6722 </field>
6723 <field>
6724 <name>HTIF7</name>
6725 <description>Stream x half transfer interrupt flag
6726 (x=7..4)</description>
6727 <bitOffset>26</bitOffset>
6728 <bitWidth>1</bitWidth>
6729 </field>
6730 <field>
6731 <name>TEIF7</name>
6732 <description>Stream x transfer error interrupt flag
6733 (x=7..4)</description>
6734 <bitOffset>25</bitOffset>
6735 <bitWidth>1</bitWidth>
6736 </field>
6737 <field>
6738 <name>DMEIF7</name>
6739 <description>Stream x direct mode error interrupt
6740 flag (x=7..4)</description>
6741 <bitOffset>24</bitOffset>
6742 <bitWidth>1</bitWidth>
6743 </field>
6744 <field>
6745 <name>FEIF7</name>
6746 <description>Stream x FIFO error interrupt flag
6747 (x=7..4)</description>
6748 <bitOffset>22</bitOffset>
6749 <bitWidth>1</bitWidth>
6750 </field>
6751 <field>
6752 <name>TCIF6</name>
6753 <description>Stream x transfer complete interrupt
6754 flag (x=7..4)</description>
6755 <bitOffset>21</bitOffset>
6756 <bitWidth>1</bitWidth>
6757 </field>
6758 <field>
6759 <name>HTIF6</name>
6760 <description>Stream x half transfer interrupt flag
6761 (x=7..4)</description>
6762 <bitOffset>20</bitOffset>
6763 <bitWidth>1</bitWidth>
6764 </field>
6765 <field>
6766 <name>TEIF6</name>
6767 <description>Stream x transfer error interrupt flag
6768 (x=7..4)</description>
6769 <bitOffset>19</bitOffset>
6770 <bitWidth>1</bitWidth>
6771 </field>
6772 <field>
6773 <name>DMEIF6</name>
6774 <description>Stream x direct mode error interrupt
6775 flag (x=7..4)</description>
6776 <bitOffset>18</bitOffset>
6777 <bitWidth>1</bitWidth>
6778 </field>
6779 <field>
6780 <name>FEIF6</name>
6781 <description>Stream x FIFO error interrupt flag
6782 (x=7..4)</description>
6783 <bitOffset>16</bitOffset>
6784 <bitWidth>1</bitWidth>
6785 </field>
6786 <field>
6787 <name>TCIF5</name>
6788 <description>Stream x transfer complete interrupt
6789 flag (x=7..4)</description>
6790 <bitOffset>11</bitOffset>
6791 <bitWidth>1</bitWidth>
6792 </field>
6793 <field>
6794 <name>HTIF5</name>
6795 <description>Stream x half transfer interrupt flag
6796 (x=7..4)</description>
6797 <bitOffset>10</bitOffset>
6798 <bitWidth>1</bitWidth>
6799 </field>
6800 <field>
6801 <name>TEIF5</name>
6802 <description>Stream x transfer error interrupt flag
6803 (x=7..4)</description>
6804 <bitOffset>9</bitOffset>
6805 <bitWidth>1</bitWidth>
6806 </field>
6807 <field>
6808 <name>DMEIF5</name>
6809 <description>Stream x direct mode error interrupt
6810 flag (x=7..4)</description>
6811 <bitOffset>8</bitOffset>
6812 <bitWidth>1</bitWidth>
6813 </field>
6814 <field>
6815 <name>FEIF5</name>
6816 <description>Stream x FIFO error interrupt flag
6817 (x=7..4)</description>
6818 <bitOffset>6</bitOffset>
6819 <bitWidth>1</bitWidth>
6820 </field>
6821 <field>
6822 <name>TCIF4</name>
6823 <description>Stream x transfer complete interrupt
6824 flag (x=7..4)</description>
6825 <bitOffset>5</bitOffset>
6826 <bitWidth>1</bitWidth>
6827 </field>
6828 <field>
6829 <name>HTIF4</name>
6830 <description>Stream x half transfer interrupt flag
6831 (x=7..4)</description>
6832 <bitOffset>4</bitOffset>
6833 <bitWidth>1</bitWidth>
6834 </field>
6835 <field>
6836 <name>TEIF4</name>
6837 <description>Stream x transfer error interrupt flag
6838 (x=7..4)</description>
6839 <bitOffset>3</bitOffset>
6840 <bitWidth>1</bitWidth>
6841 </field>
6842 <field>
6843 <name>DMEIF4</name>
6844 <description>Stream x direct mode error interrupt
6845 flag (x=7..4)</description>
6846 <bitOffset>2</bitOffset>
6847 <bitWidth>1</bitWidth>
6848 </field>
6849 <field>
6850 <name>FEIF4</name>
6851 <description>Stream x FIFO error interrupt flag
6852 (x=7..4)</description>
6853 <bitOffset>0</bitOffset>
6854 <bitWidth>1</bitWidth>
6855 </field>
6856 </fields>
6857 </register>
6858 <register>
6859 <name>LIFCR</name>
6860 <displayName>LIFCR</displayName>
6861 <description>low interrupt flag clear
6862 register</description>
6863 <addressOffset>0x8</addressOffset>
6864 <size>0x20</size>
6865 <access>read-write</access>
6866 <resetValue>0x00000000</resetValue>
6867 <fields>
6868 <field>
6869 <name>CTCIF3</name>
6870 <description>Stream x clear transfer complete
6871 interrupt flag (x = 3..0)</description>
6872 <bitOffset>27</bitOffset>
6873 <bitWidth>1</bitWidth>
6874 </field>
6875 <field>
6876 <name>CHTIF3</name>
6877 <description>Stream x clear half transfer interrupt
6878 flag (x = 3..0)</description>
6879 <bitOffset>26</bitOffset>
6880 <bitWidth>1</bitWidth>
6881 </field>
6882 <field>
6883 <name>CTEIF3</name>
6884 <description>Stream x clear transfer error interrupt
6885 flag (x = 3..0)</description>
6886 <bitOffset>25</bitOffset>
6887 <bitWidth>1</bitWidth>
6888 </field>
6889 <field>
6890 <name>CDMEIF3</name>
6891 <description>Stream x clear direct mode error
6892 interrupt flag (x = 3..0)</description>
6893 <bitOffset>24</bitOffset>
6894 <bitWidth>1</bitWidth>
6895 </field>
6896 <field>
6897 <name>CFEIF3</name>
6898 <description>Stream x clear FIFO error interrupt flag
6899 (x = 3..0)</description>
6900 <bitOffset>22</bitOffset>
6901 <bitWidth>1</bitWidth>
6902 </field>
6903 <field>
6904 <name>CTCIF2</name>
6905 <description>Stream x clear transfer complete
6906 interrupt flag (x = 3..0)</description>
6907 <bitOffset>21</bitOffset>
6908 <bitWidth>1</bitWidth>
6909 </field>
6910 <field>
6911 <name>CHTIF2</name>
6912 <description>Stream x clear half transfer interrupt
6913 flag (x = 3..0)</description>
6914 <bitOffset>20</bitOffset>
6915 <bitWidth>1</bitWidth>
6916 </field>
6917 <field>
6918 <name>CTEIF2</name>
6919 <description>Stream x clear transfer error interrupt
6920 flag (x = 3..0)</description>
6921 <bitOffset>19</bitOffset>
6922 <bitWidth>1</bitWidth>
6923 </field>
6924 <field>
6925 <name>CDMEIF2</name>
6926 <description>Stream x clear direct mode error
6927 interrupt flag (x = 3..0)</description>
6928 <bitOffset>18</bitOffset>
6929 <bitWidth>1</bitWidth>
6930 </field>
6931 <field>
6932 <name>CFEIF2</name>
6933 <description>Stream x clear FIFO error interrupt flag
6934 (x = 3..0)</description>
6935 <bitOffset>16</bitOffset>
6936 <bitWidth>1</bitWidth>
6937 </field>
6938 <field>
6939 <name>CTCIF1</name>
6940 <description>Stream x clear transfer complete
6941 interrupt flag (x = 3..0)</description>
6942 <bitOffset>11</bitOffset>
6943 <bitWidth>1</bitWidth>
6944 </field>
6945 <field>
6946 <name>CHTIF1</name>
6947 <description>Stream x clear half transfer interrupt
6948 flag (x = 3..0)</description>
6949 <bitOffset>10</bitOffset>
6950 <bitWidth>1</bitWidth>
6951 </field>
6952 <field>
6953 <name>CTEIF1</name>
6954 <description>Stream x clear transfer error interrupt
6955 flag (x = 3..0)</description>
6956 <bitOffset>9</bitOffset>
6957 <bitWidth>1</bitWidth>
6958 </field>
6959 <field>
6960 <name>CDMEIF1</name>
6961 <description>Stream x clear direct mode error
6962 interrupt flag (x = 3..0)</description>
6963 <bitOffset>8</bitOffset>
6964 <bitWidth>1</bitWidth>
6965 </field>
6966 <field>
6967 <name>CFEIF1</name>
6968 <description>Stream x clear FIFO error interrupt flag
6969 (x = 3..0)</description>
6970 <bitOffset>6</bitOffset>
6971 <bitWidth>1</bitWidth>
6972 </field>
6973 <field>
6974 <name>CTCIF0</name>
6975 <description>Stream x clear transfer complete
6976 interrupt flag (x = 3..0)</description>
6977 <bitOffset>5</bitOffset>
6978 <bitWidth>1</bitWidth>
6979 </field>
6980 <field>
6981 <name>CHTIF0</name>
6982 <description>Stream x clear half transfer interrupt
6983 flag (x = 3..0)</description>
6984 <bitOffset>4</bitOffset>
6985 <bitWidth>1</bitWidth>
6986 </field>
6987 <field>
6988 <name>CTEIF0</name>
6989 <description>Stream x clear transfer error interrupt
6990 flag (x = 3..0)</description>
6991 <bitOffset>3</bitOffset>
6992 <bitWidth>1</bitWidth>
6993 </field>
6994 <field>
6995 <name>CDMEIF0</name>
6996 <description>Stream x clear direct mode error
6997 interrupt flag (x = 3..0)</description>
6998 <bitOffset>2</bitOffset>
6999 <bitWidth>1</bitWidth>
7000 </field>
7001 <field>
7002 <name>CFEIF0</name>
7003 <description>Stream x clear FIFO error interrupt flag
7004 (x = 3..0)</description>
7005 <bitOffset>0</bitOffset>
7006 <bitWidth>1</bitWidth>
7007 </field>
7008 </fields>
7009 </register>
7010 <register>
7011 <name>HIFCR</name>
7012 <displayName>HIFCR</displayName>
7013 <description>high interrupt flag clear
7014 register</description>
7015 <addressOffset>0xC</addressOffset>
7016 <size>0x20</size>
7017 <access>read-write</access>
7018 <resetValue>0x00000000</resetValue>
7019 <fields>
7020 <field>
7021 <name>CTCIF7</name>
7022 <description>Stream x clear transfer complete
7023 interrupt flag (x = 7..4)</description>
7024 <bitOffset>27</bitOffset>
7025 <bitWidth>1</bitWidth>
7026 </field>
7027 <field>
7028 <name>CHTIF7</name>
7029 <description>Stream x clear half transfer interrupt
7030 flag (x = 7..4)</description>
7031 <bitOffset>26</bitOffset>
7032 <bitWidth>1</bitWidth>
7033 </field>
7034 <field>
7035 <name>CTEIF7</name>
7036 <description>Stream x clear transfer error interrupt
7037 flag (x = 7..4)</description>
7038 <bitOffset>25</bitOffset>
7039 <bitWidth>1</bitWidth>
7040 </field>
7041 <field>
7042 <name>CDMEIF7</name>
7043 <description>Stream x clear direct mode error
7044 interrupt flag (x = 7..4)</description>
7045 <bitOffset>24</bitOffset>
7046 <bitWidth>1</bitWidth>
7047 </field>
7048 <field>
7049 <name>CFEIF7</name>
7050 <description>Stream x clear FIFO error interrupt flag
7051 (x = 7..4)</description>
7052 <bitOffset>22</bitOffset>
7053 <bitWidth>1</bitWidth>
7054 </field>
7055 <field>
7056 <name>CTCIF6</name>
7057 <description>Stream x clear transfer complete
7058 interrupt flag (x = 7..4)</description>
7059 <bitOffset>21</bitOffset>
7060 <bitWidth>1</bitWidth>
7061 </field>
7062 <field>
7063 <name>CHTIF6</name>
7064 <description>Stream x clear half transfer interrupt
7065 flag (x = 7..4)</description>
7066 <bitOffset>20</bitOffset>
7067 <bitWidth>1</bitWidth>
7068 </field>
7069 <field>
7070 <name>CTEIF6</name>
7071 <description>Stream x clear transfer error interrupt
7072 flag (x = 7..4)</description>
7073 <bitOffset>19</bitOffset>
7074 <bitWidth>1</bitWidth>
7075 </field>
7076 <field>
7077 <name>CDMEIF6</name>
7078 <description>Stream x clear direct mode error
7079 interrupt flag (x = 7..4)</description>
7080 <bitOffset>18</bitOffset>
7081 <bitWidth>1</bitWidth>
7082 </field>
7083 <field>
7084 <name>CFEIF6</name>
7085 <description>Stream x clear FIFO error interrupt flag
7086 (x = 7..4)</description>
7087 <bitOffset>16</bitOffset>
7088 <bitWidth>1</bitWidth>
7089 </field>
7090 <field>
7091 <name>CTCIF5</name>
7092 <description>Stream x clear transfer complete
7093 interrupt flag (x = 7..4)</description>
7094 <bitOffset>11</bitOffset>
7095 <bitWidth>1</bitWidth>
7096 </field>
7097 <field>
7098 <name>CHTIF5</name>
7099 <description>Stream x clear half transfer interrupt
7100 flag (x = 7..4)</description>
7101 <bitOffset>10</bitOffset>
7102 <bitWidth>1</bitWidth>
7103 </field>
7104 <field>
7105 <name>CTEIF5</name>
7106 <description>Stream x clear transfer error interrupt
7107 flag (x = 7..4)</description>
7108 <bitOffset>9</bitOffset>
7109 <bitWidth>1</bitWidth>
7110 </field>
7111 <field>
7112 <name>CDMEIF5</name>
7113 <description>Stream x clear direct mode error
7114 interrupt flag (x = 7..4)</description>
7115 <bitOffset>8</bitOffset>
7116 <bitWidth>1</bitWidth>
7117 </field>
7118 <field>
7119 <name>CFEIF5</name>
7120 <description>Stream x clear FIFO error interrupt flag
7121 (x = 7..4)</description>
7122 <bitOffset>6</bitOffset>
7123 <bitWidth>1</bitWidth>
7124 </field>
7125 <field>
7126 <name>CTCIF4</name>
7127 <description>Stream x clear transfer complete
7128 interrupt flag (x = 7..4)</description>
7129 <bitOffset>5</bitOffset>
7130 <bitWidth>1</bitWidth>
7131 </field>
7132 <field>
7133 <name>CHTIF4</name>
7134 <description>Stream x clear half transfer interrupt
7135 flag (x = 7..4)</description>
7136 <bitOffset>4</bitOffset>
7137 <bitWidth>1</bitWidth>
7138 </field>
7139 <field>
7140 <name>CTEIF4</name>
7141 <description>Stream x clear transfer error interrupt
7142 flag (x = 7..4)</description>
7143 <bitOffset>3</bitOffset>
7144 <bitWidth>1</bitWidth>
7145 </field>
7146 <field>
7147 <name>CDMEIF4</name>
7148 <description>Stream x clear direct mode error
7149 interrupt flag (x = 7..4)</description>
7150 <bitOffset>2</bitOffset>
7151 <bitWidth>1</bitWidth>
7152 </field>
7153 <field>
7154 <name>CFEIF4</name>
7155 <description>Stream x clear FIFO error interrupt flag
7156 (x = 7..4)</description>
7157 <bitOffset>0</bitOffset>
7158 <bitWidth>1</bitWidth>
7159 </field>
7160 </fields>
7161 </register>
7162 <register>
7163 <name>S0CR</name>
7164 <displayName>S0CR</displayName>
7165 <description>stream x configuration
7166 register</description>
7167 <addressOffset>0x10</addressOffset>
7168 <size>0x20</size>
7169 <access>read-write</access>
7170 <resetValue>0x00000000</resetValue>
7171 <fields>
7172 <field>
7173 <name>CHSEL</name>
7174 <description>Channel selection</description>
7175 <bitOffset>25</bitOffset>
7176 <bitWidth>3</bitWidth>
7177 </field>
7178 <field>
7179 <name>MBURST</name>
7180 <description>Memory burst transfer
7181 configuration</description>
7182 <bitOffset>23</bitOffset>
7183 <bitWidth>2</bitWidth>
7184 </field>
7185 <field>
7186 <name>PBURST</name>
7187 <description>Peripheral burst transfer
7188 configuration</description>
7189 <bitOffset>21</bitOffset>
7190 <bitWidth>2</bitWidth>
7191 </field>
7192 <field>
7193 <name>CT</name>
7194 <description>Current target (only in double buffer
7195 mode)</description>
7196 <bitOffset>19</bitOffset>
7197 <bitWidth>1</bitWidth>
7198 </field>
7199 <field>
7200 <name>DBM</name>
7201 <description>Double buffer mode</description>
7202 <bitOffset>18</bitOffset>
7203 <bitWidth>1</bitWidth>
7204 </field>
7205 <field>
7206 <name>PL</name>
7207 <description>Priority level</description>
7208 <bitOffset>16</bitOffset>
7209 <bitWidth>2</bitWidth>
7210 </field>
7211 <field>
7212 <name>PINCOS</name>
7213 <description>Peripheral increment offset
7214 size</description>
7215 <bitOffset>15</bitOffset>
7216 <bitWidth>1</bitWidth>
7217 </field>
7218 <field>
7219 <name>MSIZE</name>
7220 <description>Memory data size</description>
7221 <bitOffset>13</bitOffset>
7222 <bitWidth>2</bitWidth>
7223 </field>
7224 <field>
7225 <name>PSIZE</name>
7226 <description>Peripheral data size</description>
7227 <bitOffset>11</bitOffset>
7228 <bitWidth>2</bitWidth>
7229 </field>
7230 <field>
7231 <name>MINC</name>
7232 <description>Memory increment mode</description>
7233 <bitOffset>10</bitOffset>
7234 <bitWidth>1</bitWidth>
7235 </field>
7236 <field>
7237 <name>PINC</name>
7238 <description>Peripheral increment mode</description>
7239 <bitOffset>9</bitOffset>
7240 <bitWidth>1</bitWidth>
7241 </field>
7242 <field>
7243 <name>CIRC</name>
7244 <description>Circular mode</description>
7245 <bitOffset>8</bitOffset>
7246 <bitWidth>1</bitWidth>
7247 </field>
7248 <field>
7249 <name>DIR</name>
7250 <description>Data transfer direction</description>
7251 <bitOffset>6</bitOffset>
7252 <bitWidth>2</bitWidth>
7253 </field>
7254 <field>
7255 <name>PFCTRL</name>
7256 <description>Peripheral flow controller</description>
7257 <bitOffset>5</bitOffset>
7258 <bitWidth>1</bitWidth>
7259 </field>
7260 <field>
7261 <name>TCIE</name>
7262 <description>Transfer complete interrupt
7263 enable</description>
7264 <bitOffset>4</bitOffset>
7265 <bitWidth>1</bitWidth>
7266 </field>
7267 <field>
7268 <name>HTIE</name>
7269 <description>Half transfer interrupt
7270 enable</description>
7271 <bitOffset>3</bitOffset>
7272 <bitWidth>1</bitWidth>
7273 </field>
7274 <field>
7275 <name>TEIE</name>
7276 <description>Transfer error interrupt
7277 enable</description>
7278 <bitOffset>2</bitOffset>
7279 <bitWidth>1</bitWidth>
7280 </field>
7281 <field>
7282 <name>DMEIE</name>
7283 <description>Direct mode error interrupt
7284 enable</description>
7285 <bitOffset>1</bitOffset>
7286 <bitWidth>1</bitWidth>
7287 </field>
7288 <field>
7289 <name>EN</name>
7290 <description>Stream enable / flag stream ready when
7291 read low</description>
7292 <bitOffset>0</bitOffset>
7293 <bitWidth>1</bitWidth>
7294 </field>
7295 </fields>
7296 </register>
7297 <register>
7298 <name>S0NDTR</name>
7299 <displayName>S0NDTR</displayName>
7300 <description>stream x number of data
7301 register</description>
7302 <addressOffset>0x14</addressOffset>
7303 <size>0x20</size>
7304 <access>read-write</access>
7305 <resetValue>0x00000000</resetValue>
7306 <fields>
7307 <field>
7308 <name>NDT</name>
7309 <description>Number of data items to
7310 transfer</description>
7311 <bitOffset>0</bitOffset>
7312 <bitWidth>16</bitWidth>
7313 </field>
7314 </fields>
7315 </register>
7316 <register>
7317 <name>S0PAR</name>
7318 <displayName>S0PAR</displayName>
7319 <description>stream x peripheral address
7320 register</description>
7321 <addressOffset>0x18</addressOffset>
7322 <size>0x20</size>
7323 <access>read-write</access>
7324 <resetValue>0x00000000</resetValue>
7325 <fields>
7326 <field>
7327 <name>PA</name>
7328 <description>Peripheral address</description>
7329 <bitOffset>0</bitOffset>
7330 <bitWidth>32</bitWidth>
7331 </field>
7332 </fields>
7333 </register>
7334 <register>
7335 <name>S0M0AR</name>
7336 <displayName>S0M0AR</displayName>
7337 <description>stream x memory 0 address
7338 register</description>
7339 <addressOffset>0x1C</addressOffset>
7340 <size>0x20</size>
7341 <access>read-write</access>
7342 <resetValue>0x00000000</resetValue>
7343 <fields>
7344 <field>
7345 <name>M0A</name>
7346 <description>Memory 0 address</description>
7347 <bitOffset>0</bitOffset>
7348 <bitWidth>32</bitWidth>
7349 </field>
7350 </fields>
7351 </register>
7352 <register>
7353 <name>S0M1AR</name>
7354 <displayName>S0M1AR</displayName>
7355 <description>stream x memory 1 address
7356 register</description>
7357 <addressOffset>0x20</addressOffset>
7358 <size>0x20</size>
7359 <access>read-write</access>
7360 <resetValue>0x00000000</resetValue>
7361 <fields>
7362 <field>
7363 <name>M1A</name>
7364 <description>Memory 1 address (used in case of Double
7365 buffer mode)</description>
7366 <bitOffset>0</bitOffset>
7367 <bitWidth>32</bitWidth>
7368 </field>
7369 </fields>
7370 </register>
7371 <register>
7372 <name>S0FCR</name>
7373 <displayName>S0FCR</displayName>
7374 <description>stream x FIFO control register</description>
7375 <addressOffset>0x24</addressOffset>
7376 <size>0x20</size>
7377 <resetValue>0x00000021</resetValue>
7378 <fields>
7379 <field>
7380 <name>FEIE</name>
7381 <description>FIFO error interrupt
7382 enable</description>
7383 <bitOffset>7</bitOffset>
7384 <bitWidth>1</bitWidth>
7385 <access>read-write</access>
7386 </field>
7387 <field>
7388 <name>FS</name>
7389 <description>FIFO status</description>
7390 <bitOffset>3</bitOffset>
7391 <bitWidth>3</bitWidth>
7392 <access>read-only</access>
7393 </field>
7394 <field>
7395 <name>DMDIS</name>
7396 <description>Direct mode disable</description>
7397 <bitOffset>2</bitOffset>
7398 <bitWidth>1</bitWidth>
7399 <access>read-write</access>
7400 </field>
7401 <field>
7402 <name>FTH</name>
7403 <description>FIFO threshold selection</description>
7404 <bitOffset>0</bitOffset>
7405 <bitWidth>2</bitWidth>
7406 <access>read-write</access>
7407 </field>
7408 </fields>
7409 </register>
7410 <register>
7411 <name>S1CR</name>
7412 <displayName>S1CR</displayName>
7413 <description>stream x configuration
7414 register</description>
7415 <addressOffset>0x28</addressOffset>
7416 <size>0x20</size>
7417 <access>read-write</access>
7418 <resetValue>0x00000000</resetValue>
7419 <fields>
7420 <field>
7421 <name>CHSEL</name>
7422 <description>Channel selection</description>
7423 <bitOffset>25</bitOffset>
7424 <bitWidth>3</bitWidth>
7425 </field>
7426 <field>
7427 <name>MBURST</name>
7428 <description>Memory burst transfer
7429 configuration</description>
7430 <bitOffset>23</bitOffset>
7431 <bitWidth>2</bitWidth>
7432 </field>
7433 <field>
7434 <name>PBURST</name>
7435 <description>Peripheral burst transfer
7436 configuration</description>
7437 <bitOffset>21</bitOffset>
7438 <bitWidth>2</bitWidth>
7439 </field>
7440 <field>
7441 <name>ACK</name>
7442 <description>ACK</description>
7443 <bitOffset>20</bitOffset>
7444 <bitWidth>1</bitWidth>
7445 </field>
7446 <field>
7447 <name>CT</name>
7448 <description>Current target (only in double buffer
7449 mode)</description>
7450 <bitOffset>19</bitOffset>
7451 <bitWidth>1</bitWidth>
7452 </field>
7453 <field>
7454 <name>DBM</name>
7455 <description>Double buffer mode</description>
7456 <bitOffset>18</bitOffset>
7457 <bitWidth>1</bitWidth>
7458 </field>
7459 <field>
7460 <name>PL</name>
7461 <description>Priority level</description>
7462 <bitOffset>16</bitOffset>
7463 <bitWidth>2</bitWidth>
7464 </field>
7465 <field>
7466 <name>PINCOS</name>
7467 <description>Peripheral increment offset
7468 size</description>
7469 <bitOffset>15</bitOffset>
7470 <bitWidth>1</bitWidth>
7471 </field>
7472 <field>
7473 <name>MSIZE</name>
7474 <description>Memory data size</description>
7475 <bitOffset>13</bitOffset>
7476 <bitWidth>2</bitWidth>
7477 </field>
7478 <field>
7479 <name>PSIZE</name>
7480 <description>Peripheral data size</description>
7481 <bitOffset>11</bitOffset>
7482 <bitWidth>2</bitWidth>
7483 </field>
7484 <field>
7485 <name>MINC</name>
7486 <description>Memory increment mode</description>
7487 <bitOffset>10</bitOffset>
7488 <bitWidth>1</bitWidth>
7489 </field>
7490 <field>
7491 <name>PINC</name>
7492 <description>Peripheral increment mode</description>
7493 <bitOffset>9</bitOffset>
7494 <bitWidth>1</bitWidth>
7495 </field>
7496 <field>
7497 <name>CIRC</name>
7498 <description>Circular mode</description>
7499 <bitOffset>8</bitOffset>
7500 <bitWidth>1</bitWidth>
7501 </field>
7502 <field>
7503 <name>DIR</name>
7504 <description>Data transfer direction</description>
7505 <bitOffset>6</bitOffset>
7506 <bitWidth>2</bitWidth>
7507 </field>
7508 <field>
7509 <name>PFCTRL</name>
7510 <description>Peripheral flow controller</description>
7511 <bitOffset>5</bitOffset>
7512 <bitWidth>1</bitWidth>
7513 </field>
7514 <field>
7515 <name>TCIE</name>
7516 <description>Transfer complete interrupt
7517 enable</description>
7518 <bitOffset>4</bitOffset>
7519 <bitWidth>1</bitWidth>
7520 </field>
7521 <field>
7522 <name>HTIE</name>
7523 <description>Half transfer interrupt
7524 enable</description>
7525 <bitOffset>3</bitOffset>
7526 <bitWidth>1</bitWidth>
7527 </field>
7528 <field>
7529 <name>TEIE</name>
7530 <description>Transfer error interrupt
7531 enable</description>
7532 <bitOffset>2</bitOffset>
7533 <bitWidth>1</bitWidth>
7534 </field>
7535 <field>
7536 <name>DMEIE</name>
7537 <description>Direct mode error interrupt
7538 enable</description>
7539 <bitOffset>1</bitOffset>
7540 <bitWidth>1</bitWidth>
7541 </field>
7542 <field>
7543 <name>EN</name>
7544 <description>Stream enable / flag stream ready when
7545 read low</description>
7546 <bitOffset>0</bitOffset>
7547 <bitWidth>1</bitWidth>
7548 </field>
7549 </fields>
7550 </register>
7551 <register>
7552 <name>S1NDTR</name>
7553 <displayName>S1NDTR</displayName>
7554 <description>stream x number of data
7555 register</description>
7556 <addressOffset>0x2C</addressOffset>
7557 <size>0x20</size>
7558 <access>read-write</access>
7559 <resetValue>0x00000000</resetValue>
7560 <fields>
7561 <field>
7562 <name>NDT</name>
7563 <description>Number of data items to
7564 transfer</description>
7565 <bitOffset>0</bitOffset>
7566 <bitWidth>16</bitWidth>
7567 </field>
7568 </fields>
7569 </register>
7570 <register>
7571 <name>S1PAR</name>
7572 <displayName>S1PAR</displayName>
7573 <description>stream x peripheral address
7574 register</description>
7575 <addressOffset>0x30</addressOffset>
7576 <size>0x20</size>
7577 <access>read-write</access>
7578 <resetValue>0x00000000</resetValue>
7579 <fields>
7580 <field>
7581 <name>PA</name>
7582 <description>Peripheral address</description>
7583 <bitOffset>0</bitOffset>
7584 <bitWidth>32</bitWidth>
7585 </field>
7586 </fields>
7587 </register>
7588 <register>
7589 <name>S1M0AR</name>
7590 <displayName>S1M0AR</displayName>
7591 <description>stream x memory 0 address
7592 register</description>
7593 <addressOffset>0x34</addressOffset>
7594 <size>0x20</size>
7595 <access>read-write</access>
7596 <resetValue>0x00000000</resetValue>
7597 <fields>
7598 <field>
7599 <name>M0A</name>
7600 <description>Memory 0 address</description>
7601 <bitOffset>0</bitOffset>
7602 <bitWidth>32</bitWidth>
7603 </field>
7604 </fields>
7605 </register>
7606 <register>
7607 <name>S1M1AR</name>
7608 <displayName>S1M1AR</displayName>
7609 <description>stream x memory 1 address
7610 register</description>
7611 <addressOffset>0x38</addressOffset>
7612 <size>0x20</size>
7613 <access>read-write</access>
7614 <resetValue>0x00000000</resetValue>
7615 <fields>
7616 <field>
7617 <name>M1A</name>
7618 <description>Memory 1 address (used in case of Double
7619 buffer mode)</description>
7620 <bitOffset>0</bitOffset>
7621 <bitWidth>32</bitWidth>
7622 </field>
7623 </fields>
7624 </register>
7625 <register>
7626 <name>S1FCR</name>
7627 <displayName>S1FCR</displayName>
7628 <description>stream x FIFO control register</description>
7629 <addressOffset>0x3C</addressOffset>
7630 <size>0x20</size>
7631 <resetValue>0x00000021</resetValue>
7632 <fields>
7633 <field>
7634 <name>FEIE</name>
7635 <description>FIFO error interrupt
7636 enable</description>
7637 <bitOffset>7</bitOffset>
7638 <bitWidth>1</bitWidth>
7639 <access>read-write</access>
7640 </field>
7641 <field>
7642 <name>FS</name>
7643 <description>FIFO status</description>
7644 <bitOffset>3</bitOffset>
7645 <bitWidth>3</bitWidth>
7646 <access>read-only</access>
7647 </field>
7648 <field>
7649 <name>DMDIS</name>
7650 <description>Direct mode disable</description>
7651 <bitOffset>2</bitOffset>
7652 <bitWidth>1</bitWidth>
7653 <access>read-write</access>
7654 </field>
7655 <field>
7656 <name>FTH</name>
7657 <description>FIFO threshold selection</description>
7658 <bitOffset>0</bitOffset>
7659 <bitWidth>2</bitWidth>
7660 <access>read-write</access>
7661 </field>
7662 </fields>
7663 </register>
7664 <register>
7665 <name>S2CR</name>
7666 <displayName>S2CR</displayName>
7667 <description>stream x configuration
7668 register</description>
7669 <addressOffset>0x40</addressOffset>
7670 <size>0x20</size>
7671 <access>read-write</access>
7672 <resetValue>0x00000000</resetValue>
7673 <fields>
7674 <field>
7675 <name>CHSEL</name>
7676 <description>Channel selection</description>
7677 <bitOffset>25</bitOffset>
7678 <bitWidth>3</bitWidth>
7679 </field>
7680 <field>
7681 <name>MBURST</name>
7682 <description>Memory burst transfer
7683 configuration</description>
7684 <bitOffset>23</bitOffset>
7685 <bitWidth>2</bitWidth>
7686 </field>
7687 <field>
7688 <name>PBURST</name>
7689 <description>Peripheral burst transfer
7690 configuration</description>
7691 <bitOffset>21</bitOffset>
7692 <bitWidth>2</bitWidth>
7693 </field>
7694 <field>
7695 <name>ACK</name>
7696 <description>ACK</description>
7697 <bitOffset>20</bitOffset>
7698 <bitWidth>1</bitWidth>
7699 </field>
7700 <field>
7701 <name>CT</name>
7702 <description>Current target (only in double buffer
7703 mode)</description>
7704 <bitOffset>19</bitOffset>
7705 <bitWidth>1</bitWidth>
7706 </field>
7707 <field>
7708 <name>DBM</name>
7709 <description>Double buffer mode</description>
7710 <bitOffset>18</bitOffset>
7711 <bitWidth>1</bitWidth>
7712 </field>
7713 <field>
7714 <name>PL</name>
7715 <description>Priority level</description>
7716 <bitOffset>16</bitOffset>
7717 <bitWidth>2</bitWidth>
7718 </field>
7719 <field>
7720 <name>PINCOS</name>
7721 <description>Peripheral increment offset
7722 size</description>
7723 <bitOffset>15</bitOffset>
7724 <bitWidth>1</bitWidth>
7725 </field>
7726 <field>
7727 <name>MSIZE</name>
7728 <description>Memory data size</description>
7729 <bitOffset>13</bitOffset>
7730 <bitWidth>2</bitWidth>
7731 </field>
7732 <field>
7733 <name>PSIZE</name>
7734 <description>Peripheral data size</description>
7735 <bitOffset>11</bitOffset>
7736 <bitWidth>2</bitWidth>
7737 </field>
7738 <field>
7739 <name>MINC</name>
7740 <description>Memory increment mode</description>
7741 <bitOffset>10</bitOffset>
7742 <bitWidth>1</bitWidth>
7743 </field>
7744 <field>
7745 <name>PINC</name>
7746 <description>Peripheral increment mode</description>
7747 <bitOffset>9</bitOffset>
7748 <bitWidth>1</bitWidth>
7749 </field>
7750 <field>
7751 <name>CIRC</name>
7752 <description>Circular mode</description>
7753 <bitOffset>8</bitOffset>
7754 <bitWidth>1</bitWidth>
7755 </field>
7756 <field>
7757 <name>DIR</name>
7758 <description>Data transfer direction</description>
7759 <bitOffset>6</bitOffset>
7760 <bitWidth>2</bitWidth>
7761 </field>
7762 <field>
7763 <name>PFCTRL</name>
7764 <description>Peripheral flow controller</description>
7765 <bitOffset>5</bitOffset>
7766 <bitWidth>1</bitWidth>
7767 </field>
7768 <field>
7769 <name>TCIE</name>
7770 <description>Transfer complete interrupt
7771 enable</description>
7772 <bitOffset>4</bitOffset>
7773 <bitWidth>1</bitWidth>
7774 </field>
7775 <field>
7776 <name>HTIE</name>
7777 <description>Half transfer interrupt
7778 enable</description>
7779 <bitOffset>3</bitOffset>
7780 <bitWidth>1</bitWidth>
7781 </field>
7782 <field>
7783 <name>TEIE</name>
7784 <description>Transfer error interrupt
7785 enable</description>
7786 <bitOffset>2</bitOffset>
7787 <bitWidth>1</bitWidth>
7788 </field>
7789 <field>
7790 <name>DMEIE</name>
7791 <description>Direct mode error interrupt
7792 enable</description>
7793 <bitOffset>1</bitOffset>
7794 <bitWidth>1</bitWidth>
7795 </field>
7796 <field>
7797 <name>EN</name>
7798 <description>Stream enable / flag stream ready when
7799 read low</description>
7800 <bitOffset>0</bitOffset>
7801 <bitWidth>1</bitWidth>
7802 </field>
7803 </fields>
7804 </register>
7805 <register>
7806 <name>S2NDTR</name>
7807 <displayName>S2NDTR</displayName>
7808 <description>stream x number of data
7809 register</description>
7810 <addressOffset>0x44</addressOffset>
7811 <size>0x20</size>
7812 <access>read-write</access>
7813 <resetValue>0x00000000</resetValue>
7814 <fields>
7815 <field>
7816 <name>NDT</name>
7817 <description>Number of data items to
7818 transfer</description>
7819 <bitOffset>0</bitOffset>
7820 <bitWidth>16</bitWidth>
7821 </field>
7822 </fields>
7823 </register>
7824 <register>
7825 <name>S2PAR</name>
7826 <displayName>S2PAR</displayName>
7827 <description>stream x peripheral address
7828 register</description>
7829 <addressOffset>0x48</addressOffset>
7830 <size>0x20</size>
7831 <access>read-write</access>
7832 <resetValue>0x00000000</resetValue>
7833 <fields>
7834 <field>
7835 <name>PA</name>
7836 <description>Peripheral address</description>
7837 <bitOffset>0</bitOffset>
7838 <bitWidth>32</bitWidth>
7839 </field>
7840 </fields>
7841 </register>
7842 <register>
7843 <name>S2M0AR</name>
7844 <displayName>S2M0AR</displayName>
7845 <description>stream x memory 0 address
7846 register</description>
7847 <addressOffset>0x4C</addressOffset>
7848 <size>0x20</size>
7849 <access>read-write</access>
7850 <resetValue>0x00000000</resetValue>
7851 <fields>
7852 <field>
7853 <name>M0A</name>
7854 <description>Memory 0 address</description>
7855 <bitOffset>0</bitOffset>
7856 <bitWidth>32</bitWidth>
7857 </field>
7858 </fields>
7859 </register>
7860 <register>
7861 <name>S2M1AR</name>
7862 <displayName>S2M1AR</displayName>
7863 <description>stream x memory 1 address
7864 register</description>
7865 <addressOffset>0x50</addressOffset>
7866 <size>0x20</size>
7867 <access>read-write</access>
7868 <resetValue>0x00000000</resetValue>
7869 <fields>
7870 <field>
7871 <name>M1A</name>
7872 <description>Memory 1 address (used in case of Double
7873 buffer mode)</description>
7874 <bitOffset>0</bitOffset>
7875 <bitWidth>32</bitWidth>
7876 </field>
7877 </fields>
7878 </register>
7879 <register>
7880 <name>S2FCR</name>
7881 <displayName>S2FCR</displayName>
7882 <description>stream x FIFO control register</description>
7883 <addressOffset>0x54</addressOffset>
7884 <size>0x20</size>
7885 <resetValue>0x00000021</resetValue>
7886 <fields>
7887 <field>
7888 <name>FEIE</name>
7889 <description>FIFO error interrupt
7890 enable</description>
7891 <bitOffset>7</bitOffset>
7892 <bitWidth>1</bitWidth>
7893 <access>read-write</access>
7894 </field>
7895 <field>
7896 <name>FS</name>
7897 <description>FIFO status</description>
7898 <bitOffset>3</bitOffset>
7899 <bitWidth>3</bitWidth>
7900 <access>read-only</access>
7901 </field>
7902 <field>
7903 <name>DMDIS</name>
7904 <description>Direct mode disable</description>
7905 <bitOffset>2</bitOffset>
7906 <bitWidth>1</bitWidth>
7907 <access>read-write</access>
7908 </field>
7909 <field>
7910 <name>FTH</name>
7911 <description>FIFO threshold selection</description>
7912 <bitOffset>0</bitOffset>
7913 <bitWidth>2</bitWidth>
7914 <access>read-write</access>
7915 </field>
7916 </fields>
7917 </register>
7918 <register>
7919 <name>S3CR</name>
7920 <displayName>S3CR</displayName>
7921 <description>stream x configuration
7922 register</description>
7923 <addressOffset>0x58</addressOffset>
7924 <size>0x20</size>
7925 <access>read-write</access>
7926 <resetValue>0x00000000</resetValue>
7927 <fields>
7928 <field>
7929 <name>CHSEL</name>
7930 <description>Channel selection</description>
7931 <bitOffset>25</bitOffset>
7932 <bitWidth>3</bitWidth>
7933 </field>
7934 <field>
7935 <name>MBURST</name>
7936 <description>Memory burst transfer
7937 configuration</description>
7938 <bitOffset>23</bitOffset>
7939 <bitWidth>2</bitWidth>
7940 </field>
7941 <field>
7942 <name>PBURST</name>
7943 <description>Peripheral burst transfer
7944 configuration</description>
7945 <bitOffset>21</bitOffset>
7946 <bitWidth>2</bitWidth>
7947 </field>
7948 <field>
7949 <name>ACK</name>
7950 <description>ACK</description>
7951 <bitOffset>20</bitOffset>
7952 <bitWidth>1</bitWidth>
7953 </field>
7954 <field>
7955 <name>CT</name>
7956 <description>Current target (only in double buffer
7957 mode)</description>
7958 <bitOffset>19</bitOffset>
7959 <bitWidth>1</bitWidth>
7960 </field>
7961 <field>
7962 <name>DBM</name>
7963 <description>Double buffer mode</description>
7964 <bitOffset>18</bitOffset>
7965 <bitWidth>1</bitWidth>
7966 </field>
7967 <field>
7968 <name>PL</name>
7969 <description>Priority level</description>
7970 <bitOffset>16</bitOffset>
7971 <bitWidth>2</bitWidth>
7972 </field>
7973 <field>
7974 <name>PINCOS</name>
7975 <description>Peripheral increment offset
7976 size</description>
7977 <bitOffset>15</bitOffset>
7978 <bitWidth>1</bitWidth>
7979 </field>
7980 <field>
7981 <name>MSIZE</name>
7982 <description>Memory data size</description>
7983 <bitOffset>13</bitOffset>
7984 <bitWidth>2</bitWidth>
7985 </field>
7986 <field>
7987 <name>PSIZE</name>
7988 <description>Peripheral data size</description>
7989 <bitOffset>11</bitOffset>
7990 <bitWidth>2</bitWidth>
7991 </field>
7992 <field>
7993 <name>MINC</name>
7994 <description>Memory increment mode</description>
7995 <bitOffset>10</bitOffset>
7996 <bitWidth>1</bitWidth>
7997 </field>
7998 <field>
7999 <name>PINC</name>
8000 <description>Peripheral increment mode</description>
8001 <bitOffset>9</bitOffset>
8002 <bitWidth>1</bitWidth>
8003 </field>
8004 <field>
8005 <name>CIRC</name>
8006 <description>Circular mode</description>
8007 <bitOffset>8</bitOffset>
8008 <bitWidth>1</bitWidth>
8009 </field>
8010 <field>
8011 <name>DIR</name>
8012 <description>Data transfer direction</description>
8013 <bitOffset>6</bitOffset>
8014 <bitWidth>2</bitWidth>
8015 </field>
8016 <field>
8017 <name>PFCTRL</name>
8018 <description>Peripheral flow controller</description>
8019 <bitOffset>5</bitOffset>
8020 <bitWidth>1</bitWidth>
8021 </field>
8022 <field>
8023 <name>TCIE</name>
8024 <description>Transfer complete interrupt
8025 enable</description>
8026 <bitOffset>4</bitOffset>
8027 <bitWidth>1</bitWidth>
8028 </field>
8029 <field>
8030 <name>HTIE</name>
8031 <description>Half transfer interrupt
8032 enable</description>
8033 <bitOffset>3</bitOffset>
8034 <bitWidth>1</bitWidth>
8035 </field>
8036 <field>
8037 <name>TEIE</name>
8038 <description>Transfer error interrupt
8039 enable</description>
8040 <bitOffset>2</bitOffset>
8041 <bitWidth>1</bitWidth>
8042 </field>
8043 <field>
8044 <name>DMEIE</name>
8045 <description>Direct mode error interrupt
8046 enable</description>
8047 <bitOffset>1</bitOffset>
8048 <bitWidth>1</bitWidth>
8049 </field>
8050 <field>
8051 <name>EN</name>
8052 <description>Stream enable / flag stream ready when
8053 read low</description>
8054 <bitOffset>0</bitOffset>
8055 <bitWidth>1</bitWidth>
8056 </field>
8057 </fields>
8058 </register>
8059 <register>
8060 <name>S3NDTR</name>
8061 <displayName>S3NDTR</displayName>
8062 <description>stream x number of data
8063 register</description>
8064 <addressOffset>0x5C</addressOffset>
8065 <size>0x20</size>
8066 <access>read-write</access>
8067 <resetValue>0x00000000</resetValue>
8068 <fields>
8069 <field>
8070 <name>NDT</name>
8071 <description>Number of data items to
8072 transfer</description>
8073 <bitOffset>0</bitOffset>
8074 <bitWidth>16</bitWidth>
8075 </field>
8076 </fields>
8077 </register>
8078 <register>
8079 <name>S3PAR</name>
8080 <displayName>S3PAR</displayName>
8081 <description>stream x peripheral address
8082 register</description>
8083 <addressOffset>0x60</addressOffset>
8084 <size>0x20</size>
8085 <access>read-write</access>
8086 <resetValue>0x00000000</resetValue>
8087 <fields>
8088 <field>
8089 <name>PA</name>
8090 <description>Peripheral address</description>
8091 <bitOffset>0</bitOffset>
8092 <bitWidth>32</bitWidth>
8093 </field>
8094 </fields>
8095 </register>
8096 <register>
8097 <name>S3M0AR</name>
8098 <displayName>S3M0AR</displayName>
8099 <description>stream x memory 0 address
8100 register</description>
8101 <addressOffset>0x64</addressOffset>
8102 <size>0x20</size>
8103 <access>read-write</access>
8104 <resetValue>0x00000000</resetValue>
8105 <fields>
8106 <field>
8107 <name>M0A</name>
8108 <description>Memory 0 address</description>
8109 <bitOffset>0</bitOffset>
8110 <bitWidth>32</bitWidth>
8111 </field>
8112 </fields>
8113 </register>
8114 <register>
8115 <name>S3M1AR</name>
8116 <displayName>S3M1AR</displayName>
8117 <description>stream x memory 1 address
8118 register</description>
8119 <addressOffset>0x68</addressOffset>
8120 <size>0x20</size>
8121 <access>read-write</access>
8122 <resetValue>0x00000000</resetValue>
8123 <fields>
8124 <field>
8125 <name>M1A</name>
8126 <description>Memory 1 address (used in case of Double
8127 buffer mode)</description>
8128 <bitOffset>0</bitOffset>
8129 <bitWidth>32</bitWidth>
8130 </field>
8131 </fields>
8132 </register>
8133 <register>
8134 <name>S3FCR</name>
8135 <displayName>S3FCR</displayName>
8136 <description>stream x FIFO control register</description>
8137 <addressOffset>0x6C</addressOffset>
8138 <size>0x20</size>
8139 <resetValue>0x00000021</resetValue>
8140 <fields>
8141 <field>
8142 <name>FEIE</name>
8143 <description>FIFO error interrupt
8144 enable</description>
8145 <bitOffset>7</bitOffset>
8146 <bitWidth>1</bitWidth>
8147 <access>read-write</access>
8148 </field>
8149 <field>
8150 <name>FS</name>
8151 <description>FIFO status</description>
8152 <bitOffset>3</bitOffset>
8153 <bitWidth>3</bitWidth>
8154 <access>read-only</access>
8155 </field>
8156 <field>
8157 <name>DMDIS</name>
8158 <description>Direct mode disable</description>
8159 <bitOffset>2</bitOffset>
8160 <bitWidth>1</bitWidth>
8161 <access>read-write</access>
8162 </field>
8163 <field>
8164 <name>FTH</name>
8165 <description>FIFO threshold selection</description>
8166 <bitOffset>0</bitOffset>
8167 <bitWidth>2</bitWidth>
8168 <access>read-write</access>
8169 </field>
8170 </fields>
8171 </register>
8172 <register>
8173 <name>S4CR</name>
8174 <displayName>S4CR</displayName>
8175 <description>stream x configuration
8176 register</description>
8177 <addressOffset>0x70</addressOffset>
8178 <size>0x20</size>
8179 <access>read-write</access>
8180 <resetValue>0x00000000</resetValue>
8181 <fields>
8182 <field>
8183 <name>CHSEL</name>
8184 <description>Channel selection</description>
8185 <bitOffset>25</bitOffset>
8186 <bitWidth>3</bitWidth>
8187 </field>
8188 <field>
8189 <name>MBURST</name>
8190 <description>Memory burst transfer
8191 configuration</description>
8192 <bitOffset>23</bitOffset>
8193 <bitWidth>2</bitWidth>
8194 </field>
8195 <field>
8196 <name>PBURST</name>
8197 <description>Peripheral burst transfer
8198 configuration</description>
8199 <bitOffset>21</bitOffset>
8200 <bitWidth>2</bitWidth>
8201 </field>
8202 <field>
8203 <name>ACK</name>
8204 <description>ACK</description>
8205 <bitOffset>20</bitOffset>
8206 <bitWidth>1</bitWidth>
8207 </field>
8208 <field>
8209 <name>CT</name>
8210 <description>Current target (only in double buffer
8211 mode)</description>
8212 <bitOffset>19</bitOffset>
8213 <bitWidth>1</bitWidth>
8214 </field>
8215 <field>
8216 <name>DBM</name>
8217 <description>Double buffer mode</description>
8218 <bitOffset>18</bitOffset>
8219 <bitWidth>1</bitWidth>
8220 </field>
8221 <field>
8222 <name>PL</name>
8223 <description>Priority level</description>
8224 <bitOffset>16</bitOffset>
8225 <bitWidth>2</bitWidth>
8226 </field>
8227 <field>
8228 <name>PINCOS</name>
8229 <description>Peripheral increment offset
8230 size</description>
8231 <bitOffset>15</bitOffset>
8232 <bitWidth>1</bitWidth>
8233 </field>
8234 <field>
8235 <name>MSIZE</name>
8236 <description>Memory data size</description>
8237 <bitOffset>13</bitOffset>
8238 <bitWidth>2</bitWidth>
8239 </field>
8240 <field>
8241 <name>PSIZE</name>
8242 <description>Peripheral data size</description>
8243 <bitOffset>11</bitOffset>
8244 <bitWidth>2</bitWidth>
8245 </field>
8246 <field>
8247 <name>MINC</name>
8248 <description>Memory increment mode</description>
8249 <bitOffset>10</bitOffset>
8250 <bitWidth>1</bitWidth>
8251 </field>
8252 <field>
8253 <name>PINC</name>
8254 <description>Peripheral increment mode</description>
8255 <bitOffset>9</bitOffset>
8256 <bitWidth>1</bitWidth>
8257 </field>
8258 <field>
8259 <name>CIRC</name>
8260 <description>Circular mode</description>
8261 <bitOffset>8</bitOffset>
8262 <bitWidth>1</bitWidth>
8263 </field>
8264 <field>
8265 <name>DIR</name>
8266 <description>Data transfer direction</description>
8267 <bitOffset>6</bitOffset>
8268 <bitWidth>2</bitWidth>
8269 </field>
8270 <field>
8271 <name>PFCTRL</name>
8272 <description>Peripheral flow controller</description>
8273 <bitOffset>5</bitOffset>
8274 <bitWidth>1</bitWidth>
8275 </field>
8276 <field>
8277 <name>TCIE</name>
8278 <description>Transfer complete interrupt
8279 enable</description>
8280 <bitOffset>4</bitOffset>
8281 <bitWidth>1</bitWidth>
8282 </field>
8283 <field>
8284 <name>HTIE</name>
8285 <description>Half transfer interrupt
8286 enable</description>
8287 <bitOffset>3</bitOffset>
8288 <bitWidth>1</bitWidth>
8289 </field>
8290 <field>
8291 <name>TEIE</name>
8292 <description>Transfer error interrupt
8293 enable</description>
8294 <bitOffset>2</bitOffset>
8295 <bitWidth>1</bitWidth>
8296 </field>
8297 <field>
8298 <name>DMEIE</name>
8299 <description>Direct mode error interrupt
8300 enable</description>
8301 <bitOffset>1</bitOffset>
8302 <bitWidth>1</bitWidth>
8303 </field>
8304 <field>
8305 <name>EN</name>
8306 <description>Stream enable / flag stream ready when
8307 read low</description>
8308 <bitOffset>0</bitOffset>
8309 <bitWidth>1</bitWidth>
8310 </field>
8311 </fields>
8312 </register>
8313 <register>
8314 <name>S4NDTR</name>
8315 <displayName>S4NDTR</displayName>
8316 <description>stream x number of data
8317 register</description>
8318 <addressOffset>0x74</addressOffset>
8319 <size>0x20</size>
8320 <access>read-write</access>
8321 <resetValue>0x00000000</resetValue>
8322 <fields>
8323 <field>
8324 <name>NDT</name>
8325 <description>Number of data items to
8326 transfer</description>
8327 <bitOffset>0</bitOffset>
8328 <bitWidth>16</bitWidth>
8329 </field>
8330 </fields>
8331 </register>
8332 <register>
8333 <name>S4PAR</name>
8334 <displayName>S4PAR</displayName>
8335 <description>stream x peripheral address
8336 register</description>
8337 <addressOffset>0x78</addressOffset>
8338 <size>0x20</size>
8339 <access>read-write</access>
8340 <resetValue>0x00000000</resetValue>
8341 <fields>
8342 <field>
8343 <name>PA</name>
8344 <description>Peripheral address</description>
8345 <bitOffset>0</bitOffset>
8346 <bitWidth>32</bitWidth>
8347 </field>
8348 </fields>
8349 </register>
8350 <register>
8351 <name>S4M0AR</name>
8352 <displayName>S4M0AR</displayName>
8353 <description>stream x memory 0 address
8354 register</description>
8355 <addressOffset>0x7C</addressOffset>
8356 <size>0x20</size>
8357 <access>read-write</access>
8358 <resetValue>0x00000000</resetValue>
8359 <fields>
8360 <field>
8361 <name>M0A</name>
8362 <description>Memory 0 address</description>
8363 <bitOffset>0</bitOffset>
8364 <bitWidth>32</bitWidth>
8365 </field>
8366 </fields>
8367 </register>
8368 <register>
8369 <name>S4M1AR</name>
8370 <displayName>S4M1AR</displayName>
8371 <description>stream x memory 1 address
8372 register</description>
8373 <addressOffset>0x80</addressOffset>
8374 <size>0x20</size>
8375 <access>read-write</access>
8376 <resetValue>0x00000000</resetValue>
8377 <fields>
8378 <field>
8379 <name>M1A</name>
8380 <description>Memory 1 address (used in case of Double
8381 buffer mode)</description>
8382 <bitOffset>0</bitOffset>
8383 <bitWidth>32</bitWidth>
8384 </field>
8385 </fields>
8386 </register>
8387 <register>
8388 <name>S4FCR</name>
8389 <displayName>S4FCR</displayName>
8390 <description>stream x FIFO control register</description>
8391 <addressOffset>0x84</addressOffset>
8392 <size>0x20</size>
8393 <resetValue>0x00000021</resetValue>
8394 <fields>
8395 <field>
8396 <name>FEIE</name>
8397 <description>FIFO error interrupt
8398 enable</description>
8399 <bitOffset>7</bitOffset>
8400 <bitWidth>1</bitWidth>
8401 <access>read-write</access>
8402 </field>
8403 <field>
8404 <name>FS</name>
8405 <description>FIFO status</description>
8406 <bitOffset>3</bitOffset>
8407 <bitWidth>3</bitWidth>
8408 <access>read-only</access>
8409 </field>
8410 <field>
8411 <name>DMDIS</name>
8412 <description>Direct mode disable</description>
8413 <bitOffset>2</bitOffset>
8414 <bitWidth>1</bitWidth>
8415 <access>read-write</access>
8416 </field>
8417 <field>
8418 <name>FTH</name>
8419 <description>FIFO threshold selection</description>
8420 <bitOffset>0</bitOffset>
8421 <bitWidth>2</bitWidth>
8422 <access>read-write</access>
8423 </field>
8424 </fields>
8425 </register>
8426 <register>
8427 <name>S5CR</name>
8428 <displayName>S5CR</displayName>
8429 <description>stream x configuration
8430 register</description>
8431 <addressOffset>0x88</addressOffset>
8432 <size>0x20</size>
8433 <access>read-write</access>
8434 <resetValue>0x00000000</resetValue>
8435 <fields>
8436 <field>
8437 <name>CHSEL</name>
8438 <description>Channel selection</description>
8439 <bitOffset>25</bitOffset>
8440 <bitWidth>3</bitWidth>
8441 </field>
8442 <field>
8443 <name>MBURST</name>
8444 <description>Memory burst transfer
8445 configuration</description>
8446 <bitOffset>23</bitOffset>
8447 <bitWidth>2</bitWidth>
8448 </field>
8449 <field>
8450 <name>PBURST</name>
8451 <description>Peripheral burst transfer
8452 configuration</description>
8453 <bitOffset>21</bitOffset>
8454 <bitWidth>2</bitWidth>
8455 </field>
8456 <field>
8457 <name>ACK</name>
8458 <description>ACK</description>
8459 <bitOffset>20</bitOffset>
8460 <bitWidth>1</bitWidth>
8461 </field>
8462 <field>
8463 <name>CT</name>
8464 <description>Current target (only in double buffer
8465 mode)</description>
8466 <bitOffset>19</bitOffset>
8467 <bitWidth>1</bitWidth>
8468 </field>
8469 <field>
8470 <name>DBM</name>
8471 <description>Double buffer mode</description>
8472 <bitOffset>18</bitOffset>
8473 <bitWidth>1</bitWidth>
8474 </field>
8475 <field>
8476 <name>PL</name>
8477 <description>Priority level</description>
8478 <bitOffset>16</bitOffset>
8479 <bitWidth>2</bitWidth>
8480 </field>
8481 <field>
8482 <name>PINCOS</name>
8483 <description>Peripheral increment offset
8484 size</description>
8485 <bitOffset>15</bitOffset>
8486 <bitWidth>1</bitWidth>
8487 </field>
8488 <field>
8489 <name>MSIZE</name>
8490 <description>Memory data size</description>
8491 <bitOffset>13</bitOffset>
8492 <bitWidth>2</bitWidth>
8493 </field>
8494 <field>
8495 <name>PSIZE</name>
8496 <description>Peripheral data size</description>
8497 <bitOffset>11</bitOffset>
8498 <bitWidth>2</bitWidth>
8499 </field>
8500 <field>
8501 <name>MINC</name>
8502 <description>Memory increment mode</description>
8503 <bitOffset>10</bitOffset>
8504 <bitWidth>1</bitWidth>
8505 </field>
8506 <field>
8507 <name>PINC</name>
8508 <description>Peripheral increment mode</description>
8509 <bitOffset>9</bitOffset>
8510 <bitWidth>1</bitWidth>
8511 </field>
8512 <field>
8513 <name>CIRC</name>
8514 <description>Circular mode</description>
8515 <bitOffset>8</bitOffset>
8516 <bitWidth>1</bitWidth>
8517 </field>
8518 <field>
8519 <name>DIR</name>
8520 <description>Data transfer direction</description>
8521 <bitOffset>6</bitOffset>
8522 <bitWidth>2</bitWidth>
8523 </field>
8524 <field>
8525 <name>PFCTRL</name>
8526 <description>Peripheral flow controller</description>
8527 <bitOffset>5</bitOffset>
8528 <bitWidth>1</bitWidth>
8529 </field>
8530 <field>
8531 <name>TCIE</name>
8532 <description>Transfer complete interrupt
8533 enable</description>
8534 <bitOffset>4</bitOffset>
8535 <bitWidth>1</bitWidth>
8536 </field>
8537 <field>
8538 <name>HTIE</name>
8539 <description>Half transfer interrupt
8540 enable</description>
8541 <bitOffset>3</bitOffset>
8542 <bitWidth>1</bitWidth>
8543 </field>
8544 <field>
8545 <name>TEIE</name>
8546 <description>Transfer error interrupt
8547 enable</description>
8548 <bitOffset>2</bitOffset>
8549 <bitWidth>1</bitWidth>
8550 </field>
8551 <field>
8552 <name>DMEIE</name>
8553 <description>Direct mode error interrupt
8554 enable</description>
8555 <bitOffset>1</bitOffset>
8556 <bitWidth>1</bitWidth>
8557 </field>
8558 <field>
8559 <name>EN</name>
8560 <description>Stream enable / flag stream ready when
8561 read low</description>
8562 <bitOffset>0</bitOffset>
8563 <bitWidth>1</bitWidth>
8564 </field>
8565 </fields>
8566 </register>
8567 <register>
8568 <name>S5NDTR</name>
8569 <displayName>S5NDTR</displayName>
8570 <description>stream x number of data
8571 register</description>
8572 <addressOffset>0x8C</addressOffset>
8573 <size>0x20</size>
8574 <access>read-write</access>
8575 <resetValue>0x00000000</resetValue>
8576 <fields>
8577 <field>
8578 <name>NDT</name>
8579 <description>Number of data items to
8580 transfer</description>
8581 <bitOffset>0</bitOffset>
8582 <bitWidth>16</bitWidth>
8583 </field>
8584 </fields>
8585 </register>
8586 <register>
8587 <name>S5PAR</name>
8588 <displayName>S5PAR</displayName>
8589 <description>stream x peripheral address
8590 register</description>
8591 <addressOffset>0x90</addressOffset>
8592 <size>0x20</size>
8593 <access>read-write</access>
8594 <resetValue>0x00000000</resetValue>
8595 <fields>
8596 <field>
8597 <name>PA</name>
8598 <description>Peripheral address</description>
8599 <bitOffset>0</bitOffset>
8600 <bitWidth>32</bitWidth>
8601 </field>
8602 </fields>
8603 </register>
8604 <register>
8605 <name>S5M0AR</name>
8606 <displayName>S5M0AR</displayName>
8607 <description>stream x memory 0 address
8608 register</description>
8609 <addressOffset>0x94</addressOffset>
8610 <size>0x20</size>
8611 <access>read-write</access>
8612 <resetValue>0x00000000</resetValue>
8613 <fields>
8614 <field>
8615 <name>M0A</name>
8616 <description>Memory 0 address</description>
8617 <bitOffset>0</bitOffset>
8618 <bitWidth>32</bitWidth>
8619 </field>
8620 </fields>
8621 </register>
8622 <register>
8623 <name>S5M1AR</name>
8624 <displayName>S5M1AR</displayName>
8625 <description>stream x memory 1 address
8626 register</description>
8627 <addressOffset>0x98</addressOffset>
8628 <size>0x20</size>
8629 <access>read-write</access>
8630 <resetValue>0x00000000</resetValue>
8631 <fields>
8632 <field>
8633 <name>M1A</name>
8634 <description>Memory 1 address (used in case of Double
8635 buffer mode)</description>
8636 <bitOffset>0</bitOffset>
8637 <bitWidth>32</bitWidth>
8638 </field>
8639 </fields>
8640 </register>
8641 <register>
8642 <name>S5FCR</name>
8643 <displayName>S5FCR</displayName>
8644 <description>stream x FIFO control register</description>
8645 <addressOffset>0x9C</addressOffset>
8646 <size>0x20</size>
8647 <resetValue>0x00000021</resetValue>
8648 <fields>
8649 <field>
8650 <name>FEIE</name>
8651 <description>FIFO error interrupt
8652 enable</description>
8653 <bitOffset>7</bitOffset>
8654 <bitWidth>1</bitWidth>
8655 <access>read-write</access>
8656 </field>
8657 <field>
8658 <name>FS</name>
8659 <description>FIFO status</description>
8660 <bitOffset>3</bitOffset>
8661 <bitWidth>3</bitWidth>
8662 <access>read-only</access>
8663 </field>
8664 <field>
8665 <name>DMDIS</name>
8666 <description>Direct mode disable</description>
8667 <bitOffset>2</bitOffset>
8668 <bitWidth>1</bitWidth>
8669 <access>read-write</access>
8670 </field>
8671 <field>
8672 <name>FTH</name>
8673 <description>FIFO threshold selection</description>
8674 <bitOffset>0</bitOffset>
8675 <bitWidth>2</bitWidth>
8676 <access>read-write</access>
8677 </field>
8678 </fields>
8679 </register>
8680 <register>
8681 <name>S6CR</name>
8682 <displayName>S6CR</displayName>
8683 <description>stream x configuration
8684 register</description>
8685 <addressOffset>0xA0</addressOffset>
8686 <size>0x20</size>
8687 <access>read-write</access>
8688 <resetValue>0x00000000</resetValue>
8689 <fields>
8690 <field>
8691 <name>CHSEL</name>
8692 <description>Channel selection</description>
8693 <bitOffset>25</bitOffset>
8694 <bitWidth>3</bitWidth>
8695 </field>
8696 <field>
8697 <name>MBURST</name>
8698 <description>Memory burst transfer
8699 configuration</description>
8700 <bitOffset>23</bitOffset>
8701 <bitWidth>2</bitWidth>
8702 </field>
8703 <field>
8704 <name>PBURST</name>
8705 <description>Peripheral burst transfer
8706 configuration</description>
8707 <bitOffset>21</bitOffset>
8708 <bitWidth>2</bitWidth>
8709 </field>
8710 <field>
8711 <name>ACK</name>
8712 <description>ACK</description>
8713 <bitOffset>20</bitOffset>
8714 <bitWidth>1</bitWidth>
8715 </field>
8716 <field>
8717 <name>CT</name>
8718 <description>Current target (only in double buffer
8719 mode)</description>
8720 <bitOffset>19</bitOffset>
8721 <bitWidth>1</bitWidth>
8722 </field>
8723 <field>
8724 <name>DBM</name>
8725 <description>Double buffer mode</description>
8726 <bitOffset>18</bitOffset>
8727 <bitWidth>1</bitWidth>
8728 </field>
8729 <field>
8730 <name>PL</name>
8731 <description>Priority level</description>
8732 <bitOffset>16</bitOffset>
8733 <bitWidth>2</bitWidth>
8734 </field>
8735 <field>
8736 <name>PINCOS</name>
8737 <description>Peripheral increment offset
8738 size</description>
8739 <bitOffset>15</bitOffset>
8740 <bitWidth>1</bitWidth>
8741 </field>
8742 <field>
8743 <name>MSIZE</name>
8744 <description>Memory data size</description>
8745 <bitOffset>13</bitOffset>
8746 <bitWidth>2</bitWidth>
8747 </field>
8748 <field>
8749 <name>PSIZE</name>
8750 <description>Peripheral data size</description>
8751 <bitOffset>11</bitOffset>
8752 <bitWidth>2</bitWidth>
8753 </field>
8754 <field>
8755 <name>MINC</name>
8756 <description>Memory increment mode</description>
8757 <bitOffset>10</bitOffset>
8758 <bitWidth>1</bitWidth>
8759 </field>
8760 <field>
8761 <name>PINC</name>
8762 <description>Peripheral increment mode</description>
8763 <bitOffset>9</bitOffset>
8764 <bitWidth>1</bitWidth>
8765 </field>
8766 <field>
8767 <name>CIRC</name>
8768 <description>Circular mode</description>
8769 <bitOffset>8</bitOffset>
8770 <bitWidth>1</bitWidth>
8771 </field>
8772 <field>
8773 <name>DIR</name>
8774 <description>Data transfer direction</description>
8775 <bitOffset>6</bitOffset>
8776 <bitWidth>2</bitWidth>
8777 </field>
8778 <field>
8779 <name>PFCTRL</name>
8780 <description>Peripheral flow controller</description>
8781 <bitOffset>5</bitOffset>
8782 <bitWidth>1</bitWidth>
8783 </field>
8784 <field>
8785 <name>TCIE</name>
8786 <description>Transfer complete interrupt
8787 enable</description>
8788 <bitOffset>4</bitOffset>
8789 <bitWidth>1</bitWidth>
8790 </field>
8791 <field>
8792 <name>HTIE</name>
8793 <description>Half transfer interrupt
8794 enable</description>
8795 <bitOffset>3</bitOffset>
8796 <bitWidth>1</bitWidth>
8797 </field>
8798 <field>
8799 <name>TEIE</name>
8800 <description>Transfer error interrupt
8801 enable</description>
8802 <bitOffset>2</bitOffset>
8803 <bitWidth>1</bitWidth>
8804 </field>
8805 <field>
8806 <name>DMEIE</name>
8807 <description>Direct mode error interrupt
8808 enable</description>
8809 <bitOffset>1</bitOffset>
8810 <bitWidth>1</bitWidth>
8811 </field>
8812 <field>
8813 <name>EN</name>
8814 <description>Stream enable / flag stream ready when
8815 read low</description>
8816 <bitOffset>0</bitOffset>
8817 <bitWidth>1</bitWidth>
8818 </field>
8819 </fields>
8820 </register>
8821 <register>
8822 <name>S6NDTR</name>
8823 <displayName>S6NDTR</displayName>
8824 <description>stream x number of data
8825 register</description>
8826 <addressOffset>0xA4</addressOffset>
8827 <size>0x20</size>
8828 <access>read-write</access>
8829 <resetValue>0x00000000</resetValue>
8830 <fields>
8831 <field>
8832 <name>NDT</name>
8833 <description>Number of data items to
8834 transfer</description>
8835 <bitOffset>0</bitOffset>
8836 <bitWidth>16</bitWidth>
8837 </field>
8838 </fields>
8839 </register>
8840 <register>
8841 <name>S6PAR</name>
8842 <displayName>S6PAR</displayName>
8843 <description>stream x peripheral address
8844 register</description>
8845 <addressOffset>0xA8</addressOffset>
8846 <size>0x20</size>
8847 <access>read-write</access>
8848 <resetValue>0x00000000</resetValue>
8849 <fields>
8850 <field>
8851 <name>PA</name>
8852 <description>Peripheral address</description>
8853 <bitOffset>0</bitOffset>
8854 <bitWidth>32</bitWidth>
8855 </field>
8856 </fields>
8857 </register>
8858 <register>
8859 <name>S6M0AR</name>
8860 <displayName>S6M0AR</displayName>
8861 <description>stream x memory 0 address
8862 register</description>
8863 <addressOffset>0xAC</addressOffset>
8864 <size>0x20</size>
8865 <access>read-write</access>
8866 <resetValue>0x00000000</resetValue>
8867 <fields>
8868 <field>
8869 <name>M0A</name>
8870 <description>Memory 0 address</description>
8871 <bitOffset>0</bitOffset>
8872 <bitWidth>32</bitWidth>
8873 </field>
8874 </fields>
8875 </register>
8876 <register>
8877 <name>S6M1AR</name>
8878 <displayName>S6M1AR</displayName>
8879 <description>stream x memory 1 address
8880 register</description>
8881 <addressOffset>0xB0</addressOffset>
8882 <size>0x20</size>
8883 <access>read-write</access>
8884 <resetValue>0x00000000</resetValue>
8885 <fields>
8886 <field>
8887 <name>M1A</name>
8888 <description>Memory 1 address (used in case of Double
8889 buffer mode)</description>
8890 <bitOffset>0</bitOffset>
8891 <bitWidth>32</bitWidth>
8892 </field>
8893 </fields>
8894 </register>
8895 <register>
8896 <name>S6FCR</name>
8897 <displayName>S6FCR</displayName>
8898 <description>stream x FIFO control register</description>
8899 <addressOffset>0xB4</addressOffset>
8900 <size>0x20</size>
8901 <resetValue>0x00000021</resetValue>
8902 <fields>
8903 <field>
8904 <name>FEIE</name>
8905 <description>FIFO error interrupt
8906 enable</description>
8907 <bitOffset>7</bitOffset>
8908 <bitWidth>1</bitWidth>
8909 <access>read-write</access>
8910 </field>
8911 <field>
8912 <name>FS</name>
8913 <description>FIFO status</description>
8914 <bitOffset>3</bitOffset>
8915 <bitWidth>3</bitWidth>
8916 <access>read-only</access>
8917 </field>
8918 <field>
8919 <name>DMDIS</name>
8920 <description>Direct mode disable</description>
8921 <bitOffset>2</bitOffset>
8922 <bitWidth>1</bitWidth>
8923 <access>read-write</access>
8924 </field>
8925 <field>
8926 <name>FTH</name>
8927 <description>FIFO threshold selection</description>
8928 <bitOffset>0</bitOffset>
8929 <bitWidth>2</bitWidth>
8930 <access>read-write</access>
8931 </field>
8932 </fields>
8933 </register>
8934 <register>
8935 <name>S7CR</name>
8936 <displayName>S7CR</displayName>
8937 <description>stream x configuration
8938 register</description>
8939 <addressOffset>0xB8</addressOffset>
8940 <size>0x20</size>
8941 <access>read-write</access>
8942 <resetValue>0x00000000</resetValue>
8943 <fields>
8944 <field>
8945 <name>CHSEL</name>
8946 <description>Channel selection</description>
8947 <bitOffset>25</bitOffset>
8948 <bitWidth>3</bitWidth>
8949 </field>
8950 <field>
8951 <name>MBURST</name>
8952 <description>Memory burst transfer
8953 configuration</description>
8954 <bitOffset>23</bitOffset>
8955 <bitWidth>2</bitWidth>
8956 </field>
8957 <field>
8958 <name>PBURST</name>
8959 <description>Peripheral burst transfer
8960 configuration</description>
8961 <bitOffset>21</bitOffset>
8962 <bitWidth>2</bitWidth>
8963 </field>
8964 <field>
8965 <name>ACK</name>
8966 <description>ACK</description>
8967 <bitOffset>20</bitOffset>
8968 <bitWidth>1</bitWidth>
8969 </field>
8970 <field>
8971 <name>CT</name>
8972 <description>Current target (only in double buffer
8973 mode)</description>
8974 <bitOffset>19</bitOffset>
8975 <bitWidth>1</bitWidth>
8976 </field>
8977 <field>
8978 <name>DBM</name>
8979 <description>Double buffer mode</description>
8980 <bitOffset>18</bitOffset>
8981 <bitWidth>1</bitWidth>
8982 </field>
8983 <field>
8984 <name>PL</name>
8985 <description>Priority level</description>
8986 <bitOffset>16</bitOffset>
8987 <bitWidth>2</bitWidth>
8988 </field>
8989 <field>
8990 <name>PINCOS</name>
8991 <description>Peripheral increment offset
8992 size</description>
8993 <bitOffset>15</bitOffset>
8994 <bitWidth>1</bitWidth>
8995 </field>
8996 <field>
8997 <name>MSIZE</name>
8998 <description>Memory data size</description>
8999 <bitOffset>13</bitOffset>
9000 <bitWidth>2</bitWidth>
9001 </field>
9002 <field>
9003 <name>PSIZE</name>
9004 <description>Peripheral data size</description>
9005 <bitOffset>11</bitOffset>
9006 <bitWidth>2</bitWidth>
9007 </field>
9008 <field>
9009 <name>MINC</name>
9010 <description>Memory increment mode</description>
9011 <bitOffset>10</bitOffset>
9012 <bitWidth>1</bitWidth>
9013 </field>
9014 <field>
9015 <name>PINC</name>
9016 <description>Peripheral increment mode</description>
9017 <bitOffset>9</bitOffset>
9018 <bitWidth>1</bitWidth>
9019 </field>
9020 <field>
9021 <name>CIRC</name>
9022 <description>Circular mode</description>
9023 <bitOffset>8</bitOffset>
9024 <bitWidth>1</bitWidth>
9025 </field>
9026 <field>
9027 <name>DIR</name>
9028 <description>Data transfer direction</description>
9029 <bitOffset>6</bitOffset>
9030 <bitWidth>2</bitWidth>
9031 </field>
9032 <field>
9033 <name>PFCTRL</name>
9034 <description>Peripheral flow controller</description>
9035 <bitOffset>5</bitOffset>
9036 <bitWidth>1</bitWidth>
9037 </field>
9038 <field>
9039 <name>TCIE</name>
9040 <description>Transfer complete interrupt
9041 enable</description>
9042 <bitOffset>4</bitOffset>
9043 <bitWidth>1</bitWidth>
9044 </field>
9045 <field>
9046 <name>HTIE</name>
9047 <description>Half transfer interrupt
9048 enable</description>
9049 <bitOffset>3</bitOffset>
9050 <bitWidth>1</bitWidth>
9051 </field>
9052 <field>
9053 <name>TEIE</name>
9054 <description>Transfer error interrupt
9055 enable</description>
9056 <bitOffset>2</bitOffset>
9057 <bitWidth>1</bitWidth>
9058 </field>
9059 <field>
9060 <name>DMEIE</name>
9061 <description>Direct mode error interrupt
9062 enable</description>
9063 <bitOffset>1</bitOffset>
9064 <bitWidth>1</bitWidth>
9065 </field>
9066 <field>
9067 <name>EN</name>
9068 <description>Stream enable / flag stream ready when
9069 read low</description>
9070 <bitOffset>0</bitOffset>
9071 <bitWidth>1</bitWidth>
9072 </field>
9073 </fields>
9074 </register>
9075 <register>
9076 <name>S7NDTR</name>
9077 <displayName>S7NDTR</displayName>
9078 <description>stream x number of data
9079 register</description>
9080 <addressOffset>0xBC</addressOffset>
9081 <size>0x20</size>
9082 <access>read-write</access>
9083 <resetValue>0x00000000</resetValue>
9084 <fields>
9085 <field>
9086 <name>NDT</name>
9087 <description>Number of data items to
9088 transfer</description>
9089 <bitOffset>0</bitOffset>
9090 <bitWidth>16</bitWidth>
9091 </field>
9092 </fields>
9093 </register>
9094 <register>
9095 <name>S7PAR</name>
9096 <displayName>S7PAR</displayName>
9097 <description>stream x peripheral address
9098 register</description>
9099 <addressOffset>0xC0</addressOffset>
9100 <size>0x20</size>
9101 <access>read-write</access>
9102 <resetValue>0x00000000</resetValue>
9103 <fields>
9104 <field>
9105 <name>PA</name>
9106 <description>Peripheral address</description>
9107 <bitOffset>0</bitOffset>
9108 <bitWidth>32</bitWidth>
9109 </field>
9110 </fields>
9111 </register>
9112 <register>
9113 <name>S7M0AR</name>
9114 <displayName>S7M0AR</displayName>
9115 <description>stream x memory 0 address
9116 register</description>
9117 <addressOffset>0xC4</addressOffset>
9118 <size>0x20</size>
9119 <access>read-write</access>
9120 <resetValue>0x00000000</resetValue>
9121 <fields>
9122 <field>
9123 <name>M0A</name>
9124 <description>Memory 0 address</description>
9125 <bitOffset>0</bitOffset>
9126 <bitWidth>32</bitWidth>
9127 </field>
9128 </fields>
9129 </register>
9130 <register>
9131 <name>S7M1AR</name>
9132 <displayName>S7M1AR</displayName>
9133 <description>stream x memory 1 address
9134 register</description>
9135 <addressOffset>0xC8</addressOffset>
9136 <size>0x20</size>
9137 <access>read-write</access>
9138 <resetValue>0x00000000</resetValue>
9139 <fields>
9140 <field>
9141 <name>M1A</name>
9142 <description>Memory 1 address (used in case of Double
9143 buffer mode)</description>
9144 <bitOffset>0</bitOffset>
9145 <bitWidth>32</bitWidth>
9146 </field>
9147 </fields>
9148 </register>
9149 <register>
9150 <name>S7FCR</name>
9151 <displayName>S7FCR</displayName>
9152 <description>stream x FIFO control register</description>
9153 <addressOffset>0xCC</addressOffset>
9154 <size>0x20</size>
9155 <resetValue>0x00000021</resetValue>
9156 <fields>
9157 <field>
9158 <name>FEIE</name>
9159 <description>FIFO error interrupt
9160 enable</description>
9161 <bitOffset>7</bitOffset>
9162 <bitWidth>1</bitWidth>
9163 <access>read-write</access>
9164 </field>
9165 <field>
9166 <name>FS</name>
9167 <description>FIFO status</description>
9168 <bitOffset>3</bitOffset>
9169 <bitWidth>3</bitWidth>
9170 <access>read-only</access>
9171 </field>
9172 <field>
9173 <name>DMDIS</name>
9174 <description>Direct mode disable</description>
9175 <bitOffset>2</bitOffset>
9176 <bitWidth>1</bitWidth>
9177 <access>read-write</access>
9178 </field>
9179 <field>
9180 <name>FTH</name>
9181 <description>FIFO threshold selection</description>
9182 <bitOffset>0</bitOffset>
9183 <bitWidth>2</bitWidth>
9184 <access>read-write</access>
9185 </field>
9186 </fields>
9187 </register>
9188 </registers>
9189 </peripheral>
9190 <peripheral derivedFrom="DMA2">
9191 <name>DMA1</name>
9192 <baseAddress>0x40026000</baseAddress>
9193 <interrupt>
9194 <name>DMA1_Stream0</name>
9195 <description>DMA1 Stream0 global interrupt</description>
9196 <value>11</value>
9197 </interrupt>
9198 <interrupt>
9199 <name>DMA1_Stream1</name>
9200 <description>DMA1 Stream1 global interrupt</description>
9201 <value>12</value>
9202 </interrupt>
9203 <interrupt>
9204 <name>DMA1_Stream2</name>
9205 <description>DMA1 Stream2 global interrupt</description>
9206 <value>13</value>
9207 </interrupt>
9208 <interrupt>
9209 <name>DMA1_Stream3</name>
9210 <description>DMA1 Stream3 global interrupt</description>
9211 <value>14</value>
9212 </interrupt>
9213 <interrupt>
9214 <name>DMA1_Stream4</name>
9215 <description>DMA1 Stream4 global interrupt</description>
9216 <value>15</value>
9217 </interrupt>
9218 <interrupt>
9219 <name>DMA1_Stream5</name>
9220 <description>DMA1 Stream5 global interrupt</description>
9221 <value>16</value>
9222 </interrupt>
9223 <interrupt>
9224 <name>DMA1_Stream6</name>
9225 <description>DMA1 Stream6 global interrupt</description>
9226 <value>17</value>
9227 </interrupt>
9228 <interrupt>
9229 <name>DMA1_Stream7</name>
9230 <description>DMA1 Stream7 global interrupt</description>
9231 <value>47</value>
9232 </interrupt>
9233 </peripheral>
9234 <peripheral>
9235 <name>RCC</name>
9236 <description>Reset and clock control</description>
9237 <groupName>RCC</groupName>
9238 <baseAddress>0x40023800</baseAddress>
9239 <addressBlock>
9240 <offset>0x0</offset>
9241 <size>0x400</size>
9242 <usage>registers</usage>
9243 </addressBlock>
9244 <interrupt>
9245 <name>RCC</name>
9246 <description>RCC global interrupt</description>
9247 <value>5</value>
9248 </interrupt>
9249 <registers>
9250 <register>
9251 <name>CR</name>
9252 <displayName>CR</displayName>
9253 <description>clock control register</description>
9254 <addressOffset>0x0</addressOffset>
9255 <size>0x20</size>
9256 <resetValue>0x00000083</resetValue>
9257 <fields>
9258 <field>
9259 <name>PLLI2SRDY</name>
9260 <description>PLLI2S clock ready flag</description>
9261 <bitOffset>27</bitOffset>
9262 <bitWidth>1</bitWidth>
9263 <access>read-only</access>
9264 </field>
9265 <field>
9266 <name>PLLI2SON</name>
9267 <description>PLLI2S enable</description>
9268 <bitOffset>26</bitOffset>
9269 <bitWidth>1</bitWidth>
9270 <access>read-write</access>
9271 </field>
9272 <field>
9273 <name>PLLRDY</name>
9274 <description>Main PLL (PLL) clock ready
9275 flag</description>
9276 <bitOffset>25</bitOffset>
9277 <bitWidth>1</bitWidth>
9278 <access>read-only</access>
9279 </field>
9280 <field>
9281 <name>PLLON</name>
9282 <description>Main PLL (PLL) enable</description>
9283 <bitOffset>24</bitOffset>
9284 <bitWidth>1</bitWidth>
9285 <access>read-write</access>
9286 </field>
9287 <field>
9288 <name>CSSON</name>
9289 <description>Clock security system
9290 enable</description>
9291 <bitOffset>19</bitOffset>
9292 <bitWidth>1</bitWidth>
9293 <access>read-write</access>
9294 </field>
9295 <field>
9296 <name>HSEBYP</name>
9297 <description>HSE clock bypass</description>
9298 <bitOffset>18</bitOffset>
9299 <bitWidth>1</bitWidth>
9300 <access>read-write</access>
9301 </field>
9302 <field>
9303 <name>HSERDY</name>
9304 <description>HSE clock ready flag</description>
9305 <bitOffset>17</bitOffset>
9306 <bitWidth>1</bitWidth>
9307 <access>read-only</access>
9308 </field>
9309 <field>
9310 <name>HSEON</name>
9311 <description>HSE clock enable</description>
9312 <bitOffset>16</bitOffset>
9313 <bitWidth>1</bitWidth>
9314 <access>read-write</access>
9315 </field>
9316 <field>
9317 <name>HSICAL</name>
9318 <description>Internal high-speed clock
9319 calibration</description>
9320 <bitOffset>8</bitOffset>
9321 <bitWidth>8</bitWidth>
9322 <access>read-only</access>
9323 </field>
9324 <field>
9325 <name>HSITRIM</name>
9326 <description>Internal high-speed clock
9327 trimming</description>
9328 <bitOffset>3</bitOffset>
9329 <bitWidth>5</bitWidth>
9330 <access>read-write</access>
9331 </field>
9332 <field>
9333 <name>HSIRDY</name>
9334 <description>Internal high-speed clock ready
9335 flag</description>
9336 <bitOffset>1</bitOffset>
9337 <bitWidth>1</bitWidth>
9338 <access>read-only</access>
9339 </field>
9340 <field>
9341 <name>HSION</name>
9342 <description>Internal high-speed clock
9343 enable</description>
9344 <bitOffset>0</bitOffset>
9345 <bitWidth>1</bitWidth>
9346 <access>read-write</access>
9347 </field>
9348 </fields>
9349 </register>
9350 <register>
9351 <name>PLLCFGR</name>
9352 <displayName>PLLCFGR</displayName>
9353 <description>PLL configuration register</description>
9354 <addressOffset>0x4</addressOffset>
9355 <size>0x20</size>
9356 <access>read-write</access>
9357 <resetValue>0x24003010</resetValue>
9358 <fields>
9359 <field>
9360 <name>PLLQ3</name>
9361 <description>Main PLL (PLL) division factor for USB
9362 OTG FS, SDIO and random number generator
9363 clocks</description>
9364 <bitOffset>27</bitOffset>
9365 <bitWidth>1</bitWidth>
9366 </field>
9367 <field>
9368 <name>PLLQ2</name>
9369 <description>Main PLL (PLL) division factor for USB
9370 OTG FS, SDIO and random number generator
9371 clocks</description>
9372 <bitOffset>26</bitOffset>
9373 <bitWidth>1</bitWidth>
9374 </field>
9375 <field>
9376 <name>PLLQ1</name>
9377 <description>Main PLL (PLL) division factor for USB
9378 OTG FS, SDIO and random number generator
9379 clocks</description>
9380 <bitOffset>25</bitOffset>
9381 <bitWidth>1</bitWidth>
9382 </field>
9383 <field>
9384 <name>PLLQ0</name>
9385 <description>Main PLL (PLL) division factor for USB
9386 OTG FS, SDIO and random number generator
9387 clocks</description>
9388 <bitOffset>24</bitOffset>
9389 <bitWidth>1</bitWidth>
9390 </field>
9391 <field>
9392 <name>PLLSRC</name>
9393 <description>Main PLL(PLL) and audio PLL (PLLI2S)
9394 entry clock source</description>
9395 <bitOffset>22</bitOffset>
9396 <bitWidth>1</bitWidth>
9397 </field>
9398 <field>
9399 <name>PLLP1</name>
9400 <description>Main PLL (PLL) division factor for main
9401 system clock</description>
9402 <bitOffset>17</bitOffset>
9403 <bitWidth>1</bitWidth>
9404 </field>
9405 <field>
9406 <name>PLLP0</name>
9407 <description>Main PLL (PLL) division factor for main
9408 system clock</description>
9409 <bitOffset>16</bitOffset>
9410 <bitWidth>1</bitWidth>
9411 </field>
9412 <field>
9413 <name>PLLN8</name>
9414 <description>Main PLL (PLL) multiplication factor for
9415 VCO</description>
9416 <bitOffset>14</bitOffset>
9417 <bitWidth>1</bitWidth>
9418 </field>
9419 <field>
9420 <name>PLLN7</name>
9421 <description>Main PLL (PLL) multiplication factor for
9422 VCO</description>
9423 <bitOffset>13</bitOffset>
9424 <bitWidth>1</bitWidth>
9425 </field>
9426 <field>
9427 <name>PLLN6</name>
9428 <description>Main PLL (PLL) multiplication factor for
9429 VCO</description>
9430 <bitOffset>12</bitOffset>
9431 <bitWidth>1</bitWidth>
9432 </field>
9433 <field>
9434 <name>PLLN5</name>
9435 <description>Main PLL (PLL) multiplication factor for
9436 VCO</description>
9437 <bitOffset>11</bitOffset>
9438 <bitWidth>1</bitWidth>
9439 </field>
9440 <field>
9441 <name>PLLN4</name>
9442 <description>Main PLL (PLL) multiplication factor for
9443 VCO</description>
9444 <bitOffset>10</bitOffset>
9445 <bitWidth>1</bitWidth>
9446 </field>
9447 <field>
9448 <name>PLLN3</name>
9449 <description>Main PLL (PLL) multiplication factor for
9450 VCO</description>
9451 <bitOffset>9</bitOffset>
9452 <bitWidth>1</bitWidth>
9453 </field>
9454 <field>
9455 <name>PLLN2</name>
9456 <description>Main PLL (PLL) multiplication factor for
9457 VCO</description>
9458 <bitOffset>8</bitOffset>
9459 <bitWidth>1</bitWidth>
9460 </field>
9461 <field>
9462 <name>PLLN1</name>
9463 <description>Main PLL (PLL) multiplication factor for
9464 VCO</description>
9465 <bitOffset>7</bitOffset>
9466 <bitWidth>1</bitWidth>
9467 </field>
9468 <field>
9469 <name>PLLN0</name>
9470 <description>Main PLL (PLL) multiplication factor for
9471 VCO</description>
9472 <bitOffset>6</bitOffset>
9473 <bitWidth>1</bitWidth>
9474 </field>
9475 <field>
9476 <name>PLLM5</name>
9477 <description>Division factor for the main PLL (PLL)
9478 and audio PLL (PLLI2S) input clock</description>
9479 <bitOffset>5</bitOffset>
9480 <bitWidth>1</bitWidth>
9481 </field>
9482 <field>
9483 <name>PLLM4</name>
9484 <description>Division factor for the main PLL (PLL)
9485 and audio PLL (PLLI2S) input clock</description>
9486 <bitOffset>4</bitOffset>
9487 <bitWidth>1</bitWidth>
9488 </field>
9489 <field>
9490 <name>PLLM3</name>
9491 <description>Division factor for the main PLL (PLL)
9492 and audio PLL (PLLI2S) input clock</description>
9493 <bitOffset>3</bitOffset>
9494 <bitWidth>1</bitWidth>
9495 </field>
9496 <field>
9497 <name>PLLM2</name>
9498 <description>Division factor for the main PLL (PLL)
9499 and audio PLL (PLLI2S) input clock</description>
9500 <bitOffset>2</bitOffset>
9501 <bitWidth>1</bitWidth>
9502 </field>
9503 <field>
9504 <name>PLLM1</name>
9505 <description>Division factor for the main PLL (PLL)
9506 and audio PLL (PLLI2S) input clock</description>
9507 <bitOffset>1</bitOffset>
9508 <bitWidth>1</bitWidth>
9509 </field>
9510 <field>
9511 <name>PLLM0</name>
9512 <description>Division factor for the main PLL (PLL)
9513 and audio PLL (PLLI2S) input clock</description>
9514 <bitOffset>0</bitOffset>
9515 <bitWidth>1</bitWidth>
9516 </field>
9517 </fields>
9518 </register>
9519 <register>
9520 <name>CFGR</name>
9521 <displayName>CFGR</displayName>
9522 <description>clock configuration register</description>
9523 <addressOffset>0x8</addressOffset>
9524 <size>0x20</size>
9525 <resetValue>0x00000000</resetValue>
9526 <fields>
9527 <field>
9528 <name>MCO2</name>
9529 <description>Microcontroller clock output
9530 2</description>
9531 <bitOffset>30</bitOffset>
9532 <bitWidth>2</bitWidth>
9533 <access>read-write</access>
9534 </field>
9535 <field>
9536 <name>MCO2PRE</name>
9537 <description>MCO2 prescaler</description>
9538 <bitOffset>27</bitOffset>
9539 <bitWidth>3</bitWidth>
9540 <access>read-write</access>
9541 </field>
9542 <field>
9543 <name>MCO1PRE</name>
9544 <description>MCO1 prescaler</description>
9545 <bitOffset>24</bitOffset>
9546 <bitWidth>3</bitWidth>
9547 <access>read-write</access>
9548 </field>
9549 <field>
9550 <name>I2SSRC</name>
9551 <description>I2S clock selection</description>
9552 <bitOffset>23</bitOffset>
9553 <bitWidth>1</bitWidth>
9554 <access>read-write</access>
9555 </field>
9556 <field>
9557 <name>MCO1</name>
9558 <description>Microcontroller clock output
9559 1</description>
9560 <bitOffset>21</bitOffset>
9561 <bitWidth>2</bitWidth>
9562 <access>read-write</access>
9563 </field>
9564 <field>
9565 <name>RTCPRE</name>
9566 <description>HSE division factor for RTC
9567 clock</description>
9568 <bitOffset>16</bitOffset>
9569 <bitWidth>5</bitWidth>
9570 <access>read-write</access>
9571 </field>
9572 <field>
9573 <name>PPRE2</name>
9574 <description>APB high-speed prescaler
9575 (APB2)</description>
9576 <bitOffset>13</bitOffset>
9577 <bitWidth>3</bitWidth>
9578 <access>read-write</access>
9579 </field>
9580 <field>
9581 <name>PPRE1</name>
9582 <description>APB Low speed prescaler
9583 (APB1)</description>
9584 <bitOffset>10</bitOffset>
9585 <bitWidth>3</bitWidth>
9586 <access>read-write</access>
9587 </field>
9588 <field>
9589 <name>HPRE</name>
9590 <description>AHB prescaler</description>
9591 <bitOffset>4</bitOffset>
9592 <bitWidth>4</bitWidth>
9593 <access>read-write</access>
9594 </field>
9595 <field>
9596 <name>SWS1</name>
9597 <description>System clock switch status</description>
9598 <bitOffset>3</bitOffset>
9599 <bitWidth>1</bitWidth>
9600 <access>read-only</access>
9601 </field>
9602 <field>
9603 <name>SWS0</name>
9604 <description>System clock switch status</description>
9605 <bitOffset>2</bitOffset>
9606 <bitWidth>1</bitWidth>
9607 <access>read-only</access>
9608 </field>
9609 <field>
9610 <name>SW1</name>
9611 <description>System clock switch</description>
9612 <bitOffset>1</bitOffset>
9613 <bitWidth>1</bitWidth>
9614 <access>read-write</access>
9615 </field>
9616 <field>
9617 <name>SW0</name>
9618 <description>System clock switch</description>
9619 <bitOffset>0</bitOffset>
9620 <bitWidth>1</bitWidth>
9621 <access>read-write</access>
9622 </field>
9623 </fields>
9624 </register>
9625 <register>
9626 <name>CIR</name>
9627 <displayName>CIR</displayName>
9628 <description>clock interrupt register</description>
9629 <addressOffset>0xC</addressOffset>
9630 <size>0x20</size>
9631 <resetValue>0x00000000</resetValue>
9632 <fields>
9633 <field>
9634 <name>CSSC</name>
9635 <description>Clock security system interrupt
9636 clear</description>
9637 <bitOffset>23</bitOffset>
9638 <bitWidth>1</bitWidth>
9639 <access>write-only</access>
9640 </field>
9641 <field>
9642 <name>PLLSAIRDYC</name>
9643 <description>PLLSAI Ready Interrupt
9644 Clear</description>
9645 <bitOffset>22</bitOffset>
9646 <bitWidth>1</bitWidth>
9647 <access>write-only</access>
9648 </field>
9649 <field>
9650 <name>PLLI2SRDYC</name>
9651 <description>PLLI2S ready interrupt
9652 clear</description>
9653 <bitOffset>21</bitOffset>
9654 <bitWidth>1</bitWidth>
9655 <access>write-only</access>
9656 </field>
9657 <field>
9658 <name>PLLRDYC</name>
9659 <description>Main PLL(PLL) ready interrupt
9660 clear</description>
9661 <bitOffset>20</bitOffset>
9662 <bitWidth>1</bitWidth>
9663 <access>write-only</access>
9664 </field>
9665 <field>
9666 <name>HSERDYC</name>
9667 <description>HSE ready interrupt clear</description>
9668 <bitOffset>19</bitOffset>
9669 <bitWidth>1</bitWidth>
9670 <access>write-only</access>
9671 </field>
9672 <field>
9673 <name>HSIRDYC</name>
9674 <description>HSI ready interrupt clear</description>
9675 <bitOffset>18</bitOffset>
9676 <bitWidth>1</bitWidth>
9677 <access>write-only</access>
9678 </field>
9679 <field>
9680 <name>LSERDYC</name>
9681 <description>LSE ready interrupt clear</description>
9682 <bitOffset>17</bitOffset>
9683 <bitWidth>1</bitWidth>
9684 <access>write-only</access>
9685 </field>
9686 <field>
9687 <name>LSIRDYC</name>
9688 <description>LSI ready interrupt clear</description>
9689 <bitOffset>16</bitOffset>
9690 <bitWidth>1</bitWidth>
9691 <access>write-only</access>
9692 </field>
9693 <field>
9694 <name>PLLSAIRDYIE</name>
9695 <description>PLLSAI Ready Interrupt
9696 Enable</description>
9697 <bitOffset>14</bitOffset>
9698 <bitWidth>1</bitWidth>
9699 <access>read-write</access>
9700 </field>
9701 <field>
9702 <name>PLLI2SRDYIE</name>
9703 <description>PLLI2S ready interrupt
9704 enable</description>
9705 <bitOffset>13</bitOffset>
9706 <bitWidth>1</bitWidth>
9707 <access>read-write</access>
9708 </field>
9709 <field>
9710 <name>PLLRDYIE</name>
9711 <description>Main PLL (PLL) ready interrupt
9712 enable</description>
9713 <bitOffset>12</bitOffset>
9714 <bitWidth>1</bitWidth>
9715 <access>read-write</access>
9716 </field>
9717 <field>
9718 <name>HSERDYIE</name>
9719 <description>HSE ready interrupt enable</description>
9720 <bitOffset>11</bitOffset>
9721 <bitWidth>1</bitWidth>
9722 <access>read-write</access>
9723 </field>
9724 <field>
9725 <name>HSIRDYIE</name>
9726 <description>HSI ready interrupt enable</description>
9727 <bitOffset>10</bitOffset>
9728 <bitWidth>1</bitWidth>
9729 <access>read-write</access>
9730 </field>
9731 <field>
9732 <name>LSERDYIE</name>
9733 <description>LSE ready interrupt enable</description>
9734 <bitOffset>9</bitOffset>
9735 <bitWidth>1</bitWidth>
9736 <access>read-write</access>
9737 </field>
9738 <field>
9739 <name>LSIRDYIE</name>
9740 <description>LSI ready interrupt enable</description>
9741 <bitOffset>8</bitOffset>
9742 <bitWidth>1</bitWidth>
9743 <access>read-write</access>
9744 </field>
9745 <field>
9746 <name>CSSF</name>
9747 <description>Clock security system interrupt
9748 flag</description>
9749 <bitOffset>7</bitOffset>
9750 <bitWidth>1</bitWidth>
9751 <access>read-only</access>
9752 </field>
9753 <field>
9754 <name>PLLSAIRDYF</name>
9755 <description>PLLSAI ready interrupt
9756 flag</description>
9757 <bitOffset>6</bitOffset>
9758 <bitWidth>1</bitWidth>
9759 <access>read-only</access>
9760 </field>
9761 <field>
9762 <name>PLLI2SRDYF</name>
9763 <description>PLLI2S ready interrupt
9764 flag</description>
9765 <bitOffset>5</bitOffset>
9766 <bitWidth>1</bitWidth>
9767 <access>read-only</access>
9768 </field>
9769 <field>
9770 <name>PLLRDYF</name>
9771 <description>Main PLL (PLL) ready interrupt
9772 flag</description>
9773 <bitOffset>4</bitOffset>
9774 <bitWidth>1</bitWidth>
9775 <access>read-only</access>
9776 </field>
9777 <field>
9778 <name>HSERDYF</name>
9779 <description>HSE ready interrupt flag</description>
9780 <bitOffset>3</bitOffset>
9781 <bitWidth>1</bitWidth>
9782 <access>read-only</access>
9783 </field>
9784 <field>
9785 <name>HSIRDYF</name>
9786 <description>HSI ready interrupt flag</description>
9787 <bitOffset>2</bitOffset>
9788 <bitWidth>1</bitWidth>
9789 <access>read-only</access>
9790 </field>
9791 <field>
9792 <name>LSERDYF</name>
9793 <description>LSE ready interrupt flag</description>
9794 <bitOffset>1</bitOffset>
9795 <bitWidth>1</bitWidth>
9796 <access>read-only</access>
9797 </field>
9798 <field>
9799 <name>LSIRDYF</name>
9800 <description>LSI ready interrupt flag</description>
9801 <bitOffset>0</bitOffset>
9802 <bitWidth>1</bitWidth>
9803 <access>read-only</access>
9804 </field>
9805 </fields>
9806 </register>
9807 <register>
9808 <name>AHB1RSTR</name>
9809 <displayName>AHB1RSTR</displayName>
9810 <description>AHB1 peripheral reset register</description>
9811 <addressOffset>0x10</addressOffset>
9812 <size>0x20</size>
9813 <access>read-write</access>
9814 <resetValue>0x00000000</resetValue>
9815 <fields>
9816 <field>
9817 <name>OTGHSRST</name>
9818 <description>USB OTG HS module reset</description>
9819 <bitOffset>29</bitOffset>
9820 <bitWidth>1</bitWidth>
9821 </field>
9822 <field>
9823 <name>ETHMACRST</name>
9824 <description>Ethernet MAC reset</description>
9825 <bitOffset>25</bitOffset>
9826 <bitWidth>1</bitWidth>
9827 </field>
9828 <field>
9829 <name>DMA2DRST</name>
9830 <description>DMA2D reset</description>
9831 <bitOffset>23</bitOffset>
9832 <bitWidth>1</bitWidth>
9833 </field>
9834 <field>
9835 <name>DMA2RST</name>
9836 <description>DMA2 reset</description>
9837 <bitOffset>22</bitOffset>
9838 <bitWidth>1</bitWidth>
9839 </field>
9840 <field>
9841 <name>DMA1RST</name>
9842 <description>DMA2 reset</description>
9843 <bitOffset>21</bitOffset>
9844 <bitWidth>1</bitWidth>
9845 </field>
9846 <field>
9847 <name>CRCRST</name>
9848 <description>CRC reset</description>
9849 <bitOffset>12</bitOffset>
9850 <bitWidth>1</bitWidth>
9851 </field>
9852 <field>
9853 <name>GPIOKRST</name>
9854 <description>IO port K reset</description>
9855 <bitOffset>10</bitOffset>
9856 <bitWidth>1</bitWidth>
9857 </field>
9858 <field>
9859 <name>GPIOJRST</name>
9860 <description>IO port J reset</description>
9861 <bitOffset>9</bitOffset>
9862 <bitWidth>1</bitWidth>
9863 </field>
9864 <field>
9865 <name>GPIOIRST</name>
9866 <description>IO port I reset</description>
9867 <bitOffset>8</bitOffset>
9868 <bitWidth>1</bitWidth>
9869 </field>
9870 <field>
9871 <name>GPIOHRST</name>
9872 <description>IO port H reset</description>
9873 <bitOffset>7</bitOffset>
9874 <bitWidth>1</bitWidth>
9875 </field>
9876 <field>
9877 <name>GPIOGRST</name>
9878 <description>IO port G reset</description>
9879 <bitOffset>6</bitOffset>
9880 <bitWidth>1</bitWidth>
9881 </field>
9882 <field>
9883 <name>GPIOFRST</name>
9884 <description>IO port F reset</description>
9885 <bitOffset>5</bitOffset>
9886 <bitWidth>1</bitWidth>
9887 </field>
9888 <field>
9889 <name>GPIOERST</name>
9890 <description>IO port E reset</description>
9891 <bitOffset>4</bitOffset>
9892 <bitWidth>1</bitWidth>
9893 </field>
9894 <field>
9895 <name>GPIODRST</name>
9896 <description>IO port D reset</description>
9897 <bitOffset>3</bitOffset>
9898 <bitWidth>1</bitWidth>
9899 </field>
9900 <field>
9901 <name>GPIOCRST</name>
9902 <description>IO port C reset</description>
9903 <bitOffset>2</bitOffset>
9904 <bitWidth>1</bitWidth>
9905 </field>
9906 <field>
9907 <name>GPIOBRST</name>
9908 <description>IO port B reset</description>
9909 <bitOffset>1</bitOffset>
9910 <bitWidth>1</bitWidth>
9911 </field>
9912 <field>
9913 <name>GPIOARST</name>
9914 <description>IO port A reset</description>
9915 <bitOffset>0</bitOffset>
9916 <bitWidth>1</bitWidth>
9917 </field>
9918 </fields>
9919 </register>
9920 <register>
9921 <name>AHB2RSTR</name>
9922 <displayName>AHB2RSTR</displayName>
9923 <description>AHB2 peripheral reset register</description>
9924 <addressOffset>0x14</addressOffset>
9925 <size>0x20</size>
9926 <access>read-write</access>
9927 <resetValue>0x00000000</resetValue>
9928 <fields>
9929 <field>
9930 <name>OTGFSRST</name>
9931 <description>USB OTG FS module reset</description>
9932 <bitOffset>7</bitOffset>
9933 <bitWidth>1</bitWidth>
9934 </field>
9935 <field>
9936 <name>RNGRST</name>
9937 <description>Random number generator module
9938 reset</description>
9939 <bitOffset>6</bitOffset>
9940 <bitWidth>1</bitWidth>
9941 </field>
9942 <field>
9943 <name>HSAHRST</name>
9944 <description>Hash module reset</description>
9945 <bitOffset>5</bitOffset>
9946 <bitWidth>1</bitWidth>
9947 </field>
9948 <field>
9949 <name>CRYPRST</name>
9950 <description>Cryptographic module reset</description>
9951 <bitOffset>4</bitOffset>
9952 <bitWidth>1</bitWidth>
9953 </field>
9954 <field>
9955 <name>DCMIRST</name>
9956 <description>Camera interface reset</description>
9957 <bitOffset>0</bitOffset>
9958 <bitWidth>1</bitWidth>
9959 </field>
9960 </fields>
9961 </register>
9962 <register>
9963 <name>AHB3RSTR</name>
9964 <displayName>AHB3RSTR</displayName>
9965 <description>AHB3 peripheral reset register</description>
9966 <addressOffset>0x18</addressOffset>
9967 <size>0x20</size>
9968 <access>read-write</access>
9969 <resetValue>0x00000000</resetValue>
9970 <fields>
9971 <field>
9972 <name>FMCRST</name>
9973 <description>Flexible memory controller module
9974 reset</description>
9975 <bitOffset>0</bitOffset>
9976 <bitWidth>1</bitWidth>
9977 </field>
9978 <field>
9979 <name>QSPIRST</name>
9980 <description>Quad SPI memory controller
9981 reset</description>
9982 <bitOffset>1</bitOffset>
9983 <bitWidth>1</bitWidth>
9984 </field>
9985 </fields>
9986 </register>
9987 <register>
9988 <name>APB1RSTR</name>
9989 <displayName>APB1RSTR</displayName>
9990 <description>APB1 peripheral reset register</description>
9991 <addressOffset>0x20</addressOffset>
9992 <size>0x20</size>
9993 <access>read-write</access>
9994 <resetValue>0x00000000</resetValue>
9995 <fields>
9996 <field>
9997 <name>TIM2RST</name>
9998 <description>TIM2 reset</description>
9999 <bitOffset>0</bitOffset>
10000 <bitWidth>1</bitWidth>
10001 </field>
10002 <field>
10003 <name>TIM3RST</name>
10004 <description>TIM3 reset</description>
10005 <bitOffset>1</bitOffset>
10006 <bitWidth>1</bitWidth>
10007 </field>
10008 <field>
10009 <name>TIM4RST</name>
10010 <description>TIM4 reset</description>
10011 <bitOffset>2</bitOffset>
10012 <bitWidth>1</bitWidth>
10013 </field>
10014 <field>
10015 <name>TIM5RST</name>
10016 <description>TIM5 reset</description>
10017 <bitOffset>3</bitOffset>
10018 <bitWidth>1</bitWidth>
10019 </field>
10020 <field>
10021 <name>TIM6RST</name>
10022 <description>TIM6 reset</description>
10023 <bitOffset>4</bitOffset>
10024 <bitWidth>1</bitWidth>
10025 </field>
10026 <field>
10027 <name>TIM7RST</name>
10028 <description>TIM7 reset</description>
10029 <bitOffset>5</bitOffset>
10030 <bitWidth>1</bitWidth>
10031 </field>
10032 <field>
10033 <name>TIM12RST</name>
10034 <description>TIM12 reset</description>
10035 <bitOffset>6</bitOffset>
10036 <bitWidth>1</bitWidth>
10037 </field>
10038 <field>
10039 <name>TIM13RST</name>
10040 <description>TIM13 reset</description>
10041 <bitOffset>7</bitOffset>
10042 <bitWidth>1</bitWidth>
10043 </field>
10044 <field>
10045 <name>TIM14RST</name>
10046 <description>TIM14 reset</description>
10047 <bitOffset>8</bitOffset>
10048 <bitWidth>1</bitWidth>
10049 </field>
10050 <field>
10051 <name>WWDGRST</name>
10052 <description>Window watchdog reset</description>
10053 <bitOffset>11</bitOffset>
10054 <bitWidth>1</bitWidth>
10055 </field>
10056 <field>
10057 <name>SPI2RST</name>
10058 <description>SPI 2 reset</description>
10059 <bitOffset>14</bitOffset>
10060 <bitWidth>1</bitWidth>
10061 </field>
10062 <field>
10063 <name>SPI3RST</name>
10064 <description>SPI 3 reset</description>
10065 <bitOffset>15</bitOffset>
10066 <bitWidth>1</bitWidth>
10067 </field>
10068 <field>
10069 <name>UART2RST</name>
10070 <description>USART 2 reset</description>
10071 <bitOffset>17</bitOffset>
10072 <bitWidth>1</bitWidth>
10073 </field>
10074 <field>
10075 <name>UART3RST</name>
10076 <description>USART 3 reset</description>
10077 <bitOffset>18</bitOffset>
10078 <bitWidth>1</bitWidth>
10079 </field>
10080 <field>
10081 <name>UART4RST</name>
10082 <description>USART 4 reset</description>
10083 <bitOffset>19</bitOffset>
10084 <bitWidth>1</bitWidth>
10085 </field>
10086 <field>
10087 <name>UART5RST</name>
10088 <description>USART 5 reset</description>
10089 <bitOffset>20</bitOffset>
10090 <bitWidth>1</bitWidth>
10091 </field>
10092 <field>
10093 <name>I2C1RST</name>
10094 <description>I2C 1 reset</description>
10095 <bitOffset>21</bitOffset>
10096 <bitWidth>1</bitWidth>
10097 </field>
10098 <field>
10099 <name>I2C2RST</name>
10100 <description>I2C 2 reset</description>
10101 <bitOffset>22</bitOffset>
10102 <bitWidth>1</bitWidth>
10103 </field>
10104 <field>
10105 <name>I2C3RST</name>
10106 <description>I2C3 reset</description>
10107 <bitOffset>23</bitOffset>
10108 <bitWidth>1</bitWidth>
10109 </field>
10110 <field>
10111 <name>CAN1RST</name>
10112 <description>CAN1 reset</description>
10113 <bitOffset>25</bitOffset>
10114 <bitWidth>1</bitWidth>
10115 </field>
10116 <field>
10117 <name>CAN2RST</name>
10118 <description>CAN2 reset</description>
10119 <bitOffset>26</bitOffset>
10120 <bitWidth>1</bitWidth>
10121 </field>
10122 <field>
10123 <name>PWRRST</name>
10124 <description>Power interface reset</description>
10125 <bitOffset>28</bitOffset>
10126 <bitWidth>1</bitWidth>
10127 </field>
10128 <field>
10129 <name>DACRST</name>
10130 <description>DAC reset</description>
10131 <bitOffset>29</bitOffset>
10132 <bitWidth>1</bitWidth>
10133 </field>
10134 <field>
10135 <name>UART7RST</name>
10136 <description>UART7 reset</description>
10137 <bitOffset>30</bitOffset>
10138 <bitWidth>1</bitWidth>
10139 </field>
10140 <field>
10141 <name>UART8RST</name>
10142 <description>UART8 reset</description>
10143 <bitOffset>31</bitOffset>
10144 <bitWidth>1</bitWidth>
10145 </field>
10146 <field>
10147 <name>SPDIFRXRST</name>
10148 <description>SPDIF-RX reset</description>
10149 <bitOffset>16</bitOffset>
10150 <bitWidth>1</bitWidth>
10151 </field>
10152 <field>
10153 <name>CECRST</name>
10154 <description>HDMI-CEC reset</description>
10155 <bitOffset>27</bitOffset>
10156 <bitWidth>1</bitWidth>
10157 </field>
10158 <field>
10159 <name>LPTIM1RST</name>
10160 <description>Low power timer 1 reset</description>
10161 <bitOffset>9</bitOffset>
10162 <bitWidth>1</bitWidth>
10163 </field>
10164 <field>
10165 <name>I2C4RST</name>
10166 <description>I2C 4 reset</description>
10167 <bitOffset>24</bitOffset>
10168 <bitWidth>1</bitWidth>
10169 </field>
10170 </fields>
10171 </register>
10172 <register>
10173 <name>APB2RSTR</name>
10174 <displayName>APB2RSTR</displayName>
10175 <description>APB2 peripheral reset register</description>
10176 <addressOffset>0x24</addressOffset>
10177 <size>0x20</size>
10178 <access>read-write</access>
10179 <resetValue>0x00000000</resetValue>
10180 <fields>
10181 <field>
10182 <name>TIM1RST</name>
10183 <description>TIM1 reset</description>
10184 <bitOffset>0</bitOffset>
10185 <bitWidth>1</bitWidth>
10186 </field>
10187 <field>
10188 <name>TIM8RST</name>
10189 <description>TIM8 reset</description>
10190 <bitOffset>1</bitOffset>
10191 <bitWidth>1</bitWidth>
10192 </field>
10193 <field>
10194 <name>USART1RST</name>
10195 <description>USART1 reset</description>
10196 <bitOffset>4</bitOffset>
10197 <bitWidth>1</bitWidth>
10198 </field>
10199 <field>
10200 <name>USART6RST</name>
10201 <description>USART6 reset</description>
10202 <bitOffset>5</bitOffset>
10203 <bitWidth>1</bitWidth>
10204 </field>
10205 <field>
10206 <name>ADCRST</name>
10207 <description>ADC interface reset (common to all
10208 ADCs)</description>
10209 <bitOffset>8</bitOffset>
10210 <bitWidth>1</bitWidth>
10211 </field>
10212 <field>
10213 <name>SPI1RST</name>
10214 <description>SPI 1 reset</description>
10215 <bitOffset>12</bitOffset>
10216 <bitWidth>1</bitWidth>
10217 </field>
10218 <field>
10219 <name>SPI4RST</name>
10220 <description>SPI4 reset</description>
10221 <bitOffset>13</bitOffset>
10222 <bitWidth>1</bitWidth>
10223 </field>
10224 <field>
10225 <name>SYSCFGRST</name>
10226 <description>System configuration controller
10227 reset</description>
10228 <bitOffset>14</bitOffset>
10229 <bitWidth>1</bitWidth>
10230 </field>
10231 <field>
10232 <name>TIM9RST</name>
10233 <description>TIM9 reset</description>
10234 <bitOffset>16</bitOffset>
10235 <bitWidth>1</bitWidth>
10236 </field>
10237 <field>
10238 <name>TIM10RST</name>
10239 <description>TIM10 reset</description>
10240 <bitOffset>17</bitOffset>
10241 <bitWidth>1</bitWidth>
10242 </field>
10243 <field>
10244 <name>TIM11RST</name>
10245 <description>TIM11 reset</description>
10246 <bitOffset>18</bitOffset>
10247 <bitWidth>1</bitWidth>
10248 </field>
10249 <field>
10250 <name>SPI5RST</name>
10251 <description>SPI5 reset</description>
10252 <bitOffset>20</bitOffset>
10253 <bitWidth>1</bitWidth>
10254 </field>
10255 <field>
10256 <name>SPI6RST</name>
10257 <description>SPI6 reset</description>
10258 <bitOffset>21</bitOffset>
10259 <bitWidth>1</bitWidth>
10260 </field>
10261 <field>
10262 <name>SAI1RST</name>
10263 <description>SAI1 reset</description>
10264 <bitOffset>22</bitOffset>
10265 <bitWidth>1</bitWidth>
10266 </field>
10267 <field>
10268 <name>LTDCRST</name>
10269 <description>LTDC reset</description>
10270 <bitOffset>26</bitOffset>
10271 <bitWidth>1</bitWidth>
10272 </field>
10273 <field>
10274 <name>SAI2RST</name>
10275 <description>SAI2 reset</description>
10276 <bitOffset>23</bitOffset>
10277 <bitWidth>1</bitWidth>
10278 </field>
10279 <field>
10280 <name>SDMMC1RST</name>
10281 <description>SDMMC1 reset</description>
10282 <bitOffset>11</bitOffset>
10283 <bitWidth>1</bitWidth>
10284 </field>
10285 </fields>
10286 </register>
10287 <register>
10288 <name>AHB1ENR</name>
10289 <displayName>AHB1ENR</displayName>
10290 <description>AHB1 peripheral clock register</description>
10291 <addressOffset>0x30</addressOffset>
10292 <size>0x20</size>
10293 <access>read-write</access>
10294 <resetValue>0x00100000</resetValue>
10295 <fields>
10296 <field>
10297 <name>OTGHSULPIEN</name>
10298 <description>USB OTG HSULPI clock
10299 enable</description>
10300 <bitOffset>30</bitOffset>
10301 <bitWidth>1</bitWidth>
10302 </field>
10303 <field>
10304 <name>OTGHSEN</name>
10305 <description>USB OTG HS clock enable</description>
10306 <bitOffset>29</bitOffset>
10307 <bitWidth>1</bitWidth>
10308 </field>
10309 <field>
10310 <name>ETHMACPTPEN</name>
10311 <description>Ethernet PTP clock enable</description>
10312 <bitOffset>28</bitOffset>
10313 <bitWidth>1</bitWidth>
10314 </field>
10315 <field>
10316 <name>ETHMACRXEN</name>
10317 <description>Ethernet Reception clock
10318 enable</description>
10319 <bitOffset>27</bitOffset>
10320 <bitWidth>1</bitWidth>
10321 </field>
10322 <field>
10323 <name>ETHMACTXEN</name>
10324 <description>Ethernet Transmission clock
10325 enable</description>
10326 <bitOffset>26</bitOffset>
10327 <bitWidth>1</bitWidth>
10328 </field>
10329 <field>
10330 <name>ETHMACEN</name>
10331 <description>Ethernet MAC clock enable</description>
10332 <bitOffset>25</bitOffset>
10333 <bitWidth>1</bitWidth>
10334 </field>
10335 <field>
10336 <name>DMA2DEN</name>
10337 <description>DMA2D clock enable</description>
10338 <bitOffset>23</bitOffset>
10339 <bitWidth>1</bitWidth>
10340 </field>
10341 <field>
10342 <name>DMA2EN</name>
10343 <description>DMA2 clock enable</description>
10344 <bitOffset>22</bitOffset>
10345 <bitWidth>1</bitWidth>
10346 </field>
10347 <field>
10348 <name>DMA1EN</name>
10349 <description>DMA1 clock enable</description>
10350 <bitOffset>21</bitOffset>
10351 <bitWidth>1</bitWidth>
10352 </field>
10353 <field>
10354 <name>CCMDATARAMEN</name>
10355 <description>CCM data RAM clock enable</description>
10356 <bitOffset>20</bitOffset>
10357 <bitWidth>1</bitWidth>
10358 </field>
10359 <field>
10360 <name>BKPSRAMEN</name>
10361 <description>Backup SRAM interface clock
10362 enable</description>
10363 <bitOffset>18</bitOffset>
10364 <bitWidth>1</bitWidth>
10365 </field>
10366 <field>
10367 <name>CRCEN</name>
10368 <description>CRC clock enable</description>
10369 <bitOffset>12</bitOffset>
10370 <bitWidth>1</bitWidth>
10371 </field>
10372 <field>
10373 <name>GPIOKEN</name>
10374 <description>IO port K clock enable</description>
10375 <bitOffset>10</bitOffset>
10376 <bitWidth>1</bitWidth>
10377 </field>
10378 <field>
10379 <name>GPIOJEN</name>
10380 <description>IO port J clock enable</description>
10381 <bitOffset>9</bitOffset>
10382 <bitWidth>1</bitWidth>
10383 </field>
10384 <field>
10385 <name>GPIOIEN</name>
10386 <description>IO port I clock enable</description>
10387 <bitOffset>8</bitOffset>
10388 <bitWidth>1</bitWidth>
10389 </field>
10390 <field>
10391 <name>GPIOHEN</name>
10392 <description>IO port H clock enable</description>
10393 <bitOffset>7</bitOffset>
10394 <bitWidth>1</bitWidth>
10395 </field>
10396 <field>
10397 <name>GPIOGEN</name>
10398 <description>IO port G clock enable</description>
10399 <bitOffset>6</bitOffset>
10400 <bitWidth>1</bitWidth>
10401 </field>
10402 <field>
10403 <name>GPIOFEN</name>
10404 <description>IO port F clock enable</description>
10405 <bitOffset>5</bitOffset>
10406 <bitWidth>1</bitWidth>
10407 </field>
10408 <field>
10409 <name>GPIOEEN</name>
10410 <description>IO port E clock enable</description>
10411 <bitOffset>4</bitOffset>
10412 <bitWidth>1</bitWidth>
10413 </field>
10414 <field>
10415 <name>GPIODEN</name>
10416 <description>IO port D clock enable</description>
10417 <bitOffset>3</bitOffset>
10418 <bitWidth>1</bitWidth>
10419 </field>
10420 <field>
10421 <name>GPIOCEN</name>
10422 <description>IO port C clock enable</description>
10423 <bitOffset>2</bitOffset>
10424 <bitWidth>1</bitWidth>
10425 </field>
10426 <field>
10427 <name>GPIOBEN</name>
10428 <description>IO port B clock enable</description>
10429 <bitOffset>1</bitOffset>
10430 <bitWidth>1</bitWidth>
10431 </field>
10432 <field>
10433 <name>GPIOAEN</name>
10434 <description>IO port A clock enable</description>
10435 <bitOffset>0</bitOffset>
10436 <bitWidth>1</bitWidth>
10437 </field>
10438 </fields>
10439 </register>
10440 <register>
10441 <name>AHB2ENR</name>
10442 <displayName>AHB2ENR</displayName>
10443 <description>AHB2 peripheral clock enable
10444 register</description>
10445 <addressOffset>0x34</addressOffset>
10446 <size>0x20</size>
10447 <access>read-write</access>
10448 <resetValue>0x00000000</resetValue>
10449 <fields>
10450 <field>
10451 <name>OTGFSEN</name>
10452 <description>USB OTG FS clock enable</description>
10453 <bitOffset>7</bitOffset>
10454 <bitWidth>1</bitWidth>
10455 </field>
10456 <field>
10457 <name>RNGEN</name>
10458 <description>Random number generator clock
10459 enable</description>
10460 <bitOffset>6</bitOffset>
10461 <bitWidth>1</bitWidth>
10462 </field>
10463 <field>
10464 <name>HASHEN</name>
10465 <description>Hash modules clock enable</description>
10466 <bitOffset>5</bitOffset>
10467 <bitWidth>1</bitWidth>
10468 </field>
10469 <field>
10470 <name>CRYPEN</name>
10471 <description>Cryptographic modules clock
10472 enable</description>
10473 <bitOffset>4</bitOffset>
10474 <bitWidth>1</bitWidth>
10475 </field>
10476 <field>
10477 <name>DCMIEN</name>
10478 <description>Camera interface enable</description>
10479 <bitOffset>0</bitOffset>
10480 <bitWidth>1</bitWidth>
10481 </field>
10482 </fields>
10483 </register>
10484 <register>
10485 <name>AHB3ENR</name>
10486 <displayName>AHB3ENR</displayName>
10487 <description>AHB3 peripheral clock enable
10488 register</description>
10489 <addressOffset>0x38</addressOffset>
10490 <size>0x20</size>
10491 <access>read-write</access>
10492 <resetValue>0x00000000</resetValue>
10493 <fields>
10494 <field>
10495 <name>FMCEN</name>
10496 <description>Flexible memory controller module clock
10497 enable</description>
10498 <bitOffset>0</bitOffset>
10499 <bitWidth>1</bitWidth>
10500 </field>
10501 <field>
10502 <name>QSPIEN</name>
10503 <description>Quad SPI memory controller clock
10504 enable</description>
10505 <bitOffset>1</bitOffset>
10506 <bitWidth>1</bitWidth>
10507 </field>
10508 </fields>
10509 </register>
10510 <register>
10511 <name>APB1ENR</name>
10512 <displayName>APB1ENR</displayName>
10513 <description>APB1 peripheral clock enable
10514 register</description>
10515 <addressOffset>0x40</addressOffset>
10516 <size>0x20</size>
10517 <access>read-write</access>
10518 <resetValue>0x00000000</resetValue>
10519 <fields>
10520 <field>
10521 <name>TIM2EN</name>
10522 <description>TIM2 clock enable</description>
10523 <bitOffset>0</bitOffset>
10524 <bitWidth>1</bitWidth>
10525 </field>
10526 <field>
10527 <name>TIM3EN</name>
10528 <description>TIM3 clock enable</description>
10529 <bitOffset>1</bitOffset>
10530 <bitWidth>1</bitWidth>
10531 </field>
10532 <field>
10533 <name>TIM4EN</name>
10534 <description>TIM4 clock enable</description>
10535 <bitOffset>2</bitOffset>
10536 <bitWidth>1</bitWidth>
10537 </field>
10538 <field>
10539 <name>TIM5EN</name>
10540 <description>TIM5 clock enable</description>
10541 <bitOffset>3</bitOffset>
10542 <bitWidth>1</bitWidth>
10543 </field>
10544 <field>
10545 <name>TIM6EN</name>
10546 <description>TIM6 clock enable</description>
10547 <bitOffset>4</bitOffset>
10548 <bitWidth>1</bitWidth>
10549 </field>
10550 <field>
10551 <name>TIM7EN</name>
10552 <description>TIM7 clock enable</description>
10553 <bitOffset>5</bitOffset>
10554 <bitWidth>1</bitWidth>
10555 </field>
10556 <field>
10557 <name>TIM12EN</name>
10558 <description>TIM12 clock enable</description>
10559 <bitOffset>6</bitOffset>
10560 <bitWidth>1</bitWidth>
10561 </field>
10562 <field>
10563 <name>TIM13EN</name>
10564 <description>TIM13 clock enable</description>
10565 <bitOffset>7</bitOffset>
10566 <bitWidth>1</bitWidth>
10567 </field>
10568 <field>
10569 <name>TIM14EN</name>
10570 <description>TIM14 clock enable</description>
10571 <bitOffset>8</bitOffset>
10572 <bitWidth>1</bitWidth>
10573 </field>
10574 <field>
10575 <name>WWDGEN</name>
10576 <description>Window watchdog clock
10577 enable</description>
10578 <bitOffset>11</bitOffset>
10579 <bitWidth>1</bitWidth>
10580 </field>
10581 <field>
10582 <name>SPI2EN</name>
10583 <description>SPI2 clock enable</description>
10584 <bitOffset>14</bitOffset>
10585 <bitWidth>1</bitWidth>
10586 </field>
10587 <field>
10588 <name>SPI3EN</name>
10589 <description>SPI3 clock enable</description>
10590 <bitOffset>15</bitOffset>
10591 <bitWidth>1</bitWidth>
10592 </field>
10593 <field>
10594 <name>USART2EN</name>
10595 <description>USART 2 clock enable</description>
10596 <bitOffset>17</bitOffset>
10597 <bitWidth>1</bitWidth>
10598 </field>
10599 <field>
10600 <name>USART3EN</name>
10601 <description>USART3 clock enable</description>
10602 <bitOffset>18</bitOffset>
10603 <bitWidth>1</bitWidth>
10604 </field>
10605 <field>
10606 <name>UART4EN</name>
10607 <description>UART4 clock enable</description>
10608 <bitOffset>19</bitOffset>
10609 <bitWidth>1</bitWidth>
10610 </field>
10611 <field>
10612 <name>UART5EN</name>
10613 <description>UART5 clock enable</description>
10614 <bitOffset>20</bitOffset>
10615 <bitWidth>1</bitWidth>
10616 </field>
10617 <field>
10618 <name>I2C1EN</name>
10619 <description>I2C1 clock enable</description>
10620 <bitOffset>21</bitOffset>
10621 <bitWidth>1</bitWidth>
10622 </field>
10623 <field>
10624 <name>I2C2EN</name>
10625 <description>I2C2 clock enable</description>
10626 <bitOffset>22</bitOffset>
10627 <bitWidth>1</bitWidth>
10628 </field>
10629 <field>
10630 <name>I2C3EN</name>
10631 <description>I2C3 clock enable</description>
10632 <bitOffset>23</bitOffset>
10633 <bitWidth>1</bitWidth>
10634 </field>
10635 <field>
10636 <name>CAN1EN</name>
10637 <description>CAN 1 clock enable</description>
10638 <bitOffset>25</bitOffset>
10639 <bitWidth>1</bitWidth>
10640 </field>
10641 <field>
10642 <name>CAN2EN</name>
10643 <description>CAN 2 clock enable</description>
10644 <bitOffset>26</bitOffset>
10645 <bitWidth>1</bitWidth>
10646 </field>
10647 <field>
10648 <name>PWREN</name>
10649 <description>Power interface clock
10650 enable</description>
10651 <bitOffset>28</bitOffset>
10652 <bitWidth>1</bitWidth>
10653 </field>
10654 <field>
10655 <name>DACEN</name>
10656 <description>DAC interface clock enable</description>
10657 <bitOffset>29</bitOffset>
10658 <bitWidth>1</bitWidth>
10659 </field>
10660 <field>
10661 <name>UART7ENR</name>
10662 <description>UART7 clock enable</description>
10663 <bitOffset>30</bitOffset>
10664 <bitWidth>1</bitWidth>
10665 </field>
10666 <field>
10667 <name>UART8ENR</name>
10668 <description>UART8 clock enable</description>
10669 <bitOffset>31</bitOffset>
10670 <bitWidth>1</bitWidth>
10671 </field>
10672 <field>
10673 <name>SPDIFRXEN</name>
10674 <description>SPDIF-RX clock enable</description>
10675 <bitOffset>16</bitOffset>
10676 <bitWidth>1</bitWidth>
10677 </field>
10678 <field>
10679 <name>CECEN</name>
10680 <description>HDMI-CEN clock enable</description>
10681 <bitOffset>27</bitOffset>
10682 <bitWidth>1</bitWidth>
10683 </field>
10684 <field>
10685 <name>LPTMI1EN</name>
10686 <description>Low power timer 1 clock
10687 enable</description>
10688 <bitOffset>9</bitOffset>
10689 <bitWidth>1</bitWidth>
10690 </field>
10691 <field>
10692 <name>I2C4EN</name>
10693 <description>I2C4 clock enable</description>
10694 <bitOffset>24</bitOffset>
10695 <bitWidth>1</bitWidth>
10696 </field>
10697 </fields>
10698 </register>
10699 <register>
10700 <name>APB2ENR</name>
10701 <displayName>APB2ENR</displayName>
10702 <description>APB2 peripheral clock enable
10703 register</description>
10704 <addressOffset>0x44</addressOffset>
10705 <size>0x20</size>
10706 <access>read-write</access>
10707 <resetValue>0x00000000</resetValue>
10708 <fields>
10709 <field>
10710 <name>TIM1EN</name>
10711 <description>TIM1 clock enable</description>
10712 <bitOffset>0</bitOffset>
10713 <bitWidth>1</bitWidth>
10714 </field>
10715 <field>
10716 <name>TIM8EN</name>
10717 <description>TIM8 clock enable</description>
10718 <bitOffset>1</bitOffset>
10719 <bitWidth>1</bitWidth>
10720 </field>
10721 <field>
10722 <name>USART1EN</name>
10723 <description>USART1 clock enable</description>
10724 <bitOffset>4</bitOffset>
10725 <bitWidth>1</bitWidth>
10726 </field>
10727 <field>
10728 <name>USART6EN</name>
10729 <description>USART6 clock enable</description>
10730 <bitOffset>5</bitOffset>
10731 <bitWidth>1</bitWidth>
10732 </field>
10733 <field>
10734 <name>ADC1EN</name>
10735 <description>ADC1 clock enable</description>
10736 <bitOffset>8</bitOffset>
10737 <bitWidth>1</bitWidth>
10738 </field>
10739 <field>
10740 <name>ADC2EN</name>
10741 <description>ADC2 clock enable</description>
10742 <bitOffset>9</bitOffset>
10743 <bitWidth>1</bitWidth>
10744 </field>
10745 <field>
10746 <name>ADC3EN</name>
10747 <description>ADC3 clock enable</description>
10748 <bitOffset>10</bitOffset>
10749 <bitWidth>1</bitWidth>
10750 </field>
10751 <field>
10752 <name>SPI1EN</name>
10753 <description>SPI1 clock enable</description>
10754 <bitOffset>12</bitOffset>
10755 <bitWidth>1</bitWidth>
10756 </field>
10757 <field>
10758 <name>SPI4ENR</name>
10759 <description>SPI4 clock enable</description>
10760 <bitOffset>13</bitOffset>
10761 <bitWidth>1</bitWidth>
10762 </field>
10763 <field>
10764 <name>SYSCFGEN</name>
10765 <description>System configuration controller clock
10766 enable</description>
10767 <bitOffset>14</bitOffset>
10768 <bitWidth>1</bitWidth>
10769 </field>
10770 <field>
10771 <name>TIM9EN</name>
10772 <description>TIM9 clock enable</description>
10773 <bitOffset>16</bitOffset>
10774 <bitWidth>1</bitWidth>
10775 </field>
10776 <field>
10777 <name>TIM10EN</name>
10778 <description>TIM10 clock enable</description>
10779 <bitOffset>17</bitOffset>
10780 <bitWidth>1</bitWidth>
10781 </field>
10782 <field>
10783 <name>TIM11EN</name>
10784 <description>TIM11 clock enable</description>
10785 <bitOffset>18</bitOffset>
10786 <bitWidth>1</bitWidth>
10787 </field>
10788 <field>
10789 <name>SPI5ENR</name>
10790 <description>SPI5 clock enable</description>
10791 <bitOffset>20</bitOffset>
10792 <bitWidth>1</bitWidth>
10793 </field>
10794 <field>
10795 <name>SPI6ENR</name>
10796 <description>SPI6 clock enable</description>
10797 <bitOffset>21</bitOffset>
10798 <bitWidth>1</bitWidth>
10799 </field>
10800 <field>
10801 <name>SAI1EN</name>
10802 <description>SAI1 clock enable</description>
10803 <bitOffset>22</bitOffset>
10804 <bitWidth>1</bitWidth>
10805 </field>
10806 <field>
10807 <name>LTDCEN</name>
10808 <description>LTDC clock enable</description>
10809 <bitOffset>26</bitOffset>
10810 <bitWidth>1</bitWidth>
10811 </field>
10812 <field>
10813 <name>SAI2EN</name>
10814 <description>SAI2 clock enable</description>
10815 <bitOffset>23</bitOffset>
10816 <bitWidth>1</bitWidth>
10817 </field>
10818 <field>
10819 <name>SDMMC1EN</name>
10820 <description>SDMMC1 clock enable</description>
10821 <bitOffset>11</bitOffset>
10822 <bitWidth>1</bitWidth>
10823 </field>
10824 </fields>
10825 </register>
10826 <register>
10827 <name>AHB1LPENR</name>
10828 <displayName>AHB1LPENR</displayName>
10829 <description>AHB1 peripheral clock enable in low power
10830 mode register</description>
10831 <addressOffset>0x50</addressOffset>
10832 <size>0x20</size>
10833 <access>read-write</access>
10834 <resetValue>0x7E6791FF</resetValue>
10835 <fields>
10836 <field>
10837 <name>GPIOALPEN</name>
10838 <description>IO port A clock enable during sleep
10839 mode</description>
10840 <bitOffset>0</bitOffset>
10841 <bitWidth>1</bitWidth>
10842 </field>
10843 <field>
10844 <name>GPIOBLPEN</name>
10845 <description>IO port B clock enable during Sleep
10846 mode</description>
10847 <bitOffset>1</bitOffset>
10848 <bitWidth>1</bitWidth>
10849 </field>
10850 <field>
10851 <name>GPIOCLPEN</name>
10852 <description>IO port C clock enable during Sleep
10853 mode</description>
10854 <bitOffset>2</bitOffset>
10855 <bitWidth>1</bitWidth>
10856 </field>
10857 <field>
10858 <name>GPIODLPEN</name>
10859 <description>IO port D clock enable during Sleep
10860 mode</description>
10861 <bitOffset>3</bitOffset>
10862 <bitWidth>1</bitWidth>
10863 </field>
10864 <field>
10865 <name>GPIOELPEN</name>
10866 <description>IO port E clock enable during Sleep
10867 mode</description>
10868 <bitOffset>4</bitOffset>
10869 <bitWidth>1</bitWidth>
10870 </field>
10871 <field>
10872 <name>GPIOFLPEN</name>
10873 <description>IO port F clock enable during Sleep
10874 mode</description>
10875 <bitOffset>5</bitOffset>
10876 <bitWidth>1</bitWidth>
10877 </field>
10878 <field>
10879 <name>GPIOGLPEN</name>
10880 <description>IO port G clock enable during Sleep
10881 mode</description>
10882 <bitOffset>6</bitOffset>
10883 <bitWidth>1</bitWidth>
10884 </field>
10885 <field>
10886 <name>GPIOHLPEN</name>
10887 <description>IO port H clock enable during Sleep
10888 mode</description>
10889 <bitOffset>7</bitOffset>
10890 <bitWidth>1</bitWidth>
10891 </field>
10892 <field>
10893 <name>GPIOILPEN</name>
10894 <description>IO port I clock enable during Sleep
10895 mode</description>
10896 <bitOffset>8</bitOffset>
10897 <bitWidth>1</bitWidth>
10898 </field>
10899 <field>
10900 <name>GPIOJLPEN</name>
10901 <description>IO port J clock enable during Sleep
10902 mode</description>
10903 <bitOffset>9</bitOffset>
10904 <bitWidth>1</bitWidth>
10905 </field>
10906 <field>
10907 <name>GPIOKLPEN</name>
10908 <description>IO port K clock enable during Sleep
10909 mode</description>
10910 <bitOffset>10</bitOffset>
10911 <bitWidth>1</bitWidth>
10912 </field>
10913 <field>
10914 <name>CRCLPEN</name>
10915 <description>CRC clock enable during Sleep
10916 mode</description>
10917 <bitOffset>12</bitOffset>
10918 <bitWidth>1</bitWidth>
10919 </field>
10920 <field>
10921 <name>FLITFLPEN</name>
10922 <description>Flash interface clock enable during
10923 Sleep mode</description>
10924 <bitOffset>15</bitOffset>
10925 <bitWidth>1</bitWidth>
10926 </field>
10927 <field>
10928 <name>SRAM1LPEN</name>
10929 <description>SRAM 1interface clock enable during
10930 Sleep mode</description>
10931 <bitOffset>16</bitOffset>
10932 <bitWidth>1</bitWidth>
10933 </field>
10934 <field>
10935 <name>SRAM2LPEN</name>
10936 <description>SRAM 2 interface clock enable during
10937 Sleep mode</description>
10938 <bitOffset>17</bitOffset>
10939 <bitWidth>1</bitWidth>
10940 </field>
10941 <field>
10942 <name>BKPSRAMLPEN</name>
10943 <description>Backup SRAM interface clock enable
10944 during Sleep mode</description>
10945 <bitOffset>18</bitOffset>
10946 <bitWidth>1</bitWidth>
10947 </field>
10948 <field>
10949 <name>SRAM3LPEN</name>
10950 <description>SRAM 3 interface clock enable during
10951 Sleep mode</description>
10952 <bitOffset>19</bitOffset>
10953 <bitWidth>1</bitWidth>
10954 </field>
10955 <field>
10956 <name>DMA1LPEN</name>
10957 <description>DMA1 clock enable during Sleep
10958 mode</description>
10959 <bitOffset>21</bitOffset>
10960 <bitWidth>1</bitWidth>
10961 </field>
10962 <field>
10963 <name>DMA2LPEN</name>
10964 <description>DMA2 clock enable during Sleep
10965 mode</description>
10966 <bitOffset>22</bitOffset>
10967 <bitWidth>1</bitWidth>
10968 </field>
10969 <field>
10970 <name>DMA2DLPEN</name>
10971 <description>DMA2D clock enable during Sleep
10972 mode</description>
10973 <bitOffset>23</bitOffset>
10974 <bitWidth>1</bitWidth>
10975 </field>
10976 <field>
10977 <name>ETHMACLPEN</name>
10978 <description>Ethernet MAC clock enable during Sleep
10979 mode</description>
10980 <bitOffset>25</bitOffset>
10981 <bitWidth>1</bitWidth>
10982 </field>
10983 <field>
10984 <name>ETHMACTXLPEN</name>
10985 <description>Ethernet transmission clock enable
10986 during Sleep mode</description>
10987 <bitOffset>26</bitOffset>
10988 <bitWidth>1</bitWidth>
10989 </field>
10990 <field>
10991 <name>ETHMACRXLPEN</name>
10992 <description>Ethernet reception clock enable during
10993 Sleep mode</description>
10994 <bitOffset>27</bitOffset>
10995 <bitWidth>1</bitWidth>
10996 </field>
10997 <field>
10998 <name>ETHMACPTPLPEN</name>
10999 <description>Ethernet PTP clock enable during Sleep
11000 mode</description>
11001 <bitOffset>28</bitOffset>
11002 <bitWidth>1</bitWidth>
11003 </field>
11004 <field>
11005 <name>OTGHSLPEN</name>
11006 <description>USB OTG HS clock enable during Sleep
11007 mode</description>
11008 <bitOffset>29</bitOffset>
11009 <bitWidth>1</bitWidth>
11010 </field>
11011 <field>
11012 <name>OTGHSULPILPEN</name>
11013 <description>USB OTG HS ULPI clock enable during
11014 Sleep mode</description>
11015 <bitOffset>30</bitOffset>
11016 <bitWidth>1</bitWidth>
11017 </field>
11018 </fields>
11019 </register>
11020 <register>
11021 <name>AHB2LPENR</name>
11022 <displayName>AHB2LPENR</displayName>
11023 <description>AHB2 peripheral clock enable in low power
11024 mode register</description>
11025 <addressOffset>0x54</addressOffset>
11026 <size>0x20</size>
11027 <access>read-write</access>
11028 <resetValue>0x000000F1</resetValue>
11029 <fields>
11030 <field>
11031 <name>OTGFSLPEN</name>
11032 <description>USB OTG FS clock enable during Sleep
11033 mode</description>
11034 <bitOffset>7</bitOffset>
11035 <bitWidth>1</bitWidth>
11036 </field>
11037 <field>
11038 <name>RNGLPEN</name>
11039 <description>Random number generator clock enable
11040 during Sleep mode</description>
11041 <bitOffset>6</bitOffset>
11042 <bitWidth>1</bitWidth>
11043 </field>
11044 <field>
11045 <name>HASHLPEN</name>
11046 <description>Hash modules clock enable during Sleep
11047 mode</description>
11048 <bitOffset>5</bitOffset>
11049 <bitWidth>1</bitWidth>
11050 </field>
11051 <field>
11052 <name>CRYPLPEN</name>
11053 <description>Cryptography modules clock enable during
11054 Sleep mode</description>
11055 <bitOffset>4</bitOffset>
11056 <bitWidth>1</bitWidth>
11057 </field>
11058 <field>
11059 <name>DCMILPEN</name>
11060 <description>Camera interface enable during Sleep
11061 mode</description>
11062 <bitOffset>0</bitOffset>
11063 <bitWidth>1</bitWidth>
11064 </field>
11065 </fields>
11066 </register>
11067 <register>
11068 <name>AHB3LPENR</name>
11069 <displayName>AHB3LPENR</displayName>
11070 <description>AHB3 peripheral clock enable in low power
11071 mode register</description>
11072 <addressOffset>0x58</addressOffset>
11073 <size>0x20</size>
11074 <access>read-write</access>
11075 <resetValue>0x00000001</resetValue>
11076 <fields>
11077 <field>
11078 <name>FMCLPEN</name>
11079 <description>Flexible memory controller module clock
11080 enable during Sleep mode</description>
11081 <bitOffset>0</bitOffset>
11082 <bitWidth>1</bitWidth>
11083 </field>
11084 <field>
11085 <name>QSPILPEN</name>
11086 <description>Quand SPI memory controller clock enable
11087 during Sleep mode</description>
11088 <bitOffset>1</bitOffset>
11089 <bitWidth>1</bitWidth>
11090 </field>
11091 </fields>
11092 </register>
11093 <register>
11094 <name>APB1LPENR</name>
11095 <displayName>APB1LPENR</displayName>
11096 <description>APB1 peripheral clock enable in low power
11097 mode register</description>
11098 <addressOffset>0x60</addressOffset>
11099 <size>0x20</size>
11100 <access>read-write</access>
11101 <resetValue>0x36FEC9FF</resetValue>
11102 <fields>
11103 <field>
11104 <name>TIM2LPEN</name>
11105 <description>TIM2 clock enable during Sleep
11106 mode</description>
11107 <bitOffset>0</bitOffset>
11108 <bitWidth>1</bitWidth>
11109 </field>
11110 <field>
11111 <name>TIM3LPEN</name>
11112 <description>TIM3 clock enable during Sleep
11113 mode</description>
11114 <bitOffset>1</bitOffset>
11115 <bitWidth>1</bitWidth>
11116 </field>
11117 <field>
11118 <name>TIM4LPEN</name>
11119 <description>TIM4 clock enable during Sleep
11120 mode</description>
11121 <bitOffset>2</bitOffset>
11122 <bitWidth>1</bitWidth>
11123 </field>
11124 <field>
11125 <name>TIM5LPEN</name>
11126 <description>TIM5 clock enable during Sleep
11127 mode</description>
11128 <bitOffset>3</bitOffset>
11129 <bitWidth>1</bitWidth>
11130 </field>
11131 <field>
11132 <name>TIM6LPEN</name>
11133 <description>TIM6 clock enable during Sleep
11134 mode</description>
11135 <bitOffset>4</bitOffset>
11136 <bitWidth>1</bitWidth>
11137 </field>
11138 <field>
11139 <name>TIM7LPEN</name>
11140 <description>TIM7 clock enable during Sleep
11141 mode</description>
11142 <bitOffset>5</bitOffset>
11143 <bitWidth>1</bitWidth>
11144 </field>
11145 <field>
11146 <name>TIM12LPEN</name>
11147 <description>TIM12 clock enable during Sleep
11148 mode</description>
11149 <bitOffset>6</bitOffset>
11150 <bitWidth>1</bitWidth>
11151 </field>
11152 <field>
11153 <name>TIM13LPEN</name>
11154 <description>TIM13 clock enable during Sleep
11155 mode</description>
11156 <bitOffset>7</bitOffset>
11157 <bitWidth>1</bitWidth>
11158 </field>
11159 <field>
11160 <name>TIM14LPEN</name>
11161 <description>TIM14 clock enable during Sleep
11162 mode</description>
11163 <bitOffset>8</bitOffset>
11164 <bitWidth>1</bitWidth>
11165 </field>
11166 <field>
11167 <name>WWDGLPEN</name>
11168 <description>Window watchdog clock enable during
11169 Sleep mode</description>
11170 <bitOffset>11</bitOffset>
11171 <bitWidth>1</bitWidth>
11172 </field>
11173 <field>
11174 <name>SPI2LPEN</name>
11175 <description>SPI2 clock enable during Sleep
11176 mode</description>
11177 <bitOffset>14</bitOffset>
11178 <bitWidth>1</bitWidth>
11179 </field>
11180 <field>
11181 <name>SPI3LPEN</name>
11182 <description>SPI3 clock enable during Sleep
11183 mode</description>
11184 <bitOffset>15</bitOffset>
11185 <bitWidth>1</bitWidth>
11186 </field>
11187 <field>
11188 <name>USART2LPEN</name>
11189 <description>USART2 clock enable during Sleep
11190 mode</description>
11191 <bitOffset>17</bitOffset>
11192 <bitWidth>1</bitWidth>
11193 </field>
11194 <field>
11195 <name>USART3LPEN</name>
11196 <description>USART3 clock enable during Sleep
11197 mode</description>
11198 <bitOffset>18</bitOffset>
11199 <bitWidth>1</bitWidth>
11200 </field>
11201 <field>
11202 <name>UART4LPEN</name>
11203 <description>UART4 clock enable during Sleep
11204 mode</description>
11205 <bitOffset>19</bitOffset>
11206 <bitWidth>1</bitWidth>
11207 </field>
11208 <field>
11209 <name>UART5LPEN</name>
11210 <description>UART5 clock enable during Sleep
11211 mode</description>
11212 <bitOffset>20</bitOffset>
11213 <bitWidth>1</bitWidth>
11214 </field>
11215 <field>
11216 <name>I2C1LPEN</name>
11217 <description>I2C1 clock enable during Sleep
11218 mode</description>
11219 <bitOffset>21</bitOffset>
11220 <bitWidth>1</bitWidth>
11221 </field>
11222 <field>
11223 <name>I2C2LPEN</name>
11224 <description>I2C2 clock enable during Sleep
11225 mode</description>
11226 <bitOffset>22</bitOffset>
11227 <bitWidth>1</bitWidth>
11228 </field>
11229 <field>
11230 <name>I2C3LPEN</name>
11231 <description>I2C3 clock enable during Sleep
11232 mode</description>
11233 <bitOffset>23</bitOffset>
11234 <bitWidth>1</bitWidth>
11235 </field>
11236 <field>
11237 <name>CAN1LPEN</name>
11238 <description>CAN 1 clock enable during Sleep
11239 mode</description>
11240 <bitOffset>25</bitOffset>
11241 <bitWidth>1</bitWidth>
11242 </field>
11243 <field>
11244 <name>CAN2LPEN</name>
11245 <description>CAN 2 clock enable during Sleep
11246 mode</description>
11247 <bitOffset>26</bitOffset>
11248 <bitWidth>1</bitWidth>
11249 </field>
11250 <field>
11251 <name>PWRLPEN</name>
11252 <description>Power interface clock enable during
11253 Sleep mode</description>
11254 <bitOffset>28</bitOffset>
11255 <bitWidth>1</bitWidth>
11256 </field>
11257 <field>
11258 <name>DACLPEN</name>
11259 <description>DAC interface clock enable during Sleep
11260 mode</description>
11261 <bitOffset>29</bitOffset>
11262 <bitWidth>1</bitWidth>
11263 </field>
11264 <field>
11265 <name>UART7LPEN</name>
11266 <description>UART7 clock enable during Sleep
11267 mode</description>
11268 <bitOffset>30</bitOffset>
11269 <bitWidth>1</bitWidth>
11270 </field>
11271 <field>
11272 <name>UART8LPEN</name>
11273 <description>UART8 clock enable during Sleep
11274 mode</description>
11275 <bitOffset>31</bitOffset>
11276 <bitWidth>1</bitWidth>
11277 </field>
11278 <field>
11279 <name>SPDIFRXLPEN</name>
11280 <description>SPDIF-RX clock enable during sleep
11281 mode</description>
11282 <bitOffset>16</bitOffset>
11283 <bitWidth>1</bitWidth>
11284 </field>
11285 <field>
11286 <name>CECLPEN</name>
11287 <description>HDMI-CEN clock enable during Sleep
11288 mode</description>
11289 <bitOffset>27</bitOffset>
11290 <bitWidth>1</bitWidth>
11291 </field>
11292 <field>
11293 <name>LPTIM1LPEN</name>
11294 <description>low power timer 1 clock enable during
11295 Sleep mode</description>
11296 <bitOffset>9</bitOffset>
11297 <bitWidth>1</bitWidth>
11298 </field>
11299 <field>
11300 <name>I2C4LPEN</name>
11301 <description>I2C4 clock enable during Sleep
11302 mode</description>
11303 <bitOffset>24</bitOffset>
11304 <bitWidth>1</bitWidth>
11305 </field>
11306 </fields>
11307 </register>
11308 <register>
11309 <name>APB2LPENR</name>
11310 <displayName>APB2LPENR</displayName>
11311 <description>APB2 peripheral clock enabled in low power
11312 mode register</description>
11313 <addressOffset>0x64</addressOffset>
11314 <size>0x20</size>
11315 <access>read-write</access>
11316 <resetValue>0x00075F33</resetValue>
11317 <fields>
11318 <field>
11319 <name>TIM1LPEN</name>
11320 <description>TIM1 clock enable during Sleep
11321 mode</description>
11322 <bitOffset>0</bitOffset>
11323 <bitWidth>1</bitWidth>
11324 </field>
11325 <field>
11326 <name>TIM8LPEN</name>
11327 <description>TIM8 clock enable during Sleep
11328 mode</description>
11329 <bitOffset>1</bitOffset>
11330 <bitWidth>1</bitWidth>
11331 </field>
11332 <field>
11333 <name>USART1LPEN</name>
11334 <description>USART1 clock enable during Sleep
11335 mode</description>
11336 <bitOffset>4</bitOffset>
11337 <bitWidth>1</bitWidth>
11338 </field>
11339 <field>
11340 <name>USART6LPEN</name>
11341 <description>USART6 clock enable during Sleep
11342 mode</description>
11343 <bitOffset>5</bitOffset>
11344 <bitWidth>1</bitWidth>
11345 </field>
11346 <field>
11347 <name>ADC1LPEN</name>
11348 <description>ADC1 clock enable during Sleep
11349 mode</description>
11350 <bitOffset>8</bitOffset>
11351 <bitWidth>1</bitWidth>
11352 </field>
11353 <field>
11354 <name>ADC2LPEN</name>
11355 <description>ADC2 clock enable during Sleep
11356 mode</description>
11357 <bitOffset>9</bitOffset>
11358 <bitWidth>1</bitWidth>
11359 </field>
11360 <field>
11361 <name>ADC3LPEN</name>
11362 <description>ADC 3 clock enable during Sleep
11363 mode</description>
11364 <bitOffset>10</bitOffset>
11365 <bitWidth>1</bitWidth>
11366 </field>
11367 <field>
11368 <name>SPI1LPEN</name>
11369 <description>SPI 1 clock enable during Sleep
11370 mode</description>
11371 <bitOffset>12</bitOffset>
11372 <bitWidth>1</bitWidth>
11373 </field>
11374 <field>
11375 <name>SPI4LPEN</name>
11376 <description>SPI 4 clock enable during Sleep
11377 mode</description>
11378 <bitOffset>13</bitOffset>
11379 <bitWidth>1</bitWidth>
11380 </field>
11381 <field>
11382 <name>SYSCFGLPEN</name>
11383 <description>System configuration controller clock
11384 enable during Sleep mode</description>
11385 <bitOffset>14</bitOffset>
11386 <bitWidth>1</bitWidth>
11387 </field>
11388 <field>
11389 <name>TIM9LPEN</name>
11390 <description>TIM9 clock enable during sleep
11391 mode</description>
11392 <bitOffset>16</bitOffset>
11393 <bitWidth>1</bitWidth>
11394 </field>
11395 <field>
11396 <name>TIM10LPEN</name>
11397 <description>TIM10 clock enable during Sleep
11398 mode</description>
11399 <bitOffset>17</bitOffset>
11400 <bitWidth>1</bitWidth>
11401 </field>
11402 <field>
11403 <name>TIM11LPEN</name>
11404 <description>TIM11 clock enable during Sleep
11405 mode</description>
11406 <bitOffset>18</bitOffset>
11407 <bitWidth>1</bitWidth>
11408 </field>
11409 <field>
11410 <name>SPI5LPEN</name>
11411 <description>SPI 5 clock enable during Sleep
11412 mode</description>
11413 <bitOffset>20</bitOffset>
11414 <bitWidth>1</bitWidth>
11415 </field>
11416 <field>
11417 <name>SPI6LPEN</name>
11418 <description>SPI 6 clock enable during Sleep
11419 mode</description>
11420 <bitOffset>21</bitOffset>
11421 <bitWidth>1</bitWidth>
11422 </field>
11423 <field>
11424 <name>SAI1LPEN</name>
11425 <description>SAI1 clock enable during sleep
11426 mode</description>
11427 <bitOffset>22</bitOffset>
11428 <bitWidth>1</bitWidth>
11429 </field>
11430 <field>
11431 <name>LTDCLPEN</name>
11432 <description>LTDC clock enable during sleep
11433 mode</description>
11434 <bitOffset>26</bitOffset>
11435 <bitWidth>1</bitWidth>
11436 </field>
11437 <field>
11438 <name>SAI2LPEN</name>
11439 <description>SAI2 clock enable during sleep
11440 mode</description>
11441 <bitOffset>23</bitOffset>
11442 <bitWidth>1</bitWidth>
11443 </field>
11444 <field>
11445 <name>SDMMC1LPEN</name>
11446 <description>SDMMC1 clock enable during Sleep
11447 mode</description>
11448 <bitOffset>11</bitOffset>
11449 <bitWidth>1</bitWidth>
11450 </field>
11451 </fields>
11452 </register>
11453 <register>
11454 <name>BDCR</name>
11455 <displayName>BDCR</displayName>
11456 <description>Backup domain control register</description>
11457 <addressOffset>0x70</addressOffset>
11458 <size>0x20</size>
11459 <resetValue>0x00000000</resetValue>
11460 <fields>
11461 <field>
11462 <name>BDRST</name>
11463 <description>Backup domain software
11464 reset</description>
11465 <bitOffset>16</bitOffset>
11466 <bitWidth>1</bitWidth>
11467 <access>read-write</access>
11468 </field>
11469 <field>
11470 <name>RTCEN</name>
11471 <description>RTC clock enable</description>
11472 <bitOffset>15</bitOffset>
11473 <bitWidth>1</bitWidth>
11474 <access>read-write</access>
11475 </field>
11476 <field>
11477 <name>RTCSEL1</name>
11478 <description>RTC clock source selection</description>
11479 <bitOffset>9</bitOffset>
11480 <bitWidth>1</bitWidth>
11481 <access>read-write</access>
11482 </field>
11483 <field>
11484 <name>RTCSEL0</name>
11485 <description>RTC clock source selection</description>
11486 <bitOffset>8</bitOffset>
11487 <bitWidth>1</bitWidth>
11488 <access>read-write</access>
11489 </field>
11490 <field>
11491 <name>LSEBYP</name>
11492 <description>External low-speed oscillator
11493 bypass</description>
11494 <bitOffset>2</bitOffset>
11495 <bitWidth>1</bitWidth>
11496 <access>read-write</access>
11497 </field>
11498 <field>
11499 <name>LSERDY</name>
11500 <description>External low-speed oscillator
11501 ready</description>
11502 <bitOffset>1</bitOffset>
11503 <bitWidth>1</bitWidth>
11504 <access>read-only</access>
11505 </field>
11506 <field>
11507 <name>LSEON</name>
11508 <description>External low-speed oscillator
11509 enable</description>
11510 <bitOffset>0</bitOffset>
11511 <bitWidth>1</bitWidth>
11512 <access>read-write</access>
11513 </field>
11514 </fields>
11515 </register>
11516 <register>
11517 <name>CSR</name>
11518 <displayName>CSR</displayName>
11519 <description>clock control &amp; status
11520 register</description>
11521 <addressOffset>0x74</addressOffset>
11522 <size>0x20</size>
11523 <resetValue>0x0E000000</resetValue>
11524 <fields>
11525 <field>
11526 <name>LPWRRSTF</name>
11527 <description>Low-power reset flag</description>
11528 <bitOffset>31</bitOffset>
11529 <bitWidth>1</bitWidth>
11530 <access>read-write</access>
11531 </field>
11532 <field>
11533 <name>WWDGRSTF</name>
11534 <description>Window watchdog reset flag</description>
11535 <bitOffset>30</bitOffset>
11536 <bitWidth>1</bitWidth>
11537 <access>read-write</access>
11538 </field>
11539 <field>
11540 <name>WDGRSTF</name>
11541 <description>Independent watchdog reset
11542 flag</description>
11543 <bitOffset>29</bitOffset>
11544 <bitWidth>1</bitWidth>
11545 <access>read-write</access>
11546 </field>
11547 <field>
11548 <name>SFTRSTF</name>
11549 <description>Software reset flag</description>
11550 <bitOffset>28</bitOffset>
11551 <bitWidth>1</bitWidth>
11552 <access>read-write</access>
11553 </field>
11554 <field>
11555 <name>PORRSTF</name>
11556 <description>POR/PDR reset flag</description>
11557 <bitOffset>27</bitOffset>
11558 <bitWidth>1</bitWidth>
11559 <access>read-write</access>
11560 </field>
11561 <field>
11562 <name>PADRSTF</name>
11563 <description>PIN reset flag</description>
11564 <bitOffset>26</bitOffset>
11565 <bitWidth>1</bitWidth>
11566 <access>read-write</access>
11567 </field>
11568 <field>
11569 <name>BORRSTF</name>
11570 <description>BOR reset flag</description>
11571 <bitOffset>25</bitOffset>
11572 <bitWidth>1</bitWidth>
11573 <access>read-write</access>
11574 </field>
11575 <field>
11576 <name>RMVF</name>
11577 <description>Remove reset flag</description>
11578 <bitOffset>24</bitOffset>
11579 <bitWidth>1</bitWidth>
11580 <access>read-write</access>
11581 </field>
11582 <field>
11583 <name>LSIRDY</name>
11584 <description>Internal low-speed oscillator
11585 ready</description>
11586 <bitOffset>1</bitOffset>
11587 <bitWidth>1</bitWidth>
11588 <access>read-only</access>
11589 </field>
11590 <field>
11591 <name>LSION</name>
11592 <description>Internal low-speed oscillator
11593 enable</description>
11594 <bitOffset>0</bitOffset>
11595 <bitWidth>1</bitWidth>
11596 <access>read-write</access>
11597 </field>
11598 </fields>
11599 </register>
11600 <register>
11601 <name>SSCGR</name>
11602 <displayName>SSCGR</displayName>
11603 <description>spread spectrum clock generation
11604 register</description>
11605 <addressOffset>0x80</addressOffset>
11606 <size>0x20</size>
11607 <access>read-write</access>
11608 <resetValue>0x00000000</resetValue>
11609 <fields>
11610 <field>
11611 <name>SSCGEN</name>
11612 <description>Spread spectrum modulation
11613 enable</description>
11614 <bitOffset>31</bitOffset>
11615 <bitWidth>1</bitWidth>
11616 </field>
11617 <field>
11618 <name>SPREADSEL</name>
11619 <description>Spread Select</description>
11620 <bitOffset>30</bitOffset>
11621 <bitWidth>1</bitWidth>
11622 </field>
11623 <field>
11624 <name>INCSTEP</name>
11625 <description>Incrementation step</description>
11626 <bitOffset>13</bitOffset>
11627 <bitWidth>15</bitWidth>
11628 </field>
11629 <field>
11630 <name>MODPER</name>
11631 <description>Modulation period</description>
11632 <bitOffset>0</bitOffset>
11633 <bitWidth>13</bitWidth>
11634 </field>
11635 </fields>
11636 </register>
11637 <register>
11638 <name>PLLI2SCFGR</name>
11639 <displayName>PLLI2SCFGR</displayName>
11640 <description>PLLI2S configuration register</description>
11641 <addressOffset>0x84</addressOffset>
11642 <size>0x20</size>
11643 <access>read-write</access>
11644 <resetValue>0x20003000</resetValue>
11645 <fields>
11646 <field>
11647 <name>PLLI2SR</name>
11648 <description>PLLI2S division factor for I2S
11649 clocks</description>
11650 <bitOffset>28</bitOffset>
11651 <bitWidth>3</bitWidth>
11652 </field>
11653 <field>
11654 <name>PLLI2SQ</name>
11655 <description>PLLI2S division factor for SAI1
11656 clock</description>
11657 <bitOffset>24</bitOffset>
11658 <bitWidth>4</bitWidth>
11659 </field>
11660 <field>
11661 <name>PLLI2SN</name>
11662 <description>PLLI2S multiplication factor for
11663 VCO</description>
11664 <bitOffset>6</bitOffset>
11665 <bitWidth>9</bitWidth>
11666 </field>
11667 </fields>
11668 </register>
11669 <register>
11670 <name>PLLSAICFGR</name>
11671 <displayName>PLLSAICFGR</displayName>
11672 <description>PLL configuration register</description>
11673 <addressOffset>0x88</addressOffset>
11674 <size>0x20</size>
11675 <access>read-write</access>
11676 <resetValue>0x20003000</resetValue>
11677 <fields>
11678 <field>
11679 <name>PLLSAIN</name>
11680 <description>PLLSAI division factor for
11681 VCO</description>
11682 <bitOffset>6</bitOffset>
11683 <bitWidth>9</bitWidth>
11684 </field>
11685 <field>
11686 <name>PLLSAIP</name>
11687 <description>PLLSAI division factor for 48MHz
11688 clock</description>
11689 <bitOffset>16</bitOffset>
11690 <bitWidth>2</bitWidth>
11691 </field>
11692 <field>
11693 <name>PLLSAIQ</name>
11694 <description>PLLSAI division factor for SAI
11695 clock</description>
11696 <bitOffset>24</bitOffset>
11697 <bitWidth>4</bitWidth>
11698 </field>
11699 <field>
11700 <name>PLLSAIR</name>
11701 <description>PLLSAI division factor for LCD
11702 clock</description>
11703 <bitOffset>28</bitOffset>
11704 <bitWidth>3</bitWidth>
11705 </field>
11706 </fields>
11707 </register>
11708 <register>
11709 <name>DKCFGR1</name>
11710 <displayName>DKCFGR1</displayName>
11711 <description>dedicated clocks configuration
11712 register</description>
11713 <addressOffset>0x8C</addressOffset>
11714 <size>0x20</size>
11715 <access>read-write</access>
11716 <resetValue>0x20003000</resetValue>
11717 <fields>
11718 <field>
11719 <name>PLLI2SDIV</name>
11720 <description>PLLI2S division factor for SAI1
11721 clock</description>
11722 <bitOffset>0</bitOffset>
11723 <bitWidth>5</bitWidth>
11724 </field>
11725 <field>
11726 <name>PLLSAIDIVQ</name>
11727 <description>PLLSAI division factor for SAI1
11728 clock</description>
11729 <bitOffset>8</bitOffset>
11730 <bitWidth>5</bitWidth>
11731 </field>
11732 <field>
11733 <name>PLLSAIDIVR</name>
11734 <description>division factor for
11735 LCD_CLK</description>
11736 <bitOffset>16</bitOffset>
11737 <bitWidth>2</bitWidth>
11738 </field>
11739 <field>
11740 <name>SAI1SEL</name>
11741 <description>SAI1 clock source
11742 selection</description>
11743 <bitOffset>20</bitOffset>
11744 <bitWidth>2</bitWidth>
11745 </field>
11746 <field>
11747 <name>SAI2SEL</name>
11748 <description>SAI2 clock source
11749 selection</description>
11750 <bitOffset>22</bitOffset>
11751 <bitWidth>2</bitWidth>
11752 </field>
11753 <field>
11754 <name>TIMPRE</name>
11755 <description>Timers clocks prescalers
11756 selection</description>
11757 <bitOffset>24</bitOffset>
11758 <bitWidth>1</bitWidth>
11759 </field>
11760 </fields>
11761 </register>
11762 <register>
11763 <name>DKCFGR2</name>
11764 <displayName>DKCFGR2</displayName>
11765 <description>dedicated clocks configuration
11766 register</description>
11767 <addressOffset>0x90</addressOffset>
11768 <size>0x20</size>
11769 <access>read-write</access>
11770 <resetValue>0x20003000</resetValue>
11771 <fields>
11772 <field>
11773 <name>USART1SEL</name>
11774 <description>USART 1 clock source
11775 selection</description>
11776 <bitOffset>0</bitOffset>
11777 <bitWidth>2</bitWidth>
11778 </field>
11779 <field>
11780 <name>USART2SEL</name>
11781 <description>USART 2 clock source
11782 selection</description>
11783 <bitOffset>2</bitOffset>
11784 <bitWidth>2</bitWidth>
11785 </field>
11786 <field>
11787 <name>USART3SEL</name>
11788 <description>USART 3 clock source
11789 selection</description>
11790 <bitOffset>4</bitOffset>
11791 <bitWidth>2</bitWidth>
11792 </field>
11793 <field>
11794 <name>UART4SEL</name>
11795 <description>UART 4 clock source
11796 selection</description>
11797 <bitOffset>6</bitOffset>
11798 <bitWidth>2</bitWidth>
11799 </field>
11800 <field>
11801 <name>UART5SEL</name>
11802 <description>UART 5 clock source
11803 selection</description>
11804 <bitOffset>8</bitOffset>
11805 <bitWidth>2</bitWidth>
11806 </field>
11807 <field>
11808 <name>USART6SEL</name>
11809 <description>USART 6 clock source
11810 selection</description>
11811 <bitOffset>10</bitOffset>
11812 <bitWidth>2</bitWidth>
11813 </field>
11814 <field>
11815 <name>UART7SEL</name>
11816 <description>UART 7 clock source
11817 selection</description>
11818 <bitOffset>12</bitOffset>
11819 <bitWidth>2</bitWidth>
11820 </field>
11821 <field>
11822 <name>UART8SEL</name>
11823 <description>UART 8 clock source
11824 selection</description>
11825 <bitOffset>14</bitOffset>
11826 <bitWidth>2</bitWidth>
11827 </field>
11828 <field>
11829 <name>I2C1SEL</name>
11830 <description>I2C1 clock source
11831 selection</description>
11832 <bitOffset>16</bitOffset>
11833 <bitWidth>2</bitWidth>
11834 </field>
11835 <field>
11836 <name>I2C2SEL</name>
11837 <description>I2C2 clock source
11838 selection</description>
11839 <bitOffset>18</bitOffset>
11840 <bitWidth>2</bitWidth>
11841 </field>
11842 <field>
11843 <name>I2C3SEL</name>
11844 <description>I2C3 clock source
11845 selection</description>
11846 <bitOffset>20</bitOffset>
11847 <bitWidth>2</bitWidth>
11848 </field>
11849 <field>
11850 <name>I2C4SEL</name>
11851 <description>I2C4 clock source
11852 selection</description>
11853 <bitOffset>22</bitOffset>
11854 <bitWidth>2</bitWidth>
11855 </field>
11856 <field>
11857 <name>LPTIM1SEL</name>
11858 <description>Low power timer 1 clock source
11859 selection</description>
11860 <bitOffset>24</bitOffset>
11861 <bitWidth>2</bitWidth>
11862 </field>
11863 <field>
11864 <name>CECSEL</name>
11865 <description>HDMI-CEC clock source
11866 selection</description>
11867 <bitOffset>26</bitOffset>
11868 <bitWidth>1</bitWidth>
11869 </field>
11870 <field>
11871 <name>CK48MSEL</name>
11872 <description>48MHz clock source
11873 selection</description>
11874 <bitOffset>27</bitOffset>
11875 <bitWidth>1</bitWidth>
11876 </field>
11877 <field>
11878 <name>SDMMCSEL</name>
11879 <description>SDMMC clock source
11880 selection</description>
11881 <bitOffset>28</bitOffset>
11882 <bitWidth>1</bitWidth>
11883 </field>
11884 </fields>
11885 </register>
11886 </registers>
11887 </peripheral>
11888 <peripheral>
11889 <name>GPIOD</name>
11890 <description>General-purpose I/Os</description>
11891 <groupName>GPIO</groupName>
11892 <baseAddress>0X40020C00</baseAddress>
11893 <addressBlock>
11894 <offset>0x0</offset>
11895 <size>0x400</size>
11896 <usage>registers</usage>
11897 </addressBlock>
11898 <registers>
11899 <register>
11900 <name>MODER</name>
11901 <displayName>MODER</displayName>
11902 <description>GPIO port mode register</description>
11903 <addressOffset>0x0</addressOffset>
11904 <size>0x20</size>
11905 <access>read-write</access>
11906 <resetValue>0x00000000</resetValue>
11907 <fields>
11908 <field>
11909 <name>MODER15</name>
11910 <description>Port x configuration bits (y =
11911 0..15)</description>
11912 <bitOffset>30</bitOffset>
11913 <bitWidth>2</bitWidth>
11914 </field>
11915 <field>
11916 <name>MODER14</name>
11917 <description>Port x configuration bits (y =
11918 0..15)</description>
11919 <bitOffset>28</bitOffset>
11920 <bitWidth>2</bitWidth>
11921 </field>
11922 <field>
11923 <name>MODER13</name>
11924 <description>Port x configuration bits (y =
11925 0..15)</description>
11926 <bitOffset>26</bitOffset>
11927 <bitWidth>2</bitWidth>
11928 </field>
11929 <field>
11930 <name>MODER12</name>
11931 <description>Port x configuration bits (y =
11932 0..15)</description>
11933 <bitOffset>24</bitOffset>
11934 <bitWidth>2</bitWidth>
11935 </field>
11936 <field>
11937 <name>MODER11</name>
11938 <description>Port x configuration bits (y =
11939 0..15)</description>
11940 <bitOffset>22</bitOffset>
11941 <bitWidth>2</bitWidth>
11942 </field>
11943 <field>
11944 <name>MODER10</name>
11945 <description>Port x configuration bits (y =
11946 0..15)</description>
11947 <bitOffset>20</bitOffset>
11948 <bitWidth>2</bitWidth>
11949 </field>
11950 <field>
11951 <name>MODER9</name>
11952 <description>Port x configuration bits (y =
11953 0..15)</description>
11954 <bitOffset>18</bitOffset>
11955 <bitWidth>2</bitWidth>
11956 </field>
11957 <field>
11958 <name>MODER8</name>
11959 <description>Port x configuration bits (y =
11960 0..15)</description>
11961 <bitOffset>16</bitOffset>
11962 <bitWidth>2</bitWidth>
11963 </field>
11964 <field>
11965 <name>MODER7</name>
11966 <description>Port x configuration bits (y =
11967 0..15)</description>
11968 <bitOffset>14</bitOffset>
11969 <bitWidth>2</bitWidth>
11970 </field>
11971 <field>
11972 <name>MODER6</name>
11973 <description>Port x configuration bits (y =
11974 0..15)</description>
11975 <bitOffset>12</bitOffset>
11976 <bitWidth>2</bitWidth>
11977 </field>
11978 <field>
11979 <name>MODER5</name>
11980 <description>Port x configuration bits (y =
11981 0..15)</description>
11982 <bitOffset>10</bitOffset>
11983 <bitWidth>2</bitWidth>
11984 </field>
11985 <field>
11986 <name>MODER4</name>
11987 <description>Port x configuration bits (y =
11988 0..15)</description>
11989 <bitOffset>8</bitOffset>
11990 <bitWidth>2</bitWidth>
11991 </field>
11992 <field>
11993 <name>MODER3</name>
11994 <description>Port x configuration bits (y =
11995 0..15)</description>
11996 <bitOffset>6</bitOffset>
11997 <bitWidth>2</bitWidth>
11998 </field>
11999 <field>
12000 <name>MODER2</name>
12001 <description>Port x configuration bits (y =
12002 0..15)</description>
12003 <bitOffset>4</bitOffset>
12004 <bitWidth>2</bitWidth>
12005 </field>
12006 <field>
12007 <name>MODER1</name>
12008 <description>Port x configuration bits (y =
12009 0..15)</description>
12010 <bitOffset>2</bitOffset>
12011 <bitWidth>2</bitWidth>
12012 </field>
12013 <field>
12014 <name>MODER0</name>
12015 <description>Port x configuration bits (y =
12016 0..15)</description>
12017 <bitOffset>0</bitOffset>
12018 <bitWidth>2</bitWidth>
12019 </field>
12020 </fields>
12021 </register>
12022 <register>
12023 <name>OTYPER</name>
12024 <displayName>OTYPER</displayName>
12025 <description>GPIO port output type register</description>
12026 <addressOffset>0x4</addressOffset>
12027 <size>0x20</size>
12028 <access>read-write</access>
12029 <resetValue>0x00000000</resetValue>
12030 <fields>
12031 <field>
12032 <name>OT15</name>
12033 <description>Port x configuration bits (y =
12034 0..15)</description>
12035 <bitOffset>15</bitOffset>
12036 <bitWidth>1</bitWidth>
12037 </field>
12038 <field>
12039 <name>OT14</name>
12040 <description>Port x configuration bits (y =
12041 0..15)</description>
12042 <bitOffset>14</bitOffset>
12043 <bitWidth>1</bitWidth>
12044 </field>
12045 <field>
12046 <name>OT13</name>
12047 <description>Port x configuration bits (y =
12048 0..15)</description>
12049 <bitOffset>13</bitOffset>
12050 <bitWidth>1</bitWidth>
12051 </field>
12052 <field>
12053 <name>OT12</name>
12054 <description>Port x configuration bits (y =
12055 0..15)</description>
12056 <bitOffset>12</bitOffset>
12057 <bitWidth>1</bitWidth>
12058 </field>
12059 <field>
12060 <name>OT11</name>
12061 <description>Port x configuration bits (y =
12062 0..15)</description>
12063 <bitOffset>11</bitOffset>
12064 <bitWidth>1</bitWidth>
12065 </field>
12066 <field>
12067 <name>OT10</name>
12068 <description>Port x configuration bits (y =
12069 0..15)</description>
12070 <bitOffset>10</bitOffset>
12071 <bitWidth>1</bitWidth>
12072 </field>
12073 <field>
12074 <name>OT9</name>
12075 <description>Port x configuration bits (y =
12076 0..15)</description>
12077 <bitOffset>9</bitOffset>
12078 <bitWidth>1</bitWidth>
12079 </field>
12080 <field>
12081 <name>OT8</name>
12082 <description>Port x configuration bits (y =
12083 0..15)</description>
12084 <bitOffset>8</bitOffset>
12085 <bitWidth>1</bitWidth>
12086 </field>
12087 <field>
12088 <name>OT7</name>
12089 <description>Port x configuration bits (y =
12090 0..15)</description>
12091 <bitOffset>7</bitOffset>
12092 <bitWidth>1</bitWidth>
12093 </field>
12094 <field>
12095 <name>OT6</name>
12096 <description>Port x configuration bits (y =
12097 0..15)</description>
12098 <bitOffset>6</bitOffset>
12099 <bitWidth>1</bitWidth>
12100 </field>
12101 <field>
12102 <name>OT5</name>
12103 <description>Port x configuration bits (y =
12104 0..15)</description>
12105 <bitOffset>5</bitOffset>
12106 <bitWidth>1</bitWidth>
12107 </field>
12108 <field>
12109 <name>OT4</name>
12110 <description>Port x configuration bits (y =
12111 0..15)</description>
12112 <bitOffset>4</bitOffset>
12113 <bitWidth>1</bitWidth>
12114 </field>
12115 <field>
12116 <name>OT3</name>
12117 <description>Port x configuration bits (y =
12118 0..15)</description>
12119 <bitOffset>3</bitOffset>
12120 <bitWidth>1</bitWidth>
12121 </field>
12122 <field>
12123 <name>OT2</name>
12124 <description>Port x configuration bits (y =
12125 0..15)</description>
12126 <bitOffset>2</bitOffset>
12127 <bitWidth>1</bitWidth>
12128 </field>
12129 <field>
12130 <name>OT1</name>
12131 <description>Port x configuration bits (y =
12132 0..15)</description>
12133 <bitOffset>1</bitOffset>
12134 <bitWidth>1</bitWidth>
12135 </field>
12136 <field>
12137 <name>OT0</name>
12138 <description>Port x configuration bits (y =
12139 0..15)</description>
12140 <bitOffset>0</bitOffset>
12141 <bitWidth>1</bitWidth>
12142 </field>
12143 </fields>
12144 </register>
12145 <register>
12146 <name>GPIOB_OSPEEDR</name>
12147 <displayName>GPIOB_OSPEEDR</displayName>
12148 <description>GPIO port output speed
12149 register</description>
12150 <addressOffset>0x8</addressOffset>
12151 <size>0x20</size>
12152 <access>read-write</access>
12153 <resetValue>0x00000000</resetValue>
12154 <fields>
12155 <field>
12156 <name>OSPEEDR15</name>
12157 <description>Port x configuration bits (y =
12158 0..15)</description>
12159 <bitOffset>30</bitOffset>
12160 <bitWidth>2</bitWidth>
12161 </field>
12162 <field>
12163 <name>OSPEEDR14</name>
12164 <description>Port x configuration bits (y =
12165 0..15)</description>
12166 <bitOffset>28</bitOffset>
12167 <bitWidth>2</bitWidth>
12168 </field>
12169 <field>
12170 <name>OSPEEDR13</name>
12171 <description>Port x configuration bits (y =
12172 0..15)</description>
12173 <bitOffset>26</bitOffset>
12174 <bitWidth>2</bitWidth>
12175 </field>
12176 <field>
12177 <name>OSPEEDR12</name>
12178 <description>Port x configuration bits (y =
12179 0..15)</description>
12180 <bitOffset>24</bitOffset>
12181 <bitWidth>2</bitWidth>
12182 </field>
12183 <field>
12184 <name>OSPEEDR11</name>
12185 <description>Port x configuration bits (y =
12186 0..15)</description>
12187 <bitOffset>22</bitOffset>
12188 <bitWidth>2</bitWidth>
12189 </field>
12190 <field>
12191 <name>OSPEEDR10</name>
12192 <description>Port x configuration bits (y =
12193 0..15)</description>
12194 <bitOffset>20</bitOffset>
12195 <bitWidth>2</bitWidth>
12196 </field>
12197 <field>
12198 <name>OSPEEDR9</name>
12199 <description>Port x configuration bits (y =
12200 0..15)</description>
12201 <bitOffset>18</bitOffset>
12202 <bitWidth>2</bitWidth>
12203 </field>
12204 <field>
12205 <name>OSPEEDR8</name>
12206 <description>Port x configuration bits (y =
12207 0..15)</description>
12208 <bitOffset>16</bitOffset>
12209 <bitWidth>2</bitWidth>
12210 </field>
12211 <field>
12212 <name>OSPEEDR7</name>
12213 <description>Port x configuration bits (y =
12214 0..15)</description>
12215 <bitOffset>14</bitOffset>
12216 <bitWidth>2</bitWidth>
12217 </field>
12218 <field>
12219 <name>OSPEEDR6</name>
12220 <description>Port x configuration bits (y =
12221 0..15)</description>
12222 <bitOffset>12</bitOffset>
12223 <bitWidth>2</bitWidth>
12224 </field>
12225 <field>
12226 <name>OSPEEDR5</name>
12227 <description>Port x configuration bits (y =
12228 0..15)</description>
12229 <bitOffset>10</bitOffset>
12230 <bitWidth>2</bitWidth>
12231 </field>
12232 <field>
12233 <name>OSPEEDR4</name>
12234 <description>Port x configuration bits (y =
12235 0..15)</description>
12236 <bitOffset>8</bitOffset>
12237 <bitWidth>2</bitWidth>
12238 </field>
12239 <field>
12240 <name>OSPEEDR3</name>
12241 <description>Port x configuration bits (y =
12242 0..15)</description>
12243 <bitOffset>6</bitOffset>
12244 <bitWidth>2</bitWidth>
12245 </field>
12246 <field>
12247 <name>OSPEEDR2</name>
12248 <description>Port x configuration bits (y =
12249 0..15)</description>
12250 <bitOffset>4</bitOffset>
12251 <bitWidth>2</bitWidth>
12252 </field>
12253 <field>
12254 <name>OSPEEDR1</name>
12255 <description>Port x configuration bits (y =
12256 0..15)</description>
12257 <bitOffset>2</bitOffset>
12258 <bitWidth>2</bitWidth>
12259 </field>
12260 <field>
12261 <name>OSPEEDR0</name>
12262 <description>Port x configuration bits (y =
12263 0..15)</description>
12264 <bitOffset>0</bitOffset>
12265 <bitWidth>2</bitWidth>
12266 </field>
12267 </fields>
12268 </register>
12269 <register>
12270 <name>PUPDR</name>
12271 <displayName>PUPDR</displayName>
12272 <description>GPIO port pull-up/pull-down
12273 register</description>
12274 <addressOffset>0xC</addressOffset>
12275 <size>0x20</size>
12276 <access>read-write</access>
12277 <resetValue>0x00000000</resetValue>
12278 <fields>
12279 <field>
12280 <name>PUPDR15</name>
12281 <description>Port x configuration bits (y =
12282 0..15)</description>
12283 <bitOffset>30</bitOffset>
12284 <bitWidth>2</bitWidth>
12285 </field>
12286 <field>
12287 <name>PUPDR14</name>
12288 <description>Port x configuration bits (y =
12289 0..15)</description>
12290 <bitOffset>28</bitOffset>
12291 <bitWidth>2</bitWidth>
12292 </field>
12293 <field>
12294 <name>PUPDR13</name>
12295 <description>Port x configuration bits (y =
12296 0..15)</description>
12297 <bitOffset>26</bitOffset>
12298 <bitWidth>2</bitWidth>
12299 </field>
12300 <field>
12301 <name>PUPDR12</name>
12302 <description>Port x configuration bits (y =
12303 0..15)</description>
12304 <bitOffset>24</bitOffset>
12305 <bitWidth>2</bitWidth>
12306 </field>
12307 <field>
12308 <name>PUPDR11</name>
12309 <description>Port x configuration bits (y =
12310 0..15)</description>
12311 <bitOffset>22</bitOffset>
12312 <bitWidth>2</bitWidth>
12313 </field>
12314 <field>
12315 <name>PUPDR10</name>
12316 <description>Port x configuration bits (y =
12317 0..15)</description>
12318 <bitOffset>20</bitOffset>
12319 <bitWidth>2</bitWidth>
12320 </field>
12321 <field>
12322 <name>PUPDR9</name>
12323 <description>Port x configuration bits (y =
12324 0..15)</description>
12325 <bitOffset>18</bitOffset>
12326 <bitWidth>2</bitWidth>
12327 </field>
12328 <field>
12329 <name>PUPDR8</name>
12330 <description>Port x configuration bits (y =
12331 0..15)</description>
12332 <bitOffset>16</bitOffset>
12333 <bitWidth>2</bitWidth>
12334 </field>
12335 <field>
12336 <name>PUPDR7</name>
12337 <description>Port x configuration bits (y =
12338 0..15)</description>
12339 <bitOffset>14</bitOffset>
12340 <bitWidth>2</bitWidth>
12341 </field>
12342 <field>
12343 <name>PUPDR6</name>
12344 <description>Port x configuration bits (y =
12345 0..15)</description>
12346 <bitOffset>12</bitOffset>
12347 <bitWidth>2</bitWidth>
12348 </field>
12349 <field>
12350 <name>PUPDR5</name>
12351 <description>Port x configuration bits (y =
12352 0..15)</description>
12353 <bitOffset>10</bitOffset>
12354 <bitWidth>2</bitWidth>
12355 </field>
12356 <field>
12357 <name>PUPDR4</name>
12358 <description>Port x configuration bits (y =
12359 0..15)</description>
12360 <bitOffset>8</bitOffset>
12361 <bitWidth>2</bitWidth>
12362 </field>
12363 <field>
12364 <name>PUPDR3</name>
12365 <description>Port x configuration bits (y =
12366 0..15)</description>
12367 <bitOffset>6</bitOffset>
12368 <bitWidth>2</bitWidth>
12369 </field>
12370 <field>
12371 <name>PUPDR2</name>
12372 <description>Port x configuration bits (y =
12373 0..15)</description>
12374 <bitOffset>4</bitOffset>
12375 <bitWidth>2</bitWidth>
12376 </field>
12377 <field>
12378 <name>PUPDR1</name>
12379 <description>Port x configuration bits (y =
12380 0..15)</description>
12381 <bitOffset>2</bitOffset>
12382 <bitWidth>2</bitWidth>
12383 </field>
12384 <field>
12385 <name>PUPDR0</name>
12386 <description>Port x configuration bits (y =
12387 0..15)</description>
12388 <bitOffset>0</bitOffset>
12389 <bitWidth>2</bitWidth>
12390 </field>
12391 </fields>
12392 </register>
12393 <register>
12394 <name>IDR</name>
12395 <displayName>IDR</displayName>
12396 <description>GPIO port input data register</description>
12397 <addressOffset>0x10</addressOffset>
12398 <size>0x20</size>
12399 <access>read-only</access>
12400 <resetValue>0x00000000</resetValue>
12401 <fields>
12402 <field>
12403 <name>IDR15</name>
12404 <description>Port input data (y =
12405 0..15)</description>
12406 <bitOffset>15</bitOffset>
12407 <bitWidth>1</bitWidth>
12408 </field>
12409 <field>
12410 <name>IDR14</name>
12411 <description>Port input data (y =
12412 0..15)</description>
12413 <bitOffset>14</bitOffset>
12414 <bitWidth>1</bitWidth>
12415 </field>
12416 <field>
12417 <name>IDR13</name>
12418 <description>Port input data (y =
12419 0..15)</description>
12420 <bitOffset>13</bitOffset>
12421 <bitWidth>1</bitWidth>
12422 </field>
12423 <field>
12424 <name>IDR12</name>
12425 <description>Port input data (y =
12426 0..15)</description>
12427 <bitOffset>12</bitOffset>
12428 <bitWidth>1</bitWidth>
12429 </field>
12430 <field>
12431 <name>IDR11</name>
12432 <description>Port input data (y =
12433 0..15)</description>
12434 <bitOffset>11</bitOffset>
12435 <bitWidth>1</bitWidth>
12436 </field>
12437 <field>
12438 <name>IDR10</name>
12439 <description>Port input data (y =
12440 0..15)</description>
12441 <bitOffset>10</bitOffset>
12442 <bitWidth>1</bitWidth>
12443 </field>
12444 <field>
12445 <name>IDR9</name>
12446 <description>Port input data (y =
12447 0..15)</description>
12448 <bitOffset>9</bitOffset>
12449 <bitWidth>1</bitWidth>
12450 </field>
12451 <field>
12452 <name>IDR8</name>
12453 <description>Port input data (y =
12454 0..15)</description>
12455 <bitOffset>8</bitOffset>
12456 <bitWidth>1</bitWidth>
12457 </field>
12458 <field>
12459 <name>IDR7</name>
12460 <description>Port input data (y =
12461 0..15)</description>
12462 <bitOffset>7</bitOffset>
12463 <bitWidth>1</bitWidth>
12464 </field>
12465 <field>
12466 <name>IDR6</name>
12467 <description>Port input data (y =
12468 0..15)</description>
12469 <bitOffset>6</bitOffset>
12470 <bitWidth>1</bitWidth>
12471 </field>
12472 <field>
12473 <name>IDR5</name>
12474 <description>Port input data (y =
12475 0..15)</description>
12476 <bitOffset>5</bitOffset>
12477 <bitWidth>1</bitWidth>
12478 </field>
12479 <field>
12480 <name>IDR4</name>
12481 <description>Port input data (y =
12482 0..15)</description>
12483 <bitOffset>4</bitOffset>
12484 <bitWidth>1</bitWidth>
12485 </field>
12486 <field>
12487 <name>IDR3</name>
12488 <description>Port input data (y =
12489 0..15)</description>
12490 <bitOffset>3</bitOffset>
12491 <bitWidth>1</bitWidth>
12492 </field>
12493 <field>
12494 <name>IDR2</name>
12495 <description>Port input data (y =
12496 0..15)</description>
12497 <bitOffset>2</bitOffset>
12498 <bitWidth>1</bitWidth>
12499 </field>
12500 <field>
12501 <name>IDR1</name>
12502 <description>Port input data (y =
12503 0..15)</description>
12504 <bitOffset>1</bitOffset>
12505 <bitWidth>1</bitWidth>
12506 </field>
12507 <field>
12508 <name>IDR0</name>
12509 <description>Port input data (y =
12510 0..15)</description>
12511 <bitOffset>0</bitOffset>
12512 <bitWidth>1</bitWidth>
12513 </field>
12514 </fields>
12515 </register>
12516 <register>
12517 <name>ODR</name>
12518 <displayName>ODR</displayName>
12519 <description>GPIO port output data register</description>
12520 <addressOffset>0x14</addressOffset>
12521 <size>0x20</size>
12522 <access>read-write</access>
12523 <resetValue>0x00000000</resetValue>
12524 <fields>
12525 <field>
12526 <name>ODR15</name>
12527 <description>Port output data (y =
12528 0..15)</description>
12529 <bitOffset>15</bitOffset>
12530 <bitWidth>1</bitWidth>
12531 </field>
12532 <field>
12533 <name>ODR14</name>
12534 <description>Port output data (y =
12535 0..15)</description>
12536 <bitOffset>14</bitOffset>
12537 <bitWidth>1</bitWidth>
12538 </field>
12539 <field>
12540 <name>ODR13</name>
12541 <description>Port output data (y =
12542 0..15)</description>
12543 <bitOffset>13</bitOffset>
12544 <bitWidth>1</bitWidth>
12545 </field>
12546 <field>
12547 <name>ODR12</name>
12548 <description>Port output data (y =
12549 0..15)</description>
12550 <bitOffset>12</bitOffset>
12551 <bitWidth>1</bitWidth>
12552 </field>
12553 <field>
12554 <name>ODR11</name>
12555 <description>Port output data (y =
12556 0..15)</description>
12557 <bitOffset>11</bitOffset>
12558 <bitWidth>1</bitWidth>
12559 </field>
12560 <field>
12561 <name>ODR10</name>
12562 <description>Port output data (y =
12563 0..15)</description>
12564 <bitOffset>10</bitOffset>
12565 <bitWidth>1</bitWidth>
12566 </field>
12567 <field>
12568 <name>ODR9</name>
12569 <description>Port output data (y =
12570 0..15)</description>
12571 <bitOffset>9</bitOffset>
12572 <bitWidth>1</bitWidth>
12573 </field>
12574 <field>
12575 <name>ODR8</name>
12576 <description>Port output data (y =
12577 0..15)</description>
12578 <bitOffset>8</bitOffset>
12579 <bitWidth>1</bitWidth>
12580 </field>
12581 <field>
12582 <name>ODR7</name>
12583 <description>Port output data (y =
12584 0..15)</description>
12585 <bitOffset>7</bitOffset>
12586 <bitWidth>1</bitWidth>
12587 </field>
12588 <field>
12589 <name>ODR6</name>
12590 <description>Port output data (y =
12591 0..15)</description>
12592 <bitOffset>6</bitOffset>
12593 <bitWidth>1</bitWidth>
12594 </field>
12595 <field>
12596 <name>ODR5</name>
12597 <description>Port output data (y =
12598 0..15)</description>
12599 <bitOffset>5</bitOffset>
12600 <bitWidth>1</bitWidth>
12601 </field>
12602 <field>
12603 <name>ODR4</name>
12604 <description>Port output data (y =
12605 0..15)</description>
12606 <bitOffset>4</bitOffset>
12607 <bitWidth>1</bitWidth>
12608 </field>
12609 <field>
12610 <name>ODR3</name>
12611 <description>Port output data (y =
12612 0..15)</description>
12613 <bitOffset>3</bitOffset>
12614 <bitWidth>1</bitWidth>
12615 </field>
12616 <field>
12617 <name>ODR2</name>
12618 <description>Port output data (y =
12619 0..15)</description>
12620 <bitOffset>2</bitOffset>
12621 <bitWidth>1</bitWidth>
12622 </field>
12623 <field>
12624 <name>ODR1</name>
12625 <description>Port output data (y =
12626 0..15)</description>
12627 <bitOffset>1</bitOffset>
12628 <bitWidth>1</bitWidth>
12629 </field>
12630 <field>
12631 <name>ODR0</name>
12632 <description>Port output data (y =
12633 0..15)</description>
12634 <bitOffset>0</bitOffset>
12635 <bitWidth>1</bitWidth>
12636 </field>
12637 </fields>
12638 </register>
12639 <register>
12640 <name>BSRR</name>
12641 <displayName>BSRR</displayName>
12642 <description>GPIO port bit set/reset
12643 register</description>
12644 <addressOffset>0x18</addressOffset>
12645 <size>0x20</size>
12646 <access>write-only</access>
12647 <resetValue>0x00000000</resetValue>
12648 <fields>
12649 <field>
12650 <name>BR15</name>
12651 <description>Port x reset bit y (y =
12652 0..15)</description>
12653 <bitOffset>31</bitOffset>
12654 <bitWidth>1</bitWidth>
12655 </field>
12656 <field>
12657 <name>BR14</name>
12658 <description>Port x reset bit y (y =
12659 0..15)</description>
12660 <bitOffset>30</bitOffset>
12661 <bitWidth>1</bitWidth>
12662 </field>
12663 <field>
12664 <name>BR13</name>
12665 <description>Port x reset bit y (y =
12666 0..15)</description>
12667 <bitOffset>29</bitOffset>
12668 <bitWidth>1</bitWidth>
12669 </field>
12670 <field>
12671 <name>BR12</name>
12672 <description>Port x reset bit y (y =
12673 0..15)</description>
12674 <bitOffset>28</bitOffset>
12675 <bitWidth>1</bitWidth>
12676 </field>
12677 <field>
12678 <name>BR11</name>
12679 <description>Port x reset bit y (y =
12680 0..15)</description>
12681 <bitOffset>27</bitOffset>
12682 <bitWidth>1</bitWidth>
12683 </field>
12684 <field>
12685 <name>BR10</name>
12686 <description>Port x reset bit y (y =
12687 0..15)</description>
12688 <bitOffset>26</bitOffset>
12689 <bitWidth>1</bitWidth>
12690 </field>
12691 <field>
12692 <name>BR9</name>
12693 <description>Port x reset bit y (y =
12694 0..15)</description>
12695 <bitOffset>25</bitOffset>
12696 <bitWidth>1</bitWidth>
12697 </field>
12698 <field>
12699 <name>BR8</name>
12700 <description>Port x reset bit y (y =
12701 0..15)</description>
12702 <bitOffset>24</bitOffset>
12703 <bitWidth>1</bitWidth>
12704 </field>
12705 <field>
12706 <name>BR7</name>
12707 <description>Port x reset bit y (y =
12708 0..15)</description>
12709 <bitOffset>23</bitOffset>
12710 <bitWidth>1</bitWidth>
12711 </field>
12712 <field>
12713 <name>BR6</name>
12714 <description>Port x reset bit y (y =
12715 0..15)</description>
12716 <bitOffset>22</bitOffset>
12717 <bitWidth>1</bitWidth>
12718 </field>
12719 <field>
12720 <name>BR5</name>
12721 <description>Port x reset bit y (y =
12722 0..15)</description>
12723 <bitOffset>21</bitOffset>
12724 <bitWidth>1</bitWidth>
12725 </field>
12726 <field>
12727 <name>BR4</name>
12728 <description>Port x reset bit y (y =
12729 0..15)</description>
12730 <bitOffset>20</bitOffset>
12731 <bitWidth>1</bitWidth>
12732 </field>
12733 <field>
12734 <name>BR3</name>
12735 <description>Port x reset bit y (y =
12736 0..15)</description>
12737 <bitOffset>19</bitOffset>
12738 <bitWidth>1</bitWidth>
12739 </field>
12740 <field>
12741 <name>BR2</name>
12742 <description>Port x reset bit y (y =
12743 0..15)</description>
12744 <bitOffset>18</bitOffset>
12745 <bitWidth>1</bitWidth>
12746 </field>
12747 <field>
12748 <name>BR1</name>
12749 <description>Port x reset bit y (y =
12750 0..15)</description>
12751 <bitOffset>17</bitOffset>
12752 <bitWidth>1</bitWidth>
12753 </field>
12754 <field>
12755 <name>BR0</name>
12756 <description>Port x set bit y (y=
12757 0..15)</description>
12758 <bitOffset>16</bitOffset>
12759 <bitWidth>1</bitWidth>
12760 </field>
12761 <field>
12762 <name>BS15</name>
12763 <description>Port x set bit y (y=
12764 0..15)</description>
12765 <bitOffset>15</bitOffset>
12766 <bitWidth>1</bitWidth>
12767 </field>
12768 <field>
12769 <name>BS14</name>
12770 <description>Port x set bit y (y=
12771 0..15)</description>
12772 <bitOffset>14</bitOffset>
12773 <bitWidth>1</bitWidth>
12774 </field>
12775 <field>
12776 <name>BS13</name>
12777 <description>Port x set bit y (y=
12778 0..15)</description>
12779 <bitOffset>13</bitOffset>
12780 <bitWidth>1</bitWidth>
12781 </field>
12782 <field>
12783 <name>BS12</name>
12784 <description>Port x set bit y (y=
12785 0..15)</description>
12786 <bitOffset>12</bitOffset>
12787 <bitWidth>1</bitWidth>
12788 </field>
12789 <field>
12790 <name>BS11</name>
12791 <description>Port x set bit y (y=
12792 0..15)</description>
12793 <bitOffset>11</bitOffset>
12794 <bitWidth>1</bitWidth>
12795 </field>
12796 <field>
12797 <name>BS10</name>
12798 <description>Port x set bit y (y=
12799 0..15)</description>
12800 <bitOffset>10</bitOffset>
12801 <bitWidth>1</bitWidth>
12802 </field>
12803 <field>
12804 <name>BS9</name>
12805 <description>Port x set bit y (y=
12806 0..15)</description>
12807 <bitOffset>9</bitOffset>
12808 <bitWidth>1</bitWidth>
12809 </field>
12810 <field>
12811 <name>BS8</name>
12812 <description>Port x set bit y (y=
12813 0..15)</description>
12814 <bitOffset>8</bitOffset>
12815 <bitWidth>1</bitWidth>
12816 </field>
12817 <field>
12818 <name>BS7</name>
12819 <description>Port x set bit y (y=
12820 0..15)</description>
12821 <bitOffset>7</bitOffset>
12822 <bitWidth>1</bitWidth>
12823 </field>
12824 <field>
12825 <name>BS6</name>
12826 <description>Port x set bit y (y=
12827 0..15)</description>
12828 <bitOffset>6</bitOffset>
12829 <bitWidth>1</bitWidth>
12830 </field>
12831 <field>
12832 <name>BS5</name>
12833 <description>Port x set bit y (y=
12834 0..15)</description>
12835 <bitOffset>5</bitOffset>
12836 <bitWidth>1</bitWidth>
12837 </field>
12838 <field>
12839 <name>BS4</name>
12840 <description>Port x set bit y (y=
12841 0..15)</description>
12842 <bitOffset>4</bitOffset>
12843 <bitWidth>1</bitWidth>
12844 </field>
12845 <field>
12846 <name>BS3</name>
12847 <description>Port x set bit y (y=
12848 0..15)</description>
12849 <bitOffset>3</bitOffset>
12850 <bitWidth>1</bitWidth>
12851 </field>
12852 <field>
12853 <name>BS2</name>
12854 <description>Port x set bit y (y=
12855 0..15)</description>
12856 <bitOffset>2</bitOffset>
12857 <bitWidth>1</bitWidth>
12858 </field>
12859 <field>
12860 <name>BS1</name>
12861 <description>Port x set bit y (y=
12862 0..15)</description>
12863 <bitOffset>1</bitOffset>
12864 <bitWidth>1</bitWidth>
12865 </field>
12866 <field>
12867 <name>BS0</name>
12868 <description>Port x set bit y (y=
12869 0..15)</description>
12870 <bitOffset>0</bitOffset>
12871 <bitWidth>1</bitWidth>
12872 </field>
12873 </fields>
12874 </register>
12875 <register>
12876 <name>LCKR</name>
12877 <displayName>LCKR</displayName>
12878 <description>GPIO port configuration lock
12879 register</description>
12880 <addressOffset>0x1C</addressOffset>
12881 <size>0x20</size>
12882 <access>read-write</access>
12883 <resetValue>0x00000000</resetValue>
12884 <fields>
12885 <field>
12886 <name>LCKK</name>
12887 <description>Port x lock bit y (y=
12888 0..15)</description>
12889 <bitOffset>16</bitOffset>
12890 <bitWidth>1</bitWidth>
12891 </field>
12892 <field>
12893 <name>LCK15</name>
12894 <description>Port x lock bit y (y=
12895 0..15)</description>
12896 <bitOffset>15</bitOffset>
12897 <bitWidth>1</bitWidth>
12898 </field>
12899 <field>
12900 <name>LCK14</name>
12901 <description>Port x lock bit y (y=
12902 0..15)</description>
12903 <bitOffset>14</bitOffset>
12904 <bitWidth>1</bitWidth>
12905 </field>
12906 <field>
12907 <name>LCK13</name>
12908 <description>Port x lock bit y (y=
12909 0..15)</description>
12910 <bitOffset>13</bitOffset>
12911 <bitWidth>1</bitWidth>
12912 </field>
12913 <field>
12914 <name>LCK12</name>
12915 <description>Port x lock bit y (y=
12916 0..15)</description>
12917 <bitOffset>12</bitOffset>
12918 <bitWidth>1</bitWidth>
12919 </field>
12920 <field>
12921 <name>LCK11</name>
12922 <description>Port x lock bit y (y=
12923 0..15)</description>
12924 <bitOffset>11</bitOffset>
12925 <bitWidth>1</bitWidth>
12926 </field>
12927 <field>
12928 <name>LCK10</name>
12929 <description>Port x lock bit y (y=
12930 0..15)</description>
12931 <bitOffset>10</bitOffset>
12932 <bitWidth>1</bitWidth>
12933 </field>
12934 <field>
12935 <name>LCK9</name>
12936 <description>Port x lock bit y (y=
12937 0..15)</description>
12938 <bitOffset>9</bitOffset>
12939 <bitWidth>1</bitWidth>
12940 </field>
12941 <field>
12942 <name>LCK8</name>
12943 <description>Port x lock bit y (y=
12944 0..15)</description>
12945 <bitOffset>8</bitOffset>
12946 <bitWidth>1</bitWidth>
12947 </field>
12948 <field>
12949 <name>LCK7</name>
12950 <description>Port x lock bit y (y=
12951 0..15)</description>
12952 <bitOffset>7</bitOffset>
12953 <bitWidth>1</bitWidth>
12954 </field>
12955 <field>
12956 <name>LCK6</name>
12957 <description>Port x lock bit y (y=
12958 0..15)</description>
12959 <bitOffset>6</bitOffset>
12960 <bitWidth>1</bitWidth>
12961 </field>
12962 <field>
12963 <name>LCK5</name>
12964 <description>Port x lock bit y (y=
12965 0..15)</description>
12966 <bitOffset>5</bitOffset>
12967 <bitWidth>1</bitWidth>
12968 </field>
12969 <field>
12970 <name>LCK4</name>
12971 <description>Port x lock bit y (y=
12972 0..15)</description>
12973 <bitOffset>4</bitOffset>
12974 <bitWidth>1</bitWidth>
12975 </field>
12976 <field>
12977 <name>LCK3</name>
12978 <description>Port x lock bit y (y=
12979 0..15)</description>
12980 <bitOffset>3</bitOffset>
12981 <bitWidth>1</bitWidth>
12982 </field>
12983 <field>
12984 <name>LCK2</name>
12985 <description>Port x lock bit y (y=
12986 0..15)</description>
12987 <bitOffset>2</bitOffset>
12988 <bitWidth>1</bitWidth>
12989 </field>
12990 <field>
12991 <name>LCK1</name>
12992 <description>Port x lock bit y (y=
12993 0..15)</description>
12994 <bitOffset>1</bitOffset>
12995 <bitWidth>1</bitWidth>
12996 </field>
12997 <field>
12998 <name>LCK0</name>
12999 <description>Port x lock bit y (y=
13000 0..15)</description>
13001 <bitOffset>0</bitOffset>
13002 <bitWidth>1</bitWidth>
13003 </field>
13004 </fields>
13005 </register>
13006 <register>
13007 <name>AFRL</name>
13008 <displayName>AFRL</displayName>
13009 <description>GPIO alternate function
13010 lowregister</description>
13011 <addressOffset>0x20</addressOffset>
13012 <size>0x20</size>
13013 <access>read-write</access>
13014 <resetValue>0x00000000</resetValue>
13015 <fields>
13016 <field>
13017 <name>AFRL7</name>
13018 <description>Alternate function selection for port x
13019 bit y (y = 0..7)</description>
13020 <bitOffset>28</bitOffset>
13021 <bitWidth>4</bitWidth>
13022 </field>
13023 <field>
13024 <name>AFRL6</name>
13025 <description>Alternate function selection for port x
13026 bit y (y = 0..7)</description>
13027 <bitOffset>24</bitOffset>
13028 <bitWidth>4</bitWidth>
13029 </field>
13030 <field>
13031 <name>AFRL5</name>
13032 <description>Alternate function selection for port x
13033 bit y (y = 0..7)</description>
13034 <bitOffset>20</bitOffset>
13035 <bitWidth>4</bitWidth>
13036 </field>
13037 <field>
13038 <name>AFRL4</name>
13039 <description>Alternate function selection for port x
13040 bit y (y = 0..7)</description>
13041 <bitOffset>16</bitOffset>
13042 <bitWidth>4</bitWidth>
13043 </field>
13044 <field>
13045 <name>AFRL3</name>
13046 <description>Alternate function selection for port x
13047 bit y (y = 0..7)</description>
13048 <bitOffset>12</bitOffset>
13049 <bitWidth>4</bitWidth>
13050 </field>
13051 <field>
13052 <name>AFRL2</name>
13053 <description>Alternate function selection for port x
13054 bit y (y = 0..7)</description>
13055 <bitOffset>8</bitOffset>
13056 <bitWidth>4</bitWidth>
13057 </field>
13058 <field>
13059 <name>AFRL1</name>
13060 <description>Alternate function selection for port x
13061 bit y (y = 0..7)</description>
13062 <bitOffset>4</bitOffset>
13063 <bitWidth>4</bitWidth>
13064 </field>
13065 <field>
13066 <name>AFRL0</name>
13067 <description>Alternate function selection for port x
13068 bit y (y = 0..7)</description>
13069 <bitOffset>0</bitOffset>
13070 <bitWidth>4</bitWidth>
13071 </field>
13072 </fields>
13073 </register>
13074 <register>
13075 <name>AFRH</name>
13076 <displayName>AFRH</displayName>
13077 <description>GPIO alternate function high
13078 register</description>
13079 <addressOffset>0x24</addressOffset>
13080 <size>0x20</size>
13081 <access>read-write</access>
13082 <resetValue>0x00000000</resetValue>
13083 <fields>
13084 <field>
13085 <name>AFRH15</name>
13086 <description>Alternate function selection for port x
13087 bit y (y = 8..15)</description>
13088 <bitOffset>28</bitOffset>
13089 <bitWidth>4</bitWidth>
13090 </field>
13091 <field>
13092 <name>AFRH14</name>
13093 <description>Alternate function selection for port x
13094 bit y (y = 8..15)</description>
13095 <bitOffset>24</bitOffset>
13096 <bitWidth>4</bitWidth>
13097 </field>
13098 <field>
13099 <name>AFRH13</name>
13100 <description>Alternate function selection for port x
13101 bit y (y = 8..15)</description>
13102 <bitOffset>20</bitOffset>
13103 <bitWidth>4</bitWidth>
13104 </field>
13105 <field>
13106 <name>AFRH12</name>
13107 <description>Alternate function selection for port x
13108 bit y (y = 8..15)</description>
13109 <bitOffset>16</bitOffset>
13110 <bitWidth>4</bitWidth>
13111 </field>
13112 <field>
13113 <name>AFRH11</name>
13114 <description>Alternate function selection for port x
13115 bit y (y = 8..15)</description>
13116 <bitOffset>12</bitOffset>
13117 <bitWidth>4</bitWidth>
13118 </field>
13119 <field>
13120 <name>AFRH10</name>
13121 <description>Alternate function selection for port x
13122 bit y (y = 8..15)</description>
13123 <bitOffset>8</bitOffset>
13124 <bitWidth>4</bitWidth>
13125 </field>
13126 <field>
13127 <name>AFRH9</name>
13128 <description>Alternate function selection for port x
13129 bit y (y = 8..15)</description>
13130 <bitOffset>4</bitOffset>
13131 <bitWidth>4</bitWidth>
13132 </field>
13133 <field>
13134 <name>AFRH8</name>
13135 <description>Alternate function selection for port x
13136 bit y (y = 8..15)</description>
13137 <bitOffset>0</bitOffset>
13138 <bitWidth>4</bitWidth>
13139 </field>
13140 </fields>
13141 </register>
13142 <register>
13143 <name>BRR</name>
13144 <displayName>BRR</displayName>
13145 <description>GPIO port bit reset register</description>
13146 <addressOffset>0x28</addressOffset>
13147 <size>0x20</size>
13148 <access>read-write</access>
13149 <resetValue>0x00000000</resetValue>
13150 <fields>
13151 <field>
13152 <name>BR0</name>
13153 <description>Port D Reset bit 0</description>
13154 <bitOffset>0</bitOffset>
13155 <bitWidth>1</bitWidth>
13156 </field>
13157 <field>
13158 <name>BR1</name>
13159 <description>Port D Reset bit 1</description>
13160 <bitOffset>1</bitOffset>
13161 <bitWidth>1</bitWidth>
13162 </field>
13163 <field>
13164 <name>BR2</name>
13165 <description>Port D Reset bit 2</description>
13166 <bitOffset>2</bitOffset>
13167 <bitWidth>1</bitWidth>
13168 </field>
13169 <field>
13170 <name>BR3</name>
13171 <description>Port D Reset bit 3</description>
13172 <bitOffset>3</bitOffset>
13173 <bitWidth>1</bitWidth>
13174 </field>
13175 <field>
13176 <name>BR4</name>
13177 <description>Port D Reset bit 4</description>
13178 <bitOffset>4</bitOffset>
13179 <bitWidth>1</bitWidth>
13180 </field>
13181 <field>
13182 <name>BR5</name>
13183 <description>Port D Reset bit 5</description>
13184 <bitOffset>5</bitOffset>
13185 <bitWidth>1</bitWidth>
13186 </field>
13187 <field>
13188 <name>BR6</name>
13189 <description>Port D Reset bit 6</description>
13190 <bitOffset>6</bitOffset>
13191 <bitWidth>1</bitWidth>
13192 </field>
13193 <field>
13194 <name>BR7</name>
13195 <description>Port D Reset bit 7</description>
13196 <bitOffset>7</bitOffset>
13197 <bitWidth>1</bitWidth>
13198 </field>
13199 <field>
13200 <name>BR8</name>
13201 <description>Port D Reset bit 8</description>
13202 <bitOffset>8</bitOffset>
13203 <bitWidth>1</bitWidth>
13204 </field>
13205 <field>
13206 <name>BR9</name>
13207 <description>Port D Reset bit 9</description>
13208 <bitOffset>9</bitOffset>
13209 <bitWidth>1</bitWidth>
13210 </field>
13211 <field>
13212 <name>BR10</name>
13213 <description>Port D Reset bit 10</description>
13214 <bitOffset>10</bitOffset>
13215 <bitWidth>1</bitWidth>
13216 </field>
13217 <field>
13218 <name>BR11</name>
13219 <description>Port D Reset bit 11</description>
13220 <bitOffset>11</bitOffset>
13221 <bitWidth>1</bitWidth>
13222 </field>
13223 <field>
13224 <name>BR12</name>
13225 <description>Port D Reset bit 12</description>
13226 <bitOffset>12</bitOffset>
13227 <bitWidth>1</bitWidth>
13228 </field>
13229 <field>
13230 <name>BR13</name>
13231 <description>Port D Reset bit 13</description>
13232 <bitOffset>13</bitOffset>
13233 <bitWidth>1</bitWidth>
13234 </field>
13235 <field>
13236 <name>BR14</name>
13237 <description>Port D Reset bit 14</description>
13238 <bitOffset>14</bitOffset>
13239 <bitWidth>1</bitWidth>
13240 </field>
13241 <field>
13242 <name>BR15</name>
13243 <description>Port D Reset bit 15</description>
13244 <bitOffset>15</bitOffset>
13245 <bitWidth>1</bitWidth>
13246 </field>
13247 </fields>
13248 </register>
13249 </registers>
13250 </peripheral>
13251 <peripheral derivedFrom="GPIOD">
13252 <name>GPIOC</name>
13253 <baseAddress>0x40020800</baseAddress>
13254 </peripheral>
13255 <peripheral derivedFrom="GPIOD">
13256 <name>GPIOK</name>
13257 <baseAddress>0X40022800</baseAddress>
13258 </peripheral>
13259 <peripheral derivedFrom="GPIOD">
13260 <name>GPIOJ</name>
13261 <baseAddress>0X40022400</baseAddress>
13262 </peripheral>
13263 <peripheral derivedFrom="GPIOD">
13264 <name>GPIOI</name>
13265 <baseAddress>0X40022000</baseAddress>
13266 </peripheral>
13267 <peripheral derivedFrom="GPIOD">
13268 <name>GPIOH</name>
13269 <baseAddress>0X40021C00</baseAddress>
13270 </peripheral>
13271 <peripheral derivedFrom="GPIOD">
13272 <name>GPIOG</name>
13273 <baseAddress>0X40021800</baseAddress>
13274 </peripheral>
13275 <peripheral derivedFrom="GPIOD">
13276 <name>GPIOF</name>
13277 <baseAddress>0X40021400</baseAddress>
13278 </peripheral>
13279 <peripheral derivedFrom="GPIOD">
13280 <name>GPIOE</name>
13281 <baseAddress>0X40021000</baseAddress>
13282 </peripheral>
13283 <peripheral>
13284 <name>GPIOB</name>
13285 <description>General-purpose I/Os</description>
13286 <groupName>GPIO</groupName>
13287 <baseAddress>0x40020400</baseAddress>
13288 <addressBlock>
13289 <offset>0x0</offset>
13290 <size>0x400</size>
13291 <usage>registers</usage>
13292 </addressBlock>
13293 <registers>
13294 <register>
13295 <name>MODER</name>
13296 <displayName>MODER</displayName>
13297 <description>GPIO port mode register</description>
13298 <addressOffset>0x0</addressOffset>
13299 <size>0x20</size>
13300 <access>read-write</access>
13301 <resetValue>0x00000280</resetValue>
13302 <fields>
13303 <field>
13304 <name>MODER15</name>
13305 <description>Port x configuration bits (y =
13306 0..15)</description>
13307 <bitOffset>30</bitOffset>
13308 <bitWidth>2</bitWidth>
13309 </field>
13310 <field>
13311 <name>MODER14</name>
13312 <description>Port x configuration bits (y =
13313 0..15)</description>
13314 <bitOffset>28</bitOffset>
13315 <bitWidth>2</bitWidth>
13316 </field>
13317 <field>
13318 <name>MODER13</name>
13319 <description>Port x configuration bits (y =
13320 0..15)</description>
13321 <bitOffset>26</bitOffset>
13322 <bitWidth>2</bitWidth>
13323 </field>
13324 <field>
13325 <name>MODER12</name>
13326 <description>Port x configuration bits (y =
13327 0..15)</description>
13328 <bitOffset>24</bitOffset>
13329 <bitWidth>2</bitWidth>
13330 </field>
13331 <field>
13332 <name>MODER11</name>
13333 <description>Port x configuration bits (y =
13334 0..15)</description>
13335 <bitOffset>22</bitOffset>
13336 <bitWidth>2</bitWidth>
13337 </field>
13338 <field>
13339 <name>MODER10</name>
13340 <description>Port x configuration bits (y =
13341 0..15)</description>
13342 <bitOffset>20</bitOffset>
13343 <bitWidth>2</bitWidth>
13344 </field>
13345 <field>
13346 <name>MODER9</name>
13347 <description>Port x configuration bits (y =
13348 0..15)</description>
13349 <bitOffset>18</bitOffset>
13350 <bitWidth>2</bitWidth>
13351 </field>
13352 <field>
13353 <name>MODER8</name>
13354 <description>Port x configuration bits (y =
13355 0..15)</description>
13356 <bitOffset>16</bitOffset>
13357 <bitWidth>2</bitWidth>
13358 </field>
13359 <field>
13360 <name>MODER7</name>
13361 <description>Port x configuration bits (y =
13362 0..15)</description>
13363 <bitOffset>14</bitOffset>
13364 <bitWidth>2</bitWidth>
13365 </field>
13366 <field>
13367 <name>MODER6</name>
13368 <description>Port x configuration bits (y =
13369 0..15)</description>
13370 <bitOffset>12</bitOffset>
13371 <bitWidth>2</bitWidth>
13372 </field>
13373 <field>
13374 <name>MODER5</name>
13375 <description>Port x configuration bits (y =
13376 0..15)</description>
13377 <bitOffset>10</bitOffset>
13378 <bitWidth>2</bitWidth>
13379 </field>
13380 <field>
13381 <name>MODER4</name>
13382 <description>Port x configuration bits (y =
13383 0..15)</description>
13384 <bitOffset>8</bitOffset>
13385 <bitWidth>2</bitWidth>
13386 </field>
13387 <field>
13388 <name>MODER3</name>
13389 <description>Port x configuration bits (y =
13390 0..15)</description>
13391 <bitOffset>6</bitOffset>
13392 <bitWidth>2</bitWidth>
13393 </field>
13394 <field>
13395 <name>MODER2</name>
13396 <description>Port x configuration bits (y =
13397 0..15)</description>
13398 <bitOffset>4</bitOffset>
13399 <bitWidth>2</bitWidth>
13400 </field>
13401 <field>
13402 <name>MODER1</name>
13403 <description>Port x configuration bits (y =
13404 0..15)</description>
13405 <bitOffset>2</bitOffset>
13406 <bitWidth>2</bitWidth>
13407 </field>
13408 <field>
13409 <name>MODER0</name>
13410 <description>Port x configuration bits (y =
13411 0..15)</description>
13412 <bitOffset>0</bitOffset>
13413 <bitWidth>2</bitWidth>
13414 </field>
13415 </fields>
13416 </register>
13417 <register>
13418 <name>OTYPER</name>
13419 <displayName>OTYPER</displayName>
13420 <description>GPIO port output type register</description>
13421 <addressOffset>0x4</addressOffset>
13422 <size>0x20</size>
13423 <access>read-write</access>
13424 <resetValue>0x00000000</resetValue>
13425 <fields>
13426 <field>
13427 <name>OT15</name>
13428 <description>Port x configuration bits (y =
13429 0..15)</description>
13430 <bitOffset>15</bitOffset>
13431 <bitWidth>1</bitWidth>
13432 </field>
13433 <field>
13434 <name>OT14</name>
13435 <description>Port x configuration bits (y =
13436 0..15)</description>
13437 <bitOffset>14</bitOffset>
13438 <bitWidth>1</bitWidth>
13439 </field>
13440 <field>
13441 <name>OT13</name>
13442 <description>Port x configuration bits (y =
13443 0..15)</description>
13444 <bitOffset>13</bitOffset>
13445 <bitWidth>1</bitWidth>
13446 </field>
13447 <field>
13448 <name>OT12</name>
13449 <description>Port x configuration bits (y =
13450 0..15)</description>
13451 <bitOffset>12</bitOffset>
13452 <bitWidth>1</bitWidth>
13453 </field>
13454 <field>
13455 <name>OT11</name>
13456 <description>Port x configuration bits (y =
13457 0..15)</description>
13458 <bitOffset>11</bitOffset>
13459 <bitWidth>1</bitWidth>
13460 </field>
13461 <field>
13462 <name>OT10</name>
13463 <description>Port x configuration bits (y =
13464 0..15)</description>
13465 <bitOffset>10</bitOffset>
13466 <bitWidth>1</bitWidth>
13467 </field>
13468 <field>
13469 <name>OT9</name>
13470 <description>Port x configuration bits (y =
13471 0..15)</description>
13472 <bitOffset>9</bitOffset>
13473 <bitWidth>1</bitWidth>
13474 </field>
13475 <field>
13476 <name>OT8</name>
13477 <description>Port x configuration bits (y =
13478 0..15)</description>
13479 <bitOffset>8</bitOffset>
13480 <bitWidth>1</bitWidth>
13481 </field>
13482 <field>
13483 <name>OT7</name>
13484 <description>Port x configuration bits (y =
13485 0..15)</description>
13486 <bitOffset>7</bitOffset>
13487 <bitWidth>1</bitWidth>
13488 </field>
13489 <field>
13490 <name>OT6</name>
13491 <description>Port x configuration bits (y =
13492 0..15)</description>
13493 <bitOffset>6</bitOffset>
13494 <bitWidth>1</bitWidth>
13495 </field>
13496 <field>
13497 <name>OT5</name>
13498 <description>Port x configuration bits (y =
13499 0..15)</description>
13500 <bitOffset>5</bitOffset>
13501 <bitWidth>1</bitWidth>
13502 </field>
13503 <field>
13504 <name>OT4</name>
13505 <description>Port x configuration bits (y =
13506 0..15)</description>
13507 <bitOffset>4</bitOffset>
13508 <bitWidth>1</bitWidth>
13509 </field>
13510 <field>
13511 <name>OT3</name>
13512 <description>Port x configuration bits (y =
13513 0..15)</description>
13514 <bitOffset>3</bitOffset>
13515 <bitWidth>1</bitWidth>
13516 </field>
13517 <field>
13518 <name>OT2</name>
13519 <description>Port x configuration bits (y =
13520 0..15)</description>
13521 <bitOffset>2</bitOffset>
13522 <bitWidth>1</bitWidth>
13523 </field>
13524 <field>
13525 <name>OT1</name>
13526 <description>Port x configuration bits (y =
13527 0..15)</description>
13528 <bitOffset>1</bitOffset>
13529 <bitWidth>1</bitWidth>
13530 </field>
13531 <field>
13532 <name>OT0</name>
13533 <description>Port x configuration bits (y =
13534 0..15)</description>
13535 <bitOffset>0</bitOffset>
13536 <bitWidth>1</bitWidth>
13537 </field>
13538 </fields>
13539 </register>
13540 <register>
13541 <name>GPIOB_OSPEEDR</name>
13542 <displayName>GPIOB_OSPEEDR</displayName>
13543 <description>GPIO port output speed
13544 register</description>
13545 <addressOffset>0x8</addressOffset>
13546 <size>0x20</size>
13547 <access>read-write</access>
13548 <resetValue>0x000000C0</resetValue>
13549 <fields>
13550 <field>
13551 <name>OSPEEDR15</name>
13552 <description>Port x configuration bits (y =
13553 0..15)</description>
13554 <bitOffset>30</bitOffset>
13555 <bitWidth>2</bitWidth>
13556 </field>
13557 <field>
13558 <name>OSPEEDR14</name>
13559 <description>Port x configuration bits (y =
13560 0..15)</description>
13561 <bitOffset>28</bitOffset>
13562 <bitWidth>2</bitWidth>
13563 </field>
13564 <field>
13565 <name>OSPEEDR13</name>
13566 <description>Port x configuration bits (y =
13567 0..15)</description>
13568 <bitOffset>26</bitOffset>
13569 <bitWidth>2</bitWidth>
13570 </field>
13571 <field>
13572 <name>OSPEEDR12</name>
13573 <description>Port x configuration bits (y =
13574 0..15)</description>
13575 <bitOffset>24</bitOffset>
13576 <bitWidth>2</bitWidth>
13577 </field>
13578 <field>
13579 <name>OSPEEDR11</name>
13580 <description>Port x configuration bits (y =
13581 0..15)</description>
13582 <bitOffset>22</bitOffset>
13583 <bitWidth>2</bitWidth>
13584 </field>
13585 <field>
13586 <name>OSPEEDR10</name>
13587 <description>Port x configuration bits (y =
13588 0..15)</description>
13589 <bitOffset>20</bitOffset>
13590 <bitWidth>2</bitWidth>
13591 </field>
13592 <field>
13593 <name>OSPEEDR9</name>
13594 <description>Port x configuration bits (y =
13595 0..15)</description>
13596 <bitOffset>18</bitOffset>
13597 <bitWidth>2</bitWidth>
13598 </field>
13599 <field>
13600 <name>OSPEEDR8</name>
13601 <description>Port x configuration bits (y =
13602 0..15)</description>
13603 <bitOffset>16</bitOffset>
13604 <bitWidth>2</bitWidth>
13605 </field>
13606 <field>
13607 <name>OSPEEDR7</name>
13608 <description>Port x configuration bits (y =
13609 0..15)</description>
13610 <bitOffset>14</bitOffset>
13611 <bitWidth>2</bitWidth>
13612 </field>
13613 <field>
13614 <name>OSPEEDR6</name>
13615 <description>Port x configuration bits (y =
13616 0..15)</description>
13617 <bitOffset>12</bitOffset>
13618 <bitWidth>2</bitWidth>
13619 </field>
13620 <field>
13621 <name>OSPEEDR5</name>
13622 <description>Port x configuration bits (y =
13623 0..15)</description>
13624 <bitOffset>10</bitOffset>
13625 <bitWidth>2</bitWidth>
13626 </field>
13627 <field>
13628 <name>OSPEEDR4</name>
13629 <description>Port x configuration bits (y =
13630 0..15)</description>
13631 <bitOffset>8</bitOffset>
13632 <bitWidth>2</bitWidth>
13633 </field>
13634 <field>
13635 <name>OSPEEDR3</name>
13636 <description>Port x configuration bits (y =
13637 0..15)</description>
13638 <bitOffset>6</bitOffset>
13639 <bitWidth>2</bitWidth>
13640 </field>
13641 <field>
13642 <name>OSPEEDR2</name>
13643 <description>Port x configuration bits (y =
13644 0..15)</description>
13645 <bitOffset>4</bitOffset>
13646 <bitWidth>2</bitWidth>
13647 </field>
13648 <field>
13649 <name>OSPEEDR1</name>
13650 <description>Port x configuration bits (y =
13651 0..15)</description>
13652 <bitOffset>2</bitOffset>
13653 <bitWidth>2</bitWidth>
13654 </field>
13655 <field>
13656 <name>OSPEEDR0</name>
13657 <description>Port x configuration bits (y =
13658 0..15)</description>
13659 <bitOffset>0</bitOffset>
13660 <bitWidth>2</bitWidth>
13661 </field>
13662 </fields>
13663 </register>
13664 <register>
13665 <name>PUPDR</name>
13666 <displayName>PUPDR</displayName>
13667 <description>GPIO port pull-up/pull-down
13668 register</description>
13669 <addressOffset>0xC</addressOffset>
13670 <size>0x20</size>
13671 <access>read-write</access>
13672 <resetValue>0x00000100</resetValue>
13673 <fields>
13674 <field>
13675 <name>PUPDR15</name>
13676 <description>Port x configuration bits (y =
13677 0..15)</description>
13678 <bitOffset>30</bitOffset>
13679 <bitWidth>2</bitWidth>
13680 </field>
13681 <field>
13682 <name>PUPDR14</name>
13683 <description>Port x configuration bits (y =
13684 0..15)</description>
13685 <bitOffset>28</bitOffset>
13686 <bitWidth>2</bitWidth>
13687 </field>
13688 <field>
13689 <name>PUPDR13</name>
13690 <description>Port x configuration bits (y =
13691 0..15)</description>
13692 <bitOffset>26</bitOffset>
13693 <bitWidth>2</bitWidth>
13694 </field>
13695 <field>
13696 <name>PUPDR12</name>
13697 <description>Port x configuration bits (y =
13698 0..15)</description>
13699 <bitOffset>24</bitOffset>
13700 <bitWidth>2</bitWidth>
13701 </field>
13702 <field>
13703 <name>PUPDR11</name>
13704 <description>Port x configuration bits (y =
13705 0..15)</description>
13706 <bitOffset>22</bitOffset>
13707 <bitWidth>2</bitWidth>
13708 </field>
13709 <field>
13710 <name>PUPDR10</name>
13711 <description>Port x configuration bits (y =
13712 0..15)</description>
13713 <bitOffset>20</bitOffset>
13714 <bitWidth>2</bitWidth>
13715 </field>
13716 <field>
13717 <name>PUPDR9</name>
13718 <description>Port x configuration bits (y =
13719 0..15)</description>
13720 <bitOffset>18</bitOffset>
13721 <bitWidth>2</bitWidth>
13722 </field>
13723 <field>
13724 <name>PUPDR8</name>
13725 <description>Port x configuration bits (y =
13726 0..15)</description>
13727 <bitOffset>16</bitOffset>
13728 <bitWidth>2</bitWidth>
13729 </field>
13730 <field>
13731 <name>PUPDR7</name>
13732 <description>Port x configuration bits (y =
13733 0..15)</description>
13734 <bitOffset>14</bitOffset>
13735 <bitWidth>2</bitWidth>
13736 </field>
13737 <field>
13738 <name>PUPDR6</name>
13739 <description>Port x configuration bits (y =
13740 0..15)</description>
13741 <bitOffset>12</bitOffset>
13742 <bitWidth>2</bitWidth>
13743 </field>
13744 <field>
13745 <name>PUPDR5</name>
13746 <description>Port x configuration bits (y =
13747 0..15)</description>
13748 <bitOffset>10</bitOffset>
13749 <bitWidth>2</bitWidth>
13750 </field>
13751 <field>
13752 <name>PUPDR4</name>
13753 <description>Port x configuration bits (y =
13754 0..15)</description>
13755 <bitOffset>8</bitOffset>
13756 <bitWidth>2</bitWidth>
13757 </field>
13758 <field>
13759 <name>PUPDR3</name>
13760 <description>Port x configuration bits (y =
13761 0..15)</description>
13762 <bitOffset>6</bitOffset>
13763 <bitWidth>2</bitWidth>
13764 </field>
13765 <field>
13766 <name>PUPDR2</name>
13767 <description>Port x configuration bits (y =
13768 0..15)</description>
13769 <bitOffset>4</bitOffset>
13770 <bitWidth>2</bitWidth>
13771 </field>
13772 <field>
13773 <name>PUPDR1</name>
13774 <description>Port x configuration bits (y =
13775 0..15)</description>
13776 <bitOffset>2</bitOffset>
13777 <bitWidth>2</bitWidth>
13778 </field>
13779 <field>
13780 <name>PUPDR0</name>
13781 <description>Port x configuration bits (y =
13782 0..15)</description>
13783 <bitOffset>0</bitOffset>
13784 <bitWidth>2</bitWidth>
13785 </field>
13786 </fields>
13787 </register>
13788 <register>
13789 <name>IDR</name>
13790 <displayName>IDR</displayName>
13791 <description>GPIO port input data register</description>
13792 <addressOffset>0x10</addressOffset>
13793 <size>0x20</size>
13794 <access>read-only</access>
13795 <resetValue>0x00000000</resetValue>
13796 <fields>
13797 <field>
13798 <name>IDR15</name>
13799 <description>Port input data (y =
13800 0..15)</description>
13801 <bitOffset>15</bitOffset>
13802 <bitWidth>1</bitWidth>
13803 </field>
13804 <field>
13805 <name>IDR14</name>
13806 <description>Port input data (y =
13807 0..15)</description>
13808 <bitOffset>14</bitOffset>
13809 <bitWidth>1</bitWidth>
13810 </field>
13811 <field>
13812 <name>IDR13</name>
13813 <description>Port input data (y =
13814 0..15)</description>
13815 <bitOffset>13</bitOffset>
13816 <bitWidth>1</bitWidth>
13817 </field>
13818 <field>
13819 <name>IDR12</name>
13820 <description>Port input data (y =
13821 0..15)</description>
13822 <bitOffset>12</bitOffset>
13823 <bitWidth>1</bitWidth>
13824 </field>
13825 <field>
13826 <name>IDR11</name>
13827 <description>Port input data (y =
13828 0..15)</description>
13829 <bitOffset>11</bitOffset>
13830 <bitWidth>1</bitWidth>
13831 </field>
13832 <field>
13833 <name>IDR10</name>
13834 <description>Port input data (y =
13835 0..15)</description>
13836 <bitOffset>10</bitOffset>
13837 <bitWidth>1</bitWidth>
13838 </field>
13839 <field>
13840 <name>IDR9</name>
13841 <description>Port input data (y =
13842 0..15)</description>
13843 <bitOffset>9</bitOffset>
13844 <bitWidth>1</bitWidth>
13845 </field>
13846 <field>
13847 <name>IDR8</name>
13848 <description>Port input data (y =
13849 0..15)</description>
13850 <bitOffset>8</bitOffset>
13851 <bitWidth>1</bitWidth>
13852 </field>
13853 <field>
13854 <name>IDR7</name>
13855 <description>Port input data (y =
13856 0..15)</description>
13857 <bitOffset>7</bitOffset>
13858 <bitWidth>1</bitWidth>
13859 </field>
13860 <field>
13861 <name>IDR6</name>
13862 <description>Port input data (y =
13863 0..15)</description>
13864 <bitOffset>6</bitOffset>
13865 <bitWidth>1</bitWidth>
13866 </field>
13867 <field>
13868 <name>IDR5</name>
13869 <description>Port input data (y =
13870 0..15)</description>
13871 <bitOffset>5</bitOffset>
13872 <bitWidth>1</bitWidth>
13873 </field>
13874 <field>
13875 <name>IDR4</name>
13876 <description>Port input data (y =
13877 0..15)</description>
13878 <bitOffset>4</bitOffset>
13879 <bitWidth>1</bitWidth>
13880 </field>
13881 <field>
13882 <name>IDR3</name>
13883 <description>Port input data (y =
13884 0..15)</description>
13885 <bitOffset>3</bitOffset>
13886 <bitWidth>1</bitWidth>
13887 </field>
13888 <field>
13889 <name>IDR2</name>
13890 <description>Port input data (y =
13891 0..15)</description>
13892 <bitOffset>2</bitOffset>
13893 <bitWidth>1</bitWidth>
13894 </field>
13895 <field>
13896 <name>IDR1</name>
13897 <description>Port input data (y =
13898 0..15)</description>
13899 <bitOffset>1</bitOffset>
13900 <bitWidth>1</bitWidth>
13901 </field>
13902 <field>
13903 <name>IDR0</name>
13904 <description>Port input data (y =
13905 0..15)</description>
13906 <bitOffset>0</bitOffset>
13907 <bitWidth>1</bitWidth>
13908 </field>
13909 </fields>
13910 </register>
13911 <register>
13912 <name>ODR</name>
13913 <displayName>ODR</displayName>
13914 <description>GPIO port output data register</description>
13915 <addressOffset>0x14</addressOffset>
13916 <size>0x20</size>
13917 <access>read-write</access>
13918 <resetValue>0x00000000</resetValue>
13919 <fields>
13920 <field>
13921 <name>ODR15</name>
13922 <description>Port output data (y =
13923 0..15)</description>
13924 <bitOffset>15</bitOffset>
13925 <bitWidth>1</bitWidth>
13926 </field>
13927 <field>
13928 <name>ODR14</name>
13929 <description>Port output data (y =
13930 0..15)</description>
13931 <bitOffset>14</bitOffset>
13932 <bitWidth>1</bitWidth>
13933 </field>
13934 <field>
13935 <name>ODR13</name>
13936 <description>Port output data (y =
13937 0..15)</description>
13938 <bitOffset>13</bitOffset>
13939 <bitWidth>1</bitWidth>
13940 </field>
13941 <field>
13942 <name>ODR12</name>
13943 <description>Port output data (y =
13944 0..15)</description>
13945 <bitOffset>12</bitOffset>
13946 <bitWidth>1</bitWidth>
13947 </field>
13948 <field>
13949 <name>ODR11</name>
13950 <description>Port output data (y =
13951 0..15)</description>
13952 <bitOffset>11</bitOffset>
13953 <bitWidth>1</bitWidth>
13954 </field>
13955 <field>
13956 <name>ODR10</name>
13957 <description>Port output data (y =
13958 0..15)</description>
13959 <bitOffset>10</bitOffset>
13960 <bitWidth>1</bitWidth>
13961 </field>
13962 <field>
13963 <name>ODR9</name>
13964 <description>Port output data (y =
13965 0..15)</description>
13966 <bitOffset>9</bitOffset>
13967 <bitWidth>1</bitWidth>
13968 </field>
13969 <field>
13970 <name>ODR8</name>
13971 <description>Port output data (y =
13972 0..15)</description>
13973 <bitOffset>8</bitOffset>
13974 <bitWidth>1</bitWidth>
13975 </field>
13976 <field>
13977 <name>ODR7</name>
13978 <description>Port output data (y =
13979 0..15)</description>
13980 <bitOffset>7</bitOffset>
13981 <bitWidth>1</bitWidth>
13982 </field>
13983 <field>
13984 <name>ODR6</name>
13985 <description>Port output data (y =
13986 0..15)</description>
13987 <bitOffset>6</bitOffset>
13988 <bitWidth>1</bitWidth>
13989 </field>
13990 <field>
13991 <name>ODR5</name>
13992 <description>Port output data (y =
13993 0..15)</description>
13994 <bitOffset>5</bitOffset>
13995 <bitWidth>1</bitWidth>
13996 </field>
13997 <field>
13998 <name>ODR4</name>
13999 <description>Port output data (y =
14000 0..15)</description>
14001 <bitOffset>4</bitOffset>
14002 <bitWidth>1</bitWidth>
14003 </field>
14004 <field>
14005 <name>ODR3</name>
14006 <description>Port output data (y =
14007 0..15)</description>
14008 <bitOffset>3</bitOffset>
14009 <bitWidth>1</bitWidth>
14010 </field>
14011 <field>
14012 <name>ODR2</name>
14013 <description>Port output data (y =
14014 0..15)</description>
14015 <bitOffset>2</bitOffset>
14016 <bitWidth>1</bitWidth>
14017 </field>
14018 <field>
14019 <name>ODR1</name>
14020 <description>Port output data (y =
14021 0..15)</description>
14022 <bitOffset>1</bitOffset>
14023 <bitWidth>1</bitWidth>
14024 </field>
14025 <field>
14026 <name>ODR0</name>
14027 <description>Port output data (y =
14028 0..15)</description>
14029 <bitOffset>0</bitOffset>
14030 <bitWidth>1</bitWidth>
14031 </field>
14032 </fields>
14033 </register>
14034 <register>
14035 <name>BSRR</name>
14036 <displayName>BSRR</displayName>
14037 <description>GPIO port bit set/reset
14038 register</description>
14039 <addressOffset>0x18</addressOffset>
14040 <size>0x20</size>
14041 <access>write-only</access>
14042 <resetValue>0x00000000</resetValue>
14043 <fields>
14044 <field>
14045 <name>BR15</name>
14046 <description>Port x reset bit y (y =
14047 0..15)</description>
14048 <bitOffset>31</bitOffset>
14049 <bitWidth>1</bitWidth>
14050 </field>
14051 <field>
14052 <name>BR14</name>
14053 <description>Port x reset bit y (y =
14054 0..15)</description>
14055 <bitOffset>30</bitOffset>
14056 <bitWidth>1</bitWidth>
14057 </field>
14058 <field>
14059 <name>BR13</name>
14060 <description>Port x reset bit y (y =
14061 0..15)</description>
14062 <bitOffset>29</bitOffset>
14063 <bitWidth>1</bitWidth>
14064 </field>
14065 <field>
14066 <name>BR12</name>
14067 <description>Port x reset bit y (y =
14068 0..15)</description>
14069 <bitOffset>28</bitOffset>
14070 <bitWidth>1</bitWidth>
14071 </field>
14072 <field>
14073 <name>BR11</name>
14074 <description>Port x reset bit y (y =
14075 0..15)</description>
14076 <bitOffset>27</bitOffset>
14077 <bitWidth>1</bitWidth>
14078 </field>
14079 <field>
14080 <name>BR10</name>
14081 <description>Port x reset bit y (y =
14082 0..15)</description>
14083 <bitOffset>26</bitOffset>
14084 <bitWidth>1</bitWidth>
14085 </field>
14086 <field>
14087 <name>BR9</name>
14088 <description>Port x reset bit y (y =
14089 0..15)</description>
14090 <bitOffset>25</bitOffset>
14091 <bitWidth>1</bitWidth>
14092 </field>
14093 <field>
14094 <name>BR8</name>
14095 <description>Port x reset bit y (y =
14096 0..15)</description>
14097 <bitOffset>24</bitOffset>
14098 <bitWidth>1</bitWidth>
14099 </field>
14100 <field>
14101 <name>BR7</name>
14102 <description>Port x reset bit y (y =
14103 0..15)</description>
14104 <bitOffset>23</bitOffset>
14105 <bitWidth>1</bitWidth>
14106 </field>
14107 <field>
14108 <name>BR6</name>
14109 <description>Port x reset bit y (y =
14110 0..15)</description>
14111 <bitOffset>22</bitOffset>
14112 <bitWidth>1</bitWidth>
14113 </field>
14114 <field>
14115 <name>BR5</name>
14116 <description>Port x reset bit y (y =
14117 0..15)</description>
14118 <bitOffset>21</bitOffset>
14119 <bitWidth>1</bitWidth>
14120 </field>
14121 <field>
14122 <name>BR4</name>
14123 <description>Port x reset bit y (y =
14124 0..15)</description>
14125 <bitOffset>20</bitOffset>
14126 <bitWidth>1</bitWidth>
14127 </field>
14128 <field>
14129 <name>BR3</name>
14130 <description>Port x reset bit y (y =
14131 0..15)</description>
14132 <bitOffset>19</bitOffset>
14133 <bitWidth>1</bitWidth>
14134 </field>
14135 <field>
14136 <name>BR2</name>
14137 <description>Port x reset bit y (y =
14138 0..15)</description>
14139 <bitOffset>18</bitOffset>
14140 <bitWidth>1</bitWidth>
14141 </field>
14142 <field>
14143 <name>BR1</name>
14144 <description>Port x reset bit y (y =
14145 0..15)</description>
14146 <bitOffset>17</bitOffset>
14147 <bitWidth>1</bitWidth>
14148 </field>
14149 <field>
14150 <name>BR0</name>
14151 <description>Port x set bit y (y=
14152 0..15)</description>
14153 <bitOffset>16</bitOffset>
14154 <bitWidth>1</bitWidth>
14155 </field>
14156 <field>
14157 <name>BS15</name>
14158 <description>Port x set bit y (y=
14159 0..15)</description>
14160 <bitOffset>15</bitOffset>
14161 <bitWidth>1</bitWidth>
14162 </field>
14163 <field>
14164 <name>BS14</name>
14165 <description>Port x set bit y (y=
14166 0..15)</description>
14167 <bitOffset>14</bitOffset>
14168 <bitWidth>1</bitWidth>
14169 </field>
14170 <field>
14171 <name>BS13</name>
14172 <description>Port x set bit y (y=
14173 0..15)</description>
14174 <bitOffset>13</bitOffset>
14175 <bitWidth>1</bitWidth>
14176 </field>
14177 <field>
14178 <name>BS12</name>
14179 <description>Port x set bit y (y=
14180 0..15)</description>
14181 <bitOffset>12</bitOffset>
14182 <bitWidth>1</bitWidth>
14183 </field>
14184 <field>
14185 <name>BS11</name>
14186 <description>Port x set bit y (y=
14187 0..15)</description>
14188 <bitOffset>11</bitOffset>
14189 <bitWidth>1</bitWidth>
14190 </field>
14191 <field>
14192 <name>BS10</name>
14193 <description>Port x set bit y (y=
14194 0..15)</description>
14195 <bitOffset>10</bitOffset>
14196 <bitWidth>1</bitWidth>
14197 </field>
14198 <field>
14199 <name>BS9</name>
14200 <description>Port x set bit y (y=
14201 0..15)</description>
14202 <bitOffset>9</bitOffset>
14203 <bitWidth>1</bitWidth>
14204 </field>
14205 <field>
14206 <name>BS8</name>
14207 <description>Port x set bit y (y=
14208 0..15)</description>
14209 <bitOffset>8</bitOffset>
14210 <bitWidth>1</bitWidth>
14211 </field>
14212 <field>
14213 <name>BS7</name>
14214 <description>Port x set bit y (y=
14215 0..15)</description>
14216 <bitOffset>7</bitOffset>
14217 <bitWidth>1</bitWidth>
14218 </field>
14219 <field>
14220 <name>BS6</name>
14221 <description>Port x set bit y (y=
14222 0..15)</description>
14223 <bitOffset>6</bitOffset>
14224 <bitWidth>1</bitWidth>
14225 </field>
14226 <field>
14227 <name>BS5</name>
14228 <description>Port x set bit y (y=
14229 0..15)</description>
14230 <bitOffset>5</bitOffset>
14231 <bitWidth>1</bitWidth>
14232 </field>
14233 <field>
14234 <name>BS4</name>
14235 <description>Port x set bit y (y=
14236 0..15)</description>
14237 <bitOffset>4</bitOffset>
14238 <bitWidth>1</bitWidth>
14239 </field>
14240 <field>
14241 <name>BS3</name>
14242 <description>Port x set bit y (y=
14243 0..15)</description>
14244 <bitOffset>3</bitOffset>
14245 <bitWidth>1</bitWidth>
14246 </field>
14247 <field>
14248 <name>BS2</name>
14249 <description>Port x set bit y (y=
14250 0..15)</description>
14251 <bitOffset>2</bitOffset>
14252 <bitWidth>1</bitWidth>
14253 </field>
14254 <field>
14255 <name>BS1</name>
14256 <description>Port x set bit y (y=
14257 0..15)</description>
14258 <bitOffset>1</bitOffset>
14259 <bitWidth>1</bitWidth>
14260 </field>
14261 <field>
14262 <name>BS0</name>
14263 <description>Port x set bit y (y=
14264 0..15)</description>
14265 <bitOffset>0</bitOffset>
14266 <bitWidth>1</bitWidth>
14267 </field>
14268 </fields>
14269 </register>
14270 <register>
14271 <name>LCKR</name>
14272 <displayName>LCKR</displayName>
14273 <description>GPIO port configuration lock
14274 register</description>
14275 <addressOffset>0x1C</addressOffset>
14276 <size>0x20</size>
14277 <access>read-write</access>
14278 <resetValue>0x00000000</resetValue>
14279 <fields>
14280 <field>
14281 <name>LCKK</name>
14282 <description>Port x lock bit y (y=
14283 0..15)</description>
14284 <bitOffset>16</bitOffset>
14285 <bitWidth>1</bitWidth>
14286 </field>
14287 <field>
14288 <name>LCK15</name>
14289 <description>Port x lock bit y (y=
14290 0..15)</description>
14291 <bitOffset>15</bitOffset>
14292 <bitWidth>1</bitWidth>
14293 </field>
14294 <field>
14295 <name>LCK14</name>
14296 <description>Port x lock bit y (y=
14297 0..15)</description>
14298 <bitOffset>14</bitOffset>
14299 <bitWidth>1</bitWidth>
14300 </field>
14301 <field>
14302 <name>LCK13</name>
14303 <description>Port x lock bit y (y=
14304 0..15)</description>
14305 <bitOffset>13</bitOffset>
14306 <bitWidth>1</bitWidth>
14307 </field>
14308 <field>
14309 <name>LCK12</name>
14310 <description>Port x lock bit y (y=
14311 0..15)</description>
14312 <bitOffset>12</bitOffset>
14313 <bitWidth>1</bitWidth>
14314 </field>
14315 <field>
14316 <name>LCK11</name>
14317 <description>Port x lock bit y (y=
14318 0..15)</description>
14319 <bitOffset>11</bitOffset>
14320 <bitWidth>1</bitWidth>
14321 </field>
14322 <field>
14323 <name>LCK10</name>
14324 <description>Port x lock bit y (y=
14325 0..15)</description>
14326 <bitOffset>10</bitOffset>
14327 <bitWidth>1</bitWidth>
14328 </field>
14329 <field>
14330 <name>LCK9</name>
14331 <description>Port x lock bit y (y=
14332 0..15)</description>
14333 <bitOffset>9</bitOffset>
14334 <bitWidth>1</bitWidth>
14335 </field>
14336 <field>
14337 <name>LCK8</name>
14338 <description>Port x lock bit y (y=
14339 0..15)</description>
14340 <bitOffset>8</bitOffset>
14341 <bitWidth>1</bitWidth>
14342 </field>
14343 <field>
14344 <name>LCK7</name>
14345 <description>Port x lock bit y (y=
14346 0..15)</description>
14347 <bitOffset>7</bitOffset>
14348 <bitWidth>1</bitWidth>
14349 </field>
14350 <field>
14351 <name>LCK6</name>
14352 <description>Port x lock bit y (y=
14353 0..15)</description>
14354 <bitOffset>6</bitOffset>
14355 <bitWidth>1</bitWidth>
14356 </field>
14357 <field>
14358 <name>LCK5</name>
14359 <description>Port x lock bit y (y=
14360 0..15)</description>
14361 <bitOffset>5</bitOffset>
14362 <bitWidth>1</bitWidth>
14363 </field>
14364 <field>
14365 <name>LCK4</name>
14366 <description>Port x lock bit y (y=
14367 0..15)</description>
14368 <bitOffset>4</bitOffset>
14369 <bitWidth>1</bitWidth>
14370 </field>
14371 <field>
14372 <name>LCK3</name>
14373 <description>Port x lock bit y (y=
14374 0..15)</description>
14375 <bitOffset>3</bitOffset>
14376 <bitWidth>1</bitWidth>
14377 </field>
14378 <field>
14379 <name>LCK2</name>
14380 <description>Port x lock bit y (y=
14381 0..15)</description>
14382 <bitOffset>2</bitOffset>
14383 <bitWidth>1</bitWidth>
14384 </field>
14385 <field>
14386 <name>LCK1</name>
14387 <description>Port x lock bit y (y=
14388 0..15)</description>
14389 <bitOffset>1</bitOffset>
14390 <bitWidth>1</bitWidth>
14391 </field>
14392 <field>
14393 <name>LCK0</name>
14394 <description>Port x lock bit y (y=
14395 0..15)</description>
14396 <bitOffset>0</bitOffset>
14397 <bitWidth>1</bitWidth>
14398 </field>
14399 </fields>
14400 </register>
14401 <register>
14402 <name>AFRL</name>
14403 <displayName>AFRL</displayName>
14404 <description>GPIO alternate function low
14405 register</description>
14406 <addressOffset>0x20</addressOffset>
14407 <size>0x20</size>
14408 <access>read-write</access>
14409 <resetValue>0x00000000</resetValue>
14410 <fields>
14411 <field>
14412 <name>AFRL7</name>
14413 <description>Alternate function selection for port x
14414 bit y (y = 0..7)</description>
14415 <bitOffset>28</bitOffset>
14416 <bitWidth>4</bitWidth>
14417 </field>
14418 <field>
14419 <name>AFRL6</name>
14420 <description>Alternate function selection for port x
14421 bit y (y = 0..7)</description>
14422 <bitOffset>24</bitOffset>
14423 <bitWidth>4</bitWidth>
14424 </field>
14425 <field>
14426 <name>AFRL5</name>
14427 <description>Alternate function selection for port x
14428 bit y (y = 0..7)</description>
14429 <bitOffset>20</bitOffset>
14430 <bitWidth>4</bitWidth>
14431 </field>
14432 <field>
14433 <name>AFRL4</name>
14434 <description>Alternate function selection for port x
14435 bit y (y = 0..7)</description>
14436 <bitOffset>16</bitOffset>
14437 <bitWidth>4</bitWidth>
14438 </field>
14439 <field>
14440 <name>AFRL3</name>
14441 <description>Alternate function selection for port x
14442 bit y (y = 0..7)</description>
14443 <bitOffset>12</bitOffset>
14444 <bitWidth>4</bitWidth>
14445 </field>
14446 <field>
14447 <name>AFRL2</name>
14448 <description>Alternate function selection for port x
14449 bit y (y = 0..7)</description>
14450 <bitOffset>8</bitOffset>
14451 <bitWidth>4</bitWidth>
14452 </field>
14453 <field>
14454 <name>AFRL1</name>
14455 <description>Alternate function selection for port x
14456 bit y (y = 0..7)</description>
14457 <bitOffset>4</bitOffset>
14458 <bitWidth>4</bitWidth>
14459 </field>
14460 <field>
14461 <name>AFRL0</name>
14462 <description>Alternate function selection for port x
14463 bit y (y = 0..7)</description>
14464 <bitOffset>0</bitOffset>
14465 <bitWidth>4</bitWidth>
14466 </field>
14467 </fields>
14468 </register>
14469 <register>
14470 <name>AFRH</name>
14471 <displayName>AFRH</displayName>
14472 <description>GPIO alternate function high
14473 register</description>
14474 <addressOffset>0x24</addressOffset>
14475 <size>0x20</size>
14476 <access>read-write</access>
14477 <resetValue>0x00000000</resetValue>
14478 <fields>
14479 <field>
14480 <name>AFRH15</name>
14481 <description>Alternate function selection for port x
14482 bit y (y = 8..15)</description>
14483 <bitOffset>28</bitOffset>
14484 <bitWidth>4</bitWidth>
14485 </field>
14486 <field>
14487 <name>AFRH14</name>
14488 <description>Alternate function selection for port x
14489 bit y (y = 8..15)</description>
14490 <bitOffset>24</bitOffset>
14491 <bitWidth>4</bitWidth>
14492 </field>
14493 <field>
14494 <name>AFRH13</name>
14495 <description>Alternate function selection for port x
14496 bit y (y = 8..15)</description>
14497 <bitOffset>20</bitOffset>
14498 <bitWidth>4</bitWidth>
14499 </field>
14500 <field>
14501 <name>AFRH12</name>
14502 <description>Alternate function selection for port x
14503 bit y (y = 8..15)</description>
14504 <bitOffset>16</bitOffset>
14505 <bitWidth>4</bitWidth>
14506 </field>
14507 <field>
14508 <name>AFRH11</name>
14509 <description>Alternate function selection for port x
14510 bit y (y = 8..15)</description>
14511 <bitOffset>12</bitOffset>
14512 <bitWidth>4</bitWidth>
14513 </field>
14514 <field>
14515 <name>AFRH10</name>
14516 <description>Alternate function selection for port x
14517 bit y (y = 8..15)</description>
14518 <bitOffset>8</bitOffset>
14519 <bitWidth>4</bitWidth>
14520 </field>
14521 <field>
14522 <name>AFRH9</name>
14523 <description>Alternate function selection for port x
14524 bit y (y = 8..15)</description>
14525 <bitOffset>4</bitOffset>
14526 <bitWidth>4</bitWidth>
14527 </field>
14528 <field>
14529 <name>AFRH8</name>
14530 <description>Alternate function selection for port x
14531 bit y (y = 8..15)</description>
14532 <bitOffset>0</bitOffset>
14533 <bitWidth>4</bitWidth>
14534 </field>
14535 </fields>
14536 </register>
14537 <register>
14538 <name>BRR</name>
14539 <displayName>BRR</displayName>
14540 <description>GPIO port bit reset register</description>
14541 <addressOffset>0x28</addressOffset>
14542 <size>0x20</size>
14543 <access>read-write</access>
14544 <resetValue>0x00000000</resetValue>
14545 <fields>
14546 <field>
14547 <name>BR0</name>
14548 <description>Port B Reset bit 0</description>
14549 <bitOffset>0</bitOffset>
14550 <bitWidth>1</bitWidth>
14551 </field>
14552 <field>
14553 <name>BR1</name>
14554 <description>Port B Reset bit 1</description>
14555 <bitOffset>1</bitOffset>
14556 <bitWidth>1</bitWidth>
14557 </field>
14558 <field>
14559 <name>BR2</name>
14560 <description>Port B Reset bit 2</description>
14561 <bitOffset>2</bitOffset>
14562 <bitWidth>1</bitWidth>
14563 </field>
14564 <field>
14565 <name>BR3</name>
14566 <description>Port B Reset bit 3</description>
14567 <bitOffset>3</bitOffset>
14568 <bitWidth>1</bitWidth>
14569 </field>
14570 <field>
14571 <name>BR4</name>
14572 <description>Port B Reset bit 4</description>
14573 <bitOffset>4</bitOffset>
14574 <bitWidth>1</bitWidth>
14575 </field>
14576 <field>
14577 <name>BR5</name>
14578 <description>Port B Reset bit 5</description>
14579 <bitOffset>5</bitOffset>
14580 <bitWidth>1</bitWidth>
14581 </field>
14582 <field>
14583 <name>BR6</name>
14584 <description>Port B Reset bit 6</description>
14585 <bitOffset>6</bitOffset>
14586 <bitWidth>1</bitWidth>
14587 </field>
14588 <field>
14589 <name>BR7</name>
14590 <description>Port B Reset bit 7</description>
14591 <bitOffset>7</bitOffset>
14592 <bitWidth>1</bitWidth>
14593 </field>
14594 <field>
14595 <name>BR8</name>
14596 <description>Port B Reset bit 8</description>
14597 <bitOffset>8</bitOffset>
14598 <bitWidth>1</bitWidth>
14599 </field>
14600 <field>
14601 <name>BR9</name>
14602 <description>Port B Reset bit 9</description>
14603 <bitOffset>9</bitOffset>
14604 <bitWidth>1</bitWidth>
14605 </field>
14606 <field>
14607 <name>BR10</name>
14608 <description>Port B Reset bit 10</description>
14609 <bitOffset>10</bitOffset>
14610 <bitWidth>1</bitWidth>
14611 </field>
14612 <field>
14613 <name>BR11</name>
14614 <description>Port B Reset bit 11</description>
14615 <bitOffset>11</bitOffset>
14616 <bitWidth>1</bitWidth>
14617 </field>
14618 <field>
14619 <name>BR12</name>
14620 <description>Port B Reset bit 12</description>
14621 <bitOffset>12</bitOffset>
14622 <bitWidth>1</bitWidth>
14623 </field>
14624 <field>
14625 <name>BR13</name>
14626 <description>Port B Reset bit 13</description>
14627 <bitOffset>13</bitOffset>
14628 <bitWidth>1</bitWidth>
14629 </field>
14630 <field>
14631 <name>BR14</name>
14632 <description>Port B Reset bit 14</description>
14633 <bitOffset>14</bitOffset>
14634 <bitWidth>1</bitWidth>
14635 </field>
14636 <field>
14637 <name>BR15</name>
14638 <description>Port B Reset bit 15</description>
14639 <bitOffset>15</bitOffset>
14640 <bitWidth>1</bitWidth>
14641 </field>
14642 </fields>
14643 </register>
14644 </registers>
14645 </peripheral>
14646 <peripheral>
14647 <name>GPIOA</name>
14648 <description>General-purpose I/Os</description>
14649 <groupName>GPIO</groupName>
14650 <baseAddress>0x40020000</baseAddress>
14651 <addressBlock>
14652 <offset>0x0</offset>
14653 <size>0x400</size>
14654 <usage>registers</usage>
14655 </addressBlock>
14656 <registers>
14657 <register>
14658 <name>MODER</name>
14659 <displayName>MODER</displayName>
14660 <description>GPIO port mode register</description>
14661 <addressOffset>0x0</addressOffset>
14662 <size>0x20</size>
14663 <access>read-write</access>
14664 <resetValue>0xA8000000</resetValue>
14665 <fields>
14666 <field>
14667 <name>MODER15</name>
14668 <description>Port x configuration bits (y =
14669 0..15)</description>
14670 <bitOffset>30</bitOffset>
14671 <bitWidth>2</bitWidth>
14672 </field>
14673 <field>
14674 <name>MODER14</name>
14675 <description>Port x configuration bits (y =
14676 0..15)</description>
14677 <bitOffset>28</bitOffset>
14678 <bitWidth>2</bitWidth>
14679 </field>
14680 <field>
14681 <name>MODER13</name>
14682 <description>Port x configuration bits (y =
14683 0..15)</description>
14684 <bitOffset>26</bitOffset>
14685 <bitWidth>2</bitWidth>
14686 </field>
14687 <field>
14688 <name>MODER12</name>
14689 <description>Port x configuration bits (y =
14690 0..15)</description>
14691 <bitOffset>24</bitOffset>
14692 <bitWidth>2</bitWidth>
14693 </field>
14694 <field>
14695 <name>MODER11</name>
14696 <description>Port x configuration bits (y =
14697 0..15)</description>
14698 <bitOffset>22</bitOffset>
14699 <bitWidth>2</bitWidth>
14700 </field>
14701 <field>
14702 <name>MODER10</name>
14703 <description>Port x configuration bits (y =
14704 0..15)</description>
14705 <bitOffset>20</bitOffset>
14706 <bitWidth>2</bitWidth>
14707 </field>
14708 <field>
14709 <name>MODER9</name>
14710 <description>Port x configuration bits (y =
14711 0..15)</description>
14712 <bitOffset>18</bitOffset>
14713 <bitWidth>2</bitWidth>
14714 </field>
14715 <field>
14716 <name>MODER8</name>
14717 <description>Port x configuration bits (y =
14718 0..15)</description>
14719 <bitOffset>16</bitOffset>
14720 <bitWidth>2</bitWidth>
14721 </field>
14722 <field>
14723 <name>MODER7</name>
14724 <description>Port x configuration bits (y =
14725 0..15)</description>
14726 <bitOffset>14</bitOffset>
14727 <bitWidth>2</bitWidth>
14728 </field>
14729 <field>
14730 <name>MODER6</name>
14731 <description>Port x configuration bits (y =
14732 0..15)</description>
14733 <bitOffset>12</bitOffset>
14734 <bitWidth>2</bitWidth>
14735 </field>
14736 <field>
14737 <name>MODER5</name>
14738 <description>Port x configuration bits (y =
14739 0..15)</description>
14740 <bitOffset>10</bitOffset>
14741 <bitWidth>2</bitWidth>
14742 </field>
14743 <field>
14744 <name>MODER4</name>
14745 <description>Port x configuration bits (y =
14746 0..15)</description>
14747 <bitOffset>8</bitOffset>
14748 <bitWidth>2</bitWidth>
14749 </field>
14750 <field>
14751 <name>MODER3</name>
14752 <description>Port x configuration bits (y =
14753 0..15)</description>
14754 <bitOffset>6</bitOffset>
14755 <bitWidth>2</bitWidth>
14756 </field>
14757 <field>
14758 <name>MODER2</name>
14759 <description>Port x configuration bits (y =
14760 0..15)</description>
14761 <bitOffset>4</bitOffset>
14762 <bitWidth>2</bitWidth>
14763 </field>
14764 <field>
14765 <name>MODER1</name>
14766 <description>Port x configuration bits (y =
14767 0..15)</description>
14768 <bitOffset>2</bitOffset>
14769 <bitWidth>2</bitWidth>
14770 </field>
14771 <field>
14772 <name>MODER0</name>
14773 <description>Port x configuration bits (y =
14774 0..15)</description>
14775 <bitOffset>0</bitOffset>
14776 <bitWidth>2</bitWidth>
14777 </field>
14778 </fields>
14779 </register>
14780 <register>
14781 <name>OTYPER</name>
14782 <displayName>OTYPER</displayName>
14783 <description>GPIO port output type register</description>
14784 <addressOffset>0x4</addressOffset>
14785 <size>0x20</size>
14786 <access>read-write</access>
14787 <resetValue>0x00000000</resetValue>
14788 <fields>
14789 <field>
14790 <name>OT15</name>
14791 <description>Port x configuration bits (y =
14792 0..15)</description>
14793 <bitOffset>15</bitOffset>
14794 <bitWidth>1</bitWidth>
14795 </field>
14796 <field>
14797 <name>OT14</name>
14798 <description>Port x configuration bits (y =
14799 0..15)</description>
14800 <bitOffset>14</bitOffset>
14801 <bitWidth>1</bitWidth>
14802 </field>
14803 <field>
14804 <name>OT13</name>
14805 <description>Port x configuration bits (y =
14806 0..15)</description>
14807 <bitOffset>13</bitOffset>
14808 <bitWidth>1</bitWidth>
14809 </field>
14810 <field>
14811 <name>OT12</name>
14812 <description>Port x configuration bits (y =
14813 0..15)</description>
14814 <bitOffset>12</bitOffset>
14815 <bitWidth>1</bitWidth>
14816 </field>
14817 <field>
14818 <name>OT11</name>
14819 <description>Port x configuration bits (y =
14820 0..15)</description>
14821 <bitOffset>11</bitOffset>
14822 <bitWidth>1</bitWidth>
14823 </field>
14824 <field>
14825 <name>OT10</name>
14826 <description>Port x configuration bits (y =
14827 0..15)</description>
14828 <bitOffset>10</bitOffset>
14829 <bitWidth>1</bitWidth>
14830 </field>
14831 <field>
14832 <name>OT9</name>
14833 <description>Port x configuration bits (y =
14834 0..15)</description>
14835 <bitOffset>9</bitOffset>
14836 <bitWidth>1</bitWidth>
14837 </field>
14838 <field>
14839 <name>OT8</name>
14840 <description>Port x configuration bits (y =
14841 0..15)</description>
14842 <bitOffset>8</bitOffset>
14843 <bitWidth>1</bitWidth>
14844 </field>
14845 <field>
14846 <name>OT7</name>
14847 <description>Port x configuration bits (y =
14848 0..15)</description>
14849 <bitOffset>7</bitOffset>
14850 <bitWidth>1</bitWidth>
14851 </field>
14852 <field>
14853 <name>OT6</name>
14854 <description>Port x configuration bits (y =
14855 0..15)</description>
14856 <bitOffset>6</bitOffset>
14857 <bitWidth>1</bitWidth>
14858 </field>
14859 <field>
14860 <name>OT5</name>
14861 <description>Port x configuration bits (y =
14862 0..15)</description>
14863 <bitOffset>5</bitOffset>
14864 <bitWidth>1</bitWidth>
14865 </field>
14866 <field>
14867 <name>OT4</name>
14868 <description>Port x configuration bits (y =
14869 0..15)</description>
14870 <bitOffset>4</bitOffset>
14871 <bitWidth>1</bitWidth>
14872 </field>
14873 <field>
14874 <name>OT3</name>
14875 <description>Port x configuration bits (y =
14876 0..15)</description>
14877 <bitOffset>3</bitOffset>
14878 <bitWidth>1</bitWidth>
14879 </field>
14880 <field>
14881 <name>OT2</name>
14882 <description>Port x configuration bits (y =
14883 0..15)</description>
14884 <bitOffset>2</bitOffset>
14885 <bitWidth>1</bitWidth>
14886 </field>
14887 <field>
14888 <name>OT1</name>
14889 <description>Port x configuration bits (y =
14890 0..15)</description>
14891 <bitOffset>1</bitOffset>
14892 <bitWidth>1</bitWidth>
14893 </field>
14894 <field>
14895 <name>OT0</name>
14896 <description>Port x configuration bits (y =
14897 0..15)</description>
14898 <bitOffset>0</bitOffset>
14899 <bitWidth>1</bitWidth>
14900 </field>
14901 </fields>
14902 </register>
14903 <register>
14904 <name>GPIOB_OSPEEDR</name>
14905 <displayName>GPIOB_OSPEEDR</displayName>
14906 <description>GPIO port output speed
14907 register</description>
14908 <addressOffset>0x8</addressOffset>
14909 <size>0x20</size>
14910 <access>read-write</access>
14911 <resetValue>0x00000000</resetValue>
14912 <fields>
14913 <field>
14914 <name>OSPEEDR15</name>
14915 <description>Port x configuration bits (y =
14916 0..15)</description>
14917 <bitOffset>30</bitOffset>
14918 <bitWidth>2</bitWidth>
14919 </field>
14920 <field>
14921 <name>OSPEEDR14</name>
14922 <description>Port x configuration bits (y =
14923 0..15)</description>
14924 <bitOffset>28</bitOffset>
14925 <bitWidth>2</bitWidth>
14926 </field>
14927 <field>
14928 <name>OSPEEDR13</name>
14929 <description>Port x configuration bits (y =
14930 0..15)</description>
14931 <bitOffset>26</bitOffset>
14932 <bitWidth>2</bitWidth>
14933 </field>
14934 <field>
14935 <name>OSPEEDR12</name>
14936 <description>Port x configuration bits (y =
14937 0..15)</description>
14938 <bitOffset>24</bitOffset>
14939 <bitWidth>2</bitWidth>
14940 </field>
14941 <field>
14942 <name>OSPEEDR11</name>
14943 <description>Port x configuration bits (y =
14944 0..15)</description>
14945 <bitOffset>22</bitOffset>
14946 <bitWidth>2</bitWidth>
14947 </field>
14948 <field>
14949 <name>OSPEEDR10</name>
14950 <description>Port x configuration bits (y =
14951 0..15)</description>
14952 <bitOffset>20</bitOffset>
14953 <bitWidth>2</bitWidth>
14954 </field>
14955 <field>
14956 <name>OSPEEDR9</name>
14957 <description>Port x configuration bits (y =
14958 0..15)</description>
14959 <bitOffset>18</bitOffset>
14960 <bitWidth>2</bitWidth>
14961 </field>
14962 <field>
14963 <name>OSPEEDR8</name>
14964 <description>Port x configuration bits (y =
14965 0..15)</description>
14966 <bitOffset>16</bitOffset>
14967 <bitWidth>2</bitWidth>
14968 </field>
14969 <field>
14970 <name>OSPEEDR7</name>
14971 <description>Port x configuration bits (y =
14972 0..15)</description>
14973 <bitOffset>14</bitOffset>
14974 <bitWidth>2</bitWidth>
14975 </field>
14976 <field>
14977 <name>OSPEEDR6</name>
14978 <description>Port x configuration bits (y =
14979 0..15)</description>
14980 <bitOffset>12</bitOffset>
14981 <bitWidth>2</bitWidth>
14982 </field>
14983 <field>
14984 <name>OSPEEDR5</name>
14985 <description>Port x configuration bits (y =
14986 0..15)</description>
14987 <bitOffset>10</bitOffset>
14988 <bitWidth>2</bitWidth>
14989 </field>
14990 <field>
14991 <name>OSPEEDR4</name>
14992 <description>Port x configuration bits (y =
14993 0..15)</description>
14994 <bitOffset>8</bitOffset>
14995 <bitWidth>2</bitWidth>
14996 </field>
14997 <field>
14998 <name>OSPEEDR3</name>
14999 <description>Port x configuration bits (y =
15000 0..15)</description>
15001 <bitOffset>6</bitOffset>
15002 <bitWidth>2</bitWidth>
15003 </field>
15004 <field>
15005 <name>OSPEEDR2</name>
15006 <description>Port x configuration bits (y =
15007 0..15)</description>
15008 <bitOffset>4</bitOffset>
15009 <bitWidth>2</bitWidth>
15010 </field>
15011 <field>
15012 <name>OSPEEDR1</name>
15013 <description>Port x configuration bits (y =
15014 0..15)</description>
15015 <bitOffset>2</bitOffset>
15016 <bitWidth>2</bitWidth>
15017 </field>
15018 <field>
15019 <name>OSPEEDR0</name>
15020 <description>Port x configuration bits (y =
15021 0..15)</description>
15022 <bitOffset>0</bitOffset>
15023 <bitWidth>2</bitWidth>
15024 </field>
15025 </fields>
15026 </register>
15027 <register>
15028 <name>PUPDR</name>
15029 <displayName>PUPDR</displayName>
15030 <description>GPIO port pull-up/pull-down
15031 register</description>
15032 <addressOffset>0xC</addressOffset>
15033 <size>0x20</size>
15034 <access>read-write</access>
15035 <resetValue>0x64000000</resetValue>
15036 <fields>
15037 <field>
15038 <name>PUPDR15</name>
15039 <description>Port x configuration bits (y =
15040 0..15)</description>
15041 <bitOffset>30</bitOffset>
15042 <bitWidth>2</bitWidth>
15043 </field>
15044 <field>
15045 <name>PUPDR14</name>
15046 <description>Port x configuration bits (y =
15047 0..15)</description>
15048 <bitOffset>28</bitOffset>
15049 <bitWidth>2</bitWidth>
15050 </field>
15051 <field>
15052 <name>PUPDR13</name>
15053 <description>Port x configuration bits (y =
15054 0..15)</description>
15055 <bitOffset>26</bitOffset>
15056 <bitWidth>2</bitWidth>
15057 </field>
15058 <field>
15059 <name>PUPDR12</name>
15060 <description>Port x configuration bits (y =
15061 0..15)</description>
15062 <bitOffset>24</bitOffset>
15063 <bitWidth>2</bitWidth>
15064 </field>
15065 <field>
15066 <name>PUPDR11</name>
15067 <description>Port x configuration bits (y =
15068 0..15)</description>
15069 <bitOffset>22</bitOffset>
15070 <bitWidth>2</bitWidth>
15071 </field>
15072 <field>
15073 <name>PUPDR10</name>
15074 <description>Port x configuration bits (y =
15075 0..15)</description>
15076 <bitOffset>20</bitOffset>
15077 <bitWidth>2</bitWidth>
15078 </field>
15079 <field>
15080 <name>PUPDR9</name>
15081 <description>Port x configuration bits (y =
15082 0..15)</description>
15083 <bitOffset>18</bitOffset>
15084 <bitWidth>2</bitWidth>
15085 </field>
15086 <field>
15087 <name>PUPDR8</name>
15088 <description>Port x configuration bits (y =
15089 0..15)</description>
15090 <bitOffset>16</bitOffset>
15091 <bitWidth>2</bitWidth>
15092 </field>
15093 <field>
15094 <name>PUPDR7</name>
15095 <description>Port x configuration bits (y =
15096 0..15)</description>
15097 <bitOffset>14</bitOffset>
15098 <bitWidth>2</bitWidth>
15099 </field>
15100 <field>
15101 <name>PUPDR6</name>
15102 <description>Port x configuration bits (y =
15103 0..15)</description>
15104 <bitOffset>12</bitOffset>
15105 <bitWidth>2</bitWidth>
15106 </field>
15107 <field>
15108 <name>PUPDR5</name>
15109 <description>Port x configuration bits (y =
15110 0..15)</description>
15111 <bitOffset>10</bitOffset>
15112 <bitWidth>2</bitWidth>
15113 </field>
15114 <field>
15115 <name>PUPDR4</name>
15116 <description>Port x configuration bits (y =
15117 0..15)</description>
15118 <bitOffset>8</bitOffset>
15119 <bitWidth>2</bitWidth>
15120 </field>
15121 <field>
15122 <name>PUPDR3</name>
15123 <description>Port x configuration bits (y =
15124 0..15)</description>
15125 <bitOffset>6</bitOffset>
15126 <bitWidth>2</bitWidth>
15127 </field>
15128 <field>
15129 <name>PUPDR2</name>
15130 <description>Port x configuration bits (y =
15131 0..15)</description>
15132 <bitOffset>4</bitOffset>
15133 <bitWidth>2</bitWidth>
15134 </field>
15135 <field>
15136 <name>PUPDR1</name>
15137 <description>Port x configuration bits (y =
15138 0..15)</description>
15139 <bitOffset>2</bitOffset>
15140 <bitWidth>2</bitWidth>
15141 </field>
15142 <field>
15143 <name>PUPDR0</name>
15144 <description>Port x configuration bits (y =
15145 0..15)</description>
15146 <bitOffset>0</bitOffset>
15147 <bitWidth>2</bitWidth>
15148 </field>
15149 </fields>
15150 </register>
15151 <register>
15152 <name>IDR</name>
15153 <displayName>IDR</displayName>
15154 <description>GPIO port input data register</description>
15155 <addressOffset>0x10</addressOffset>
15156 <size>0x20</size>
15157 <access>read-only</access>
15158 <resetValue>0x00000000</resetValue>
15159 <fields>
15160 <field>
15161 <name>IDR15</name>
15162 <description>Port input data (y =
15163 0..15)</description>
15164 <bitOffset>15</bitOffset>
15165 <bitWidth>1</bitWidth>
15166 </field>
15167 <field>
15168 <name>IDR14</name>
15169 <description>Port input data (y =
15170 0..15)</description>
15171 <bitOffset>14</bitOffset>
15172 <bitWidth>1</bitWidth>
15173 </field>
15174 <field>
15175 <name>IDR13</name>
15176 <description>Port input data (y =
15177 0..15)</description>
15178 <bitOffset>13</bitOffset>
15179 <bitWidth>1</bitWidth>
15180 </field>
15181 <field>
15182 <name>IDR12</name>
15183 <description>Port input data (y =
15184 0..15)</description>
15185 <bitOffset>12</bitOffset>
15186 <bitWidth>1</bitWidth>
15187 </field>
15188 <field>
15189 <name>IDR11</name>
15190 <description>Port input data (y =
15191 0..15)</description>
15192 <bitOffset>11</bitOffset>
15193 <bitWidth>1</bitWidth>
15194 </field>
15195 <field>
15196 <name>IDR10</name>
15197 <description>Port input data (y =
15198 0..15)</description>
15199 <bitOffset>10</bitOffset>
15200 <bitWidth>1</bitWidth>
15201 </field>
15202 <field>
15203 <name>IDR9</name>
15204 <description>Port input data (y =
15205 0..15)</description>
15206 <bitOffset>9</bitOffset>
15207 <bitWidth>1</bitWidth>
15208 </field>
15209 <field>
15210 <name>IDR8</name>
15211 <description>Port input data (y =
15212 0..15)</description>
15213 <bitOffset>8</bitOffset>
15214 <bitWidth>1</bitWidth>
15215 </field>
15216 <field>
15217 <name>IDR7</name>
15218 <description>Port input data (y =
15219 0..15)</description>
15220 <bitOffset>7</bitOffset>
15221 <bitWidth>1</bitWidth>
15222 </field>
15223 <field>
15224 <name>IDR6</name>
15225 <description>Port input data (y =
15226 0..15)</description>
15227 <bitOffset>6</bitOffset>
15228 <bitWidth>1</bitWidth>
15229 </field>
15230 <field>
15231 <name>IDR5</name>
15232 <description>Port input data (y =
15233 0..15)</description>
15234 <bitOffset>5</bitOffset>
15235 <bitWidth>1</bitWidth>
15236 </field>
15237 <field>
15238 <name>IDR4</name>
15239 <description>Port input data (y =
15240 0..15)</description>
15241 <bitOffset>4</bitOffset>
15242 <bitWidth>1</bitWidth>
15243 </field>
15244 <field>
15245 <name>IDR3</name>
15246 <description>Port input data (y =
15247 0..15)</description>
15248 <bitOffset>3</bitOffset>
15249 <bitWidth>1</bitWidth>
15250 </field>
15251 <field>
15252 <name>IDR2</name>
15253 <description>Port input data (y =
15254 0..15)</description>
15255 <bitOffset>2</bitOffset>
15256 <bitWidth>1</bitWidth>
15257 </field>
15258 <field>
15259 <name>IDR1</name>
15260 <description>Port input data (y =
15261 0..15)</description>
15262 <bitOffset>1</bitOffset>
15263 <bitWidth>1</bitWidth>
15264 </field>
15265 <field>
15266 <name>IDR0</name>
15267 <description>Port input data (y =
15268 0..15)</description>
15269 <bitOffset>0</bitOffset>
15270 <bitWidth>1</bitWidth>
15271 </field>
15272 </fields>
15273 </register>
15274 <register>
15275 <name>ODR</name>
15276 <displayName>ODR</displayName>
15277 <description>GPIO port output data register</description>
15278 <addressOffset>0x14</addressOffset>
15279 <size>0x20</size>
15280 <access>read-write</access>
15281 <resetValue>0x00000000</resetValue>
15282 <fields>
15283 <field>
15284 <name>ODR15</name>
15285 <description>Port output data (y =
15286 0..15)</description>
15287 <bitOffset>15</bitOffset>
15288 <bitWidth>1</bitWidth>
15289 </field>
15290 <field>
15291 <name>ODR14</name>
15292 <description>Port output data (y =
15293 0..15)</description>
15294 <bitOffset>14</bitOffset>
15295 <bitWidth>1</bitWidth>
15296 </field>
15297 <field>
15298 <name>ODR13</name>
15299 <description>Port output data (y =
15300 0..15)</description>
15301 <bitOffset>13</bitOffset>
15302 <bitWidth>1</bitWidth>
15303 </field>
15304 <field>
15305 <name>ODR12</name>
15306 <description>Port output data (y =
15307 0..15)</description>
15308 <bitOffset>12</bitOffset>
15309 <bitWidth>1</bitWidth>
15310 </field>
15311 <field>
15312 <name>ODR11</name>
15313 <description>Port output data (y =
15314 0..15)</description>
15315 <bitOffset>11</bitOffset>
15316 <bitWidth>1</bitWidth>
15317 </field>
15318 <field>
15319 <name>ODR10</name>
15320 <description>Port output data (y =
15321 0..15)</description>
15322 <bitOffset>10</bitOffset>
15323 <bitWidth>1</bitWidth>
15324 </field>
15325 <field>
15326 <name>ODR9</name>
15327 <description>Port output data (y =
15328 0..15)</description>
15329 <bitOffset>9</bitOffset>
15330 <bitWidth>1</bitWidth>
15331 </field>
15332 <field>
15333 <name>ODR8</name>
15334 <description>Port output data (y =
15335 0..15)</description>
15336 <bitOffset>8</bitOffset>
15337 <bitWidth>1</bitWidth>
15338 </field>
15339 <field>
15340 <name>ODR7</name>
15341 <description>Port output data (y =
15342 0..15)</description>
15343 <bitOffset>7</bitOffset>
15344 <bitWidth>1</bitWidth>
15345 </field>
15346 <field>
15347 <name>ODR6</name>
15348 <description>Port output data (y =
15349 0..15)</description>
15350 <bitOffset>6</bitOffset>
15351 <bitWidth>1</bitWidth>
15352 </field>
15353 <field>
15354 <name>ODR5</name>
15355 <description>Port output data (y =
15356 0..15)</description>
15357 <bitOffset>5</bitOffset>
15358 <bitWidth>1</bitWidth>
15359 </field>
15360 <field>
15361 <name>ODR4</name>
15362 <description>Port output data (y =
15363 0..15)</description>
15364 <bitOffset>4</bitOffset>
15365 <bitWidth>1</bitWidth>
15366 </field>
15367 <field>
15368 <name>ODR3</name>
15369 <description>Port output data (y =
15370 0..15)</description>
15371 <bitOffset>3</bitOffset>
15372 <bitWidth>1</bitWidth>
15373 </field>
15374 <field>
15375 <name>ODR2</name>
15376 <description>Port output data (y =
15377 0..15)</description>
15378 <bitOffset>2</bitOffset>
15379 <bitWidth>1</bitWidth>
15380 </field>
15381 <field>
15382 <name>ODR1</name>
15383 <description>Port output data (y =
15384 0..15)</description>
15385 <bitOffset>1</bitOffset>
15386 <bitWidth>1</bitWidth>
15387 </field>
15388 <field>
15389 <name>ODR0</name>
15390 <description>Port output data (y =
15391 0..15)</description>
15392 <bitOffset>0</bitOffset>
15393 <bitWidth>1</bitWidth>
15394 </field>
15395 </fields>
15396 </register>
15397 <register>
15398 <name>BSRR</name>
15399 <displayName>BSRR</displayName>
15400 <description>GPIO port bit set/reset
15401 register</description>
15402 <addressOffset>0x18</addressOffset>
15403 <size>0x20</size>
15404 <access>write-only</access>
15405 <resetValue>0x00000000</resetValue>
15406 <fields>
15407 <field>
15408 <name>BR15</name>
15409 <description>Port x reset bit y (y =
15410 0..15)</description>
15411 <bitOffset>31</bitOffset>
15412 <bitWidth>1</bitWidth>
15413 </field>
15414 <field>
15415 <name>BR14</name>
15416 <description>Port x reset bit y (y =
15417 0..15)</description>
15418 <bitOffset>30</bitOffset>
15419 <bitWidth>1</bitWidth>
15420 </field>
15421 <field>
15422 <name>BR13</name>
15423 <description>Port x reset bit y (y =
15424 0..15)</description>
15425 <bitOffset>29</bitOffset>
15426 <bitWidth>1</bitWidth>
15427 </field>
15428 <field>
15429 <name>BR12</name>
15430 <description>Port x reset bit y (y =
15431 0..15)</description>
15432 <bitOffset>28</bitOffset>
15433 <bitWidth>1</bitWidth>
15434 </field>
15435 <field>
15436 <name>BR11</name>
15437 <description>Port x reset bit y (y =
15438 0..15)</description>
15439 <bitOffset>27</bitOffset>
15440 <bitWidth>1</bitWidth>
15441 </field>
15442 <field>
15443 <name>BR10</name>
15444 <description>Port x reset bit y (y =
15445 0..15)</description>
15446 <bitOffset>26</bitOffset>
15447 <bitWidth>1</bitWidth>
15448 </field>
15449 <field>
15450 <name>BR9</name>
15451 <description>Port x reset bit y (y =
15452 0..15)</description>
15453 <bitOffset>25</bitOffset>
15454 <bitWidth>1</bitWidth>
15455 </field>
15456 <field>
15457 <name>BR8</name>
15458 <description>Port x reset bit y (y =
15459 0..15)</description>
15460 <bitOffset>24</bitOffset>
15461 <bitWidth>1</bitWidth>
15462 </field>
15463 <field>
15464 <name>BR7</name>
15465 <description>Port x reset bit y (y =
15466 0..15)</description>
15467 <bitOffset>23</bitOffset>
15468 <bitWidth>1</bitWidth>
15469 </field>
15470 <field>
15471 <name>BR6</name>
15472 <description>Port x reset bit y (y =
15473 0..15)</description>
15474 <bitOffset>22</bitOffset>
15475 <bitWidth>1</bitWidth>
15476 </field>
15477 <field>
15478 <name>BR5</name>
15479 <description>Port x reset bit y (y =
15480 0..15)</description>
15481 <bitOffset>21</bitOffset>
15482 <bitWidth>1</bitWidth>
15483 </field>
15484 <field>
15485 <name>BR4</name>
15486 <description>Port x reset bit y (y =
15487 0..15)</description>
15488 <bitOffset>20</bitOffset>
15489 <bitWidth>1</bitWidth>
15490 </field>
15491 <field>
15492 <name>BR3</name>
15493 <description>Port x reset bit y (y =
15494 0..15)</description>
15495 <bitOffset>19</bitOffset>
15496 <bitWidth>1</bitWidth>
15497 </field>
15498 <field>
15499 <name>BR2</name>
15500 <description>Port x reset bit y (y =
15501 0..15)</description>
15502 <bitOffset>18</bitOffset>
15503 <bitWidth>1</bitWidth>
15504 </field>
15505 <field>
15506 <name>BR1</name>
15507 <description>Port x reset bit y (y =
15508 0..15)</description>
15509 <bitOffset>17</bitOffset>
15510 <bitWidth>1</bitWidth>
15511 </field>
15512 <field>
15513 <name>BR0</name>
15514 <description>Port x set bit y (y=
15515 0..15)</description>
15516 <bitOffset>16</bitOffset>
15517 <bitWidth>1</bitWidth>
15518 </field>
15519 <field>
15520 <name>BS15</name>
15521 <description>Port x set bit y (y=
15522 0..15)</description>
15523 <bitOffset>15</bitOffset>
15524 <bitWidth>1</bitWidth>
15525 </field>
15526 <field>
15527 <name>BS14</name>
15528 <description>Port x set bit y (y=
15529 0..15)</description>
15530 <bitOffset>14</bitOffset>
15531 <bitWidth>1</bitWidth>
15532 </field>
15533 <field>
15534 <name>BS13</name>
15535 <description>Port x set bit y (y=
15536 0..15)</description>
15537 <bitOffset>13</bitOffset>
15538 <bitWidth>1</bitWidth>
15539 </field>
15540 <field>
15541 <name>BS12</name>
15542 <description>Port x set bit y (y=
15543 0..15)</description>
15544 <bitOffset>12</bitOffset>
15545 <bitWidth>1</bitWidth>
15546 </field>
15547 <field>
15548 <name>BS11</name>
15549 <description>Port x set bit y (y=
15550 0..15)</description>
15551 <bitOffset>11</bitOffset>
15552 <bitWidth>1</bitWidth>
15553 </field>
15554 <field>
15555 <name>BS10</name>
15556 <description>Port x set bit y (y=
15557 0..15)</description>
15558 <bitOffset>10</bitOffset>
15559 <bitWidth>1</bitWidth>
15560 </field>
15561 <field>
15562 <name>BS9</name>
15563 <description>Port x set bit y (y=
15564 0..15)</description>
15565 <bitOffset>9</bitOffset>
15566 <bitWidth>1</bitWidth>
15567 </field>
15568 <field>
15569 <name>BS8</name>
15570 <description>Port x set bit y (y=
15571 0..15)</description>
15572 <bitOffset>8</bitOffset>
15573 <bitWidth>1</bitWidth>
15574 </field>
15575 <field>
15576 <name>BS7</name>
15577 <description>Port x set bit y (y=
15578 0..15)</description>
15579 <bitOffset>7</bitOffset>
15580 <bitWidth>1</bitWidth>
15581 </field>
15582 <field>
15583 <name>BS6</name>
15584 <description>Port x set bit y (y=
15585 0..15)</description>
15586 <bitOffset>6</bitOffset>
15587 <bitWidth>1</bitWidth>
15588 </field>
15589 <field>
15590 <name>BS5</name>
15591 <description>Port x set bit y (y=
15592 0..15)</description>
15593 <bitOffset>5</bitOffset>
15594 <bitWidth>1</bitWidth>
15595 </field>
15596 <field>
15597 <name>BS4</name>
15598 <description>Port x set bit y (y=
15599 0..15)</description>
15600 <bitOffset>4</bitOffset>
15601 <bitWidth>1</bitWidth>
15602 </field>
15603 <field>
15604 <name>BS3</name>
15605 <description>Port x set bit y (y=
15606 0..15)</description>
15607 <bitOffset>3</bitOffset>
15608 <bitWidth>1</bitWidth>
15609 </field>
15610 <field>
15611 <name>BS2</name>
15612 <description>Port x set bit y (y=
15613 0..15)</description>
15614 <bitOffset>2</bitOffset>
15615 <bitWidth>1</bitWidth>
15616 </field>
15617 <field>
15618 <name>BS1</name>
15619 <description>Port x set bit y (y=
15620 0..15)</description>
15621 <bitOffset>1</bitOffset>
15622 <bitWidth>1</bitWidth>
15623 </field>
15624 <field>
15625 <name>BS0</name>
15626 <description>Port x set bit y (y=
15627 0..15)</description>
15628 <bitOffset>0</bitOffset>
15629 <bitWidth>1</bitWidth>
15630 </field>
15631 </fields>
15632 </register>
15633 <register>
15634 <name>LCKR</name>
15635 <displayName>LCKR</displayName>
15636 <description>GPIO port configuration lock
15637 register</description>
15638 <addressOffset>0x1C</addressOffset>
15639 <size>0x20</size>
15640 <access>read-write</access>
15641 <resetValue>0x00000000</resetValue>
15642 <fields>
15643 <field>
15644 <name>LCKK</name>
15645 <description>Port x lock bit y (y=
15646 0..15)</description>
15647 <bitOffset>16</bitOffset>
15648 <bitWidth>1</bitWidth>
15649 </field>
15650 <field>
15651 <name>LCK15</name>
15652 <description>Port x lock bit y (y=
15653 0..15)</description>
15654 <bitOffset>15</bitOffset>
15655 <bitWidth>1</bitWidth>
15656 </field>
15657 <field>
15658 <name>LCK14</name>
15659 <description>Port x lock bit y (y=
15660 0..15)</description>
15661 <bitOffset>14</bitOffset>
15662 <bitWidth>1</bitWidth>
15663 </field>
15664 <field>
15665 <name>LCK13</name>
15666 <description>Port x lock bit y (y=
15667 0..15)</description>
15668 <bitOffset>13</bitOffset>
15669 <bitWidth>1</bitWidth>
15670 </field>
15671 <field>
15672 <name>LCK12</name>
15673 <description>Port x lock bit y (y=
15674 0..15)</description>
15675 <bitOffset>12</bitOffset>
15676 <bitWidth>1</bitWidth>
15677 </field>
15678 <field>
15679 <name>LCK11</name>
15680 <description>Port x lock bit y (y=
15681 0..15)</description>
15682 <bitOffset>11</bitOffset>
15683 <bitWidth>1</bitWidth>
15684 </field>
15685 <field>
15686 <name>LCK10</name>
15687 <description>Port x lock bit y (y=
15688 0..15)</description>
15689 <bitOffset>10</bitOffset>
15690 <bitWidth>1</bitWidth>
15691 </field>
15692 <field>
15693 <name>LCK9</name>
15694 <description>Port x lock bit y (y=
15695 0..15)</description>
15696 <bitOffset>9</bitOffset>
15697 <bitWidth>1</bitWidth>
15698 </field>
15699 <field>
15700 <name>LCK8</name>
15701 <description>Port x lock bit y (y=
15702 0..15)</description>
15703 <bitOffset>8</bitOffset>
15704 <bitWidth>1</bitWidth>
15705 </field>
15706 <field>
15707 <name>LCK7</name>
15708 <description>Port x lock bit y (y=
15709 0..15)</description>
15710 <bitOffset>7</bitOffset>
15711 <bitWidth>1</bitWidth>
15712 </field>
15713 <field>
15714 <name>LCK6</name>
15715 <description>Port x lock bit y (y=
15716 0..15)</description>
15717 <bitOffset>6</bitOffset>
15718 <bitWidth>1</bitWidth>
15719 </field>
15720 <field>
15721 <name>LCK5</name>
15722 <description>Port x lock bit y (y=
15723 0..15)</description>
15724 <bitOffset>5</bitOffset>
15725 <bitWidth>1</bitWidth>
15726 </field>
15727 <field>
15728 <name>LCK4</name>
15729 <description>Port x lock bit y (y=
15730 0..15)</description>
15731 <bitOffset>4</bitOffset>
15732 <bitWidth>1</bitWidth>
15733 </field>
15734 <field>
15735 <name>LCK3</name>
15736 <description>Port x lock bit y (y=
15737 0..15)</description>
15738 <bitOffset>3</bitOffset>
15739 <bitWidth>1</bitWidth>
15740 </field>
15741 <field>
15742 <name>LCK2</name>
15743 <description>Port x lock bit y (y=
15744 0..15)</description>
15745 <bitOffset>2</bitOffset>
15746 <bitWidth>1</bitWidth>
15747 </field>
15748 <field>
15749 <name>LCK1</name>
15750 <description>Port x lock bit y (y=
15751 0..15)</description>
15752 <bitOffset>1</bitOffset>
15753 <bitWidth>1</bitWidth>
15754 </field>
15755 <field>
15756 <name>LCK0</name>
15757 <description>Port x lock bit y (y=
15758 0..15)</description>
15759 <bitOffset>0</bitOffset>
15760 <bitWidth>1</bitWidth>
15761 </field>
15762 </fields>
15763 </register>
15764 <register>
15765 <name>AFRL</name>
15766 <displayName>AFRL</displayName>
15767 <description>GPIO alternate function low
15768 register</description>
15769 <addressOffset>0x20</addressOffset>
15770 <size>0x20</size>
15771 <access>read-write</access>
15772 <resetValue>0x00000000</resetValue>
15773 <fields>
15774 <field>
15775 <name>AFRL7</name>
15776 <description>Alternate function selection for port x
15777 bit y (y = 0..7)</description>
15778 <bitOffset>28</bitOffset>
15779 <bitWidth>4</bitWidth>
15780 </field>
15781 <field>
15782 <name>AFRL6</name>
15783 <description>Alternate function selection for port x
15784 bit y (y = 0..7)</description>
15785 <bitOffset>24</bitOffset>
15786 <bitWidth>4</bitWidth>
15787 </field>
15788 <field>
15789 <name>AFRL5</name>
15790 <description>Alternate function selection for port x
15791 bit y (y = 0..7)</description>
15792 <bitOffset>20</bitOffset>
15793 <bitWidth>4</bitWidth>
15794 </field>
15795 <field>
15796 <name>AFRL4</name>
15797 <description>Alternate function selection for port x
15798 bit y (y = 0..7)</description>
15799 <bitOffset>16</bitOffset>
15800 <bitWidth>4</bitWidth>
15801 </field>
15802 <field>
15803 <name>AFRL3</name>
15804 <description>Alternate function selection for port x
15805 bit y (y = 0..7)</description>
15806 <bitOffset>12</bitOffset>
15807 <bitWidth>4</bitWidth>
15808 </field>
15809 <field>
15810 <name>AFRL2</name>
15811 <description>Alternate function selection for port x
15812 bit y (y = 0..7)</description>
15813 <bitOffset>8</bitOffset>
15814 <bitWidth>4</bitWidth>
15815 </field>
15816 <field>
15817 <name>AFRL1</name>
15818 <description>Alternate function selection for port x
15819 bit y (y = 0..7)</description>
15820 <bitOffset>4</bitOffset>
15821 <bitWidth>4</bitWidth>
15822 </field>
15823 <field>
15824 <name>AFRL0</name>
15825 <description>Alternate function selection for port x
15826 bit y (y = 0..7)</description>
15827 <bitOffset>0</bitOffset>
15828 <bitWidth>4</bitWidth>
15829 </field>
15830 </fields>
15831 </register>
15832 <register>
15833 <name>AFRH</name>
15834 <displayName>AFRH</displayName>
15835 <description>GPIO alternate function high
15836 register</description>
15837 <addressOffset>0x24</addressOffset>
15838 <size>0x20</size>
15839 <access>read-write</access>
15840 <resetValue>0x00000000</resetValue>
15841 <fields>
15842 <field>
15843 <name>AFRH15</name>
15844 <description>Alternate function selection for port x
15845 bit y (y = 8..15)</description>
15846 <bitOffset>28</bitOffset>
15847 <bitWidth>4</bitWidth>
15848 </field>
15849 <field>
15850 <name>AFRH14</name>
15851 <description>Alternate function selection for port x
15852 bit y (y = 8..15)</description>
15853 <bitOffset>24</bitOffset>
15854 <bitWidth>4</bitWidth>
15855 </field>
15856 <field>
15857 <name>AFRH13</name>
15858 <description>Alternate function selection for port x
15859 bit y (y = 8..15)</description>
15860 <bitOffset>20</bitOffset>
15861 <bitWidth>4</bitWidth>
15862 </field>
15863 <field>
15864 <name>AFRH12</name>
15865 <description>Alternate function selection for port x
15866 bit y (y = 8..15)</description>
15867 <bitOffset>16</bitOffset>
15868 <bitWidth>4</bitWidth>
15869 </field>
15870 <field>
15871 <name>AFRH11</name>
15872 <description>Alternate function selection for port x
15873 bit y (y = 8..15)</description>
15874 <bitOffset>12</bitOffset>
15875 <bitWidth>4</bitWidth>
15876 </field>
15877 <field>
15878 <name>AFRH10</name>
15879 <description>Alternate function selection for port x
15880 bit y (y = 8..15)</description>
15881 <bitOffset>8</bitOffset>
15882 <bitWidth>4</bitWidth>
15883 </field>
15884 <field>
15885 <name>AFRH9</name>
15886 <description>Alternate function selection for port x
15887 bit y (y = 8..15)</description>
15888 <bitOffset>4</bitOffset>
15889 <bitWidth>4</bitWidth>
15890 </field>
15891 <field>
15892 <name>AFRH8</name>
15893 <description>Alternate function selection for port x
15894 bit y (y = 8..15)</description>
15895 <bitOffset>0</bitOffset>
15896 <bitWidth>4</bitWidth>
15897 </field>
15898 </fields>
15899 </register>
15900 <register>
15901 <name>BRR</name>
15902 <displayName>BRR</displayName>
15903 <description>GPIO port bit reset register</description>
15904 <addressOffset>0x28</addressOffset>
15905 <size>0x20</size>
15906 <access>read-write</access>
15907 <resetValue>0x00000000</resetValue>
15908 <fields>
15909 <field>
15910 <name>BR0</name>
15911 <description>Port A Reset bit 0</description>
15912 <bitOffset>0</bitOffset>
15913 <bitWidth>1</bitWidth>
15914 </field>
15915 <field>
15916 <name>BR1</name>
15917 <description>Port A Reset bit 1</description>
15918 <bitOffset>1</bitOffset>
15919 <bitWidth>1</bitWidth>
15920 </field>
15921 <field>
15922 <name>BR2</name>
15923 <description>Port A Reset bit 2</description>
15924 <bitOffset>2</bitOffset>
15925 <bitWidth>1</bitWidth>
15926 </field>
15927 <field>
15928 <name>BR3</name>
15929 <description>Port A Reset bit 3</description>
15930 <bitOffset>3</bitOffset>
15931 <bitWidth>1</bitWidth>
15932 </field>
15933 <field>
15934 <name>BR4</name>
15935 <description>Port A Reset bit 4</description>
15936 <bitOffset>4</bitOffset>
15937 <bitWidth>1</bitWidth>
15938 </field>
15939 <field>
15940 <name>BR5</name>
15941 <description>Port A Reset bit 5</description>
15942 <bitOffset>5</bitOffset>
15943 <bitWidth>1</bitWidth>
15944 </field>
15945 <field>
15946 <name>BR6</name>
15947 <description>Port A Reset bit 6</description>
15948 <bitOffset>6</bitOffset>
15949 <bitWidth>1</bitWidth>
15950 </field>
15951 <field>
15952 <name>BR7</name>
15953 <description>Port A Reset bit 7</description>
15954 <bitOffset>7</bitOffset>
15955 <bitWidth>1</bitWidth>
15956 </field>
15957 <field>
15958 <name>BR8</name>
15959 <description>Port A Reset bit 8</description>
15960 <bitOffset>8</bitOffset>
15961 <bitWidth>1</bitWidth>
15962 </field>
15963 <field>
15964 <name>BR9</name>
15965 <description>Port A Reset bit 9</description>
15966 <bitOffset>9</bitOffset>
15967 <bitWidth>1</bitWidth>
15968 </field>
15969 <field>
15970 <name>BR10</name>
15971 <description>Port A Reset bit 10</description>
15972 <bitOffset>10</bitOffset>
15973 <bitWidth>1</bitWidth>
15974 </field>
15975 <field>
15976 <name>BR11</name>
15977 <description>Port A Reset bit 11</description>
15978 <bitOffset>11</bitOffset>
15979 <bitWidth>1</bitWidth>
15980 </field>
15981 <field>
15982 <name>BR12</name>
15983 <description>Port A Reset bit 12</description>
15984 <bitOffset>12</bitOffset>
15985 <bitWidth>1</bitWidth>
15986 </field>
15987 <field>
15988 <name>BR13</name>
15989 <description>Port A Reset bit 13</description>
15990 <bitOffset>13</bitOffset>
15991 <bitWidth>1</bitWidth>
15992 </field>
15993 <field>
15994 <name>BR14</name>
15995 <description>Port A Reset bit 14</description>
15996 <bitOffset>14</bitOffset>
15997 <bitWidth>1</bitWidth>
15998 </field>
15999 <field>
16000 <name>BR15</name>
16001 <description>Port A Reset bit 15</description>
16002 <bitOffset>15</bitOffset>
16003 <bitWidth>1</bitWidth>
16004 </field>
16005 </fields>
16006 </register>
16007 </registers>
16008 </peripheral>
16009 <peripheral>
16010 <name>SYSCFG</name>
16011 <description>System configuration controller</description>
16012 <groupName>SYSCFG</groupName>
16013 <baseAddress>0x40013800</baseAddress>
16014 <addressBlock>
16015 <offset>0x0</offset>
16016 <size>0x400</size>
16017 <usage>registers</usage>
16018 </addressBlock>
16019 <registers>
16020 <register>
16021 <name>MEMRM</name>
16022 <displayName>MEMRM</displayName>
16023 <description>memory remap register</description>
16024 <addressOffset>0x0</addressOffset>
16025 <size>0x20</size>
16026 <access>read-write</access>
16027 <resetValue>0x00000000</resetValue>
16028 <fields>
16029 <field>
16030 <name>MEM_MODE</name>
16031 <description>Memory mapping selection</description>
16032 <bitOffset>0</bitOffset>
16033 <bitWidth>3</bitWidth>
16034 </field>
16035 <field>
16036 <name>FB_MODE</name>
16037 <description>Flash bank mode selection</description>
16038 <bitOffset>8</bitOffset>
16039 <bitWidth>1</bitWidth>
16040 </field>
16041 <field>
16042 <name>SWP_FMC</name>
16043 <description>FMC memory mapping swap</description>
16044 <bitOffset>10</bitOffset>
16045 <bitWidth>2</bitWidth>
16046 </field>
16047 </fields>
16048 </register>
16049 <register>
16050 <name>PMC</name>
16051 <displayName>PMC</displayName>
16052 <description>peripheral mode configuration
16053 register</description>
16054 <addressOffset>0x4</addressOffset>
16055 <size>0x20</size>
16056 <access>read-write</access>
16057 <resetValue>0x00000000</resetValue>
16058 <fields>
16059 <field>
16060 <name>MII_RMII_SEL</name>
16061 <description>Ethernet PHY interface
16062 selection</description>
16063 <bitOffset>23</bitOffset>
16064 <bitWidth>1</bitWidth>
16065 </field>
16066 <field>
16067 <name>ADC1DC2</name>
16068 <description>ADC1DC2</description>
16069 <bitOffset>16</bitOffset>
16070 <bitWidth>1</bitWidth>
16071 </field>
16072 <field>
16073 <name>ADC2DC2</name>
16074 <description>ADC2DC2</description>
16075 <bitOffset>17</bitOffset>
16076 <bitWidth>1</bitWidth>
16077 </field>
16078 <field>
16079 <name>ADC3DC2</name>
16080 <description>ADC3DC2</description>
16081 <bitOffset>18</bitOffset>
16082 <bitWidth>1</bitWidth>
16083 </field>
16084 </fields>
16085 </register>
16086 <register>
16087 <name>EXTICR1</name>
16088 <displayName>EXTICR1</displayName>
16089 <description>external interrupt configuration register
16090 1</description>
16091 <addressOffset>0x8</addressOffset>
16092 <size>0x20</size>
16093 <access>read-write</access>
16094 <resetValue>0x0000</resetValue>
16095 <fields>
16096 <field>
16097 <name>EXTI3</name>
16098 <description>EXTI x configuration (x = 0 to
16099 3)</description>
16100 <bitOffset>12</bitOffset>
16101 <bitWidth>4</bitWidth>
16102 </field>
16103 <field>
16104 <name>EXTI2</name>
16105 <description>EXTI x configuration (x = 0 to
16106 3)</description>
16107 <bitOffset>8</bitOffset>
16108 <bitWidth>4</bitWidth>
16109 </field>
16110 <field>
16111 <name>EXTI1</name>
16112 <description>EXTI x configuration (x = 0 to
16113 3)</description>
16114 <bitOffset>4</bitOffset>
16115 <bitWidth>4</bitWidth>
16116 </field>
16117 <field>
16118 <name>EXTI0</name>
16119 <description>EXTI x configuration (x = 0 to
16120 3)</description>
16121 <bitOffset>0</bitOffset>
16122 <bitWidth>4</bitWidth>
16123 </field>
16124 </fields>
16125 </register>
16126 <register>
16127 <name>EXTICR2</name>
16128 <displayName>EXTICR2</displayName>
16129 <description>external interrupt configuration register
16130 2</description>
16131 <addressOffset>0xC</addressOffset>
16132 <size>0x20</size>
16133 <access>read-write</access>
16134 <resetValue>0x0000</resetValue>
16135 <fields>
16136 <field>
16137 <name>EXTI7</name>
16138 <description>EXTI x configuration (x = 4 to
16139 7)</description>
16140 <bitOffset>12</bitOffset>
16141 <bitWidth>4</bitWidth>
16142 </field>
16143 <field>
16144 <name>EXTI6</name>
16145 <description>EXTI x configuration (x = 4 to
16146 7)</description>
16147 <bitOffset>8</bitOffset>
16148 <bitWidth>4</bitWidth>
16149 </field>
16150 <field>
16151 <name>EXTI5</name>
16152 <description>EXTI x configuration (x = 4 to
16153 7)</description>
16154 <bitOffset>4</bitOffset>
16155 <bitWidth>4</bitWidth>
16156 </field>
16157 <field>
16158 <name>EXTI4</name>
16159 <description>EXTI x configuration (x = 4 to
16160 7)</description>
16161 <bitOffset>0</bitOffset>
16162 <bitWidth>4</bitWidth>
16163 </field>
16164 </fields>
16165 </register>
16166 <register>
16167 <name>EXTICR3</name>
16168 <displayName>EXTICR3</displayName>
16169 <description>external interrupt configuration register
16170 3</description>
16171 <addressOffset>0x10</addressOffset>
16172 <size>0x20</size>
16173 <access>read-write</access>
16174 <resetValue>0x0000</resetValue>
16175 <fields>
16176 <field>
16177 <name>EXTI11</name>
16178 <description>EXTI x configuration (x = 8 to
16179 11)</description>
16180 <bitOffset>12</bitOffset>
16181 <bitWidth>4</bitWidth>
16182 </field>
16183 <field>
16184 <name>EXTI10</name>
16185 <description>EXTI10</description>
16186 <bitOffset>8</bitOffset>
16187 <bitWidth>4</bitWidth>
16188 </field>
16189 <field>
16190 <name>EXTI9</name>
16191 <description>EXTI x configuration (x = 8 to
16192 11)</description>
16193 <bitOffset>4</bitOffset>
16194 <bitWidth>4</bitWidth>
16195 </field>
16196 <field>
16197 <name>EXTI8</name>
16198 <description>EXTI x configuration (x = 8 to
16199 11)</description>
16200 <bitOffset>0</bitOffset>
16201 <bitWidth>4</bitWidth>
16202 </field>
16203 </fields>
16204 </register>
16205 <register>
16206 <name>EXTICR4</name>
16207 <displayName>EXTICR4</displayName>
16208 <description>external interrupt configuration register
16209 4</description>
16210 <addressOffset>0x14</addressOffset>
16211 <size>0x20</size>
16212 <access>read-write</access>
16213 <resetValue>0x0000</resetValue>
16214 <fields>
16215 <field>
16216 <name>EXTI15</name>
16217 <description>EXTI x configuration (x = 12 to
16218 15)</description>
16219 <bitOffset>12</bitOffset>
16220 <bitWidth>4</bitWidth>
16221 </field>
16222 <field>
16223 <name>EXTI14</name>
16224 <description>EXTI x configuration (x = 12 to
16225 15)</description>
16226 <bitOffset>8</bitOffset>
16227 <bitWidth>4</bitWidth>
16228 </field>
16229 <field>
16230 <name>EXTI13</name>
16231 <description>EXTI x configuration (x = 12 to
16232 15)</description>
16233 <bitOffset>4</bitOffset>
16234 <bitWidth>4</bitWidth>
16235 </field>
16236 <field>
16237 <name>EXTI12</name>
16238 <description>EXTI x configuration (x = 12 to
16239 15)</description>
16240 <bitOffset>0</bitOffset>
16241 <bitWidth>4</bitWidth>
16242 </field>
16243 </fields>
16244 </register>
16245 <register>
16246 <name>CMPCR</name>
16247 <displayName>CMPCR</displayName>
16248 <description>Compensation cell control
16249 register</description>
16250 <addressOffset>0x20</addressOffset>
16251 <size>0x20</size>
16252 <access>read-only</access>
16253 <resetValue>0x00000000</resetValue>
16254 <fields>
16255 <field>
16256 <name>READY</name>
16257 <description>READY</description>
16258 <bitOffset>8</bitOffset>
16259 <bitWidth>1</bitWidth>
16260 </field>
16261 <field>
16262 <name>CMP_PD</name>
16263 <description>Compensation cell
16264 power-down</description>
16265 <bitOffset>0</bitOffset>
16266 <bitWidth>1</bitWidth>
16267 </field>
16268 </fields>
16269 </register>
16270 </registers>
16271 </peripheral>
16272 <peripheral>
16273 <name>SPI1</name>
16274 <description>Serial peripheral interface</description>
16275 <groupName>SPI</groupName>
16276 <baseAddress>0x40013000</baseAddress>
16277 <addressBlock>
16278 <offset>0x0</offset>
16279 <size>0x400</size>
16280 <usage>registers</usage>
16281 </addressBlock>
16282 <interrupt>
16283 <name>SPI1</name>
16284 <description>SPI1 global interrupt</description>
16285 <value>35</value>
16286 </interrupt>
16287 <registers>
16288 <register>
16289 <name>CR1</name>
16290 <displayName>CR1</displayName>
16291 <description>control register 1</description>
16292 <addressOffset>0x0</addressOffset>
16293 <size>0x20</size>
16294 <access>read-write</access>
16295 <resetValue>0x0000</resetValue>
16296 <fields>
16297 <field>
16298 <name>BIDIMODE</name>
16299 <description>Bidirectional data mode
16300 enable</description>
16301 <bitOffset>15</bitOffset>
16302 <bitWidth>1</bitWidth>
16303 </field>
16304 <field>
16305 <name>BIDIOE</name>
16306 <description>Output enable in bidirectional
16307 mode</description>
16308 <bitOffset>14</bitOffset>
16309 <bitWidth>1</bitWidth>
16310 </field>
16311 <field>
16312 <name>CRCEN</name>
16313 <description>Hardware CRC calculation
16314 enable</description>
16315 <bitOffset>13</bitOffset>
16316 <bitWidth>1</bitWidth>
16317 </field>
16318 <field>
16319 <name>CRCNEXT</name>
16320 <description>CRC transfer next</description>
16321 <bitOffset>12</bitOffset>
16322 <bitWidth>1</bitWidth>
16323 </field>
16324 <field>
16325 <name>CRCL</name>
16326 <description>CRC length</description>
16327 <bitOffset>11</bitOffset>
16328 <bitWidth>1</bitWidth>
16329 </field>
16330 <field>
16331 <name>RXONLY</name>
16332 <description>Receive only</description>
16333 <bitOffset>10</bitOffset>
16334 <bitWidth>1</bitWidth>
16335 </field>
16336 <field>
16337 <name>SSM</name>
16338 <description>Software slave management</description>
16339 <bitOffset>9</bitOffset>
16340 <bitWidth>1</bitWidth>
16341 </field>
16342 <field>
16343 <name>SSI</name>
16344 <description>Internal slave select</description>
16345 <bitOffset>8</bitOffset>
16346 <bitWidth>1</bitWidth>
16347 </field>
16348 <field>
16349 <name>LSBFIRST</name>
16350 <description>Frame format</description>
16351 <bitOffset>7</bitOffset>
16352 <bitWidth>1</bitWidth>
16353 </field>
16354 <field>
16355 <name>SPE</name>
16356 <description>SPI enable</description>
16357 <bitOffset>6</bitOffset>
16358 <bitWidth>1</bitWidth>
16359 </field>
16360 <field>
16361 <name>BR</name>
16362 <description>Baud rate control</description>
16363 <bitOffset>3</bitOffset>
16364 <bitWidth>3</bitWidth>
16365 </field>
16366 <field>
16367 <name>MSTR</name>
16368 <description>Master selection</description>
16369 <bitOffset>2</bitOffset>
16370 <bitWidth>1</bitWidth>
16371 </field>
16372 <field>
16373 <name>CPOL</name>
16374 <description>Clock polarity</description>
16375 <bitOffset>1</bitOffset>
16376 <bitWidth>1</bitWidth>
16377 </field>
16378 <field>
16379 <name>CPHA</name>
16380 <description>Clock phase</description>
16381 <bitOffset>0</bitOffset>
16382 <bitWidth>1</bitWidth>
16383 </field>
16384 </fields>
16385 </register>
16386 <register>
16387 <name>CR2</name>
16388 <displayName>CR2</displayName>
16389 <description>control register 2</description>
16390 <addressOffset>0x4</addressOffset>
16391 <size>0x20</size>
16392 <access>read-write</access>
16393 <resetValue>0x0700</resetValue>
16394 <fields>
16395 <field>
16396 <name>RXDMAEN</name>
16397 <description>Rx buffer DMA enable</description>
16398 <bitOffset>0</bitOffset>
16399 <bitWidth>1</bitWidth>
16400 </field>
16401 <field>
16402 <name>TXDMAEN</name>
16403 <description>Tx buffer DMA enable</description>
16404 <bitOffset>1</bitOffset>
16405 <bitWidth>1</bitWidth>
16406 </field>
16407 <field>
16408 <name>SSOE</name>
16409 <description>SS output enable</description>
16410 <bitOffset>2</bitOffset>
16411 <bitWidth>1</bitWidth>
16412 </field>
16413 <field>
16414 <name>NSSP</name>
16415 <description>NSS pulse management</description>
16416 <bitOffset>3</bitOffset>
16417 <bitWidth>1</bitWidth>
16418 </field>
16419 <field>
16420 <name>FRF</name>
16421 <description>Frame format</description>
16422 <bitOffset>4</bitOffset>
16423 <bitWidth>1</bitWidth>
16424 </field>
16425 <field>
16426 <name>ERRIE</name>
16427 <description>Error interrupt enable</description>
16428 <bitOffset>5</bitOffset>
16429 <bitWidth>1</bitWidth>
16430 </field>
16431 <field>
16432 <name>RXNEIE</name>
16433 <description>RX buffer not empty interrupt
16434 enable</description>
16435 <bitOffset>6</bitOffset>
16436 <bitWidth>1</bitWidth>
16437 </field>
16438 <field>
16439 <name>TXEIE</name>
16440 <description>Tx buffer empty interrupt
16441 enable</description>
16442 <bitOffset>7</bitOffset>
16443 <bitWidth>1</bitWidth>
16444 </field>
16445 <field>
16446 <name>DS</name>
16447 <description>Data size</description>
16448 <bitOffset>8</bitOffset>
16449 <bitWidth>4</bitWidth>
16450 </field>
16451 <field>
16452 <name>FRXTH</name>
16453 <description>FIFO reception threshold</description>
16454 <bitOffset>12</bitOffset>
16455 <bitWidth>1</bitWidth>
16456 </field>
16457 <field>
16458 <name>LDMA_RX</name>
16459 <description>Last DMA transfer for
16460 reception</description>
16461 <bitOffset>13</bitOffset>
16462 <bitWidth>1</bitWidth>
16463 </field>
16464 <field>
16465 <name>LDMA_TX</name>
16466 <description>Last DMA transfer for
16467 transmission</description>
16468 <bitOffset>14</bitOffset>
16469 <bitWidth>1</bitWidth>
16470 </field>
16471 </fields>
16472 </register>
16473 <register>
16474 <name>SR</name>
16475 <displayName>SR</displayName>
16476 <description>status register</description>
16477 <addressOffset>0x8</addressOffset>
16478 <size>0x20</size>
16479 <resetValue>0x0002</resetValue>
16480 <fields>
16481 <field>
16482 <name>FRE</name>
16483 <description>Frame format error</description>
16484 <bitOffset>8</bitOffset>
16485 <bitWidth>1</bitWidth>
16486 <access>read-only</access>
16487 </field>
16488 <field>
16489 <name>BSY</name>
16490 <description>Busy flag</description>
16491 <bitOffset>7</bitOffset>
16492 <bitWidth>1</bitWidth>
16493 <access>read-only</access>
16494 </field>
16495 <field>
16496 <name>OVR</name>
16497 <description>Overrun flag</description>
16498 <bitOffset>6</bitOffset>
16499 <bitWidth>1</bitWidth>
16500 <access>read-only</access>
16501 </field>
16502 <field>
16503 <name>MODF</name>
16504 <description>Mode fault</description>
16505 <bitOffset>5</bitOffset>
16506 <bitWidth>1</bitWidth>
16507 <access>read-only</access>
16508 </field>
16509 <field>
16510 <name>CRCERR</name>
16511 <description>CRC error flag</description>
16512 <bitOffset>4</bitOffset>
16513 <bitWidth>1</bitWidth>
16514 <access>read-write</access>
16515 </field>
16516 <field>
16517 <name>UDR</name>
16518 <description>Underrun flag</description>
16519 <bitOffset>3</bitOffset>
16520 <bitWidth>1</bitWidth>
16521 <access>read-only</access>
16522 </field>
16523 <field>
16524 <name>CHSIDE</name>
16525 <description>Channel side</description>
16526 <bitOffset>2</bitOffset>
16527 <bitWidth>1</bitWidth>
16528 <access>read-only</access>
16529 </field>
16530 <field>
16531 <name>TXE</name>
16532 <description>Transmit buffer empty</description>
16533 <bitOffset>1</bitOffset>
16534 <bitWidth>1</bitWidth>
16535 <access>read-only</access>
16536 </field>
16537 <field>
16538 <name>RXNE</name>
16539 <description>Receive buffer not empty</description>
16540 <bitOffset>0</bitOffset>
16541 <bitWidth>1</bitWidth>
16542 <access>read-only</access>
16543 </field>
16544 <field>
16545 <name>FRLVL</name>
16546 <description>FIFO reception level</description>
16547 <bitOffset>9</bitOffset>
16548 <bitWidth>2</bitWidth>
16549 <access>read-only</access>
16550 </field>
16551 <field>
16552 <name>FTLVL</name>
16553 <description>FIFO Transmission Level</description>
16554 <bitOffset>11</bitOffset>
16555 <bitWidth>2</bitWidth>
16556 <access>read-only</access>
16557 </field>
16558 </fields>
16559 </register>
16560 <register>
16561 <name>DR</name>
16562 <displayName>DR</displayName>
16563 <description>data register</description>
16564 <addressOffset>0xC</addressOffset>
16565 <size>0x20</size>
16566 <access>read-write</access>
16567 <resetValue>0x0000</resetValue>
16568 <fields>
16569 <field>
16570 <name>DR</name>
16571 <description>Data register</description>
16572 <bitOffset>0</bitOffset>
16573 <bitWidth>16</bitWidth>
16574 </field>
16575 </fields>
16576 </register>
16577 <register>
16578 <name>CRCPR</name>
16579 <displayName>CRCPR</displayName>
16580 <description>CRC polynomial register</description>
16581 <addressOffset>0x10</addressOffset>
16582 <size>0x20</size>
16583 <access>read-write</access>
16584 <resetValue>0x0007</resetValue>
16585 <fields>
16586 <field>
16587 <name>CRCPOLY</name>
16588 <description>CRC polynomial register</description>
16589 <bitOffset>0</bitOffset>
16590 <bitWidth>16</bitWidth>
16591 </field>
16592 </fields>
16593 </register>
16594 <register>
16595 <name>RXCRCR</name>
16596 <displayName>RXCRCR</displayName>
16597 <description>RX CRC register</description>
16598 <addressOffset>0x14</addressOffset>
16599 <size>0x20</size>
16600 <access>read-only</access>
16601 <resetValue>0x0000</resetValue>
16602 <fields>
16603 <field>
16604 <name>RxCRC</name>
16605 <description>Rx CRC register</description>
16606 <bitOffset>0</bitOffset>
16607 <bitWidth>16</bitWidth>
16608 </field>
16609 </fields>
16610 </register>
16611 <register>
16612 <name>TXCRCR</name>
16613 <displayName>TXCRCR</displayName>
16614 <description>TX CRC register</description>
16615 <addressOffset>0x18</addressOffset>
16616 <size>0x20</size>
16617 <access>read-only</access>
16618 <resetValue>0x0000</resetValue>
16619 <fields>
16620 <field>
16621 <name>TxCRC</name>
16622 <description>Tx CRC register</description>
16623 <bitOffset>0</bitOffset>
16624 <bitWidth>16</bitWidth>
16625 </field>
16626 </fields>
16627 </register>
16628 <register>
16629 <name>I2SCFGR</name>
16630 <displayName>I2SCFGR</displayName>
16631 <description>I2S configuration register</description>
16632 <addressOffset>0x1C</addressOffset>
16633 <size>0x20</size>
16634 <access>read-write</access>
16635 <resetValue>0x0000</resetValue>
16636 <fields>
16637 <field>
16638 <name>I2SMOD</name>
16639 <description>I2S mode selection</description>
16640 <bitOffset>11</bitOffset>
16641 <bitWidth>1</bitWidth>
16642 </field>
16643 <field>
16644 <name>I2SE</name>
16645 <description>I2S Enable</description>
16646 <bitOffset>10</bitOffset>
16647 <bitWidth>1</bitWidth>
16648 </field>
16649 <field>
16650 <name>I2SCFG</name>
16651 <description>I2S configuration mode</description>
16652 <bitOffset>8</bitOffset>
16653 <bitWidth>2</bitWidth>
16654 </field>
16655 <field>
16656 <name>PCMSYNC</name>
16657 <description>PCM frame synchronization</description>
16658 <bitOffset>7</bitOffset>
16659 <bitWidth>1</bitWidth>
16660 </field>
16661 <field>
16662 <name>I2SSTD</name>
16663 <description>I2S standard selection</description>
16664 <bitOffset>4</bitOffset>
16665 <bitWidth>2</bitWidth>
16666 </field>
16667 <field>
16668 <name>CKPOL</name>
16669 <description>Steady state clock
16670 polarity</description>
16671 <bitOffset>3</bitOffset>
16672 <bitWidth>1</bitWidth>
16673 </field>
16674 <field>
16675 <name>DATLEN</name>
16676 <description>Data length to be
16677 transferred</description>
16678 <bitOffset>1</bitOffset>
16679 <bitWidth>2</bitWidth>
16680 </field>
16681 <field>
16682 <name>CHLEN</name>
16683 <description>Channel length (number of bits per audio
16684 channel)</description>
16685 <bitOffset>0</bitOffset>
16686 <bitWidth>1</bitWidth>
16687 </field>
16688 <field>
16689 <name>ASTRTEN</name>
16690 <description>Asynchronous start enable</description>
16691 <bitOffset>12</bitOffset>
16692 <bitWidth>1</bitWidth>
16693 </field>
16694 </fields>
16695 </register>
16696 <register>
16697 <name>I2SPR</name>
16698 <displayName>I2SPR</displayName>
16699 <description>I2S prescaler register</description>
16700 <addressOffset>0x20</addressOffset>
16701 <size>0x20</size>
16702 <access>read-write</access>
16703 <resetValue>00000010</resetValue>
16704 <fields>
16705 <field>
16706 <name>MCKOE</name>
16707 <description>Master clock output enable</description>
16708 <bitOffset>9</bitOffset>
16709 <bitWidth>1</bitWidth>
16710 </field>
16711 <field>
16712 <name>ODD</name>
16713 <description>Odd factor for the
16714 prescaler</description>
16715 <bitOffset>8</bitOffset>
16716 <bitWidth>1</bitWidth>
16717 </field>
16718 <field>
16719 <name>I2SDIV</name>
16720 <description>I2S Linear prescaler</description>
16721 <bitOffset>0</bitOffset>
16722 <bitWidth>8</bitWidth>
16723 </field>
16724 </fields>
16725 </register>
16726 </registers>
16727 </peripheral>
16728 <peripheral derivedFrom="SPI1">
16729 <name>SPI3</name>
16730 <baseAddress>0x40003C00</baseAddress>
16731 <interrupt>
16732 <name>SPI3</name>
16733 <description>SPI3 global interrupt</description>
16734 <value>51</value>
16735 </interrupt>
16736 </peripheral>
16737 <peripheral derivedFrom="SPI1">
16738 <name>SPI4</name>
16739 <baseAddress>0x40013400</baseAddress>
16740 <interrupt>
16741 <name>SPI4</name>
16742 <description>SPI 4 global interrupt</description>
16743 <value>84</value>
16744 </interrupt>
16745 </peripheral>
16746 <peripheral derivedFrom="SPI1">
16747 <name>SPI5</name>
16748 <baseAddress>0x40015000</baseAddress>
16749 <interrupt>
16750 <name>SPI5</name>
16751 <description>SPI 5 global interrupt</description>
16752 <value>85</value>
16753 </interrupt>
16754 </peripheral>
16755 <peripheral derivedFrom="SPI1">
16756 <name>SPI6</name>
16757 <baseAddress>0x40015400</baseAddress>
16758 <interrupt>
16759 <name>SPI6</name>
16760 <description>SPI 6 global interrupt</description>
16761 <value>86</value>
16762 </interrupt>
16763 </peripheral>
16764 <peripheral>
16765 <name>SPI2</name>
16766 <description>Serial peripheral interface</description>
16767 <groupName>SPI</groupName>
16768 <baseAddress>0x40003800</baseAddress>
16769 <addressBlock>
16770 <offset>0x0</offset>
16771 <size>0x400</size>
16772 <usage>registers</usage>
16773 </addressBlock>
16774 <interrupt>
16775 <name>SPI2</name>
16776 <description>SPI2 global interrupt</description>
16777 <value>36</value>
16778 </interrupt>
16779 <registers>
16780 <register>
16781 <name>CR1</name>
16782 <displayName>CR1</displayName>
16783 <description>control register 1</description>
16784 <addressOffset>0x0</addressOffset>
16785 <size>0x20</size>
16786 <access>read-write</access>
16787 <resetValue>0x0000</resetValue>
16788 <fields>
16789 <field>
16790 <name>BIDIMODE</name>
16791 <description>Bidirectional data mode
16792 enable</description>
16793 <bitOffset>15</bitOffset>
16794 <bitWidth>1</bitWidth>
16795 </field>
16796 <field>
16797 <name>BIDIOE</name>
16798 <description>Output enable in bidirectional
16799 mode</description>
16800 <bitOffset>14</bitOffset>
16801 <bitWidth>1</bitWidth>
16802 </field>
16803 <field>
16804 <name>CRCEN</name>
16805 <description>Hardware CRC calculation
16806 enable</description>
16807 <bitOffset>13</bitOffset>
16808 <bitWidth>1</bitWidth>
16809 </field>
16810 <field>
16811 <name>CRCNEXT</name>
16812 <description>CRC transfer next</description>
16813 <bitOffset>12</bitOffset>
16814 <bitWidth>1</bitWidth>
16815 </field>
16816 <field>
16817 <name>CRCL</name>
16818 <description>CRC length</description>
16819 <bitOffset>11</bitOffset>
16820 <bitWidth>1</bitWidth>
16821 </field>
16822 <field>
16823 <name>RXONLY</name>
16824 <description>Receive only</description>
16825 <bitOffset>10</bitOffset>
16826 <bitWidth>1</bitWidth>
16827 </field>
16828 <field>
16829 <name>SSM</name>
16830 <description>Software slave management</description>
16831 <bitOffset>9</bitOffset>
16832 <bitWidth>1</bitWidth>
16833 </field>
16834 <field>
16835 <name>SSI</name>
16836 <description>Internal slave select</description>
16837 <bitOffset>8</bitOffset>
16838 <bitWidth>1</bitWidth>
16839 </field>
16840 <field>
16841 <name>LSBFIRST</name>
16842 <description>Frame format</description>
16843 <bitOffset>7</bitOffset>
16844 <bitWidth>1</bitWidth>
16845 </field>
16846 <field>
16847 <name>SPE</name>
16848 <description>SPI enable</description>
16849 <bitOffset>6</bitOffset>
16850 <bitWidth>1</bitWidth>
16851 </field>
16852 <field>
16853 <name>BR</name>
16854 <description>Baud rate control</description>
16855 <bitOffset>3</bitOffset>
16856 <bitWidth>3</bitWidth>
16857 </field>
16858 <field>
16859 <name>MSTR</name>
16860 <description>Master selection</description>
16861 <bitOffset>2</bitOffset>
16862 <bitWidth>1</bitWidth>
16863 </field>
16864 <field>
16865 <name>CPOL</name>
16866 <description>Clock polarity</description>
16867 <bitOffset>1</bitOffset>
16868 <bitWidth>1</bitWidth>
16869 </field>
16870 <field>
16871 <name>CPHA</name>
16872 <description>Clock phase</description>
16873 <bitOffset>0</bitOffset>
16874 <bitWidth>1</bitWidth>
16875 </field>
16876 </fields>
16877 </register>
16878 <register>
16879 <name>CR2</name>
16880 <displayName>CR2</displayName>
16881 <description>control register 2</description>
16882 <addressOffset>0x4</addressOffset>
16883 <size>0x20</size>
16884 <access>read-write</access>
16885 <resetValue>0x0700</resetValue>
16886 <fields>
16887 <field>
16888 <name>RXDMAEN</name>
16889 <description>Rx buffer DMA enable</description>
16890 <bitOffset>0</bitOffset>
16891 <bitWidth>1</bitWidth>
16892 </field>
16893 <field>
16894 <name>TXDMAEN</name>
16895 <description>Tx buffer DMA enable</description>
16896 <bitOffset>1</bitOffset>
16897 <bitWidth>1</bitWidth>
16898 </field>
16899 <field>
16900 <name>SSOE</name>
16901 <description>SS output enable</description>
16902 <bitOffset>2</bitOffset>
16903 <bitWidth>1</bitWidth>
16904 </field>
16905 <field>
16906 <name>NSSP</name>
16907 <description>NSS pulse management</description>
16908 <bitOffset>3</bitOffset>
16909 <bitWidth>1</bitWidth>
16910 </field>
16911 <field>
16912 <name>FRF</name>
16913 <description>Frame format</description>
16914 <bitOffset>4</bitOffset>
16915 <bitWidth>1</bitWidth>
16916 </field>
16917 <field>
16918 <name>ERRIE</name>
16919 <description>Error interrupt enable</description>
16920 <bitOffset>5</bitOffset>
16921 <bitWidth>1</bitWidth>
16922 </field>
16923 <field>
16924 <name>RXNEIE</name>
16925 <description>RX buffer not empty interrupt
16926 enable</description>
16927 <bitOffset>6</bitOffset>
16928 <bitWidth>1</bitWidth>
16929 </field>
16930 <field>
16931 <name>TXEIE</name>
16932 <description>Tx buffer empty interrupt
16933 enable</description>
16934 <bitOffset>7</bitOffset>
16935 <bitWidth>1</bitWidth>
16936 </field>
16937 <field>
16938 <name>DS</name>
16939 <description>Data size</description>
16940 <bitOffset>8</bitOffset>
16941 <bitWidth>4</bitWidth>
16942 </field>
16943 <field>
16944 <name>FRXTH</name>
16945 <description>FIFO reception threshold</description>
16946 <bitOffset>12</bitOffset>
16947 <bitWidth>1</bitWidth>
16948 </field>
16949 <field>
16950 <name>LDMA_RX</name>
16951 <description>Last DMA transfer for
16952 reception</description>
16953 <bitOffset>13</bitOffset>
16954 <bitWidth>1</bitWidth>
16955 </field>
16956 <field>
16957 <name>LDMA_TX</name>
16958 <description>Last DMA transfer for
16959 transmission</description>
16960 <bitOffset>14</bitOffset>
16961 <bitWidth>1</bitWidth>
16962 </field>
16963 </fields>
16964 </register>
16965 <register>
16966 <name>SR</name>
16967 <displayName>SR</displayName>
16968 <description>status register</description>
16969 <addressOffset>0x8</addressOffset>
16970 <size>0x20</size>
16971 <resetValue>0x0002</resetValue>
16972 <fields>
16973 <field>
16974 <name>BSY</name>
16975 <description>Busy flag</description>
16976 <bitOffset>7</bitOffset>
16977 <bitWidth>1</bitWidth>
16978 <access>read-only</access>
16979 </field>
16980 <field>
16981 <name>OVR</name>
16982 <description>Overrun flag</description>
16983 <bitOffset>6</bitOffset>
16984 <bitWidth>1</bitWidth>
16985 <access>read-only</access>
16986 </field>
16987 <field>
16988 <name>MODF</name>
16989 <description>Mode fault</description>
16990 <bitOffset>5</bitOffset>
16991 <bitWidth>1</bitWidth>
16992 <access>read-only</access>
16993 </field>
16994 <field>
16995 <name>CRCERR</name>
16996 <description>CRC error flag</description>
16997 <bitOffset>4</bitOffset>
16998 <bitWidth>1</bitWidth>
16999 <access>read-write</access>
17000 </field>
17001 <field>
17002 <name>UDR</name>
17003 <description>Underrun flag</description>
17004 <bitOffset>3</bitOffset>
17005 <bitWidth>1</bitWidth>
17006 <access>read-only</access>
17007 </field>
17008 <field>
17009 <name>CHSIDE</name>
17010 <description>Channel side</description>
17011 <bitOffset>2</bitOffset>
17012 <bitWidth>1</bitWidth>
17013 <access>read-only</access>
17014 </field>
17015 <field>
17016 <name>TXE</name>
17017 <description>Transmit buffer empty</description>
17018 <bitOffset>1</bitOffset>
17019 <bitWidth>1</bitWidth>
17020 <access>read-only</access>
17021 </field>
17022 <field>
17023 <name>RXNE</name>
17024 <description>Receive buffer not empty</description>
17025 <bitOffset>0</bitOffset>
17026 <bitWidth>1</bitWidth>
17027 <access>read-only</access>
17028 </field>
17029 <field>
17030 <name>FRE</name>
17031 <description>Frame format error</description>
17032 <bitOffset>8</bitOffset>
17033 <bitWidth>1</bitWidth>
17034 <access>read-only</access>
17035 </field>
17036 <field>
17037 <name>FRLVL</name>
17038 <description>FIFO reception level</description>
17039 <bitOffset>9</bitOffset>
17040 <bitWidth>2</bitWidth>
17041 <access>read-only</access>
17042 </field>
17043 <field>
17044 <name>FTLVL</name>
17045 <description>FIFO Transmission Level</description>
17046 <bitOffset>11</bitOffset>
17047 <bitWidth>2</bitWidth>
17048 <access>read-only</access>
17049 </field>
17050 </fields>
17051 </register>
17052 <register>
17053 <name>DR</name>
17054 <displayName>DR</displayName>
17055 <description>data register</description>
17056 <addressOffset>0xC</addressOffset>
17057 <size>0x20</size>
17058 <access>read-write</access>
17059 <resetValue>0x0000</resetValue>
17060 <fields>
17061 <field>
17062 <name>DR</name>
17063 <description>Data register</description>
17064 <bitOffset>0</bitOffset>
17065 <bitWidth>16</bitWidth>
17066 </field>
17067 </fields>
17068 </register>
17069 <register>
17070 <name>CRCPR</name>
17071 <displayName>CRCPR</displayName>
17072 <description>CRC polynomial register</description>
17073 <addressOffset>0x10</addressOffset>
17074 <size>0x20</size>
17075 <access>read-write</access>
17076 <resetValue>0x0007</resetValue>
17077 <fields>
17078 <field>
17079 <name>CRCPOLY</name>
17080 <description>CRC polynomial register</description>
17081 <bitOffset>0</bitOffset>
17082 <bitWidth>16</bitWidth>
17083 </field>
17084 </fields>
17085 </register>
17086 <register>
17087 <name>RXCRCR</name>
17088 <displayName>RXCRCR</displayName>
17089 <description>RX CRC register</description>
17090 <addressOffset>0x14</addressOffset>
17091 <size>0x20</size>
17092 <access>read-only</access>
17093 <resetValue>0x0000</resetValue>
17094 <fields>
17095 <field>
17096 <name>RxCRC</name>
17097 <description>Rx CRC register</description>
17098 <bitOffset>0</bitOffset>
17099 <bitWidth>16</bitWidth>
17100 </field>
17101 </fields>
17102 </register>
17103 <register>
17104 <name>TXCRCR</name>
17105 <displayName>TXCRCR</displayName>
17106 <description>TX CRC register</description>
17107 <addressOffset>0x18</addressOffset>
17108 <size>0x20</size>
17109 <access>read-only</access>
17110 <resetValue>0x0000</resetValue>
17111 <fields>
17112 <field>
17113 <name>TxCRC</name>
17114 <description>Tx CRC register</description>
17115 <bitOffset>0</bitOffset>
17116 <bitWidth>16</bitWidth>
17117 </field>
17118 </fields>
17119 </register>
17120 <register>
17121 <name>I2SCFGR</name>
17122 <displayName>I2SCFGR</displayName>
17123 <description>I2S configuration register</description>
17124 <addressOffset>0x1C</addressOffset>
17125 <size>0x20</size>
17126 <access>read-write</access>
17127 <resetValue>0x0000</resetValue>
17128 <fields>
17129 <field>
17130 <name>I2SMOD</name>
17131 <description>I2S mode selection</description>
17132 <bitOffset>11</bitOffset>
17133 <bitWidth>1</bitWidth>
17134 </field>
17135 <field>
17136 <name>I2SE</name>
17137 <description>I2S Enable</description>
17138 <bitOffset>10</bitOffset>
17139 <bitWidth>1</bitWidth>
17140 </field>
17141 <field>
17142 <name>I2SCFG</name>
17143 <description>I2S configuration mode</description>
17144 <bitOffset>8</bitOffset>
17145 <bitWidth>2</bitWidth>
17146 </field>
17147 <field>
17148 <name>PCMSYNC</name>
17149 <description>PCM frame synchronization</description>
17150 <bitOffset>7</bitOffset>
17151 <bitWidth>1</bitWidth>
17152 </field>
17153 <field>
17154 <name>I2SSTD</name>
17155 <description>I2S standard selection</description>
17156 <bitOffset>4</bitOffset>
17157 <bitWidth>2</bitWidth>
17158 </field>
17159 <field>
17160 <name>CKPOL</name>
17161 <description>Steady state clock
17162 polarity</description>
17163 <bitOffset>3</bitOffset>
17164 <bitWidth>1</bitWidth>
17165 </field>
17166 <field>
17167 <name>DATLEN</name>
17168 <description>Data length to be
17169 transferred</description>
17170 <bitOffset>1</bitOffset>
17171 <bitWidth>2</bitWidth>
17172 </field>
17173 <field>
17174 <name>CHLEN</name>
17175 <description>Channel length (number of bits per audio
17176 channel)</description>
17177 <bitOffset>0</bitOffset>
17178 <bitWidth>1</bitWidth>
17179 </field>
17180 <field>
17181 <name>ASTRTEN</name>
17182 <description>Asynchronous start enable</description>
17183 <bitOffset>12</bitOffset>
17184 <bitWidth>1</bitWidth>
17185 </field>
17186 </fields>
17187 </register>
17188 <register>
17189 <name>I2SPR</name>
17190 <displayName>I2SPR</displayName>
17191 <description>I2S prescaler register</description>
17192 <addressOffset>0x20</addressOffset>
17193 <size>0x20</size>
17194 <access>read-write</access>
17195 <resetValue>00000010</resetValue>
17196 <fields>
17197 <field>
17198 <name>MCKOE</name>
17199 <description>Master clock output enable</description>
17200 <bitOffset>9</bitOffset>
17201 <bitWidth>1</bitWidth>
17202 </field>
17203 <field>
17204 <name>ODD</name>
17205 <description>Odd factor for the
17206 prescaler</description>
17207 <bitOffset>8</bitOffset>
17208 <bitWidth>1</bitWidth>
17209 </field>
17210 <field>
17211 <name>I2SDIV</name>
17212 <description>I2S Linear prescaler</description>
17213 <bitOffset>0</bitOffset>
17214 <bitWidth>8</bitWidth>
17215 </field>
17216 </fields>
17217 </register>
17218 </registers>
17219 </peripheral>
17220 <peripheral>
17221 <name>ADC1</name>
17222 <description>Analog-to-digital converter</description>
17223 <groupName>ADC</groupName>
17224 <baseAddress>0x40012000</baseAddress>
17225 <addressBlock>
17226 <offset>0x0</offset>
17227 <size>0x100</size>
17228 <usage>registers</usage>
17229 </addressBlock>
17230 <interrupt>
17231 <name>ADC</name>
17232 <description>ADC1 global interrupt</description>
17233 <value>18</value>
17234 </interrupt>
17235 <registers>
17236 <register>
17237 <name>SR</name>
17238 <displayName>SR</displayName>
17239 <description>status register</description>
17240 <addressOffset>0x0</addressOffset>
17241 <size>0x20</size>
17242 <access>read-write</access>
17243 <resetValue>0x00000000</resetValue>
17244 <fields>
17245 <field>
17246 <name>OVR</name>
17247 <description>Overrun</description>
17248 <bitOffset>5</bitOffset>
17249 <bitWidth>1</bitWidth>
17250 </field>
17251 <field>
17252 <name>STRT</name>
17253 <description>Regular channel start flag</description>
17254 <bitOffset>4</bitOffset>
17255 <bitWidth>1</bitWidth>
17256 </field>
17257 <field>
17258 <name>JSTRT</name>
17259 <description>Injected channel start
17260 flag</description>
17261 <bitOffset>3</bitOffset>
17262 <bitWidth>1</bitWidth>
17263 </field>
17264 <field>
17265 <name>JEOC</name>
17266 <description>Injected channel end of
17267 conversion</description>
17268 <bitOffset>2</bitOffset>
17269 <bitWidth>1</bitWidth>
17270 </field>
17271 <field>
17272 <name>EOC</name>
17273 <description>Regular channel end of
17274 conversion</description>
17275 <bitOffset>1</bitOffset>
17276 <bitWidth>1</bitWidth>
17277 </field>
17278 <field>
17279 <name>AWD</name>
17280 <description>Analog watchdog flag</description>
17281 <bitOffset>0</bitOffset>
17282 <bitWidth>1</bitWidth>
17283 </field>
17284 </fields>
17285 </register>
17286 <register>
17287 <name>CR1</name>
17288 <displayName>CR1</displayName>
17289 <description>control register 1</description>
17290 <addressOffset>0x4</addressOffset>
17291 <size>0x20</size>
17292 <access>read-write</access>
17293 <resetValue>0x00000000</resetValue>
17294 <fields>
17295 <field>
17296 <name>OVRIE</name>
17297 <description>Overrun interrupt enable</description>
17298 <bitOffset>26</bitOffset>
17299 <bitWidth>1</bitWidth>
17300 </field>
17301 <field>
17302 <name>RES</name>
17303 <description>Resolution</description>
17304 <bitOffset>24</bitOffset>
17305 <bitWidth>2</bitWidth>
17306 </field>
17307 <field>
17308 <name>AWDEN</name>
17309 <description>Analog watchdog enable on regular
17310 channels</description>
17311 <bitOffset>23</bitOffset>
17312 <bitWidth>1</bitWidth>
17313 </field>
17314 <field>
17315 <name>JAWDEN</name>
17316 <description>Analog watchdog enable on injected
17317 channels</description>
17318 <bitOffset>22</bitOffset>
17319 <bitWidth>1</bitWidth>
17320 </field>
17321 <field>
17322 <name>DISCNUM</name>
17323 <description>Discontinuous mode channel
17324 count</description>
17325 <bitOffset>13</bitOffset>
17326 <bitWidth>3</bitWidth>
17327 </field>
17328 <field>
17329 <name>JDISCEN</name>
17330 <description>Discontinuous mode on injected
17331 channels</description>
17332 <bitOffset>12</bitOffset>
17333 <bitWidth>1</bitWidth>
17334 </field>
17335 <field>
17336 <name>DISCEN</name>
17337 <description>Discontinuous mode on regular
17338 channels</description>
17339 <bitOffset>11</bitOffset>
17340 <bitWidth>1</bitWidth>
17341 </field>
17342 <field>
17343 <name>JAUTO</name>
17344 <description>Automatic injected group
17345 conversion</description>
17346 <bitOffset>10</bitOffset>
17347 <bitWidth>1</bitWidth>
17348 </field>
17349 <field>
17350 <name>AWDSGL</name>
17351 <description>Enable the watchdog on a single channel
17352 in scan mode</description>
17353 <bitOffset>9</bitOffset>
17354 <bitWidth>1</bitWidth>
17355 </field>
17356 <field>
17357 <name>SCAN</name>
17358 <description>Scan mode</description>
17359 <bitOffset>8</bitOffset>
17360 <bitWidth>1</bitWidth>
17361 </field>
17362 <field>
17363 <name>JEOCIE</name>
17364 <description>Interrupt enable for injected
17365 channels</description>
17366 <bitOffset>7</bitOffset>
17367 <bitWidth>1</bitWidth>
17368 </field>
17369 <field>
17370 <name>AWDIE</name>
17371 <description>Analog watchdog interrupt
17372 enable</description>
17373 <bitOffset>6</bitOffset>
17374 <bitWidth>1</bitWidth>
17375 </field>
17376 <field>
17377 <name>EOCIE</name>
17378 <description>Interrupt enable for EOC</description>
17379 <bitOffset>5</bitOffset>
17380 <bitWidth>1</bitWidth>
17381 </field>
17382 <field>
17383 <name>AWDCH</name>
17384 <description>Analog watchdog channel select
17385 bits</description>
17386 <bitOffset>0</bitOffset>
17387 <bitWidth>5</bitWidth>
17388 </field>
17389 </fields>
17390 </register>
17391 <register>
17392 <name>CR2</name>
17393 <displayName>CR2</displayName>
17394 <description>control register 2</description>
17395 <addressOffset>0x8</addressOffset>
17396 <size>0x20</size>
17397 <access>read-write</access>
17398 <resetValue>0x00000000</resetValue>
17399 <fields>
17400 <field>
17401 <name>SWSTART</name>
17402 <description>Start conversion of regular
17403 channels</description>
17404 <bitOffset>30</bitOffset>
17405 <bitWidth>1</bitWidth>
17406 </field>
17407 <field>
17408 <name>EXTEN</name>
17409 <description>External trigger enable for regular
17410 channels</description>
17411 <bitOffset>28</bitOffset>
17412 <bitWidth>2</bitWidth>
17413 </field>
17414 <field>
17415 <name>EXTSEL</name>
17416 <description>External event select for regular
17417 group</description>
17418 <bitOffset>24</bitOffset>
17419 <bitWidth>4</bitWidth>
17420 </field>
17421 <field>
17422 <name>JSWSTART</name>
17423 <description>Start conversion of injected
17424 channels</description>
17425 <bitOffset>22</bitOffset>
17426 <bitWidth>1</bitWidth>
17427 </field>
17428 <field>
17429 <name>JEXTEN</name>
17430 <description>External trigger enable for injected
17431 channels</description>
17432 <bitOffset>20</bitOffset>
17433 <bitWidth>2</bitWidth>
17434 </field>
17435 <field>
17436 <name>JEXTSEL</name>
17437 <description>External event select for injected
17438 group</description>
17439 <bitOffset>16</bitOffset>
17440 <bitWidth>4</bitWidth>
17441 </field>
17442 <field>
17443 <name>ALIGN</name>
17444 <description>Data alignment</description>
17445 <bitOffset>11</bitOffset>
17446 <bitWidth>1</bitWidth>
17447 </field>
17448 <field>
17449 <name>EOCS</name>
17450 <description>End of conversion
17451 selection</description>
17452 <bitOffset>10</bitOffset>
17453 <bitWidth>1</bitWidth>
17454 </field>
17455 <field>
17456 <name>DDS</name>
17457 <description>DMA disable selection (for single ADC
17458 mode)</description>
17459 <bitOffset>9</bitOffset>
17460 <bitWidth>1</bitWidth>
17461 </field>
17462 <field>
17463 <name>DMA</name>
17464 <description>Direct memory access mode (for single
17465 ADC mode)</description>
17466 <bitOffset>8</bitOffset>
17467 <bitWidth>1</bitWidth>
17468 </field>
17469 <field>
17470 <name>CONT</name>
17471 <description>Continuous conversion</description>
17472 <bitOffset>1</bitOffset>
17473 <bitWidth>1</bitWidth>
17474 </field>
17475 <field>
17476 <name>ADON</name>
17477 <description>A/D Converter ON / OFF</description>
17478 <bitOffset>0</bitOffset>
17479 <bitWidth>1</bitWidth>
17480 </field>
17481 </fields>
17482 </register>
17483 <register>
17484 <name>SMPR1</name>
17485 <displayName>SMPR1</displayName>
17486 <description>sample time register 1</description>
17487 <addressOffset>0xC</addressOffset>
17488 <size>0x20</size>
17489 <access>read-write</access>
17490 <resetValue>0x00000000</resetValue>
17491 <fields>
17492 <field>
17493 <name>SMPx_x</name>
17494 <description>Sample time bits</description>
17495 <bitOffset>0</bitOffset>
17496 <bitWidth>32</bitWidth>
17497 </field>
17498 </fields>
17499 </register>
17500 <register>
17501 <name>SMPR2</name>
17502 <displayName>SMPR2</displayName>
17503 <description>sample time register 2</description>
17504 <addressOffset>0x10</addressOffset>
17505 <size>0x20</size>
17506 <access>read-write</access>
17507 <resetValue>0x00000000</resetValue>
17508 <fields>
17509 <field>
17510 <name>SMPx_x</name>
17511 <description>Sample time bits</description>
17512 <bitOffset>0</bitOffset>
17513 <bitWidth>32</bitWidth>
17514 </field>
17515 </fields>
17516 </register>
17517 <register>
17518 <name>JOFR1</name>
17519 <displayName>JOFR1</displayName>
17520 <description>injected channel data offset register
17521 x</description>
17522 <addressOffset>0x14</addressOffset>
17523 <size>0x20</size>
17524 <access>read-write</access>
17525 <resetValue>0x00000000</resetValue>
17526 <fields>
17527 <field>
17528 <name>JOFFSET1</name>
17529 <description>Data offset for injected channel
17530 x</description>
17531 <bitOffset>0</bitOffset>
17532 <bitWidth>12</bitWidth>
17533 </field>
17534 </fields>
17535 </register>
17536 <register>
17537 <name>JOFR2</name>
17538 <displayName>JOFR2</displayName>
17539 <description>injected channel data offset register
17540 x</description>
17541 <addressOffset>0x18</addressOffset>
17542 <size>0x20</size>
17543 <access>read-write</access>
17544 <resetValue>0x00000000</resetValue>
17545 <fields>
17546 <field>
17547 <name>JOFFSET2</name>
17548 <description>Data offset for injected channel
17549 x</description>
17550 <bitOffset>0</bitOffset>
17551 <bitWidth>12</bitWidth>
17552 </field>
17553 </fields>
17554 </register>
17555 <register>
17556 <name>JOFR3</name>
17557 <displayName>JOFR3</displayName>
17558 <description>injected channel data offset register
17559 x</description>
17560 <addressOffset>0x1C</addressOffset>
17561 <size>0x20</size>
17562 <access>read-write</access>
17563 <resetValue>0x00000000</resetValue>
17564 <fields>
17565 <field>
17566 <name>JOFFSET3</name>
17567 <description>Data offset for injected channel
17568 x</description>
17569 <bitOffset>0</bitOffset>
17570 <bitWidth>12</bitWidth>
17571 </field>
17572 </fields>
17573 </register>
17574 <register>
17575 <name>JOFR4</name>
17576 <displayName>JOFR4</displayName>
17577 <description>injected channel data offset register
17578 x</description>
17579 <addressOffset>0x20</addressOffset>
17580 <size>0x20</size>
17581 <access>read-write</access>
17582 <resetValue>0x00000000</resetValue>
17583 <fields>
17584 <field>
17585 <name>JOFFSET4</name>
17586 <description>Data offset for injected channel
17587 x</description>
17588 <bitOffset>0</bitOffset>
17589 <bitWidth>12</bitWidth>
17590 </field>
17591 </fields>
17592 </register>
17593 <register>
17594 <name>HTR</name>
17595 <displayName>HTR</displayName>
17596 <description>watchdog higher threshold
17597 register</description>
17598 <addressOffset>0x24</addressOffset>
17599 <size>0x20</size>
17600 <access>read-write</access>
17601 <resetValue>0x00000FFF</resetValue>
17602 <fields>
17603 <field>
17604 <name>HT</name>
17605 <description>Analog watchdog higher
17606 threshold</description>
17607 <bitOffset>0</bitOffset>
17608 <bitWidth>12</bitWidth>
17609 </field>
17610 </fields>
17611 </register>
17612 <register>
17613 <name>LTR</name>
17614 <displayName>LTR</displayName>
17615 <description>watchdog lower threshold
17616 register</description>
17617 <addressOffset>0x28</addressOffset>
17618 <size>0x20</size>
17619 <access>read-write</access>
17620 <resetValue>0x00000000</resetValue>
17621 <fields>
17622 <field>
17623 <name>LT</name>
17624 <description>Analog watchdog lower
17625 threshold</description>
17626 <bitOffset>0</bitOffset>
17627 <bitWidth>12</bitWidth>
17628 </field>
17629 </fields>
17630 </register>
17631 <register>
17632 <name>SQR1</name>
17633 <displayName>SQR1</displayName>
17634 <description>regular sequence register 1</description>
17635 <addressOffset>0x2C</addressOffset>
17636 <size>0x20</size>
17637 <access>read-write</access>
17638 <resetValue>0x00000000</resetValue>
17639 <fields>
17640 <field>
17641 <name>L</name>
17642 <description>Regular channel sequence
17643 length</description>
17644 <bitOffset>20</bitOffset>
17645 <bitWidth>4</bitWidth>
17646 </field>
17647 <field>
17648 <name>SQ16</name>
17649 <description>16th conversion in regular
17650 sequence</description>
17651 <bitOffset>15</bitOffset>
17652 <bitWidth>5</bitWidth>
17653 </field>
17654 <field>
17655 <name>SQ15</name>
17656 <description>15th conversion in regular
17657 sequence</description>
17658 <bitOffset>10</bitOffset>
17659 <bitWidth>5</bitWidth>
17660 </field>
17661 <field>
17662 <name>SQ14</name>
17663 <description>14th conversion in regular
17664 sequence</description>
17665 <bitOffset>5</bitOffset>
17666 <bitWidth>5</bitWidth>
17667 </field>
17668 <field>
17669 <name>SQ13</name>
17670 <description>13th conversion in regular
17671 sequence</description>
17672 <bitOffset>0</bitOffset>
17673 <bitWidth>5</bitWidth>
17674 </field>
17675 </fields>
17676 </register>
17677 <register>
17678 <name>SQR2</name>
17679 <displayName>SQR2</displayName>
17680 <description>regular sequence register 2</description>
17681 <addressOffset>0x30</addressOffset>
17682 <size>0x20</size>
17683 <access>read-write</access>
17684 <resetValue>0x00000000</resetValue>
17685 <fields>
17686 <field>
17687 <name>SQ12</name>
17688 <description>12th conversion in regular
17689 sequence</description>
17690 <bitOffset>25</bitOffset>
17691 <bitWidth>5</bitWidth>
17692 </field>
17693 <field>
17694 <name>SQ11</name>
17695 <description>11th conversion in regular
17696 sequence</description>
17697 <bitOffset>20</bitOffset>
17698 <bitWidth>5</bitWidth>
17699 </field>
17700 <field>
17701 <name>SQ10</name>
17702 <description>10th conversion in regular
17703 sequence</description>
17704 <bitOffset>15</bitOffset>
17705 <bitWidth>5</bitWidth>
17706 </field>
17707 <field>
17708 <name>SQ9</name>
17709 <description>9th conversion in regular
17710 sequence</description>
17711 <bitOffset>10</bitOffset>
17712 <bitWidth>5</bitWidth>
17713 </field>
17714 <field>
17715 <name>SQ8</name>
17716 <description>8th conversion in regular
17717 sequence</description>
17718 <bitOffset>5</bitOffset>
17719 <bitWidth>5</bitWidth>
17720 </field>
17721 <field>
17722 <name>SQ7</name>
17723 <description>7th conversion in regular
17724 sequence</description>
17725 <bitOffset>0</bitOffset>
17726 <bitWidth>5</bitWidth>
17727 </field>
17728 </fields>
17729 </register>
17730 <register>
17731 <name>SQR3</name>
17732 <displayName>SQR3</displayName>
17733 <description>regular sequence register 3</description>
17734 <addressOffset>0x34</addressOffset>
17735 <size>0x20</size>
17736 <access>read-write</access>
17737 <resetValue>0x00000000</resetValue>
17738 <fields>
17739 <field>
17740 <name>SQ6</name>
17741 <description>6th conversion in regular
17742 sequence</description>
17743 <bitOffset>25</bitOffset>
17744 <bitWidth>5</bitWidth>
17745 </field>
17746 <field>
17747 <name>SQ5</name>
17748 <description>5th conversion in regular
17749 sequence</description>
17750 <bitOffset>20</bitOffset>
17751 <bitWidth>5</bitWidth>
17752 </field>
17753 <field>
17754 <name>SQ4</name>
17755 <description>4th conversion in regular
17756 sequence</description>
17757 <bitOffset>15</bitOffset>
17758 <bitWidth>5</bitWidth>
17759 </field>
17760 <field>
17761 <name>SQ3</name>
17762 <description>3rd conversion in regular
17763 sequence</description>
17764 <bitOffset>10</bitOffset>
17765 <bitWidth>5</bitWidth>
17766 </field>
17767 <field>
17768 <name>SQ2</name>
17769 <description>2nd conversion in regular
17770 sequence</description>
17771 <bitOffset>5</bitOffset>
17772 <bitWidth>5</bitWidth>
17773 </field>
17774 <field>
17775 <name>SQ1</name>
17776 <description>1st conversion in regular
17777 sequence</description>
17778 <bitOffset>0</bitOffset>
17779 <bitWidth>5</bitWidth>
17780 </field>
17781 </fields>
17782 </register>
17783 <register>
17784 <name>JSQR</name>
17785 <displayName>JSQR</displayName>
17786 <description>injected sequence register</description>
17787 <addressOffset>0x38</addressOffset>
17788 <size>0x20</size>
17789 <access>read-write</access>
17790 <resetValue>0x00000000</resetValue>
17791 <fields>
17792 <field>
17793 <name>JL</name>
17794 <description>Injected sequence length</description>
17795 <bitOffset>20</bitOffset>
17796 <bitWidth>2</bitWidth>
17797 </field>
17798 <field>
17799 <name>JSQ4</name>
17800 <description>4th conversion in injected
17801 sequence</description>
17802 <bitOffset>15</bitOffset>
17803 <bitWidth>5</bitWidth>
17804 </field>
17805 <field>
17806 <name>JSQ3</name>
17807 <description>3rd conversion in injected
17808 sequence</description>
17809 <bitOffset>10</bitOffset>
17810 <bitWidth>5</bitWidth>
17811 </field>
17812 <field>
17813 <name>JSQ2</name>
17814 <description>2nd conversion in injected
17815 sequence</description>
17816 <bitOffset>5</bitOffset>
17817 <bitWidth>5</bitWidth>
17818 </field>
17819 <field>
17820 <name>JSQ1</name>
17821 <description>1st conversion in injected
17822 sequence</description>
17823 <bitOffset>0</bitOffset>
17824 <bitWidth>5</bitWidth>
17825 </field>
17826 </fields>
17827 </register>
17828 <register>
17829 <name>JDR1</name>
17830 <displayName>JDR1</displayName>
17831 <description>injected data register x</description>
17832 <addressOffset>0x3C</addressOffset>
17833 <size>0x20</size>
17834 <access>read-only</access>
17835 <resetValue>0x00000000</resetValue>
17836 <fields>
17837 <field>
17838 <name>JDATA</name>
17839 <description>Injected data</description>
17840 <bitOffset>0</bitOffset>
17841 <bitWidth>16</bitWidth>
17842 </field>
17843 </fields>
17844 </register>
17845 <register>
17846 <name>JDR2</name>
17847 <displayName>JDR2</displayName>
17848 <description>injected data register x</description>
17849 <addressOffset>0x40</addressOffset>
17850 <size>0x20</size>
17851 <access>read-only</access>
17852 <resetValue>0x00000000</resetValue>
17853 <fields>
17854 <field>
17855 <name>JDATA</name>
17856 <description>Injected data</description>
17857 <bitOffset>0</bitOffset>
17858 <bitWidth>16</bitWidth>
17859 </field>
17860 </fields>
17861 </register>
17862 <register>
17863 <name>JDR3</name>
17864 <displayName>JDR3</displayName>
17865 <description>injected data register x</description>
17866 <addressOffset>0x44</addressOffset>
17867 <size>0x20</size>
17868 <access>read-only</access>
17869 <resetValue>0x00000000</resetValue>
17870 <fields>
17871 <field>
17872 <name>JDATA</name>
17873 <description>Injected data</description>
17874 <bitOffset>0</bitOffset>
17875 <bitWidth>16</bitWidth>
17876 </field>
17877 </fields>
17878 </register>
17879 <register>
17880 <name>JDR4</name>
17881 <displayName>JDR4</displayName>
17882 <description>injected data register x</description>
17883 <addressOffset>0x48</addressOffset>
17884 <size>0x20</size>
17885 <access>read-only</access>
17886 <resetValue>0x00000000</resetValue>
17887 <fields>
17888 <field>
17889 <name>JDATA</name>
17890 <description>Injected data</description>
17891 <bitOffset>0</bitOffset>
17892 <bitWidth>16</bitWidth>
17893 </field>
17894 </fields>
17895 </register>
17896 <register>
17897 <name>DR</name>
17898 <displayName>DR</displayName>
17899 <description>regular data register</description>
17900 <addressOffset>0x4C</addressOffset>
17901 <size>0x20</size>
17902 <access>read-only</access>
17903 <resetValue>0x00000000</resetValue>
17904 <fields>
17905 <field>
17906 <name>DATA</name>
17907 <description>Regular data</description>
17908 <bitOffset>0</bitOffset>
17909 <bitWidth>16</bitWidth>
17910 </field>
17911 </fields>
17912 </register>
17913 </registers>
17914 </peripheral>
17915 <peripheral derivedFrom="ADC1">
17916 <name>ADC2</name>
17917 <baseAddress>0x40012100</baseAddress>
17918 </peripheral>
17919 <peripheral derivedFrom="ADC1">
17920 <name>ADC3</name>
17921 <baseAddress>0x40012200</baseAddress>
17922 </peripheral>
17923 <peripheral>
17924 <name>DAC</name>
17925 <description>Digital-to-analog converter</description>
17926 <groupName>DAC</groupName>
17927 <baseAddress>0x40007400</baseAddress>
17928 <addressBlock>
17929 <offset>0x0</offset>
17930 <size>0x400</size>
17931 <usage>registers</usage>
17932 </addressBlock>
17933 <registers>
17934 <register>
17935 <name>CR</name>
17936 <displayName>CR</displayName>
17937 <description>control register</description>
17938 <addressOffset>0x0</addressOffset>
17939 <size>0x20</size>
17940 <access>read-write</access>
17941 <resetValue>0x00000000</resetValue>
17942 <fields>
17943 <field>
17944 <name>DMAUDRIE2</name>
17945 <description>DAC channel2 DMA underrun interrupt
17946 enable</description>
17947 <bitOffset>29</bitOffset>
17948 <bitWidth>1</bitWidth>
17949 </field>
17950 <field>
17951 <name>DMAEN2</name>
17952 <description>DAC channel2 DMA enable</description>
17953 <bitOffset>28</bitOffset>
17954 <bitWidth>1</bitWidth>
17955 </field>
17956 <field>
17957 <name>MAMP2</name>
17958 <description>DAC channel2 mask/amplitude
17959 selector</description>
17960 <bitOffset>24</bitOffset>
17961 <bitWidth>4</bitWidth>
17962 </field>
17963 <field>
17964 <name>WAVE2</name>
17965 <description>DAC channel2 noise/triangle wave
17966 generation enable</description>
17967 <bitOffset>22</bitOffset>
17968 <bitWidth>2</bitWidth>
17969 </field>
17970 <field>
17971 <name>TSEL2</name>
17972 <description>DAC channel2 trigger
17973 selection</description>
17974 <bitOffset>19</bitOffset>
17975 <bitWidth>3</bitWidth>
17976 </field>
17977 <field>
17978 <name>TEN2</name>
17979 <description>DAC channel2 trigger
17980 enable</description>
17981 <bitOffset>18</bitOffset>
17982 <bitWidth>1</bitWidth>
17983 </field>
17984 <field>
17985 <name>BOFF2</name>
17986 <description>DAC channel2 output buffer
17987 disable</description>
17988 <bitOffset>17</bitOffset>
17989 <bitWidth>1</bitWidth>
17990 </field>
17991 <field>
17992 <name>EN2</name>
17993 <description>DAC channel2 enable</description>
17994 <bitOffset>16</bitOffset>
17995 <bitWidth>1</bitWidth>
17996 </field>
17997 <field>
17998 <name>DMAUDRIE1</name>
17999 <description>DAC channel1 DMA Underrun Interrupt
18000 enable</description>
18001 <bitOffset>13</bitOffset>
18002 <bitWidth>1</bitWidth>
18003 </field>
18004 <field>
18005 <name>DMAEN1</name>
18006 <description>DAC channel1 DMA enable</description>
18007 <bitOffset>12</bitOffset>
18008 <bitWidth>1</bitWidth>
18009 </field>
18010 <field>
18011 <name>MAMP1</name>
18012 <description>DAC channel1 mask/amplitude
18013 selector</description>
18014 <bitOffset>8</bitOffset>
18015 <bitWidth>4</bitWidth>
18016 </field>
18017 <field>
18018 <name>WAVE1</name>
18019 <description>DAC channel1 noise/triangle wave
18020 generation enable</description>
18021 <bitOffset>6</bitOffset>
18022 <bitWidth>2</bitWidth>
18023 </field>
18024 <field>
18025 <name>TSEL1</name>
18026 <description>DAC channel1 trigger
18027 selection</description>
18028 <bitOffset>3</bitOffset>
18029 <bitWidth>3</bitWidth>
18030 </field>
18031 <field>
18032 <name>TEN1</name>
18033 <description>DAC channel1 trigger
18034 enable</description>
18035 <bitOffset>2</bitOffset>
18036 <bitWidth>1</bitWidth>
18037 </field>
18038 <field>
18039 <name>BOFF1</name>
18040 <description>DAC channel1 output buffer
18041 disable</description>
18042 <bitOffset>1</bitOffset>
18043 <bitWidth>1</bitWidth>
18044 </field>
18045 <field>
18046 <name>EN1</name>
18047 <description>DAC channel1 enable</description>
18048 <bitOffset>0</bitOffset>
18049 <bitWidth>1</bitWidth>
18050 </field>
18051 </fields>
18052 </register>
18053 <register>
18054 <name>SWTRIGR</name>
18055 <displayName>SWTRIGR</displayName>
18056 <description>software trigger register</description>
18057 <addressOffset>0x4</addressOffset>
18058 <size>0x20</size>
18059 <access>write-only</access>
18060 <resetValue>0x00000000</resetValue>
18061 <fields>
18062 <field>
18063 <name>SWTRIG2</name>
18064 <description>DAC channel2 software
18065 trigger</description>
18066 <bitOffset>1</bitOffset>
18067 <bitWidth>1</bitWidth>
18068 </field>
18069 <field>
18070 <name>SWTRIG1</name>
18071 <description>DAC channel1 software
18072 trigger</description>
18073 <bitOffset>0</bitOffset>
18074 <bitWidth>1</bitWidth>
18075 </field>
18076 </fields>
18077 </register>
18078 <register>
18079 <name>DHR12R1</name>
18080 <displayName>DHR12R1</displayName>
18081 <description>channel1 12-bit right-aligned data holding
18082 register</description>
18083 <addressOffset>0x8</addressOffset>
18084 <size>0x20</size>
18085 <access>read-write</access>
18086 <resetValue>0x00000000</resetValue>
18087 <fields>
18088 <field>
18089 <name>DACC1DHR</name>
18090 <description>DAC channel1 12-bit right-aligned
18091 data</description>
18092 <bitOffset>0</bitOffset>
18093 <bitWidth>12</bitWidth>
18094 </field>
18095 </fields>
18096 </register>
18097 <register>
18098 <name>DHR12L1</name>
18099 <displayName>DHR12L1</displayName>
18100 <description>channel1 12-bit left aligned data holding
18101 register</description>
18102 <addressOffset>0xC</addressOffset>
18103 <size>0x20</size>
18104 <access>read-write</access>
18105 <resetValue>0x00000000</resetValue>
18106 <fields>
18107 <field>
18108 <name>DACC1DHR</name>
18109 <description>DAC channel1 12-bit left-aligned
18110 data</description>
18111 <bitOffset>4</bitOffset>
18112 <bitWidth>12</bitWidth>
18113 </field>
18114 </fields>
18115 </register>
18116 <register>
18117 <name>DHR8R1</name>
18118 <displayName>DHR8R1</displayName>
18119 <description>channel1 8-bit right aligned data holding
18120 register</description>
18121 <addressOffset>0x10</addressOffset>
18122 <size>0x20</size>
18123 <access>read-write</access>
18124 <resetValue>0x00000000</resetValue>
18125 <fields>
18126 <field>
18127 <name>DACC1DHR</name>
18128 <description>DAC channel1 8-bit right-aligned
18129 data</description>
18130 <bitOffset>0</bitOffset>
18131 <bitWidth>8</bitWidth>
18132 </field>
18133 </fields>
18134 </register>
18135 <register>
18136 <name>DHR12R2</name>
18137 <displayName>DHR12R2</displayName>
18138 <description>channel2 12-bit right aligned data holding
18139 register</description>
18140 <addressOffset>0x14</addressOffset>
18141 <size>0x20</size>
18142 <access>read-write</access>
18143 <resetValue>0x00000000</resetValue>
18144 <fields>
18145 <field>
18146 <name>DACC2DHR</name>
18147 <description>DAC channel2 12-bit right-aligned
18148 data</description>
18149 <bitOffset>0</bitOffset>
18150 <bitWidth>12</bitWidth>
18151 </field>
18152 </fields>
18153 </register>
18154 <register>
18155 <name>DHR12L2</name>
18156 <displayName>DHR12L2</displayName>
18157 <description>channel2 12-bit left aligned data holding
18158 register</description>
18159 <addressOffset>0x18</addressOffset>
18160 <size>0x20</size>
18161 <access>read-write</access>
18162 <resetValue>0x00000000</resetValue>
18163 <fields>
18164 <field>
18165 <name>DACC2DHR</name>
18166 <description>DAC channel2 12-bit left-aligned
18167 data</description>
18168 <bitOffset>4</bitOffset>
18169 <bitWidth>12</bitWidth>
18170 </field>
18171 </fields>
18172 </register>
18173 <register>
18174 <name>DHR8R2</name>
18175 <displayName>DHR8R2</displayName>
18176 <description>channel2 8-bit right-aligned data holding
18177 register</description>
18178 <addressOffset>0x1C</addressOffset>
18179 <size>0x20</size>
18180 <access>read-write</access>
18181 <resetValue>0x00000000</resetValue>
18182 <fields>
18183 <field>
18184 <name>DACC2DHR</name>
18185 <description>DAC channel2 8-bit right-aligned
18186 data</description>
18187 <bitOffset>0</bitOffset>
18188 <bitWidth>8</bitWidth>
18189 </field>
18190 </fields>
18191 </register>
18192 <register>
18193 <name>DHR12RD</name>
18194 <displayName>DHR12RD</displayName>
18195 <description>Dual DAC 12-bit right-aligned data holding
18196 register</description>
18197 <addressOffset>0x20</addressOffset>
18198 <size>0x20</size>
18199 <access>read-write</access>
18200 <resetValue>0x00000000</resetValue>
18201 <fields>
18202 <field>
18203 <name>DACC2DHR</name>
18204 <description>DAC channel2 12-bit right-aligned
18205 data</description>
18206 <bitOffset>16</bitOffset>
18207 <bitWidth>12</bitWidth>
18208 </field>
18209 <field>
18210 <name>DACC1DHR</name>
18211 <description>DAC channel1 12-bit right-aligned
18212 data</description>
18213 <bitOffset>0</bitOffset>
18214 <bitWidth>12</bitWidth>
18215 </field>
18216 </fields>
18217 </register>
18218 <register>
18219 <name>DHR12LD</name>
18220 <displayName>DHR12LD</displayName>
18221 <description>DUAL DAC 12-bit left aligned data holding
18222 register</description>
18223 <addressOffset>0x24</addressOffset>
18224 <size>0x20</size>
18225 <access>read-write</access>
18226 <resetValue>0x00000000</resetValue>
18227 <fields>
18228 <field>
18229 <name>DACC2DHR</name>
18230 <description>DAC channel2 12-bit left-aligned
18231 data</description>
18232 <bitOffset>20</bitOffset>
18233 <bitWidth>12</bitWidth>
18234 </field>
18235 <field>
18236 <name>DACC1DHR</name>
18237 <description>DAC channel1 12-bit left-aligned
18238 data</description>
18239 <bitOffset>4</bitOffset>
18240 <bitWidth>12</bitWidth>
18241 </field>
18242 </fields>
18243 </register>
18244 <register>
18245 <name>DHR8RD</name>
18246 <displayName>DHR8RD</displayName>
18247 <description>DUAL DAC 8-bit right aligned data holding
18248 register</description>
18249 <addressOffset>0x28</addressOffset>
18250 <size>0x20</size>
18251 <access>read-write</access>
18252 <resetValue>0x00000000</resetValue>
18253 <fields>
18254 <field>
18255 <name>DACC2DHR</name>
18256 <description>DAC channel2 8-bit right-aligned
18257 data</description>
18258 <bitOffset>8</bitOffset>
18259 <bitWidth>8</bitWidth>
18260 </field>
18261 <field>
18262 <name>DACC1DHR</name>
18263 <description>DAC channel1 8-bit right-aligned
18264 data</description>
18265 <bitOffset>0</bitOffset>
18266 <bitWidth>8</bitWidth>
18267 </field>
18268 </fields>
18269 </register>
18270 <register>
18271 <name>DOR1</name>
18272 <displayName>DOR1</displayName>
18273 <description>channel1 data output register</description>
18274 <addressOffset>0x2C</addressOffset>
18275 <size>0x20</size>
18276 <access>read-only</access>
18277 <resetValue>0x00000000</resetValue>
18278 <fields>
18279 <field>
18280 <name>DACC1DOR</name>
18281 <description>DAC channel1 data output</description>
18282 <bitOffset>0</bitOffset>
18283 <bitWidth>12</bitWidth>
18284 </field>
18285 </fields>
18286 </register>
18287 <register>
18288 <name>DOR2</name>
18289 <displayName>DOR2</displayName>
18290 <description>channel2 data output register</description>
18291 <addressOffset>0x30</addressOffset>
18292 <size>0x20</size>
18293 <access>read-only</access>
18294 <resetValue>0x00000000</resetValue>
18295 <fields>
18296 <field>
18297 <name>DACC2DOR</name>
18298 <description>DAC channel2 data output</description>
18299 <bitOffset>0</bitOffset>
18300 <bitWidth>12</bitWidth>
18301 </field>
18302 </fields>
18303 </register>
18304 <register>
18305 <name>SR</name>
18306 <displayName>SR</displayName>
18307 <description>status register</description>
18308 <addressOffset>0x34</addressOffset>
18309 <size>0x20</size>
18310 <access>read-write</access>
18311 <resetValue>0x00000000</resetValue>
18312 <fields>
18313 <field>
18314 <name>DMAUDR2</name>
18315 <description>DAC channel2 DMA underrun
18316 flag</description>
18317 <bitOffset>29</bitOffset>
18318 <bitWidth>1</bitWidth>
18319 </field>
18320 <field>
18321 <name>DMAUDR1</name>
18322 <description>DAC channel1 DMA underrun
18323 flag</description>
18324 <bitOffset>13</bitOffset>
18325 <bitWidth>1</bitWidth>
18326 </field>
18327 </fields>
18328 </register>
18329 </registers>
18330 </peripheral>
18331 <peripheral>
18332 <name>PWR</name>
18333 <description>Power control</description>
18334 <groupName>PWR</groupName>
18335 <baseAddress>0x40007000</baseAddress>
18336 <addressBlock>
18337 <offset>0x0</offset>
18338 <size>0x400</size>
18339 <usage>registers</usage>
18340 </addressBlock>
18341 <registers>
18342 <register>
18343 <name>CR1</name>
18344 <displayName>CR1</displayName>
18345 <description>power control register</description>
18346 <addressOffset>0x0</addressOffset>
18347 <size>0x20</size>
18348 <access>read-write</access>
18349 <resetValue>0x0000C000</resetValue>
18350 <fields>
18351 <field>
18352 <name>LPDS</name>
18353 <description>Low-power deep sleep</description>
18354 <bitOffset>0</bitOffset>
18355 <bitWidth>1</bitWidth>
18356 </field>
18357 <field>
18358 <name>PDDS</name>
18359 <description>Power down deepsleep</description>
18360 <bitOffset>1</bitOffset>
18361 <bitWidth>1</bitWidth>
18362 </field>
18363 <field>
18364 <name>CSBF</name>
18365 <description>Clear standby flag</description>
18366 <bitOffset>3</bitOffset>
18367 <bitWidth>1</bitWidth>
18368 </field>
18369 <field>
18370 <name>PVDE</name>
18371 <description>Power voltage detector
18372 enable</description>
18373 <bitOffset>4</bitOffset>
18374 <bitWidth>1</bitWidth>
18375 </field>
18376 <field>
18377 <name>PLS</name>
18378 <description>PVD level selection</description>
18379 <bitOffset>5</bitOffset>
18380 <bitWidth>3</bitWidth>
18381 </field>
18382 <field>
18383 <name>DBP</name>
18384 <description>Disable backup domain write
18385 protection</description>
18386 <bitOffset>8</bitOffset>
18387 <bitWidth>1</bitWidth>
18388 </field>
18389 <field>
18390 <name>FPDS</name>
18391 <description>Flash power down in Stop
18392 mode</description>
18393 <bitOffset>9</bitOffset>
18394 <bitWidth>1</bitWidth>
18395 </field>
18396 <field>
18397 <name>LPUDS</name>
18398 <description>Low-power regulator in deepsleep
18399 under-drive mode</description>
18400 <bitOffset>10</bitOffset>
18401 <bitWidth>1</bitWidth>
18402 </field>
18403 <field>
18404 <name>MRUDS</name>
18405 <description>Main regulator in deepsleep under-drive
18406 mode</description>
18407 <bitOffset>11</bitOffset>
18408 <bitWidth>1</bitWidth>
18409 </field>
18410 <field>
18411 <name>ADCDC1</name>
18412 <description>ADCDC1</description>
18413 <bitOffset>13</bitOffset>
18414 <bitWidth>1</bitWidth>
18415 </field>
18416 <field>
18417 <name>VOS</name>
18418 <description>Regulator voltage scaling output
18419 selection</description>
18420 <bitOffset>14</bitOffset>
18421 <bitWidth>2</bitWidth>
18422 </field>
18423 <field>
18424 <name>ODEN</name>
18425 <description>Over-drive enable</description>
18426 <bitOffset>16</bitOffset>
18427 <bitWidth>1</bitWidth>
18428 </field>
18429 <field>
18430 <name>ODSWEN</name>
18431 <description>Over-drive switching
18432 enabled</description>
18433 <bitOffset>17</bitOffset>
18434 <bitWidth>1</bitWidth>
18435 </field>
18436 <field>
18437 <name>UDEN</name>
18438 <description>Under-drive enable in stop
18439 mode</description>
18440 <bitOffset>18</bitOffset>
18441 <bitWidth>2</bitWidth>
18442 </field>
18443 </fields>
18444 </register>
18445 <register>
18446 <name>CSR1</name>
18447 <displayName>CSR1</displayName>
18448 <description>power control/status register</description>
18449 <addressOffset>0x4</addressOffset>
18450 <size>0x20</size>
18451 <resetValue>0x00000000</resetValue>
18452 <fields>
18453 <field>
18454 <name>WUIF</name>
18455 <description>Wakeup internal flag</description>
18456 <bitOffset>0</bitOffset>
18457 <bitWidth>1</bitWidth>
18458 <access>read-only</access>
18459 </field>
18460 <field>
18461 <name>SBF</name>
18462 <description>Standby flag</description>
18463 <bitOffset>1</bitOffset>
18464 <bitWidth>1</bitWidth>
18465 <access>read-only</access>
18466 </field>
18467 <field>
18468 <name>PVDO</name>
18469 <description>PVD output</description>
18470 <bitOffset>2</bitOffset>
18471 <bitWidth>1</bitWidth>
18472 <access>read-only</access>
18473 </field>
18474 <field>
18475 <name>BRR</name>
18476 <description>Backup regulator ready</description>
18477 <bitOffset>3</bitOffset>
18478 <bitWidth>1</bitWidth>
18479 <access>read-only</access>
18480 </field>
18481 <field>
18482 <name>BRE</name>
18483 <description>Backup regulator enable</description>
18484 <bitOffset>9</bitOffset>
18485 <bitWidth>1</bitWidth>
18486 <access>read-write</access>
18487 </field>
18488 <field>
18489 <name>VOSRDY</name>
18490 <description>Regulator voltage scaling output
18491 selection ready bit</description>
18492 <bitOffset>14</bitOffset>
18493 <bitWidth>1</bitWidth>
18494 <access>read-write</access>
18495 </field>
18496 <field>
18497 <name>ODRDY</name>
18498 <description>Over-drive mode ready</description>
18499 <bitOffset>16</bitOffset>
18500 <bitWidth>1</bitWidth>
18501 <access>read-write</access>
18502 </field>
18503 <field>
18504 <name>ODSWRDY</name>
18505 <description>Over-drive mode switching
18506 ready</description>
18507 <bitOffset>17</bitOffset>
18508 <bitWidth>1</bitWidth>
18509 <access>read-write</access>
18510 </field>
18511 <field>
18512 <name>UDRDY</name>
18513 <description>Under-drive ready flag</description>
18514 <bitOffset>18</bitOffset>
18515 <bitWidth>2</bitWidth>
18516 <access>read-write</access>
18517 </field>
18518 </fields>
18519 </register>
18520 <register>
18521 <name>CR2</name>
18522 <displayName>CR2</displayName>
18523 <description>power control register</description>
18524 <addressOffset>0x8</addressOffset>
18525 <size>0x20</size>
18526 <resetValue>0x00000000</resetValue>
18527 <fields>
18528 <field>
18529 <name>CWUPF1</name>
18530 <description>Clear Wakeup Pin flag for
18531 PA0</description>
18532 <bitOffset>0</bitOffset>
18533 <bitWidth>1</bitWidth>
18534 <access>read-only</access>
18535 </field>
18536 <field>
18537 <name>CWUPF2</name>
18538 <description>Clear Wakeup Pin flag for
18539 PA2</description>
18540 <bitOffset>1</bitOffset>
18541 <bitWidth>1</bitWidth>
18542 <access>read-only</access>
18543 </field>
18544 <field>
18545 <name>CWUPF3</name>
18546 <description>Clear Wakeup Pin flag for
18547 PC1</description>
18548 <bitOffset>2</bitOffset>
18549 <bitWidth>1</bitWidth>
18550 <access>read-only</access>
18551 </field>
18552 <field>
18553 <name>CWUPF4</name>
18554 <description>Clear Wakeup Pin flag for
18555 PC13</description>
18556 <bitOffset>3</bitOffset>
18557 <bitWidth>1</bitWidth>
18558 <access>read-only</access>
18559 </field>
18560 <field>
18561 <name>CWUPF5</name>
18562 <description>Clear Wakeup Pin flag for
18563 PI8</description>
18564 <bitOffset>4</bitOffset>
18565 <bitWidth>1</bitWidth>
18566 <access>read-only</access>
18567 </field>
18568 <field>
18569 <name>CWUPF6</name>
18570 <description>Clear Wakeup Pin flag for
18571 PI11</description>
18572 <bitOffset>5</bitOffset>
18573 <bitWidth>1</bitWidth>
18574 <access>read-only</access>
18575 </field>
18576 <field>
18577 <name>WUPP1</name>
18578 <description>Wakeup pin polarity bit for
18579 PA0</description>
18580 <bitOffset>8</bitOffset>
18581 <bitWidth>1</bitWidth>
18582 <access>read-write</access>
18583 </field>
18584 <field>
18585 <name>WUPP2</name>
18586 <description>Wakeup pin polarity bit for
18587 PA2</description>
18588 <bitOffset>9</bitOffset>
18589 <bitWidth>1</bitWidth>
18590 <access>read-write</access>
18591 </field>
18592 <field>
18593 <name>WUPP3</name>
18594 <description>Wakeup pin polarity bit for
18595 PC1</description>
18596 <bitOffset>10</bitOffset>
18597 <bitWidth>1</bitWidth>
18598 <access>read-write</access>
18599 </field>
18600 <field>
18601 <name>WUPP4</name>
18602 <description>Wakeup pin polarity bit for
18603 PC13</description>
18604 <bitOffset>11</bitOffset>
18605 <bitWidth>1</bitWidth>
18606 <access>read-write</access>
18607 </field>
18608 <field>
18609 <name>WUPP5</name>
18610 <description>Wakeup pin polarity bit for
18611 PI8</description>
18612 <bitOffset>12</bitOffset>
18613 <bitWidth>1</bitWidth>
18614 <access>read-write</access>
18615 </field>
18616 <field>
18617 <name>WUPP6</name>
18618 <description>Wakeup pin polarity bit for
18619 PI11</description>
18620 <bitOffset>13</bitOffset>
18621 <bitWidth>1</bitWidth>
18622 <access>read-write</access>
18623 </field>
18624 </fields>
18625 </register>
18626 <register>
18627 <name>CSR2</name>
18628 <displayName>CSR2</displayName>
18629 <description>power control/status register</description>
18630 <addressOffset>0xC</addressOffset>
18631 <size>0x20</size>
18632 <resetValue>0x00000000</resetValue>
18633 <fields>
18634 <field>
18635 <name>WUPF1</name>
18636 <description>Wakeup Pin flag for PA0</description>
18637 <bitOffset>0</bitOffset>
18638 <bitWidth>1</bitWidth>
18639 <access>read-only</access>
18640 </field>
18641 <field>
18642 <name>WUPF2</name>
18643 <description>Wakeup Pin flag for PA2</description>
18644 <bitOffset>1</bitOffset>
18645 <bitWidth>1</bitWidth>
18646 <access>read-only</access>
18647 </field>
18648 <field>
18649 <name>WUPF3</name>
18650 <description>Wakeup Pin flag for PC1</description>
18651 <bitOffset>2</bitOffset>
18652 <bitWidth>1</bitWidth>
18653 <access>read-only</access>
18654 </field>
18655 <field>
18656 <name>WUPF4</name>
18657 <description>Wakeup Pin flag for PC13</description>
18658 <bitOffset>3</bitOffset>
18659 <bitWidth>1</bitWidth>
18660 <access>read-only</access>
18661 </field>
18662 <field>
18663 <name>WUPF5</name>
18664 <description>Wakeup Pin flag for PI8</description>
18665 <bitOffset>4</bitOffset>
18666 <bitWidth>1</bitWidth>
18667 <access>read-only</access>
18668 </field>
18669 <field>
18670 <name>WUPF6</name>
18671 <description>Wakeup Pin flag for PI11</description>
18672 <bitOffset>5</bitOffset>
18673 <bitWidth>1</bitWidth>
18674 <access>read-only</access>
18675 </field>
18676 <field>
18677 <name>EWUP1</name>
18678 <description>Enable Wakeup pin for PA0</description>
18679 <bitOffset>8</bitOffset>
18680 <bitWidth>1</bitWidth>
18681 <access>read-write</access>
18682 </field>
18683 <field>
18684 <name>EWUP2</name>
18685 <description>Enable Wakeup pin for PA2</description>
18686 <bitOffset>9</bitOffset>
18687 <bitWidth>1</bitWidth>
18688 <access>read-write</access>
18689 </field>
18690 <field>
18691 <name>EWUP3</name>
18692 <description>Enable Wakeup pin for PC1</description>
18693 <bitOffset>10</bitOffset>
18694 <bitWidth>1</bitWidth>
18695 <access>read-write</access>
18696 </field>
18697 <field>
18698 <name>EWUP4</name>
18699 <description>Enable Wakeup pin for PC13</description>
18700 <bitOffset>11</bitOffset>
18701 <bitWidth>1</bitWidth>
18702 <access>read-write</access>
18703 </field>
18704 <field>
18705 <name>EWUP5</name>
18706 <description>Enable Wakeup pin for PI8</description>
18707 <bitOffset>12</bitOffset>
18708 <bitWidth>1</bitWidth>
18709 <access>read-write</access>
18710 </field>
18711 <field>
18712 <name>EWUP6</name>
18713 <description>Enable Wakeup pin for PI11</description>
18714 <bitOffset>13</bitOffset>
18715 <bitWidth>1</bitWidth>
18716 <access>read-write</access>
18717 </field>
18718 </fields>
18719 </register>
18720 </registers>
18721 </peripheral>
18722 <peripheral>
18723 <name>IWDG</name>
18724 <description>Independent watchdog</description>
18725 <groupName>IWDG</groupName>
18726 <baseAddress>0x40003000</baseAddress>
18727 <addressBlock>
18728 <offset>0x0</offset>
18729 <size>0x400</size>
18730 <usage>registers</usage>
18731 </addressBlock>
18732 <registers>
18733 <register>
18734 <name>KR</name>
18735 <displayName>KR</displayName>
18736 <description>Key register</description>
18737 <addressOffset>0x0</addressOffset>
18738 <size>0x20</size>
18739 <access>write-only</access>
18740 <resetValue>0x00000000</resetValue>
18741 <fields>
18742 <field>
18743 <name>KEY</name>
18744 <description>Key value (write only, read
18745 0000h)</description>
18746 <bitOffset>0</bitOffset>
18747 <bitWidth>16</bitWidth>
18748 </field>
18749 </fields>
18750 </register>
18751 <register>
18752 <name>PR</name>
18753 <displayName>PR</displayName>
18754 <description>Prescaler register</description>
18755 <addressOffset>0x4</addressOffset>
18756 <size>0x20</size>
18757 <access>read-write</access>
18758 <resetValue>0x00000000</resetValue>
18759 <fields>
18760 <field>
18761 <name>PR</name>
18762 <description>Prescaler divider</description>
18763 <bitOffset>0</bitOffset>
18764 <bitWidth>3</bitWidth>
18765 </field>
18766 </fields>
18767 </register>
18768 <register>
18769 <name>RLR</name>
18770 <displayName>RLR</displayName>
18771 <description>Reload register</description>
18772 <addressOffset>0x8</addressOffset>
18773 <size>0x20</size>
18774 <access>read-write</access>
18775 <resetValue>0x00000FFF</resetValue>
18776 <fields>
18777 <field>
18778 <name>RL</name>
18779 <description>Watchdog counter reload
18780 value</description>
18781 <bitOffset>0</bitOffset>
18782 <bitWidth>12</bitWidth>
18783 </field>
18784 </fields>
18785 </register>
18786 <register>
18787 <name>SR</name>
18788 <displayName>SR</displayName>
18789 <description>Status register</description>
18790 <addressOffset>0xC</addressOffset>
18791 <size>0x20</size>
18792 <access>read-only</access>
18793 <resetValue>0x00000000</resetValue>
18794 <fields>
18795 <field>
18796 <name>RVU</name>
18797 <description>Watchdog counter reload value
18798 update</description>
18799 <bitOffset>1</bitOffset>
18800 <bitWidth>1</bitWidth>
18801 </field>
18802 <field>
18803 <name>PVU</name>
18804 <description>Watchdog prescaler value
18805 update</description>
18806 <bitOffset>0</bitOffset>
18807 <bitWidth>1</bitWidth>
18808 </field>
18809 </fields>
18810 </register>
18811 <register>
18812 <name>WINR</name>
18813 <displayName>WINR</displayName>
18814 <description>Window register</description>
18815 <addressOffset>0x10</addressOffset>
18816 <size>0x20</size>
18817 <access>read-write</access>
18818 <resetValue>0x00000000</resetValue>
18819 <fields>
18820 <field>
18821 <name>WIN</name>
18822 <description>Watchdog counter window
18823 value</description>
18824 <bitOffset>0</bitOffset>
18825 <bitWidth>12</bitWidth>
18826 </field>
18827 </fields>
18828 </register>
18829 </registers>
18830 </peripheral>
18831 <peripheral>
18832 <name>WWDG</name>
18833 <description>Window watchdog</description>
18834 <groupName>WWDG</groupName>
18835 <baseAddress>0x40002C00</baseAddress>
18836 <addressBlock>
18837 <offset>0x0</offset>
18838 <size>0x400</size>
18839 <usage>registers</usage>
18840 </addressBlock>
18841 <interrupt>
18842 <name>WWDG</name>
18843 <description>Window Watchdog interrupt</description>
18844 <value>0</value>
18845 </interrupt>
18846 <registers>
18847 <register>
18848 <name>CR</name>
18849 <displayName>CR</displayName>
18850 <description>Control register</description>
18851 <addressOffset>0x0</addressOffset>
18852 <size>0x20</size>
18853 <access>read-write</access>
18854 <resetValue>0x7F</resetValue>
18855 <fields>
18856 <field>
18857 <name>WDGA</name>
18858 <description>Activation bit</description>
18859 <bitOffset>7</bitOffset>
18860 <bitWidth>1</bitWidth>
18861 </field>
18862 <field>
18863 <name>T</name>
18864 <description>7-bit counter (MSB to LSB)</description>
18865 <bitOffset>0</bitOffset>
18866 <bitWidth>7</bitWidth>
18867 </field>
18868 </fields>
18869 </register>
18870 <register>
18871 <name>CFR</name>
18872 <displayName>CFR</displayName>
18873 <description>Configuration register</description>
18874 <addressOffset>0x4</addressOffset>
18875 <size>0x20</size>
18876 <access>read-write</access>
18877 <resetValue>0x7F</resetValue>
18878 <fields>
18879 <field>
18880 <name>EWI</name>
18881 <description>Early wakeup interrupt</description>
18882 <bitOffset>9</bitOffset>
18883 <bitWidth>1</bitWidth>
18884 </field>
18885 <field>
18886 <name>WDGTB1</name>
18887 <description>Timer base</description>
18888 <bitOffset>8</bitOffset>
18889 <bitWidth>1</bitWidth>
18890 </field>
18891 <field>
18892 <name>WDGTB0</name>
18893 <description>Timer base</description>
18894 <bitOffset>7</bitOffset>
18895 <bitWidth>1</bitWidth>
18896 </field>
18897 <field>
18898 <name>W</name>
18899 <description>7-bit window value</description>
18900 <bitOffset>0</bitOffset>
18901 <bitWidth>7</bitWidth>
18902 </field>
18903 </fields>
18904 </register>
18905 <register>
18906 <name>SR</name>
18907 <displayName>SR</displayName>
18908 <description>Status register</description>
18909 <addressOffset>0x8</addressOffset>
18910 <size>0x20</size>
18911 <access>read-write</access>
18912 <resetValue>0x00</resetValue>
18913 <fields>
18914 <field>
18915 <name>EWIF</name>
18916 <description>Early wakeup interrupt
18917 flag</description>
18918 <bitOffset>0</bitOffset>
18919 <bitWidth>1</bitWidth>
18920 </field>
18921 </fields>
18922 </register>
18923 </registers>
18924 </peripheral>
18925 <peripheral>
18926 <name>C_ADC</name>
18927 <description>Common ADC registers</description>
18928 <groupName>ADC</groupName>
18929 <baseAddress>0x40012300</baseAddress>
18930 <addressBlock>
18931 <offset>0x0</offset>
18932 <size>0x400</size>
18933 <usage>registers</usage>
18934 </addressBlock>
18935 <registers>
18936 <register>
18937 <name>CSR</name>
18938 <displayName>CSR</displayName>
18939 <description>ADC Common status register</description>
18940 <addressOffset>0x0</addressOffset>
18941 <size>0x20</size>
18942 <access>read-only</access>
18943 <resetValue>0x00000000</resetValue>
18944 <fields>
18945 <field>
18946 <name>OVR3</name>
18947 <description>Overrun flag of ADC3</description>
18948 <bitOffset>21</bitOffset>
18949 <bitWidth>1</bitWidth>
18950 </field>
18951 <field>
18952 <name>STRT3</name>
18953 <description>Regular channel Start flag of ADC
18954 3</description>
18955 <bitOffset>20</bitOffset>
18956 <bitWidth>1</bitWidth>
18957 </field>
18958 <field>
18959 <name>JSTRT3</name>
18960 <description>Injected channel Start flag of ADC
18961 3</description>
18962 <bitOffset>19</bitOffset>
18963 <bitWidth>1</bitWidth>
18964 </field>
18965 <field>
18966 <name>JEOC3</name>
18967 <description>Injected channel end of conversion of
18968 ADC 3</description>
18969 <bitOffset>18</bitOffset>
18970 <bitWidth>1</bitWidth>
18971 </field>
18972 <field>
18973 <name>EOC3</name>
18974 <description>End of conversion of ADC 3</description>
18975 <bitOffset>17</bitOffset>
18976 <bitWidth>1</bitWidth>
18977 </field>
18978 <field>
18979 <name>AWD3</name>
18980 <description>Analog watchdog flag of ADC
18981 3</description>
18982 <bitOffset>16</bitOffset>
18983 <bitWidth>1</bitWidth>
18984 </field>
18985 <field>
18986 <name>OVR2</name>
18987 <description>Overrun flag of ADC 2</description>
18988 <bitOffset>13</bitOffset>
18989 <bitWidth>1</bitWidth>
18990 </field>
18991 <field>
18992 <name>STRT2</name>
18993 <description>Regular channel Start flag of ADC
18994 2</description>
18995 <bitOffset>12</bitOffset>
18996 <bitWidth>1</bitWidth>
18997 </field>
18998 <field>
18999 <name>JSTRT2</name>
19000 <description>Injected channel Start flag of ADC
19001 2</description>
19002 <bitOffset>11</bitOffset>
19003 <bitWidth>1</bitWidth>
19004 </field>
19005 <field>
19006 <name>JEOC2</name>
19007 <description>Injected channel end of conversion of
19008 ADC 2</description>
19009 <bitOffset>10</bitOffset>
19010 <bitWidth>1</bitWidth>
19011 </field>
19012 <field>
19013 <name>EOC2</name>
19014 <description>End of conversion of ADC 2</description>
19015 <bitOffset>9</bitOffset>
19016 <bitWidth>1</bitWidth>
19017 </field>
19018 <field>
19019 <name>AWD2</name>
19020 <description>Analog watchdog flag of ADC
19021 2</description>
19022 <bitOffset>8</bitOffset>
19023 <bitWidth>1</bitWidth>
19024 </field>
19025 <field>
19026 <name>OVR1</name>
19027 <description>Overrun flag of ADC 1</description>
19028 <bitOffset>5</bitOffset>
19029 <bitWidth>1</bitWidth>
19030 </field>
19031 <field>
19032 <name>STRT1</name>
19033 <description>Regular channel Start flag of ADC
19034 1</description>
19035 <bitOffset>4</bitOffset>
19036 <bitWidth>1</bitWidth>
19037 </field>
19038 <field>
19039 <name>JSTRT1</name>
19040 <description>Injected channel Start flag of ADC
19041 1</description>
19042 <bitOffset>3</bitOffset>
19043 <bitWidth>1</bitWidth>
19044 </field>
19045 <field>
19046 <name>JEOC1</name>
19047 <description>Injected channel end of conversion of
19048 ADC 1</description>
19049 <bitOffset>2</bitOffset>
19050 <bitWidth>1</bitWidth>
19051 </field>
19052 <field>
19053 <name>EOC1</name>
19054 <description>End of conversion of ADC 1</description>
19055 <bitOffset>1</bitOffset>
19056 <bitWidth>1</bitWidth>
19057 </field>
19058 <field>
19059 <name>AWD1</name>
19060 <description>Analog watchdog flag of ADC
19061 1</description>
19062 <bitOffset>0</bitOffset>
19063 <bitWidth>1</bitWidth>
19064 </field>
19065 </fields>
19066 </register>
19067 <register>
19068 <name>CCR</name>
19069 <displayName>CCR</displayName>
19070 <description>ADC common control register</description>
19071 <addressOffset>0x4</addressOffset>
19072 <size>0x20</size>
19073 <access>read-write</access>
19074 <resetValue>0x00000000</resetValue>
19075 <fields>
19076 <field>
19077 <name>TSVREFE</name>
19078 <description>Temperature sensor and VREFINT
19079 enable</description>
19080 <bitOffset>23</bitOffset>
19081 <bitWidth>1</bitWidth>
19082 </field>
19083 <field>
19084 <name>VBATE</name>
19085 <description>VBAT enable</description>
19086 <bitOffset>22</bitOffset>
19087 <bitWidth>1</bitWidth>
19088 </field>
19089 <field>
19090 <name>ADCPRE</name>
19091 <description>ADC prescaler</description>
19092 <bitOffset>16</bitOffset>
19093 <bitWidth>2</bitWidth>
19094 </field>
19095 <field>
19096 <name>DMA</name>
19097 <description>Direct memory access mode for multi ADC
19098 mode</description>
19099 <bitOffset>14</bitOffset>
19100 <bitWidth>2</bitWidth>
19101 </field>
19102 <field>
19103 <name>DDS</name>
19104 <description>DMA disable selection for multi-ADC
19105 mode</description>
19106 <bitOffset>13</bitOffset>
19107 <bitWidth>1</bitWidth>
19108 </field>
19109 <field>
19110 <name>DELAY</name>
19111 <description>Delay between 2 sampling
19112 phases</description>
19113 <bitOffset>8</bitOffset>
19114 <bitWidth>4</bitWidth>
19115 </field>
19116 <field>
19117 <name>MULT</name>
19118 <description>Multi ADC mode selection</description>
19119 <bitOffset>0</bitOffset>
19120 <bitWidth>5</bitWidth>
19121 </field>
19122 </fields>
19123 </register>
19124 <register>
19125 <name>CDR</name>
19126 <displayName>CDR</displayName>
19127 <description>ADC common regular data register for dual
19128 and triple modes</description>
19129 <addressOffset>0x8</addressOffset>
19130 <size>0x20</size>
19131 <access>read-only</access>
19132 <resetValue>0x00000000</resetValue>
19133 <fields>
19134 <field>
19135 <name>DATA2</name>
19136 <description>2nd data item of a pair of regular
19137 conversions</description>
19138 <bitOffset>16</bitOffset>
19139 <bitWidth>16</bitWidth>
19140 </field>
19141 <field>
19142 <name>DATA1</name>
19143 <description>1st data item of a pair of regular
19144 conversions</description>
19145 <bitOffset>0</bitOffset>
19146 <bitWidth>16</bitWidth>
19147 </field>
19148 </fields>
19149 </register>
19150 </registers>
19151 </peripheral>
19152 <peripheral>
19153 <name>TIM1</name>
19154 <description>Advanced-timers</description>
19155 <groupName>TIM</groupName>
19156 <baseAddress>0x40010000</baseAddress>
19157 <addressBlock>
19158 <offset>0x0</offset>
19159 <size>0x400</size>
19160 <usage>registers</usage>
19161 </addressBlock>
19162 <interrupt>
19163 <name>TIM1_BRK_TIM9</name>
19164 <description>TIM1 Break interrupt and TIM9 global
19165 interrupt</description>
19166 <value>24</value>
19167 </interrupt>
19168 <interrupt>
19169 <name>TIM1_TRG_COM_TIM11</name>
19170 <description>TIM1 Trigger and Commutation interrupts and
19171 TIM11 global interrupt</description>
19172 <value>26</value>
19173 </interrupt>
19174 <registers>
19175 <register>
19176 <name>CR1</name>
19177 <displayName>CR1</displayName>
19178 <description>control register 1</description>
19179 <addressOffset>0x0</addressOffset>
19180 <size>0x20</size>
19181 <access>read-write</access>
19182 <resetValue>0x0000</resetValue>
19183 <fields>
19184 <field>
19185 <name>CKD</name>
19186 <description>Clock division</description>
19187 <bitOffset>8</bitOffset>
19188 <bitWidth>2</bitWidth>
19189 </field>
19190 <field>
19191 <name>ARPE</name>
19192 <description>Auto-reload preload enable</description>
19193 <bitOffset>7</bitOffset>
19194 <bitWidth>1</bitWidth>
19195 </field>
19196 <field>
19197 <name>CMS</name>
19198 <description>Center-aligned mode
19199 selection</description>
19200 <bitOffset>5</bitOffset>
19201 <bitWidth>2</bitWidth>
19202 </field>
19203 <field>
19204 <name>DIR</name>
19205 <description>Direction</description>
19206 <bitOffset>4</bitOffset>
19207 <bitWidth>1</bitWidth>
19208 </field>
19209 <field>
19210 <name>OPM</name>
19211 <description>One-pulse mode</description>
19212 <bitOffset>3</bitOffset>
19213 <bitWidth>1</bitWidth>
19214 </field>
19215 <field>
19216 <name>URS</name>
19217 <description>Update request source</description>
19218 <bitOffset>2</bitOffset>
19219 <bitWidth>1</bitWidth>
19220 </field>
19221 <field>
19222 <name>UDIS</name>
19223 <description>Update disable</description>
19224 <bitOffset>1</bitOffset>
19225 <bitWidth>1</bitWidth>
19226 </field>
19227 <field>
19228 <name>CEN</name>
19229 <description>Counter enable</description>
19230 <bitOffset>0</bitOffset>
19231 <bitWidth>1</bitWidth>
19232 </field>
19233 </fields>
19234 </register>
19235 <register>
19236 <name>CR2</name>
19237 <displayName>CR2</displayName>
19238 <description>control register 2</description>
19239 <addressOffset>0x4</addressOffset>
19240 <size>0x20</size>
19241 <access>read-write</access>
19242 <resetValue>0x0000</resetValue>
19243 <fields>
19244 <field>
19245 <name>OIS4</name>
19246 <description>Output Idle state 4</description>
19247 <bitOffset>14</bitOffset>
19248 <bitWidth>1</bitWidth>
19249 </field>
19250 <field>
19251 <name>OIS3N</name>
19252 <description>Output Idle state 3</description>
19253 <bitOffset>13</bitOffset>
19254 <bitWidth>1</bitWidth>
19255 </field>
19256 <field>
19257 <name>OIS3</name>
19258 <description>Output Idle state 3</description>
19259 <bitOffset>12</bitOffset>
19260 <bitWidth>1</bitWidth>
19261 </field>
19262 <field>
19263 <name>OIS2N</name>
19264 <description>Output Idle state 2</description>
19265 <bitOffset>11</bitOffset>
19266 <bitWidth>1</bitWidth>
19267 </field>
19268 <field>
19269 <name>OIS2</name>
19270 <description>Output Idle state 2</description>
19271 <bitOffset>10</bitOffset>
19272 <bitWidth>1</bitWidth>
19273 </field>
19274 <field>
19275 <name>OIS1N</name>
19276 <description>Output Idle state 1</description>
19277 <bitOffset>9</bitOffset>
19278 <bitWidth>1</bitWidth>
19279 </field>
19280 <field>
19281 <name>OIS1</name>
19282 <description>Output Idle state 1</description>
19283 <bitOffset>8</bitOffset>
19284 <bitWidth>1</bitWidth>
19285 </field>
19286 <field>
19287 <name>TI1S</name>
19288 <description>TI1 selection</description>
19289 <bitOffset>7</bitOffset>
19290 <bitWidth>1</bitWidth>
19291 </field>
19292 <field>
19293 <name>MMS</name>
19294 <description>Master mode selection</description>
19295 <bitOffset>4</bitOffset>
19296 <bitWidth>3</bitWidth>
19297 </field>
19298 <field>
19299 <name>CCDS</name>
19300 <description>Capture/compare DMA
19301 selection</description>
19302 <bitOffset>3</bitOffset>
19303 <bitWidth>1</bitWidth>
19304 </field>
19305 <field>
19306 <name>CCUS</name>
19307 <description>Capture/compare control update
19308 selection</description>
19309 <bitOffset>2</bitOffset>
19310 <bitWidth>1</bitWidth>
19311 </field>
19312 <field>
19313 <name>CCPC</name>
19314 <description>Capture/compare preloaded
19315 control</description>
19316 <bitOffset>0</bitOffset>
19317 <bitWidth>1</bitWidth>
19318 </field>
19319 </fields>
19320 </register>
19321 <register>
19322 <name>SMCR</name>
19323 <displayName>SMCR</displayName>
19324 <description>slave mode control register</description>
19325 <addressOffset>0x8</addressOffset>
19326 <size>0x20</size>
19327 <access>read-write</access>
19328 <resetValue>0x0000</resetValue>
19329 <fields>
19330 <field>
19331 <name>SMS_3</name>
19332 <description>Slave model selection -
19333 bit[3]</description>
19334 <bitOffset>16</bitOffset>
19335 <bitWidth>1</bitWidth>
19336 </field>
19337 <field>
19338 <name>ETP</name>
19339 <description>External trigger polarity</description>
19340 <bitOffset>15</bitOffset>
19341 <bitWidth>1</bitWidth>
19342 </field>
19343 <field>
19344 <name>ECE</name>
19345 <description>External clock enable</description>
19346 <bitOffset>14</bitOffset>
19347 <bitWidth>1</bitWidth>
19348 </field>
19349 <field>
19350 <name>ETPS</name>
19351 <description>External trigger prescaler</description>
19352 <bitOffset>12</bitOffset>
19353 <bitWidth>2</bitWidth>
19354 </field>
19355 <field>
19356 <name>ETF</name>
19357 <description>External trigger filter</description>
19358 <bitOffset>8</bitOffset>
19359 <bitWidth>4</bitWidth>
19360 </field>
19361 <field>
19362 <name>MSM</name>
19363 <description>Master/Slave mode</description>
19364 <bitOffset>7</bitOffset>
19365 <bitWidth>1</bitWidth>
19366 </field>
19367 <field>
19368 <name>TS</name>
19369 <description>Trigger selection</description>
19370 <bitOffset>4</bitOffset>
19371 <bitWidth>3</bitWidth>
19372 </field>
19373 <field>
19374 <name>SMS</name>
19375 <description>Slave mode selection -
19376 bit[2:0]</description>
19377 <bitOffset>0</bitOffset>
19378 <bitWidth>3</bitWidth>
19379 </field>
19380 </fields>
19381 </register>
19382 <register>
19383 <name>DIER</name>
19384 <displayName>DIER</displayName>
19385 <description>DMA/Interrupt enable register</description>
19386 <addressOffset>0xC</addressOffset>
19387 <size>0x20</size>
19388 <access>read-write</access>
19389 <resetValue>0x0000</resetValue>
19390 <fields>
19391 <field>
19392 <name>TDE</name>
19393 <description>Trigger DMA request enable</description>
19394 <bitOffset>14</bitOffset>
19395 <bitWidth>1</bitWidth>
19396 </field>
19397 <field>
19398 <name>COMDE</name>
19399 <description>COM DMA request enable</description>
19400 <bitOffset>13</bitOffset>
19401 <bitWidth>1</bitWidth>
19402 </field>
19403 <field>
19404 <name>CC4DE</name>
19405 <description>Capture/Compare 4 DMA request
19406 enable</description>
19407 <bitOffset>12</bitOffset>
19408 <bitWidth>1</bitWidth>
19409 </field>
19410 <field>
19411 <name>CC3DE</name>
19412 <description>Capture/Compare 3 DMA request
19413 enable</description>
19414 <bitOffset>11</bitOffset>
19415 <bitWidth>1</bitWidth>
19416 </field>
19417 <field>
19418 <name>CC2DE</name>
19419 <description>Capture/Compare 2 DMA request
19420 enable</description>
19421 <bitOffset>10</bitOffset>
19422 <bitWidth>1</bitWidth>
19423 </field>
19424 <field>
19425 <name>CC1DE</name>
19426 <description>Capture/Compare 1 DMA request
19427 enable</description>
19428 <bitOffset>9</bitOffset>
19429 <bitWidth>1</bitWidth>
19430 </field>
19431 <field>
19432 <name>UDE</name>
19433 <description>Update DMA request enable</description>
19434 <bitOffset>8</bitOffset>
19435 <bitWidth>1</bitWidth>
19436 </field>
19437 <field>
19438 <name>TIE</name>
19439 <description>Trigger interrupt enable</description>
19440 <bitOffset>6</bitOffset>
19441 <bitWidth>1</bitWidth>
19442 </field>
19443 <field>
19444 <name>CC4IE</name>
19445 <description>Capture/Compare 4 interrupt
19446 enable</description>
19447 <bitOffset>4</bitOffset>
19448 <bitWidth>1</bitWidth>
19449 </field>
19450 <field>
19451 <name>CC3IE</name>
19452 <description>Capture/Compare 3 interrupt
19453 enable</description>
19454 <bitOffset>3</bitOffset>
19455 <bitWidth>1</bitWidth>
19456 </field>
19457 <field>
19458 <name>CC2IE</name>
19459 <description>Capture/Compare 2 interrupt
19460 enable</description>
19461 <bitOffset>2</bitOffset>
19462 <bitWidth>1</bitWidth>
19463 </field>
19464 <field>
19465 <name>CC1IE</name>
19466 <description>Capture/Compare 1 interrupt
19467 enable</description>
19468 <bitOffset>1</bitOffset>
19469 <bitWidth>1</bitWidth>
19470 </field>
19471 <field>
19472 <name>UIE</name>
19473 <description>Update interrupt enable</description>
19474 <bitOffset>0</bitOffset>
19475 <bitWidth>1</bitWidth>
19476 </field>
19477 <field>
19478 <name>BIE</name>
19479 <description>Break interrupt enable</description>
19480 <bitOffset>7</bitOffset>
19481 <bitWidth>1</bitWidth>
19482 </field>
19483 <field>
19484 <name>COMIE</name>
19485 <description>COM interrupt enable</description>
19486 <bitOffset>5</bitOffset>
19487 <bitWidth>1</bitWidth>
19488 </field>
19489 </fields>
19490 </register>
19491 <register>
19492 <name>SR</name>
19493 <displayName>SR</displayName>
19494 <description>status register</description>
19495 <addressOffset>0x10</addressOffset>
19496 <size>0x20</size>
19497 <access>read-write</access>
19498 <resetValue>0x0000</resetValue>
19499 <fields>
19500 <field>
19501 <name>CC4OF</name>
19502 <description>Capture/Compare 4 overcapture
19503 flag</description>
19504 <bitOffset>12</bitOffset>
19505 <bitWidth>1</bitWidth>
19506 </field>
19507 <field>
19508 <name>CC3OF</name>
19509 <description>Capture/Compare 3 overcapture
19510 flag</description>
19511 <bitOffset>11</bitOffset>
19512 <bitWidth>1</bitWidth>
19513 </field>
19514 <field>
19515 <name>CC2OF</name>
19516 <description>Capture/compare 2 overcapture
19517 flag</description>
19518 <bitOffset>10</bitOffset>
19519 <bitWidth>1</bitWidth>
19520 </field>
19521 <field>
19522 <name>CC1OF</name>
19523 <description>Capture/Compare 1 overcapture
19524 flag</description>
19525 <bitOffset>9</bitOffset>
19526 <bitWidth>1</bitWidth>
19527 </field>
19528 <field>
19529 <name>BIF</name>
19530 <description>Break interrupt flag</description>
19531 <bitOffset>7</bitOffset>
19532 <bitWidth>1</bitWidth>
19533 </field>
19534 <field>
19535 <name>TIF</name>
19536 <description>Trigger interrupt flag</description>
19537 <bitOffset>6</bitOffset>
19538 <bitWidth>1</bitWidth>
19539 </field>
19540 <field>
19541 <name>COMIF</name>
19542 <description>COM interrupt flag</description>
19543 <bitOffset>5</bitOffset>
19544 <bitWidth>1</bitWidth>
19545 </field>
19546 <field>
19547 <name>CC4IF</name>
19548 <description>Capture/Compare 4 interrupt
19549 flag</description>
19550 <bitOffset>4</bitOffset>
19551 <bitWidth>1</bitWidth>
19552 </field>
19553 <field>
19554 <name>CC3IF</name>
19555 <description>Capture/Compare 3 interrupt
19556 flag</description>
19557 <bitOffset>3</bitOffset>
19558 <bitWidth>1</bitWidth>
19559 </field>
19560 <field>
19561 <name>CC2IF</name>
19562 <description>Capture/Compare 2 interrupt
19563 flag</description>
19564 <bitOffset>2</bitOffset>
19565 <bitWidth>1</bitWidth>
19566 </field>
19567 <field>
19568 <name>CC1IF</name>
19569 <description>Capture/compare 1 interrupt
19570 flag</description>
19571 <bitOffset>1</bitOffset>
19572 <bitWidth>1</bitWidth>
19573 </field>
19574 <field>
19575 <name>UIF</name>
19576 <description>Update interrupt flag</description>
19577 <bitOffset>0</bitOffset>
19578 <bitWidth>1</bitWidth>
19579 </field>
19580 </fields>
19581 </register>
19582 <register>
19583 <name>EGR</name>
19584 <displayName>EGR</displayName>
19585 <description>event generation register</description>
19586 <addressOffset>0x14</addressOffset>
19587 <size>0x20</size>
19588 <access>write-only</access>
19589 <resetValue>0x0000</resetValue>
19590 <fields>
19591 <field>
19592 <name>BG</name>
19593 <description>Break generation</description>
19594 <bitOffset>7</bitOffset>
19595 <bitWidth>1</bitWidth>
19596 </field>
19597 <field>
19598 <name>TG</name>
19599 <description>Trigger generation</description>
19600 <bitOffset>6</bitOffset>
19601 <bitWidth>1</bitWidth>
19602 </field>
19603 <field>
19604 <name>COMG</name>
19605 <description>Capture/Compare control update
19606 generation</description>
19607 <bitOffset>5</bitOffset>
19608 <bitWidth>1</bitWidth>
19609 </field>
19610 <field>
19611 <name>CC4G</name>
19612 <description>Capture/compare 4
19613 generation</description>
19614 <bitOffset>4</bitOffset>
19615 <bitWidth>1</bitWidth>
19616 </field>
19617 <field>
19618 <name>CC3G</name>
19619 <description>Capture/compare 3
19620 generation</description>
19621 <bitOffset>3</bitOffset>
19622 <bitWidth>1</bitWidth>
19623 </field>
19624 <field>
19625 <name>CC2G</name>
19626 <description>Capture/compare 2
19627 generation</description>
19628 <bitOffset>2</bitOffset>
19629 <bitWidth>1</bitWidth>
19630 </field>
19631 <field>
19632 <name>CC1G</name>
19633 <description>Capture/compare 1
19634 generation</description>
19635 <bitOffset>1</bitOffset>
19636 <bitWidth>1</bitWidth>
19637 </field>
19638 <field>
19639 <name>UG</name>
19640 <description>Update generation</description>
19641 <bitOffset>0</bitOffset>
19642 <bitWidth>1</bitWidth>
19643 </field>
19644 </fields>
19645 </register>
19646 <register>
19647 <name>CCMR1_Output</name>
19648 <displayName>CCMR1_Output</displayName>
19649 <description>capture/compare mode register 1 (output
19650 mode)</description>
19651 <addressOffset>0x18</addressOffset>
19652 <size>0x20</size>
19653 <access>read-write</access>
19654 <resetValue>0x00000000</resetValue>
19655 <fields>
19656 <field>
19657 <name>OC2CE</name>
19658 <description>Output Compare 2 clear
19659 enable</description>
19660 <bitOffset>15</bitOffset>
19661 <bitWidth>1</bitWidth>
19662 </field>
19663 <field>
19664 <name>OC2M</name>
19665 <description>Output Compare 2 mode</description>
19666 <bitOffset>12</bitOffset>
19667 <bitWidth>3</bitWidth>
19668 </field>
19669 <field>
19670 <name>OC2PE</name>
19671 <description>Output Compare 2 preload
19672 enable</description>
19673 <bitOffset>11</bitOffset>
19674 <bitWidth>1</bitWidth>
19675 </field>
19676 <field>
19677 <name>OC2FE</name>
19678 <description>Output Compare 2 fast
19679 enable</description>
19680 <bitOffset>10</bitOffset>
19681 <bitWidth>1</bitWidth>
19682 </field>
19683 <field>
19684 <name>CC2S</name>
19685 <description>Capture/Compare 2
19686 selection</description>
19687 <bitOffset>8</bitOffset>
19688 <bitWidth>2</bitWidth>
19689 </field>
19690 <field>
19691 <name>OC1CE</name>
19692 <description>Output Compare 1 clear
19693 enable</description>
19694 <bitOffset>7</bitOffset>
19695 <bitWidth>1</bitWidth>
19696 </field>
19697 <field>
19698 <name>OC1M</name>
19699 <description>Output Compare 1 mode</description>
19700 <bitOffset>4</bitOffset>
19701 <bitWidth>3</bitWidth>
19702 </field>
19703 <field>
19704 <name>OC1PE</name>
19705 <description>Output Compare 1 preload
19706 enable</description>
19707 <bitOffset>3</bitOffset>
19708 <bitWidth>1</bitWidth>
19709 </field>
19710 <field>
19711 <name>OC1FE</name>
19712 <description>Output Compare 1 fast
19713 enable</description>
19714 <bitOffset>2</bitOffset>
19715 <bitWidth>1</bitWidth>
19716 </field>
19717 <field>
19718 <name>CC1S</name>
19719 <description>Capture/Compare 1
19720 selection</description>
19721 <bitOffset>0</bitOffset>
19722 <bitWidth>2</bitWidth>
19723 </field>
19724 </fields>
19725 </register>
19726 <register>
19727 <name>CCMR1_Input</name>
19728 <displayName>CCMR1_Input</displayName>
19729 <description>capture/compare mode register 1 (input
19730 mode)</description>
19731 <alternateRegister>CCMR1_Output</alternateRegister>
19732 <addressOffset>0x18</addressOffset>
19733 <size>0x20</size>
19734 <access>read-write</access>
19735 <resetValue>0x00000000</resetValue>
19736 <fields>
19737 <field>
19738 <name>IC2F</name>
19739 <description>Input capture 2 filter</description>
19740 <bitOffset>12</bitOffset>
19741 <bitWidth>4</bitWidth>
19742 </field>
19743 <field>
19744 <name>IC2PCS</name>
19745 <description>Input capture 2 prescaler</description>
19746 <bitOffset>10</bitOffset>
19747 <bitWidth>2</bitWidth>
19748 </field>
19749 <field>
19750 <name>CC2S</name>
19751 <description>Capture/Compare 2
19752 selection</description>
19753 <bitOffset>8</bitOffset>
19754 <bitWidth>2</bitWidth>
19755 </field>
19756 <field>
19757 <name>IC1F</name>
19758 <description>Input capture 1 filter</description>
19759 <bitOffset>4</bitOffset>
19760 <bitWidth>4</bitWidth>
19761 </field>
19762 <field>
19763 <name>ICPCS</name>
19764 <description>Input capture 1 prescaler</description>
19765 <bitOffset>2</bitOffset>
19766 <bitWidth>2</bitWidth>
19767 </field>
19768 <field>
19769 <name>CC1S</name>
19770 <description>Capture/Compare 1
19771 selection</description>
19772 <bitOffset>0</bitOffset>
19773 <bitWidth>2</bitWidth>
19774 </field>
19775 </fields>
19776 </register>
19777 <register>
19778 <name>CCMR2_Output</name>
19779 <displayName>CCMR2_Output</displayName>
19780 <description>capture/compare mode register 2 (output
19781 mode)</description>
19782 <addressOffset>0x1C</addressOffset>
19783 <size>0x20</size>
19784 <access>read-write</access>
19785 <resetValue>0x00000000</resetValue>
19786 <fields>
19787 <field>
19788 <name>OC4CE</name>
19789 <description>Output compare 4 clear
19790 enable</description>
19791 <bitOffset>15</bitOffset>
19792 <bitWidth>1</bitWidth>
19793 </field>
19794 <field>
19795 <name>OC4M</name>
19796 <description>Output compare 4 mode</description>
19797 <bitOffset>12</bitOffset>
19798 <bitWidth>3</bitWidth>
19799 </field>
19800 <field>
19801 <name>OC4PE</name>
19802 <description>Output compare 4 preload
19803 enable</description>
19804 <bitOffset>11</bitOffset>
19805 <bitWidth>1</bitWidth>
19806 </field>
19807 <field>
19808 <name>OC4FE</name>
19809 <description>Output compare 4 fast
19810 enable</description>
19811 <bitOffset>10</bitOffset>
19812 <bitWidth>1</bitWidth>
19813 </field>
19814 <field>
19815 <name>CC4S</name>
19816 <description>Capture/Compare 4
19817 selection</description>
19818 <bitOffset>8</bitOffset>
19819 <bitWidth>2</bitWidth>
19820 </field>
19821 <field>
19822 <name>OC3CE</name>
19823 <description>Output compare 3 clear
19824 enable</description>
19825 <bitOffset>7</bitOffset>
19826 <bitWidth>1</bitWidth>
19827 </field>
19828 <field>
19829 <name>OC3M</name>
19830 <description>Output compare 3 mode</description>
19831 <bitOffset>4</bitOffset>
19832 <bitWidth>3</bitWidth>
19833 </field>
19834 <field>
19835 <name>OC3PE</name>
19836 <description>Output compare 3 preload
19837 enable</description>
19838 <bitOffset>3</bitOffset>
19839 <bitWidth>1</bitWidth>
19840 </field>
19841 <field>
19842 <name>OC3FE</name>
19843 <description>Output compare 3 fast
19844 enable</description>
19845 <bitOffset>2</bitOffset>
19846 <bitWidth>1</bitWidth>
19847 </field>
19848 <field>
19849 <name>CC3S</name>
19850 <description>Capture/Compare 3
19851 selection</description>
19852 <bitOffset>0</bitOffset>
19853 <bitWidth>2</bitWidth>
19854 </field>
19855 </fields>
19856 </register>
19857 <register>
19858 <name>CCMR2_Input</name>
19859 <displayName>CCMR2_Input</displayName>
19860 <description>capture/compare mode register 2 (input
19861 mode)</description>
19862 <alternateRegister>CCMR2_Output</alternateRegister>
19863 <addressOffset>0x1C</addressOffset>
19864 <size>0x20</size>
19865 <access>read-write</access>
19866 <resetValue>0x00000000</resetValue>
19867 <fields>
19868 <field>
19869 <name>IC4F</name>
19870 <description>Input capture 4 filter</description>
19871 <bitOffset>12</bitOffset>
19872 <bitWidth>4</bitWidth>
19873 </field>
19874 <field>
19875 <name>IC4PSC</name>
19876 <description>Input capture 4 prescaler</description>
19877 <bitOffset>10</bitOffset>
19878 <bitWidth>2</bitWidth>
19879 </field>
19880 <field>
19881 <name>CC4S</name>
19882 <description>Capture/Compare 4
19883 selection</description>
19884 <bitOffset>8</bitOffset>
19885 <bitWidth>2</bitWidth>
19886 </field>
19887 <field>
19888 <name>IC3F</name>
19889 <description>Input capture 3 filter</description>
19890 <bitOffset>4</bitOffset>
19891 <bitWidth>4</bitWidth>
19892 </field>
19893 <field>
19894 <name>IC3PSC</name>
19895 <description>Input capture 3 prescaler</description>
19896 <bitOffset>2</bitOffset>
19897 <bitWidth>2</bitWidth>
19898 </field>
19899 <field>
19900 <name>CC3S</name>
19901 <description>Capture/compare 3
19902 selection</description>
19903 <bitOffset>0</bitOffset>
19904 <bitWidth>2</bitWidth>
19905 </field>
19906 </fields>
19907 </register>
19908 <register>
19909 <name>CCER</name>
19910 <displayName>CCER</displayName>
19911 <description>capture/compare enable
19912 register</description>
19913 <addressOffset>0x20</addressOffset>
19914 <size>0x20</size>
19915 <access>read-write</access>
19916 <resetValue>0x0000</resetValue>
19917 <fields>
19918 <field>
19919 <name>CC4P</name>
19920 <description>Capture/Compare 3 output
19921 Polarity</description>
19922 <bitOffset>13</bitOffset>
19923 <bitWidth>1</bitWidth>
19924 </field>
19925 <field>
19926 <name>CC4E</name>
19927 <description>Capture/Compare 4 output
19928 enable</description>
19929 <bitOffset>12</bitOffset>
19930 <bitWidth>1</bitWidth>
19931 </field>
19932 <field>
19933 <name>CC3NP</name>
19934 <description>Capture/Compare 3 output
19935 Polarity</description>
19936 <bitOffset>11</bitOffset>
19937 <bitWidth>1</bitWidth>
19938 </field>
19939 <field>
19940 <name>CC3NE</name>
19941 <description>Capture/Compare 3 complementary output
19942 enable</description>
19943 <bitOffset>10</bitOffset>
19944 <bitWidth>1</bitWidth>
19945 </field>
19946 <field>
19947 <name>CC3P</name>
19948 <description>Capture/Compare 3 output
19949 Polarity</description>
19950 <bitOffset>9</bitOffset>
19951 <bitWidth>1</bitWidth>
19952 </field>
19953 <field>
19954 <name>CC3E</name>
19955 <description>Capture/Compare 3 output
19956 enable</description>
19957 <bitOffset>8</bitOffset>
19958 <bitWidth>1</bitWidth>
19959 </field>
19960 <field>
19961 <name>CC2NP</name>
19962 <description>Capture/Compare 2 output
19963 Polarity</description>
19964 <bitOffset>7</bitOffset>
19965 <bitWidth>1</bitWidth>
19966 </field>
19967 <field>
19968 <name>CC2NE</name>
19969 <description>Capture/Compare 2 complementary output
19970 enable</description>
19971 <bitOffset>6</bitOffset>
19972 <bitWidth>1</bitWidth>
19973 </field>
19974 <field>
19975 <name>CC2P</name>
19976 <description>Capture/Compare 2 output
19977 Polarity</description>
19978 <bitOffset>5</bitOffset>
19979 <bitWidth>1</bitWidth>
19980 </field>
19981 <field>
19982 <name>CC2E</name>
19983 <description>Capture/Compare 2 output
19984 enable</description>
19985 <bitOffset>4</bitOffset>
19986 <bitWidth>1</bitWidth>
19987 </field>
19988 <field>
19989 <name>CC1NP</name>
19990 <description>Capture/Compare 1 output
19991 Polarity</description>
19992 <bitOffset>3</bitOffset>
19993 <bitWidth>1</bitWidth>
19994 </field>
19995 <field>
19996 <name>CC1NE</name>
19997 <description>Capture/Compare 1 complementary output
19998 enable</description>
19999 <bitOffset>2</bitOffset>
20000 <bitWidth>1</bitWidth>
20001 </field>
20002 <field>
20003 <name>CC1P</name>
20004 <description>Capture/Compare 1 output
20005 Polarity</description>
20006 <bitOffset>1</bitOffset>
20007 <bitWidth>1</bitWidth>
20008 </field>
20009 <field>
20010 <name>CC1E</name>
20011 <description>Capture/Compare 1 output
20012 enable</description>
20013 <bitOffset>0</bitOffset>
20014 <bitWidth>1</bitWidth>
20015 </field>
20016 </fields>
20017 </register>
20018 <register>
20019 <name>CNT</name>
20020 <displayName>CNT</displayName>
20021 <description>counter</description>
20022 <addressOffset>0x24</addressOffset>
20023 <size>0x20</size>
20024 <access>read-write</access>
20025 <resetValue>0x00000000</resetValue>
20026 <fields>
20027 <field>
20028 <name>CNT</name>
20029 <description>counter value</description>
20030 <bitOffset>0</bitOffset>
20031 <bitWidth>16</bitWidth>
20032 </field>
20033 </fields>
20034 </register>
20035 <register>
20036 <name>PSC</name>
20037 <displayName>PSC</displayName>
20038 <description>prescaler</description>
20039 <addressOffset>0x28</addressOffset>
20040 <size>0x20</size>
20041 <access>read-write</access>
20042 <resetValue>0x0000</resetValue>
20043 <fields>
20044 <field>
20045 <name>PSC</name>
20046 <description>Prescaler value</description>
20047 <bitOffset>0</bitOffset>
20048 <bitWidth>16</bitWidth>
20049 </field>
20050 </fields>
20051 </register>
20052 <register>
20053 <name>ARR</name>
20054 <displayName>ARR</displayName>
20055 <description>auto-reload register</description>
20056 <addressOffset>0x2C</addressOffset>
20057 <size>0x20</size>
20058 <access>read-write</access>
20059 <resetValue>0x00000000</resetValue>
20060 <fields>
20061 <field>
20062 <name>ARR</name>
20063 <description>Auto-reload value</description>
20064 <bitOffset>0</bitOffset>
20065 <bitWidth>16</bitWidth>
20066 </field>
20067 </fields>
20068 </register>
20069 <register>
20070 <name>CCR1</name>
20071 <displayName>CCR1</displayName>
20072 <description>capture/compare register 1</description>
20073 <addressOffset>0x34</addressOffset>
20074 <size>0x20</size>
20075 <access>read-write</access>
20076 <resetValue>0x00000000</resetValue>
20077 <fields>
20078 <field>
20079 <name>CCR1</name>
20080 <description>Capture/Compare 1 value</description>
20081 <bitOffset>0</bitOffset>
20082 <bitWidth>16</bitWidth>
20083 </field>
20084 </fields>
20085 </register>
20086 <register>
20087 <name>CCR2</name>
20088 <displayName>CCR2</displayName>
20089 <description>capture/compare register 2</description>
20090 <addressOffset>0x38</addressOffset>
20091 <size>0x20</size>
20092 <access>read-write</access>
20093 <resetValue>0x00000000</resetValue>
20094 <fields>
20095 <field>
20096 <name>CCR2</name>
20097 <description>Capture/Compare 2 value</description>
20098 <bitOffset>0</bitOffset>
20099 <bitWidth>16</bitWidth>
20100 </field>
20101 </fields>
20102 </register>
20103 <register>
20104 <name>CCR3</name>
20105 <displayName>CCR3</displayName>
20106 <description>capture/compare register 3</description>
20107 <addressOffset>0x3C</addressOffset>
20108 <size>0x20</size>
20109 <access>read-write</access>
20110 <resetValue>0x00000000</resetValue>
20111 <fields>
20112 <field>
20113 <name>CCR3</name>
20114 <description>Capture/Compare value</description>
20115 <bitOffset>0</bitOffset>
20116 <bitWidth>16</bitWidth>
20117 </field>
20118 </fields>
20119 </register>
20120 <register>
20121 <name>CCR4</name>
20122 <displayName>CCR4</displayName>
20123 <description>capture/compare register 4</description>
20124 <addressOffset>0x40</addressOffset>
20125 <size>0x20</size>
20126 <access>read-write</access>
20127 <resetValue>0x00000000</resetValue>
20128 <fields>
20129 <field>
20130 <name>CCR4</name>
20131 <description>Capture/Compare value</description>
20132 <bitOffset>0</bitOffset>
20133 <bitWidth>16</bitWidth>
20134 </field>
20135 </fields>
20136 </register>
20137 <register>
20138 <name>DCR</name>
20139 <displayName>DCR</displayName>
20140 <description>DMA control register</description>
20141 <addressOffset>0x48</addressOffset>
20142 <size>0x20</size>
20143 <access>read-write</access>
20144 <resetValue>0x0000</resetValue>
20145 <fields>
20146 <field>
20147 <name>DBL</name>
20148 <description>DMA burst length</description>
20149 <bitOffset>8</bitOffset>
20150 <bitWidth>5</bitWidth>
20151 </field>
20152 <field>
20153 <name>DBA</name>
20154 <description>DMA base address</description>
20155 <bitOffset>0</bitOffset>
20156 <bitWidth>5</bitWidth>
20157 </field>
20158 </fields>
20159 </register>
20160 <register>
20161 <name>DMAR</name>
20162 <displayName>DMAR</displayName>
20163 <description>DMA address for full transfer</description>
20164 <addressOffset>0x4C</addressOffset>
20165 <size>0x20</size>
20166 <access>read-write</access>
20167 <resetValue>0x0000</resetValue>
20168 <fields>
20169 <field>
20170 <name>DMAB</name>
20171 <description>DMA register for burst
20172 accesses</description>
20173 <bitOffset>0</bitOffset>
20174 <bitWidth>16</bitWidth>
20175 </field>
20176 </fields>
20177 </register>
20178 <register>
20179 <name>RCR</name>
20180 <displayName>RCR</displayName>
20181 <description>repetition counter register</description>
20182 <addressOffset>0x30</addressOffset>
20183 <size>0x20</size>
20184 <access>read-write</access>
20185 <resetValue>0x0000</resetValue>
20186 <fields>
20187 <field>
20188 <name>REP</name>
20189 <description>Repetition counter value</description>
20190 <bitOffset>0</bitOffset>
20191 <bitWidth>8</bitWidth>
20192 </field>
20193 </fields>
20194 </register>
20195 <register>
20196 <name>BDTR</name>
20197 <displayName>BDTR</displayName>
20198 <description>break and dead-time register</description>
20199 <addressOffset>0x44</addressOffset>
20200 <size>0x20</size>
20201 <access>read-write</access>
20202 <resetValue>0x0000</resetValue>
20203 <fields>
20204 <field>
20205 <name>MOE</name>
20206 <description>Main output enable</description>
20207 <bitOffset>15</bitOffset>
20208 <bitWidth>1</bitWidth>
20209 </field>
20210 <field>
20211 <name>AOE</name>
20212 <description>Automatic output enable</description>
20213 <bitOffset>14</bitOffset>
20214 <bitWidth>1</bitWidth>
20215 </field>
20216 <field>
20217 <name>BKP</name>
20218 <description>Break polarity</description>
20219 <bitOffset>13</bitOffset>
20220 <bitWidth>1</bitWidth>
20221 </field>
20222 <field>
20223 <name>BKE</name>
20224 <description>Break enable</description>
20225 <bitOffset>12</bitOffset>
20226 <bitWidth>1</bitWidth>
20227 </field>
20228 <field>
20229 <name>OSSR</name>
20230 <description>Off-state selection for Run
20231 mode</description>
20232 <bitOffset>11</bitOffset>
20233 <bitWidth>1</bitWidth>
20234 </field>
20235 <field>
20236 <name>OSSI</name>
20237 <description>Off-state selection for Idle
20238 mode</description>
20239 <bitOffset>10</bitOffset>
20240 <bitWidth>1</bitWidth>
20241 </field>
20242 <field>
20243 <name>LOCK</name>
20244 <description>Lock configuration</description>
20245 <bitOffset>8</bitOffset>
20246 <bitWidth>2</bitWidth>
20247 </field>
20248 <field>
20249 <name>DTG</name>
20250 <description>Dead-time generator setup</description>
20251 <bitOffset>0</bitOffset>
20252 <bitWidth>8</bitWidth>
20253 </field>
20254 </fields>
20255 </register>
20256 <register>
20257 <name>CCMR3_Output</name>
20258 <displayName>CCMR3_Output</displayName>
20259 <description>capture/compare mode register 3 (output
20260 mode)</description>
20261 <addressOffset>0x54</addressOffset>
20262 <size>0x20</size>
20263 <access>read-write</access>
20264 <resetValue>0x0000</resetValue>
20265 <fields>
20266 <field>
20267 <name>OC5FE</name>
20268 <description>Output compare 5 fast
20269 enable</description>
20270 <bitOffset>2</bitOffset>
20271 <bitWidth>1</bitWidth>
20272 </field>
20273 <field>
20274 <name>OC5PE</name>
20275 <description>Output compare 5 preload
20276 enable</description>
20277 <bitOffset>3</bitOffset>
20278 <bitWidth>1</bitWidth>
20279 </field>
20280 <field>
20281 <name>OC5M</name>
20282 <description>Output compare 5 mode</description>
20283 <bitOffset>4</bitOffset>
20284 <bitWidth>3</bitWidth>
20285 </field>
20286 <field>
20287 <name>OC5CE</name>
20288 <description>Output compare 5 clear
20289 enable</description>
20290 <bitOffset>7</bitOffset>
20291 <bitWidth>1</bitWidth>
20292 </field>
20293 <field>
20294 <name>OC6FE</name>
20295 <description>Output compare 6 fast
20296 enable</description>
20297 <bitOffset>10</bitOffset>
20298 <bitWidth>1</bitWidth>
20299 </field>
20300 <field>
20301 <name>OC6PE</name>
20302 <description>Output compare 6 preload
20303 enable</description>
20304 <bitOffset>11</bitOffset>
20305 <bitWidth>1</bitWidth>
20306 </field>
20307 <field>
20308 <name>OC6M</name>
20309 <description>Output compare 6 mode</description>
20310 <bitOffset>12</bitOffset>
20311 <bitWidth>3</bitWidth>
20312 </field>
20313 <field>
20314 <name>OC6CE</name>
20315 <description>Output compare 6 clear
20316 enable</description>
20317 <bitOffset>15</bitOffset>
20318 <bitWidth>1</bitWidth>
20319 </field>
20320 <field>
20321 <name>OC5M3</name>
20322 <description>Output Compare 5 mode</description>
20323 <bitOffset>16</bitOffset>
20324 <bitWidth>1</bitWidth>
20325 </field>
20326 <field>
20327 <name>OC6M3</name>
20328 <description>Output Compare 6 mode</description>
20329 <bitOffset>24</bitOffset>
20330 <bitWidth>1</bitWidth>
20331 </field>
20332 </fields>
20333 </register>
20334 <register>
20335 <name>CCR5</name>
20336 <displayName>CCR5</displayName>
20337 <description>capture/compare register 5</description>
20338 <addressOffset>0x58</addressOffset>
20339 <size>0x20</size>
20340 <access>read-write</access>
20341 <resetValue>0x0000</resetValue>
20342 <fields>
20343 <field>
20344 <name>CCR5</name>
20345 <description>Capture/Compare 5 value</description>
20346 <bitOffset>0</bitOffset>
20347 <bitWidth>16</bitWidth>
20348 </field>
20349 <field>
20350 <name>GC5C1</name>
20351 <description>Group Channel 5 and Channel
20352 1</description>
20353 <bitOffset>29</bitOffset>
20354 <bitWidth>1</bitWidth>
20355 </field>
20356 <field>
20357 <name>GC5C2</name>
20358 <description>Group Channel 5 and Channel
20359 2</description>
20360 <bitOffset>30</bitOffset>
20361 <bitWidth>1</bitWidth>
20362 </field>
20363 <field>
20364 <name>GC5C3</name>
20365 <description>Group Channel 5 and Channel
20366 3</description>
20367 <bitOffset>31</bitOffset>
20368 <bitWidth>1</bitWidth>
20369 </field>
20370 </fields>
20371 </register>
20372 <register>
20373 <name>CRR6</name>
20374 <displayName>CRR6</displayName>
20375 <description>capture/compare register 6</description>
20376 <addressOffset>0x5C</addressOffset>
20377 <size>0x20</size>
20378 <access>read-write</access>
20379 <resetValue>0x0000</resetValue>
20380 <fields>
20381 <field>
20382 <name>CCR6</name>
20383 <description>Capture/Compare 6 value</description>
20384 <bitOffset>0</bitOffset>
20385 <bitWidth>16</bitWidth>
20386 </field>
20387 </fields>
20388 </register>
20389 </registers>
20390 </peripheral>
20391 <peripheral derivedFrom="TIM1">
20392 <name>TIM8</name>
20393 <baseAddress>0x40010400</baseAddress>
20394 <interrupt>
20395 <name>TIM8_BRK_TIM12</name>
20396 <description>TIM8 Break interrupt and TIM12 global
20397 interrupt</description>
20398 <value>43</value>
20399 </interrupt>
20400 <interrupt>
20401 <name>TIM8_UP_TIM13</name>
20402 <description>TIM8 Update interrupt and TIM13 global
20403 interrupt</description>
20404 <value>44</value>
20405 </interrupt>
20406 <interrupt>
20407 <name>TIM8_TRG_COM_TIM14</name>
20408 <description>TIM8 Trigger and Commutation interrupts and
20409 TIM14 global interrupt</description>
20410 <value>45</value>
20411 </interrupt>
20412 <interrupt>
20413 <name>TIM8_CC</name>
20414 <description>TIM8 Capture Compare interrupt</description>
20415 <value>46</value>
20416 </interrupt>
20417 </peripheral>
20418 <peripheral>
20419 <name>TIM2</name>
20420 <description>General purpose timers</description>
20421 <groupName>TIM</groupName>
20422 <baseAddress>0x40000000</baseAddress>
20423 <addressBlock>
20424 <offset>0x0</offset>
20425 <size>0x400</size>
20426 <usage>registers</usage>
20427 </addressBlock>
20428 <interrupt>
20429 <name>TIM2</name>
20430 <description>TIM2 global interrupt</description>
20431 <value>28</value>
20432 </interrupt>
20433 <registers>
20434 <register>
20435 <name>CR1</name>
20436 <displayName>CR1</displayName>
20437 <description>control register 1</description>
20438 <addressOffset>0x0</addressOffset>
20439 <size>0x20</size>
20440 <access>read-write</access>
20441 <resetValue>0x0000</resetValue>
20442 <fields>
20443 <field>
20444 <name>CKD</name>
20445 <description>Clock division</description>
20446 <bitOffset>8</bitOffset>
20447 <bitWidth>2</bitWidth>
20448 </field>
20449 <field>
20450 <name>ARPE</name>
20451 <description>Auto-reload preload enable</description>
20452 <bitOffset>7</bitOffset>
20453 <bitWidth>1</bitWidth>
20454 </field>
20455 <field>
20456 <name>CMS</name>
20457 <description>Center-aligned mode
20458 selection</description>
20459 <bitOffset>5</bitOffset>
20460 <bitWidth>2</bitWidth>
20461 </field>
20462 <field>
20463 <name>DIR</name>
20464 <description>Direction</description>
20465 <bitOffset>4</bitOffset>
20466 <bitWidth>1</bitWidth>
20467 </field>
20468 <field>
20469 <name>OPM</name>
20470 <description>One-pulse mode</description>
20471 <bitOffset>3</bitOffset>
20472 <bitWidth>1</bitWidth>
20473 </field>
20474 <field>
20475 <name>URS</name>
20476 <description>Update request source</description>
20477 <bitOffset>2</bitOffset>
20478 <bitWidth>1</bitWidth>
20479 </field>
20480 <field>
20481 <name>UDIS</name>
20482 <description>Update disable</description>
20483 <bitOffset>1</bitOffset>
20484 <bitWidth>1</bitWidth>
20485 </field>
20486 <field>
20487 <name>CEN</name>
20488 <description>Counter enable</description>
20489 <bitOffset>0</bitOffset>
20490 <bitWidth>1</bitWidth>
20491 </field>
20492 </fields>
20493 </register>
20494 <register>
20495 <name>CR2</name>
20496 <displayName>CR2</displayName>
20497 <description>control register 2</description>
20498 <addressOffset>0x4</addressOffset>
20499 <size>0x20</size>
20500 <access>read-write</access>
20501 <resetValue>0x0000</resetValue>
20502 <fields>
20503 <field>
20504 <name>TI1S</name>
20505 <description>TI1 selection</description>
20506 <bitOffset>7</bitOffset>
20507 <bitWidth>1</bitWidth>
20508 </field>
20509 <field>
20510 <name>MMS</name>
20511 <description>Master mode selection</description>
20512 <bitOffset>4</bitOffset>
20513 <bitWidth>3</bitWidth>
20514 </field>
20515 <field>
20516 <name>CCDS</name>
20517 <description>Capture/compare DMA
20518 selection</description>
20519 <bitOffset>3</bitOffset>
20520 <bitWidth>1</bitWidth>
20521 </field>
20522 </fields>
20523 </register>
20524 <register>
20525 <name>SMCR</name>
20526 <displayName>SMCR</displayName>
20527 <description>slave mode control register</description>
20528 <addressOffset>0x8</addressOffset>
20529 <size>0x20</size>
20530 <access>read-write</access>
20531 <resetValue>0x0000</resetValue>
20532 <fields>
20533 <field>
20534 <name>SMS</name>
20535 <description>Slave mode selection</description>
20536 <bitOffset>0</bitOffset>
20537 <bitWidth>3</bitWidth>
20538 </field>
20539 <field>
20540 <name>TS</name>
20541 <description>Trigger selection</description>
20542 <bitOffset>4</bitOffset>
20543 <bitWidth>3</bitWidth>
20544 </field>
20545 <field>
20546 <name>MSM</name>
20547 <description>Master/Slave mode</description>
20548 <bitOffset>7</bitOffset>
20549 <bitWidth>1</bitWidth>
20550 </field>
20551 <field>
20552 <name>ETF</name>
20553 <description>External trigger filter</description>
20554 <bitOffset>8</bitOffset>
20555 <bitWidth>4</bitWidth>
20556 </field>
20557 <field>
20558 <name>ETPS</name>
20559 <description>External trigger prescaler</description>
20560 <bitOffset>12</bitOffset>
20561 <bitWidth>2</bitWidth>
20562 </field>
20563 <field>
20564 <name>ECE</name>
20565 <description>External clock enable</description>
20566 <bitOffset>14</bitOffset>
20567 <bitWidth>1</bitWidth>
20568 </field>
20569 <field>
20570 <name>ETP</name>
20571 <description>External trigger polarity</description>
20572 <bitOffset>15</bitOffset>
20573 <bitWidth>1</bitWidth>
20574 </field>
20575 <field>
20576 <name>SMS_3</name>
20577 <description>Slave model selection -
20578 bit[3]</description>
20579 <bitOffset>16</bitOffset>
20580 <bitWidth>1</bitWidth>
20581 </field>
20582 </fields>
20583 </register>
20584 <register>
20585 <name>DIER</name>
20586 <displayName>DIER</displayName>
20587 <description>DMA/Interrupt enable register</description>
20588 <addressOffset>0xC</addressOffset>
20589 <size>0x20</size>
20590 <access>read-write</access>
20591 <resetValue>0x0000</resetValue>
20592 <fields>
20593 <field>
20594 <name>TDE</name>
20595 <description>Trigger DMA request enable</description>
20596 <bitOffset>14</bitOffset>
20597 <bitWidth>1</bitWidth>
20598 </field>
20599 <field>
20600 <name>CC4DE</name>
20601 <description>Capture/Compare 4 DMA request
20602 enable</description>
20603 <bitOffset>12</bitOffset>
20604 <bitWidth>1</bitWidth>
20605 </field>
20606 <field>
20607 <name>CC3DE</name>
20608 <description>Capture/Compare 3 DMA request
20609 enable</description>
20610 <bitOffset>11</bitOffset>
20611 <bitWidth>1</bitWidth>
20612 </field>
20613 <field>
20614 <name>CC2DE</name>
20615 <description>Capture/Compare 2 DMA request
20616 enable</description>
20617 <bitOffset>10</bitOffset>
20618 <bitWidth>1</bitWidth>
20619 </field>
20620 <field>
20621 <name>CC1DE</name>
20622 <description>Capture/Compare 1 DMA request
20623 enable</description>
20624 <bitOffset>9</bitOffset>
20625 <bitWidth>1</bitWidth>
20626 </field>
20627 <field>
20628 <name>UDE</name>
20629 <description>Update DMA request enable</description>
20630 <bitOffset>8</bitOffset>
20631 <bitWidth>1</bitWidth>
20632 </field>
20633 <field>
20634 <name>TIE</name>
20635 <description>Trigger interrupt enable</description>
20636 <bitOffset>6</bitOffset>
20637 <bitWidth>1</bitWidth>
20638 </field>
20639 <field>
20640 <name>CC4IE</name>
20641 <description>Capture/Compare 4 interrupt
20642 enable</description>
20643 <bitOffset>4</bitOffset>
20644 <bitWidth>1</bitWidth>
20645 </field>
20646 <field>
20647 <name>CC3IE</name>
20648 <description>Capture/Compare 3 interrupt
20649 enable</description>
20650 <bitOffset>3</bitOffset>
20651 <bitWidth>1</bitWidth>
20652 </field>
20653 <field>
20654 <name>CC2IE</name>
20655 <description>Capture/Compare 2 interrupt
20656 enable</description>
20657 <bitOffset>2</bitOffset>
20658 <bitWidth>1</bitWidth>
20659 </field>
20660 <field>
20661 <name>CC1IE</name>
20662 <description>Capture/Compare 1 interrupt
20663 enable</description>
20664 <bitOffset>1</bitOffset>
20665 <bitWidth>1</bitWidth>
20666 </field>
20667 <field>
20668 <name>UIE</name>
20669 <description>Update interrupt enable</description>
20670 <bitOffset>0</bitOffset>
20671 <bitWidth>1</bitWidth>
20672 </field>
20673 </fields>
20674 </register>
20675 <register>
20676 <name>SR</name>
20677 <displayName>SR</displayName>
20678 <description>status register</description>
20679 <addressOffset>0x10</addressOffset>
20680 <size>0x20</size>
20681 <access>read-write</access>
20682 <resetValue>0x0000</resetValue>
20683 <fields>
20684 <field>
20685 <name>CC4OF</name>
20686 <description>Capture/Compare 4 overcapture
20687 flag</description>
20688 <bitOffset>12</bitOffset>
20689 <bitWidth>1</bitWidth>
20690 </field>
20691 <field>
20692 <name>CC3OF</name>
20693 <description>Capture/Compare 3 overcapture
20694 flag</description>
20695 <bitOffset>11</bitOffset>
20696 <bitWidth>1</bitWidth>
20697 </field>
20698 <field>
20699 <name>CC2OF</name>
20700 <description>Capture/compare 2 overcapture
20701 flag</description>
20702 <bitOffset>10</bitOffset>
20703 <bitWidth>1</bitWidth>
20704 </field>
20705 <field>
20706 <name>CC1OF</name>
20707 <description>Capture/Compare 1 overcapture
20708 flag</description>
20709 <bitOffset>9</bitOffset>
20710 <bitWidth>1</bitWidth>
20711 </field>
20712 <field>
20713 <name>TIF</name>
20714 <description>Trigger interrupt flag</description>
20715 <bitOffset>6</bitOffset>
20716 <bitWidth>1</bitWidth>
20717 </field>
20718 <field>
20719 <name>CC4IF</name>
20720 <description>Capture/Compare 4 interrupt
20721 flag</description>
20722 <bitOffset>4</bitOffset>
20723 <bitWidth>1</bitWidth>
20724 </field>
20725 <field>
20726 <name>CC3IF</name>
20727 <description>Capture/Compare 3 interrupt
20728 flag</description>
20729 <bitOffset>3</bitOffset>
20730 <bitWidth>1</bitWidth>
20731 </field>
20732 <field>
20733 <name>CC2IF</name>
20734 <description>Capture/Compare 2 interrupt
20735 flag</description>
20736 <bitOffset>2</bitOffset>
20737 <bitWidth>1</bitWidth>
20738 </field>
20739 <field>
20740 <name>CC1IF</name>
20741 <description>Capture/compare 1 interrupt
20742 flag</description>
20743 <bitOffset>1</bitOffset>
20744 <bitWidth>1</bitWidth>
20745 </field>
20746 <field>
20747 <name>UIF</name>
20748 <description>Update interrupt flag</description>
20749 <bitOffset>0</bitOffset>
20750 <bitWidth>1</bitWidth>
20751 </field>
20752 </fields>
20753 </register>
20754 <register>
20755 <name>EGR</name>
20756 <displayName>EGR</displayName>
20757 <description>event generation register</description>
20758 <addressOffset>0x14</addressOffset>
20759 <size>0x20</size>
20760 <access>write-only</access>
20761 <resetValue>0x0000</resetValue>
20762 <fields>
20763 <field>
20764 <name>TG</name>
20765 <description>Trigger generation</description>
20766 <bitOffset>6</bitOffset>
20767 <bitWidth>1</bitWidth>
20768 </field>
20769 <field>
20770 <name>CC4G</name>
20771 <description>Capture/compare 4
20772 generation</description>
20773 <bitOffset>4</bitOffset>
20774 <bitWidth>1</bitWidth>
20775 </field>
20776 <field>
20777 <name>CC3G</name>
20778 <description>Capture/compare 3
20779 generation</description>
20780 <bitOffset>3</bitOffset>
20781 <bitWidth>1</bitWidth>
20782 </field>
20783 <field>
20784 <name>CC2G</name>
20785 <description>Capture/compare 2
20786 generation</description>
20787 <bitOffset>2</bitOffset>
20788 <bitWidth>1</bitWidth>
20789 </field>
20790 <field>
20791 <name>CC1G</name>
20792 <description>Capture/compare 1
20793 generation</description>
20794 <bitOffset>1</bitOffset>
20795 <bitWidth>1</bitWidth>
20796 </field>
20797 <field>
20798 <name>UG</name>
20799 <description>Update generation</description>
20800 <bitOffset>0</bitOffset>
20801 <bitWidth>1</bitWidth>
20802 </field>
20803 </fields>
20804 </register>
20805 <register>
20806 <name>CCMR1_Output</name>
20807 <displayName>CCMR1_Output</displayName>
20808 <description>capture/compare mode register 1 (output
20809 mode)</description>
20810 <addressOffset>0x18</addressOffset>
20811 <size>0x20</size>
20812 <access>read-write</access>
20813 <resetValue>0x00000000</resetValue>
20814 <fields>
20815 <field>
20816 <name>OC2CE</name>
20817 <description>OC2CE</description>
20818 <bitOffset>15</bitOffset>
20819 <bitWidth>1</bitWidth>
20820 </field>
20821 <field>
20822 <name>OC2M</name>
20823 <description>OC2M</description>
20824 <bitOffset>12</bitOffset>
20825 <bitWidth>3</bitWidth>
20826 </field>
20827 <field>
20828 <name>OC2PE</name>
20829 <description>OC2PE</description>
20830 <bitOffset>11</bitOffset>
20831 <bitWidth>1</bitWidth>
20832 </field>
20833 <field>
20834 <name>OC2FE</name>
20835 <description>OC2FE</description>
20836 <bitOffset>10</bitOffset>
20837 <bitWidth>1</bitWidth>
20838 </field>
20839 <field>
20840 <name>CC2S</name>
20841 <description>CC2S</description>
20842 <bitOffset>8</bitOffset>
20843 <bitWidth>2</bitWidth>
20844 </field>
20845 <field>
20846 <name>OC1CE</name>
20847 <description>OC1CE</description>
20848 <bitOffset>7</bitOffset>
20849 <bitWidth>1</bitWidth>
20850 </field>
20851 <field>
20852 <name>OC1M</name>
20853 <description>OC1M</description>
20854 <bitOffset>4</bitOffset>
20855 <bitWidth>3</bitWidth>
20856 </field>
20857 <field>
20858 <name>OC1PE</name>
20859 <description>OC1PE</description>
20860 <bitOffset>3</bitOffset>
20861 <bitWidth>1</bitWidth>
20862 </field>
20863 <field>
20864 <name>OC1FE</name>
20865 <description>OC1FE</description>
20866 <bitOffset>2</bitOffset>
20867 <bitWidth>1</bitWidth>
20868 </field>
20869 <field>
20870 <name>CC1S</name>
20871 <description>CC1S</description>
20872 <bitOffset>0</bitOffset>
20873 <bitWidth>2</bitWidth>
20874 </field>
20875 </fields>
20876 </register>
20877 <register>
20878 <name>CCMR1_Input</name>
20879 <displayName>CCMR1_Input</displayName>
20880 <description>capture/compare mode register 1 (input
20881 mode)</description>
20882 <alternateRegister>CCMR1_Output</alternateRegister>
20883 <addressOffset>0x18</addressOffset>
20884 <size>0x20</size>
20885 <access>read-write</access>
20886 <resetValue>0x00000000</resetValue>
20887 <fields>
20888 <field>
20889 <name>IC2F</name>
20890 <description>Input capture 2 filter</description>
20891 <bitOffset>12</bitOffset>
20892 <bitWidth>4</bitWidth>
20893 </field>
20894 <field>
20895 <name>IC2PCS</name>
20896 <description>Input capture 2 prescaler</description>
20897 <bitOffset>10</bitOffset>
20898 <bitWidth>2</bitWidth>
20899 </field>
20900 <field>
20901 <name>CC2S</name>
20902 <description>Capture/Compare 2
20903 selection</description>
20904 <bitOffset>8</bitOffset>
20905 <bitWidth>2</bitWidth>
20906 </field>
20907 <field>
20908 <name>IC1F</name>
20909 <description>Input capture 1 filter</description>
20910 <bitOffset>4</bitOffset>
20911 <bitWidth>4</bitWidth>
20912 </field>
20913 <field>
20914 <name>ICPCS</name>
20915 <description>Input capture 1 prescaler</description>
20916 <bitOffset>2</bitOffset>
20917 <bitWidth>2</bitWidth>
20918 </field>
20919 <field>
20920 <name>CC1S</name>
20921 <description>Capture/Compare 1
20922 selection</description>
20923 <bitOffset>0</bitOffset>
20924 <bitWidth>2</bitWidth>
20925 </field>
20926 </fields>
20927 </register>
20928 <register>
20929 <name>CCMR2_Output</name>
20930 <displayName>CCMR2_Output</displayName>
20931 <description>capture/compare mode register 2 (output
20932 mode)</description>
20933 <addressOffset>0x1C</addressOffset>
20934 <size>0x20</size>
20935 <access>read-write</access>
20936 <resetValue>0x00000000</resetValue>
20937 <fields>
20938 <field>
20939 <name>O24CE</name>
20940 <description>O24CE</description>
20941 <bitOffset>15</bitOffset>
20942 <bitWidth>1</bitWidth>
20943 </field>
20944 <field>
20945 <name>OC4M</name>
20946 <description>OC4M</description>
20947 <bitOffset>12</bitOffset>
20948 <bitWidth>3</bitWidth>
20949 </field>
20950 <field>
20951 <name>OC4PE</name>
20952 <description>OC4PE</description>
20953 <bitOffset>11</bitOffset>
20954 <bitWidth>1</bitWidth>
20955 </field>
20956 <field>
20957 <name>OC4FE</name>
20958 <description>OC4FE</description>
20959 <bitOffset>10</bitOffset>
20960 <bitWidth>1</bitWidth>
20961 </field>
20962 <field>
20963 <name>CC4S</name>
20964 <description>CC4S</description>
20965 <bitOffset>8</bitOffset>
20966 <bitWidth>2</bitWidth>
20967 </field>
20968 <field>
20969 <name>OC3CE</name>
20970 <description>OC3CE</description>
20971 <bitOffset>7</bitOffset>
20972 <bitWidth>1</bitWidth>
20973 </field>
20974 <field>
20975 <name>OC3M</name>
20976 <description>OC3M</description>
20977 <bitOffset>4</bitOffset>
20978 <bitWidth>3</bitWidth>
20979 </field>
20980 <field>
20981 <name>OC3PE</name>
20982 <description>OC3PE</description>
20983 <bitOffset>3</bitOffset>
20984 <bitWidth>1</bitWidth>
20985 </field>
20986 <field>
20987 <name>OC3FE</name>
20988 <description>OC3FE</description>
20989 <bitOffset>2</bitOffset>
20990 <bitWidth>1</bitWidth>
20991 </field>
20992 <field>
20993 <name>CC3S</name>
20994 <description>CC3S</description>
20995 <bitOffset>0</bitOffset>
20996 <bitWidth>2</bitWidth>
20997 </field>
20998 </fields>
20999 </register>
21000 <register>
21001 <name>CCMR2_Input</name>
21002 <displayName>CCMR2_Input</displayName>
21003 <description>capture/compare mode register 2 (input
21004 mode)</description>
21005 <alternateRegister>CCMR2_Output</alternateRegister>
21006 <addressOffset>0x1C</addressOffset>
21007 <size>0x20</size>
21008 <access>read-write</access>
21009 <resetValue>0x00000000</resetValue>
21010 <fields>
21011 <field>
21012 <name>IC4F</name>
21013 <description>Input capture 4 filter</description>
21014 <bitOffset>12</bitOffset>
21015 <bitWidth>4</bitWidth>
21016 </field>
21017 <field>
21018 <name>IC4PSC</name>
21019 <description>Input capture 4 prescaler</description>
21020 <bitOffset>10</bitOffset>
21021 <bitWidth>2</bitWidth>
21022 </field>
21023 <field>
21024 <name>CC4S</name>
21025 <description>Capture/Compare 4
21026 selection</description>
21027 <bitOffset>8</bitOffset>
21028 <bitWidth>2</bitWidth>
21029 </field>
21030 <field>
21031 <name>IC3F</name>
21032 <description>Input capture 3 filter</description>
21033 <bitOffset>4</bitOffset>
21034 <bitWidth>4</bitWidth>
21035 </field>
21036 <field>
21037 <name>IC3PSC</name>
21038 <description>Input capture 3 prescaler</description>
21039 <bitOffset>2</bitOffset>
21040 <bitWidth>2</bitWidth>
21041 </field>
21042 <field>
21043 <name>CC3S</name>
21044 <description>Capture/compare 3
21045 selection</description>
21046 <bitOffset>0</bitOffset>
21047 <bitWidth>2</bitWidth>
21048 </field>
21049 </fields>
21050 </register>
21051 <register>
21052 <name>CCER</name>
21053 <displayName>CCER</displayName>
21054 <description>capture/compare enable
21055 register</description>
21056 <addressOffset>0x20</addressOffset>
21057 <size>0x20</size>
21058 <access>read-write</access>
21059 <resetValue>0x0000</resetValue>
21060 <fields>
21061 <field>
21062 <name>CC4NP</name>
21063 <description>Capture/Compare 4 output
21064 Polarity</description>
21065 <bitOffset>15</bitOffset>
21066 <bitWidth>1</bitWidth>
21067 </field>
21068 <field>
21069 <name>CC4P</name>
21070 <description>Capture/Compare 3 output
21071 Polarity</description>
21072 <bitOffset>13</bitOffset>
21073 <bitWidth>1</bitWidth>
21074 </field>
21075 <field>
21076 <name>CC4E</name>
21077 <description>Capture/Compare 4 output
21078 enable</description>
21079 <bitOffset>12</bitOffset>
21080 <bitWidth>1</bitWidth>
21081 </field>
21082 <field>
21083 <name>CC3NP</name>
21084 <description>Capture/Compare 3 output
21085 Polarity</description>
21086 <bitOffset>11</bitOffset>
21087 <bitWidth>1</bitWidth>
21088 </field>
21089 <field>
21090 <name>CC3P</name>
21091 <description>Capture/Compare 3 output
21092 Polarity</description>
21093 <bitOffset>9</bitOffset>
21094 <bitWidth>1</bitWidth>
21095 </field>
21096 <field>
21097 <name>CC3E</name>
21098 <description>Capture/Compare 3 output
21099 enable</description>
21100 <bitOffset>8</bitOffset>
21101 <bitWidth>1</bitWidth>
21102 </field>
21103 <field>
21104 <name>CC2NP</name>
21105 <description>Capture/Compare 2 output
21106 Polarity</description>
21107 <bitOffset>7</bitOffset>
21108 <bitWidth>1</bitWidth>
21109 </field>
21110 <field>
21111 <name>CC2P</name>
21112 <description>Capture/Compare 2 output
21113 Polarity</description>
21114 <bitOffset>5</bitOffset>
21115 <bitWidth>1</bitWidth>
21116 </field>
21117 <field>
21118 <name>CC2E</name>
21119 <description>Capture/Compare 2 output
21120 enable</description>
21121 <bitOffset>4</bitOffset>
21122 <bitWidth>1</bitWidth>
21123 </field>
21124 <field>
21125 <name>CC1NP</name>
21126 <description>Capture/Compare 1 output
21127 Polarity</description>
21128 <bitOffset>3</bitOffset>
21129 <bitWidth>1</bitWidth>
21130 </field>
21131 <field>
21132 <name>CC1P</name>
21133 <description>Capture/Compare 1 output
21134 Polarity</description>
21135 <bitOffset>1</bitOffset>
21136 <bitWidth>1</bitWidth>
21137 </field>
21138 <field>
21139 <name>CC1E</name>
21140 <description>Capture/Compare 1 output
21141 enable</description>
21142 <bitOffset>0</bitOffset>
21143 <bitWidth>1</bitWidth>
21144 </field>
21145 </fields>
21146 </register>
21147 <register>
21148 <name>CNT</name>
21149 <displayName>CNT</displayName>
21150 <description>counter</description>
21151 <addressOffset>0x24</addressOffset>
21152 <size>0x20</size>
21153 <access>read-write</access>
21154 <resetValue>0x00000000</resetValue>
21155 <fields>
21156 <field>
21157 <name>CNT_H</name>
21158 <description>High counter value</description>
21159 <bitOffset>16</bitOffset>
21160 <bitWidth>16</bitWidth>
21161 </field>
21162 <field>
21163 <name>CNT_L</name>
21164 <description>Low counter value</description>
21165 <bitOffset>0</bitOffset>
21166 <bitWidth>16</bitWidth>
21167 </field>
21168 </fields>
21169 </register>
21170 <register>
21171 <name>PSC</name>
21172 <displayName>PSC</displayName>
21173 <description>prescaler</description>
21174 <addressOffset>0x28</addressOffset>
21175 <size>0x20</size>
21176 <access>read-write</access>
21177 <resetValue>0x0000</resetValue>
21178 <fields>
21179 <field>
21180 <name>PSC</name>
21181 <description>Prescaler value</description>
21182 <bitOffset>0</bitOffset>
21183 <bitWidth>16</bitWidth>
21184 </field>
21185 </fields>
21186 </register>
21187 <register>
21188 <name>ARR</name>
21189 <displayName>ARR</displayName>
21190 <description>auto-reload register</description>
21191 <addressOffset>0x2C</addressOffset>
21192 <size>0x20</size>
21193 <access>read-write</access>
21194 <resetValue>0x00000000</resetValue>
21195 <fields>
21196 <field>
21197 <name>ARR_H</name>
21198 <description>High Auto-reload value</description>
21199 <bitOffset>16</bitOffset>
21200 <bitWidth>16</bitWidth>
21201 </field>
21202 <field>
21203 <name>ARR_L</name>
21204 <description>Low Auto-reload value</description>
21205 <bitOffset>0</bitOffset>
21206 <bitWidth>16</bitWidth>
21207 </field>
21208 </fields>
21209 </register>
21210 <register>
21211 <name>CCR1</name>
21212 <displayName>CCR1</displayName>
21213 <description>capture/compare register 1</description>
21214 <addressOffset>0x34</addressOffset>
21215 <size>0x20</size>
21216 <access>read-write</access>
21217 <resetValue>0x00000000</resetValue>
21218 <fields>
21219 <field>
21220 <name>CCR1_H</name>
21221 <description>High Capture/Compare 1
21222 value</description>
21223 <bitOffset>16</bitOffset>
21224 <bitWidth>16</bitWidth>
21225 </field>
21226 <field>
21227 <name>CCR1_L</name>
21228 <description>Low Capture/Compare 1
21229 value</description>
21230 <bitOffset>0</bitOffset>
21231 <bitWidth>16</bitWidth>
21232 </field>
21233 </fields>
21234 </register>
21235 <register>
21236 <name>CCR2</name>
21237 <displayName>CCR2</displayName>
21238 <description>capture/compare register 2</description>
21239 <addressOffset>0x38</addressOffset>
21240 <size>0x20</size>
21241 <access>read-write</access>
21242 <resetValue>0x00000000</resetValue>
21243 <fields>
21244 <field>
21245 <name>CCR2_H</name>
21246 <description>High Capture/Compare 2
21247 value</description>
21248 <bitOffset>16</bitOffset>
21249 <bitWidth>16</bitWidth>
21250 </field>
21251 <field>
21252 <name>CCR2_L</name>
21253 <description>Low Capture/Compare 2
21254 value</description>
21255 <bitOffset>0</bitOffset>
21256 <bitWidth>16</bitWidth>
21257 </field>
21258 </fields>
21259 </register>
21260 <register>
21261 <name>CCR3</name>
21262 <displayName>CCR3</displayName>
21263 <description>capture/compare register 3</description>
21264 <addressOffset>0x3C</addressOffset>
21265 <size>0x20</size>
21266 <access>read-write</access>
21267 <resetValue>0x00000000</resetValue>
21268 <fields>
21269 <field>
21270 <name>CCR3_H</name>
21271 <description>High Capture/Compare value</description>
21272 <bitOffset>16</bitOffset>
21273 <bitWidth>16</bitWidth>
21274 </field>
21275 <field>
21276 <name>CCR3_L</name>
21277 <description>Low Capture/Compare value</description>
21278 <bitOffset>0</bitOffset>
21279 <bitWidth>16</bitWidth>
21280 </field>
21281 </fields>
21282 </register>
21283 <register>
21284 <name>CCR4</name>
21285 <displayName>CCR4</displayName>
21286 <description>capture/compare register 4</description>
21287 <addressOffset>0x40</addressOffset>
21288 <size>0x20</size>
21289 <access>read-write</access>
21290 <resetValue>0x00000000</resetValue>
21291 <fields>
21292 <field>
21293 <name>CCR4_H</name>
21294 <description>High Capture/Compare value</description>
21295 <bitOffset>16</bitOffset>
21296 <bitWidth>16</bitWidth>
21297 </field>
21298 <field>
21299 <name>CCR4_L</name>
21300 <description>Low Capture/Compare value</description>
21301 <bitOffset>0</bitOffset>
21302 <bitWidth>16</bitWidth>
21303 </field>
21304 </fields>
21305 </register>
21306 <register>
21307 <name>DCR</name>
21308 <displayName>DCR</displayName>
21309 <description>DMA control register</description>
21310 <addressOffset>0x48</addressOffset>
21311 <size>0x20</size>
21312 <access>read-write</access>
21313 <resetValue>0x0000</resetValue>
21314 <fields>
21315 <field>
21316 <name>DBL</name>
21317 <description>DMA burst length</description>
21318 <bitOffset>8</bitOffset>
21319 <bitWidth>5</bitWidth>
21320 </field>
21321 <field>
21322 <name>DBA</name>
21323 <description>DMA base address</description>
21324 <bitOffset>0</bitOffset>
21325 <bitWidth>5</bitWidth>
21326 </field>
21327 </fields>
21328 </register>
21329 <register>
21330 <name>DMAR</name>
21331 <displayName>DMAR</displayName>
21332 <description>DMA address for full transfer</description>
21333 <addressOffset>0x4C</addressOffset>
21334 <size>0x20</size>
21335 <access>read-write</access>
21336 <resetValue>0x0000</resetValue>
21337 <fields>
21338 <field>
21339 <name>DMAB</name>
21340 <description>DMA register for burst
21341 accesses</description>
21342 <bitOffset>0</bitOffset>
21343 <bitWidth>16</bitWidth>
21344 </field>
21345 </fields>
21346 </register>
21347 <register>
21348 <name>OR1</name>
21349 <displayName>OR1</displayName>
21350 <description>TIM2 option register 1</description>
21351 <addressOffset>0x50</addressOffset>
21352 <size>0x20</size>
21353 <access>read-write</access>
21354 <resetValue>0x0000</resetValue>
21355 <fields>
21356 <field>
21357 <name>TI4_RMP</name>
21358 <description>Input Capture 4 remap</description>
21359 <bitOffset>2</bitOffset>
21360 <bitWidth>2</bitWidth>
21361 </field>
21362 <field>
21363 <name>ETR1_RMP</name>
21364 <description>External trigger remap</description>
21365 <bitOffset>1</bitOffset>
21366 <bitWidth>1</bitWidth>
21367 </field>
21368 <field>
21369 <name>ITR1_RMP</name>
21370 <description>Internal trigger 1 remap</description>
21371 <bitOffset>0</bitOffset>
21372 <bitWidth>1</bitWidth>
21373 </field>
21374 </fields>
21375 </register>
21376 <register>
21377 <name>OR2</name>
21378 <displayName>OR2</displayName>
21379 <description>TIM2 option register 2</description>
21380 <addressOffset>0x60</addressOffset>
21381 <size>0x20</size>
21382 <access>read-write</access>
21383 <resetValue>0x0000</resetValue>
21384 <fields>
21385 <field>
21386 <name>ETRSEL</name>
21387 <description>ETR source selection</description>
21388 <bitOffset>14</bitOffset>
21389 <bitWidth>3</bitWidth>
21390 </field>
21391 </fields>
21392 </register>
21393 </registers>
21394 </peripheral>
21395 <peripheral>
21396 <name>TIM3</name>
21397 <description>General purpose timers</description>
21398 <groupName>TIM</groupName>
21399 <baseAddress>0x40000400</baseAddress>
21400 <addressBlock>
21401 <offset>0x0</offset>
21402 <size>0x400</size>
21403 <usage>registers</usage>
21404 </addressBlock>
21405 <interrupt>
21406 <name>TIM3</name>
21407 <description>TIM3 global interrupt</description>
21408 <value>29</value>
21409 </interrupt>
21410 <registers>
21411 <register>
21412 <name>CR1</name>
21413 <displayName>CR1</displayName>
21414 <description>control register 1</description>
21415 <addressOffset>0x0</addressOffset>
21416 <size>0x20</size>
21417 <access>read-write</access>
21418 <resetValue>0x0000</resetValue>
21419 <fields>
21420 <field>
21421 <name>CKD</name>
21422 <description>Clock division</description>
21423 <bitOffset>8</bitOffset>
21424 <bitWidth>2</bitWidth>
21425 </field>
21426 <field>
21427 <name>ARPE</name>
21428 <description>Auto-reload preload enable</description>
21429 <bitOffset>7</bitOffset>
21430 <bitWidth>1</bitWidth>
21431 </field>
21432 <field>
21433 <name>CMS</name>
21434 <description>Center-aligned mode
21435 selection</description>
21436 <bitOffset>5</bitOffset>
21437 <bitWidth>2</bitWidth>
21438 </field>
21439 <field>
21440 <name>DIR</name>
21441 <description>Direction</description>
21442 <bitOffset>4</bitOffset>
21443 <bitWidth>1</bitWidth>
21444 </field>
21445 <field>
21446 <name>OPM</name>
21447 <description>One-pulse mode</description>
21448 <bitOffset>3</bitOffset>
21449 <bitWidth>1</bitWidth>
21450 </field>
21451 <field>
21452 <name>URS</name>
21453 <description>Update request source</description>
21454 <bitOffset>2</bitOffset>
21455 <bitWidth>1</bitWidth>
21456 </field>
21457 <field>
21458 <name>UDIS</name>
21459 <description>Update disable</description>
21460 <bitOffset>1</bitOffset>
21461 <bitWidth>1</bitWidth>
21462 </field>
21463 <field>
21464 <name>CEN</name>
21465 <description>Counter enable</description>
21466 <bitOffset>0</bitOffset>
21467 <bitWidth>1</bitWidth>
21468 </field>
21469 </fields>
21470 </register>
21471 <register>
21472 <name>CR2</name>
21473 <displayName>CR2</displayName>
21474 <description>control register 2</description>
21475 <addressOffset>0x4</addressOffset>
21476 <size>0x20</size>
21477 <access>read-write</access>
21478 <resetValue>0x0000</resetValue>
21479 <fields>
21480 <field>
21481 <name>TI1S</name>
21482 <description>TI1 selection</description>
21483 <bitOffset>7</bitOffset>
21484 <bitWidth>1</bitWidth>
21485 </field>
21486 <field>
21487 <name>MMS</name>
21488 <description>Master mode selection</description>
21489 <bitOffset>4</bitOffset>
21490 <bitWidth>3</bitWidth>
21491 </field>
21492 <field>
21493 <name>CCDS</name>
21494 <description>Capture/compare DMA
21495 selection</description>
21496 <bitOffset>3</bitOffset>
21497 <bitWidth>1</bitWidth>
21498 </field>
21499 </fields>
21500 </register>
21501 <register>
21502 <name>SMCR</name>
21503 <displayName>SMCR</displayName>
21504 <description>slave mode control register</description>
21505 <addressOffset>0x8</addressOffset>
21506 <size>0x20</size>
21507 <access>read-write</access>
21508 <resetValue>0x0000</resetValue>
21509 <fields>
21510 <field>
21511 <name>SMS</name>
21512 <description>Slave mode selection</description>
21513 <bitOffset>0</bitOffset>
21514 <bitWidth>3</bitWidth>
21515 </field>
21516 <field>
21517 <name>TS</name>
21518 <description>Trigger selection</description>
21519 <bitOffset>4</bitOffset>
21520 <bitWidth>3</bitWidth>
21521 </field>
21522 <field>
21523 <name>MSM</name>
21524 <description>Master/Slave mode</description>
21525 <bitOffset>7</bitOffset>
21526 <bitWidth>1</bitWidth>
21527 </field>
21528 <field>
21529 <name>ETF</name>
21530 <description>External trigger filter</description>
21531 <bitOffset>8</bitOffset>
21532 <bitWidth>4</bitWidth>
21533 </field>
21534 <field>
21535 <name>ETPS</name>
21536 <description>External trigger prescaler</description>
21537 <bitOffset>12</bitOffset>
21538 <bitWidth>2</bitWidth>
21539 </field>
21540 <field>
21541 <name>ECE</name>
21542 <description>External clock enable</description>
21543 <bitOffset>14</bitOffset>
21544 <bitWidth>1</bitWidth>
21545 </field>
21546 <field>
21547 <name>ETP</name>
21548 <description>External trigger polarity</description>
21549 <bitOffset>15</bitOffset>
21550 <bitWidth>1</bitWidth>
21551 </field>
21552 <field>
21553 <name>SMS_3</name>
21554 <description>Slave model selection -
21555 bit[3]</description>
21556 <bitOffset>16</bitOffset>
21557 <bitWidth>1</bitWidth>
21558 </field>
21559 </fields>
21560 </register>
21561 <register>
21562 <name>DIER</name>
21563 <displayName>DIER</displayName>
21564 <description>DMA/Interrupt enable register</description>
21565 <addressOffset>0xC</addressOffset>
21566 <size>0x20</size>
21567 <access>read-write</access>
21568 <resetValue>0x0000</resetValue>
21569 <fields>
21570 <field>
21571 <name>TDE</name>
21572 <description>Trigger DMA request enable</description>
21573 <bitOffset>14</bitOffset>
21574 <bitWidth>1</bitWidth>
21575 </field>
21576 <field>
21577 <name>CC4DE</name>
21578 <description>Capture/Compare 4 DMA request
21579 enable</description>
21580 <bitOffset>12</bitOffset>
21581 <bitWidth>1</bitWidth>
21582 </field>
21583 <field>
21584 <name>CC3DE</name>
21585 <description>Capture/Compare 3 DMA request
21586 enable</description>
21587 <bitOffset>11</bitOffset>
21588 <bitWidth>1</bitWidth>
21589 </field>
21590 <field>
21591 <name>CC2DE</name>
21592 <description>Capture/Compare 2 DMA request
21593 enable</description>
21594 <bitOffset>10</bitOffset>
21595 <bitWidth>1</bitWidth>
21596 </field>
21597 <field>
21598 <name>CC1DE</name>
21599 <description>Capture/Compare 1 DMA request
21600 enable</description>
21601 <bitOffset>9</bitOffset>
21602 <bitWidth>1</bitWidth>
21603 </field>
21604 <field>
21605 <name>UDE</name>
21606 <description>Update DMA request enable</description>
21607 <bitOffset>8</bitOffset>
21608 <bitWidth>1</bitWidth>
21609 </field>
21610 <field>
21611 <name>TIE</name>
21612 <description>Trigger interrupt enable</description>
21613 <bitOffset>6</bitOffset>
21614 <bitWidth>1</bitWidth>
21615 </field>
21616 <field>
21617 <name>CC4IE</name>
21618 <description>Capture/Compare 4 interrupt
21619 enable</description>
21620 <bitOffset>4</bitOffset>
21621 <bitWidth>1</bitWidth>
21622 </field>
21623 <field>
21624 <name>CC3IE</name>
21625 <description>Capture/Compare 3 interrupt
21626 enable</description>
21627 <bitOffset>3</bitOffset>
21628 <bitWidth>1</bitWidth>
21629 </field>
21630 <field>
21631 <name>CC2IE</name>
21632 <description>Capture/Compare 2 interrupt
21633 enable</description>
21634 <bitOffset>2</bitOffset>
21635 <bitWidth>1</bitWidth>
21636 </field>
21637 <field>
21638 <name>CC1IE</name>
21639 <description>Capture/Compare 1 interrupt
21640 enable</description>
21641 <bitOffset>1</bitOffset>
21642 <bitWidth>1</bitWidth>
21643 </field>
21644 <field>
21645 <name>UIE</name>
21646 <description>Update interrupt enable</description>
21647 <bitOffset>0</bitOffset>
21648 <bitWidth>1</bitWidth>
21649 </field>
21650 </fields>
21651 </register>
21652 <register>
21653 <name>SR</name>
21654 <displayName>SR</displayName>
21655 <description>status register</description>
21656 <addressOffset>0x10</addressOffset>
21657 <size>0x20</size>
21658 <access>read-write</access>
21659 <resetValue>0x0000</resetValue>
21660 <fields>
21661 <field>
21662 <name>CC4OF</name>
21663 <description>Capture/Compare 4 overcapture
21664 flag</description>
21665 <bitOffset>12</bitOffset>
21666 <bitWidth>1</bitWidth>
21667 </field>
21668 <field>
21669 <name>CC3OF</name>
21670 <description>Capture/Compare 3 overcapture
21671 flag</description>
21672 <bitOffset>11</bitOffset>
21673 <bitWidth>1</bitWidth>
21674 </field>
21675 <field>
21676 <name>CC2OF</name>
21677 <description>Capture/compare 2 overcapture
21678 flag</description>
21679 <bitOffset>10</bitOffset>
21680 <bitWidth>1</bitWidth>
21681 </field>
21682 <field>
21683 <name>CC1OF</name>
21684 <description>Capture/Compare 1 overcapture
21685 flag</description>
21686 <bitOffset>9</bitOffset>
21687 <bitWidth>1</bitWidth>
21688 </field>
21689 <field>
21690 <name>TIF</name>
21691 <description>Trigger interrupt flag</description>
21692 <bitOffset>6</bitOffset>
21693 <bitWidth>1</bitWidth>
21694 </field>
21695 <field>
21696 <name>CC4IF</name>
21697 <description>Capture/Compare 4 interrupt
21698 flag</description>
21699 <bitOffset>4</bitOffset>
21700 <bitWidth>1</bitWidth>
21701 </field>
21702 <field>
21703 <name>CC3IF</name>
21704 <description>Capture/Compare 3 interrupt
21705 flag</description>
21706 <bitOffset>3</bitOffset>
21707 <bitWidth>1</bitWidth>
21708 </field>
21709 <field>
21710 <name>CC2IF</name>
21711 <description>Capture/Compare 2 interrupt
21712 flag</description>
21713 <bitOffset>2</bitOffset>
21714 <bitWidth>1</bitWidth>
21715 </field>
21716 <field>
21717 <name>CC1IF</name>
21718 <description>Capture/compare 1 interrupt
21719 flag</description>
21720 <bitOffset>1</bitOffset>
21721 <bitWidth>1</bitWidth>
21722 </field>
21723 <field>
21724 <name>UIF</name>
21725 <description>Update interrupt flag</description>
21726 <bitOffset>0</bitOffset>
21727 <bitWidth>1</bitWidth>
21728 </field>
21729 </fields>
21730 </register>
21731 <register>
21732 <name>EGR</name>
21733 <displayName>EGR</displayName>
21734 <description>event generation register</description>
21735 <addressOffset>0x14</addressOffset>
21736 <size>0x20</size>
21737 <access>write-only</access>
21738 <resetValue>0x0000</resetValue>
21739 <fields>
21740 <field>
21741 <name>TG</name>
21742 <description>Trigger generation</description>
21743 <bitOffset>6</bitOffset>
21744 <bitWidth>1</bitWidth>
21745 </field>
21746 <field>
21747 <name>CC4G</name>
21748 <description>Capture/compare 4
21749 generation</description>
21750 <bitOffset>4</bitOffset>
21751 <bitWidth>1</bitWidth>
21752 </field>
21753 <field>
21754 <name>CC3G</name>
21755 <description>Capture/compare 3
21756 generation</description>
21757 <bitOffset>3</bitOffset>
21758 <bitWidth>1</bitWidth>
21759 </field>
21760 <field>
21761 <name>CC2G</name>
21762 <description>Capture/compare 2
21763 generation</description>
21764 <bitOffset>2</bitOffset>
21765 <bitWidth>1</bitWidth>
21766 </field>
21767 <field>
21768 <name>CC1G</name>
21769 <description>Capture/compare 1
21770 generation</description>
21771 <bitOffset>1</bitOffset>
21772 <bitWidth>1</bitWidth>
21773 </field>
21774 <field>
21775 <name>UG</name>
21776 <description>Update generation</description>
21777 <bitOffset>0</bitOffset>
21778 <bitWidth>1</bitWidth>
21779 </field>
21780 </fields>
21781 </register>
21782 <register>
21783 <name>CCMR1_Output</name>
21784 <displayName>CCMR1_Output</displayName>
21785 <description>capture/compare mode register 1 (output
21786 mode)</description>
21787 <addressOffset>0x18</addressOffset>
21788 <size>0x20</size>
21789 <access>read-write</access>
21790 <resetValue>0x00000000</resetValue>
21791 <fields>
21792 <field>
21793 <name>OC2CE</name>
21794 <description>OC2CE</description>
21795 <bitOffset>15</bitOffset>
21796 <bitWidth>1</bitWidth>
21797 </field>
21798 <field>
21799 <name>OC2M</name>
21800 <description>OC2M</description>
21801 <bitOffset>12</bitOffset>
21802 <bitWidth>3</bitWidth>
21803 </field>
21804 <field>
21805 <name>OC2PE</name>
21806 <description>OC2PE</description>
21807 <bitOffset>11</bitOffset>
21808 <bitWidth>1</bitWidth>
21809 </field>
21810 <field>
21811 <name>OC2FE</name>
21812 <description>OC2FE</description>
21813 <bitOffset>10</bitOffset>
21814 <bitWidth>1</bitWidth>
21815 </field>
21816 <field>
21817 <name>CC2S</name>
21818 <description>CC2S</description>
21819 <bitOffset>8</bitOffset>
21820 <bitWidth>2</bitWidth>
21821 </field>
21822 <field>
21823 <name>OC1CE</name>
21824 <description>OC1CE</description>
21825 <bitOffset>7</bitOffset>
21826 <bitWidth>1</bitWidth>
21827 </field>
21828 <field>
21829 <name>OC1M</name>
21830 <description>OC1M</description>
21831 <bitOffset>4</bitOffset>
21832 <bitWidth>3</bitWidth>
21833 </field>
21834 <field>
21835 <name>OC1PE</name>
21836 <description>OC1PE</description>
21837 <bitOffset>3</bitOffset>
21838 <bitWidth>1</bitWidth>
21839 </field>
21840 <field>
21841 <name>OC1FE</name>
21842 <description>OC1FE</description>
21843 <bitOffset>2</bitOffset>
21844 <bitWidth>1</bitWidth>
21845 </field>
21846 <field>
21847 <name>CC1S</name>
21848 <description>CC1S</description>
21849 <bitOffset>0</bitOffset>
21850 <bitWidth>2</bitWidth>
21851 </field>
21852 </fields>
21853 </register>
21854 <register>
21855 <name>CCMR1_Input</name>
21856 <displayName>CCMR1_Input</displayName>
21857 <description>capture/compare mode register 1 (input
21858 mode)</description>
21859 <alternateRegister>CCMR1_Output</alternateRegister>
21860 <addressOffset>0x18</addressOffset>
21861 <size>0x20</size>
21862 <access>read-write</access>
21863 <resetValue>0x00000000</resetValue>
21864 <fields>
21865 <field>
21866 <name>IC2F</name>
21867 <description>Input capture 2 filter</description>
21868 <bitOffset>12</bitOffset>
21869 <bitWidth>4</bitWidth>
21870 </field>
21871 <field>
21872 <name>IC2PCS</name>
21873 <description>Input capture 2 prescaler</description>
21874 <bitOffset>10</bitOffset>
21875 <bitWidth>2</bitWidth>
21876 </field>
21877 <field>
21878 <name>CC2S</name>
21879 <description>Capture/Compare 2
21880 selection</description>
21881 <bitOffset>8</bitOffset>
21882 <bitWidth>2</bitWidth>
21883 </field>
21884 <field>
21885 <name>IC1F</name>
21886 <description>Input capture 1 filter</description>
21887 <bitOffset>4</bitOffset>
21888 <bitWidth>4</bitWidth>
21889 </field>
21890 <field>
21891 <name>ICPCS</name>
21892 <description>Input capture 1 prescaler</description>
21893 <bitOffset>2</bitOffset>
21894 <bitWidth>2</bitWidth>
21895 </field>
21896 <field>
21897 <name>CC1S</name>
21898 <description>Capture/Compare 1
21899 selection</description>
21900 <bitOffset>0</bitOffset>
21901 <bitWidth>2</bitWidth>
21902 </field>
21903 </fields>
21904 </register>
21905 <register>
21906 <name>CCMR2_Output</name>
21907 <displayName>CCMR2_Output</displayName>
21908 <description>capture/compare mode register 2 (output
21909 mode)</description>
21910 <addressOffset>0x1C</addressOffset>
21911 <size>0x20</size>
21912 <access>read-write</access>
21913 <resetValue>0x00000000</resetValue>
21914 <fields>
21915 <field>
21916 <name>O24CE</name>
21917 <description>O24CE</description>
21918 <bitOffset>15</bitOffset>
21919 <bitWidth>1</bitWidth>
21920 </field>
21921 <field>
21922 <name>OC4M</name>
21923 <description>OC4M</description>
21924 <bitOffset>12</bitOffset>
21925 <bitWidth>3</bitWidth>
21926 </field>
21927 <field>
21928 <name>OC4PE</name>
21929 <description>OC4PE</description>
21930 <bitOffset>11</bitOffset>
21931 <bitWidth>1</bitWidth>
21932 </field>
21933 <field>
21934 <name>OC4FE</name>
21935 <description>OC4FE</description>
21936 <bitOffset>10</bitOffset>
21937 <bitWidth>1</bitWidth>
21938 </field>
21939 <field>
21940 <name>CC4S</name>
21941 <description>CC4S</description>
21942 <bitOffset>8</bitOffset>
21943 <bitWidth>2</bitWidth>
21944 </field>
21945 <field>
21946 <name>OC3CE</name>
21947 <description>OC3CE</description>
21948 <bitOffset>7</bitOffset>
21949 <bitWidth>1</bitWidth>
21950 </field>
21951 <field>
21952 <name>OC3M</name>
21953 <description>OC3M</description>
21954 <bitOffset>4</bitOffset>
21955 <bitWidth>3</bitWidth>
21956 </field>
21957 <field>
21958 <name>OC3PE</name>
21959 <description>OC3PE</description>
21960 <bitOffset>3</bitOffset>
21961 <bitWidth>1</bitWidth>
21962 </field>
21963 <field>
21964 <name>OC3FE</name>
21965 <description>OC3FE</description>
21966 <bitOffset>2</bitOffset>
21967 <bitWidth>1</bitWidth>
21968 </field>
21969 <field>
21970 <name>CC3S</name>
21971 <description>CC3S</description>
21972 <bitOffset>0</bitOffset>
21973 <bitWidth>2</bitWidth>
21974 </field>
21975 </fields>
21976 </register>
21977 <register>
21978 <name>CCMR2_Input</name>
21979 <displayName>CCMR2_Input</displayName>
21980 <description>capture/compare mode register 2 (input
21981 mode)</description>
21982 <alternateRegister>CCMR2_Output</alternateRegister>
21983 <addressOffset>0x1C</addressOffset>
21984 <size>0x20</size>
21985 <access>read-write</access>
21986 <resetValue>0x00000000</resetValue>
21987 <fields>
21988 <field>
21989 <name>IC4F</name>
21990 <description>Input capture 4 filter</description>
21991 <bitOffset>12</bitOffset>
21992 <bitWidth>4</bitWidth>
21993 </field>
21994 <field>
21995 <name>IC4PSC</name>
21996 <description>Input capture 4 prescaler</description>
21997 <bitOffset>10</bitOffset>
21998 <bitWidth>2</bitWidth>
21999 </field>
22000 <field>
22001 <name>CC4S</name>
22002 <description>Capture/Compare 4
22003 selection</description>
22004 <bitOffset>8</bitOffset>
22005 <bitWidth>2</bitWidth>
22006 </field>
22007 <field>
22008 <name>IC3F</name>
22009 <description>Input capture 3 filter</description>
22010 <bitOffset>4</bitOffset>
22011 <bitWidth>4</bitWidth>
22012 </field>
22013 <field>
22014 <name>IC3PSC</name>
22015 <description>Input capture 3 prescaler</description>
22016 <bitOffset>2</bitOffset>
22017 <bitWidth>2</bitWidth>
22018 </field>
22019 <field>
22020 <name>CC3S</name>
22021 <description>Capture/compare 3
22022 selection</description>
22023 <bitOffset>0</bitOffset>
22024 <bitWidth>2</bitWidth>
22025 </field>
22026 </fields>
22027 </register>
22028 <register>
22029 <name>CCER</name>
22030 <displayName>CCER</displayName>
22031 <description>capture/compare enable
22032 register</description>
22033 <addressOffset>0x20</addressOffset>
22034 <size>0x20</size>
22035 <access>read-write</access>
22036 <resetValue>0x0000</resetValue>
22037 <fields>
22038 <field>
22039 <name>CC4NP</name>
22040 <description>Capture/Compare 4 output
22041 Polarity</description>
22042 <bitOffset>15</bitOffset>
22043 <bitWidth>1</bitWidth>
22044 </field>
22045 <field>
22046 <name>CC4P</name>
22047 <description>Capture/Compare 3 output
22048 Polarity</description>
22049 <bitOffset>13</bitOffset>
22050 <bitWidth>1</bitWidth>
22051 </field>
22052 <field>
22053 <name>CC4E</name>
22054 <description>Capture/Compare 4 output
22055 enable</description>
22056 <bitOffset>12</bitOffset>
22057 <bitWidth>1</bitWidth>
22058 </field>
22059 <field>
22060 <name>CC3NP</name>
22061 <description>Capture/Compare 3 output
22062 Polarity</description>
22063 <bitOffset>11</bitOffset>
22064 <bitWidth>1</bitWidth>
22065 </field>
22066 <field>
22067 <name>CC3P</name>
22068 <description>Capture/Compare 3 output
22069 Polarity</description>
22070 <bitOffset>9</bitOffset>
22071 <bitWidth>1</bitWidth>
22072 </field>
22073 <field>
22074 <name>CC3E</name>
22075 <description>Capture/Compare 3 output
22076 enable</description>
22077 <bitOffset>8</bitOffset>
22078 <bitWidth>1</bitWidth>
22079 </field>
22080 <field>
22081 <name>CC2NP</name>
22082 <description>Capture/Compare 2 output
22083 Polarity</description>
22084 <bitOffset>7</bitOffset>
22085 <bitWidth>1</bitWidth>
22086 </field>
22087 <field>
22088 <name>CC2P</name>
22089 <description>Capture/Compare 2 output
22090 Polarity</description>
22091 <bitOffset>5</bitOffset>
22092 <bitWidth>1</bitWidth>
22093 </field>
22094 <field>
22095 <name>CC2E</name>
22096 <description>Capture/Compare 2 output
22097 enable</description>
22098 <bitOffset>4</bitOffset>
22099 <bitWidth>1</bitWidth>
22100 </field>
22101 <field>
22102 <name>CC1NP</name>
22103 <description>Capture/Compare 1 output
22104 Polarity</description>
22105 <bitOffset>3</bitOffset>
22106 <bitWidth>1</bitWidth>
22107 </field>
22108 <field>
22109 <name>CC1P</name>
22110 <description>Capture/Compare 1 output
22111 Polarity</description>
22112 <bitOffset>1</bitOffset>
22113 <bitWidth>1</bitWidth>
22114 </field>
22115 <field>
22116 <name>CC1E</name>
22117 <description>Capture/Compare 1 output
22118 enable</description>
22119 <bitOffset>0</bitOffset>
22120 <bitWidth>1</bitWidth>
22121 </field>
22122 </fields>
22123 </register>
22124 <register>
22125 <name>CNT</name>
22126 <displayName>CNT</displayName>
22127 <description>counter</description>
22128 <addressOffset>0x24</addressOffset>
22129 <size>0x20</size>
22130 <access>read-write</access>
22131 <resetValue>0x00000000</resetValue>
22132 <fields>
22133 <field>
22134 <name>CNT_H</name>
22135 <description>High counter value</description>
22136 <bitOffset>16</bitOffset>
22137 <bitWidth>16</bitWidth>
22138 </field>
22139 <field>
22140 <name>CNT_L</name>
22141 <description>Low counter value</description>
22142 <bitOffset>0</bitOffset>
22143 <bitWidth>16</bitWidth>
22144 </field>
22145 </fields>
22146 </register>
22147 <register>
22148 <name>PSC</name>
22149 <displayName>PSC</displayName>
22150 <description>prescaler</description>
22151 <addressOffset>0x28</addressOffset>
22152 <size>0x20</size>
22153 <access>read-write</access>
22154 <resetValue>0x0000</resetValue>
22155 <fields>
22156 <field>
22157 <name>PSC</name>
22158 <description>Prescaler value</description>
22159 <bitOffset>0</bitOffset>
22160 <bitWidth>16</bitWidth>
22161 </field>
22162 </fields>
22163 </register>
22164 <register>
22165 <name>ARR</name>
22166 <displayName>ARR</displayName>
22167 <description>auto-reload register</description>
22168 <addressOffset>0x2C</addressOffset>
22169 <size>0x20</size>
22170 <access>read-write</access>
22171 <resetValue>0x00000000</resetValue>
22172 <fields>
22173 <field>
22174 <name>ARR_H</name>
22175 <description>High Auto-reload value</description>
22176 <bitOffset>16</bitOffset>
22177 <bitWidth>16</bitWidth>
22178 </field>
22179 <field>
22180 <name>ARR_L</name>
22181 <description>Low Auto-reload value</description>
22182 <bitOffset>0</bitOffset>
22183 <bitWidth>16</bitWidth>
22184 </field>
22185 </fields>
22186 </register>
22187 <register>
22188 <name>CCR1</name>
22189 <displayName>CCR1</displayName>
22190 <description>capture/compare register 1</description>
22191 <addressOffset>0x34</addressOffset>
22192 <size>0x20</size>
22193 <access>read-write</access>
22194 <resetValue>0x00000000</resetValue>
22195 <fields>
22196 <field>
22197 <name>CCR1_H</name>
22198 <description>High Capture/Compare 1
22199 value</description>
22200 <bitOffset>16</bitOffset>
22201 <bitWidth>16</bitWidth>
22202 </field>
22203 <field>
22204 <name>CCR1_L</name>
22205 <description>Low Capture/Compare 1
22206 value</description>
22207 <bitOffset>0</bitOffset>
22208 <bitWidth>16</bitWidth>
22209 </field>
22210 </fields>
22211 </register>
22212 <register>
22213 <name>CCR2</name>
22214 <displayName>CCR2</displayName>
22215 <description>capture/compare register 2</description>
22216 <addressOffset>0x38</addressOffset>
22217 <size>0x20</size>
22218 <access>read-write</access>
22219 <resetValue>0x00000000</resetValue>
22220 <fields>
22221 <field>
22222 <name>CCR2_H</name>
22223 <description>High Capture/Compare 2
22224 value</description>
22225 <bitOffset>16</bitOffset>
22226 <bitWidth>16</bitWidth>
22227 </field>
22228 <field>
22229 <name>CCR2_L</name>
22230 <description>Low Capture/Compare 2
22231 value</description>
22232 <bitOffset>0</bitOffset>
22233 <bitWidth>16</bitWidth>
22234 </field>
22235 </fields>
22236 </register>
22237 <register>
22238 <name>CCR3</name>
22239 <displayName>CCR3</displayName>
22240 <description>capture/compare register 3</description>
22241 <addressOffset>0x3C</addressOffset>
22242 <size>0x20</size>
22243 <access>read-write</access>
22244 <resetValue>0x00000000</resetValue>
22245 <fields>
22246 <field>
22247 <name>CCR3_H</name>
22248 <description>High Capture/Compare value</description>
22249 <bitOffset>16</bitOffset>
22250 <bitWidth>16</bitWidth>
22251 </field>
22252 <field>
22253 <name>CCR3_L</name>
22254 <description>Low Capture/Compare value</description>
22255 <bitOffset>0</bitOffset>
22256 <bitWidth>16</bitWidth>
22257 </field>
22258 </fields>
22259 </register>
22260 <register>
22261 <name>CCR4</name>
22262 <displayName>CCR4</displayName>
22263 <description>capture/compare register 4</description>
22264 <addressOffset>0x40</addressOffset>
22265 <size>0x20</size>
22266 <access>read-write</access>
22267 <resetValue>0x00000000</resetValue>
22268 <fields>
22269 <field>
22270 <name>CCR4_H</name>
22271 <description>High Capture/Compare value</description>
22272 <bitOffset>16</bitOffset>
22273 <bitWidth>16</bitWidth>
22274 </field>
22275 <field>
22276 <name>CCR4_L</name>
22277 <description>Low Capture/Compare value</description>
22278 <bitOffset>0</bitOffset>
22279 <bitWidth>16</bitWidth>
22280 </field>
22281 </fields>
22282 </register>
22283 <register>
22284 <name>DCR</name>
22285 <displayName>DCR</displayName>
22286 <description>DMA control register</description>
22287 <addressOffset>0x48</addressOffset>
22288 <size>0x20</size>
22289 <access>read-write</access>
22290 <resetValue>0x0000</resetValue>
22291 <fields>
22292 <field>
22293 <name>DBL</name>
22294 <description>DMA burst length</description>
22295 <bitOffset>8</bitOffset>
22296 <bitWidth>5</bitWidth>
22297 </field>
22298 <field>
22299 <name>DBA</name>
22300 <description>DMA base address</description>
22301 <bitOffset>0</bitOffset>
22302 <bitWidth>5</bitWidth>
22303 </field>
22304 </fields>
22305 </register>
22306 <register>
22307 <name>DMAR</name>
22308 <displayName>DMAR</displayName>
22309 <description>DMA address for full transfer</description>
22310 <addressOffset>0x4C</addressOffset>
22311 <size>0x20</size>
22312 <access>read-write</access>
22313 <resetValue>0x0000</resetValue>
22314 <fields>
22315 <field>
22316 <name>DMAB</name>
22317 <description>DMA register for burst
22318 accesses</description>
22319 <bitOffset>0</bitOffset>
22320 <bitWidth>16</bitWidth>
22321 </field>
22322 </fields>
22323 </register>
22324 <register>
22325 <name>OR1</name>
22326 <displayName>OR1</displayName>
22327 <description>TIM3 option register 1</description>
22328 <addressOffset>0x50</addressOffset>
22329 <size>0x20</size>
22330 <access>read-write</access>
22331 <resetValue>0x0000</resetValue>
22332 <fields>
22333 <field>
22334 <name>TI1_RMP</name>
22335 <description>Input Capture 1 remap</description>
22336 <bitOffset>0</bitOffset>
22337 <bitWidth>2</bitWidth>
22338 </field>
22339 </fields>
22340 </register>
22341 <register>
22342 <name>OR2</name>
22343 <displayName>OR2</displayName>
22344 <description>TIM3 option register 2</description>
22345 <addressOffset>0x60</addressOffset>
22346 <size>0x20</size>
22347 <access>read-write</access>
22348 <resetValue>0x0000</resetValue>
22349 <fields>
22350 <field>
22351 <name>ETRSEL</name>
22352 <description>ETR source selection</description>
22353 <bitOffset>14</bitOffset>
22354 <bitWidth>3</bitWidth>
22355 </field>
22356 </fields>
22357 </register>
22358 </registers>
22359 </peripheral>
22360 <peripheral>
22361 <name>TIM4</name>
22362 <description>General purpose timers</description>
22363 <groupName>TIM</groupName>
22364 <baseAddress>0x40000800</baseAddress>
22365 <addressBlock>
22366 <offset>0x0</offset>
22367 <size>0x400</size>
22368 <usage>registers</usage>
22369 </addressBlock>
22370 <interrupt>
22371 <name>TIM4</name>
22372 <description>TIM4 global interrupt</description>
22373 <value>30</value>
22374 </interrupt>
22375 <registers>
22376 <register>
22377 <name>CR1</name>
22378 <displayName>CR1</displayName>
22379 <description>control register 1</description>
22380 <addressOffset>0x0</addressOffset>
22381 <size>0x20</size>
22382 <access>read-write</access>
22383 <resetValue>0x0000</resetValue>
22384 <fields>
22385 <field>
22386 <name>CKD</name>
22387 <description>Clock division</description>
22388 <bitOffset>8</bitOffset>
22389 <bitWidth>2</bitWidth>
22390 </field>
22391 <field>
22392 <name>ARPE</name>
22393 <description>Auto-reload preload enable</description>
22394 <bitOffset>7</bitOffset>
22395 <bitWidth>1</bitWidth>
22396 </field>
22397 <field>
22398 <name>CMS</name>
22399 <description>Center-aligned mode
22400 selection</description>
22401 <bitOffset>5</bitOffset>
22402 <bitWidth>2</bitWidth>
22403 </field>
22404 <field>
22405 <name>DIR</name>
22406 <description>Direction</description>
22407 <bitOffset>4</bitOffset>
22408 <bitWidth>1</bitWidth>
22409 </field>
22410 <field>
22411 <name>OPM</name>
22412 <description>One-pulse mode</description>
22413 <bitOffset>3</bitOffset>
22414 <bitWidth>1</bitWidth>
22415 </field>
22416 <field>
22417 <name>URS</name>
22418 <description>Update request source</description>
22419 <bitOffset>2</bitOffset>
22420 <bitWidth>1</bitWidth>
22421 </field>
22422 <field>
22423 <name>UDIS</name>
22424 <description>Update disable</description>
22425 <bitOffset>1</bitOffset>
22426 <bitWidth>1</bitWidth>
22427 </field>
22428 <field>
22429 <name>CEN</name>
22430 <description>Counter enable</description>
22431 <bitOffset>0</bitOffset>
22432 <bitWidth>1</bitWidth>
22433 </field>
22434 </fields>
22435 </register>
22436 <register>
22437 <name>CR2</name>
22438 <displayName>CR2</displayName>
22439 <description>control register 2</description>
22440 <addressOffset>0x4</addressOffset>
22441 <size>0x20</size>
22442 <access>read-write</access>
22443 <resetValue>0x0000</resetValue>
22444 <fields>
22445 <field>
22446 <name>TI1S</name>
22447 <description>TI1 selection</description>
22448 <bitOffset>7</bitOffset>
22449 <bitWidth>1</bitWidth>
22450 </field>
22451 <field>
22452 <name>MMS</name>
22453 <description>Master mode selection</description>
22454 <bitOffset>4</bitOffset>
22455 <bitWidth>3</bitWidth>
22456 </field>
22457 <field>
22458 <name>CCDS</name>
22459 <description>Capture/compare DMA
22460 selection</description>
22461 <bitOffset>3</bitOffset>
22462 <bitWidth>1</bitWidth>
22463 </field>
22464 </fields>
22465 </register>
22466 <register>
22467 <name>SMCR</name>
22468 <displayName>SMCR</displayName>
22469 <description>slave mode control register</description>
22470 <addressOffset>0x8</addressOffset>
22471 <size>0x20</size>
22472 <access>read-write</access>
22473 <resetValue>0x0000</resetValue>
22474 <fields>
22475 <field>
22476 <name>SMS</name>
22477 <description>Slave mode selection</description>
22478 <bitOffset>0</bitOffset>
22479 <bitWidth>3</bitWidth>
22480 </field>
22481 <field>
22482 <name>TS</name>
22483 <description>Trigger selection</description>
22484 <bitOffset>4</bitOffset>
22485 <bitWidth>3</bitWidth>
22486 </field>
22487 <field>
22488 <name>MSM</name>
22489 <description>Master/Slave mode</description>
22490 <bitOffset>7</bitOffset>
22491 <bitWidth>1</bitWidth>
22492 </field>
22493 <field>
22494 <name>ETF</name>
22495 <description>External trigger filter</description>
22496 <bitOffset>8</bitOffset>
22497 <bitWidth>4</bitWidth>
22498 </field>
22499 <field>
22500 <name>ETPS</name>
22501 <description>External trigger prescaler</description>
22502 <bitOffset>12</bitOffset>
22503 <bitWidth>2</bitWidth>
22504 </field>
22505 <field>
22506 <name>ECE</name>
22507 <description>External clock enable</description>
22508 <bitOffset>14</bitOffset>
22509 <bitWidth>1</bitWidth>
22510 </field>
22511 <field>
22512 <name>ETP</name>
22513 <description>External trigger polarity</description>
22514 <bitOffset>15</bitOffset>
22515 <bitWidth>1</bitWidth>
22516 </field>
22517 <field>
22518 <name>SMS_3</name>
22519 <description>Slave model selection -
22520 bit[3]</description>
22521 <bitOffset>16</bitOffset>
22522 <bitWidth>1</bitWidth>
22523 </field>
22524 </fields>
22525 </register>
22526 <register>
22527 <name>DIER</name>
22528 <displayName>DIER</displayName>
22529 <description>DMA/Interrupt enable register</description>
22530 <addressOffset>0xC</addressOffset>
22531 <size>0x20</size>
22532 <access>read-write</access>
22533 <resetValue>0x0000</resetValue>
22534 <fields>
22535 <field>
22536 <name>TDE</name>
22537 <description>Trigger DMA request enable</description>
22538 <bitOffset>14</bitOffset>
22539 <bitWidth>1</bitWidth>
22540 </field>
22541 <field>
22542 <name>CC4DE</name>
22543 <description>Capture/Compare 4 DMA request
22544 enable</description>
22545 <bitOffset>12</bitOffset>
22546 <bitWidth>1</bitWidth>
22547 </field>
22548 <field>
22549 <name>CC3DE</name>
22550 <description>Capture/Compare 3 DMA request
22551 enable</description>
22552 <bitOffset>11</bitOffset>
22553 <bitWidth>1</bitWidth>
22554 </field>
22555 <field>
22556 <name>CC2DE</name>
22557 <description>Capture/Compare 2 DMA request
22558 enable</description>
22559 <bitOffset>10</bitOffset>
22560 <bitWidth>1</bitWidth>
22561 </field>
22562 <field>
22563 <name>CC1DE</name>
22564 <description>Capture/Compare 1 DMA request
22565 enable</description>
22566 <bitOffset>9</bitOffset>
22567 <bitWidth>1</bitWidth>
22568 </field>
22569 <field>
22570 <name>UDE</name>
22571 <description>Update DMA request enable</description>
22572 <bitOffset>8</bitOffset>
22573 <bitWidth>1</bitWidth>
22574 </field>
22575 <field>
22576 <name>TIE</name>
22577 <description>Trigger interrupt enable</description>
22578 <bitOffset>6</bitOffset>
22579 <bitWidth>1</bitWidth>
22580 </field>
22581 <field>
22582 <name>CC4IE</name>
22583 <description>Capture/Compare 4 interrupt
22584 enable</description>
22585 <bitOffset>4</bitOffset>
22586 <bitWidth>1</bitWidth>
22587 </field>
22588 <field>
22589 <name>CC3IE</name>
22590 <description>Capture/Compare 3 interrupt
22591 enable</description>
22592 <bitOffset>3</bitOffset>
22593 <bitWidth>1</bitWidth>
22594 </field>
22595 <field>
22596 <name>CC2IE</name>
22597 <description>Capture/Compare 2 interrupt
22598 enable</description>
22599 <bitOffset>2</bitOffset>
22600 <bitWidth>1</bitWidth>
22601 </field>
22602 <field>
22603 <name>CC1IE</name>
22604 <description>Capture/Compare 1 interrupt
22605 enable</description>
22606 <bitOffset>1</bitOffset>
22607 <bitWidth>1</bitWidth>
22608 </field>
22609 <field>
22610 <name>UIE</name>
22611 <description>Update interrupt enable</description>
22612 <bitOffset>0</bitOffset>
22613 <bitWidth>1</bitWidth>
22614 </field>
22615 </fields>
22616 </register>
22617 <register>
22618 <name>SR</name>
22619 <displayName>SR</displayName>
22620 <description>status register</description>
22621 <addressOffset>0x10</addressOffset>
22622 <size>0x20</size>
22623 <access>read-write</access>
22624 <resetValue>0x0000</resetValue>
22625 <fields>
22626 <field>
22627 <name>CC4OF</name>
22628 <description>Capture/Compare 4 overcapture
22629 flag</description>
22630 <bitOffset>12</bitOffset>
22631 <bitWidth>1</bitWidth>
22632 </field>
22633 <field>
22634 <name>CC3OF</name>
22635 <description>Capture/Compare 3 overcapture
22636 flag</description>
22637 <bitOffset>11</bitOffset>
22638 <bitWidth>1</bitWidth>
22639 </field>
22640 <field>
22641 <name>CC2OF</name>
22642 <description>Capture/compare 2 overcapture
22643 flag</description>
22644 <bitOffset>10</bitOffset>
22645 <bitWidth>1</bitWidth>
22646 </field>
22647 <field>
22648 <name>CC1OF</name>
22649 <description>Capture/Compare 1 overcapture
22650 flag</description>
22651 <bitOffset>9</bitOffset>
22652 <bitWidth>1</bitWidth>
22653 </field>
22654 <field>
22655 <name>TIF</name>
22656 <description>Trigger interrupt flag</description>
22657 <bitOffset>6</bitOffset>
22658 <bitWidth>1</bitWidth>
22659 </field>
22660 <field>
22661 <name>CC4IF</name>
22662 <description>Capture/Compare 4 interrupt
22663 flag</description>
22664 <bitOffset>4</bitOffset>
22665 <bitWidth>1</bitWidth>
22666 </field>
22667 <field>
22668 <name>CC3IF</name>
22669 <description>Capture/Compare 3 interrupt
22670 flag</description>
22671 <bitOffset>3</bitOffset>
22672 <bitWidth>1</bitWidth>
22673 </field>
22674 <field>
22675 <name>CC2IF</name>
22676 <description>Capture/Compare 2 interrupt
22677 flag</description>
22678 <bitOffset>2</bitOffset>
22679 <bitWidth>1</bitWidth>
22680 </field>
22681 <field>
22682 <name>CC1IF</name>
22683 <description>Capture/compare 1 interrupt
22684 flag</description>
22685 <bitOffset>1</bitOffset>
22686 <bitWidth>1</bitWidth>
22687 </field>
22688 <field>
22689 <name>UIF</name>
22690 <description>Update interrupt flag</description>
22691 <bitOffset>0</bitOffset>
22692 <bitWidth>1</bitWidth>
22693 </field>
22694 </fields>
22695 </register>
22696 <register>
22697 <name>EGR</name>
22698 <displayName>EGR</displayName>
22699 <description>event generation register</description>
22700 <addressOffset>0x14</addressOffset>
22701 <size>0x20</size>
22702 <access>write-only</access>
22703 <resetValue>0x0000</resetValue>
22704 <fields>
22705 <field>
22706 <name>TG</name>
22707 <description>Trigger generation</description>
22708 <bitOffset>6</bitOffset>
22709 <bitWidth>1</bitWidth>
22710 </field>
22711 <field>
22712 <name>CC4G</name>
22713 <description>Capture/compare 4
22714 generation</description>
22715 <bitOffset>4</bitOffset>
22716 <bitWidth>1</bitWidth>
22717 </field>
22718 <field>
22719 <name>CC3G</name>
22720 <description>Capture/compare 3
22721 generation</description>
22722 <bitOffset>3</bitOffset>
22723 <bitWidth>1</bitWidth>
22724 </field>
22725 <field>
22726 <name>CC2G</name>
22727 <description>Capture/compare 2
22728 generation</description>
22729 <bitOffset>2</bitOffset>
22730 <bitWidth>1</bitWidth>
22731 </field>
22732 <field>
22733 <name>CC1G</name>
22734 <description>Capture/compare 1
22735 generation</description>
22736 <bitOffset>1</bitOffset>
22737 <bitWidth>1</bitWidth>
22738 </field>
22739 <field>
22740 <name>UG</name>
22741 <description>Update generation</description>
22742 <bitOffset>0</bitOffset>
22743 <bitWidth>1</bitWidth>
22744 </field>
22745 </fields>
22746 </register>
22747 <register>
22748 <name>CCMR1_Output</name>
22749 <displayName>CCMR1_Output</displayName>
22750 <description>capture/compare mode register 1 (output
22751 mode)</description>
22752 <addressOffset>0x18</addressOffset>
22753 <size>0x20</size>
22754 <access>read-write</access>
22755 <resetValue>0x00000000</resetValue>
22756 <fields>
22757 <field>
22758 <name>OC2CE</name>
22759 <description>OC2CE</description>
22760 <bitOffset>15</bitOffset>
22761 <bitWidth>1</bitWidth>
22762 </field>
22763 <field>
22764 <name>OC2M</name>
22765 <description>OC2M</description>
22766 <bitOffset>12</bitOffset>
22767 <bitWidth>3</bitWidth>
22768 </field>
22769 <field>
22770 <name>OC2PE</name>
22771 <description>OC2PE</description>
22772 <bitOffset>11</bitOffset>
22773 <bitWidth>1</bitWidth>
22774 </field>
22775 <field>
22776 <name>OC2FE</name>
22777 <description>OC2FE</description>
22778 <bitOffset>10</bitOffset>
22779 <bitWidth>1</bitWidth>
22780 </field>
22781 <field>
22782 <name>CC2S</name>
22783 <description>CC2S</description>
22784 <bitOffset>8</bitOffset>
22785 <bitWidth>2</bitWidth>
22786 </field>
22787 <field>
22788 <name>OC1CE</name>
22789 <description>OC1CE</description>
22790 <bitOffset>7</bitOffset>
22791 <bitWidth>1</bitWidth>
22792 </field>
22793 <field>
22794 <name>OC1M</name>
22795 <description>OC1M</description>
22796 <bitOffset>4</bitOffset>
22797 <bitWidth>3</bitWidth>
22798 </field>
22799 <field>
22800 <name>OC1PE</name>
22801 <description>OC1PE</description>
22802 <bitOffset>3</bitOffset>
22803 <bitWidth>1</bitWidth>
22804 </field>
22805 <field>
22806 <name>OC1FE</name>
22807 <description>OC1FE</description>
22808 <bitOffset>2</bitOffset>
22809 <bitWidth>1</bitWidth>
22810 </field>
22811 <field>
22812 <name>CC1S</name>
22813 <description>CC1S</description>
22814 <bitOffset>0</bitOffset>
22815 <bitWidth>2</bitWidth>
22816 </field>
22817 </fields>
22818 </register>
22819 <register>
22820 <name>CCMR1_Input</name>
22821 <displayName>CCMR1_Input</displayName>
22822 <description>capture/compare mode register 1 (input
22823 mode)</description>
22824 <alternateRegister>CCMR1_Output</alternateRegister>
22825 <addressOffset>0x18</addressOffset>
22826 <size>0x20</size>
22827 <access>read-write</access>
22828 <resetValue>0x00000000</resetValue>
22829 <fields>
22830 <field>
22831 <name>IC2F</name>
22832 <description>Input capture 2 filter</description>
22833 <bitOffset>12</bitOffset>
22834 <bitWidth>4</bitWidth>
22835 </field>
22836 <field>
22837 <name>IC2PCS</name>
22838 <description>Input capture 2 prescaler</description>
22839 <bitOffset>10</bitOffset>
22840 <bitWidth>2</bitWidth>
22841 </field>
22842 <field>
22843 <name>CC2S</name>
22844 <description>Capture/Compare 2
22845 selection</description>
22846 <bitOffset>8</bitOffset>
22847 <bitWidth>2</bitWidth>
22848 </field>
22849 <field>
22850 <name>IC1F</name>
22851 <description>Input capture 1 filter</description>
22852 <bitOffset>4</bitOffset>
22853 <bitWidth>4</bitWidth>
22854 </field>
22855 <field>
22856 <name>ICPCS</name>
22857 <description>Input capture 1 prescaler</description>
22858 <bitOffset>2</bitOffset>
22859 <bitWidth>2</bitWidth>
22860 </field>
22861 <field>
22862 <name>CC1S</name>
22863 <description>Capture/Compare 1
22864 selection</description>
22865 <bitOffset>0</bitOffset>
22866 <bitWidth>2</bitWidth>
22867 </field>
22868 </fields>
22869 </register>
22870 <register>
22871 <name>CCMR2_Output</name>
22872 <displayName>CCMR2_Output</displayName>
22873 <description>capture/compare mode register 2 (output
22874 mode)</description>
22875 <addressOffset>0x1C</addressOffset>
22876 <size>0x20</size>
22877 <access>read-write</access>
22878 <resetValue>0x00000000</resetValue>
22879 <fields>
22880 <field>
22881 <name>O24CE</name>
22882 <description>O24CE</description>
22883 <bitOffset>15</bitOffset>
22884 <bitWidth>1</bitWidth>
22885 </field>
22886 <field>
22887 <name>OC4M</name>
22888 <description>OC4M</description>
22889 <bitOffset>12</bitOffset>
22890 <bitWidth>3</bitWidth>
22891 </field>
22892 <field>
22893 <name>OC4PE</name>
22894 <description>OC4PE</description>
22895 <bitOffset>11</bitOffset>
22896 <bitWidth>1</bitWidth>
22897 </field>
22898 <field>
22899 <name>OC4FE</name>
22900 <description>OC4FE</description>
22901 <bitOffset>10</bitOffset>
22902 <bitWidth>1</bitWidth>
22903 </field>
22904 <field>
22905 <name>CC4S</name>
22906 <description>CC4S</description>
22907 <bitOffset>8</bitOffset>
22908 <bitWidth>2</bitWidth>
22909 </field>
22910 <field>
22911 <name>OC3CE</name>
22912 <description>OC3CE</description>
22913 <bitOffset>7</bitOffset>
22914 <bitWidth>1</bitWidth>
22915 </field>
22916 <field>
22917 <name>OC3M</name>
22918 <description>OC3M</description>
22919 <bitOffset>4</bitOffset>
22920 <bitWidth>3</bitWidth>
22921 </field>
22922 <field>
22923 <name>OC3PE</name>
22924 <description>OC3PE</description>
22925 <bitOffset>3</bitOffset>
22926 <bitWidth>1</bitWidth>
22927 </field>
22928 <field>
22929 <name>OC3FE</name>
22930 <description>OC3FE</description>
22931 <bitOffset>2</bitOffset>
22932 <bitWidth>1</bitWidth>
22933 </field>
22934 <field>
22935 <name>CC3S</name>
22936 <description>CC3S</description>
22937 <bitOffset>0</bitOffset>
22938 <bitWidth>2</bitWidth>
22939 </field>
22940 </fields>
22941 </register>
22942 <register>
22943 <name>CCMR2_Input</name>
22944 <displayName>CCMR2_Input</displayName>
22945 <description>capture/compare mode register 2 (input
22946 mode)</description>
22947 <alternateRegister>CCMR2_Output</alternateRegister>
22948 <addressOffset>0x1C</addressOffset>
22949 <size>0x20</size>
22950 <access>read-write</access>
22951 <resetValue>0x00000000</resetValue>
22952 <fields>
22953 <field>
22954 <name>IC4F</name>
22955 <description>Input capture 4 filter</description>
22956 <bitOffset>12</bitOffset>
22957 <bitWidth>4</bitWidth>
22958 </field>
22959 <field>
22960 <name>IC4PSC</name>
22961 <description>Input capture 4 prescaler</description>
22962 <bitOffset>10</bitOffset>
22963 <bitWidth>2</bitWidth>
22964 </field>
22965 <field>
22966 <name>CC4S</name>
22967 <description>Capture/Compare 4
22968 selection</description>
22969 <bitOffset>8</bitOffset>
22970 <bitWidth>2</bitWidth>
22971 </field>
22972 <field>
22973 <name>IC3F</name>
22974 <description>Input capture 3 filter</description>
22975 <bitOffset>4</bitOffset>
22976 <bitWidth>4</bitWidth>
22977 </field>
22978 <field>
22979 <name>IC3PSC</name>
22980 <description>Input capture 3 prescaler</description>
22981 <bitOffset>2</bitOffset>
22982 <bitWidth>2</bitWidth>
22983 </field>
22984 <field>
22985 <name>CC3S</name>
22986 <description>Capture/compare 3
22987 selection</description>
22988 <bitOffset>0</bitOffset>
22989 <bitWidth>2</bitWidth>
22990 </field>
22991 </fields>
22992 </register>
22993 <register>
22994 <name>CCER</name>
22995 <displayName>CCER</displayName>
22996 <description>capture/compare enable
22997 register</description>
22998 <addressOffset>0x20</addressOffset>
22999 <size>0x20</size>
23000 <access>read-write</access>
23001 <resetValue>0x0000</resetValue>
23002 <fields>
23003 <field>
23004 <name>CC4NP</name>
23005 <description>Capture/Compare 4 output
23006 Polarity</description>
23007 <bitOffset>15</bitOffset>
23008 <bitWidth>1</bitWidth>
23009 </field>
23010 <field>
23011 <name>CC4P</name>
23012 <description>Capture/Compare 3 output
23013 Polarity</description>
23014 <bitOffset>13</bitOffset>
23015 <bitWidth>1</bitWidth>
23016 </field>
23017 <field>
23018 <name>CC4E</name>
23019 <description>Capture/Compare 4 output
23020 enable</description>
23021 <bitOffset>12</bitOffset>
23022 <bitWidth>1</bitWidth>
23023 </field>
23024 <field>
23025 <name>CC3NP</name>
23026 <description>Capture/Compare 3 output
23027 Polarity</description>
23028 <bitOffset>11</bitOffset>
23029 <bitWidth>1</bitWidth>
23030 </field>
23031 <field>
23032 <name>CC3P</name>
23033 <description>Capture/Compare 3 output
23034 Polarity</description>
23035 <bitOffset>9</bitOffset>
23036 <bitWidth>1</bitWidth>
23037 </field>
23038 <field>
23039 <name>CC3E</name>
23040 <description>Capture/Compare 3 output
23041 enable</description>
23042 <bitOffset>8</bitOffset>
23043 <bitWidth>1</bitWidth>
23044 </field>
23045 <field>
23046 <name>CC2NP</name>
23047 <description>Capture/Compare 2 output
23048 Polarity</description>
23049 <bitOffset>7</bitOffset>
23050 <bitWidth>1</bitWidth>
23051 </field>
23052 <field>
23053 <name>CC2P</name>
23054 <description>Capture/Compare 2 output
23055 Polarity</description>
23056 <bitOffset>5</bitOffset>
23057 <bitWidth>1</bitWidth>
23058 </field>
23059 <field>
23060 <name>CC2E</name>
23061 <description>Capture/Compare 2 output
23062 enable</description>
23063 <bitOffset>4</bitOffset>
23064 <bitWidth>1</bitWidth>
23065 </field>
23066 <field>
23067 <name>CC1NP</name>
23068 <description>Capture/Compare 1 output
23069 Polarity</description>
23070 <bitOffset>3</bitOffset>
23071 <bitWidth>1</bitWidth>
23072 </field>
23073 <field>
23074 <name>CC1P</name>
23075 <description>Capture/Compare 1 output
23076 Polarity</description>
23077 <bitOffset>1</bitOffset>
23078 <bitWidth>1</bitWidth>
23079 </field>
23080 <field>
23081 <name>CC1E</name>
23082 <description>Capture/Compare 1 output
23083 enable</description>
23084 <bitOffset>0</bitOffset>
23085 <bitWidth>1</bitWidth>
23086 </field>
23087 </fields>
23088 </register>
23089 <register>
23090 <name>CNT</name>
23091 <displayName>CNT</displayName>
23092 <description>counter</description>
23093 <addressOffset>0x24</addressOffset>
23094 <size>0x20</size>
23095 <access>read-write</access>
23096 <resetValue>0x00000000</resetValue>
23097 <fields>
23098 <field>
23099 <name>CNT_H</name>
23100 <description>High counter value</description>
23101 <bitOffset>16</bitOffset>
23102 <bitWidth>16</bitWidth>
23103 </field>
23104 <field>
23105 <name>CNT_L</name>
23106 <description>Low counter value</description>
23107 <bitOffset>0</bitOffset>
23108 <bitWidth>16</bitWidth>
23109 </field>
23110 </fields>
23111 </register>
23112 <register>
23113 <name>PSC</name>
23114 <displayName>PSC</displayName>
23115 <description>prescaler</description>
23116 <addressOffset>0x28</addressOffset>
23117 <size>0x20</size>
23118 <access>read-write</access>
23119 <resetValue>0x0000</resetValue>
23120 <fields>
23121 <field>
23122 <name>PSC</name>
23123 <description>Prescaler value</description>
23124 <bitOffset>0</bitOffset>
23125 <bitWidth>16</bitWidth>
23126 </field>
23127 </fields>
23128 </register>
23129 <register>
23130 <name>ARR</name>
23131 <displayName>ARR</displayName>
23132 <description>auto-reload register</description>
23133 <addressOffset>0x2C</addressOffset>
23134 <size>0x20</size>
23135 <access>read-write</access>
23136 <resetValue>0x00000000</resetValue>
23137 <fields>
23138 <field>
23139 <name>ARR_H</name>
23140 <description>High Auto-reload value</description>
23141 <bitOffset>16</bitOffset>
23142 <bitWidth>16</bitWidth>
23143 </field>
23144 <field>
23145 <name>ARR_L</name>
23146 <description>Low Auto-reload value</description>
23147 <bitOffset>0</bitOffset>
23148 <bitWidth>16</bitWidth>
23149 </field>
23150 </fields>
23151 </register>
23152 <register>
23153 <name>CCR1</name>
23154 <displayName>CCR1</displayName>
23155 <description>capture/compare register 1</description>
23156 <addressOffset>0x34</addressOffset>
23157 <size>0x20</size>
23158 <access>read-write</access>
23159 <resetValue>0x00000000</resetValue>
23160 <fields>
23161 <field>
23162 <name>CCR1_H</name>
23163 <description>High Capture/Compare 1
23164 value</description>
23165 <bitOffset>16</bitOffset>
23166 <bitWidth>16</bitWidth>
23167 </field>
23168 <field>
23169 <name>CCR1_L</name>
23170 <description>Low Capture/Compare 1
23171 value</description>
23172 <bitOffset>0</bitOffset>
23173 <bitWidth>16</bitWidth>
23174 </field>
23175 </fields>
23176 </register>
23177 <register>
23178 <name>CCR2</name>
23179 <displayName>CCR2</displayName>
23180 <description>capture/compare register 2</description>
23181 <addressOffset>0x38</addressOffset>
23182 <size>0x20</size>
23183 <access>read-write</access>
23184 <resetValue>0x00000000</resetValue>
23185 <fields>
23186 <field>
23187 <name>CCR2_H</name>
23188 <description>High Capture/Compare 2
23189 value</description>
23190 <bitOffset>16</bitOffset>
23191 <bitWidth>16</bitWidth>
23192 </field>
23193 <field>
23194 <name>CCR2_L</name>
23195 <description>Low Capture/Compare 2
23196 value</description>
23197 <bitOffset>0</bitOffset>
23198 <bitWidth>16</bitWidth>
23199 </field>
23200 </fields>
23201 </register>
23202 <register>
23203 <name>CCR3</name>
23204 <displayName>CCR3</displayName>
23205 <description>capture/compare register 3</description>
23206 <addressOffset>0x3C</addressOffset>
23207 <size>0x20</size>
23208 <access>read-write</access>
23209 <resetValue>0x00000000</resetValue>
23210 <fields>
23211 <field>
23212 <name>CCR3_H</name>
23213 <description>High Capture/Compare value</description>
23214 <bitOffset>16</bitOffset>
23215 <bitWidth>16</bitWidth>
23216 </field>
23217 <field>
23218 <name>CCR3_L</name>
23219 <description>Low Capture/Compare value</description>
23220 <bitOffset>0</bitOffset>
23221 <bitWidth>16</bitWidth>
23222 </field>
23223 </fields>
23224 </register>
23225 <register>
23226 <name>CCR4</name>
23227 <displayName>CCR4</displayName>
23228 <description>capture/compare register 4</description>
23229 <addressOffset>0x40</addressOffset>
23230 <size>0x20</size>
23231 <access>read-write</access>
23232 <resetValue>0x00000000</resetValue>
23233 <fields>
23234 <field>
23235 <name>CCR4_H</name>
23236 <description>High Capture/Compare value</description>
23237 <bitOffset>16</bitOffset>
23238 <bitWidth>16</bitWidth>
23239 </field>
23240 <field>
23241 <name>CCR4_L</name>
23242 <description>Low Capture/Compare value</description>
23243 <bitOffset>0</bitOffset>
23244 <bitWidth>16</bitWidth>
23245 </field>
23246 </fields>
23247 </register>
23248 <register>
23249 <name>DCR</name>
23250 <displayName>DCR</displayName>
23251 <description>DMA control register</description>
23252 <addressOffset>0x48</addressOffset>
23253 <size>0x20</size>
23254 <access>read-write</access>
23255 <resetValue>0x0000</resetValue>
23256 <fields>
23257 <field>
23258 <name>DBL</name>
23259 <description>DMA burst length</description>
23260 <bitOffset>8</bitOffset>
23261 <bitWidth>5</bitWidth>
23262 </field>
23263 <field>
23264 <name>DBA</name>
23265 <description>DMA base address</description>
23266 <bitOffset>0</bitOffset>
23267 <bitWidth>5</bitWidth>
23268 </field>
23269 </fields>
23270 </register>
23271 <register>
23272 <name>DMAR</name>
23273 <displayName>DMAR</displayName>
23274 <description>DMA address for full transfer</description>
23275 <addressOffset>0x4C</addressOffset>
23276 <size>0x20</size>
23277 <access>read-write</access>
23278 <resetValue>0x0000</resetValue>
23279 <fields>
23280 <field>
23281 <name>DMAB</name>
23282 <description>DMA register for burst
23283 accesses</description>
23284 <bitOffset>0</bitOffset>
23285 <bitWidth>16</bitWidth>
23286 </field>
23287 </fields>
23288 </register>
23289 </registers>
23290 </peripheral>
23291 <peripheral derivedFrom="TIM4">
23292 <name>TIM5</name>
23293 <baseAddress>0x40000C00</baseAddress>
23294 <interrupt>
23295 <name>TIM5</name>
23296 <description>TIM5 global interrupt</description>
23297 <value>50</value>
23298 </interrupt>
23299 </peripheral>
23300 <peripheral>
23301 <name>TIM9</name>
23302 <description>General purpose timers</description>
23303 <groupName>TIM</groupName>
23304 <baseAddress>0x40014000</baseAddress>
23305 <addressBlock>
23306 <offset>0x0</offset>
23307 <size>0x400</size>
23308 <usage>registers</usage>
23309 </addressBlock>
23310 <registers>
23311 <register>
23312 <name>CR1</name>
23313 <displayName>CR1</displayName>
23314 <description>control register 1</description>
23315 <addressOffset>0x0</addressOffset>
23316 <size>0x20</size>
23317 <access>read-write</access>
23318 <resetValue>0x0000</resetValue>
23319 <fields>
23320 <field>
23321 <name>CKD</name>
23322 <description>Clock division</description>
23323 <bitOffset>8</bitOffset>
23324 <bitWidth>2</bitWidth>
23325 </field>
23326 <field>
23327 <name>ARPE</name>
23328 <description>Auto-reload preload enable</description>
23329 <bitOffset>7</bitOffset>
23330 <bitWidth>1</bitWidth>
23331 </field>
23332 <field>
23333 <name>OPM</name>
23334 <description>One-pulse mode</description>
23335 <bitOffset>3</bitOffset>
23336 <bitWidth>1</bitWidth>
23337 </field>
23338 <field>
23339 <name>URS</name>
23340 <description>Update request source</description>
23341 <bitOffset>2</bitOffset>
23342 <bitWidth>1</bitWidth>
23343 </field>
23344 <field>
23345 <name>UDIS</name>
23346 <description>Update disable</description>
23347 <bitOffset>1</bitOffset>
23348 <bitWidth>1</bitWidth>
23349 </field>
23350 <field>
23351 <name>CEN</name>
23352 <description>Counter enable</description>
23353 <bitOffset>0</bitOffset>
23354 <bitWidth>1</bitWidth>
23355 </field>
23356 </fields>
23357 </register>
23358 <register>
23359 <name>SMCR</name>
23360 <displayName>SMCR</displayName>
23361 <description>slave mode control register</description>
23362 <addressOffset>0x8</addressOffset>
23363 <size>0x20</size>
23364 <access>read-write</access>
23365 <resetValue>0x0000</resetValue>
23366 <fields>
23367 <field>
23368 <name>MSM</name>
23369 <description>Master/Slave mode</description>
23370 <bitOffset>7</bitOffset>
23371 <bitWidth>1</bitWidth>
23372 </field>
23373 <field>
23374 <name>TS</name>
23375 <description>Trigger selection</description>
23376 <bitOffset>4</bitOffset>
23377 <bitWidth>3</bitWidth>
23378 </field>
23379 <field>
23380 <name>SMS</name>
23381 <description>Slave mode selection</description>
23382 <bitOffset>0</bitOffset>
23383 <bitWidth>3</bitWidth>
23384 </field>
23385 </fields>
23386 </register>
23387 <register>
23388 <name>DIER</name>
23389 <displayName>DIER</displayName>
23390 <description>DMA/Interrupt enable register</description>
23391 <addressOffset>0xC</addressOffset>
23392 <size>0x20</size>
23393 <access>read-write</access>
23394 <resetValue>0x0000</resetValue>
23395 <fields>
23396 <field>
23397 <name>TIE</name>
23398 <description>Trigger interrupt enable</description>
23399 <bitOffset>6</bitOffset>
23400 <bitWidth>1</bitWidth>
23401 </field>
23402 <field>
23403 <name>CC2IE</name>
23404 <description>Capture/Compare 2 interrupt
23405 enable</description>
23406 <bitOffset>2</bitOffset>
23407 <bitWidth>1</bitWidth>
23408 </field>
23409 <field>
23410 <name>CC1IE</name>
23411 <description>Capture/Compare 1 interrupt
23412 enable</description>
23413 <bitOffset>1</bitOffset>
23414 <bitWidth>1</bitWidth>
23415 </field>
23416 <field>
23417 <name>UIE</name>
23418 <description>Update interrupt enable</description>
23419 <bitOffset>0</bitOffset>
23420 <bitWidth>1</bitWidth>
23421 </field>
23422 </fields>
23423 </register>
23424 <register>
23425 <name>SR</name>
23426 <displayName>SR</displayName>
23427 <description>status register</description>
23428 <addressOffset>0x10</addressOffset>
23429 <size>0x20</size>
23430 <access>read-write</access>
23431 <resetValue>0x0000</resetValue>
23432 <fields>
23433 <field>
23434 <name>CC2OF</name>
23435 <description>Capture/compare 2 overcapture
23436 flag</description>
23437 <bitOffset>10</bitOffset>
23438 <bitWidth>1</bitWidth>
23439 </field>
23440 <field>
23441 <name>CC1OF</name>
23442 <description>Capture/Compare 1 overcapture
23443 flag</description>
23444 <bitOffset>9</bitOffset>
23445 <bitWidth>1</bitWidth>
23446 </field>
23447 <field>
23448 <name>TIF</name>
23449 <description>Trigger interrupt flag</description>
23450 <bitOffset>6</bitOffset>
23451 <bitWidth>1</bitWidth>
23452 </field>
23453 <field>
23454 <name>CC2IF</name>
23455 <description>Capture/Compare 2 interrupt
23456 flag</description>
23457 <bitOffset>2</bitOffset>
23458 <bitWidth>1</bitWidth>
23459 </field>
23460 <field>
23461 <name>CC1IF</name>
23462 <description>Capture/compare 1 interrupt
23463 flag</description>
23464 <bitOffset>1</bitOffset>
23465 <bitWidth>1</bitWidth>
23466 </field>
23467 <field>
23468 <name>UIF</name>
23469 <description>Update interrupt flag</description>
23470 <bitOffset>0</bitOffset>
23471 <bitWidth>1</bitWidth>
23472 </field>
23473 </fields>
23474 </register>
23475 <register>
23476 <name>EGR</name>
23477 <displayName>EGR</displayName>
23478 <description>event generation register</description>
23479 <addressOffset>0x14</addressOffset>
23480 <size>0x20</size>
23481 <access>write-only</access>
23482 <resetValue>0x0000</resetValue>
23483 <fields>
23484 <field>
23485 <name>TG</name>
23486 <description>Trigger generation</description>
23487 <bitOffset>6</bitOffset>
23488 <bitWidth>1</bitWidth>
23489 </field>
23490 <field>
23491 <name>CC2G</name>
23492 <description>Capture/compare 2
23493 generation</description>
23494 <bitOffset>2</bitOffset>
23495 <bitWidth>1</bitWidth>
23496 </field>
23497 <field>
23498 <name>CC1G</name>
23499 <description>Capture/compare 1
23500 generation</description>
23501 <bitOffset>1</bitOffset>
23502 <bitWidth>1</bitWidth>
23503 </field>
23504 <field>
23505 <name>UG</name>
23506 <description>Update generation</description>
23507 <bitOffset>0</bitOffset>
23508 <bitWidth>1</bitWidth>
23509 </field>
23510 </fields>
23511 </register>
23512 <register>
23513 <name>CCMR1_Output</name>
23514 <displayName>CCMR1_Output</displayName>
23515 <description>capture/compare mode register 1 (output
23516 mode)</description>
23517 <addressOffset>0x18</addressOffset>
23518 <size>0x20</size>
23519 <access>read-write</access>
23520 <resetValue>0x00000000</resetValue>
23521 <fields>
23522 <field>
23523 <name>OC2M</name>
23524 <description>Output Compare 2 mode</description>
23525 <bitOffset>12</bitOffset>
23526 <bitWidth>3</bitWidth>
23527 </field>
23528 <field>
23529 <name>OC2PE</name>
23530 <description>Output Compare 2 preload
23531 enable</description>
23532 <bitOffset>11</bitOffset>
23533 <bitWidth>1</bitWidth>
23534 </field>
23535 <field>
23536 <name>OC2FE</name>
23537 <description>Output Compare 2 fast
23538 enable</description>
23539 <bitOffset>10</bitOffset>
23540 <bitWidth>1</bitWidth>
23541 </field>
23542 <field>
23543 <name>CC2S</name>
23544 <description>Capture/Compare 2
23545 selection</description>
23546 <bitOffset>8</bitOffset>
23547 <bitWidth>2</bitWidth>
23548 </field>
23549 <field>
23550 <name>OC1M</name>
23551 <description>Output Compare 1 mode</description>
23552 <bitOffset>4</bitOffset>
23553 <bitWidth>3</bitWidth>
23554 </field>
23555 <field>
23556 <name>OC1PE</name>
23557 <description>Output Compare 1 preload
23558 enable</description>
23559 <bitOffset>3</bitOffset>
23560 <bitWidth>1</bitWidth>
23561 </field>
23562 <field>
23563 <name>OC1FE</name>
23564 <description>Output Compare 1 fast
23565 enable</description>
23566 <bitOffset>2</bitOffset>
23567 <bitWidth>1</bitWidth>
23568 </field>
23569 <field>
23570 <name>CC1S</name>
23571 <description>Capture/Compare 1
23572 selection</description>
23573 <bitOffset>0</bitOffset>
23574 <bitWidth>2</bitWidth>
23575 </field>
23576 </fields>
23577 </register>
23578 <register>
23579 <name>CCMR1_Input</name>
23580 <displayName>CCMR1_Input</displayName>
23581 <description>capture/compare mode register 1 (input
23582 mode)</description>
23583 <alternateRegister>CCMR1_Output</alternateRegister>
23584 <addressOffset>0x18</addressOffset>
23585 <size>0x20</size>
23586 <access>read-write</access>
23587 <resetValue>0x00000000</resetValue>
23588 <fields>
23589 <field>
23590 <name>IC2F</name>
23591 <description>Input capture 2 filter</description>
23592 <bitOffset>12</bitOffset>
23593 <bitWidth>3</bitWidth>
23594 </field>
23595 <field>
23596 <name>IC2PCS</name>
23597 <description>Input capture 2 prescaler</description>
23598 <bitOffset>10</bitOffset>
23599 <bitWidth>2</bitWidth>
23600 </field>
23601 <field>
23602 <name>CC2S</name>
23603 <description>Capture/Compare 2
23604 selection</description>
23605 <bitOffset>8</bitOffset>
23606 <bitWidth>2</bitWidth>
23607 </field>
23608 <field>
23609 <name>IC1F</name>
23610 <description>Input capture 1 filter</description>
23611 <bitOffset>4</bitOffset>
23612 <bitWidth>3</bitWidth>
23613 </field>
23614 <field>
23615 <name>ICPCS</name>
23616 <description>Input capture 1 prescaler</description>
23617 <bitOffset>2</bitOffset>
23618 <bitWidth>2</bitWidth>
23619 </field>
23620 <field>
23621 <name>CC1S</name>
23622 <description>Capture/Compare 1
23623 selection</description>
23624 <bitOffset>0</bitOffset>
23625 <bitWidth>2</bitWidth>
23626 </field>
23627 </fields>
23628 </register>
23629 <register>
23630 <name>CCER</name>
23631 <displayName>CCER</displayName>
23632 <description>capture/compare enable
23633 register</description>
23634 <addressOffset>0x20</addressOffset>
23635 <size>0x20</size>
23636 <access>read-write</access>
23637 <resetValue>0x0000</resetValue>
23638 <fields>
23639 <field>
23640 <name>CC2NP</name>
23641 <description>Capture/Compare 2 output
23642 Polarity</description>
23643 <bitOffset>7</bitOffset>
23644 <bitWidth>1</bitWidth>
23645 </field>
23646 <field>
23647 <name>CC2P</name>
23648 <description>Capture/Compare 2 output
23649 Polarity</description>
23650 <bitOffset>5</bitOffset>
23651 <bitWidth>1</bitWidth>
23652 </field>
23653 <field>
23654 <name>CC2E</name>
23655 <description>Capture/Compare 2 output
23656 enable</description>
23657 <bitOffset>4</bitOffset>
23658 <bitWidth>1</bitWidth>
23659 </field>
23660 <field>
23661 <name>CC1NP</name>
23662 <description>Capture/Compare 1 output
23663 Polarity</description>
23664 <bitOffset>3</bitOffset>
23665 <bitWidth>1</bitWidth>
23666 </field>
23667 <field>
23668 <name>CC1P</name>
23669 <description>Capture/Compare 1 output
23670 Polarity</description>
23671 <bitOffset>1</bitOffset>
23672 <bitWidth>1</bitWidth>
23673 </field>
23674 <field>
23675 <name>CC1E</name>
23676 <description>Capture/Compare 1 output
23677 enable</description>
23678 <bitOffset>0</bitOffset>
23679 <bitWidth>1</bitWidth>
23680 </field>
23681 </fields>
23682 </register>
23683 <register>
23684 <name>CNT</name>
23685 <displayName>CNT</displayName>
23686 <description>counter</description>
23687 <addressOffset>0x24</addressOffset>
23688 <size>0x20</size>
23689 <access>read-write</access>
23690 <resetValue>0x00000000</resetValue>
23691 <fields>
23692 <field>
23693 <name>CNT</name>
23694 <description>counter value</description>
23695 <bitOffset>0</bitOffset>
23696 <bitWidth>16</bitWidth>
23697 </field>
23698 </fields>
23699 </register>
23700 <register>
23701 <name>PSC</name>
23702 <displayName>PSC</displayName>
23703 <description>prescaler</description>
23704 <addressOffset>0x28</addressOffset>
23705 <size>0x20</size>
23706 <access>read-write</access>
23707 <resetValue>0x0000</resetValue>
23708 <fields>
23709 <field>
23710 <name>PSC</name>
23711 <description>Prescaler value</description>
23712 <bitOffset>0</bitOffset>
23713 <bitWidth>16</bitWidth>
23714 </field>
23715 </fields>
23716 </register>
23717 <register>
23718 <name>ARR</name>
23719 <displayName>ARR</displayName>
23720 <description>auto-reload register</description>
23721 <addressOffset>0x2C</addressOffset>
23722 <size>0x20</size>
23723 <access>read-write</access>
23724 <resetValue>0x00000000</resetValue>
23725 <fields>
23726 <field>
23727 <name>ARR</name>
23728 <description>Auto-reload value</description>
23729 <bitOffset>0</bitOffset>
23730 <bitWidth>16</bitWidth>
23731 </field>
23732 </fields>
23733 </register>
23734 <register>
23735 <name>CCR1</name>
23736 <displayName>CCR1</displayName>
23737 <description>capture/compare register 1</description>
23738 <addressOffset>0x34</addressOffset>
23739 <size>0x20</size>
23740 <access>read-write</access>
23741 <resetValue>0x00000000</resetValue>
23742 <fields>
23743 <field>
23744 <name>CCR1</name>
23745 <description>Capture/Compare 1 value</description>
23746 <bitOffset>0</bitOffset>
23747 <bitWidth>16</bitWidth>
23748 </field>
23749 </fields>
23750 </register>
23751 <register>
23752 <name>CCR2</name>
23753 <displayName>CCR2</displayName>
23754 <description>capture/compare register 2</description>
23755 <addressOffset>0x38</addressOffset>
23756 <size>0x20</size>
23757 <access>read-write</access>
23758 <resetValue>0x00000000</resetValue>
23759 <fields>
23760 <field>
23761 <name>CCR2</name>
23762 <description>Capture/Compare 2 value</description>
23763 <bitOffset>0</bitOffset>
23764 <bitWidth>16</bitWidth>
23765 </field>
23766 </fields>
23767 </register>
23768 </registers>
23769 </peripheral>
23770 <peripheral derivedFrom="TIM9">
23771 <name>TIM12</name>
23772 <baseAddress>0x40001800</baseAddress>
23773 </peripheral>
23774 <peripheral>
23775 <name>TIM10</name>
23776 <description>General-purpose-timers</description>
23777 <groupName>TIM</groupName>
23778 <baseAddress>0x40014400</baseAddress>
23779 <addressBlock>
23780 <offset>0x0</offset>
23781 <size>0x400</size>
23782 <usage>registers</usage>
23783 </addressBlock>
23784 <registers>
23785 <register>
23786 <name>CR1</name>
23787 <displayName>CR1</displayName>
23788 <description>control register 1</description>
23789 <addressOffset>0x0</addressOffset>
23790 <size>0x20</size>
23791 <access>read-write</access>
23792 <resetValue>0x0000</resetValue>
23793 <fields>
23794 <field>
23795 <name>CKD</name>
23796 <description>Clock division</description>
23797 <bitOffset>8</bitOffset>
23798 <bitWidth>2</bitWidth>
23799 </field>
23800 <field>
23801 <name>ARPE</name>
23802 <description>Auto-reload preload enable</description>
23803 <bitOffset>7</bitOffset>
23804 <bitWidth>1</bitWidth>
23805 </field>
23806 <field>
23807 <name>URS</name>
23808 <description>Update request source</description>
23809 <bitOffset>2</bitOffset>
23810 <bitWidth>1</bitWidth>
23811 </field>
23812 <field>
23813 <name>UDIS</name>
23814 <description>Update disable</description>
23815 <bitOffset>1</bitOffset>
23816 <bitWidth>1</bitWidth>
23817 </field>
23818 <field>
23819 <name>CEN</name>
23820 <description>Counter enable</description>
23821 <bitOffset>0</bitOffset>
23822 <bitWidth>1</bitWidth>
23823 </field>
23824 </fields>
23825 </register>
23826 <register>
23827 <name>DIER</name>
23828 <displayName>DIER</displayName>
23829 <description>DMA/Interrupt enable register</description>
23830 <addressOffset>0xC</addressOffset>
23831 <size>0x20</size>
23832 <access>read-write</access>
23833 <resetValue>0x0000</resetValue>
23834 <fields>
23835 <field>
23836 <name>CC1IE</name>
23837 <description>Capture/Compare 1 interrupt
23838 enable</description>
23839 <bitOffset>1</bitOffset>
23840 <bitWidth>1</bitWidth>
23841 </field>
23842 <field>
23843 <name>UIE</name>
23844 <description>Update interrupt enable</description>
23845 <bitOffset>0</bitOffset>
23846 <bitWidth>1</bitWidth>
23847 </field>
23848 </fields>
23849 </register>
23850 <register>
23851 <name>SR</name>
23852 <displayName>SR</displayName>
23853 <description>status register</description>
23854 <addressOffset>0x10</addressOffset>
23855 <size>0x20</size>
23856 <access>read-write</access>
23857 <resetValue>0x0000</resetValue>
23858 <fields>
23859 <field>
23860 <name>CC1OF</name>
23861 <description>Capture/Compare 1 overcapture
23862 flag</description>
23863 <bitOffset>9</bitOffset>
23864 <bitWidth>1</bitWidth>
23865 </field>
23866 <field>
23867 <name>CC1IF</name>
23868 <description>Capture/compare 1 interrupt
23869 flag</description>
23870 <bitOffset>1</bitOffset>
23871 <bitWidth>1</bitWidth>
23872 </field>
23873 <field>
23874 <name>UIF</name>
23875 <description>Update interrupt flag</description>
23876 <bitOffset>0</bitOffset>
23877 <bitWidth>1</bitWidth>
23878 </field>
23879 </fields>
23880 </register>
23881 <register>
23882 <name>EGR</name>
23883 <displayName>EGR</displayName>
23884 <description>event generation register</description>
23885 <addressOffset>0x14</addressOffset>
23886 <size>0x20</size>
23887 <access>write-only</access>
23888 <resetValue>0x0000</resetValue>
23889 <fields>
23890 <field>
23891 <name>CC1G</name>
23892 <description>Capture/compare 1
23893 generation</description>
23894 <bitOffset>1</bitOffset>
23895 <bitWidth>1</bitWidth>
23896 </field>
23897 <field>
23898 <name>UG</name>
23899 <description>Update generation</description>
23900 <bitOffset>0</bitOffset>
23901 <bitWidth>1</bitWidth>
23902 </field>
23903 </fields>
23904 </register>
23905 <register>
23906 <name>CCMR1_Output</name>
23907 <displayName>CCMR1_Output</displayName>
23908 <description>capture/compare mode register 1 (output
23909 mode)</description>
23910 <addressOffset>0x18</addressOffset>
23911 <size>0x20</size>
23912 <access>read-write</access>
23913 <resetValue>0x00000000</resetValue>
23914 <fields>
23915 <field>
23916 <name>OC1M</name>
23917 <description>Output Compare 1 mode</description>
23918 <bitOffset>4</bitOffset>
23919 <bitWidth>3</bitWidth>
23920 </field>
23921 <field>
23922 <name>OC1PE</name>
23923 <description>Output Compare 1 preload
23924 enable</description>
23925 <bitOffset>3</bitOffset>
23926 <bitWidth>1</bitWidth>
23927 </field>
23928 <field>
23929 <name>OC1FE</name>
23930 <description>Output Compare 1 fast
23931 enable</description>
23932 <bitOffset>2</bitOffset>
23933 <bitWidth>1</bitWidth>
23934 </field>
23935 <field>
23936 <name>CC1S</name>
23937 <description>Capture/Compare 1
23938 selection</description>
23939 <bitOffset>0</bitOffset>
23940 <bitWidth>2</bitWidth>
23941 </field>
23942 </fields>
23943 </register>
23944 <register>
23945 <name>CCMR1_Input</name>
23946 <displayName>CCMR1_Input</displayName>
23947 <description>capture/compare mode register 1 (input
23948 mode)</description>
23949 <alternateRegister>CCMR1_Output</alternateRegister>
23950 <addressOffset>0x18</addressOffset>
23951 <size>0x20</size>
23952 <access>read-write</access>
23953 <resetValue>0x00000000</resetValue>
23954 <fields>
23955 <field>
23956 <name>IC1F</name>
23957 <description>Input capture 1 filter</description>
23958 <bitOffset>4</bitOffset>
23959 <bitWidth>4</bitWidth>
23960 </field>
23961 <field>
23962 <name>ICPCS</name>
23963 <description>Input capture 1 prescaler</description>
23964 <bitOffset>2</bitOffset>
23965 <bitWidth>2</bitWidth>
23966 </field>
23967 <field>
23968 <name>CC1S</name>
23969 <description>Capture/Compare 1
23970 selection</description>
23971 <bitOffset>0</bitOffset>
23972 <bitWidth>2</bitWidth>
23973 </field>
23974 </fields>
23975 </register>
23976 <register>
23977 <name>CCER</name>
23978 <displayName>CCER</displayName>
23979 <description>capture/compare enable
23980 register</description>
23981 <addressOffset>0x20</addressOffset>
23982 <size>0x20</size>
23983 <access>read-write</access>
23984 <resetValue>0x0000</resetValue>
23985 <fields>
23986 <field>
23987 <name>CC1NP</name>
23988 <description>Capture/Compare 1 output
23989 Polarity</description>
23990 <bitOffset>3</bitOffset>
23991 <bitWidth>1</bitWidth>
23992 </field>
23993 <field>
23994 <name>CC1P</name>
23995 <description>Capture/Compare 1 output
23996 Polarity</description>
23997 <bitOffset>1</bitOffset>
23998 <bitWidth>1</bitWidth>
23999 </field>
24000 <field>
24001 <name>CC1E</name>
24002 <description>Capture/Compare 1 output
24003 enable</description>
24004 <bitOffset>0</bitOffset>
24005 <bitWidth>1</bitWidth>
24006 </field>
24007 </fields>
24008 </register>
24009 <register>
24010 <name>CNT</name>
24011 <displayName>CNT</displayName>
24012 <description>counter</description>
24013 <addressOffset>0x24</addressOffset>
24014 <size>0x20</size>
24015 <access>read-write</access>
24016 <resetValue>0x00000000</resetValue>
24017 <fields>
24018 <field>
24019 <name>CNT</name>
24020 <description>counter value</description>
24021 <bitOffset>0</bitOffset>
24022 <bitWidth>16</bitWidth>
24023 </field>
24024 </fields>
24025 </register>
24026 <register>
24027 <name>PSC</name>
24028 <displayName>PSC</displayName>
24029 <description>prescaler</description>
24030 <addressOffset>0x28</addressOffset>
24031 <size>0x20</size>
24032 <access>read-write</access>
24033 <resetValue>0x0000</resetValue>
24034 <fields>
24035 <field>
24036 <name>PSC</name>
24037 <description>Prescaler value</description>
24038 <bitOffset>0</bitOffset>
24039 <bitWidth>16</bitWidth>
24040 </field>
24041 </fields>
24042 </register>
24043 <register>
24044 <name>ARR</name>
24045 <displayName>ARR</displayName>
24046 <description>auto-reload register</description>
24047 <addressOffset>0x2C</addressOffset>
24048 <size>0x20</size>
24049 <access>read-write</access>
24050 <resetValue>0x00000000</resetValue>
24051 <fields>
24052 <field>
24053 <name>ARR</name>
24054 <description>Auto-reload value</description>
24055 <bitOffset>0</bitOffset>
24056 <bitWidth>16</bitWidth>
24057 </field>
24058 </fields>
24059 </register>
24060 <register>
24061 <name>CCR1</name>
24062 <displayName>CCR1</displayName>
24063 <description>capture/compare register 1</description>
24064 <addressOffset>0x34</addressOffset>
24065 <size>0x20</size>
24066 <access>read-write</access>
24067 <resetValue>0x00000000</resetValue>
24068 <fields>
24069 <field>
24070 <name>CCR1</name>
24071 <description>Capture/Compare 1 value</description>
24072 <bitOffset>0</bitOffset>
24073 <bitWidth>16</bitWidth>
24074 </field>
24075 </fields>
24076 </register>
24077 <register>
24078 <name>SMCR</name>
24079 <displayName>SMCR</displayName>
24080 <description>slave mode control register</description>
24081 <addressOffset>0x8</addressOffset>
24082 <size>0x20</size>
24083 <access>read-write</access>
24084 <resetValue>0x00000000</resetValue>
24085 <fields>
24086 <field>
24087 <name>SMS3</name>
24088 <description>Slave mode selection</description>
24089 <bitOffset>16</bitOffset>
24090 <bitWidth>1</bitWidth>
24091 </field>
24092 <field>
24093 <name>ETP</name>
24094 <description>External trigger polarity</description>
24095 <bitOffset>15</bitOffset>
24096 <bitWidth>1</bitWidth>
24097 </field>
24098 <field>
24099 <name>ECE</name>
24100 <description>External clock enable</description>
24101 <bitOffset>14</bitOffset>
24102 <bitWidth>1</bitWidth>
24103 </field>
24104 <field>
24105 <name>ETPS</name>
24106 <description>External trigger prescaler</description>
24107 <bitOffset>12</bitOffset>
24108 <bitWidth>2</bitWidth>
24109 </field>
24110 <field>
24111 <name>ETF</name>
24112 <description>External trigger filter</description>
24113 <bitOffset>8</bitOffset>
24114 <bitWidth>4</bitWidth>
24115 </field>
24116 <field>
24117 <name>MSM</name>
24118 <description>Master/slave mode</description>
24119 <bitOffset>7</bitOffset>
24120 <bitWidth>1</bitWidth>
24121 </field>
24122 <field>
24123 <name>TS</name>
24124 <description>Trigger selection</description>
24125 <bitOffset>4</bitOffset>
24126 <bitWidth>3</bitWidth>
24127 </field>
24128 <field>
24129 <name>SMS</name>
24130 <description>Slave mode selection</description>
24131 <bitOffset>0</bitOffset>
24132 <bitWidth>3</bitWidth>
24133 </field>
24134 </fields>
24135 </register>
24136 <register>
24137 <name>OR</name>
24138 <displayName>OR</displayName>
24139 <description>option register</description>
24140 <addressOffset>0x50</addressOffset>
24141 <size>0x20</size>
24142 <access>read-write</access>
24143 <resetValue>0x00000000</resetValue>
24144 <fields>
24145 <field>
24146 <name>TI1_RMP</name>
24147 <description>TIM11 Input 1 remapping
24148 capability</description>
24149 <bitOffset>0</bitOffset>
24150 <bitWidth>2</bitWidth>
24151 </field>
24152 </fields>
24153 </register>
24154 </registers>
24155 </peripheral>
24156 <peripheral derivedFrom="TIM10">
24157 <name>TIM11</name>
24158 <baseAddress>0x40014800</baseAddress>
24159 </peripheral>
24160 <peripheral derivedFrom="TIM10">
24161 <name>TIM13</name>
24162 <baseAddress>0x40001C00</baseAddress>
24163 </peripheral>
24164 <peripheral derivedFrom="TIM10">
24165 <name>TIM14</name>
24166 <baseAddress>0x40002000</baseAddress>
24167 </peripheral>
24168 <peripheral>
24169 <name>TIM6</name>
24170 <description>Basic timers</description>
24171 <groupName>TIM</groupName>
24172 <baseAddress>0x40001000</baseAddress>
24173 <addressBlock>
24174 <offset>0x0</offset>
24175 <size>0x400</size>
24176 <usage>registers</usage>
24177 </addressBlock>
24178 <interrupt>
24179 <name>TIM6_DAC</name>
24180 <description>TIM6 global interrupt, DAC1 and DAC2 underrun
24181 error interrupt</description>
24182 <value>54</value>
24183 </interrupt>
24184 <registers>
24185 <register>
24186 <name>CR1</name>
24187 <displayName>CR1</displayName>
24188 <description>control register 1</description>
24189 <addressOffset>0x0</addressOffset>
24190 <size>0x20</size>
24191 <access>read-write</access>
24192 <resetValue>0x0000</resetValue>
24193 <fields>
24194 <field>
24195 <name>ARPE</name>
24196 <description>Auto-reload preload enable</description>
24197 <bitOffset>7</bitOffset>
24198 <bitWidth>1</bitWidth>
24199 </field>
24200 <field>
24201 <name>OPM</name>
24202 <description>One-pulse mode</description>
24203 <bitOffset>3</bitOffset>
24204 <bitWidth>1</bitWidth>
24205 </field>
24206 <field>
24207 <name>URS</name>
24208 <description>Update request source</description>
24209 <bitOffset>2</bitOffset>
24210 <bitWidth>1</bitWidth>
24211 </field>
24212 <field>
24213 <name>UDIS</name>
24214 <description>Update disable</description>
24215 <bitOffset>1</bitOffset>
24216 <bitWidth>1</bitWidth>
24217 </field>
24218 <field>
24219 <name>CEN</name>
24220 <description>Counter enable</description>
24221 <bitOffset>0</bitOffset>
24222 <bitWidth>1</bitWidth>
24223 </field>
24224 </fields>
24225 </register>
24226 <register>
24227 <name>CR2</name>
24228 <displayName>CR2</displayName>
24229 <description>control register 2</description>
24230 <addressOffset>0x4</addressOffset>
24231 <size>0x20</size>
24232 <access>read-write</access>
24233 <resetValue>0x0000</resetValue>
24234 <fields>
24235 <field>
24236 <name>MMS</name>
24237 <description>Master mode selection</description>
24238 <bitOffset>4</bitOffset>
24239 <bitWidth>3</bitWidth>
24240 </field>
24241 </fields>
24242 </register>
24243 <register>
24244 <name>DIER</name>
24245 <displayName>DIER</displayName>
24246 <description>DMA/Interrupt enable register</description>
24247 <addressOffset>0xC</addressOffset>
24248 <size>0x20</size>
24249 <access>read-write</access>
24250 <resetValue>0x0000</resetValue>
24251 <fields>
24252 <field>
24253 <name>UDE</name>
24254 <description>Update DMA request enable</description>
24255 <bitOffset>8</bitOffset>
24256 <bitWidth>1</bitWidth>
24257 </field>
24258 <field>
24259 <name>UIE</name>
24260 <description>Update interrupt enable</description>
24261 <bitOffset>0</bitOffset>
24262 <bitWidth>1</bitWidth>
24263 </field>
24264 </fields>
24265 </register>
24266 <register>
24267 <name>SR</name>
24268 <displayName>SR</displayName>
24269 <description>status register</description>
24270 <addressOffset>0x10</addressOffset>
24271 <size>0x20</size>
24272 <access>read-write</access>
24273 <resetValue>0x0000</resetValue>
24274 <fields>
24275 <field>
24276 <name>UIF</name>
24277 <description>Update interrupt flag</description>
24278 <bitOffset>0</bitOffset>
24279 <bitWidth>1</bitWidth>
24280 </field>
24281 </fields>
24282 </register>
24283 <register>
24284 <name>EGR</name>
24285 <displayName>EGR</displayName>
24286 <description>event generation register</description>
24287 <addressOffset>0x14</addressOffset>
24288 <size>0x20</size>
24289 <access>write-only</access>
24290 <resetValue>0x0000</resetValue>
24291 <fields>
24292 <field>
24293 <name>UG</name>
24294 <description>Update generation</description>
24295 <bitOffset>0</bitOffset>
24296 <bitWidth>1</bitWidth>
24297 </field>
24298 </fields>
24299 </register>
24300 <register>
24301 <name>CNT</name>
24302 <displayName>CNT</displayName>
24303 <description>counter</description>
24304 <addressOffset>0x24</addressOffset>
24305 <size>0x20</size>
24306 <access>read-write</access>
24307 <resetValue>0x00000000</resetValue>
24308 <fields>
24309 <field>
24310 <name>CNT</name>
24311 <description>Low counter value</description>
24312 <bitOffset>0</bitOffset>
24313 <bitWidth>16</bitWidth>
24314 </field>
24315 </fields>
24316 </register>
24317 <register>
24318 <name>PSC</name>
24319 <displayName>PSC</displayName>
24320 <description>prescaler</description>
24321 <addressOffset>0x28</addressOffset>
24322 <size>0x20</size>
24323 <access>read-write</access>
24324 <resetValue>0x0000</resetValue>
24325 <fields>
24326 <field>
24327 <name>PSC</name>
24328 <description>Prescaler value</description>
24329 <bitOffset>0</bitOffset>
24330 <bitWidth>16</bitWidth>
24331 </field>
24332 </fields>
24333 </register>
24334 <register>
24335 <name>ARR</name>
24336 <displayName>ARR</displayName>
24337 <description>auto-reload register</description>
24338 <addressOffset>0x2C</addressOffset>
24339 <size>0x20</size>
24340 <access>read-write</access>
24341 <resetValue>0x00000000</resetValue>
24342 <fields>
24343 <field>
24344 <name>ARR</name>
24345 <description>Low Auto-reload value</description>
24346 <bitOffset>0</bitOffset>
24347 <bitWidth>16</bitWidth>
24348 </field>
24349 </fields>
24350 </register>
24351 </registers>
24352 </peripheral>
24353 <peripheral derivedFrom="TIM6">
24354 <name>TIM7</name>
24355 <baseAddress>0x40001400</baseAddress>
24356 <interrupt>
24357 <name>TIM7</name>
24358 <description>TIM7 global interrupt</description>
24359 <value>55</value>
24360 </interrupt>
24361 </peripheral>
24362 <peripheral>
24363 <name>Ethernet_MAC</name>
24364 <description>Ethernet: media access control
24365 (MAC)</description>
24366 <groupName>Ethernet</groupName>
24367 <baseAddress>0x40028000</baseAddress>
24368 <addressBlock>
24369 <offset>0x0</offset>
24370 <size>0x100</size>
24371 <usage>registers</usage>
24372 </addressBlock>
24373 <registers>
24374 <register>
24375 <name>MACCR</name>
24376 <displayName>MACCR</displayName>
24377 <description>Ethernet MAC configuration
24378 register</description>
24379 <addressOffset>0x0</addressOffset>
24380 <size>0x20</size>
24381 <access>read-write</access>
24382 <resetValue>0x0008000</resetValue>
24383 <fields>
24384 <field>
24385 <name>RE</name>
24386 <description>RE</description>
24387 <bitOffset>2</bitOffset>
24388 <bitWidth>1</bitWidth>
24389 </field>
24390 <field>
24391 <name>TE</name>
24392 <description>TE</description>
24393 <bitOffset>3</bitOffset>
24394 <bitWidth>1</bitWidth>
24395 </field>
24396 <field>
24397 <name>DC</name>
24398 <description>DC</description>
24399 <bitOffset>4</bitOffset>
24400 <bitWidth>1</bitWidth>
24401 </field>
24402 <field>
24403 <name>BL</name>
24404 <description>BL</description>
24405 <bitOffset>5</bitOffset>
24406 <bitWidth>2</bitWidth>
24407 </field>
24408 <field>
24409 <name>APCS</name>
24410 <description>APCS</description>
24411 <bitOffset>7</bitOffset>
24412 <bitWidth>1</bitWidth>
24413 </field>
24414 <field>
24415 <name>RD</name>
24416 <description>RD</description>
24417 <bitOffset>9</bitOffset>
24418 <bitWidth>1</bitWidth>
24419 </field>
24420 <field>
24421 <name>IPCO</name>
24422 <description>IPCO</description>
24423 <bitOffset>10</bitOffset>
24424 <bitWidth>1</bitWidth>
24425 </field>
24426 <field>
24427 <name>DM</name>
24428 <description>DM</description>
24429 <bitOffset>11</bitOffset>
24430 <bitWidth>1</bitWidth>
24431 </field>
24432 <field>
24433 <name>LM</name>
24434 <description>LM</description>
24435 <bitOffset>12</bitOffset>
24436 <bitWidth>1</bitWidth>
24437 </field>
24438 <field>
24439 <name>ROD</name>
24440 <description>ROD</description>
24441 <bitOffset>13</bitOffset>
24442 <bitWidth>1</bitWidth>
24443 </field>
24444 <field>
24445 <name>FES</name>
24446 <description>FES</description>
24447 <bitOffset>14</bitOffset>
24448 <bitWidth>1</bitWidth>
24449 </field>
24450 <field>
24451 <name>CSD</name>
24452 <description>CSD</description>
24453 <bitOffset>16</bitOffset>
24454 <bitWidth>1</bitWidth>
24455 </field>
24456 <field>
24457 <name>IFG</name>
24458 <description>IFG</description>
24459 <bitOffset>17</bitOffset>
24460 <bitWidth>3</bitWidth>
24461 </field>
24462 <field>
24463 <name>JD</name>
24464 <description>JD</description>
24465 <bitOffset>22</bitOffset>
24466 <bitWidth>1</bitWidth>
24467 </field>
24468 <field>
24469 <name>WD</name>
24470 <description>WD</description>
24471 <bitOffset>23</bitOffset>
24472 <bitWidth>1</bitWidth>
24473 </field>
24474 <field>
24475 <name>CSTF</name>
24476 <description>CSTF</description>
24477 <bitOffset>25</bitOffset>
24478 <bitWidth>1</bitWidth>
24479 </field>
24480 </fields>
24481 </register>
24482 <register>
24483 <name>MACFFR</name>
24484 <displayName>MACFFR</displayName>
24485 <description>Ethernet MAC frame filter
24486 register</description>
24487 <addressOffset>0x4</addressOffset>
24488 <size>0x20</size>
24489 <access>read-write</access>
24490 <resetValue>0x00000000</resetValue>
24491 <fields>
24492 <field>
24493 <name>PM</name>
24494 <description>PM</description>
24495 <bitOffset>0</bitOffset>
24496 <bitWidth>1</bitWidth>
24497 </field>
24498 <field>
24499 <name>HU</name>
24500 <description>HU</description>
24501 <bitOffset>1</bitOffset>
24502 <bitWidth>1</bitWidth>
24503 </field>
24504 <field>
24505 <name>HM</name>
24506 <description>HM</description>
24507 <bitOffset>2</bitOffset>
24508 <bitWidth>1</bitWidth>
24509 </field>
24510 <field>
24511 <name>DAIF</name>
24512 <description>DAIF</description>
24513 <bitOffset>3</bitOffset>
24514 <bitWidth>1</bitWidth>
24515 </field>
24516 <field>
24517 <name>RAM</name>
24518 <description>RAM</description>
24519 <bitOffset>4</bitOffset>
24520 <bitWidth>1</bitWidth>
24521 </field>
24522 <field>
24523 <name>BFD</name>
24524 <description>BFD</description>
24525 <bitOffset>5</bitOffset>
24526 <bitWidth>1</bitWidth>
24527 </field>
24528 <field>
24529 <name>PCF</name>
24530 <description>PCF</description>
24531 <bitOffset>6</bitOffset>
24532 <bitWidth>1</bitWidth>
24533 </field>
24534 <field>
24535 <name>SAIF</name>
24536 <description>SAIF</description>
24537 <bitOffset>7</bitOffset>
24538 <bitWidth>1</bitWidth>
24539 </field>
24540 <field>
24541 <name>SAF</name>
24542 <description>SAF</description>
24543 <bitOffset>8</bitOffset>
24544 <bitWidth>1</bitWidth>
24545 </field>
24546 <field>
24547 <name>HPF</name>
24548 <description>HPF</description>
24549 <bitOffset>9</bitOffset>
24550 <bitWidth>1</bitWidth>
24551 </field>
24552 <field>
24553 <name>RA</name>
24554 <description>RA</description>
24555 <bitOffset>31</bitOffset>
24556 <bitWidth>1</bitWidth>
24557 </field>
24558 </fields>
24559 </register>
24560 <register>
24561 <name>MACHTHR</name>
24562 <displayName>MACHTHR</displayName>
24563 <description>Ethernet MAC hash table high
24564 register</description>
24565 <addressOffset>0x8</addressOffset>
24566 <size>0x20</size>
24567 <access>read-write</access>
24568 <resetValue>0x00000000</resetValue>
24569 <fields>
24570 <field>
24571 <name>HTH</name>
24572 <description>HTH</description>
24573 <bitOffset>0</bitOffset>
24574 <bitWidth>32</bitWidth>
24575 </field>
24576 </fields>
24577 </register>
24578 <register>
24579 <name>MACHTLR</name>
24580 <displayName>MACHTLR</displayName>
24581 <description>Ethernet MAC hash table low
24582 register</description>
24583 <addressOffset>0xC</addressOffset>
24584 <size>0x20</size>
24585 <access>read-write</access>
24586 <resetValue>0x00000000</resetValue>
24587 <fields>
24588 <field>
24589 <name>HTL</name>
24590 <description>HTL</description>
24591 <bitOffset>0</bitOffset>
24592 <bitWidth>32</bitWidth>
24593 </field>
24594 </fields>
24595 </register>
24596 <register>
24597 <name>MACMIIAR</name>
24598 <displayName>MACMIIAR</displayName>
24599 <description>Ethernet MAC MII address
24600 register</description>
24601 <addressOffset>0x10</addressOffset>
24602 <size>0x20</size>
24603 <access>read-write</access>
24604 <resetValue>0x00000000</resetValue>
24605 <fields>
24606 <field>
24607 <name>MB</name>
24608 <description>MB</description>
24609 <bitOffset>0</bitOffset>
24610 <bitWidth>1</bitWidth>
24611 </field>
24612 <field>
24613 <name>MW</name>
24614 <description>MW</description>
24615 <bitOffset>1</bitOffset>
24616 <bitWidth>1</bitWidth>
24617 </field>
24618 <field>
24619 <name>CR</name>
24620 <description>CR</description>
24621 <bitOffset>2</bitOffset>
24622 <bitWidth>3</bitWidth>
24623 </field>
24624 <field>
24625 <name>MR</name>
24626 <description>MR</description>
24627 <bitOffset>6</bitOffset>
24628 <bitWidth>5</bitWidth>
24629 </field>
24630 <field>
24631 <name>PA</name>
24632 <description>PA</description>
24633 <bitOffset>11</bitOffset>
24634 <bitWidth>5</bitWidth>
24635 </field>
24636 </fields>
24637 </register>
24638 <register>
24639 <name>MACMIIDR</name>
24640 <displayName>MACMIIDR</displayName>
24641 <description>Ethernet MAC MII data register</description>
24642 <addressOffset>0x14</addressOffset>
24643 <size>0x20</size>
24644 <access>read-write</access>
24645 <resetValue>0x00000000</resetValue>
24646 <fields>
24647 <field>
24648 <name>TD</name>
24649 <description>TD</description>
24650 <bitOffset>0</bitOffset>
24651 <bitWidth>16</bitWidth>
24652 </field>
24653 </fields>
24654 </register>
24655 <register>
24656 <name>MACFCR</name>
24657 <displayName>MACFCR</displayName>
24658 <description>Ethernet MAC flow control
24659 register</description>
24660 <addressOffset>0x18</addressOffset>
24661 <size>0x20</size>
24662 <access>read-write</access>
24663 <resetValue>0x00000000</resetValue>
24664 <fields>
24665 <field>
24666 <name>FCB</name>
24667 <description>FCB</description>
24668 <bitOffset>0</bitOffset>
24669 <bitWidth>1</bitWidth>
24670 </field>
24671 <field>
24672 <name>TFCE</name>
24673 <description>TFCE</description>
24674 <bitOffset>1</bitOffset>
24675 <bitWidth>1</bitWidth>
24676 </field>
24677 <field>
24678 <name>RFCE</name>
24679 <description>RFCE</description>
24680 <bitOffset>2</bitOffset>
24681 <bitWidth>1</bitWidth>
24682 </field>
24683 <field>
24684 <name>UPFD</name>
24685 <description>UPFD</description>
24686 <bitOffset>3</bitOffset>
24687 <bitWidth>1</bitWidth>
24688 </field>
24689 <field>
24690 <name>PLT</name>
24691 <description>PLT</description>
24692 <bitOffset>4</bitOffset>
24693 <bitWidth>2</bitWidth>
24694 </field>
24695 <field>
24696 <name>ZQPD</name>
24697 <description>ZQPD</description>
24698 <bitOffset>7</bitOffset>
24699 <bitWidth>1</bitWidth>
24700 </field>
24701 <field>
24702 <name>PT</name>
24703 <description>PT</description>
24704 <bitOffset>16</bitOffset>
24705 <bitWidth>16</bitWidth>
24706 </field>
24707 </fields>
24708 </register>
24709 <register>
24710 <name>MACVLANTR</name>
24711 <displayName>MACVLANTR</displayName>
24712 <description>Ethernet MAC VLAN tag register</description>
24713 <addressOffset>0x1C</addressOffset>
24714 <size>0x20</size>
24715 <access>read-write</access>
24716 <resetValue>0x00000000</resetValue>
24717 <fields>
24718 <field>
24719 <name>VLANTI</name>
24720 <description>VLANTI</description>
24721 <bitOffset>0</bitOffset>
24722 <bitWidth>16</bitWidth>
24723 </field>
24724 <field>
24725 <name>VLANTC</name>
24726 <description>VLANTC</description>
24727 <bitOffset>16</bitOffset>
24728 <bitWidth>1</bitWidth>
24729 </field>
24730 </fields>
24731 </register>
24732 <register>
24733 <name>MACPMTCSR</name>
24734 <displayName>MACPMTCSR</displayName>
24735 <description>Ethernet MAC PMT control and status
24736 register</description>
24737 <addressOffset>0x2C</addressOffset>
24738 <size>0x20</size>
24739 <access>read-write</access>
24740 <resetValue>0x00000000</resetValue>
24741 <fields>
24742 <field>
24743 <name>PD</name>
24744 <description>PD</description>
24745 <bitOffset>0</bitOffset>
24746 <bitWidth>1</bitWidth>
24747 </field>
24748 <field>
24749 <name>MPE</name>
24750 <description>MPE</description>
24751 <bitOffset>1</bitOffset>
24752 <bitWidth>1</bitWidth>
24753 </field>
24754 <field>
24755 <name>WFE</name>
24756 <description>WFE</description>
24757 <bitOffset>2</bitOffset>
24758 <bitWidth>1</bitWidth>
24759 </field>
24760 <field>
24761 <name>MPR</name>
24762 <description>MPR</description>
24763 <bitOffset>5</bitOffset>
24764 <bitWidth>1</bitWidth>
24765 </field>
24766 <field>
24767 <name>WFR</name>
24768 <description>WFR</description>
24769 <bitOffset>6</bitOffset>
24770 <bitWidth>1</bitWidth>
24771 </field>
24772 <field>
24773 <name>GU</name>
24774 <description>GU</description>
24775 <bitOffset>9</bitOffset>
24776 <bitWidth>1</bitWidth>
24777 </field>
24778 <field>
24779 <name>WFFRPR</name>
24780 <description>WFFRPR</description>
24781 <bitOffset>31</bitOffset>
24782 <bitWidth>1</bitWidth>
24783 </field>
24784 </fields>
24785 </register>
24786 <register>
24787 <name>MACDBGR</name>
24788 <displayName>MACDBGR</displayName>
24789 <description>Ethernet MAC debug register</description>
24790 <addressOffset>0x34</addressOffset>
24791 <size>0x20</size>
24792 <access>read-only</access>
24793 <resetValue>0x00000000</resetValue>
24794 <fields>
24795 <field>
24796 <name>CR</name>
24797 <description>CR</description>
24798 <bitOffset>0</bitOffset>
24799 <bitWidth>1</bitWidth>
24800 </field>
24801 <field>
24802 <name>CSR</name>
24803 <description>CSR</description>
24804 <bitOffset>1</bitOffset>
24805 <bitWidth>1</bitWidth>
24806 </field>
24807 <field>
24808 <name>ROR</name>
24809 <description>ROR</description>
24810 <bitOffset>2</bitOffset>
24811 <bitWidth>1</bitWidth>
24812 </field>
24813 <field>
24814 <name>MCF</name>
24815 <description>MCF</description>
24816 <bitOffset>3</bitOffset>
24817 <bitWidth>1</bitWidth>
24818 </field>
24819 <field>
24820 <name>MCP</name>
24821 <description>MCP</description>
24822 <bitOffset>4</bitOffset>
24823 <bitWidth>1</bitWidth>
24824 </field>
24825 <field>
24826 <name>MCFHP</name>
24827 <description>MCFHP</description>
24828 <bitOffset>5</bitOffset>
24829 <bitWidth>1</bitWidth>
24830 </field>
24831 </fields>
24832 </register>
24833 <register>
24834 <name>MACSR</name>
24835 <displayName>MACSR</displayName>
24836 <description>Ethernet MAC interrupt status
24837 register</description>
24838 <addressOffset>0x38</addressOffset>
24839 <size>0x20</size>
24840 <resetValue>0x00000000</resetValue>
24841 <fields>
24842 <field>
24843 <name>PMTS</name>
24844 <description>PMTS</description>
24845 <bitOffset>3</bitOffset>
24846 <bitWidth>1</bitWidth>
24847 <access>read-only</access>
24848 </field>
24849 <field>
24850 <name>MMCS</name>
24851 <description>MMCS</description>
24852 <bitOffset>4</bitOffset>
24853 <bitWidth>1</bitWidth>
24854 <access>read-only</access>
24855 </field>
24856 <field>
24857 <name>MMCRS</name>
24858 <description>MMCRS</description>
24859 <bitOffset>5</bitOffset>
24860 <bitWidth>1</bitWidth>
24861 <access>read-only</access>
24862 </field>
24863 <field>
24864 <name>MMCTS</name>
24865 <description>MMCTS</description>
24866 <bitOffset>6</bitOffset>
24867 <bitWidth>1</bitWidth>
24868 <access>read-only</access>
24869 </field>
24870 <field>
24871 <name>TSTS</name>
24872 <description>TSTS</description>
24873 <bitOffset>9</bitOffset>
24874 <bitWidth>1</bitWidth>
24875 <access>read-write</access>
24876 </field>
24877 </fields>
24878 </register>
24879 <register>
24880 <name>MACIMR</name>
24881 <displayName>MACIMR</displayName>
24882 <description>Ethernet MAC interrupt mask
24883 register</description>
24884 <addressOffset>0x3C</addressOffset>
24885 <size>0x20</size>
24886 <access>read-write</access>
24887 <resetValue>0x00000000</resetValue>
24888 <fields>
24889 <field>
24890 <name>PMTIM</name>
24891 <description>PMTIM</description>
24892 <bitOffset>3</bitOffset>
24893 <bitWidth>1</bitWidth>
24894 </field>
24895 <field>
24896 <name>TSTIM</name>
24897 <description>TSTIM</description>
24898 <bitOffset>9</bitOffset>
24899 <bitWidth>1</bitWidth>
24900 </field>
24901 </fields>
24902 </register>
24903 <register>
24904 <name>MACA0HR</name>
24905 <displayName>MACA0HR</displayName>
24906 <description>Ethernet MAC address 0 high
24907 register</description>
24908 <addressOffset>0x40</addressOffset>
24909 <size>0x20</size>
24910 <resetValue>0x0010FFFF</resetValue>
24911 <fields>
24912 <field>
24913 <name>MACA0H</name>
24914 <description>MAC address0 high</description>
24915 <bitOffset>0</bitOffset>
24916 <bitWidth>16</bitWidth>
24917 <access>read-write</access>
24918 </field>
24919 <field>
24920 <name>MO</name>
24921 <description>Always 1</description>
24922 <bitOffset>31</bitOffset>
24923 <bitWidth>1</bitWidth>
24924 <access>read-only</access>
24925 </field>
24926 </fields>
24927 </register>
24928 <register>
24929 <name>MACA0LR</name>
24930 <displayName>MACA0LR</displayName>
24931 <description>Ethernet MAC address 0 low
24932 register</description>
24933 <addressOffset>0x44</addressOffset>
24934 <size>0x20</size>
24935 <access>read-write</access>
24936 <resetValue>0xFFFFFFFF</resetValue>
24937 <fields>
24938 <field>
24939 <name>MACA0L</name>
24940 <description>0</description>
24941 <bitOffset>0</bitOffset>
24942 <bitWidth>32</bitWidth>
24943 </field>
24944 </fields>
24945 </register>
24946 <register>
24947 <name>MACA1HR</name>
24948 <displayName>MACA1HR</displayName>
24949 <description>Ethernet MAC address 1 high
24950 register</description>
24951 <addressOffset>0x48</addressOffset>
24952 <size>0x20</size>
24953 <access>read-write</access>
24954 <resetValue>0x0000FFFF</resetValue>
24955 <fields>
24956 <field>
24957 <name>MACA1H</name>
24958 <description>MACA1H</description>
24959 <bitOffset>0</bitOffset>
24960 <bitWidth>16</bitWidth>
24961 </field>
24962 <field>
24963 <name>MBC</name>
24964 <description>MBC</description>
24965 <bitOffset>24</bitOffset>
24966 <bitWidth>6</bitWidth>
24967 </field>
24968 <field>
24969 <name>SA</name>
24970 <description>SA</description>
24971 <bitOffset>30</bitOffset>
24972 <bitWidth>1</bitWidth>
24973 </field>
24974 <field>
24975 <name>AE</name>
24976 <description>AE</description>
24977 <bitOffset>31</bitOffset>
24978 <bitWidth>1</bitWidth>
24979 </field>
24980 </fields>
24981 </register>
24982 <register>
24983 <name>MACA1LR</name>
24984 <displayName>MACA1LR</displayName>
24985 <description>Ethernet MAC address1 low
24986 register</description>
24987 <addressOffset>0x4C</addressOffset>
24988 <size>0x20</size>
24989 <access>read-write</access>
24990 <resetValue>0xFFFFFFFF</resetValue>
24991 <fields>
24992 <field>
24993 <name>MACA1LR</name>
24994 <description>MACA1LR</description>
24995 <bitOffset>0</bitOffset>
24996 <bitWidth>32</bitWidth>
24997 </field>
24998 </fields>
24999 </register>
25000 <register>
25001 <name>MACA2HR</name>
25002 <displayName>MACA2HR</displayName>
25003 <description>Ethernet MAC address 2 high
25004 register</description>
25005 <addressOffset>0x50</addressOffset>
25006 <size>0x20</size>
25007 <access>read-write</access>
25008 <resetValue>0x0000FFFF</resetValue>
25009 <fields>
25010 <field>
25011 <name>MAC2AH</name>
25012 <description>MAC2AH</description>
25013 <bitOffset>0</bitOffset>
25014 <bitWidth>16</bitWidth>
25015 </field>
25016 <field>
25017 <name>MBC</name>
25018 <description>MBC</description>
25019 <bitOffset>24</bitOffset>
25020 <bitWidth>6</bitWidth>
25021 </field>
25022 <field>
25023 <name>SA</name>
25024 <description>SA</description>
25025 <bitOffset>30</bitOffset>
25026 <bitWidth>1</bitWidth>
25027 </field>
25028 <field>
25029 <name>AE</name>
25030 <description>AE</description>
25031 <bitOffset>31</bitOffset>
25032 <bitWidth>1</bitWidth>
25033 </field>
25034 </fields>
25035 </register>
25036 <register>
25037 <name>MACA2LR</name>
25038 <displayName>MACA2LR</displayName>
25039 <description>Ethernet MAC address 2 low
25040 register</description>
25041 <addressOffset>0x54</addressOffset>
25042 <size>0x20</size>
25043 <access>read-write</access>
25044 <resetValue>0xFFFFFFFF</resetValue>
25045 <fields>
25046 <field>
25047 <name>MACA2L</name>
25048 <description>MACA2L</description>
25049 <bitOffset>0</bitOffset>
25050 <bitWidth>31</bitWidth>
25051 </field>
25052 </fields>
25053 </register>
25054 <register>
25055 <name>MACA3HR</name>
25056 <displayName>MACA3HR</displayName>
25057 <description>Ethernet MAC address 3 high
25058 register</description>
25059 <addressOffset>0x58</addressOffset>
25060 <size>0x20</size>
25061 <access>read-write</access>
25062 <resetValue>0x0000FFFF</resetValue>
25063 <fields>
25064 <field>
25065 <name>MACA3H</name>
25066 <description>MACA3H</description>
25067 <bitOffset>0</bitOffset>
25068 <bitWidth>16</bitWidth>
25069 </field>
25070 <field>
25071 <name>MBC</name>
25072 <description>MBC</description>
25073 <bitOffset>24</bitOffset>
25074 <bitWidth>6</bitWidth>
25075 </field>
25076 <field>
25077 <name>SA</name>
25078 <description>SA</description>
25079 <bitOffset>30</bitOffset>
25080 <bitWidth>1</bitWidth>
25081 </field>
25082 <field>
25083 <name>AE</name>
25084 <description>AE</description>
25085 <bitOffset>31</bitOffset>
25086 <bitWidth>1</bitWidth>
25087 </field>
25088 </fields>
25089 </register>
25090 <register>
25091 <name>MACA3LR</name>
25092 <displayName>MACA3LR</displayName>
25093 <description>Ethernet MAC address 3 low
25094 register</description>
25095 <addressOffset>0x5C</addressOffset>
25096 <size>0x20</size>
25097 <access>read-write</access>
25098 <resetValue>0xFFFFFFFF</resetValue>
25099 <fields>
25100 <field>
25101 <name>MBCA3L</name>
25102 <description>MBCA3L</description>
25103 <bitOffset>0</bitOffset>
25104 <bitWidth>32</bitWidth>
25105 </field>
25106 </fields>
25107 </register>
25108 <register>
25109 <name>MACRWUFFER</name>
25110 <displayName>MACRWUFFER</displayName>
25111 <description>Ethernet MAC remote wakeup frame filter
25112 register</description>
25113 <addressOffset>0x60</addressOffset>
25114 <size>0x20</size>
25115 <access>read-write</access>
25116 <resetValue>0xFFFFFFFF</resetValue>
25117 </register>
25118 </registers>
25119 </peripheral>
25120 <peripheral>
25121 <name>Ethernet_MMC</name>
25122 <description>Ethernet: MAC management counters</description>
25123 <groupName>Ethernet</groupName>
25124 <baseAddress>0x40028100</baseAddress>
25125 <addressBlock>
25126 <offset>0x0</offset>
25127 <size>0x400</size>
25128 <usage>registers</usage>
25129 </addressBlock>
25130 <registers>
25131 <register>
25132 <name>MMCCR</name>
25133 <displayName>MMCCR</displayName>
25134 <description>Ethernet MMC control register</description>
25135 <addressOffset>0x0</addressOffset>
25136 <size>0x20</size>
25137 <access>read-write</access>
25138 <resetValue>0x00000000</resetValue>
25139 <fields>
25140 <field>
25141 <name>CR</name>
25142 <description>CR</description>
25143 <bitOffset>0</bitOffset>
25144 <bitWidth>1</bitWidth>
25145 </field>
25146 <field>
25147 <name>CSR</name>
25148 <description>CSR</description>
25149 <bitOffset>1</bitOffset>
25150 <bitWidth>1</bitWidth>
25151 </field>
25152 <field>
25153 <name>ROR</name>
25154 <description>ROR</description>
25155 <bitOffset>2</bitOffset>
25156 <bitWidth>1</bitWidth>
25157 </field>
25158 <field>
25159 <name>MCF</name>
25160 <description>MCF</description>
25161 <bitOffset>3</bitOffset>
25162 <bitWidth>1</bitWidth>
25163 </field>
25164 <field>
25165 <name>MCP</name>
25166 <description>MCP</description>
25167 <bitOffset>4</bitOffset>
25168 <bitWidth>1</bitWidth>
25169 </field>
25170 <field>
25171 <name>MCFHP</name>
25172 <description>MCFHP</description>
25173 <bitOffset>5</bitOffset>
25174 <bitWidth>1</bitWidth>
25175 </field>
25176 </fields>
25177 </register>
25178 <register>
25179 <name>MMCRIR</name>
25180 <displayName>MMCRIR</displayName>
25181 <description>Ethernet MMC receive interrupt
25182 register</description>
25183 <addressOffset>0x4</addressOffset>
25184 <size>0x20</size>
25185 <access>read-write</access>
25186 <resetValue>0x00000000</resetValue>
25187 <fields>
25188 <field>
25189 <name>RFCES</name>
25190 <description>RFCES</description>
25191 <bitOffset>5</bitOffset>
25192 <bitWidth>1</bitWidth>
25193 </field>
25194 <field>
25195 <name>RFAES</name>
25196 <description>RFAES</description>
25197 <bitOffset>6</bitOffset>
25198 <bitWidth>1</bitWidth>
25199 </field>
25200 <field>
25201 <name>RGUFS</name>
25202 <description>RGUFS</description>
25203 <bitOffset>17</bitOffset>
25204 <bitWidth>1</bitWidth>
25205 </field>
25206 </fields>
25207 </register>
25208 <register>
25209 <name>MMCTIR</name>
25210 <displayName>MMCTIR</displayName>
25211 <description>Ethernet MMC transmit interrupt
25212 register</description>
25213 <addressOffset>0x8</addressOffset>
25214 <size>0x20</size>
25215 <access>read-only</access>
25216 <resetValue>0x00000000</resetValue>
25217 <fields>
25218 <field>
25219 <name>TGFSCS</name>
25220 <description>TGFSCS</description>
25221 <bitOffset>14</bitOffset>
25222 <bitWidth>1</bitWidth>
25223 </field>
25224 <field>
25225 <name>TGFMSCS</name>
25226 <description>TGFMSCS</description>
25227 <bitOffset>15</bitOffset>
25228 <bitWidth>1</bitWidth>
25229 </field>
25230 <field>
25231 <name>TGFS</name>
25232 <description>TGFS</description>
25233 <bitOffset>21</bitOffset>
25234 <bitWidth>1</bitWidth>
25235 </field>
25236 </fields>
25237 </register>
25238 <register>
25239 <name>MMCRIMR</name>
25240 <displayName>MMCRIMR</displayName>
25241 <description>Ethernet MMC receive interrupt mask
25242 register</description>
25243 <addressOffset>0xC</addressOffset>
25244 <size>0x20</size>
25245 <access>read-write</access>
25246 <resetValue>0x00000000</resetValue>
25247 <fields>
25248 <field>
25249 <name>RFCEM</name>
25250 <description>RFCEM</description>
25251 <bitOffset>5</bitOffset>
25252 <bitWidth>1</bitWidth>
25253 </field>
25254 <field>
25255 <name>RFAEM</name>
25256 <description>RFAEM</description>
25257 <bitOffset>6</bitOffset>
25258 <bitWidth>1</bitWidth>
25259 </field>
25260 <field>
25261 <name>RGUFM</name>
25262 <description>RGUFM</description>
25263 <bitOffset>17</bitOffset>
25264 <bitWidth>1</bitWidth>
25265 </field>
25266 </fields>
25267 </register>
25268 <register>
25269 <name>MMCTIMR</name>
25270 <displayName>MMCTIMR</displayName>
25271 <description>Ethernet MMC transmit interrupt mask
25272 register</description>
25273 <addressOffset>0x10</addressOffset>
25274 <size>0x20</size>
25275 <access>read-write</access>
25276 <resetValue>0x00000000</resetValue>
25277 <fields>
25278 <field>
25279 <name>TGFSCM</name>
25280 <description>TGFSCM</description>
25281 <bitOffset>14</bitOffset>
25282 <bitWidth>1</bitWidth>
25283 </field>
25284 <field>
25285 <name>TGFMSCM</name>
25286 <description>TGFMSCM</description>
25287 <bitOffset>15</bitOffset>
25288 <bitWidth>1</bitWidth>
25289 </field>
25290 <field>
25291 <name>TGFM</name>
25292 <description>TGFM</description>
25293 <bitOffset>16</bitOffset>
25294 <bitWidth>1</bitWidth>
25295 </field>
25296 </fields>
25297 </register>
25298 <register>
25299 <name>MMCTGFSCCR</name>
25300 <displayName>MMCTGFSCCR</displayName>
25301 <description>Ethernet MMC transmitted good frames after a
25302 single collision counter</description>
25303 <addressOffset>0x4C</addressOffset>
25304 <size>0x20</size>
25305 <access>read-only</access>
25306 <resetValue>0x00000000</resetValue>
25307 <fields>
25308 <field>
25309 <name>TGFSCC</name>
25310 <description>TGFSCC</description>
25311 <bitOffset>0</bitOffset>
25312 <bitWidth>32</bitWidth>
25313 </field>
25314 </fields>
25315 </register>
25316 <register>
25317 <name>MMCTGFMSCCR</name>
25318 <displayName>MMCTGFMSCCR</displayName>
25319 <description>Ethernet MMC transmitted good frames after
25320 more than a single collision</description>
25321 <addressOffset>0x50</addressOffset>
25322 <size>0x20</size>
25323 <access>read-only</access>
25324 <resetValue>0x00000000</resetValue>
25325 <fields>
25326 <field>
25327 <name>TGFMSCC</name>
25328 <description>TGFMSCC</description>
25329 <bitOffset>0</bitOffset>
25330 <bitWidth>32</bitWidth>
25331 </field>
25332 </fields>
25333 </register>
25334 <register>
25335 <name>MMCTGFCR</name>
25336 <displayName>MMCTGFCR</displayName>
25337 <description>Ethernet MMC transmitted good frames counter
25338 register</description>
25339 <addressOffset>0x68</addressOffset>
25340 <size>0x20</size>
25341 <access>read-only</access>
25342 <resetValue>0x00000000</resetValue>
25343 <fields>
25344 <field>
25345 <name>TGFC</name>
25346 <description>HTL</description>
25347 <bitOffset>0</bitOffset>
25348 <bitWidth>32</bitWidth>
25349 </field>
25350 </fields>
25351 </register>
25352 <register>
25353 <name>MMCRFCECR</name>
25354 <displayName>MMCRFCECR</displayName>
25355 <description>Ethernet MMC received frames with CRC error
25356 counter register</description>
25357 <addressOffset>0x94</addressOffset>
25358 <size>0x20</size>
25359 <access>read-only</access>
25360 <resetValue>0x00000000</resetValue>
25361 <fields>
25362 <field>
25363 <name>RFCFC</name>
25364 <description>RFCFC</description>
25365 <bitOffset>0</bitOffset>
25366 <bitWidth>32</bitWidth>
25367 </field>
25368 </fields>
25369 </register>
25370 <register>
25371 <name>MMCRFAECR</name>
25372 <displayName>MMCRFAECR</displayName>
25373 <description>Ethernet MMC received frames with alignment
25374 error counter register</description>
25375 <addressOffset>0x98</addressOffset>
25376 <size>0x20</size>
25377 <access>read-only</access>
25378 <resetValue>0x00000000</resetValue>
25379 <fields>
25380 <field>
25381 <name>RFAEC</name>
25382 <description>RFAEC</description>
25383 <bitOffset>0</bitOffset>
25384 <bitWidth>32</bitWidth>
25385 </field>
25386 </fields>
25387 </register>
25388 <register>
25389 <name>MMCRGUFCR</name>
25390 <displayName>MMCRGUFCR</displayName>
25391 <description>MMC received good unicast frames counter
25392 register</description>
25393 <addressOffset>0xC4</addressOffset>
25394 <size>0x20</size>
25395 <access>read-only</access>
25396 <resetValue>0x00000000</resetValue>
25397 <fields>
25398 <field>
25399 <name>RGUFC</name>
25400 <description>RGUFC</description>
25401 <bitOffset>0</bitOffset>
25402 <bitWidth>32</bitWidth>
25403 </field>
25404 </fields>
25405 </register>
25406 </registers>
25407 </peripheral>
25408 <peripheral>
25409 <name>Ethernet_PTP</name>
25410 <description>Ethernet: Precision time protocol</description>
25411 <groupName>Ethernet</groupName>
25412 <baseAddress>0x40028700</baseAddress>
25413 <addressBlock>
25414 <offset>0x0</offset>
25415 <size>0x400</size>
25416 <usage>registers</usage>
25417 </addressBlock>
25418 <registers>
25419 <register>
25420 <name>PTPTSCR</name>
25421 <displayName>PTPTSCR</displayName>
25422 <description>Ethernet PTP time stamp control
25423 register</description>
25424 <addressOffset>0x0</addressOffset>
25425 <size>0x20</size>
25426 <access>read-write</access>
25427 <resetValue>0x00002000</resetValue>
25428 <fields>
25429 <field>
25430 <name>TSE</name>
25431 <description>TSE</description>
25432 <bitOffset>0</bitOffset>
25433 <bitWidth>1</bitWidth>
25434 </field>
25435 <field>
25436 <name>TSFCU</name>
25437 <description>TSFCU</description>
25438 <bitOffset>1</bitOffset>
25439 <bitWidth>1</bitWidth>
25440 </field>
25441 <field>
25442 <name>TSPTPPSV2E</name>
25443 <description>TSPTPPSV2E</description>
25444 <bitOffset>10</bitOffset>
25445 <bitWidth>1</bitWidth>
25446 </field>
25447 <field>
25448 <name>TSSPTPOEFE</name>
25449 <description>TSSPTPOEFE</description>
25450 <bitOffset>11</bitOffset>
25451 <bitWidth>1</bitWidth>
25452 </field>
25453 <field>
25454 <name>TSSIPV6FE</name>
25455 <description>TSSIPV6FE</description>
25456 <bitOffset>12</bitOffset>
25457 <bitWidth>1</bitWidth>
25458 </field>
25459 <field>
25460 <name>TSSIPV4FE</name>
25461 <description>TSSIPV4FE</description>
25462 <bitOffset>13</bitOffset>
25463 <bitWidth>1</bitWidth>
25464 </field>
25465 <field>
25466 <name>TSSEME</name>
25467 <description>TSSEME</description>
25468 <bitOffset>14</bitOffset>
25469 <bitWidth>1</bitWidth>
25470 </field>
25471 <field>
25472 <name>TSSMRME</name>
25473 <description>TSSMRME</description>
25474 <bitOffset>15</bitOffset>
25475 <bitWidth>1</bitWidth>
25476 </field>
25477 <field>
25478 <name>TSCNT</name>
25479 <description>TSCNT</description>
25480 <bitOffset>16</bitOffset>
25481 <bitWidth>2</bitWidth>
25482 </field>
25483 <field>
25484 <name>TSPFFMAE</name>
25485 <description>TSPFFMAE</description>
25486 <bitOffset>18</bitOffset>
25487 <bitWidth>1</bitWidth>
25488 </field>
25489 <field>
25490 <name>TSSTI</name>
25491 <description>TSSTI</description>
25492 <bitOffset>2</bitOffset>
25493 <bitWidth>1</bitWidth>
25494 </field>
25495 <field>
25496 <name>TSSTU</name>
25497 <description>TSSTU</description>
25498 <bitOffset>3</bitOffset>
25499 <bitWidth>1</bitWidth>
25500 </field>
25501 <field>
25502 <name>TSITE</name>
25503 <description>TSITE</description>
25504 <bitOffset>4</bitOffset>
25505 <bitWidth>1</bitWidth>
25506 </field>
25507 <field>
25508 <name>TTSARU</name>
25509 <description>TTSARU</description>
25510 <bitOffset>5</bitOffset>
25511 <bitWidth>1</bitWidth>
25512 </field>
25513 <field>
25514 <name>TSSARFE</name>
25515 <description>TSSARFE</description>
25516 <bitOffset>8</bitOffset>
25517 <bitWidth>1</bitWidth>
25518 </field>
25519 <field>
25520 <name>TSSSR</name>
25521 <description>TSSSR</description>
25522 <bitOffset>9</bitOffset>
25523 <bitWidth>1</bitWidth>
25524 </field>
25525 </fields>
25526 </register>
25527 <register>
25528 <name>PTPSSIR</name>
25529 <displayName>PTPSSIR</displayName>
25530 <description>Ethernet PTP subsecond increment
25531 register</description>
25532 <addressOffset>0x4</addressOffset>
25533 <size>0x20</size>
25534 <access>read-write</access>
25535 <resetValue>0x00000000</resetValue>
25536 <fields>
25537 <field>
25538 <name>STSSI</name>
25539 <description>STSSI</description>
25540 <bitOffset>0</bitOffset>
25541 <bitWidth>8</bitWidth>
25542 </field>
25543 </fields>
25544 </register>
25545 <register>
25546 <name>PTPTSHR</name>
25547 <displayName>PTPTSHR</displayName>
25548 <description>Ethernet PTP time stamp high
25549 register</description>
25550 <addressOffset>0x8</addressOffset>
25551 <size>0x20</size>
25552 <access>read-only</access>
25553 <resetValue>0x00000000</resetValue>
25554 <fields>
25555 <field>
25556 <name>STS</name>
25557 <description>STS</description>
25558 <bitOffset>0</bitOffset>
25559 <bitWidth>32</bitWidth>
25560 </field>
25561 </fields>
25562 </register>
25563 <register>
25564 <name>PTPTSLR</name>
25565 <displayName>PTPTSLR</displayName>
25566 <description>Ethernet PTP time stamp low
25567 register</description>
25568 <addressOffset>0xC</addressOffset>
25569 <size>0x20</size>
25570 <access>read-only</access>
25571 <resetValue>0x00000000</resetValue>
25572 <fields>
25573 <field>
25574 <name>STSS</name>
25575 <description>STSS</description>
25576 <bitOffset>0</bitOffset>
25577 <bitWidth>31</bitWidth>
25578 </field>
25579 <field>
25580 <name>STPNS</name>
25581 <description>STPNS</description>
25582 <bitOffset>31</bitOffset>
25583 <bitWidth>1</bitWidth>
25584 </field>
25585 </fields>
25586 </register>
25587 <register>
25588 <name>PTPTSHUR</name>
25589 <displayName>PTPTSHUR</displayName>
25590 <description>Ethernet PTP time stamp high update
25591 register</description>
25592 <addressOffset>0x10</addressOffset>
25593 <size>0x20</size>
25594 <access>read-write</access>
25595 <resetValue>0x00000000</resetValue>
25596 <fields>
25597 <field>
25598 <name>TSUS</name>
25599 <description>TSUS</description>
25600 <bitOffset>0</bitOffset>
25601 <bitWidth>32</bitWidth>
25602 </field>
25603 </fields>
25604 </register>
25605 <register>
25606 <name>PTPTSLUR</name>
25607 <displayName>PTPTSLUR</displayName>
25608 <description>Ethernet PTP time stamp low update
25609 register</description>
25610 <addressOffset>0x14</addressOffset>
25611 <size>0x20</size>
25612 <access>read-write</access>
25613 <resetValue>0x00000000</resetValue>
25614 <fields>
25615 <field>
25616 <name>TSUSS</name>
25617 <description>TSUSS</description>
25618 <bitOffset>0</bitOffset>
25619 <bitWidth>31</bitWidth>
25620 </field>
25621 <field>
25622 <name>TSUPNS</name>
25623 <description>TSUPNS</description>
25624 <bitOffset>31</bitOffset>
25625 <bitWidth>1</bitWidth>
25626 </field>
25627 </fields>
25628 </register>
25629 <register>
25630 <name>PTPTSAR</name>
25631 <displayName>PTPTSAR</displayName>
25632 <description>Ethernet PTP time stamp addend
25633 register</description>
25634 <addressOffset>0x18</addressOffset>
25635 <size>0x20</size>
25636 <access>read-write</access>
25637 <resetValue>0x00000000</resetValue>
25638 <fields>
25639 <field>
25640 <name>TSA</name>
25641 <description>TSA</description>
25642 <bitOffset>0</bitOffset>
25643 <bitWidth>32</bitWidth>
25644 </field>
25645 </fields>
25646 </register>
25647 <register>
25648 <name>PTPTTHR</name>
25649 <displayName>PTPTTHR</displayName>
25650 <description>Ethernet PTP target time high
25651 register</description>
25652 <addressOffset>0x1C</addressOffset>
25653 <size>0x20</size>
25654 <access>read-write</access>
25655 <resetValue>0x00000000</resetValue>
25656 <fields>
25657 <field>
25658 <name>TTSH</name>
25659 <description>0</description>
25660 <bitOffset>0</bitOffset>
25661 <bitWidth>32</bitWidth>
25662 </field>
25663 </fields>
25664 </register>
25665 <register>
25666 <name>PTPTTLR</name>
25667 <displayName>PTPTTLR</displayName>
25668 <description>Ethernet PTP target time low
25669 register</description>
25670 <addressOffset>0x20</addressOffset>
25671 <size>0x20</size>
25672 <access>read-write</access>
25673 <resetValue>0x00000000</resetValue>
25674 <fields>
25675 <field>
25676 <name>TTSL</name>
25677 <description>TTSL</description>
25678 <bitOffset>0</bitOffset>
25679 <bitWidth>32</bitWidth>
25680 </field>
25681 </fields>
25682 </register>
25683 <register>
25684 <name>PTPTSSR</name>
25685 <displayName>PTPTSSR</displayName>
25686 <description>Ethernet PTP time stamp status
25687 register</description>
25688 <addressOffset>0x28</addressOffset>
25689 <size>0x20</size>
25690 <access>read-only</access>
25691 <resetValue>0x00000000</resetValue>
25692 <fields>
25693 <field>
25694 <name>TSSO</name>
25695 <description>TSSO</description>
25696 <bitOffset>0</bitOffset>
25697 <bitWidth>1</bitWidth>
25698 </field>
25699 <field>
25700 <name>TSTTR</name>
25701 <description>TSTTR</description>
25702 <bitOffset>1</bitOffset>
25703 <bitWidth>1</bitWidth>
25704 </field>
25705 </fields>
25706 </register>
25707 <register>
25708 <name>PTPPPSCR</name>
25709 <displayName>PTPPPSCR</displayName>
25710 <description>Ethernet PTP PPS control
25711 register</description>
25712 <addressOffset>0x2C</addressOffset>
25713 <size>0x20</size>
25714 <access>read-only</access>
25715 <resetValue>0x00000000</resetValue>
25716 <fields>
25717 <field>
25718 <name>TSSO</name>
25719 <description>TSSO</description>
25720 <bitOffset>0</bitOffset>
25721 <bitWidth>1</bitWidth>
25722 </field>
25723 <field>
25724 <name>TSTTR</name>
25725 <description>TSTTR</description>
25726 <bitOffset>1</bitOffset>
25727 <bitWidth>1</bitWidth>
25728 </field>
25729 </fields>
25730 </register>
25731 </registers>
25732 </peripheral>
25733 <peripheral>
25734 <name>Ethernet_DMA</name>
25735 <description>Ethernet: DMA controller operation</description>
25736 <groupName>Ethernet</groupName>
25737 <baseAddress>0x40029000</baseAddress>
25738 <addressBlock>
25739 <offset>0x0</offset>
25740 <size>0x400</size>
25741 <usage>registers</usage>
25742 </addressBlock>
25743 <interrupt>
25744 <name>ETH</name>
25745 <description>Ethernet global interrupt</description>
25746 <value>61</value>
25747 </interrupt>
25748 <interrupt>
25749 <name>ETH_WKUP</name>
25750 <description>Ethernet Wakeup through EXTI line
25751 interrupt</description>
25752 <value>62</value>
25753 </interrupt>
25754 <registers>
25755 <register>
25756 <name>DMABMR</name>
25757 <displayName>DMABMR</displayName>
25758 <description>Ethernet DMA bus mode register</description>
25759 <addressOffset>0x0</addressOffset>
25760 <size>0x20</size>
25761 <access>read-write</access>
25762 <resetValue>0x00002101</resetValue>
25763 <fields>
25764 <field>
25765 <name>SR</name>
25766 <description>SR</description>
25767 <bitOffset>0</bitOffset>
25768 <bitWidth>1</bitWidth>
25769 </field>
25770 <field>
25771 <name>DA</name>
25772 <description>DA</description>
25773 <bitOffset>1</bitOffset>
25774 <bitWidth>1</bitWidth>
25775 </field>
25776 <field>
25777 <name>DSL</name>
25778 <description>DSL</description>
25779 <bitOffset>2</bitOffset>
25780 <bitWidth>5</bitWidth>
25781 </field>
25782 <field>
25783 <name>EDFE</name>
25784 <description>EDFE</description>
25785 <bitOffset>7</bitOffset>
25786 <bitWidth>1</bitWidth>
25787 </field>
25788 <field>
25789 <name>PBL</name>
25790 <description>PBL</description>
25791 <bitOffset>8</bitOffset>
25792 <bitWidth>6</bitWidth>
25793 </field>
25794 <field>
25795 <name>RTPR</name>
25796 <description>RTPR</description>
25797 <bitOffset>14</bitOffset>
25798 <bitWidth>2</bitWidth>
25799 </field>
25800 <field>
25801 <name>FB</name>
25802 <description>FB</description>
25803 <bitOffset>16</bitOffset>
25804 <bitWidth>1</bitWidth>
25805 </field>
25806 <field>
25807 <name>RDP</name>
25808 <description>RDP</description>
25809 <bitOffset>17</bitOffset>
25810 <bitWidth>6</bitWidth>
25811 </field>
25812 <field>
25813 <name>USP</name>
25814 <description>USP</description>
25815 <bitOffset>23</bitOffset>
25816 <bitWidth>1</bitWidth>
25817 </field>
25818 <field>
25819 <name>FPM</name>
25820 <description>FPM</description>
25821 <bitOffset>24</bitOffset>
25822 <bitWidth>1</bitWidth>
25823 </field>
25824 <field>
25825 <name>AAB</name>
25826 <description>AAB</description>
25827 <bitOffset>25</bitOffset>
25828 <bitWidth>1</bitWidth>
25829 </field>
25830 <field>
25831 <name>MB</name>
25832 <description>MB</description>
25833 <bitOffset>26</bitOffset>
25834 <bitWidth>1</bitWidth>
25835 </field>
25836 </fields>
25837 </register>
25838 <register>
25839 <name>DMATPDR</name>
25840 <displayName>DMATPDR</displayName>
25841 <description>Ethernet DMA transmit poll demand
25842 register</description>
25843 <addressOffset>0x4</addressOffset>
25844 <size>0x20</size>
25845 <access>read-write</access>
25846 <resetValue>0x00000000</resetValue>
25847 <fields>
25848 <field>
25849 <name>TPD</name>
25850 <description>TPD</description>
25851 <bitOffset>0</bitOffset>
25852 <bitWidth>32</bitWidth>
25853 </field>
25854 </fields>
25855 </register>
25856 <register>
25857 <name>DMARPDR</name>
25858 <displayName>DMARPDR</displayName>
25859 <description>EHERNET DMA receive poll demand
25860 register</description>
25861 <addressOffset>0x8</addressOffset>
25862 <size>0x20</size>
25863 <access>read-write</access>
25864 <resetValue>0x00000000</resetValue>
25865 <fields>
25866 <field>
25867 <name>RPD</name>
25868 <description>RPD</description>
25869 <bitOffset>0</bitOffset>
25870 <bitWidth>32</bitWidth>
25871 </field>
25872 </fields>
25873 </register>
25874 <register>
25875 <name>DMARDLAR</name>
25876 <displayName>DMARDLAR</displayName>
25877 <description>Ethernet DMA receive descriptor list address
25878 register</description>
25879 <addressOffset>0xC</addressOffset>
25880 <size>0x20</size>
25881 <access>read-write</access>
25882 <resetValue>0x00000000</resetValue>
25883 <fields>
25884 <field>
25885 <name>SRL</name>
25886 <description>SRL</description>
25887 <bitOffset>0</bitOffset>
25888 <bitWidth>32</bitWidth>
25889 </field>
25890 </fields>
25891 </register>
25892 <register>
25893 <name>DMATDLAR</name>
25894 <displayName>DMATDLAR</displayName>
25895 <description>Ethernet DMA transmit descriptor list
25896 address register</description>
25897 <addressOffset>0x10</addressOffset>
25898 <size>0x20</size>
25899 <access>read-write</access>
25900 <resetValue>0x00000000</resetValue>
25901 <fields>
25902 <field>
25903 <name>STL</name>
25904 <description>STL</description>
25905 <bitOffset>0</bitOffset>
25906 <bitWidth>32</bitWidth>
25907 </field>
25908 </fields>
25909 </register>
25910 <register>
25911 <name>DMASR</name>
25912 <displayName>DMASR</displayName>
25913 <description>Ethernet DMA status register</description>
25914 <addressOffset>0x14</addressOffset>
25915 <size>0x20</size>
25916 <resetValue>0x00000000</resetValue>
25917 <fields>
25918 <field>
25919 <name>TS</name>
25920 <description>TS</description>
25921 <bitOffset>0</bitOffset>
25922 <bitWidth>1</bitWidth>
25923 <access>read-write</access>
25924 </field>
25925 <field>
25926 <name>TPSS</name>
25927 <description>TPSS</description>
25928 <bitOffset>1</bitOffset>
25929 <bitWidth>1</bitWidth>
25930 <access>read-write</access>
25931 </field>
25932 <field>
25933 <name>TBUS</name>
25934 <description>TBUS</description>
25935 <bitOffset>2</bitOffset>
25936 <bitWidth>1</bitWidth>
25937 <access>read-write</access>
25938 </field>
25939 <field>
25940 <name>TJTS</name>
25941 <description>TJTS</description>
25942 <bitOffset>3</bitOffset>
25943 <bitWidth>1</bitWidth>
25944 <access>read-write</access>
25945 </field>
25946 <field>
25947 <name>ROS</name>
25948 <description>ROS</description>
25949 <bitOffset>4</bitOffset>
25950 <bitWidth>1</bitWidth>
25951 <access>read-write</access>
25952 </field>
25953 <field>
25954 <name>TUS</name>
25955 <description>TUS</description>
25956 <bitOffset>5</bitOffset>
25957 <bitWidth>1</bitWidth>
25958 <access>read-write</access>
25959 </field>
25960 <field>
25961 <name>RS</name>
25962 <description>RS</description>
25963 <bitOffset>6</bitOffset>
25964 <bitWidth>1</bitWidth>
25965 <access>read-write</access>
25966 </field>
25967 <field>
25968 <name>RBUS</name>
25969 <description>RBUS</description>
25970 <bitOffset>7</bitOffset>
25971 <bitWidth>1</bitWidth>
25972 <access>read-write</access>
25973 </field>
25974 <field>
25975 <name>RPSS</name>
25976 <description>RPSS</description>
25977 <bitOffset>8</bitOffset>
25978 <bitWidth>1</bitWidth>
25979 <access>read-write</access>
25980 </field>
25981 <field>
25982 <name>PWTS</name>
25983 <description>PWTS</description>
25984 <bitOffset>9</bitOffset>
25985 <bitWidth>1</bitWidth>
25986 <access>read-write</access>
25987 </field>
25988 <field>
25989 <name>ETS</name>
25990 <description>ETS</description>
25991 <bitOffset>10</bitOffset>
25992 <bitWidth>1</bitWidth>
25993 <access>read-write</access>
25994 </field>
25995 <field>
25996 <name>FBES</name>
25997 <description>FBES</description>
25998 <bitOffset>13</bitOffset>
25999 <bitWidth>1</bitWidth>
26000 <access>read-write</access>
26001 </field>
26002 <field>
26003 <name>ERS</name>
26004 <description>ERS</description>
26005 <bitOffset>14</bitOffset>
26006 <bitWidth>1</bitWidth>
26007 <access>read-write</access>
26008 </field>
26009 <field>
26010 <name>AIS</name>
26011 <description>AIS</description>
26012 <bitOffset>15</bitOffset>
26013 <bitWidth>1</bitWidth>
26014 <access>read-write</access>
26015 </field>
26016 <field>
26017 <name>NIS</name>
26018 <description>NIS</description>
26019 <bitOffset>16</bitOffset>
26020 <bitWidth>1</bitWidth>
26021 <access>read-write</access>
26022 </field>
26023 <field>
26024 <name>RPS</name>
26025 <description>RPS</description>
26026 <bitOffset>17</bitOffset>
26027 <bitWidth>3</bitWidth>
26028 <access>read-only</access>
26029 </field>
26030 <field>
26031 <name>TPS</name>
26032 <description>TPS</description>
26033 <bitOffset>20</bitOffset>
26034 <bitWidth>3</bitWidth>
26035 <access>read-only</access>
26036 </field>
26037 <field>
26038 <name>EBS</name>
26039 <description>EBS</description>
26040 <bitOffset>23</bitOffset>
26041 <bitWidth>3</bitWidth>
26042 <access>read-only</access>
26043 </field>
26044 <field>
26045 <name>MMCS</name>
26046 <description>MMCS</description>
26047 <bitOffset>27</bitOffset>
26048 <bitWidth>1</bitWidth>
26049 <access>read-only</access>
26050 </field>
26051 <field>
26052 <name>PMTS</name>
26053 <description>PMTS</description>
26054 <bitOffset>28</bitOffset>
26055 <bitWidth>1</bitWidth>
26056 <access>read-only</access>
26057 </field>
26058 <field>
26059 <name>TSTS</name>
26060 <description>TSTS</description>
26061 <bitOffset>29</bitOffset>
26062 <bitWidth>1</bitWidth>
26063 <access>read-only</access>
26064 </field>
26065 </fields>
26066 </register>
26067 <register>
26068 <name>DMAOMR</name>
26069 <displayName>DMAOMR</displayName>
26070 <description>Ethernet DMA operation mode
26071 register</description>
26072 <addressOffset>0x18</addressOffset>
26073 <size>0x20</size>
26074 <access>read-write</access>
26075 <resetValue>0x00000000</resetValue>
26076 <fields>
26077 <field>
26078 <name>SR</name>
26079 <description>SR</description>
26080 <bitOffset>1</bitOffset>
26081 <bitWidth>1</bitWidth>
26082 </field>
26083 <field>
26084 <name>OSF</name>
26085 <description>OSF</description>
26086 <bitOffset>2</bitOffset>
26087 <bitWidth>1</bitWidth>
26088 </field>
26089 <field>
26090 <name>RTC</name>
26091 <description>RTC</description>
26092 <bitOffset>3</bitOffset>
26093 <bitWidth>2</bitWidth>
26094 </field>
26095 <field>
26096 <name>FUGF</name>
26097 <description>FUGF</description>
26098 <bitOffset>6</bitOffset>
26099 <bitWidth>1</bitWidth>
26100 </field>
26101 <field>
26102 <name>FEF</name>
26103 <description>FEF</description>
26104 <bitOffset>7</bitOffset>
26105 <bitWidth>1</bitWidth>
26106 </field>
26107 <field>
26108 <name>ST</name>
26109 <description>ST</description>
26110 <bitOffset>13</bitOffset>
26111 <bitWidth>1</bitWidth>
26112 </field>
26113 <field>
26114 <name>TTC</name>
26115 <description>TTC</description>
26116 <bitOffset>14</bitOffset>
26117 <bitWidth>3</bitWidth>
26118 </field>
26119 <field>
26120 <name>FTF</name>
26121 <description>FTF</description>
26122 <bitOffset>20</bitOffset>
26123 <bitWidth>1</bitWidth>
26124 </field>
26125 <field>
26126 <name>TSF</name>
26127 <description>TSF</description>
26128 <bitOffset>21</bitOffset>
26129 <bitWidth>1</bitWidth>
26130 </field>
26131 <field>
26132 <name>DFRF</name>
26133 <description>DFRF</description>
26134 <bitOffset>24</bitOffset>
26135 <bitWidth>1</bitWidth>
26136 </field>
26137 <field>
26138 <name>RSF</name>
26139 <description>RSF</description>
26140 <bitOffset>25</bitOffset>
26141 <bitWidth>1</bitWidth>
26142 </field>
26143 <field>
26144 <name>DTCEFD</name>
26145 <description>DTCEFD</description>
26146 <bitOffset>26</bitOffset>
26147 <bitWidth>1</bitWidth>
26148 </field>
26149 </fields>
26150 </register>
26151 <register>
26152 <name>DMAIER</name>
26153 <displayName>DMAIER</displayName>
26154 <description>Ethernet DMA interrupt enable
26155 register</description>
26156 <addressOffset>0x1C</addressOffset>
26157 <size>0x20</size>
26158 <access>read-write</access>
26159 <resetValue>0x00000000</resetValue>
26160 <fields>
26161 <field>
26162 <name>TIE</name>
26163 <description>TIE</description>
26164 <bitOffset>0</bitOffset>
26165 <bitWidth>1</bitWidth>
26166 </field>
26167 <field>
26168 <name>TPSIE</name>
26169 <description>TPSIE</description>
26170 <bitOffset>1</bitOffset>
26171 <bitWidth>1</bitWidth>
26172 </field>
26173 <field>
26174 <name>TBUIE</name>
26175 <description>TBUIE</description>
26176 <bitOffset>2</bitOffset>
26177 <bitWidth>1</bitWidth>
26178 </field>
26179 <field>
26180 <name>TJTIE</name>
26181 <description>TJTIE</description>
26182 <bitOffset>3</bitOffset>
26183 <bitWidth>1</bitWidth>
26184 </field>
26185 <field>
26186 <name>ROIE</name>
26187 <description>ROIE</description>
26188 <bitOffset>4</bitOffset>
26189 <bitWidth>1</bitWidth>
26190 </field>
26191 <field>
26192 <name>TUIE</name>
26193 <description>TUIE</description>
26194 <bitOffset>5</bitOffset>
26195 <bitWidth>1</bitWidth>
26196 </field>
26197 <field>
26198 <name>RIE</name>
26199 <description>RIE</description>
26200 <bitOffset>6</bitOffset>
26201 <bitWidth>1</bitWidth>
26202 </field>
26203 <field>
26204 <name>RBUIE</name>
26205 <description>RBUIE</description>
26206 <bitOffset>7</bitOffset>
26207 <bitWidth>1</bitWidth>
26208 </field>
26209 <field>
26210 <name>RPSIE</name>
26211 <description>RPSIE</description>
26212 <bitOffset>8</bitOffset>
26213 <bitWidth>1</bitWidth>
26214 </field>
26215 <field>
26216 <name>RWTIE</name>
26217 <description>RWTIE</description>
26218 <bitOffset>9</bitOffset>
26219 <bitWidth>1</bitWidth>
26220 </field>
26221 <field>
26222 <name>ETIE</name>
26223 <description>ETIE</description>
26224 <bitOffset>10</bitOffset>
26225 <bitWidth>1</bitWidth>
26226 </field>
26227 <field>
26228 <name>FBEIE</name>
26229 <description>FBEIE</description>
26230 <bitOffset>13</bitOffset>
26231 <bitWidth>1</bitWidth>
26232 </field>
26233 <field>
26234 <name>ERIE</name>
26235 <description>ERIE</description>
26236 <bitOffset>14</bitOffset>
26237 <bitWidth>1</bitWidth>
26238 </field>
26239 <field>
26240 <name>AISE</name>
26241 <description>AISE</description>
26242 <bitOffset>15</bitOffset>
26243 <bitWidth>1</bitWidth>
26244 </field>
26245 <field>
26246 <name>NISE</name>
26247 <description>NISE</description>
26248 <bitOffset>16</bitOffset>
26249 <bitWidth>1</bitWidth>
26250 </field>
26251 </fields>
26252 </register>
26253 <register>
26254 <name>DMAMFBOCR</name>
26255 <displayName>DMAMFBOCR</displayName>
26256 <description>Ethernet DMA missed frame and buffer
26257 overflow counter register</description>
26258 <addressOffset>0x20</addressOffset>
26259 <size>0x20</size>
26260 <access>read-write</access>
26261 <resetValue>0x00000000</resetValue>
26262 <fields>
26263 <field>
26264 <name>MFC</name>
26265 <description>MFC</description>
26266 <bitOffset>0</bitOffset>
26267 <bitWidth>16</bitWidth>
26268 </field>
26269 <field>
26270 <name>OMFC</name>
26271 <description>OMFC</description>
26272 <bitOffset>16</bitOffset>
26273 <bitWidth>1</bitWidth>
26274 </field>
26275 <field>
26276 <name>MFA</name>
26277 <description>MFA</description>
26278 <bitOffset>17</bitOffset>
26279 <bitWidth>11</bitWidth>
26280 </field>
26281 <field>
26282 <name>OFOC</name>
26283 <description>OFOC</description>
26284 <bitOffset>28</bitOffset>
26285 <bitWidth>1</bitWidth>
26286 </field>
26287 </fields>
26288 </register>
26289 <register>
26290 <name>DMARSWTR</name>
26291 <displayName>DMARSWTR</displayName>
26292 <description>Ethernet DMA receive status watchdog timer
26293 register</description>
26294 <addressOffset>0x24</addressOffset>
26295 <size>0x20</size>
26296 <access>read-write</access>
26297 <resetValue>0x00000000</resetValue>
26298 <fields>
26299 <field>
26300 <name>RSWTC</name>
26301 <description>RSWTC</description>
26302 <bitOffset>0</bitOffset>
26303 <bitWidth>8</bitWidth>
26304 </field>
26305 </fields>
26306 </register>
26307 <register>
26308 <name>DMACHTDR</name>
26309 <displayName>DMACHTDR</displayName>
26310 <description>Ethernet DMA current host transmit
26311 descriptor register</description>
26312 <addressOffset>0x48</addressOffset>
26313 <size>0x20</size>
26314 <access>read-only</access>
26315 <resetValue>0x00000000</resetValue>
26316 <fields>
26317 <field>
26318 <name>HTDAP</name>
26319 <description>HTDAP</description>
26320 <bitOffset>0</bitOffset>
26321 <bitWidth>32</bitWidth>
26322 </field>
26323 </fields>
26324 </register>
26325 <register>
26326 <name>DMACHRDR</name>
26327 <displayName>DMACHRDR</displayName>
26328 <description>Ethernet DMA current host receive descriptor
26329 register</description>
26330 <addressOffset>0x4C</addressOffset>
26331 <size>0x20</size>
26332 <access>read-only</access>
26333 <resetValue>0x00000000</resetValue>
26334 <fields>
26335 <field>
26336 <name>HRDAP</name>
26337 <description>HRDAP</description>
26338 <bitOffset>0</bitOffset>
26339 <bitWidth>32</bitWidth>
26340 </field>
26341 </fields>
26342 </register>
26343 <register>
26344 <name>DMACHTBAR</name>
26345 <displayName>DMACHTBAR</displayName>
26346 <description>Ethernet DMA current host transmit buffer
26347 address register</description>
26348 <addressOffset>0x50</addressOffset>
26349 <size>0x20</size>
26350 <access>read-only</access>
26351 <resetValue>0x00000000</resetValue>
26352 <fields>
26353 <field>
26354 <name>HTBAP</name>
26355 <description>HTBAP</description>
26356 <bitOffset>0</bitOffset>
26357 <bitWidth>32</bitWidth>
26358 </field>
26359 </fields>
26360 </register>
26361 <register>
26362 <name>DMACHRBAR</name>
26363 <displayName>DMACHRBAR</displayName>
26364 <description>Ethernet DMA current host receive buffer
26365 address register</description>
26366 <addressOffset>0x54</addressOffset>
26367 <size>0x20</size>
26368 <access>read-only</access>
26369 <resetValue>0x00000000</resetValue>
26370 <fields>
26371 <field>
26372 <name>HRBAP</name>
26373 <description>HRBAP</description>
26374 <bitOffset>0</bitOffset>
26375 <bitWidth>32</bitWidth>
26376 </field>
26377 </fields>
26378 </register>
26379 </registers>
26380 </peripheral>
26381 <peripheral>
26382 <name>CRC</name>
26383 <description>Cryptographic processor</description>
26384 <groupName>CRC</groupName>
26385 <baseAddress>0x40023000</baseAddress>
26386 <addressBlock>
26387 <offset>0x0</offset>
26388 <size>0x400</size>
26389 <usage>registers</usage>
26390 </addressBlock>
26391 <registers>
26392 <register>
26393 <name>DR</name>
26394 <displayName>DR</displayName>
26395 <description>Data register</description>
26396 <addressOffset>0x0</addressOffset>
26397 <size>0x20</size>
26398 <access>read-write</access>
26399 <resetValue>0xFFFFFFFF</resetValue>
26400 <fields>
26401 <field>
26402 <name>DR</name>
26403 <description>Data Register</description>
26404 <bitOffset>0</bitOffset>
26405 <bitWidth>32</bitWidth>
26406 </field>
26407 </fields>
26408 </register>
26409 <register>
26410 <name>IDR</name>
26411 <displayName>IDR</displayName>
26412 <description>Independent Data register</description>
26413 <addressOffset>0x4</addressOffset>
26414 <size>0x20</size>
26415 <access>read-write</access>
26416 <resetValue>0x00000000</resetValue>
26417 <fields>
26418 <field>
26419 <name>IDR</name>
26420 <description>Independent Data register</description>
26421 <bitOffset>0</bitOffset>
26422 <bitWidth>8</bitWidth>
26423 </field>
26424 </fields>
26425 </register>
26426 <register>
26427 <name>CR</name>
26428 <displayName>CR</displayName>
26429 <description>Control register</description>
26430 <addressOffset>0x8</addressOffset>
26431 <size>0x20</size>
26432 <access>write-only</access>
26433 <resetValue>0x00000000</resetValue>
26434 <fields>
26435 <field>
26436 <name>CR</name>
26437 <description>Control regidter</description>
26438 <bitOffset>0</bitOffset>
26439 <bitWidth>1</bitWidth>
26440 </field>
26441 </fields>
26442 </register>
26443 <register>
26444 <name>INIT</name>
26445 <displayName>INIT</displayName>
26446 <description>Initial CRC value</description>
26447 <addressOffset>0xC</addressOffset>
26448 <size>0x20</size>
26449 <access>read-write</access>
26450 <resetValue>0x00000000</resetValue>
26451 <fields>
26452 <field>
26453 <name>CRC_INIT</name>
26454 <description>Programmable initial CRC
26455 value</description>
26456 <bitOffset>0</bitOffset>
26457 <bitWidth>32</bitWidth>
26458 </field>
26459 </fields>
26460 </register>
26461 <register>
26462 <name>POL</name>
26463 <displayName>POL</displayName>
26464 <description>CRC polynomial</description>
26465 <addressOffset>0x10</addressOffset>
26466 <size>0x20</size>
26467 <access>read-write</access>
26468 <resetValue>0x00000000</resetValue>
26469 <fields>
26470 <field>
26471 <name>POL</name>
26472 <description>Programmable polynomial</description>
26473 <bitOffset>0</bitOffset>
26474 <bitWidth>32</bitWidth>
26475 </field>
26476 </fields>
26477 </register>
26478 </registers>
26479 </peripheral>
26480 <peripheral>
26481 <name>CAN1</name>
26482 <description>Controller area network</description>
26483 <groupName>CAN</groupName>
26484 <baseAddress>0x40006400</baseAddress>
26485 <addressBlock>
26486 <offset>0x0</offset>
26487 <size>0x400</size>
26488 <usage>registers</usage>
26489 </addressBlock>
26490 <interrupt>
26491 <name>CAN1_TX</name>
26492 <description>CAN1 TX interrupts</description>
26493 <value>19</value>
26494 </interrupt>
26495 <interrupt>
26496 <name>CAN1_RX0</name>
26497 <description>CAN1 RX0 interrupts</description>
26498 <value>20</value>
26499 </interrupt>
26500 <interrupt>
26501 <name>CAN1_RX1</name>
26502 <description>CAN1 RX1 interrupts</description>
26503 <value>21</value>
26504 </interrupt>
26505 <interrupt>
26506 <name>CAN1_SCE</name>
26507 <description>CAN1 SCE interrupt</description>
26508 <value>22</value>
26509 </interrupt>
26510 <registers>
26511 <register>
26512 <name>MCR</name>
26513 <displayName>MCR</displayName>
26514 <description>master control register</description>
26515 <addressOffset>0x0</addressOffset>
26516 <size>0x20</size>
26517 <access>read-write</access>
26518 <resetValue>0x00010002</resetValue>
26519 <fields>
26520 <field>
26521 <name>DBF</name>
26522 <description>DBF</description>
26523 <bitOffset>16</bitOffset>
26524 <bitWidth>1</bitWidth>
26525 </field>
26526 <field>
26527 <name>RESET</name>
26528 <description>RESET</description>
26529 <bitOffset>15</bitOffset>
26530 <bitWidth>1</bitWidth>
26531 </field>
26532 <field>
26533 <name>TTCM</name>
26534 <description>TTCM</description>
26535 <bitOffset>7</bitOffset>
26536 <bitWidth>1</bitWidth>
26537 </field>
26538 <field>
26539 <name>ABOM</name>
26540 <description>ABOM</description>
26541 <bitOffset>6</bitOffset>
26542 <bitWidth>1</bitWidth>
26543 </field>
26544 <field>
26545 <name>AWUM</name>
26546 <description>AWUM</description>
26547 <bitOffset>5</bitOffset>
26548 <bitWidth>1</bitWidth>
26549 </field>
26550 <field>
26551 <name>NART</name>
26552 <description>NART</description>
26553 <bitOffset>4</bitOffset>
26554 <bitWidth>1</bitWidth>
26555 </field>
26556 <field>
26557 <name>RFLM</name>
26558 <description>RFLM</description>
26559 <bitOffset>3</bitOffset>
26560 <bitWidth>1</bitWidth>
26561 </field>
26562 <field>
26563 <name>TXFP</name>
26564 <description>TXFP</description>
26565 <bitOffset>2</bitOffset>
26566 <bitWidth>1</bitWidth>
26567 </field>
26568 <field>
26569 <name>SLEEP</name>
26570 <description>SLEEP</description>
26571 <bitOffset>1</bitOffset>
26572 <bitWidth>1</bitWidth>
26573 </field>
26574 <field>
26575 <name>INRQ</name>
26576 <description>INRQ</description>
26577 <bitOffset>0</bitOffset>
26578 <bitWidth>1</bitWidth>
26579 </field>
26580 </fields>
26581 </register>
26582 <register>
26583 <name>MSR</name>
26584 <displayName>MSR</displayName>
26585 <description>master status register</description>
26586 <addressOffset>0x4</addressOffset>
26587 <size>0x20</size>
26588 <resetValue>0x00000C02</resetValue>
26589 <fields>
26590 <field>
26591 <name>RX</name>
26592 <description>RX</description>
26593 <bitOffset>11</bitOffset>
26594 <bitWidth>1</bitWidth>
26595 <access>read-only</access>
26596 </field>
26597 <field>
26598 <name>SAMP</name>
26599 <description>SAMP</description>
26600 <bitOffset>10</bitOffset>
26601 <bitWidth>1</bitWidth>
26602 <access>read-only</access>
26603 </field>
26604 <field>
26605 <name>RXM</name>
26606 <description>RXM</description>
26607 <bitOffset>9</bitOffset>
26608 <bitWidth>1</bitWidth>
26609 <access>read-only</access>
26610 </field>
26611 <field>
26612 <name>TXM</name>
26613 <description>TXM</description>
26614 <bitOffset>8</bitOffset>
26615 <bitWidth>1</bitWidth>
26616 <access>read-only</access>
26617 </field>
26618 <field>
26619 <name>SLAKI</name>
26620 <description>SLAKI</description>
26621 <bitOffset>4</bitOffset>
26622 <bitWidth>1</bitWidth>
26623 <access>read-write</access>
26624 </field>
26625 <field>
26626 <name>WKUI</name>
26627 <description>WKUI</description>
26628 <bitOffset>3</bitOffset>
26629 <bitWidth>1</bitWidth>
26630 <access>read-write</access>
26631 </field>
26632 <field>
26633 <name>ERRI</name>
26634 <description>ERRI</description>
26635 <bitOffset>2</bitOffset>
26636 <bitWidth>1</bitWidth>
26637 <access>read-write</access>
26638 </field>
26639 <field>
26640 <name>SLAK</name>
26641 <description>SLAK</description>
26642 <bitOffset>1</bitOffset>
26643 <bitWidth>1</bitWidth>
26644 <access>read-only</access>
26645 </field>
26646 <field>
26647 <name>INAK</name>
26648 <description>INAK</description>
26649 <bitOffset>0</bitOffset>
26650 <bitWidth>1</bitWidth>
26651 <access>read-only</access>
26652 </field>
26653 </fields>
26654 </register>
26655 <register>
26656 <name>TSR</name>
26657 <displayName>TSR</displayName>
26658 <description>transmit status register</description>
26659 <addressOffset>0x8</addressOffset>
26660 <size>0x20</size>
26661 <resetValue>0x1C000000</resetValue>
26662 <fields>
26663 <field>
26664 <name>LOW2</name>
26665 <description>Lowest priority flag for mailbox
26666 2</description>
26667 <bitOffset>31</bitOffset>
26668 <bitWidth>1</bitWidth>
26669 <access>read-only</access>
26670 </field>
26671 <field>
26672 <name>LOW1</name>
26673 <description>Lowest priority flag for mailbox
26674 1</description>
26675 <bitOffset>30</bitOffset>
26676 <bitWidth>1</bitWidth>
26677 <access>read-only</access>
26678 </field>
26679 <field>
26680 <name>LOW0</name>
26681 <description>Lowest priority flag for mailbox
26682 0</description>
26683 <bitOffset>29</bitOffset>
26684 <bitWidth>1</bitWidth>
26685 <access>read-only</access>
26686 </field>
26687 <field>
26688 <name>TME2</name>
26689 <description>Lowest priority flag for mailbox
26690 2</description>
26691 <bitOffset>28</bitOffset>
26692 <bitWidth>1</bitWidth>
26693 <access>read-only</access>
26694 </field>
26695 <field>
26696 <name>TME1</name>
26697 <description>Lowest priority flag for mailbox
26698 1</description>
26699 <bitOffset>27</bitOffset>
26700 <bitWidth>1</bitWidth>
26701 <access>read-only</access>
26702 </field>
26703 <field>
26704 <name>TME0</name>
26705 <description>Lowest priority flag for mailbox
26706 0</description>
26707 <bitOffset>26</bitOffset>
26708 <bitWidth>1</bitWidth>
26709 <access>read-only</access>
26710 </field>
26711 <field>
26712 <name>CODE</name>
26713 <description>CODE</description>
26714 <bitOffset>24</bitOffset>
26715 <bitWidth>2</bitWidth>
26716 <access>read-only</access>
26717 </field>
26718 <field>
26719 <name>ABRQ2</name>
26720 <description>ABRQ2</description>
26721 <bitOffset>23</bitOffset>
26722 <bitWidth>1</bitWidth>
26723 <access>read-write</access>
26724 </field>
26725 <field>
26726 <name>TERR2</name>
26727 <description>TERR2</description>
26728 <bitOffset>19</bitOffset>
26729 <bitWidth>1</bitWidth>
26730 <access>read-write</access>
26731 </field>
26732 <field>
26733 <name>ALST2</name>
26734 <description>ALST2</description>
26735 <bitOffset>18</bitOffset>
26736 <bitWidth>1</bitWidth>
26737 <access>read-write</access>
26738 </field>
26739 <field>
26740 <name>TXOK2</name>
26741 <description>TXOK2</description>
26742 <bitOffset>17</bitOffset>
26743 <bitWidth>1</bitWidth>
26744 <access>read-write</access>
26745 </field>
26746 <field>
26747 <name>RQCP2</name>
26748 <description>RQCP2</description>
26749 <bitOffset>16</bitOffset>
26750 <bitWidth>1</bitWidth>
26751 <access>read-write</access>
26752 </field>
26753 <field>
26754 <name>ABRQ1</name>
26755 <description>ABRQ1</description>
26756 <bitOffset>15</bitOffset>
26757 <bitWidth>1</bitWidth>
26758 <access>read-write</access>
26759 </field>
26760 <field>
26761 <name>TERR1</name>
26762 <description>TERR1</description>
26763 <bitOffset>11</bitOffset>
26764 <bitWidth>1</bitWidth>
26765 <access>read-write</access>
26766 </field>
26767 <field>
26768 <name>ALST1</name>
26769 <description>ALST1</description>
26770 <bitOffset>10</bitOffset>
26771 <bitWidth>1</bitWidth>
26772 <access>read-write</access>
26773 </field>
26774 <field>
26775 <name>TXOK1</name>
26776 <description>TXOK1</description>
26777 <bitOffset>9</bitOffset>
26778 <bitWidth>1</bitWidth>
26779 <access>read-write</access>
26780 </field>
26781 <field>
26782 <name>RQCP1</name>
26783 <description>RQCP1</description>
26784 <bitOffset>8</bitOffset>
26785 <bitWidth>1</bitWidth>
26786 <access>read-write</access>
26787 </field>
26788 <field>
26789 <name>ABRQ0</name>
26790 <description>ABRQ0</description>
26791 <bitOffset>7</bitOffset>
26792 <bitWidth>1</bitWidth>
26793 <access>read-write</access>
26794 </field>
26795 <field>
26796 <name>TERR0</name>
26797 <description>TERR0</description>
26798 <bitOffset>3</bitOffset>
26799 <bitWidth>1</bitWidth>
26800 <access>read-write</access>
26801 </field>
26802 <field>
26803 <name>ALST0</name>
26804 <description>ALST0</description>
26805 <bitOffset>2</bitOffset>
26806 <bitWidth>1</bitWidth>
26807 <access>read-write</access>
26808 </field>
26809 <field>
26810 <name>TXOK0</name>
26811 <description>TXOK0</description>
26812 <bitOffset>1</bitOffset>
26813 <bitWidth>1</bitWidth>
26814 <access>read-write</access>
26815 </field>
26816 <field>
26817 <name>RQCP0</name>
26818 <description>RQCP0</description>
26819 <bitOffset>0</bitOffset>
26820 <bitWidth>1</bitWidth>
26821 <access>read-write</access>
26822 </field>
26823 </fields>
26824 </register>
26825 <register>
26826 <name>RF0R</name>
26827 <displayName>RF0R</displayName>
26828 <description>receive FIFO 0 register</description>
26829 <addressOffset>0xC</addressOffset>
26830 <size>0x20</size>
26831 <resetValue>0x00000000</resetValue>
26832 <fields>
26833 <field>
26834 <name>RFOM0</name>
26835 <description>RFOM0</description>
26836 <bitOffset>5</bitOffset>
26837 <bitWidth>1</bitWidth>
26838 <access>read-write</access>
26839 </field>
26840 <field>
26841 <name>FOVR0</name>
26842 <description>FOVR0</description>
26843 <bitOffset>4</bitOffset>
26844 <bitWidth>1</bitWidth>
26845 <access>read-write</access>
26846 </field>
26847 <field>
26848 <name>FULL0</name>
26849 <description>FULL0</description>
26850 <bitOffset>3</bitOffset>
26851 <bitWidth>1</bitWidth>
26852 <access>read-write</access>
26853 </field>
26854 <field>
26855 <name>FMP0</name>
26856 <description>FMP0</description>
26857 <bitOffset>0</bitOffset>
26858 <bitWidth>2</bitWidth>
26859 <access>read-only</access>
26860 </field>
26861 </fields>
26862 </register>
26863 <register>
26864 <name>RF1R</name>
26865 <displayName>RF1R</displayName>
26866 <description>receive FIFO 1 register</description>
26867 <addressOffset>0x10</addressOffset>
26868 <size>0x20</size>
26869 <resetValue>0x00000000</resetValue>
26870 <fields>
26871 <field>
26872 <name>RFOM1</name>
26873 <description>RFOM1</description>
26874 <bitOffset>5</bitOffset>
26875 <bitWidth>1</bitWidth>
26876 <access>read-write</access>
26877 </field>
26878 <field>
26879 <name>FOVR1</name>
26880 <description>FOVR1</description>
26881 <bitOffset>4</bitOffset>
26882 <bitWidth>1</bitWidth>
26883 <access>read-write</access>
26884 </field>
26885 <field>
26886 <name>FULL1</name>
26887 <description>FULL1</description>
26888 <bitOffset>3</bitOffset>
26889 <bitWidth>1</bitWidth>
26890 <access>read-write</access>
26891 </field>
26892 <field>
26893 <name>FMP1</name>
26894 <description>FMP1</description>
26895 <bitOffset>0</bitOffset>
26896 <bitWidth>2</bitWidth>
26897 <access>read-only</access>
26898 </field>
26899 </fields>
26900 </register>
26901 <register>
26902 <name>IER</name>
26903 <displayName>IER</displayName>
26904 <description>interrupt enable register</description>
26905 <addressOffset>0x14</addressOffset>
26906 <size>0x20</size>
26907 <access>read-write</access>
26908 <resetValue>0x00000000</resetValue>
26909 <fields>
26910 <field>
26911 <name>SLKIE</name>
26912 <description>SLKIE</description>
26913 <bitOffset>17</bitOffset>
26914 <bitWidth>1</bitWidth>
26915 </field>
26916 <field>
26917 <name>WKUIE</name>
26918 <description>WKUIE</description>
26919 <bitOffset>16</bitOffset>
26920 <bitWidth>1</bitWidth>
26921 </field>
26922 <field>
26923 <name>ERRIE</name>
26924 <description>ERRIE</description>
26925 <bitOffset>15</bitOffset>
26926 <bitWidth>1</bitWidth>
26927 </field>
26928 <field>
26929 <name>LECIE</name>
26930 <description>LECIE</description>
26931 <bitOffset>11</bitOffset>
26932 <bitWidth>1</bitWidth>
26933 </field>
26934 <field>
26935 <name>BOFIE</name>
26936 <description>BOFIE</description>
26937 <bitOffset>10</bitOffset>
26938 <bitWidth>1</bitWidth>
26939 </field>
26940 <field>
26941 <name>EPVIE</name>
26942 <description>EPVIE</description>
26943 <bitOffset>9</bitOffset>
26944 <bitWidth>1</bitWidth>
26945 </field>
26946 <field>
26947 <name>EWGIE</name>
26948 <description>EWGIE</description>
26949 <bitOffset>8</bitOffset>
26950 <bitWidth>1</bitWidth>
26951 </field>
26952 <field>
26953 <name>FOVIE1</name>
26954 <description>FOVIE1</description>
26955 <bitOffset>6</bitOffset>
26956 <bitWidth>1</bitWidth>
26957 </field>
26958 <field>
26959 <name>FFIE1</name>
26960 <description>FFIE1</description>
26961 <bitOffset>5</bitOffset>
26962 <bitWidth>1</bitWidth>
26963 </field>
26964 <field>
26965 <name>FMPIE1</name>
26966 <description>FMPIE1</description>
26967 <bitOffset>4</bitOffset>
26968 <bitWidth>1</bitWidth>
26969 </field>
26970 <field>
26971 <name>FOVIE0</name>
26972 <description>FOVIE0</description>
26973 <bitOffset>3</bitOffset>
26974 <bitWidth>1</bitWidth>
26975 </field>
26976 <field>
26977 <name>FFIE0</name>
26978 <description>FFIE0</description>
26979 <bitOffset>2</bitOffset>
26980 <bitWidth>1</bitWidth>
26981 </field>
26982 <field>
26983 <name>FMPIE0</name>
26984 <description>FMPIE0</description>
26985 <bitOffset>1</bitOffset>
26986 <bitWidth>1</bitWidth>
26987 </field>
26988 <field>
26989 <name>TMEIE</name>
26990 <description>TMEIE</description>
26991 <bitOffset>0</bitOffset>
26992 <bitWidth>1</bitWidth>
26993 </field>
26994 </fields>
26995 </register>
26996 <register>
26997 <name>ESR</name>
26998 <displayName>ESR</displayName>
26999 <description>interrupt enable register</description>
27000 <addressOffset>0x18</addressOffset>
27001 <size>0x20</size>
27002 <resetValue>0x00000000</resetValue>
27003 <fields>
27004 <field>
27005 <name>REC</name>
27006 <description>REC</description>
27007 <bitOffset>24</bitOffset>
27008 <bitWidth>8</bitWidth>
27009 <access>read-only</access>
27010 </field>
27011 <field>
27012 <name>TEC</name>
27013 <description>TEC</description>
27014 <bitOffset>16</bitOffset>
27015 <bitWidth>8</bitWidth>
27016 <access>read-only</access>
27017 </field>
27018 <field>
27019 <name>LEC</name>
27020 <description>LEC</description>
27021 <bitOffset>4</bitOffset>
27022 <bitWidth>3</bitWidth>
27023 <access>read-write</access>
27024 </field>
27025 <field>
27026 <name>BOFF</name>
27027 <description>BOFF</description>
27028 <bitOffset>2</bitOffset>
27029 <bitWidth>1</bitWidth>
27030 <access>read-only</access>
27031 </field>
27032 <field>
27033 <name>EPVF</name>
27034 <description>EPVF</description>
27035 <bitOffset>1</bitOffset>
27036 <bitWidth>1</bitWidth>
27037 <access>read-only</access>
27038 </field>
27039 <field>
27040 <name>EWGF</name>
27041 <description>EWGF</description>
27042 <bitOffset>0</bitOffset>
27043 <bitWidth>1</bitWidth>
27044 <access>read-only</access>
27045 </field>
27046 </fields>
27047 </register>
27048 <register>
27049 <name>BTR</name>
27050 <displayName>BTR</displayName>
27051 <description>bit timing register</description>
27052 <addressOffset>0x1C</addressOffset>
27053 <size>0x20</size>
27054 <access>read-write</access>
27055 <resetValue>0x00000000</resetValue>
27056 <fields>
27057 <field>
27058 <name>SILM</name>
27059 <description>SILM</description>
27060 <bitOffset>31</bitOffset>
27061 <bitWidth>1</bitWidth>
27062 </field>
27063 <field>
27064 <name>LBKM</name>
27065 <description>LBKM</description>
27066 <bitOffset>30</bitOffset>
27067 <bitWidth>1</bitWidth>
27068 </field>
27069 <field>
27070 <name>SJW</name>
27071 <description>SJW</description>
27072 <bitOffset>24</bitOffset>
27073 <bitWidth>2</bitWidth>
27074 </field>
27075 <field>
27076 <name>TS2</name>
27077 <description>TS2</description>
27078 <bitOffset>20</bitOffset>
27079 <bitWidth>3</bitWidth>
27080 </field>
27081 <field>
27082 <name>TS1</name>
27083 <description>TS1</description>
27084 <bitOffset>16</bitOffset>
27085 <bitWidth>4</bitWidth>
27086 </field>
27087 <field>
27088 <name>BRP</name>
27089 <description>BRP</description>
27090 <bitOffset>0</bitOffset>
27091 <bitWidth>10</bitWidth>
27092 </field>
27093 </fields>
27094 </register>
27095 <register>
27096 <name>TI0R</name>
27097 <displayName>TI0R</displayName>
27098 <description>TX mailbox identifier register</description>
27099 <addressOffset>0x180</addressOffset>
27100 <size>0x20</size>
27101 <access>read-write</access>
27102 <resetValue>0x00000000</resetValue>
27103 <fields>
27104 <field>
27105 <name>STID</name>
27106 <description>STID</description>
27107 <bitOffset>21</bitOffset>
27108 <bitWidth>11</bitWidth>
27109 </field>
27110 <field>
27111 <name>EXID</name>
27112 <description>EXID</description>
27113 <bitOffset>3</bitOffset>
27114 <bitWidth>18</bitWidth>
27115 </field>
27116 <field>
27117 <name>IDE</name>
27118 <description>IDE</description>
27119 <bitOffset>2</bitOffset>
27120 <bitWidth>1</bitWidth>
27121 </field>
27122 <field>
27123 <name>RTR</name>
27124 <description>RTR</description>
27125 <bitOffset>1</bitOffset>
27126 <bitWidth>1</bitWidth>
27127 </field>
27128 <field>
27129 <name>TXRQ</name>
27130 <description>TXRQ</description>
27131 <bitOffset>0</bitOffset>
27132 <bitWidth>1</bitWidth>
27133 </field>
27134 </fields>
27135 </register>
27136 <register>
27137 <name>TDT0R</name>
27138 <displayName>TDT0R</displayName>
27139 <description>mailbox data length control and time stamp
27140 register</description>
27141 <addressOffset>0x184</addressOffset>
27142 <size>0x20</size>
27143 <access>read-write</access>
27144 <resetValue>0x00000000</resetValue>
27145 <fields>
27146 <field>
27147 <name>TIME</name>
27148 <description>TIME</description>
27149 <bitOffset>16</bitOffset>
27150 <bitWidth>16</bitWidth>
27151 </field>
27152 <field>
27153 <name>TGT</name>
27154 <description>TGT</description>
27155 <bitOffset>8</bitOffset>
27156 <bitWidth>1</bitWidth>
27157 </field>
27158 <field>
27159 <name>DLC</name>
27160 <description>DLC</description>
27161 <bitOffset>0</bitOffset>
27162 <bitWidth>4</bitWidth>
27163 </field>
27164 </fields>
27165 </register>
27166 <register>
27167 <name>TDL0R</name>
27168 <displayName>TDL0R</displayName>
27169 <description>mailbox data low register</description>
27170 <addressOffset>0x188</addressOffset>
27171 <size>0x20</size>
27172 <access>read-write</access>
27173 <resetValue>0x00000000</resetValue>
27174 <fields>
27175 <field>
27176 <name>DATA3</name>
27177 <description>DATA3</description>
27178 <bitOffset>24</bitOffset>
27179 <bitWidth>8</bitWidth>
27180 </field>
27181 <field>
27182 <name>DATA2</name>
27183 <description>DATA2</description>
27184 <bitOffset>16</bitOffset>
27185 <bitWidth>8</bitWidth>
27186 </field>
27187 <field>
27188 <name>DATA1</name>
27189 <description>DATA1</description>
27190 <bitOffset>8</bitOffset>
27191 <bitWidth>8</bitWidth>
27192 </field>
27193 <field>
27194 <name>DATA0</name>
27195 <description>DATA0</description>
27196 <bitOffset>0</bitOffset>
27197 <bitWidth>8</bitWidth>
27198 </field>
27199 </fields>
27200 </register>
27201 <register>
27202 <name>TDH0R</name>
27203 <displayName>TDH0R</displayName>
27204 <description>mailbox data high register</description>
27205 <addressOffset>0x18C</addressOffset>
27206 <size>0x20</size>
27207 <access>read-write</access>
27208 <resetValue>0x00000000</resetValue>
27209 <fields>
27210 <field>
27211 <name>DATA7</name>
27212 <description>DATA7</description>
27213 <bitOffset>24</bitOffset>
27214 <bitWidth>8</bitWidth>
27215 </field>
27216 <field>
27217 <name>DATA6</name>
27218 <description>DATA6</description>
27219 <bitOffset>16</bitOffset>
27220 <bitWidth>8</bitWidth>
27221 </field>
27222 <field>
27223 <name>DATA5</name>
27224 <description>DATA5</description>
27225 <bitOffset>8</bitOffset>
27226 <bitWidth>8</bitWidth>
27227 </field>
27228 <field>
27229 <name>DATA4</name>
27230 <description>DATA4</description>
27231 <bitOffset>0</bitOffset>
27232 <bitWidth>8</bitWidth>
27233 </field>
27234 </fields>
27235 </register>
27236 <register>
27237 <name>TI1R</name>
27238 <displayName>TI1R</displayName>
27239 <description>mailbox identifier register</description>
27240 <addressOffset>0x190</addressOffset>
27241 <size>0x20</size>
27242 <access>read-write</access>
27243 <resetValue>0x00000000</resetValue>
27244 <fields>
27245 <field>
27246 <name>STID</name>
27247 <description>STID</description>
27248 <bitOffset>21</bitOffset>
27249 <bitWidth>11</bitWidth>
27250 </field>
27251 <field>
27252 <name>EXID</name>
27253 <description>EXID</description>
27254 <bitOffset>3</bitOffset>
27255 <bitWidth>18</bitWidth>
27256 </field>
27257 <field>
27258 <name>IDE</name>
27259 <description>IDE</description>
27260 <bitOffset>2</bitOffset>
27261 <bitWidth>1</bitWidth>
27262 </field>
27263 <field>
27264 <name>RTR</name>
27265 <description>RTR</description>
27266 <bitOffset>1</bitOffset>
27267 <bitWidth>1</bitWidth>
27268 </field>
27269 <field>
27270 <name>TXRQ</name>
27271 <description>TXRQ</description>
27272 <bitOffset>0</bitOffset>
27273 <bitWidth>1</bitWidth>
27274 </field>
27275 </fields>
27276 </register>
27277 <register>
27278 <name>TDT1R</name>
27279 <displayName>TDT1R</displayName>
27280 <description>mailbox data length control and time stamp
27281 register</description>
27282 <addressOffset>0x194</addressOffset>
27283 <size>0x20</size>
27284 <access>read-write</access>
27285 <resetValue>0x00000000</resetValue>
27286 <fields>
27287 <field>
27288 <name>TIME</name>
27289 <description>TIME</description>
27290 <bitOffset>16</bitOffset>
27291 <bitWidth>16</bitWidth>
27292 </field>
27293 <field>
27294 <name>TGT</name>
27295 <description>TGT</description>
27296 <bitOffset>8</bitOffset>
27297 <bitWidth>1</bitWidth>
27298 </field>
27299 <field>
27300 <name>DLC</name>
27301 <description>DLC</description>
27302 <bitOffset>0</bitOffset>
27303 <bitWidth>4</bitWidth>
27304 </field>
27305 </fields>
27306 </register>
27307 <register>
27308 <name>TDL1R</name>
27309 <displayName>TDL1R</displayName>
27310 <description>mailbox data low register</description>
27311 <addressOffset>0x198</addressOffset>
27312 <size>0x20</size>
27313 <access>read-write</access>
27314 <resetValue>0x00000000</resetValue>
27315 <fields>
27316 <field>
27317 <name>DATA3</name>
27318 <description>DATA3</description>
27319 <bitOffset>24</bitOffset>
27320 <bitWidth>8</bitWidth>
27321 </field>
27322 <field>
27323 <name>DATA2</name>
27324 <description>DATA2</description>
27325 <bitOffset>16</bitOffset>
27326 <bitWidth>8</bitWidth>
27327 </field>
27328 <field>
27329 <name>DATA1</name>
27330 <description>DATA1</description>
27331 <bitOffset>8</bitOffset>
27332 <bitWidth>8</bitWidth>
27333 </field>
27334 <field>
27335 <name>DATA0</name>
27336 <description>DATA0</description>
27337 <bitOffset>0</bitOffset>
27338 <bitWidth>8</bitWidth>
27339 </field>
27340 </fields>
27341 </register>
27342 <register>
27343 <name>TDH1R</name>
27344 <displayName>TDH1R</displayName>
27345 <description>mailbox data high register</description>
27346 <addressOffset>0x19C</addressOffset>
27347 <size>0x20</size>
27348 <access>read-write</access>
27349 <resetValue>0x00000000</resetValue>
27350 <fields>
27351 <field>
27352 <name>DATA7</name>
27353 <description>DATA7</description>
27354 <bitOffset>24</bitOffset>
27355 <bitWidth>8</bitWidth>
27356 </field>
27357 <field>
27358 <name>DATA6</name>
27359 <description>DATA6</description>
27360 <bitOffset>16</bitOffset>
27361 <bitWidth>8</bitWidth>
27362 </field>
27363 <field>
27364 <name>DATA5</name>
27365 <description>DATA5</description>
27366 <bitOffset>8</bitOffset>
27367 <bitWidth>8</bitWidth>
27368 </field>
27369 <field>
27370 <name>DATA4</name>
27371 <description>DATA4</description>
27372 <bitOffset>0</bitOffset>
27373 <bitWidth>8</bitWidth>
27374 </field>
27375 </fields>
27376 </register>
27377 <register>
27378 <name>TI2R</name>
27379 <displayName>TI2R</displayName>
27380 <description>mailbox identifier register</description>
27381 <addressOffset>0x1A0</addressOffset>
27382 <size>0x20</size>
27383 <access>read-write</access>
27384 <resetValue>0x00000000</resetValue>
27385 <fields>
27386 <field>
27387 <name>STID</name>
27388 <description>STID</description>
27389 <bitOffset>21</bitOffset>
27390 <bitWidth>11</bitWidth>
27391 </field>
27392 <field>
27393 <name>EXID</name>
27394 <description>EXID</description>
27395 <bitOffset>3</bitOffset>
27396 <bitWidth>18</bitWidth>
27397 </field>
27398 <field>
27399 <name>IDE</name>
27400 <description>IDE</description>
27401 <bitOffset>2</bitOffset>
27402 <bitWidth>1</bitWidth>
27403 </field>
27404 <field>
27405 <name>RTR</name>
27406 <description>RTR</description>
27407 <bitOffset>1</bitOffset>
27408 <bitWidth>1</bitWidth>
27409 </field>
27410 <field>
27411 <name>TXRQ</name>
27412 <description>TXRQ</description>
27413 <bitOffset>0</bitOffset>
27414 <bitWidth>1</bitWidth>
27415 </field>
27416 </fields>
27417 </register>
27418 <register>
27419 <name>TDT2R</name>
27420 <displayName>TDT2R</displayName>
27421 <description>mailbox data length control and time stamp
27422 register</description>
27423 <addressOffset>0x1A4</addressOffset>
27424 <size>0x20</size>
27425 <access>read-write</access>
27426 <resetValue>0x00000000</resetValue>
27427 <fields>
27428 <field>
27429 <name>TIME</name>
27430 <description>TIME</description>
27431 <bitOffset>16</bitOffset>
27432 <bitWidth>16</bitWidth>
27433 </field>
27434 <field>
27435 <name>TGT</name>
27436 <description>TGT</description>
27437 <bitOffset>8</bitOffset>
27438 <bitWidth>1</bitWidth>
27439 </field>
27440 <field>
27441 <name>DLC</name>
27442 <description>DLC</description>
27443 <bitOffset>0</bitOffset>
27444 <bitWidth>4</bitWidth>
27445 </field>
27446 </fields>
27447 </register>
27448 <register>
27449 <name>TDL2R</name>
27450 <displayName>TDL2R</displayName>
27451 <description>mailbox data low register</description>
27452 <addressOffset>0x1A8</addressOffset>
27453 <size>0x20</size>
27454 <access>read-write</access>
27455 <resetValue>0x00000000</resetValue>
27456 <fields>
27457 <field>
27458 <name>DATA3</name>
27459 <description>DATA3</description>
27460 <bitOffset>24</bitOffset>
27461 <bitWidth>8</bitWidth>
27462 </field>
27463 <field>
27464 <name>DATA2</name>
27465 <description>DATA2</description>
27466 <bitOffset>16</bitOffset>
27467 <bitWidth>8</bitWidth>
27468 </field>
27469 <field>
27470 <name>DATA1</name>
27471 <description>DATA1</description>
27472 <bitOffset>8</bitOffset>
27473 <bitWidth>8</bitWidth>
27474 </field>
27475 <field>
27476 <name>DATA0</name>
27477 <description>DATA0</description>
27478 <bitOffset>0</bitOffset>
27479 <bitWidth>8</bitWidth>
27480 </field>
27481 </fields>
27482 </register>
27483 <register>
27484 <name>TDH2R</name>
27485 <displayName>TDH2R</displayName>
27486 <description>mailbox data high register</description>
27487 <addressOffset>0x1AC</addressOffset>
27488 <size>0x20</size>
27489 <access>read-write</access>
27490 <resetValue>0x00000000</resetValue>
27491 <fields>
27492 <field>
27493 <name>DATA7</name>
27494 <description>DATA7</description>
27495 <bitOffset>24</bitOffset>
27496 <bitWidth>8</bitWidth>
27497 </field>
27498 <field>
27499 <name>DATA6</name>
27500 <description>DATA6</description>
27501 <bitOffset>16</bitOffset>
27502 <bitWidth>8</bitWidth>
27503 </field>
27504 <field>
27505 <name>DATA5</name>
27506 <description>DATA5</description>
27507 <bitOffset>8</bitOffset>
27508 <bitWidth>8</bitWidth>
27509 </field>
27510 <field>
27511 <name>DATA4</name>
27512 <description>DATA4</description>
27513 <bitOffset>0</bitOffset>
27514 <bitWidth>8</bitWidth>
27515 </field>
27516 </fields>
27517 </register>
27518 <register>
27519 <name>RI0R</name>
27520 <displayName>RI0R</displayName>
27521 <description>receive FIFO mailbox identifier
27522 register</description>
27523 <addressOffset>0x1B0</addressOffset>
27524 <size>0x20</size>
27525 <access>read-only</access>
27526 <resetValue>0x00000000</resetValue>
27527 <fields>
27528 <field>
27529 <name>STID</name>
27530 <description>STID</description>
27531 <bitOffset>21</bitOffset>
27532 <bitWidth>11</bitWidth>
27533 </field>
27534 <field>
27535 <name>EXID</name>
27536 <description>EXID</description>
27537 <bitOffset>3</bitOffset>
27538 <bitWidth>18</bitWidth>
27539 </field>
27540 <field>
27541 <name>IDE</name>
27542 <description>IDE</description>
27543 <bitOffset>2</bitOffset>
27544 <bitWidth>1</bitWidth>
27545 </field>
27546 <field>
27547 <name>RTR</name>
27548 <description>RTR</description>
27549 <bitOffset>1</bitOffset>
27550 <bitWidth>1</bitWidth>
27551 </field>
27552 </fields>
27553 </register>
27554 <register>
27555 <name>RDT0R</name>
27556 <displayName>RDT0R</displayName>
27557 <description>mailbox data high register</description>
27558 <addressOffset>0x1B4</addressOffset>
27559 <size>0x20</size>
27560 <access>read-only</access>
27561 <resetValue>0x00000000</resetValue>
27562 <fields>
27563 <field>
27564 <name>TIME</name>
27565 <description>TIME</description>
27566 <bitOffset>16</bitOffset>
27567 <bitWidth>16</bitWidth>
27568 </field>
27569 <field>
27570 <name>FMI</name>
27571 <description>FMI</description>
27572 <bitOffset>8</bitOffset>
27573 <bitWidth>8</bitWidth>
27574 </field>
27575 <field>
27576 <name>DLC</name>
27577 <description>DLC</description>
27578 <bitOffset>0</bitOffset>
27579 <bitWidth>4</bitWidth>
27580 </field>
27581 </fields>
27582 </register>
27583 <register>
27584 <name>RDL0R</name>
27585 <displayName>RDL0R</displayName>
27586 <description>mailbox data high register</description>
27587 <addressOffset>0x1B8</addressOffset>
27588 <size>0x20</size>
27589 <access>read-only</access>
27590 <resetValue>0x00000000</resetValue>
27591 <fields>
27592 <field>
27593 <name>DATA3</name>
27594 <description>DATA3</description>
27595 <bitOffset>24</bitOffset>
27596 <bitWidth>8</bitWidth>
27597 </field>
27598 <field>
27599 <name>DATA2</name>
27600 <description>DATA2</description>
27601 <bitOffset>16</bitOffset>
27602 <bitWidth>8</bitWidth>
27603 </field>
27604 <field>
27605 <name>DATA1</name>
27606 <description>DATA1</description>
27607 <bitOffset>8</bitOffset>
27608 <bitWidth>8</bitWidth>
27609 </field>
27610 <field>
27611 <name>DATA0</name>
27612 <description>DATA0</description>
27613 <bitOffset>0</bitOffset>
27614 <bitWidth>8</bitWidth>
27615 </field>
27616 </fields>
27617 </register>
27618 <register>
27619 <name>RDH0R</name>
27620 <displayName>RDH0R</displayName>
27621 <description>receive FIFO mailbox data high
27622 register</description>
27623 <addressOffset>0x1BC</addressOffset>
27624 <size>0x20</size>
27625 <access>read-only</access>
27626 <resetValue>0x00000000</resetValue>
27627 <fields>
27628 <field>
27629 <name>DATA7</name>
27630 <description>DATA7</description>
27631 <bitOffset>24</bitOffset>
27632 <bitWidth>8</bitWidth>
27633 </field>
27634 <field>
27635 <name>DATA6</name>
27636 <description>DATA6</description>
27637 <bitOffset>16</bitOffset>
27638 <bitWidth>8</bitWidth>
27639 </field>
27640 <field>
27641 <name>DATA5</name>
27642 <description>DATA5</description>
27643 <bitOffset>8</bitOffset>
27644 <bitWidth>8</bitWidth>
27645 </field>
27646 <field>
27647 <name>DATA4</name>
27648 <description>DATA4</description>
27649 <bitOffset>0</bitOffset>
27650 <bitWidth>8</bitWidth>
27651 </field>
27652 </fields>
27653 </register>
27654 <register>
27655 <name>RI1R</name>
27656 <displayName>RI1R</displayName>
27657 <description>mailbox data high register</description>
27658 <addressOffset>0x1C0</addressOffset>
27659 <size>0x20</size>
27660 <access>read-only</access>
27661 <resetValue>0x00000000</resetValue>
27662 <fields>
27663 <field>
27664 <name>STID</name>
27665 <description>STID</description>
27666 <bitOffset>21</bitOffset>
27667 <bitWidth>11</bitWidth>
27668 </field>
27669 <field>
27670 <name>EXID</name>
27671 <description>EXID</description>
27672 <bitOffset>3</bitOffset>
27673 <bitWidth>18</bitWidth>
27674 </field>
27675 <field>
27676 <name>IDE</name>
27677 <description>IDE</description>
27678 <bitOffset>2</bitOffset>
27679 <bitWidth>1</bitWidth>
27680 </field>
27681 <field>
27682 <name>RTR</name>
27683 <description>RTR</description>
27684 <bitOffset>1</bitOffset>
27685 <bitWidth>1</bitWidth>
27686 </field>
27687 </fields>
27688 </register>
27689 <register>
27690 <name>RDT1R</name>
27691 <displayName>RDT1R</displayName>
27692 <description>mailbox data high register</description>
27693 <addressOffset>0x1C4</addressOffset>
27694 <size>0x20</size>
27695 <access>read-only</access>
27696 <resetValue>0x00000000</resetValue>
27697 <fields>
27698 <field>
27699 <name>TIME</name>
27700 <description>TIME</description>
27701 <bitOffset>16</bitOffset>
27702 <bitWidth>16</bitWidth>
27703 </field>
27704 <field>
27705 <name>FMI</name>
27706 <description>FMI</description>
27707 <bitOffset>8</bitOffset>
27708 <bitWidth>8</bitWidth>
27709 </field>
27710 <field>
27711 <name>DLC</name>
27712 <description>DLC</description>
27713 <bitOffset>0</bitOffset>
27714 <bitWidth>4</bitWidth>
27715 </field>
27716 </fields>
27717 </register>
27718 <register>
27719 <name>RDL1R</name>
27720 <displayName>RDL1R</displayName>
27721 <description>mailbox data high register</description>
27722 <addressOffset>0x1C8</addressOffset>
27723 <size>0x20</size>
27724 <access>read-only</access>
27725 <resetValue>0x00000000</resetValue>
27726 <fields>
27727 <field>
27728 <name>DATA3</name>
27729 <description>DATA3</description>
27730 <bitOffset>24</bitOffset>
27731 <bitWidth>8</bitWidth>
27732 </field>
27733 <field>
27734 <name>DATA2</name>
27735 <description>DATA2</description>
27736 <bitOffset>16</bitOffset>
27737 <bitWidth>8</bitWidth>
27738 </field>
27739 <field>
27740 <name>DATA1</name>
27741 <description>DATA1</description>
27742 <bitOffset>8</bitOffset>
27743 <bitWidth>8</bitWidth>
27744 </field>
27745 <field>
27746 <name>DATA0</name>
27747 <description>DATA0</description>
27748 <bitOffset>0</bitOffset>
27749 <bitWidth>8</bitWidth>
27750 </field>
27751 </fields>
27752 </register>
27753 <register>
27754 <name>RDH1R</name>
27755 <displayName>RDH1R</displayName>
27756 <description>mailbox data high register</description>
27757 <addressOffset>0x1CC</addressOffset>
27758 <size>0x20</size>
27759 <access>read-only</access>
27760 <resetValue>0x00000000</resetValue>
27761 <fields>
27762 <field>
27763 <name>DATA7</name>
27764 <description>DATA7</description>
27765 <bitOffset>24</bitOffset>
27766 <bitWidth>8</bitWidth>
27767 </field>
27768 <field>
27769 <name>DATA6</name>
27770 <description>DATA6</description>
27771 <bitOffset>16</bitOffset>
27772 <bitWidth>8</bitWidth>
27773 </field>
27774 <field>
27775 <name>DATA5</name>
27776 <description>DATA5</description>
27777 <bitOffset>8</bitOffset>
27778 <bitWidth>8</bitWidth>
27779 </field>
27780 <field>
27781 <name>DATA4</name>
27782 <description>DATA4</description>
27783 <bitOffset>0</bitOffset>
27784 <bitWidth>8</bitWidth>
27785 </field>
27786 </fields>
27787 </register>
27788 <register>
27789 <name>FMR</name>
27790 <displayName>FMR</displayName>
27791 <description>filter master register</description>
27792 <addressOffset>0x200</addressOffset>
27793 <size>0x20</size>
27794 <access>read-write</access>
27795 <resetValue>0x2A1C0E01</resetValue>
27796 <fields>
27797 <field>
27798 <name>CAN2SB</name>
27799 <description>CAN2SB</description>
27800 <bitOffset>8</bitOffset>
27801 <bitWidth>6</bitWidth>
27802 </field>
27803 <field>
27804 <name>FINIT</name>
27805 <description>FINIT</description>
27806 <bitOffset>0</bitOffset>
27807 <bitWidth>1</bitWidth>
27808 </field>
27809 </fields>
27810 </register>
27811 <register>
27812 <name>FM1R</name>
27813 <displayName>FM1R</displayName>
27814 <description>filter mode register</description>
27815 <addressOffset>0x204</addressOffset>
27816 <size>0x20</size>
27817 <access>read-write</access>
27818 <resetValue>0x00000000</resetValue>
27819 <fields>
27820 <field>
27821 <name>FBM0</name>
27822 <description>Filter mode</description>
27823 <bitOffset>0</bitOffset>
27824 <bitWidth>1</bitWidth>
27825 </field>
27826 <field>
27827 <name>FBM1</name>
27828 <description>Filter mode</description>
27829 <bitOffset>1</bitOffset>
27830 <bitWidth>1</bitWidth>
27831 </field>
27832 <field>
27833 <name>FBM2</name>
27834 <description>Filter mode</description>
27835 <bitOffset>2</bitOffset>
27836 <bitWidth>1</bitWidth>
27837 </field>
27838 <field>
27839 <name>FBM3</name>
27840 <description>Filter mode</description>
27841 <bitOffset>3</bitOffset>
27842 <bitWidth>1</bitWidth>
27843 </field>
27844 <field>
27845 <name>FBM4</name>
27846 <description>Filter mode</description>
27847 <bitOffset>4</bitOffset>
27848 <bitWidth>1</bitWidth>
27849 </field>
27850 <field>
27851 <name>FBM5</name>
27852 <description>Filter mode</description>
27853 <bitOffset>5</bitOffset>
27854 <bitWidth>1</bitWidth>
27855 </field>
27856 <field>
27857 <name>FBM6</name>
27858 <description>Filter mode</description>
27859 <bitOffset>6</bitOffset>
27860 <bitWidth>1</bitWidth>
27861 </field>
27862 <field>
27863 <name>FBM7</name>
27864 <description>Filter mode</description>
27865 <bitOffset>7</bitOffset>
27866 <bitWidth>1</bitWidth>
27867 </field>
27868 <field>
27869 <name>FBM8</name>
27870 <description>Filter mode</description>
27871 <bitOffset>8</bitOffset>
27872 <bitWidth>1</bitWidth>
27873 </field>
27874 <field>
27875 <name>FBM9</name>
27876 <description>Filter mode</description>
27877 <bitOffset>9</bitOffset>
27878 <bitWidth>1</bitWidth>
27879 </field>
27880 <field>
27881 <name>FBM10</name>
27882 <description>Filter mode</description>
27883 <bitOffset>10</bitOffset>
27884 <bitWidth>1</bitWidth>
27885 </field>
27886 <field>
27887 <name>FBM11</name>
27888 <description>Filter mode</description>
27889 <bitOffset>11</bitOffset>
27890 <bitWidth>1</bitWidth>
27891 </field>
27892 <field>
27893 <name>FBM12</name>
27894 <description>Filter mode</description>
27895 <bitOffset>12</bitOffset>
27896 <bitWidth>1</bitWidth>
27897 </field>
27898 <field>
27899 <name>FBM13</name>
27900 <description>Filter mode</description>
27901 <bitOffset>13</bitOffset>
27902 <bitWidth>1</bitWidth>
27903 </field>
27904 <field>
27905 <name>FBM14</name>
27906 <description>Filter mode</description>
27907 <bitOffset>14</bitOffset>
27908 <bitWidth>1</bitWidth>
27909 </field>
27910 <field>
27911 <name>FBM15</name>
27912 <description>Filter mode</description>
27913 <bitOffset>15</bitOffset>
27914 <bitWidth>1</bitWidth>
27915 </field>
27916 <field>
27917 <name>FBM16</name>
27918 <description>Filter mode</description>
27919 <bitOffset>16</bitOffset>
27920 <bitWidth>1</bitWidth>
27921 </field>
27922 <field>
27923 <name>FBM17</name>
27924 <description>Filter mode</description>
27925 <bitOffset>17</bitOffset>
27926 <bitWidth>1</bitWidth>
27927 </field>
27928 <field>
27929 <name>FBM18</name>
27930 <description>Filter mode</description>
27931 <bitOffset>18</bitOffset>
27932 <bitWidth>1</bitWidth>
27933 </field>
27934 <field>
27935 <name>FBM19</name>
27936 <description>Filter mode</description>
27937 <bitOffset>19</bitOffset>
27938 <bitWidth>1</bitWidth>
27939 </field>
27940 <field>
27941 <name>FBM20</name>
27942 <description>Filter mode</description>
27943 <bitOffset>20</bitOffset>
27944 <bitWidth>1</bitWidth>
27945 </field>
27946 <field>
27947 <name>FBM21</name>
27948 <description>Filter mode</description>
27949 <bitOffset>21</bitOffset>
27950 <bitWidth>1</bitWidth>
27951 </field>
27952 <field>
27953 <name>FBM22</name>
27954 <description>Filter mode</description>
27955 <bitOffset>22</bitOffset>
27956 <bitWidth>1</bitWidth>
27957 </field>
27958 <field>
27959 <name>FBM23</name>
27960 <description>Filter mode</description>
27961 <bitOffset>23</bitOffset>
27962 <bitWidth>1</bitWidth>
27963 </field>
27964 <field>
27965 <name>FBM24</name>
27966 <description>Filter mode</description>
27967 <bitOffset>24</bitOffset>
27968 <bitWidth>1</bitWidth>
27969 </field>
27970 <field>
27971 <name>FBM25</name>
27972 <description>Filter mode</description>
27973 <bitOffset>25</bitOffset>
27974 <bitWidth>1</bitWidth>
27975 </field>
27976 <field>
27977 <name>FBM26</name>
27978 <description>Filter mode</description>
27979 <bitOffset>26</bitOffset>
27980 <bitWidth>1</bitWidth>
27981 </field>
27982 <field>
27983 <name>FBM27</name>
27984 <description>Filter mode</description>
27985 <bitOffset>27</bitOffset>
27986 <bitWidth>1</bitWidth>
27987 </field>
27988 </fields>
27989 </register>
27990 <register>
27991 <name>FS1R</name>
27992 <displayName>FS1R</displayName>
27993 <description>filter scale register</description>
27994 <addressOffset>0x20C</addressOffset>
27995 <size>0x20</size>
27996 <access>read-write</access>
27997 <resetValue>0x00000000</resetValue>
27998 <fields>
27999 <field>
28000 <name>FSC0</name>
28001 <description>Filter scale configuration</description>
28002 <bitOffset>0</bitOffset>
28003 <bitWidth>1</bitWidth>
28004 </field>
28005 <field>
28006 <name>FSC1</name>
28007 <description>Filter scale configuration</description>
28008 <bitOffset>1</bitOffset>
28009 <bitWidth>1</bitWidth>
28010 </field>
28011 <field>
28012 <name>FSC2</name>
28013 <description>Filter scale configuration</description>
28014 <bitOffset>2</bitOffset>
28015 <bitWidth>1</bitWidth>
28016 </field>
28017 <field>
28018 <name>FSC3</name>
28019 <description>Filter scale configuration</description>
28020 <bitOffset>3</bitOffset>
28021 <bitWidth>1</bitWidth>
28022 </field>
28023 <field>
28024 <name>FSC4</name>
28025 <description>Filter scale configuration</description>
28026 <bitOffset>4</bitOffset>
28027 <bitWidth>1</bitWidth>
28028 </field>
28029 <field>
28030 <name>FSC5</name>
28031 <description>Filter scale configuration</description>
28032 <bitOffset>5</bitOffset>
28033 <bitWidth>1</bitWidth>
28034 </field>
28035 <field>
28036 <name>FSC6</name>
28037 <description>Filter scale configuration</description>
28038 <bitOffset>6</bitOffset>
28039 <bitWidth>1</bitWidth>
28040 </field>
28041 <field>
28042 <name>FSC7</name>
28043 <description>Filter scale configuration</description>
28044 <bitOffset>7</bitOffset>
28045 <bitWidth>1</bitWidth>
28046 </field>
28047 <field>
28048 <name>FSC8</name>
28049 <description>Filter scale configuration</description>
28050 <bitOffset>8</bitOffset>
28051 <bitWidth>1</bitWidth>
28052 </field>
28053 <field>
28054 <name>FSC9</name>
28055 <description>Filter scale configuration</description>
28056 <bitOffset>9</bitOffset>
28057 <bitWidth>1</bitWidth>
28058 </field>
28059 <field>
28060 <name>FSC10</name>
28061 <description>Filter scale configuration</description>
28062 <bitOffset>10</bitOffset>
28063 <bitWidth>1</bitWidth>
28064 </field>
28065 <field>
28066 <name>FSC11</name>
28067 <description>Filter scale configuration</description>
28068 <bitOffset>11</bitOffset>
28069 <bitWidth>1</bitWidth>
28070 </field>
28071 <field>
28072 <name>FSC12</name>
28073 <description>Filter scale configuration</description>
28074 <bitOffset>12</bitOffset>
28075 <bitWidth>1</bitWidth>
28076 </field>
28077 <field>
28078 <name>FSC13</name>
28079 <description>Filter scale configuration</description>
28080 <bitOffset>13</bitOffset>
28081 <bitWidth>1</bitWidth>
28082 </field>
28083 <field>
28084 <name>FSC14</name>
28085 <description>Filter scale configuration</description>
28086 <bitOffset>14</bitOffset>
28087 <bitWidth>1</bitWidth>
28088 </field>
28089 <field>
28090 <name>FSC15</name>
28091 <description>Filter scale configuration</description>
28092 <bitOffset>15</bitOffset>
28093 <bitWidth>1</bitWidth>
28094 </field>
28095 <field>
28096 <name>FSC16</name>
28097 <description>Filter scale configuration</description>
28098 <bitOffset>16</bitOffset>
28099 <bitWidth>1</bitWidth>
28100 </field>
28101 <field>
28102 <name>FSC17</name>
28103 <description>Filter scale configuration</description>
28104 <bitOffset>17</bitOffset>
28105 <bitWidth>1</bitWidth>
28106 </field>
28107 <field>
28108 <name>FSC18</name>
28109 <description>Filter scale configuration</description>
28110 <bitOffset>18</bitOffset>
28111 <bitWidth>1</bitWidth>
28112 </field>
28113 <field>
28114 <name>FSC19</name>
28115 <description>Filter scale configuration</description>
28116 <bitOffset>19</bitOffset>
28117 <bitWidth>1</bitWidth>
28118 </field>
28119 <field>
28120 <name>FSC20</name>
28121 <description>Filter scale configuration</description>
28122 <bitOffset>20</bitOffset>
28123 <bitWidth>1</bitWidth>
28124 </field>
28125 <field>
28126 <name>FSC21</name>
28127 <description>Filter scale configuration</description>
28128 <bitOffset>21</bitOffset>
28129 <bitWidth>1</bitWidth>
28130 </field>
28131 <field>
28132 <name>FSC22</name>
28133 <description>Filter scale configuration</description>
28134 <bitOffset>22</bitOffset>
28135 <bitWidth>1</bitWidth>
28136 </field>
28137 <field>
28138 <name>FSC23</name>
28139 <description>Filter scale configuration</description>
28140 <bitOffset>23</bitOffset>
28141 <bitWidth>1</bitWidth>
28142 </field>
28143 <field>
28144 <name>FSC24</name>
28145 <description>Filter scale configuration</description>
28146 <bitOffset>24</bitOffset>
28147 <bitWidth>1</bitWidth>
28148 </field>
28149 <field>
28150 <name>FSC25</name>
28151 <description>Filter scale configuration</description>
28152 <bitOffset>25</bitOffset>
28153 <bitWidth>1</bitWidth>
28154 </field>
28155 <field>
28156 <name>FSC26</name>
28157 <description>Filter scale configuration</description>
28158 <bitOffset>26</bitOffset>
28159 <bitWidth>1</bitWidth>
28160 </field>
28161 <field>
28162 <name>FSC27</name>
28163 <description>Filter scale configuration</description>
28164 <bitOffset>27</bitOffset>
28165 <bitWidth>1</bitWidth>
28166 </field>
28167 </fields>
28168 </register>
28169 <register>
28170 <name>FFA1R</name>
28171 <displayName>FFA1R</displayName>
28172 <description>filter FIFO assignment
28173 register</description>
28174 <addressOffset>0x214</addressOffset>
28175 <size>0x20</size>
28176 <access>read-write</access>
28177 <resetValue>0x00000000</resetValue>
28178 <fields>
28179 <field>
28180 <name>FFA0</name>
28181 <description>Filter FIFO assignment for filter
28182 0</description>
28183 <bitOffset>0</bitOffset>
28184 <bitWidth>1</bitWidth>
28185 </field>
28186 <field>
28187 <name>FFA1</name>
28188 <description>Filter FIFO assignment for filter
28189 1</description>
28190 <bitOffset>1</bitOffset>
28191 <bitWidth>1</bitWidth>
28192 </field>
28193 <field>
28194 <name>FFA2</name>
28195 <description>Filter FIFO assignment for filter
28196 2</description>
28197 <bitOffset>2</bitOffset>
28198 <bitWidth>1</bitWidth>
28199 </field>
28200 <field>
28201 <name>FFA3</name>
28202 <description>Filter FIFO assignment for filter
28203 3</description>
28204 <bitOffset>3</bitOffset>
28205 <bitWidth>1</bitWidth>
28206 </field>
28207 <field>
28208 <name>FFA4</name>
28209 <description>Filter FIFO assignment for filter
28210 4</description>
28211 <bitOffset>4</bitOffset>
28212 <bitWidth>1</bitWidth>
28213 </field>
28214 <field>
28215 <name>FFA5</name>
28216 <description>Filter FIFO assignment for filter
28217 5</description>
28218 <bitOffset>5</bitOffset>
28219 <bitWidth>1</bitWidth>
28220 </field>
28221 <field>
28222 <name>FFA6</name>
28223 <description>Filter FIFO assignment for filter
28224 6</description>
28225 <bitOffset>6</bitOffset>
28226 <bitWidth>1</bitWidth>
28227 </field>
28228 <field>
28229 <name>FFA7</name>
28230 <description>Filter FIFO assignment for filter
28231 7</description>
28232 <bitOffset>7</bitOffset>
28233 <bitWidth>1</bitWidth>
28234 </field>
28235 <field>
28236 <name>FFA8</name>
28237 <description>Filter FIFO assignment for filter
28238 8</description>
28239 <bitOffset>8</bitOffset>
28240 <bitWidth>1</bitWidth>
28241 </field>
28242 <field>
28243 <name>FFA9</name>
28244 <description>Filter FIFO assignment for filter
28245 9</description>
28246 <bitOffset>9</bitOffset>
28247 <bitWidth>1</bitWidth>
28248 </field>
28249 <field>
28250 <name>FFA10</name>
28251 <description>Filter FIFO assignment for filter
28252 10</description>
28253 <bitOffset>10</bitOffset>
28254 <bitWidth>1</bitWidth>
28255 </field>
28256 <field>
28257 <name>FFA11</name>
28258 <description>Filter FIFO assignment for filter
28259 11</description>
28260 <bitOffset>11</bitOffset>
28261 <bitWidth>1</bitWidth>
28262 </field>
28263 <field>
28264 <name>FFA12</name>
28265 <description>Filter FIFO assignment for filter
28266 12</description>
28267 <bitOffset>12</bitOffset>
28268 <bitWidth>1</bitWidth>
28269 </field>
28270 <field>
28271 <name>FFA13</name>
28272 <description>Filter FIFO assignment for filter
28273 13</description>
28274 <bitOffset>13</bitOffset>
28275 <bitWidth>1</bitWidth>
28276 </field>
28277 <field>
28278 <name>FFA14</name>
28279 <description>Filter FIFO assignment for filter
28280 14</description>
28281 <bitOffset>14</bitOffset>
28282 <bitWidth>1</bitWidth>
28283 </field>
28284 <field>
28285 <name>FFA15</name>
28286 <description>Filter FIFO assignment for filter
28287 15</description>
28288 <bitOffset>15</bitOffset>
28289 <bitWidth>1</bitWidth>
28290 </field>
28291 <field>
28292 <name>FFA16</name>
28293 <description>Filter FIFO assignment for filter
28294 16</description>
28295 <bitOffset>16</bitOffset>
28296 <bitWidth>1</bitWidth>
28297 </field>
28298 <field>
28299 <name>FFA17</name>
28300 <description>Filter FIFO assignment for filter
28301 17</description>
28302 <bitOffset>17</bitOffset>
28303 <bitWidth>1</bitWidth>
28304 </field>
28305 <field>
28306 <name>FFA18</name>
28307 <description>Filter FIFO assignment for filter
28308 18</description>
28309 <bitOffset>18</bitOffset>
28310 <bitWidth>1</bitWidth>
28311 </field>
28312 <field>
28313 <name>FFA19</name>
28314 <description>Filter FIFO assignment for filter
28315 19</description>
28316 <bitOffset>19</bitOffset>
28317 <bitWidth>1</bitWidth>
28318 </field>
28319 <field>
28320 <name>FFA20</name>
28321 <description>Filter FIFO assignment for filter
28322 20</description>
28323 <bitOffset>20</bitOffset>
28324 <bitWidth>1</bitWidth>
28325 </field>
28326 <field>
28327 <name>FFA21</name>
28328 <description>Filter FIFO assignment for filter
28329 21</description>
28330 <bitOffset>21</bitOffset>
28331 <bitWidth>1</bitWidth>
28332 </field>
28333 <field>
28334 <name>FFA22</name>
28335 <description>Filter FIFO assignment for filter
28336 22</description>
28337 <bitOffset>22</bitOffset>
28338 <bitWidth>1</bitWidth>
28339 </field>
28340 <field>
28341 <name>FFA23</name>
28342 <description>Filter FIFO assignment for filter
28343 23</description>
28344 <bitOffset>23</bitOffset>
28345 <bitWidth>1</bitWidth>
28346 </field>
28347 <field>
28348 <name>FFA24</name>
28349 <description>Filter FIFO assignment for filter
28350 24</description>
28351 <bitOffset>24</bitOffset>
28352 <bitWidth>1</bitWidth>
28353 </field>
28354 <field>
28355 <name>FFA25</name>
28356 <description>Filter FIFO assignment for filter
28357 25</description>
28358 <bitOffset>25</bitOffset>
28359 <bitWidth>1</bitWidth>
28360 </field>
28361 <field>
28362 <name>FFA26</name>
28363 <description>Filter FIFO assignment for filter
28364 26</description>
28365 <bitOffset>26</bitOffset>
28366 <bitWidth>1</bitWidth>
28367 </field>
28368 <field>
28369 <name>FFA27</name>
28370 <description>Filter FIFO assignment for filter
28371 27</description>
28372 <bitOffset>27</bitOffset>
28373 <bitWidth>1</bitWidth>
28374 </field>
28375 </fields>
28376 </register>
28377 <register>
28378 <name>FA1R</name>
28379 <displayName>FA1R</displayName>
28380 <description>filter activation register</description>
28381 <addressOffset>0x21C</addressOffset>
28382 <size>0x20</size>
28383 <access>read-write</access>
28384 <resetValue>0x00000000</resetValue>
28385 <fields>
28386 <field>
28387 <name>FACT0</name>
28388 <description>Filter active</description>
28389 <bitOffset>0</bitOffset>
28390 <bitWidth>1</bitWidth>
28391 </field>
28392 <field>
28393 <name>FACT1</name>
28394 <description>Filter active</description>
28395 <bitOffset>1</bitOffset>
28396 <bitWidth>1</bitWidth>
28397 </field>
28398 <field>
28399 <name>FACT2</name>
28400 <description>Filter active</description>
28401 <bitOffset>2</bitOffset>
28402 <bitWidth>1</bitWidth>
28403 </field>
28404 <field>
28405 <name>FACT3</name>
28406 <description>Filter active</description>
28407 <bitOffset>3</bitOffset>
28408 <bitWidth>1</bitWidth>
28409 </field>
28410 <field>
28411 <name>FACT4</name>
28412 <description>Filter active</description>
28413 <bitOffset>4</bitOffset>
28414 <bitWidth>1</bitWidth>
28415 </field>
28416 <field>
28417 <name>FACT5</name>
28418 <description>Filter active</description>
28419 <bitOffset>5</bitOffset>
28420 <bitWidth>1</bitWidth>
28421 </field>
28422 <field>
28423 <name>FACT6</name>
28424 <description>Filter active</description>
28425 <bitOffset>6</bitOffset>
28426 <bitWidth>1</bitWidth>
28427 </field>
28428 <field>
28429 <name>FACT7</name>
28430 <description>Filter active</description>
28431 <bitOffset>7</bitOffset>
28432 <bitWidth>1</bitWidth>
28433 </field>
28434 <field>
28435 <name>FACT8</name>
28436 <description>Filter active</description>
28437 <bitOffset>8</bitOffset>
28438 <bitWidth>1</bitWidth>
28439 </field>
28440 <field>
28441 <name>FACT9</name>
28442 <description>Filter active</description>
28443 <bitOffset>9</bitOffset>
28444 <bitWidth>1</bitWidth>
28445 </field>
28446 <field>
28447 <name>FACT10</name>
28448 <description>Filter active</description>
28449 <bitOffset>10</bitOffset>
28450 <bitWidth>1</bitWidth>
28451 </field>
28452 <field>
28453 <name>FACT11</name>
28454 <description>Filter active</description>
28455 <bitOffset>11</bitOffset>
28456 <bitWidth>1</bitWidth>
28457 </field>
28458 <field>
28459 <name>FACT12</name>
28460 <description>Filter active</description>
28461 <bitOffset>12</bitOffset>
28462 <bitWidth>1</bitWidth>
28463 </field>
28464 <field>
28465 <name>FACT13</name>
28466 <description>Filter active</description>
28467 <bitOffset>13</bitOffset>
28468 <bitWidth>1</bitWidth>
28469 </field>
28470 <field>
28471 <name>FACT14</name>
28472 <description>Filter active</description>
28473 <bitOffset>14</bitOffset>
28474 <bitWidth>1</bitWidth>
28475 </field>
28476 <field>
28477 <name>FACT15</name>
28478 <description>Filter active</description>
28479 <bitOffset>15</bitOffset>
28480 <bitWidth>1</bitWidth>
28481 </field>
28482 <field>
28483 <name>FACT16</name>
28484 <description>Filter active</description>
28485 <bitOffset>16</bitOffset>
28486 <bitWidth>1</bitWidth>
28487 </field>
28488 <field>
28489 <name>FACT17</name>
28490 <description>Filter active</description>
28491 <bitOffset>17</bitOffset>
28492 <bitWidth>1</bitWidth>
28493 </field>
28494 <field>
28495 <name>FACT18</name>
28496 <description>Filter active</description>
28497 <bitOffset>18</bitOffset>
28498 <bitWidth>1</bitWidth>
28499 </field>
28500 <field>
28501 <name>FACT19</name>
28502 <description>Filter active</description>
28503 <bitOffset>19</bitOffset>
28504 <bitWidth>1</bitWidth>
28505 </field>
28506 <field>
28507 <name>FACT20</name>
28508 <description>Filter active</description>
28509 <bitOffset>20</bitOffset>
28510 <bitWidth>1</bitWidth>
28511 </field>
28512 <field>
28513 <name>FACT21</name>
28514 <description>Filter active</description>
28515 <bitOffset>21</bitOffset>
28516 <bitWidth>1</bitWidth>
28517 </field>
28518 <field>
28519 <name>FACT22</name>
28520 <description>Filter active</description>
28521 <bitOffset>22</bitOffset>
28522 <bitWidth>1</bitWidth>
28523 </field>
28524 <field>
28525 <name>FACT23</name>
28526 <description>Filter active</description>
28527 <bitOffset>23</bitOffset>
28528 <bitWidth>1</bitWidth>
28529 </field>
28530 <field>
28531 <name>FACT24</name>
28532 <description>Filter active</description>
28533 <bitOffset>24</bitOffset>
28534 <bitWidth>1</bitWidth>
28535 </field>
28536 <field>
28537 <name>FACT25</name>
28538 <description>Filter active</description>
28539 <bitOffset>25</bitOffset>
28540 <bitWidth>1</bitWidth>
28541 </field>
28542 <field>
28543 <name>FACT26</name>
28544 <description>Filter active</description>
28545 <bitOffset>26</bitOffset>
28546 <bitWidth>1</bitWidth>
28547 </field>
28548 <field>
28549 <name>FACT27</name>
28550 <description>Filter active</description>
28551 <bitOffset>27</bitOffset>
28552 <bitWidth>1</bitWidth>
28553 </field>
28554 </fields>
28555 </register>
28556 <register>
28557 <name>F0R1</name>
28558 <displayName>F0R1</displayName>
28559 <description>Filter bank 0 register 1</description>
28560 <addressOffset>0x240</addressOffset>
28561 <size>0x20</size>
28562 <access>read-write</access>
28563 <resetValue>0x00000000</resetValue>
28564 <fields>
28565 <field>
28566 <name>FB0</name>
28567 <description>Filter bits</description>
28568 <bitOffset>0</bitOffset>
28569 <bitWidth>1</bitWidth>
28570 </field>
28571 <field>
28572 <name>FB1</name>
28573 <description>Filter bits</description>
28574 <bitOffset>1</bitOffset>
28575 <bitWidth>1</bitWidth>
28576 </field>
28577 <field>
28578 <name>FB2</name>
28579 <description>Filter bits</description>
28580 <bitOffset>2</bitOffset>
28581 <bitWidth>1</bitWidth>
28582 </field>
28583 <field>
28584 <name>FB3</name>
28585 <description>Filter bits</description>
28586 <bitOffset>3</bitOffset>
28587 <bitWidth>1</bitWidth>
28588 </field>
28589 <field>
28590 <name>FB4</name>
28591 <description>Filter bits</description>
28592 <bitOffset>4</bitOffset>
28593 <bitWidth>1</bitWidth>
28594 </field>
28595 <field>
28596 <name>FB5</name>
28597 <description>Filter bits</description>
28598 <bitOffset>5</bitOffset>
28599 <bitWidth>1</bitWidth>
28600 </field>
28601 <field>
28602 <name>FB6</name>
28603 <description>Filter bits</description>
28604 <bitOffset>6</bitOffset>
28605 <bitWidth>1</bitWidth>
28606 </field>
28607 <field>
28608 <name>FB7</name>
28609 <description>Filter bits</description>
28610 <bitOffset>7</bitOffset>
28611 <bitWidth>1</bitWidth>
28612 </field>
28613 <field>
28614 <name>FB8</name>
28615 <description>Filter bits</description>
28616 <bitOffset>8</bitOffset>
28617 <bitWidth>1</bitWidth>
28618 </field>
28619 <field>
28620 <name>FB9</name>
28621 <description>Filter bits</description>
28622 <bitOffset>9</bitOffset>
28623 <bitWidth>1</bitWidth>
28624 </field>
28625 <field>
28626 <name>FB10</name>
28627 <description>Filter bits</description>
28628 <bitOffset>10</bitOffset>
28629 <bitWidth>1</bitWidth>
28630 </field>
28631 <field>
28632 <name>FB11</name>
28633 <description>Filter bits</description>
28634 <bitOffset>11</bitOffset>
28635 <bitWidth>1</bitWidth>
28636 </field>
28637 <field>
28638 <name>FB12</name>
28639 <description>Filter bits</description>
28640 <bitOffset>12</bitOffset>
28641 <bitWidth>1</bitWidth>
28642 </field>
28643 <field>
28644 <name>FB13</name>
28645 <description>Filter bits</description>
28646 <bitOffset>13</bitOffset>
28647 <bitWidth>1</bitWidth>
28648 </field>
28649 <field>
28650 <name>FB14</name>
28651 <description>Filter bits</description>
28652 <bitOffset>14</bitOffset>
28653 <bitWidth>1</bitWidth>
28654 </field>
28655 <field>
28656 <name>FB15</name>
28657 <description>Filter bits</description>
28658 <bitOffset>15</bitOffset>
28659 <bitWidth>1</bitWidth>
28660 </field>
28661 <field>
28662 <name>FB16</name>
28663 <description>Filter bits</description>
28664 <bitOffset>16</bitOffset>
28665 <bitWidth>1</bitWidth>
28666 </field>
28667 <field>
28668 <name>FB17</name>
28669 <description>Filter bits</description>
28670 <bitOffset>17</bitOffset>
28671 <bitWidth>1</bitWidth>
28672 </field>
28673 <field>
28674 <name>FB18</name>
28675 <description>Filter bits</description>
28676 <bitOffset>18</bitOffset>
28677 <bitWidth>1</bitWidth>
28678 </field>
28679 <field>
28680 <name>FB19</name>
28681 <description>Filter bits</description>
28682 <bitOffset>19</bitOffset>
28683 <bitWidth>1</bitWidth>
28684 </field>
28685 <field>
28686 <name>FB20</name>
28687 <description>Filter bits</description>
28688 <bitOffset>20</bitOffset>
28689 <bitWidth>1</bitWidth>
28690 </field>
28691 <field>
28692 <name>FB21</name>
28693 <description>Filter bits</description>
28694 <bitOffset>21</bitOffset>
28695 <bitWidth>1</bitWidth>
28696 </field>
28697 <field>
28698 <name>FB22</name>
28699 <description>Filter bits</description>
28700 <bitOffset>22</bitOffset>
28701 <bitWidth>1</bitWidth>
28702 </field>
28703 <field>
28704 <name>FB23</name>
28705 <description>Filter bits</description>
28706 <bitOffset>23</bitOffset>
28707 <bitWidth>1</bitWidth>
28708 </field>
28709 <field>
28710 <name>FB24</name>
28711 <description>Filter bits</description>
28712 <bitOffset>24</bitOffset>
28713 <bitWidth>1</bitWidth>
28714 </field>
28715 <field>
28716 <name>FB25</name>
28717 <description>Filter bits</description>
28718 <bitOffset>25</bitOffset>
28719 <bitWidth>1</bitWidth>
28720 </field>
28721 <field>
28722 <name>FB26</name>
28723 <description>Filter bits</description>
28724 <bitOffset>26</bitOffset>
28725 <bitWidth>1</bitWidth>
28726 </field>
28727 <field>
28728 <name>FB27</name>
28729 <description>Filter bits</description>
28730 <bitOffset>27</bitOffset>
28731 <bitWidth>1</bitWidth>
28732 </field>
28733 <field>
28734 <name>FB28</name>
28735 <description>Filter bits</description>
28736 <bitOffset>28</bitOffset>
28737 <bitWidth>1</bitWidth>
28738 </field>
28739 <field>
28740 <name>FB29</name>
28741 <description>Filter bits</description>
28742 <bitOffset>29</bitOffset>
28743 <bitWidth>1</bitWidth>
28744 </field>
28745 <field>
28746 <name>FB30</name>
28747 <description>Filter bits</description>
28748 <bitOffset>30</bitOffset>
28749 <bitWidth>1</bitWidth>
28750 </field>
28751 <field>
28752 <name>FB31</name>
28753 <description>Filter bits</description>
28754 <bitOffset>31</bitOffset>
28755 <bitWidth>1</bitWidth>
28756 </field>
28757 </fields>
28758 </register>
28759 <register>
28760 <name>F0R2</name>
28761 <displayName>F0R2</displayName>
28762 <description>Filter bank 0 register 2</description>
28763 <addressOffset>0x244</addressOffset>
28764 <size>0x20</size>
28765 <access>read-write</access>
28766 <resetValue>0x00000000</resetValue>
28767 <fields>
28768 <field>
28769 <name>FB0</name>
28770 <description>Filter bits</description>
28771 <bitOffset>0</bitOffset>
28772 <bitWidth>1</bitWidth>
28773 </field>
28774 <field>
28775 <name>FB1</name>
28776 <description>Filter bits</description>
28777 <bitOffset>1</bitOffset>
28778 <bitWidth>1</bitWidth>
28779 </field>
28780 <field>
28781 <name>FB2</name>
28782 <description>Filter bits</description>
28783 <bitOffset>2</bitOffset>
28784 <bitWidth>1</bitWidth>
28785 </field>
28786 <field>
28787 <name>FB3</name>
28788 <description>Filter bits</description>
28789 <bitOffset>3</bitOffset>
28790 <bitWidth>1</bitWidth>
28791 </field>
28792 <field>
28793 <name>FB4</name>
28794 <description>Filter bits</description>
28795 <bitOffset>4</bitOffset>
28796 <bitWidth>1</bitWidth>
28797 </field>
28798 <field>
28799 <name>FB5</name>
28800 <description>Filter bits</description>
28801 <bitOffset>5</bitOffset>
28802 <bitWidth>1</bitWidth>
28803 </field>
28804 <field>
28805 <name>FB6</name>
28806 <description>Filter bits</description>
28807 <bitOffset>6</bitOffset>
28808 <bitWidth>1</bitWidth>
28809 </field>
28810 <field>
28811 <name>FB7</name>
28812 <description>Filter bits</description>
28813 <bitOffset>7</bitOffset>
28814 <bitWidth>1</bitWidth>
28815 </field>
28816 <field>
28817 <name>FB8</name>
28818 <description>Filter bits</description>
28819 <bitOffset>8</bitOffset>
28820 <bitWidth>1</bitWidth>
28821 </field>
28822 <field>
28823 <name>FB9</name>
28824 <description>Filter bits</description>
28825 <bitOffset>9</bitOffset>
28826 <bitWidth>1</bitWidth>
28827 </field>
28828 <field>
28829 <name>FB10</name>
28830 <description>Filter bits</description>
28831 <bitOffset>10</bitOffset>
28832 <bitWidth>1</bitWidth>
28833 </field>
28834 <field>
28835 <name>FB11</name>
28836 <description>Filter bits</description>
28837 <bitOffset>11</bitOffset>
28838 <bitWidth>1</bitWidth>
28839 </field>
28840 <field>
28841 <name>FB12</name>
28842 <description>Filter bits</description>
28843 <bitOffset>12</bitOffset>
28844 <bitWidth>1</bitWidth>
28845 </field>
28846 <field>
28847 <name>FB13</name>
28848 <description>Filter bits</description>
28849 <bitOffset>13</bitOffset>
28850 <bitWidth>1</bitWidth>
28851 </field>
28852 <field>
28853 <name>FB14</name>
28854 <description>Filter bits</description>
28855 <bitOffset>14</bitOffset>
28856 <bitWidth>1</bitWidth>
28857 </field>
28858 <field>
28859 <name>FB15</name>
28860 <description>Filter bits</description>
28861 <bitOffset>15</bitOffset>
28862 <bitWidth>1</bitWidth>
28863 </field>
28864 <field>
28865 <name>FB16</name>
28866 <description>Filter bits</description>
28867 <bitOffset>16</bitOffset>
28868 <bitWidth>1</bitWidth>
28869 </field>
28870 <field>
28871 <name>FB17</name>
28872 <description>Filter bits</description>
28873 <bitOffset>17</bitOffset>
28874 <bitWidth>1</bitWidth>
28875 </field>
28876 <field>
28877 <name>FB18</name>
28878 <description>Filter bits</description>
28879 <bitOffset>18</bitOffset>
28880 <bitWidth>1</bitWidth>
28881 </field>
28882 <field>
28883 <name>FB19</name>
28884 <description>Filter bits</description>
28885 <bitOffset>19</bitOffset>
28886 <bitWidth>1</bitWidth>
28887 </field>
28888 <field>
28889 <name>FB20</name>
28890 <description>Filter bits</description>
28891 <bitOffset>20</bitOffset>
28892 <bitWidth>1</bitWidth>
28893 </field>
28894 <field>
28895 <name>FB21</name>
28896 <description>Filter bits</description>
28897 <bitOffset>21</bitOffset>
28898 <bitWidth>1</bitWidth>
28899 </field>
28900 <field>
28901 <name>FB22</name>
28902 <description>Filter bits</description>
28903 <bitOffset>22</bitOffset>
28904 <bitWidth>1</bitWidth>
28905 </field>
28906 <field>
28907 <name>FB23</name>
28908 <description>Filter bits</description>
28909 <bitOffset>23</bitOffset>
28910 <bitWidth>1</bitWidth>
28911 </field>
28912 <field>
28913 <name>FB24</name>
28914 <description>Filter bits</description>
28915 <bitOffset>24</bitOffset>
28916 <bitWidth>1</bitWidth>
28917 </field>
28918 <field>
28919 <name>FB25</name>
28920 <description>Filter bits</description>
28921 <bitOffset>25</bitOffset>
28922 <bitWidth>1</bitWidth>
28923 </field>
28924 <field>
28925 <name>FB26</name>
28926 <description>Filter bits</description>
28927 <bitOffset>26</bitOffset>
28928 <bitWidth>1</bitWidth>
28929 </field>
28930 <field>
28931 <name>FB27</name>
28932 <description>Filter bits</description>
28933 <bitOffset>27</bitOffset>
28934 <bitWidth>1</bitWidth>
28935 </field>
28936 <field>
28937 <name>FB28</name>
28938 <description>Filter bits</description>
28939 <bitOffset>28</bitOffset>
28940 <bitWidth>1</bitWidth>
28941 </field>
28942 <field>
28943 <name>FB29</name>
28944 <description>Filter bits</description>
28945 <bitOffset>29</bitOffset>
28946 <bitWidth>1</bitWidth>
28947 </field>
28948 <field>
28949 <name>FB30</name>
28950 <description>Filter bits</description>
28951 <bitOffset>30</bitOffset>
28952 <bitWidth>1</bitWidth>
28953 </field>
28954 <field>
28955 <name>FB31</name>
28956 <description>Filter bits</description>
28957 <bitOffset>31</bitOffset>
28958 <bitWidth>1</bitWidth>
28959 </field>
28960 </fields>
28961 </register>
28962 <register>
28963 <name>F1R1</name>
28964 <displayName>F1R1</displayName>
28965 <description>Filter bank 1 register 1</description>
28966 <addressOffset>0x248</addressOffset>
28967 <size>0x20</size>
28968 <access>read-write</access>
28969 <resetValue>0x00000000</resetValue>
28970 <fields>
28971 <field>
28972 <name>FB0</name>
28973 <description>Filter bits</description>
28974 <bitOffset>0</bitOffset>
28975 <bitWidth>1</bitWidth>
28976 </field>
28977 <field>
28978 <name>FB1</name>
28979 <description>Filter bits</description>
28980 <bitOffset>1</bitOffset>
28981 <bitWidth>1</bitWidth>
28982 </field>
28983 <field>
28984 <name>FB2</name>
28985 <description>Filter bits</description>
28986 <bitOffset>2</bitOffset>
28987 <bitWidth>1</bitWidth>
28988 </field>
28989 <field>
28990 <name>FB3</name>
28991 <description>Filter bits</description>
28992 <bitOffset>3</bitOffset>
28993 <bitWidth>1</bitWidth>
28994 </field>
28995 <field>
28996 <name>FB4</name>
28997 <description>Filter bits</description>
28998 <bitOffset>4</bitOffset>
28999 <bitWidth>1</bitWidth>
29000 </field>
29001 <field>
29002 <name>FB5</name>
29003 <description>Filter bits</description>
29004 <bitOffset>5</bitOffset>
29005 <bitWidth>1</bitWidth>
29006 </field>
29007 <field>
29008 <name>FB6</name>
29009 <description>Filter bits</description>
29010 <bitOffset>6</bitOffset>
29011 <bitWidth>1</bitWidth>
29012 </field>
29013 <field>
29014 <name>FB7</name>
29015 <description>Filter bits</description>
29016 <bitOffset>7</bitOffset>
29017 <bitWidth>1</bitWidth>
29018 </field>
29019 <field>
29020 <name>FB8</name>
29021 <description>Filter bits</description>
29022 <bitOffset>8</bitOffset>
29023 <bitWidth>1</bitWidth>
29024 </field>
29025 <field>
29026 <name>FB9</name>
29027 <description>Filter bits</description>
29028 <bitOffset>9</bitOffset>
29029 <bitWidth>1</bitWidth>
29030 </field>
29031 <field>
29032 <name>FB10</name>
29033 <description>Filter bits</description>
29034 <bitOffset>10</bitOffset>
29035 <bitWidth>1</bitWidth>
29036 </field>
29037 <field>
29038 <name>FB11</name>
29039 <description>Filter bits</description>
29040 <bitOffset>11</bitOffset>
29041 <bitWidth>1</bitWidth>
29042 </field>
29043 <field>
29044 <name>FB12</name>
29045 <description>Filter bits</description>
29046 <bitOffset>12</bitOffset>
29047 <bitWidth>1</bitWidth>
29048 </field>
29049 <field>
29050 <name>FB13</name>
29051 <description>Filter bits</description>
29052 <bitOffset>13</bitOffset>
29053 <bitWidth>1</bitWidth>
29054 </field>
29055 <field>
29056 <name>FB14</name>
29057 <description>Filter bits</description>
29058 <bitOffset>14</bitOffset>
29059 <bitWidth>1</bitWidth>
29060 </field>
29061 <field>
29062 <name>FB15</name>
29063 <description>Filter bits</description>
29064 <bitOffset>15</bitOffset>
29065 <bitWidth>1</bitWidth>
29066 </field>
29067 <field>
29068 <name>FB16</name>
29069 <description>Filter bits</description>
29070 <bitOffset>16</bitOffset>
29071 <bitWidth>1</bitWidth>
29072 </field>
29073 <field>
29074 <name>FB17</name>
29075 <description>Filter bits</description>
29076 <bitOffset>17</bitOffset>
29077 <bitWidth>1</bitWidth>
29078 </field>
29079 <field>
29080 <name>FB18</name>
29081 <description>Filter bits</description>
29082 <bitOffset>18</bitOffset>
29083 <bitWidth>1</bitWidth>
29084 </field>
29085 <field>
29086 <name>FB19</name>
29087 <description>Filter bits</description>
29088 <bitOffset>19</bitOffset>
29089 <bitWidth>1</bitWidth>
29090 </field>
29091 <field>
29092 <name>FB20</name>
29093 <description>Filter bits</description>
29094 <bitOffset>20</bitOffset>
29095 <bitWidth>1</bitWidth>
29096 </field>
29097 <field>
29098 <name>FB21</name>
29099 <description>Filter bits</description>
29100 <bitOffset>21</bitOffset>
29101 <bitWidth>1</bitWidth>
29102 </field>
29103 <field>
29104 <name>FB22</name>
29105 <description>Filter bits</description>
29106 <bitOffset>22</bitOffset>
29107 <bitWidth>1</bitWidth>
29108 </field>
29109 <field>
29110 <name>FB23</name>
29111 <description>Filter bits</description>
29112 <bitOffset>23</bitOffset>
29113 <bitWidth>1</bitWidth>
29114 </field>
29115 <field>
29116 <name>FB24</name>
29117 <description>Filter bits</description>
29118 <bitOffset>24</bitOffset>
29119 <bitWidth>1</bitWidth>
29120 </field>
29121 <field>
29122 <name>FB25</name>
29123 <description>Filter bits</description>
29124 <bitOffset>25</bitOffset>
29125 <bitWidth>1</bitWidth>
29126 </field>
29127 <field>
29128 <name>FB26</name>
29129 <description>Filter bits</description>
29130 <bitOffset>26</bitOffset>
29131 <bitWidth>1</bitWidth>
29132 </field>
29133 <field>
29134 <name>FB27</name>
29135 <description>Filter bits</description>
29136 <bitOffset>27</bitOffset>
29137 <bitWidth>1</bitWidth>
29138 </field>
29139 <field>
29140 <name>FB28</name>
29141 <description>Filter bits</description>
29142 <bitOffset>28</bitOffset>
29143 <bitWidth>1</bitWidth>
29144 </field>
29145 <field>
29146 <name>FB29</name>
29147 <description>Filter bits</description>
29148 <bitOffset>29</bitOffset>
29149 <bitWidth>1</bitWidth>
29150 </field>
29151 <field>
29152 <name>FB30</name>
29153 <description>Filter bits</description>
29154 <bitOffset>30</bitOffset>
29155 <bitWidth>1</bitWidth>
29156 </field>
29157 <field>
29158 <name>FB31</name>
29159 <description>Filter bits</description>
29160 <bitOffset>31</bitOffset>
29161 <bitWidth>1</bitWidth>
29162 </field>
29163 </fields>
29164 </register>
29165 <register>
29166 <name>F1R2</name>
29167 <displayName>F1R2</displayName>
29168 <description>Filter bank 1 register 2</description>
29169 <addressOffset>0x24C</addressOffset>
29170 <size>0x20</size>
29171 <access>read-write</access>
29172 <resetValue>0x00000000</resetValue>
29173 <fields>
29174 <field>
29175 <name>FB0</name>
29176 <description>Filter bits</description>
29177 <bitOffset>0</bitOffset>
29178 <bitWidth>1</bitWidth>
29179 </field>
29180 <field>
29181 <name>FB1</name>
29182 <description>Filter bits</description>
29183 <bitOffset>1</bitOffset>
29184 <bitWidth>1</bitWidth>
29185 </field>
29186 <field>
29187 <name>FB2</name>
29188 <description>Filter bits</description>
29189 <bitOffset>2</bitOffset>
29190 <bitWidth>1</bitWidth>
29191 </field>
29192 <field>
29193 <name>FB3</name>
29194 <description>Filter bits</description>
29195 <bitOffset>3</bitOffset>
29196 <bitWidth>1</bitWidth>
29197 </field>
29198 <field>
29199 <name>FB4</name>
29200 <description>Filter bits</description>
29201 <bitOffset>4</bitOffset>
29202 <bitWidth>1</bitWidth>
29203 </field>
29204 <field>
29205 <name>FB5</name>
29206 <description>Filter bits</description>
29207 <bitOffset>5</bitOffset>
29208 <bitWidth>1</bitWidth>
29209 </field>
29210 <field>
29211 <name>FB6</name>
29212 <description>Filter bits</description>
29213 <bitOffset>6</bitOffset>
29214 <bitWidth>1</bitWidth>
29215 </field>
29216 <field>
29217 <name>FB7</name>
29218 <description>Filter bits</description>
29219 <bitOffset>7</bitOffset>
29220 <bitWidth>1</bitWidth>
29221 </field>
29222 <field>
29223 <name>FB8</name>
29224 <description>Filter bits</description>
29225 <bitOffset>8</bitOffset>
29226 <bitWidth>1</bitWidth>
29227 </field>
29228 <field>
29229 <name>FB9</name>
29230 <description>Filter bits</description>
29231 <bitOffset>9</bitOffset>
29232 <bitWidth>1</bitWidth>
29233 </field>
29234 <field>
29235 <name>FB10</name>
29236 <description>Filter bits</description>
29237 <bitOffset>10</bitOffset>
29238 <bitWidth>1</bitWidth>
29239 </field>
29240 <field>
29241 <name>FB11</name>
29242 <description>Filter bits</description>
29243 <bitOffset>11</bitOffset>
29244 <bitWidth>1</bitWidth>
29245 </field>
29246 <field>
29247 <name>FB12</name>
29248 <description>Filter bits</description>
29249 <bitOffset>12</bitOffset>
29250 <bitWidth>1</bitWidth>
29251 </field>
29252 <field>
29253 <name>FB13</name>
29254 <description>Filter bits</description>
29255 <bitOffset>13</bitOffset>
29256 <bitWidth>1</bitWidth>
29257 </field>
29258 <field>
29259 <name>FB14</name>
29260 <description>Filter bits</description>
29261 <bitOffset>14</bitOffset>
29262 <bitWidth>1</bitWidth>
29263 </field>
29264 <field>
29265 <name>FB15</name>
29266 <description>Filter bits</description>
29267 <bitOffset>15</bitOffset>
29268 <bitWidth>1</bitWidth>
29269 </field>
29270 <field>
29271 <name>FB16</name>
29272 <description>Filter bits</description>
29273 <bitOffset>16</bitOffset>
29274 <bitWidth>1</bitWidth>
29275 </field>
29276 <field>
29277 <name>FB17</name>
29278 <description>Filter bits</description>
29279 <bitOffset>17</bitOffset>
29280 <bitWidth>1</bitWidth>
29281 </field>
29282 <field>
29283 <name>FB18</name>
29284 <description>Filter bits</description>
29285 <bitOffset>18</bitOffset>
29286 <bitWidth>1</bitWidth>
29287 </field>
29288 <field>
29289 <name>FB19</name>
29290 <description>Filter bits</description>
29291 <bitOffset>19</bitOffset>
29292 <bitWidth>1</bitWidth>
29293 </field>
29294 <field>
29295 <name>FB20</name>
29296 <description>Filter bits</description>
29297 <bitOffset>20</bitOffset>
29298 <bitWidth>1</bitWidth>
29299 </field>
29300 <field>
29301 <name>FB21</name>
29302 <description>Filter bits</description>
29303 <bitOffset>21</bitOffset>
29304 <bitWidth>1</bitWidth>
29305 </field>
29306 <field>
29307 <name>FB22</name>
29308 <description>Filter bits</description>
29309 <bitOffset>22</bitOffset>
29310 <bitWidth>1</bitWidth>
29311 </field>
29312 <field>
29313 <name>FB23</name>
29314 <description>Filter bits</description>
29315 <bitOffset>23</bitOffset>
29316 <bitWidth>1</bitWidth>
29317 </field>
29318 <field>
29319 <name>FB24</name>
29320 <description>Filter bits</description>
29321 <bitOffset>24</bitOffset>
29322 <bitWidth>1</bitWidth>
29323 </field>
29324 <field>
29325 <name>FB25</name>
29326 <description>Filter bits</description>
29327 <bitOffset>25</bitOffset>
29328 <bitWidth>1</bitWidth>
29329 </field>
29330 <field>
29331 <name>FB26</name>
29332 <description>Filter bits</description>
29333 <bitOffset>26</bitOffset>
29334 <bitWidth>1</bitWidth>
29335 </field>
29336 <field>
29337 <name>FB27</name>
29338 <description>Filter bits</description>
29339 <bitOffset>27</bitOffset>
29340 <bitWidth>1</bitWidth>
29341 </field>
29342 <field>
29343 <name>FB28</name>
29344 <description>Filter bits</description>
29345 <bitOffset>28</bitOffset>
29346 <bitWidth>1</bitWidth>
29347 </field>
29348 <field>
29349 <name>FB29</name>
29350 <description>Filter bits</description>
29351 <bitOffset>29</bitOffset>
29352 <bitWidth>1</bitWidth>
29353 </field>
29354 <field>
29355 <name>FB30</name>
29356 <description>Filter bits</description>
29357 <bitOffset>30</bitOffset>
29358 <bitWidth>1</bitWidth>
29359 </field>
29360 <field>
29361 <name>FB31</name>
29362 <description>Filter bits</description>
29363 <bitOffset>31</bitOffset>
29364 <bitWidth>1</bitWidth>
29365 </field>
29366 </fields>
29367 </register>
29368 <register>
29369 <name>F2R1</name>
29370 <displayName>F2R1</displayName>
29371 <description>Filter bank 2 register 1</description>
29372 <addressOffset>0x250</addressOffset>
29373 <size>0x20</size>
29374 <access>read-write</access>
29375 <resetValue>0x00000000</resetValue>
29376 <fields>
29377 <field>
29378 <name>FB0</name>
29379 <description>Filter bits</description>
29380 <bitOffset>0</bitOffset>
29381 <bitWidth>1</bitWidth>
29382 </field>
29383 <field>
29384 <name>FB1</name>
29385 <description>Filter bits</description>
29386 <bitOffset>1</bitOffset>
29387 <bitWidth>1</bitWidth>
29388 </field>
29389 <field>
29390 <name>FB2</name>
29391 <description>Filter bits</description>
29392 <bitOffset>2</bitOffset>
29393 <bitWidth>1</bitWidth>
29394 </field>
29395 <field>
29396 <name>FB3</name>
29397 <description>Filter bits</description>
29398 <bitOffset>3</bitOffset>
29399 <bitWidth>1</bitWidth>
29400 </field>
29401 <field>
29402 <name>FB4</name>
29403 <description>Filter bits</description>
29404 <bitOffset>4</bitOffset>
29405 <bitWidth>1</bitWidth>
29406 </field>
29407 <field>
29408 <name>FB5</name>
29409 <description>Filter bits</description>
29410 <bitOffset>5</bitOffset>
29411 <bitWidth>1</bitWidth>
29412 </field>
29413 <field>
29414 <name>FB6</name>
29415 <description>Filter bits</description>
29416 <bitOffset>6</bitOffset>
29417 <bitWidth>1</bitWidth>
29418 </field>
29419 <field>
29420 <name>FB7</name>
29421 <description>Filter bits</description>
29422 <bitOffset>7</bitOffset>
29423 <bitWidth>1</bitWidth>
29424 </field>
29425 <field>
29426 <name>FB8</name>
29427 <description>Filter bits</description>
29428 <bitOffset>8</bitOffset>
29429 <bitWidth>1</bitWidth>
29430 </field>
29431 <field>
29432 <name>FB9</name>
29433 <description>Filter bits</description>
29434 <bitOffset>9</bitOffset>
29435 <bitWidth>1</bitWidth>
29436 </field>
29437 <field>
29438 <name>FB10</name>
29439 <description>Filter bits</description>
29440 <bitOffset>10</bitOffset>
29441 <bitWidth>1</bitWidth>
29442 </field>
29443 <field>
29444 <name>FB11</name>
29445 <description>Filter bits</description>
29446 <bitOffset>11</bitOffset>
29447 <bitWidth>1</bitWidth>
29448 </field>
29449 <field>
29450 <name>FB12</name>
29451 <description>Filter bits</description>
29452 <bitOffset>12</bitOffset>
29453 <bitWidth>1</bitWidth>
29454 </field>
29455 <field>
29456 <name>FB13</name>
29457 <description>Filter bits</description>
29458 <bitOffset>13</bitOffset>
29459 <bitWidth>1</bitWidth>
29460 </field>
29461 <field>
29462 <name>FB14</name>
29463 <description>Filter bits</description>
29464 <bitOffset>14</bitOffset>
29465 <bitWidth>1</bitWidth>
29466 </field>
29467 <field>
29468 <name>FB15</name>
29469 <description>Filter bits</description>
29470 <bitOffset>15</bitOffset>
29471 <bitWidth>1</bitWidth>
29472 </field>
29473 <field>
29474 <name>FB16</name>
29475 <description>Filter bits</description>
29476 <bitOffset>16</bitOffset>
29477 <bitWidth>1</bitWidth>
29478 </field>
29479 <field>
29480 <name>FB17</name>
29481 <description>Filter bits</description>
29482 <bitOffset>17</bitOffset>
29483 <bitWidth>1</bitWidth>
29484 </field>
29485 <field>
29486 <name>FB18</name>
29487 <description>Filter bits</description>
29488 <bitOffset>18</bitOffset>
29489 <bitWidth>1</bitWidth>
29490 </field>
29491 <field>
29492 <name>FB19</name>
29493 <description>Filter bits</description>
29494 <bitOffset>19</bitOffset>
29495 <bitWidth>1</bitWidth>
29496 </field>
29497 <field>
29498 <name>FB20</name>
29499 <description>Filter bits</description>
29500 <bitOffset>20</bitOffset>
29501 <bitWidth>1</bitWidth>
29502 </field>
29503 <field>
29504 <name>FB21</name>
29505 <description>Filter bits</description>
29506 <bitOffset>21</bitOffset>
29507 <bitWidth>1</bitWidth>
29508 </field>
29509 <field>
29510 <name>FB22</name>
29511 <description>Filter bits</description>
29512 <bitOffset>22</bitOffset>
29513 <bitWidth>1</bitWidth>
29514 </field>
29515 <field>
29516 <name>FB23</name>
29517 <description>Filter bits</description>
29518 <bitOffset>23</bitOffset>
29519 <bitWidth>1</bitWidth>
29520 </field>
29521 <field>
29522 <name>FB24</name>
29523 <description>Filter bits</description>
29524 <bitOffset>24</bitOffset>
29525 <bitWidth>1</bitWidth>
29526 </field>
29527 <field>
29528 <name>FB25</name>
29529 <description>Filter bits</description>
29530 <bitOffset>25</bitOffset>
29531 <bitWidth>1</bitWidth>
29532 </field>
29533 <field>
29534 <name>FB26</name>
29535 <description>Filter bits</description>
29536 <bitOffset>26</bitOffset>
29537 <bitWidth>1</bitWidth>
29538 </field>
29539 <field>
29540 <name>FB27</name>
29541 <description>Filter bits</description>
29542 <bitOffset>27</bitOffset>
29543 <bitWidth>1</bitWidth>
29544 </field>
29545 <field>
29546 <name>FB28</name>
29547 <description>Filter bits</description>
29548 <bitOffset>28</bitOffset>
29549 <bitWidth>1</bitWidth>
29550 </field>
29551 <field>
29552 <name>FB29</name>
29553 <description>Filter bits</description>
29554 <bitOffset>29</bitOffset>
29555 <bitWidth>1</bitWidth>
29556 </field>
29557 <field>
29558 <name>FB30</name>
29559 <description>Filter bits</description>
29560 <bitOffset>30</bitOffset>
29561 <bitWidth>1</bitWidth>
29562 </field>
29563 <field>
29564 <name>FB31</name>
29565 <description>Filter bits</description>
29566 <bitOffset>31</bitOffset>
29567 <bitWidth>1</bitWidth>
29568 </field>
29569 </fields>
29570 </register>
29571 <register>
29572 <name>F2R2</name>
29573 <displayName>F2R2</displayName>
29574 <description>Filter bank 2 register 2</description>
29575 <addressOffset>0x254</addressOffset>
29576 <size>0x20</size>
29577 <access>read-write</access>
29578 <resetValue>0x00000000</resetValue>
29579 <fields>
29580 <field>
29581 <name>FB0</name>
29582 <description>Filter bits</description>
29583 <bitOffset>0</bitOffset>
29584 <bitWidth>1</bitWidth>
29585 </field>
29586 <field>
29587 <name>FB1</name>
29588 <description>Filter bits</description>
29589 <bitOffset>1</bitOffset>
29590 <bitWidth>1</bitWidth>
29591 </field>
29592 <field>
29593 <name>FB2</name>
29594 <description>Filter bits</description>
29595 <bitOffset>2</bitOffset>
29596 <bitWidth>1</bitWidth>
29597 </field>
29598 <field>
29599 <name>FB3</name>
29600 <description>Filter bits</description>
29601 <bitOffset>3</bitOffset>
29602 <bitWidth>1</bitWidth>
29603 </field>
29604 <field>
29605 <name>FB4</name>
29606 <description>Filter bits</description>
29607 <bitOffset>4</bitOffset>
29608 <bitWidth>1</bitWidth>
29609 </field>
29610 <field>
29611 <name>FB5</name>
29612 <description>Filter bits</description>
29613 <bitOffset>5</bitOffset>
29614 <bitWidth>1</bitWidth>
29615 </field>
29616 <field>
29617 <name>FB6</name>
29618 <description>Filter bits</description>
29619 <bitOffset>6</bitOffset>
29620 <bitWidth>1</bitWidth>
29621 </field>
29622 <field>
29623 <name>FB7</name>
29624 <description>Filter bits</description>
29625 <bitOffset>7</bitOffset>
29626 <bitWidth>1</bitWidth>
29627 </field>
29628 <field>
29629 <name>FB8</name>
29630 <description>Filter bits</description>
29631 <bitOffset>8</bitOffset>
29632 <bitWidth>1</bitWidth>
29633 </field>
29634 <field>
29635 <name>FB9</name>
29636 <description>Filter bits</description>
29637 <bitOffset>9</bitOffset>
29638 <bitWidth>1</bitWidth>
29639 </field>
29640 <field>
29641 <name>FB10</name>
29642 <description>Filter bits</description>
29643 <bitOffset>10</bitOffset>
29644 <bitWidth>1</bitWidth>
29645 </field>
29646 <field>
29647 <name>FB11</name>
29648 <description>Filter bits</description>
29649 <bitOffset>11</bitOffset>
29650 <bitWidth>1</bitWidth>
29651 </field>
29652 <field>
29653 <name>FB12</name>
29654 <description>Filter bits</description>
29655 <bitOffset>12</bitOffset>
29656 <bitWidth>1</bitWidth>
29657 </field>
29658 <field>
29659 <name>FB13</name>
29660 <description>Filter bits</description>
29661 <bitOffset>13</bitOffset>
29662 <bitWidth>1</bitWidth>
29663 </field>
29664 <field>
29665 <name>FB14</name>
29666 <description>Filter bits</description>
29667 <bitOffset>14</bitOffset>
29668 <bitWidth>1</bitWidth>
29669 </field>
29670 <field>
29671 <name>FB15</name>
29672 <description>Filter bits</description>
29673 <bitOffset>15</bitOffset>
29674 <bitWidth>1</bitWidth>
29675 </field>
29676 <field>
29677 <name>FB16</name>
29678 <description>Filter bits</description>
29679 <bitOffset>16</bitOffset>
29680 <bitWidth>1</bitWidth>
29681 </field>
29682 <field>
29683 <name>FB17</name>
29684 <description>Filter bits</description>
29685 <bitOffset>17</bitOffset>
29686 <bitWidth>1</bitWidth>
29687 </field>
29688 <field>
29689 <name>FB18</name>
29690 <description>Filter bits</description>
29691 <bitOffset>18</bitOffset>
29692 <bitWidth>1</bitWidth>
29693 </field>
29694 <field>
29695 <name>FB19</name>
29696 <description>Filter bits</description>
29697 <bitOffset>19</bitOffset>
29698 <bitWidth>1</bitWidth>
29699 </field>
29700 <field>
29701 <name>FB20</name>
29702 <description>Filter bits</description>
29703 <bitOffset>20</bitOffset>
29704 <bitWidth>1</bitWidth>
29705 </field>
29706 <field>
29707 <name>FB21</name>
29708 <description>Filter bits</description>
29709 <bitOffset>21</bitOffset>
29710 <bitWidth>1</bitWidth>
29711 </field>
29712 <field>
29713 <name>FB22</name>
29714 <description>Filter bits</description>
29715 <bitOffset>22</bitOffset>
29716 <bitWidth>1</bitWidth>
29717 </field>
29718 <field>
29719 <name>FB23</name>
29720 <description>Filter bits</description>
29721 <bitOffset>23</bitOffset>
29722 <bitWidth>1</bitWidth>
29723 </field>
29724 <field>
29725 <name>FB24</name>
29726 <description>Filter bits</description>
29727 <bitOffset>24</bitOffset>
29728 <bitWidth>1</bitWidth>
29729 </field>
29730 <field>
29731 <name>FB25</name>
29732 <description>Filter bits</description>
29733 <bitOffset>25</bitOffset>
29734 <bitWidth>1</bitWidth>
29735 </field>
29736 <field>
29737 <name>FB26</name>
29738 <description>Filter bits</description>
29739 <bitOffset>26</bitOffset>
29740 <bitWidth>1</bitWidth>
29741 </field>
29742 <field>
29743 <name>FB27</name>
29744 <description>Filter bits</description>
29745 <bitOffset>27</bitOffset>
29746 <bitWidth>1</bitWidth>
29747 </field>
29748 <field>
29749 <name>FB28</name>
29750 <description>Filter bits</description>
29751 <bitOffset>28</bitOffset>
29752 <bitWidth>1</bitWidth>
29753 </field>
29754 <field>
29755 <name>FB29</name>
29756 <description>Filter bits</description>
29757 <bitOffset>29</bitOffset>
29758 <bitWidth>1</bitWidth>
29759 </field>
29760 <field>
29761 <name>FB30</name>
29762 <description>Filter bits</description>
29763 <bitOffset>30</bitOffset>
29764 <bitWidth>1</bitWidth>
29765 </field>
29766 <field>
29767 <name>FB31</name>
29768 <description>Filter bits</description>
29769 <bitOffset>31</bitOffset>
29770 <bitWidth>1</bitWidth>
29771 </field>
29772 </fields>
29773 </register>
29774 <register>
29775 <name>F3R1</name>
29776 <displayName>F3R1</displayName>
29777 <description>Filter bank 3 register 1</description>
29778 <addressOffset>0x258</addressOffset>
29779 <size>0x20</size>
29780 <access>read-write</access>
29781 <resetValue>0x00000000</resetValue>
29782 <fields>
29783 <field>
29784 <name>FB0</name>
29785 <description>Filter bits</description>
29786 <bitOffset>0</bitOffset>
29787 <bitWidth>1</bitWidth>
29788 </field>
29789 <field>
29790 <name>FB1</name>
29791 <description>Filter bits</description>
29792 <bitOffset>1</bitOffset>
29793 <bitWidth>1</bitWidth>
29794 </field>
29795 <field>
29796 <name>FB2</name>
29797 <description>Filter bits</description>
29798 <bitOffset>2</bitOffset>
29799 <bitWidth>1</bitWidth>
29800 </field>
29801 <field>
29802 <name>FB3</name>
29803 <description>Filter bits</description>
29804 <bitOffset>3</bitOffset>
29805 <bitWidth>1</bitWidth>
29806 </field>
29807 <field>
29808 <name>FB4</name>
29809 <description>Filter bits</description>
29810 <bitOffset>4</bitOffset>
29811 <bitWidth>1</bitWidth>
29812 </field>
29813 <field>
29814 <name>FB5</name>
29815 <description>Filter bits</description>
29816 <bitOffset>5</bitOffset>
29817 <bitWidth>1</bitWidth>
29818 </field>
29819 <field>
29820 <name>FB6</name>
29821 <description>Filter bits</description>
29822 <bitOffset>6</bitOffset>
29823 <bitWidth>1</bitWidth>
29824 </field>
29825 <field>
29826 <name>FB7</name>
29827 <description>Filter bits</description>
29828 <bitOffset>7</bitOffset>
29829 <bitWidth>1</bitWidth>
29830 </field>
29831 <field>
29832 <name>FB8</name>
29833 <description>Filter bits</description>
29834 <bitOffset>8</bitOffset>
29835 <bitWidth>1</bitWidth>
29836 </field>
29837 <field>
29838 <name>FB9</name>
29839 <description>Filter bits</description>
29840 <bitOffset>9</bitOffset>
29841 <bitWidth>1</bitWidth>
29842 </field>
29843 <field>
29844 <name>FB10</name>
29845 <description>Filter bits</description>
29846 <bitOffset>10</bitOffset>
29847 <bitWidth>1</bitWidth>
29848 </field>
29849 <field>
29850 <name>FB11</name>
29851 <description>Filter bits</description>
29852 <bitOffset>11</bitOffset>
29853 <bitWidth>1</bitWidth>
29854 </field>
29855 <field>
29856 <name>FB12</name>
29857 <description>Filter bits</description>
29858 <bitOffset>12</bitOffset>
29859 <bitWidth>1</bitWidth>
29860 </field>
29861 <field>
29862 <name>FB13</name>
29863 <description>Filter bits</description>
29864 <bitOffset>13</bitOffset>
29865 <bitWidth>1</bitWidth>
29866 </field>
29867 <field>
29868 <name>FB14</name>
29869 <description>Filter bits</description>
29870 <bitOffset>14</bitOffset>
29871 <bitWidth>1</bitWidth>
29872 </field>
29873 <field>
29874 <name>FB15</name>
29875 <description>Filter bits</description>
29876 <bitOffset>15</bitOffset>
29877 <bitWidth>1</bitWidth>
29878 </field>
29879 <field>
29880 <name>FB16</name>
29881 <description>Filter bits</description>
29882 <bitOffset>16</bitOffset>
29883 <bitWidth>1</bitWidth>
29884 </field>
29885 <field>
29886 <name>FB17</name>
29887 <description>Filter bits</description>
29888 <bitOffset>17</bitOffset>
29889 <bitWidth>1</bitWidth>
29890 </field>
29891 <field>
29892 <name>FB18</name>
29893 <description>Filter bits</description>
29894 <bitOffset>18</bitOffset>
29895 <bitWidth>1</bitWidth>
29896 </field>
29897 <field>
29898 <name>FB19</name>
29899 <description>Filter bits</description>
29900 <bitOffset>19</bitOffset>
29901 <bitWidth>1</bitWidth>
29902 </field>
29903 <field>
29904 <name>FB20</name>
29905 <description>Filter bits</description>
29906 <bitOffset>20</bitOffset>
29907 <bitWidth>1</bitWidth>
29908 </field>
29909 <field>
29910 <name>FB21</name>
29911 <description>Filter bits</description>
29912 <bitOffset>21</bitOffset>
29913 <bitWidth>1</bitWidth>
29914 </field>
29915 <field>
29916 <name>FB22</name>
29917 <description>Filter bits</description>
29918 <bitOffset>22</bitOffset>
29919 <bitWidth>1</bitWidth>
29920 </field>
29921 <field>
29922 <name>FB23</name>
29923 <description>Filter bits</description>
29924 <bitOffset>23</bitOffset>
29925 <bitWidth>1</bitWidth>
29926 </field>
29927 <field>
29928 <name>FB24</name>
29929 <description>Filter bits</description>
29930 <bitOffset>24</bitOffset>
29931 <bitWidth>1</bitWidth>
29932 </field>
29933 <field>
29934 <name>FB25</name>
29935 <description>Filter bits</description>
29936 <bitOffset>25</bitOffset>
29937 <bitWidth>1</bitWidth>
29938 </field>
29939 <field>
29940 <name>FB26</name>
29941 <description>Filter bits</description>
29942 <bitOffset>26</bitOffset>
29943 <bitWidth>1</bitWidth>
29944 </field>
29945 <field>
29946 <name>FB27</name>
29947 <description>Filter bits</description>
29948 <bitOffset>27</bitOffset>
29949 <bitWidth>1</bitWidth>
29950 </field>
29951 <field>
29952 <name>FB28</name>
29953 <description>Filter bits</description>
29954 <bitOffset>28</bitOffset>
29955 <bitWidth>1</bitWidth>
29956 </field>
29957 <field>
29958 <name>FB29</name>
29959 <description>Filter bits</description>
29960 <bitOffset>29</bitOffset>
29961 <bitWidth>1</bitWidth>
29962 </field>
29963 <field>
29964 <name>FB30</name>
29965 <description>Filter bits</description>
29966 <bitOffset>30</bitOffset>
29967 <bitWidth>1</bitWidth>
29968 </field>
29969 <field>
29970 <name>FB31</name>
29971 <description>Filter bits</description>
29972 <bitOffset>31</bitOffset>
29973 <bitWidth>1</bitWidth>
29974 </field>
29975 </fields>
29976 </register>
29977 <register>
29978 <name>F3R2</name>
29979 <displayName>F3R2</displayName>
29980 <description>Filter bank 3 register 2</description>
29981 <addressOffset>0x25C</addressOffset>
29982 <size>0x20</size>
29983 <access>read-write</access>
29984 <resetValue>0x00000000</resetValue>
29985 <fields>
29986 <field>
29987 <name>FB0</name>
29988 <description>Filter bits</description>
29989 <bitOffset>0</bitOffset>
29990 <bitWidth>1</bitWidth>
29991 </field>
29992 <field>
29993 <name>FB1</name>
29994 <description>Filter bits</description>
29995 <bitOffset>1</bitOffset>
29996 <bitWidth>1</bitWidth>
29997 </field>
29998 <field>
29999 <name>FB2</name>
30000 <description>Filter bits</description>
30001 <bitOffset>2</bitOffset>
30002 <bitWidth>1</bitWidth>
30003 </field>
30004 <field>
30005 <name>FB3</name>
30006 <description>Filter bits</description>
30007 <bitOffset>3</bitOffset>
30008 <bitWidth>1</bitWidth>
30009 </field>
30010 <field>
30011 <name>FB4</name>
30012 <description>Filter bits</description>
30013 <bitOffset>4</bitOffset>
30014 <bitWidth>1</bitWidth>
30015 </field>
30016 <field>
30017 <name>FB5</name>
30018 <description>Filter bits</description>
30019 <bitOffset>5</bitOffset>
30020 <bitWidth>1</bitWidth>
30021 </field>
30022 <field>
30023 <name>FB6</name>
30024 <description>Filter bits</description>
30025 <bitOffset>6</bitOffset>
30026 <bitWidth>1</bitWidth>
30027 </field>
30028 <field>
30029 <name>FB7</name>
30030 <description>Filter bits</description>
30031 <bitOffset>7</bitOffset>
30032 <bitWidth>1</bitWidth>
30033 </field>
30034 <field>
30035 <name>FB8</name>
30036 <description>Filter bits</description>
30037 <bitOffset>8</bitOffset>
30038 <bitWidth>1</bitWidth>
30039 </field>
30040 <field>
30041 <name>FB9</name>
30042 <description>Filter bits</description>
30043 <bitOffset>9</bitOffset>
30044 <bitWidth>1</bitWidth>
30045 </field>
30046 <field>
30047 <name>FB10</name>
30048 <description>Filter bits</description>
30049 <bitOffset>10</bitOffset>
30050 <bitWidth>1</bitWidth>
30051 </field>
30052 <field>
30053 <name>FB11</name>
30054 <description>Filter bits</description>
30055 <bitOffset>11</bitOffset>
30056 <bitWidth>1</bitWidth>
30057 </field>
30058 <field>
30059 <name>FB12</name>
30060 <description>Filter bits</description>
30061 <bitOffset>12</bitOffset>
30062 <bitWidth>1</bitWidth>
30063 </field>
30064 <field>
30065 <name>FB13</name>
30066 <description>Filter bits</description>
30067 <bitOffset>13</bitOffset>
30068 <bitWidth>1</bitWidth>
30069 </field>
30070 <field>
30071 <name>FB14</name>
30072 <description>Filter bits</description>
30073 <bitOffset>14</bitOffset>
30074 <bitWidth>1</bitWidth>
30075 </field>
30076 <field>
30077 <name>FB15</name>
30078 <description>Filter bits</description>
30079 <bitOffset>15</bitOffset>
30080 <bitWidth>1</bitWidth>
30081 </field>
30082 <field>
30083 <name>FB16</name>
30084 <description>Filter bits</description>
30085 <bitOffset>16</bitOffset>
30086 <bitWidth>1</bitWidth>
30087 </field>
30088 <field>
30089 <name>FB17</name>
30090 <description>Filter bits</description>
30091 <bitOffset>17</bitOffset>
30092 <bitWidth>1</bitWidth>
30093 </field>
30094 <field>
30095 <name>FB18</name>
30096 <description>Filter bits</description>
30097 <bitOffset>18</bitOffset>
30098 <bitWidth>1</bitWidth>
30099 </field>
30100 <field>
30101 <name>FB19</name>
30102 <description>Filter bits</description>
30103 <bitOffset>19</bitOffset>
30104 <bitWidth>1</bitWidth>
30105 </field>
30106 <field>
30107 <name>FB20</name>
30108 <description>Filter bits</description>
30109 <bitOffset>20</bitOffset>
30110 <bitWidth>1</bitWidth>
30111 </field>
30112 <field>
30113 <name>FB21</name>
30114 <description>Filter bits</description>
30115 <bitOffset>21</bitOffset>
30116 <bitWidth>1</bitWidth>
30117 </field>
30118 <field>
30119 <name>FB22</name>
30120 <description>Filter bits</description>
30121 <bitOffset>22</bitOffset>
30122 <bitWidth>1</bitWidth>
30123 </field>
30124 <field>
30125 <name>FB23</name>
30126 <description>Filter bits</description>
30127 <bitOffset>23</bitOffset>
30128 <bitWidth>1</bitWidth>
30129 </field>
30130 <field>
30131 <name>FB24</name>
30132 <description>Filter bits</description>
30133 <bitOffset>24</bitOffset>
30134 <bitWidth>1</bitWidth>
30135 </field>
30136 <field>
30137 <name>FB25</name>
30138 <description>Filter bits</description>
30139 <bitOffset>25</bitOffset>
30140 <bitWidth>1</bitWidth>
30141 </field>
30142 <field>
30143 <name>FB26</name>
30144 <description>Filter bits</description>
30145 <bitOffset>26</bitOffset>
30146 <bitWidth>1</bitWidth>
30147 </field>
30148 <field>
30149 <name>FB27</name>
30150 <description>Filter bits</description>
30151 <bitOffset>27</bitOffset>
30152 <bitWidth>1</bitWidth>
30153 </field>
30154 <field>
30155 <name>FB28</name>
30156 <description>Filter bits</description>
30157 <bitOffset>28</bitOffset>
30158 <bitWidth>1</bitWidth>
30159 </field>
30160 <field>
30161 <name>FB29</name>
30162 <description>Filter bits</description>
30163 <bitOffset>29</bitOffset>
30164 <bitWidth>1</bitWidth>
30165 </field>
30166 <field>
30167 <name>FB30</name>
30168 <description>Filter bits</description>
30169 <bitOffset>30</bitOffset>
30170 <bitWidth>1</bitWidth>
30171 </field>
30172 <field>
30173 <name>FB31</name>
30174 <description>Filter bits</description>
30175 <bitOffset>31</bitOffset>
30176 <bitWidth>1</bitWidth>
30177 </field>
30178 </fields>
30179 </register>
30180 <register>
30181 <name>F4R1</name>
30182 <displayName>F4R1</displayName>
30183 <description>Filter bank 4 register 1</description>
30184 <addressOffset>0x260</addressOffset>
30185 <size>0x20</size>
30186 <access>read-write</access>
30187 <resetValue>0x00000000</resetValue>
30188 <fields>
30189 <field>
30190 <name>FB0</name>
30191 <description>Filter bits</description>
30192 <bitOffset>0</bitOffset>
30193 <bitWidth>1</bitWidth>
30194 </field>
30195 <field>
30196 <name>FB1</name>
30197 <description>Filter bits</description>
30198 <bitOffset>1</bitOffset>
30199 <bitWidth>1</bitWidth>
30200 </field>
30201 <field>
30202 <name>FB2</name>
30203 <description>Filter bits</description>
30204 <bitOffset>2</bitOffset>
30205 <bitWidth>1</bitWidth>
30206 </field>
30207 <field>
30208 <name>FB3</name>
30209 <description>Filter bits</description>
30210 <bitOffset>3</bitOffset>
30211 <bitWidth>1</bitWidth>
30212 </field>
30213 <field>
30214 <name>FB4</name>
30215 <description>Filter bits</description>
30216 <bitOffset>4</bitOffset>
30217 <bitWidth>1</bitWidth>
30218 </field>
30219 <field>
30220 <name>FB5</name>
30221 <description>Filter bits</description>
30222 <bitOffset>5</bitOffset>
30223 <bitWidth>1</bitWidth>
30224 </field>
30225 <field>
30226 <name>FB6</name>
30227 <description>Filter bits</description>
30228 <bitOffset>6</bitOffset>
30229 <bitWidth>1</bitWidth>
30230 </field>
30231 <field>
30232 <name>FB7</name>
30233 <description>Filter bits</description>
30234 <bitOffset>7</bitOffset>
30235 <bitWidth>1</bitWidth>
30236 </field>
30237 <field>
30238 <name>FB8</name>
30239 <description>Filter bits</description>
30240 <bitOffset>8</bitOffset>
30241 <bitWidth>1</bitWidth>
30242 </field>
30243 <field>
30244 <name>FB9</name>
30245 <description>Filter bits</description>
30246 <bitOffset>9</bitOffset>
30247 <bitWidth>1</bitWidth>
30248 </field>
30249 <field>
30250 <name>FB10</name>
30251 <description>Filter bits</description>
30252 <bitOffset>10</bitOffset>
30253 <bitWidth>1</bitWidth>
30254 </field>
30255 <field>
30256 <name>FB11</name>
30257 <description>Filter bits</description>
30258 <bitOffset>11</bitOffset>
30259 <bitWidth>1</bitWidth>
30260 </field>
30261 <field>
30262 <name>FB12</name>
30263 <description>Filter bits</description>
30264 <bitOffset>12</bitOffset>
30265 <bitWidth>1</bitWidth>
30266 </field>
30267 <field>
30268 <name>FB13</name>
30269 <description>Filter bits</description>
30270 <bitOffset>13</bitOffset>
30271 <bitWidth>1</bitWidth>
30272 </field>
30273 <field>
30274 <name>FB14</name>
30275 <description>Filter bits</description>
30276 <bitOffset>14</bitOffset>
30277 <bitWidth>1</bitWidth>
30278 </field>
30279 <field>
30280 <name>FB15</name>
30281 <description>Filter bits</description>
30282 <bitOffset>15</bitOffset>
30283 <bitWidth>1</bitWidth>
30284 </field>
30285 <field>
30286 <name>FB16</name>
30287 <description>Filter bits</description>
30288 <bitOffset>16</bitOffset>
30289 <bitWidth>1</bitWidth>
30290 </field>
30291 <field>
30292 <name>FB17</name>
30293 <description>Filter bits</description>
30294 <bitOffset>17</bitOffset>
30295 <bitWidth>1</bitWidth>
30296 </field>
30297 <field>
30298 <name>FB18</name>
30299 <description>Filter bits</description>
30300 <bitOffset>18</bitOffset>
30301 <bitWidth>1</bitWidth>
30302 </field>
30303 <field>
30304 <name>FB19</name>
30305 <description>Filter bits</description>
30306 <bitOffset>19</bitOffset>
30307 <bitWidth>1</bitWidth>
30308 </field>
30309 <field>
30310 <name>FB20</name>
30311 <description>Filter bits</description>
30312 <bitOffset>20</bitOffset>
30313 <bitWidth>1</bitWidth>
30314 </field>
30315 <field>
30316 <name>FB21</name>
30317 <description>Filter bits</description>
30318 <bitOffset>21</bitOffset>
30319 <bitWidth>1</bitWidth>
30320 </field>
30321 <field>
30322 <name>FB22</name>
30323 <description>Filter bits</description>
30324 <bitOffset>22</bitOffset>
30325 <bitWidth>1</bitWidth>
30326 </field>
30327 <field>
30328 <name>FB23</name>
30329 <description>Filter bits</description>
30330 <bitOffset>23</bitOffset>
30331 <bitWidth>1</bitWidth>
30332 </field>
30333 <field>
30334 <name>FB24</name>
30335 <description>Filter bits</description>
30336 <bitOffset>24</bitOffset>
30337 <bitWidth>1</bitWidth>
30338 </field>
30339 <field>
30340 <name>FB25</name>
30341 <description>Filter bits</description>
30342 <bitOffset>25</bitOffset>
30343 <bitWidth>1</bitWidth>
30344 </field>
30345 <field>
30346 <name>FB26</name>
30347 <description>Filter bits</description>
30348 <bitOffset>26</bitOffset>
30349 <bitWidth>1</bitWidth>
30350 </field>
30351 <field>
30352 <name>FB27</name>
30353 <description>Filter bits</description>
30354 <bitOffset>27</bitOffset>
30355 <bitWidth>1</bitWidth>
30356 </field>
30357 <field>
30358 <name>FB28</name>
30359 <description>Filter bits</description>
30360 <bitOffset>28</bitOffset>
30361 <bitWidth>1</bitWidth>
30362 </field>
30363 <field>
30364 <name>FB29</name>
30365 <description>Filter bits</description>
30366 <bitOffset>29</bitOffset>
30367 <bitWidth>1</bitWidth>
30368 </field>
30369 <field>
30370 <name>FB30</name>
30371 <description>Filter bits</description>
30372 <bitOffset>30</bitOffset>
30373 <bitWidth>1</bitWidth>
30374 </field>
30375 <field>
30376 <name>FB31</name>
30377 <description>Filter bits</description>
30378 <bitOffset>31</bitOffset>
30379 <bitWidth>1</bitWidth>
30380 </field>
30381 </fields>
30382 </register>
30383 <register>
30384 <name>F4R2</name>
30385 <displayName>F4R2</displayName>
30386 <description>Filter bank 4 register 2</description>
30387 <addressOffset>0x264</addressOffset>
30388 <size>0x20</size>
30389 <access>read-write</access>
30390 <resetValue>0x00000000</resetValue>
30391 <fields>
30392 <field>
30393 <name>FB0</name>
30394 <description>Filter bits</description>
30395 <bitOffset>0</bitOffset>
30396 <bitWidth>1</bitWidth>
30397 </field>
30398 <field>
30399 <name>FB1</name>
30400 <description>Filter bits</description>
30401 <bitOffset>1</bitOffset>
30402 <bitWidth>1</bitWidth>
30403 </field>
30404 <field>
30405 <name>FB2</name>
30406 <description>Filter bits</description>
30407 <bitOffset>2</bitOffset>
30408 <bitWidth>1</bitWidth>
30409 </field>
30410 <field>
30411 <name>FB3</name>
30412 <description>Filter bits</description>
30413 <bitOffset>3</bitOffset>
30414 <bitWidth>1</bitWidth>
30415 </field>
30416 <field>
30417 <name>FB4</name>
30418 <description>Filter bits</description>
30419 <bitOffset>4</bitOffset>
30420 <bitWidth>1</bitWidth>
30421 </field>
30422 <field>
30423 <name>FB5</name>
30424 <description>Filter bits</description>
30425 <bitOffset>5</bitOffset>
30426 <bitWidth>1</bitWidth>
30427 </field>
30428 <field>
30429 <name>FB6</name>
30430 <description>Filter bits</description>
30431 <bitOffset>6</bitOffset>
30432 <bitWidth>1</bitWidth>
30433 </field>
30434 <field>
30435 <name>FB7</name>
30436 <description>Filter bits</description>
30437 <bitOffset>7</bitOffset>
30438 <bitWidth>1</bitWidth>
30439 </field>
30440 <field>
30441 <name>FB8</name>
30442 <description>Filter bits</description>
30443 <bitOffset>8</bitOffset>
30444 <bitWidth>1</bitWidth>
30445 </field>
30446 <field>
30447 <name>FB9</name>
30448 <description>Filter bits</description>
30449 <bitOffset>9</bitOffset>
30450 <bitWidth>1</bitWidth>
30451 </field>
30452 <field>
30453 <name>FB10</name>
30454 <description>Filter bits</description>
30455 <bitOffset>10</bitOffset>
30456 <bitWidth>1</bitWidth>
30457 </field>
30458 <field>
30459 <name>FB11</name>
30460 <description>Filter bits</description>
30461 <bitOffset>11</bitOffset>
30462 <bitWidth>1</bitWidth>
30463 </field>
30464 <field>
30465 <name>FB12</name>
30466 <description>Filter bits</description>
30467 <bitOffset>12</bitOffset>
30468 <bitWidth>1</bitWidth>
30469 </field>
30470 <field>
30471 <name>FB13</name>
30472 <description>Filter bits</description>
30473 <bitOffset>13</bitOffset>
30474 <bitWidth>1</bitWidth>
30475 </field>
30476 <field>
30477 <name>FB14</name>
30478 <description>Filter bits</description>
30479 <bitOffset>14</bitOffset>
30480 <bitWidth>1</bitWidth>
30481 </field>
30482 <field>
30483 <name>FB15</name>
30484 <description>Filter bits</description>
30485 <bitOffset>15</bitOffset>
30486 <bitWidth>1</bitWidth>
30487 </field>
30488 <field>
30489 <name>FB16</name>
30490 <description>Filter bits</description>
30491 <bitOffset>16</bitOffset>
30492 <bitWidth>1</bitWidth>
30493 </field>
30494 <field>
30495 <name>FB17</name>
30496 <description>Filter bits</description>
30497 <bitOffset>17</bitOffset>
30498 <bitWidth>1</bitWidth>
30499 </field>
30500 <field>
30501 <name>FB18</name>
30502 <description>Filter bits</description>
30503 <bitOffset>18</bitOffset>
30504 <bitWidth>1</bitWidth>
30505 </field>
30506 <field>
30507 <name>FB19</name>
30508 <description>Filter bits</description>
30509 <bitOffset>19</bitOffset>
30510 <bitWidth>1</bitWidth>
30511 </field>
30512 <field>
30513 <name>FB20</name>
30514 <description>Filter bits</description>
30515 <bitOffset>20</bitOffset>
30516 <bitWidth>1</bitWidth>
30517 </field>
30518 <field>
30519 <name>FB21</name>
30520 <description>Filter bits</description>
30521 <bitOffset>21</bitOffset>
30522 <bitWidth>1</bitWidth>
30523 </field>
30524 <field>
30525 <name>FB22</name>
30526 <description>Filter bits</description>
30527 <bitOffset>22</bitOffset>
30528 <bitWidth>1</bitWidth>
30529 </field>
30530 <field>
30531 <name>FB23</name>
30532 <description>Filter bits</description>
30533 <bitOffset>23</bitOffset>
30534 <bitWidth>1</bitWidth>
30535 </field>
30536 <field>
30537 <name>FB24</name>
30538 <description>Filter bits</description>
30539 <bitOffset>24</bitOffset>
30540 <bitWidth>1</bitWidth>
30541 </field>
30542 <field>
30543 <name>FB25</name>
30544 <description>Filter bits</description>
30545 <bitOffset>25</bitOffset>
30546 <bitWidth>1</bitWidth>
30547 </field>
30548 <field>
30549 <name>FB26</name>
30550 <description>Filter bits</description>
30551 <bitOffset>26</bitOffset>
30552 <bitWidth>1</bitWidth>
30553 </field>
30554 <field>
30555 <name>FB27</name>
30556 <description>Filter bits</description>
30557 <bitOffset>27</bitOffset>
30558 <bitWidth>1</bitWidth>
30559 </field>
30560 <field>
30561 <name>FB28</name>
30562 <description>Filter bits</description>
30563 <bitOffset>28</bitOffset>
30564 <bitWidth>1</bitWidth>
30565 </field>
30566 <field>
30567 <name>FB29</name>
30568 <description>Filter bits</description>
30569 <bitOffset>29</bitOffset>
30570 <bitWidth>1</bitWidth>
30571 </field>
30572 <field>
30573 <name>FB30</name>
30574 <description>Filter bits</description>
30575 <bitOffset>30</bitOffset>
30576 <bitWidth>1</bitWidth>
30577 </field>
30578 <field>
30579 <name>FB31</name>
30580 <description>Filter bits</description>
30581 <bitOffset>31</bitOffset>
30582 <bitWidth>1</bitWidth>
30583 </field>
30584 </fields>
30585 </register>
30586 <register>
30587 <name>F5R1</name>
30588 <displayName>F5R1</displayName>
30589 <description>Filter bank 5 register 1</description>
30590 <addressOffset>0x268</addressOffset>
30591 <size>0x20</size>
30592 <access>read-write</access>
30593 <resetValue>0x00000000</resetValue>
30594 <fields>
30595 <field>
30596 <name>FB0</name>
30597 <description>Filter bits</description>
30598 <bitOffset>0</bitOffset>
30599 <bitWidth>1</bitWidth>
30600 </field>
30601 <field>
30602 <name>FB1</name>
30603 <description>Filter bits</description>
30604 <bitOffset>1</bitOffset>
30605 <bitWidth>1</bitWidth>
30606 </field>
30607 <field>
30608 <name>FB2</name>
30609 <description>Filter bits</description>
30610 <bitOffset>2</bitOffset>
30611 <bitWidth>1</bitWidth>
30612 </field>
30613 <field>
30614 <name>FB3</name>
30615 <description>Filter bits</description>
30616 <bitOffset>3</bitOffset>
30617 <bitWidth>1</bitWidth>
30618 </field>
30619 <field>
30620 <name>FB4</name>
30621 <description>Filter bits</description>
30622 <bitOffset>4</bitOffset>
30623 <bitWidth>1</bitWidth>
30624 </field>
30625 <field>
30626 <name>FB5</name>
30627 <description>Filter bits</description>
30628 <bitOffset>5</bitOffset>
30629 <bitWidth>1</bitWidth>
30630 </field>
30631 <field>
30632 <name>FB6</name>
30633 <description>Filter bits</description>
30634 <bitOffset>6</bitOffset>
30635 <bitWidth>1</bitWidth>
30636 </field>
30637 <field>
30638 <name>FB7</name>
30639 <description>Filter bits</description>
30640 <bitOffset>7</bitOffset>
30641 <bitWidth>1</bitWidth>
30642 </field>
30643 <field>
30644 <name>FB8</name>
30645 <description>Filter bits</description>
30646 <bitOffset>8</bitOffset>
30647 <bitWidth>1</bitWidth>
30648 </field>
30649 <field>
30650 <name>FB9</name>
30651 <description>Filter bits</description>
30652 <bitOffset>9</bitOffset>
30653 <bitWidth>1</bitWidth>
30654 </field>
30655 <field>
30656 <name>FB10</name>
30657 <description>Filter bits</description>
30658 <bitOffset>10</bitOffset>
30659 <bitWidth>1</bitWidth>
30660 </field>
30661 <field>
30662 <name>FB11</name>
30663 <description>Filter bits</description>
30664 <bitOffset>11</bitOffset>
30665 <bitWidth>1</bitWidth>
30666 </field>
30667 <field>
30668 <name>FB12</name>
30669 <description>Filter bits</description>
30670 <bitOffset>12</bitOffset>
30671 <bitWidth>1</bitWidth>
30672 </field>
30673 <field>
30674 <name>FB13</name>
30675 <description>Filter bits</description>
30676 <bitOffset>13</bitOffset>
30677 <bitWidth>1</bitWidth>
30678 </field>
30679 <field>
30680 <name>FB14</name>
30681 <description>Filter bits</description>
30682 <bitOffset>14</bitOffset>
30683 <bitWidth>1</bitWidth>
30684 </field>
30685 <field>
30686 <name>FB15</name>
30687 <description>Filter bits</description>
30688 <bitOffset>15</bitOffset>
30689 <bitWidth>1</bitWidth>
30690 </field>
30691 <field>
30692 <name>FB16</name>
30693 <description>Filter bits</description>
30694 <bitOffset>16</bitOffset>
30695 <bitWidth>1</bitWidth>
30696 </field>
30697 <field>
30698 <name>FB17</name>
30699 <description>Filter bits</description>
30700 <bitOffset>17</bitOffset>
30701 <bitWidth>1</bitWidth>
30702 </field>
30703 <field>
30704 <name>FB18</name>
30705 <description>Filter bits</description>
30706 <bitOffset>18</bitOffset>
30707 <bitWidth>1</bitWidth>
30708 </field>
30709 <field>
30710 <name>FB19</name>
30711 <description>Filter bits</description>
30712 <bitOffset>19</bitOffset>
30713 <bitWidth>1</bitWidth>
30714 </field>
30715 <field>
30716 <name>FB20</name>
30717 <description>Filter bits</description>
30718 <bitOffset>20</bitOffset>
30719 <bitWidth>1</bitWidth>
30720 </field>
30721 <field>
30722 <name>FB21</name>
30723 <description>Filter bits</description>
30724 <bitOffset>21</bitOffset>
30725 <bitWidth>1</bitWidth>
30726 </field>
30727 <field>
30728 <name>FB22</name>
30729 <description>Filter bits</description>
30730 <bitOffset>22</bitOffset>
30731 <bitWidth>1</bitWidth>
30732 </field>
30733 <field>
30734 <name>FB23</name>
30735 <description>Filter bits</description>
30736 <bitOffset>23</bitOffset>
30737 <bitWidth>1</bitWidth>
30738 </field>
30739 <field>
30740 <name>FB24</name>
30741 <description>Filter bits</description>
30742 <bitOffset>24</bitOffset>
30743 <bitWidth>1</bitWidth>
30744 </field>
30745 <field>
30746 <name>FB25</name>
30747 <description>Filter bits</description>
30748 <bitOffset>25</bitOffset>
30749 <bitWidth>1</bitWidth>
30750 </field>
30751 <field>
30752 <name>FB26</name>
30753 <description>Filter bits</description>
30754 <bitOffset>26</bitOffset>
30755 <bitWidth>1</bitWidth>
30756 </field>
30757 <field>
30758 <name>FB27</name>
30759 <description>Filter bits</description>
30760 <bitOffset>27</bitOffset>
30761 <bitWidth>1</bitWidth>
30762 </field>
30763 <field>
30764 <name>FB28</name>
30765 <description>Filter bits</description>
30766 <bitOffset>28</bitOffset>
30767 <bitWidth>1</bitWidth>
30768 </field>
30769 <field>
30770 <name>FB29</name>
30771 <description>Filter bits</description>
30772 <bitOffset>29</bitOffset>
30773 <bitWidth>1</bitWidth>
30774 </field>
30775 <field>
30776 <name>FB30</name>
30777 <description>Filter bits</description>
30778 <bitOffset>30</bitOffset>
30779 <bitWidth>1</bitWidth>
30780 </field>
30781 <field>
30782 <name>FB31</name>
30783 <description>Filter bits</description>
30784 <bitOffset>31</bitOffset>
30785 <bitWidth>1</bitWidth>
30786 </field>
30787 </fields>
30788 </register>
30789 <register>
30790 <name>F5R2</name>
30791 <displayName>F5R2</displayName>
30792 <description>Filter bank 5 register 2</description>
30793 <addressOffset>0x26C</addressOffset>
30794 <size>0x20</size>
30795 <access>read-write</access>
30796 <resetValue>0x00000000</resetValue>
30797 <fields>
30798 <field>
30799 <name>FB0</name>
30800 <description>Filter bits</description>
30801 <bitOffset>0</bitOffset>
30802 <bitWidth>1</bitWidth>
30803 </field>
30804 <field>
30805 <name>FB1</name>
30806 <description>Filter bits</description>
30807 <bitOffset>1</bitOffset>
30808 <bitWidth>1</bitWidth>
30809 </field>
30810 <field>
30811 <name>FB2</name>
30812 <description>Filter bits</description>
30813 <bitOffset>2</bitOffset>
30814 <bitWidth>1</bitWidth>
30815 </field>
30816 <field>
30817 <name>FB3</name>
30818 <description>Filter bits</description>
30819 <bitOffset>3</bitOffset>
30820 <bitWidth>1</bitWidth>
30821 </field>
30822 <field>
30823 <name>FB4</name>
30824 <description>Filter bits</description>
30825 <bitOffset>4</bitOffset>
30826 <bitWidth>1</bitWidth>
30827 </field>
30828 <field>
30829 <name>FB5</name>
30830 <description>Filter bits</description>
30831 <bitOffset>5</bitOffset>
30832 <bitWidth>1</bitWidth>
30833 </field>
30834 <field>
30835 <name>FB6</name>
30836 <description>Filter bits</description>
30837 <bitOffset>6</bitOffset>
30838 <bitWidth>1</bitWidth>
30839 </field>
30840 <field>
30841 <name>FB7</name>
30842 <description>Filter bits</description>
30843 <bitOffset>7</bitOffset>
30844 <bitWidth>1</bitWidth>
30845 </field>
30846 <field>
30847 <name>FB8</name>
30848 <description>Filter bits</description>
30849 <bitOffset>8</bitOffset>
30850 <bitWidth>1</bitWidth>
30851 </field>
30852 <field>
30853 <name>FB9</name>
30854 <description>Filter bits</description>
30855 <bitOffset>9</bitOffset>
30856 <bitWidth>1</bitWidth>
30857 </field>
30858 <field>
30859 <name>FB10</name>
30860 <description>Filter bits</description>
30861 <bitOffset>10</bitOffset>
30862 <bitWidth>1</bitWidth>
30863 </field>
30864 <field>
30865 <name>FB11</name>
30866 <description>Filter bits</description>
30867 <bitOffset>11</bitOffset>
30868 <bitWidth>1</bitWidth>
30869 </field>
30870 <field>
30871 <name>FB12</name>
30872 <description>Filter bits</description>
30873 <bitOffset>12</bitOffset>
30874 <bitWidth>1</bitWidth>
30875 </field>
30876 <field>
30877 <name>FB13</name>
30878 <description>Filter bits</description>
30879 <bitOffset>13</bitOffset>
30880 <bitWidth>1</bitWidth>
30881 </field>
30882 <field>
30883 <name>FB14</name>
30884 <description>Filter bits</description>
30885 <bitOffset>14</bitOffset>
30886 <bitWidth>1</bitWidth>
30887 </field>
30888 <field>
30889 <name>FB15</name>
30890 <description>Filter bits</description>
30891 <bitOffset>15</bitOffset>
30892 <bitWidth>1</bitWidth>
30893 </field>
30894 <field>
30895 <name>FB16</name>
30896 <description>Filter bits</description>
30897 <bitOffset>16</bitOffset>
30898 <bitWidth>1</bitWidth>
30899 </field>
30900 <field>
30901 <name>FB17</name>
30902 <description>Filter bits</description>
30903 <bitOffset>17</bitOffset>
30904 <bitWidth>1</bitWidth>
30905 </field>
30906 <field>
30907 <name>FB18</name>
30908 <description>Filter bits</description>
30909 <bitOffset>18</bitOffset>
30910 <bitWidth>1</bitWidth>
30911 </field>
30912 <field>
30913 <name>FB19</name>
30914 <description>Filter bits</description>
30915 <bitOffset>19</bitOffset>
30916 <bitWidth>1</bitWidth>
30917 </field>
30918 <field>
30919 <name>FB20</name>
30920 <description>Filter bits</description>
30921 <bitOffset>20</bitOffset>
30922 <bitWidth>1</bitWidth>
30923 </field>
30924 <field>
30925 <name>FB21</name>
30926 <description>Filter bits</description>
30927 <bitOffset>21</bitOffset>
30928 <bitWidth>1</bitWidth>
30929 </field>
30930 <field>
30931 <name>FB22</name>
30932 <description>Filter bits</description>
30933 <bitOffset>22</bitOffset>
30934 <bitWidth>1</bitWidth>
30935 </field>
30936 <field>
30937 <name>FB23</name>
30938 <description>Filter bits</description>
30939 <bitOffset>23</bitOffset>
30940 <bitWidth>1</bitWidth>
30941 </field>
30942 <field>
30943 <name>FB24</name>
30944 <description>Filter bits</description>
30945 <bitOffset>24</bitOffset>
30946 <bitWidth>1</bitWidth>
30947 </field>
30948 <field>
30949 <name>FB25</name>
30950 <description>Filter bits</description>
30951 <bitOffset>25</bitOffset>
30952 <bitWidth>1</bitWidth>
30953 </field>
30954 <field>
30955 <name>FB26</name>
30956 <description>Filter bits</description>
30957 <bitOffset>26</bitOffset>
30958 <bitWidth>1</bitWidth>
30959 </field>
30960 <field>
30961 <name>FB27</name>
30962 <description>Filter bits</description>
30963 <bitOffset>27</bitOffset>
30964 <bitWidth>1</bitWidth>
30965 </field>
30966 <field>
30967 <name>FB28</name>
30968 <description>Filter bits</description>
30969 <bitOffset>28</bitOffset>
30970 <bitWidth>1</bitWidth>
30971 </field>
30972 <field>
30973 <name>FB29</name>
30974 <description>Filter bits</description>
30975 <bitOffset>29</bitOffset>
30976 <bitWidth>1</bitWidth>
30977 </field>
30978 <field>
30979 <name>FB30</name>
30980 <description>Filter bits</description>
30981 <bitOffset>30</bitOffset>
30982 <bitWidth>1</bitWidth>
30983 </field>
30984 <field>
30985 <name>FB31</name>
30986 <description>Filter bits</description>
30987 <bitOffset>31</bitOffset>
30988 <bitWidth>1</bitWidth>
30989 </field>
30990 </fields>
30991 </register>
30992 <register>
30993 <name>F6R1</name>
30994 <displayName>F6R1</displayName>
30995 <description>Filter bank 6 register 1</description>
30996 <addressOffset>0x270</addressOffset>
30997 <size>0x20</size>
30998 <access>read-write</access>
30999 <resetValue>0x00000000</resetValue>
31000 <fields>
31001 <field>
31002 <name>FB0</name>
31003 <description>Filter bits</description>
31004 <bitOffset>0</bitOffset>
31005 <bitWidth>1</bitWidth>
31006 </field>
31007 <field>
31008 <name>FB1</name>
31009 <description>Filter bits</description>
31010 <bitOffset>1</bitOffset>
31011 <bitWidth>1</bitWidth>
31012 </field>
31013 <field>
31014 <name>FB2</name>
31015 <description>Filter bits</description>
31016 <bitOffset>2</bitOffset>
31017 <bitWidth>1</bitWidth>
31018 </field>
31019 <field>
31020 <name>FB3</name>
31021 <description>Filter bits</description>
31022 <bitOffset>3</bitOffset>
31023 <bitWidth>1</bitWidth>
31024 </field>
31025 <field>
31026 <name>FB4</name>
31027 <description>Filter bits</description>
31028 <bitOffset>4</bitOffset>
31029 <bitWidth>1</bitWidth>
31030 </field>
31031 <field>
31032 <name>FB5</name>
31033 <description>Filter bits</description>
31034 <bitOffset>5</bitOffset>
31035 <bitWidth>1</bitWidth>
31036 </field>
31037 <field>
31038 <name>FB6</name>
31039 <description>Filter bits</description>
31040 <bitOffset>6</bitOffset>
31041 <bitWidth>1</bitWidth>
31042 </field>
31043 <field>
31044 <name>FB7</name>
31045 <description>Filter bits</description>
31046 <bitOffset>7</bitOffset>
31047 <bitWidth>1</bitWidth>
31048 </field>
31049 <field>
31050 <name>FB8</name>
31051 <description>Filter bits</description>
31052 <bitOffset>8</bitOffset>
31053 <bitWidth>1</bitWidth>
31054 </field>
31055 <field>
31056 <name>FB9</name>
31057 <description>Filter bits</description>
31058 <bitOffset>9</bitOffset>
31059 <bitWidth>1</bitWidth>
31060 </field>
31061 <field>
31062 <name>FB10</name>
31063 <description>Filter bits</description>
31064 <bitOffset>10</bitOffset>
31065 <bitWidth>1</bitWidth>
31066 </field>
31067 <field>
31068 <name>FB11</name>
31069 <description>Filter bits</description>
31070 <bitOffset>11</bitOffset>
31071 <bitWidth>1</bitWidth>
31072 </field>
31073 <field>
31074 <name>FB12</name>
31075 <description>Filter bits</description>
31076 <bitOffset>12</bitOffset>
31077 <bitWidth>1</bitWidth>
31078 </field>
31079 <field>
31080 <name>FB13</name>
31081 <description>Filter bits</description>
31082 <bitOffset>13</bitOffset>
31083 <bitWidth>1</bitWidth>
31084 </field>
31085 <field>
31086 <name>FB14</name>
31087 <description>Filter bits</description>
31088 <bitOffset>14</bitOffset>
31089 <bitWidth>1</bitWidth>
31090 </field>
31091 <field>
31092 <name>FB15</name>
31093 <description>Filter bits</description>
31094 <bitOffset>15</bitOffset>
31095 <bitWidth>1</bitWidth>
31096 </field>
31097 <field>
31098 <name>FB16</name>
31099 <description>Filter bits</description>
31100 <bitOffset>16</bitOffset>
31101 <bitWidth>1</bitWidth>
31102 </field>
31103 <field>
31104 <name>FB17</name>
31105 <description>Filter bits</description>
31106 <bitOffset>17</bitOffset>
31107 <bitWidth>1</bitWidth>
31108 </field>
31109 <field>
31110 <name>FB18</name>
31111 <description>Filter bits</description>
31112 <bitOffset>18</bitOffset>
31113 <bitWidth>1</bitWidth>
31114 </field>
31115 <field>
31116 <name>FB19</name>
31117 <description>Filter bits</description>
31118 <bitOffset>19</bitOffset>
31119 <bitWidth>1</bitWidth>
31120 </field>
31121 <field>
31122 <name>FB20</name>
31123 <description>Filter bits</description>
31124 <bitOffset>20</bitOffset>
31125 <bitWidth>1</bitWidth>
31126 </field>
31127 <field>
31128 <name>FB21</name>
31129 <description>Filter bits</description>
31130 <bitOffset>21</bitOffset>
31131 <bitWidth>1</bitWidth>
31132 </field>
31133 <field>
31134 <name>FB22</name>
31135 <description>Filter bits</description>
31136 <bitOffset>22</bitOffset>
31137 <bitWidth>1</bitWidth>
31138 </field>
31139 <field>
31140 <name>FB23</name>
31141 <description>Filter bits</description>
31142 <bitOffset>23</bitOffset>
31143 <bitWidth>1</bitWidth>
31144 </field>
31145 <field>
31146 <name>FB24</name>
31147 <description>Filter bits</description>
31148 <bitOffset>24</bitOffset>
31149 <bitWidth>1</bitWidth>
31150 </field>
31151 <field>
31152 <name>FB25</name>
31153 <description>Filter bits</description>
31154 <bitOffset>25</bitOffset>
31155 <bitWidth>1</bitWidth>
31156 </field>
31157 <field>
31158 <name>FB26</name>
31159 <description>Filter bits</description>
31160 <bitOffset>26</bitOffset>
31161 <bitWidth>1</bitWidth>
31162 </field>
31163 <field>
31164 <name>FB27</name>
31165 <description>Filter bits</description>
31166 <bitOffset>27</bitOffset>
31167 <bitWidth>1</bitWidth>
31168 </field>
31169 <field>
31170 <name>FB28</name>
31171 <description>Filter bits</description>
31172 <bitOffset>28</bitOffset>
31173 <bitWidth>1</bitWidth>
31174 </field>
31175 <field>
31176 <name>FB29</name>
31177 <description>Filter bits</description>
31178 <bitOffset>29</bitOffset>
31179 <bitWidth>1</bitWidth>
31180 </field>
31181 <field>
31182 <name>FB30</name>
31183 <description>Filter bits</description>
31184 <bitOffset>30</bitOffset>
31185 <bitWidth>1</bitWidth>
31186 </field>
31187 <field>
31188 <name>FB31</name>
31189 <description>Filter bits</description>
31190 <bitOffset>31</bitOffset>
31191 <bitWidth>1</bitWidth>
31192 </field>
31193 </fields>
31194 </register>
31195 <register>
31196 <name>F6R2</name>
31197 <displayName>F6R2</displayName>
31198 <description>Filter bank 6 register 2</description>
31199 <addressOffset>0x274</addressOffset>
31200 <size>0x20</size>
31201 <access>read-write</access>
31202 <resetValue>0x00000000</resetValue>
31203 <fields>
31204 <field>
31205 <name>FB0</name>
31206 <description>Filter bits</description>
31207 <bitOffset>0</bitOffset>
31208 <bitWidth>1</bitWidth>
31209 </field>
31210 <field>
31211 <name>FB1</name>
31212 <description>Filter bits</description>
31213 <bitOffset>1</bitOffset>
31214 <bitWidth>1</bitWidth>
31215 </field>
31216 <field>
31217 <name>FB2</name>
31218 <description>Filter bits</description>
31219 <bitOffset>2</bitOffset>
31220 <bitWidth>1</bitWidth>
31221 </field>
31222 <field>
31223 <name>FB3</name>
31224 <description>Filter bits</description>
31225 <bitOffset>3</bitOffset>
31226 <bitWidth>1</bitWidth>
31227 </field>
31228 <field>
31229 <name>FB4</name>
31230 <description>Filter bits</description>
31231 <bitOffset>4</bitOffset>
31232 <bitWidth>1</bitWidth>
31233 </field>
31234 <field>
31235 <name>FB5</name>
31236 <description>Filter bits</description>
31237 <bitOffset>5</bitOffset>
31238 <bitWidth>1</bitWidth>
31239 </field>
31240 <field>
31241 <name>FB6</name>
31242 <description>Filter bits</description>
31243 <bitOffset>6</bitOffset>
31244 <bitWidth>1</bitWidth>
31245 </field>
31246 <field>
31247 <name>FB7</name>
31248 <description>Filter bits</description>
31249 <bitOffset>7</bitOffset>
31250 <bitWidth>1</bitWidth>
31251 </field>
31252 <field>
31253 <name>FB8</name>
31254 <description>Filter bits</description>
31255 <bitOffset>8</bitOffset>
31256 <bitWidth>1</bitWidth>
31257 </field>
31258 <field>
31259 <name>FB9</name>
31260 <description>Filter bits</description>
31261 <bitOffset>9</bitOffset>
31262 <bitWidth>1</bitWidth>
31263 </field>
31264 <field>
31265 <name>FB10</name>
31266 <description>Filter bits</description>
31267 <bitOffset>10</bitOffset>
31268 <bitWidth>1</bitWidth>
31269 </field>
31270 <field>
31271 <name>FB11</name>
31272 <description>Filter bits</description>
31273 <bitOffset>11</bitOffset>
31274 <bitWidth>1</bitWidth>
31275 </field>
31276 <field>
31277 <name>FB12</name>
31278 <description>Filter bits</description>
31279 <bitOffset>12</bitOffset>
31280 <bitWidth>1</bitWidth>
31281 </field>
31282 <field>
31283 <name>FB13</name>
31284 <description>Filter bits</description>
31285 <bitOffset>13</bitOffset>
31286 <bitWidth>1</bitWidth>
31287 </field>
31288 <field>
31289 <name>FB14</name>
31290 <description>Filter bits</description>
31291 <bitOffset>14</bitOffset>
31292 <bitWidth>1</bitWidth>
31293 </field>
31294 <field>
31295 <name>FB15</name>
31296 <description>Filter bits</description>
31297 <bitOffset>15</bitOffset>
31298 <bitWidth>1</bitWidth>
31299 </field>
31300 <field>
31301 <name>FB16</name>
31302 <description>Filter bits</description>
31303 <bitOffset>16</bitOffset>
31304 <bitWidth>1</bitWidth>
31305 </field>
31306 <field>
31307 <name>FB17</name>
31308 <description>Filter bits</description>
31309 <bitOffset>17</bitOffset>
31310 <bitWidth>1</bitWidth>
31311 </field>
31312 <field>
31313 <name>FB18</name>
31314 <description>Filter bits</description>
31315 <bitOffset>18</bitOffset>
31316 <bitWidth>1</bitWidth>
31317 </field>
31318 <field>
31319 <name>FB19</name>
31320 <description>Filter bits</description>
31321 <bitOffset>19</bitOffset>
31322 <bitWidth>1</bitWidth>
31323 </field>
31324 <field>
31325 <name>FB20</name>
31326 <description>Filter bits</description>
31327 <bitOffset>20</bitOffset>
31328 <bitWidth>1</bitWidth>
31329 </field>
31330 <field>
31331 <name>FB21</name>
31332 <description>Filter bits</description>
31333 <bitOffset>21</bitOffset>
31334 <bitWidth>1</bitWidth>
31335 </field>
31336 <field>
31337 <name>FB22</name>
31338 <description>Filter bits</description>
31339 <bitOffset>22</bitOffset>
31340 <bitWidth>1</bitWidth>
31341 </field>
31342 <field>
31343 <name>FB23</name>
31344 <description>Filter bits</description>
31345 <bitOffset>23</bitOffset>
31346 <bitWidth>1</bitWidth>
31347 </field>
31348 <field>
31349 <name>FB24</name>
31350 <description>Filter bits</description>
31351 <bitOffset>24</bitOffset>
31352 <bitWidth>1</bitWidth>
31353 </field>
31354 <field>
31355 <name>FB25</name>
31356 <description>Filter bits</description>
31357 <bitOffset>25</bitOffset>
31358 <bitWidth>1</bitWidth>
31359 </field>
31360 <field>
31361 <name>FB26</name>
31362 <description>Filter bits</description>
31363 <bitOffset>26</bitOffset>
31364 <bitWidth>1</bitWidth>
31365 </field>
31366 <field>
31367 <name>FB27</name>
31368 <description>Filter bits</description>
31369 <bitOffset>27</bitOffset>
31370 <bitWidth>1</bitWidth>
31371 </field>
31372 <field>
31373 <name>FB28</name>
31374 <description>Filter bits</description>
31375 <bitOffset>28</bitOffset>
31376 <bitWidth>1</bitWidth>
31377 </field>
31378 <field>
31379 <name>FB29</name>
31380 <description>Filter bits</description>
31381 <bitOffset>29</bitOffset>
31382 <bitWidth>1</bitWidth>
31383 </field>
31384 <field>
31385 <name>FB30</name>
31386 <description>Filter bits</description>
31387 <bitOffset>30</bitOffset>
31388 <bitWidth>1</bitWidth>
31389 </field>
31390 <field>
31391 <name>FB31</name>
31392 <description>Filter bits</description>
31393 <bitOffset>31</bitOffset>
31394 <bitWidth>1</bitWidth>
31395 </field>
31396 </fields>
31397 </register>
31398 <register>
31399 <name>F7R1</name>
31400 <displayName>F7R1</displayName>
31401 <description>Filter bank 7 register 1</description>
31402 <addressOffset>0x278</addressOffset>
31403 <size>0x20</size>
31404 <access>read-write</access>
31405 <resetValue>0x00000000</resetValue>
31406 <fields>
31407 <field>
31408 <name>FB0</name>
31409 <description>Filter bits</description>
31410 <bitOffset>0</bitOffset>
31411 <bitWidth>1</bitWidth>
31412 </field>
31413 <field>
31414 <name>FB1</name>
31415 <description>Filter bits</description>
31416 <bitOffset>1</bitOffset>
31417 <bitWidth>1</bitWidth>
31418 </field>
31419 <field>
31420 <name>FB2</name>
31421 <description>Filter bits</description>
31422 <bitOffset>2</bitOffset>
31423 <bitWidth>1</bitWidth>
31424 </field>
31425 <field>
31426 <name>FB3</name>
31427 <description>Filter bits</description>
31428 <bitOffset>3</bitOffset>
31429 <bitWidth>1</bitWidth>
31430 </field>
31431 <field>
31432 <name>FB4</name>
31433 <description>Filter bits</description>
31434 <bitOffset>4</bitOffset>
31435 <bitWidth>1</bitWidth>
31436 </field>
31437 <field>
31438 <name>FB5</name>
31439 <description>Filter bits</description>
31440 <bitOffset>5</bitOffset>
31441 <bitWidth>1</bitWidth>
31442 </field>
31443 <field>
31444 <name>FB6</name>
31445 <description>Filter bits</description>
31446 <bitOffset>6</bitOffset>
31447 <bitWidth>1</bitWidth>
31448 </field>
31449 <field>
31450 <name>FB7</name>
31451 <description>Filter bits</description>
31452 <bitOffset>7</bitOffset>
31453 <bitWidth>1</bitWidth>
31454 </field>
31455 <field>
31456 <name>FB8</name>
31457 <description>Filter bits</description>
31458 <bitOffset>8</bitOffset>
31459 <bitWidth>1</bitWidth>
31460 </field>
31461 <field>
31462 <name>FB9</name>
31463 <description>Filter bits</description>
31464 <bitOffset>9</bitOffset>
31465 <bitWidth>1</bitWidth>
31466 </field>
31467 <field>
31468 <name>FB10</name>
31469 <description>Filter bits</description>
31470 <bitOffset>10</bitOffset>
31471 <bitWidth>1</bitWidth>
31472 </field>
31473 <field>
31474 <name>FB11</name>
31475 <description>Filter bits</description>
31476 <bitOffset>11</bitOffset>
31477 <bitWidth>1</bitWidth>
31478 </field>
31479 <field>
31480 <name>FB12</name>
31481 <description>Filter bits</description>
31482 <bitOffset>12</bitOffset>
31483 <bitWidth>1</bitWidth>
31484 </field>
31485 <field>
31486 <name>FB13</name>
31487 <description>Filter bits</description>
31488 <bitOffset>13</bitOffset>
31489 <bitWidth>1</bitWidth>
31490 </field>
31491 <field>
31492 <name>FB14</name>
31493 <description>Filter bits</description>
31494 <bitOffset>14</bitOffset>
31495 <bitWidth>1</bitWidth>
31496 </field>
31497 <field>
31498 <name>FB15</name>
31499 <description>Filter bits</description>
31500 <bitOffset>15</bitOffset>
31501 <bitWidth>1</bitWidth>
31502 </field>
31503 <field>
31504 <name>FB16</name>
31505 <description>Filter bits</description>
31506 <bitOffset>16</bitOffset>
31507 <bitWidth>1</bitWidth>
31508 </field>
31509 <field>
31510 <name>FB17</name>
31511 <description>Filter bits</description>
31512 <bitOffset>17</bitOffset>
31513 <bitWidth>1</bitWidth>
31514 </field>
31515 <field>
31516 <name>FB18</name>
31517 <description>Filter bits</description>
31518 <bitOffset>18</bitOffset>
31519 <bitWidth>1</bitWidth>
31520 </field>
31521 <field>
31522 <name>FB19</name>
31523 <description>Filter bits</description>
31524 <bitOffset>19</bitOffset>
31525 <bitWidth>1</bitWidth>
31526 </field>
31527 <field>
31528 <name>FB20</name>
31529 <description>Filter bits</description>
31530 <bitOffset>20</bitOffset>
31531 <bitWidth>1</bitWidth>
31532 </field>
31533 <field>
31534 <name>FB21</name>
31535 <description>Filter bits</description>
31536 <bitOffset>21</bitOffset>
31537 <bitWidth>1</bitWidth>
31538 </field>
31539 <field>
31540 <name>FB22</name>
31541 <description>Filter bits</description>
31542 <bitOffset>22</bitOffset>
31543 <bitWidth>1</bitWidth>
31544 </field>
31545 <field>
31546 <name>FB23</name>
31547 <description>Filter bits</description>
31548 <bitOffset>23</bitOffset>
31549 <bitWidth>1</bitWidth>
31550 </field>
31551 <field>
31552 <name>FB24</name>
31553 <description>Filter bits</description>
31554 <bitOffset>24</bitOffset>
31555 <bitWidth>1</bitWidth>
31556 </field>
31557 <field>
31558 <name>FB25</name>
31559 <description>Filter bits</description>
31560 <bitOffset>25</bitOffset>
31561 <bitWidth>1</bitWidth>
31562 </field>
31563 <field>
31564 <name>FB26</name>
31565 <description>Filter bits</description>
31566 <bitOffset>26</bitOffset>
31567 <bitWidth>1</bitWidth>
31568 </field>
31569 <field>
31570 <name>FB27</name>
31571 <description>Filter bits</description>
31572 <bitOffset>27</bitOffset>
31573 <bitWidth>1</bitWidth>
31574 </field>
31575 <field>
31576 <name>FB28</name>
31577 <description>Filter bits</description>
31578 <bitOffset>28</bitOffset>
31579 <bitWidth>1</bitWidth>
31580 </field>
31581 <field>
31582 <name>FB29</name>
31583 <description>Filter bits</description>
31584 <bitOffset>29</bitOffset>
31585 <bitWidth>1</bitWidth>
31586 </field>
31587 <field>
31588 <name>FB30</name>
31589 <description>Filter bits</description>
31590 <bitOffset>30</bitOffset>
31591 <bitWidth>1</bitWidth>
31592 </field>
31593 <field>
31594 <name>FB31</name>
31595 <description>Filter bits</description>
31596 <bitOffset>31</bitOffset>
31597 <bitWidth>1</bitWidth>
31598 </field>
31599 </fields>
31600 </register>
31601 <register>
31602 <name>F7R2</name>
31603 <displayName>F7R2</displayName>
31604 <description>Filter bank 7 register 2</description>
31605 <addressOffset>0x27C</addressOffset>
31606 <size>0x20</size>
31607 <access>read-write</access>
31608 <resetValue>0x00000000</resetValue>
31609 <fields>
31610 <field>
31611 <name>FB0</name>
31612 <description>Filter bits</description>
31613 <bitOffset>0</bitOffset>
31614 <bitWidth>1</bitWidth>
31615 </field>
31616 <field>
31617 <name>FB1</name>
31618 <description>Filter bits</description>
31619 <bitOffset>1</bitOffset>
31620 <bitWidth>1</bitWidth>
31621 </field>
31622 <field>
31623 <name>FB2</name>
31624 <description>Filter bits</description>
31625 <bitOffset>2</bitOffset>
31626 <bitWidth>1</bitWidth>
31627 </field>
31628 <field>
31629 <name>FB3</name>
31630 <description>Filter bits</description>
31631 <bitOffset>3</bitOffset>
31632 <bitWidth>1</bitWidth>
31633 </field>
31634 <field>
31635 <name>FB4</name>
31636 <description>Filter bits</description>
31637 <bitOffset>4</bitOffset>
31638 <bitWidth>1</bitWidth>
31639 </field>
31640 <field>
31641 <name>FB5</name>
31642 <description>Filter bits</description>
31643 <bitOffset>5</bitOffset>
31644 <bitWidth>1</bitWidth>
31645 </field>
31646 <field>
31647 <name>FB6</name>
31648 <description>Filter bits</description>
31649 <bitOffset>6</bitOffset>
31650 <bitWidth>1</bitWidth>
31651 </field>
31652 <field>
31653 <name>FB7</name>
31654 <description>Filter bits</description>
31655 <bitOffset>7</bitOffset>
31656 <bitWidth>1</bitWidth>
31657 </field>
31658 <field>
31659 <name>FB8</name>
31660 <description>Filter bits</description>
31661 <bitOffset>8</bitOffset>
31662 <bitWidth>1</bitWidth>
31663 </field>
31664 <field>
31665 <name>FB9</name>
31666 <description>Filter bits</description>
31667 <bitOffset>9</bitOffset>
31668 <bitWidth>1</bitWidth>
31669 </field>
31670 <field>
31671 <name>FB10</name>
31672 <description>Filter bits</description>
31673 <bitOffset>10</bitOffset>
31674 <bitWidth>1</bitWidth>
31675 </field>
31676 <field>
31677 <name>FB11</name>
31678 <description>Filter bits</description>
31679 <bitOffset>11</bitOffset>
31680 <bitWidth>1</bitWidth>
31681 </field>
31682 <field>
31683 <name>FB12</name>
31684 <description>Filter bits</description>
31685 <bitOffset>12</bitOffset>
31686 <bitWidth>1</bitWidth>
31687 </field>
31688 <field>
31689 <name>FB13</name>
31690 <description>Filter bits</description>
31691 <bitOffset>13</bitOffset>
31692 <bitWidth>1</bitWidth>
31693 </field>
31694 <field>
31695 <name>FB14</name>
31696 <description>Filter bits</description>
31697 <bitOffset>14</bitOffset>
31698 <bitWidth>1</bitWidth>
31699 </field>
31700 <field>
31701 <name>FB15</name>
31702 <description>Filter bits</description>
31703 <bitOffset>15</bitOffset>
31704 <bitWidth>1</bitWidth>
31705 </field>
31706 <field>
31707 <name>FB16</name>
31708 <description>Filter bits</description>
31709 <bitOffset>16</bitOffset>
31710 <bitWidth>1</bitWidth>
31711 </field>
31712 <field>
31713 <name>FB17</name>
31714 <description>Filter bits</description>
31715 <bitOffset>17</bitOffset>
31716 <bitWidth>1</bitWidth>
31717 </field>
31718 <field>
31719 <name>FB18</name>
31720 <description>Filter bits</description>
31721 <bitOffset>18</bitOffset>
31722 <bitWidth>1</bitWidth>
31723 </field>
31724 <field>
31725 <name>FB19</name>
31726 <description>Filter bits</description>
31727 <bitOffset>19</bitOffset>
31728 <bitWidth>1</bitWidth>
31729 </field>
31730 <field>
31731 <name>FB20</name>
31732 <description>Filter bits</description>
31733 <bitOffset>20</bitOffset>
31734 <bitWidth>1</bitWidth>
31735 </field>
31736 <field>
31737 <name>FB21</name>
31738 <description>Filter bits</description>
31739 <bitOffset>21</bitOffset>
31740 <bitWidth>1</bitWidth>
31741 </field>
31742 <field>
31743 <name>FB22</name>
31744 <description>Filter bits</description>
31745 <bitOffset>22</bitOffset>
31746 <bitWidth>1</bitWidth>
31747 </field>
31748 <field>
31749 <name>FB23</name>
31750 <description>Filter bits</description>
31751 <bitOffset>23</bitOffset>
31752 <bitWidth>1</bitWidth>
31753 </field>
31754 <field>
31755 <name>FB24</name>
31756 <description>Filter bits</description>
31757 <bitOffset>24</bitOffset>
31758 <bitWidth>1</bitWidth>
31759 </field>
31760 <field>
31761 <name>FB25</name>
31762 <description>Filter bits</description>
31763 <bitOffset>25</bitOffset>
31764 <bitWidth>1</bitWidth>
31765 </field>
31766 <field>
31767 <name>FB26</name>
31768 <description>Filter bits</description>
31769 <bitOffset>26</bitOffset>
31770 <bitWidth>1</bitWidth>
31771 </field>
31772 <field>
31773 <name>FB27</name>
31774 <description>Filter bits</description>
31775 <bitOffset>27</bitOffset>
31776 <bitWidth>1</bitWidth>
31777 </field>
31778 <field>
31779 <name>FB28</name>
31780 <description>Filter bits</description>
31781 <bitOffset>28</bitOffset>
31782 <bitWidth>1</bitWidth>
31783 </field>
31784 <field>
31785 <name>FB29</name>
31786 <description>Filter bits</description>
31787 <bitOffset>29</bitOffset>
31788 <bitWidth>1</bitWidth>
31789 </field>
31790 <field>
31791 <name>FB30</name>
31792 <description>Filter bits</description>
31793 <bitOffset>30</bitOffset>
31794 <bitWidth>1</bitWidth>
31795 </field>
31796 <field>
31797 <name>FB31</name>
31798 <description>Filter bits</description>
31799 <bitOffset>31</bitOffset>
31800 <bitWidth>1</bitWidth>
31801 </field>
31802 </fields>
31803 </register>
31804 <register>
31805 <name>F8R1</name>
31806 <displayName>F8R1</displayName>
31807 <description>Filter bank 8 register 1</description>
31808 <addressOffset>0x280</addressOffset>
31809 <size>0x20</size>
31810 <access>read-write</access>
31811 <resetValue>0x00000000</resetValue>
31812 <fields>
31813 <field>
31814 <name>FB0</name>
31815 <description>Filter bits</description>
31816 <bitOffset>0</bitOffset>
31817 <bitWidth>1</bitWidth>
31818 </field>
31819 <field>
31820 <name>FB1</name>
31821 <description>Filter bits</description>
31822 <bitOffset>1</bitOffset>
31823 <bitWidth>1</bitWidth>
31824 </field>
31825 <field>
31826 <name>FB2</name>
31827 <description>Filter bits</description>
31828 <bitOffset>2</bitOffset>
31829 <bitWidth>1</bitWidth>
31830 </field>
31831 <field>
31832 <name>FB3</name>
31833 <description>Filter bits</description>
31834 <bitOffset>3</bitOffset>
31835 <bitWidth>1</bitWidth>
31836 </field>
31837 <field>
31838 <name>FB4</name>
31839 <description>Filter bits</description>
31840 <bitOffset>4</bitOffset>
31841 <bitWidth>1</bitWidth>
31842 </field>
31843 <field>
31844 <name>FB5</name>
31845 <description>Filter bits</description>
31846 <bitOffset>5</bitOffset>
31847 <bitWidth>1</bitWidth>
31848 </field>
31849 <field>
31850 <name>FB6</name>
31851 <description>Filter bits</description>
31852 <bitOffset>6</bitOffset>
31853 <bitWidth>1</bitWidth>
31854 </field>
31855 <field>
31856 <name>FB7</name>
31857 <description>Filter bits</description>
31858 <bitOffset>7</bitOffset>
31859 <bitWidth>1</bitWidth>
31860 </field>
31861 <field>
31862 <name>FB8</name>
31863 <description>Filter bits</description>
31864 <bitOffset>8</bitOffset>
31865 <bitWidth>1</bitWidth>
31866 </field>
31867 <field>
31868 <name>FB9</name>
31869 <description>Filter bits</description>
31870 <bitOffset>9</bitOffset>
31871 <bitWidth>1</bitWidth>
31872 </field>
31873 <field>
31874 <name>FB10</name>
31875 <description>Filter bits</description>
31876 <bitOffset>10</bitOffset>
31877 <bitWidth>1</bitWidth>
31878 </field>
31879 <field>
31880 <name>FB11</name>
31881 <description>Filter bits</description>
31882 <bitOffset>11</bitOffset>
31883 <bitWidth>1</bitWidth>
31884 </field>
31885 <field>
31886 <name>FB12</name>
31887 <description>Filter bits</description>
31888 <bitOffset>12</bitOffset>
31889 <bitWidth>1</bitWidth>
31890 </field>
31891 <field>
31892 <name>FB13</name>
31893 <description>Filter bits</description>
31894 <bitOffset>13</bitOffset>
31895 <bitWidth>1</bitWidth>
31896 </field>
31897 <field>
31898 <name>FB14</name>
31899 <description>Filter bits</description>
31900 <bitOffset>14</bitOffset>
31901 <bitWidth>1</bitWidth>
31902 </field>
31903 <field>
31904 <name>FB15</name>
31905 <description>Filter bits</description>
31906 <bitOffset>15</bitOffset>
31907 <bitWidth>1</bitWidth>
31908 </field>
31909 <field>
31910 <name>FB16</name>
31911 <description>Filter bits</description>
31912 <bitOffset>16</bitOffset>
31913 <bitWidth>1</bitWidth>
31914 </field>
31915 <field>
31916 <name>FB17</name>
31917 <description>Filter bits</description>
31918 <bitOffset>17</bitOffset>
31919 <bitWidth>1</bitWidth>
31920 </field>
31921 <field>
31922 <name>FB18</name>
31923 <description>Filter bits</description>
31924 <bitOffset>18</bitOffset>
31925 <bitWidth>1</bitWidth>
31926 </field>
31927 <field>
31928 <name>FB19</name>
31929 <description>Filter bits</description>
31930 <bitOffset>19</bitOffset>
31931 <bitWidth>1</bitWidth>
31932 </field>
31933 <field>
31934 <name>FB20</name>
31935 <description>Filter bits</description>
31936 <bitOffset>20</bitOffset>
31937 <bitWidth>1</bitWidth>
31938 </field>
31939 <field>
31940 <name>FB21</name>
31941 <description>Filter bits</description>
31942 <bitOffset>21</bitOffset>
31943 <bitWidth>1</bitWidth>
31944 </field>
31945 <field>
31946 <name>FB22</name>
31947 <description>Filter bits</description>
31948 <bitOffset>22</bitOffset>
31949 <bitWidth>1</bitWidth>
31950 </field>
31951 <field>
31952 <name>FB23</name>
31953 <description>Filter bits</description>
31954 <bitOffset>23</bitOffset>
31955 <bitWidth>1</bitWidth>
31956 </field>
31957 <field>
31958 <name>FB24</name>
31959 <description>Filter bits</description>
31960 <bitOffset>24</bitOffset>
31961 <bitWidth>1</bitWidth>
31962 </field>
31963 <field>
31964 <name>FB25</name>
31965 <description>Filter bits</description>
31966 <bitOffset>25</bitOffset>
31967 <bitWidth>1</bitWidth>
31968 </field>
31969 <field>
31970 <name>FB26</name>
31971 <description>Filter bits</description>
31972 <bitOffset>26</bitOffset>
31973 <bitWidth>1</bitWidth>
31974 </field>
31975 <field>
31976 <name>FB27</name>
31977 <description>Filter bits</description>
31978 <bitOffset>27</bitOffset>
31979 <bitWidth>1</bitWidth>
31980 </field>
31981 <field>
31982 <name>FB28</name>
31983 <description>Filter bits</description>
31984 <bitOffset>28</bitOffset>
31985 <bitWidth>1</bitWidth>
31986 </field>
31987 <field>
31988 <name>FB29</name>
31989 <description>Filter bits</description>
31990 <bitOffset>29</bitOffset>
31991 <bitWidth>1</bitWidth>
31992 </field>
31993 <field>
31994 <name>FB30</name>
31995 <description>Filter bits</description>
31996 <bitOffset>30</bitOffset>
31997 <bitWidth>1</bitWidth>
31998 </field>
31999 <field>
32000 <name>FB31</name>
32001 <description>Filter bits</description>
32002 <bitOffset>31</bitOffset>
32003 <bitWidth>1</bitWidth>
32004 </field>
32005 </fields>
32006 </register>
32007 <register>
32008 <name>F8R2</name>
32009 <displayName>F8R2</displayName>
32010 <description>Filter bank 8 register 2</description>
32011 <addressOffset>0x284</addressOffset>
32012 <size>0x20</size>
32013 <access>read-write</access>
32014 <resetValue>0x00000000</resetValue>
32015 <fields>
32016 <field>
32017 <name>FB0</name>
32018 <description>Filter bits</description>
32019 <bitOffset>0</bitOffset>
32020 <bitWidth>1</bitWidth>
32021 </field>
32022 <field>
32023 <name>FB1</name>
32024 <description>Filter bits</description>
32025 <bitOffset>1</bitOffset>
32026 <bitWidth>1</bitWidth>
32027 </field>
32028 <field>
32029 <name>FB2</name>
32030 <description>Filter bits</description>
32031 <bitOffset>2</bitOffset>
32032 <bitWidth>1</bitWidth>
32033 </field>
32034 <field>
32035 <name>FB3</name>
32036 <description>Filter bits</description>
32037 <bitOffset>3</bitOffset>
32038 <bitWidth>1</bitWidth>
32039 </field>
32040 <field>
32041 <name>FB4</name>
32042 <description>Filter bits</description>
32043 <bitOffset>4</bitOffset>
32044 <bitWidth>1</bitWidth>
32045 </field>
32046 <field>
32047 <name>FB5</name>
32048 <description>Filter bits</description>
32049 <bitOffset>5</bitOffset>
32050 <bitWidth>1</bitWidth>
32051 </field>
32052 <field>
32053 <name>FB6</name>
32054 <description>Filter bits</description>
32055 <bitOffset>6</bitOffset>
32056 <bitWidth>1</bitWidth>
32057 </field>
32058 <field>
32059 <name>FB7</name>
32060 <description>Filter bits</description>
32061 <bitOffset>7</bitOffset>
32062 <bitWidth>1</bitWidth>
32063 </field>
32064 <field>
32065 <name>FB8</name>
32066 <description>Filter bits</description>
32067 <bitOffset>8</bitOffset>
32068 <bitWidth>1</bitWidth>
32069 </field>
32070 <field>
32071 <name>FB9</name>
32072 <description>Filter bits</description>
32073 <bitOffset>9</bitOffset>
32074 <bitWidth>1</bitWidth>
32075 </field>
32076 <field>
32077 <name>FB10</name>
32078 <description>Filter bits</description>
32079 <bitOffset>10</bitOffset>
32080 <bitWidth>1</bitWidth>
32081 </field>
32082 <field>
32083 <name>FB11</name>
32084 <description>Filter bits</description>
32085 <bitOffset>11</bitOffset>
32086 <bitWidth>1</bitWidth>
32087 </field>
32088 <field>
32089 <name>FB12</name>
32090 <description>Filter bits</description>
32091 <bitOffset>12</bitOffset>
32092 <bitWidth>1</bitWidth>
32093 </field>
32094 <field>
32095 <name>FB13</name>
32096 <description>Filter bits</description>
32097 <bitOffset>13</bitOffset>
32098 <bitWidth>1</bitWidth>
32099 </field>
32100 <field>
32101 <name>FB14</name>
32102 <description>Filter bits</description>
32103 <bitOffset>14</bitOffset>
32104 <bitWidth>1</bitWidth>
32105 </field>
32106 <field>
32107 <name>FB15</name>
32108 <description>Filter bits</description>
32109 <bitOffset>15</bitOffset>
32110 <bitWidth>1</bitWidth>
32111 </field>
32112 <field>
32113 <name>FB16</name>
32114 <description>Filter bits</description>
32115 <bitOffset>16</bitOffset>
32116 <bitWidth>1</bitWidth>
32117 </field>
32118 <field>
32119 <name>FB17</name>
32120 <description>Filter bits</description>
32121 <bitOffset>17</bitOffset>
32122 <bitWidth>1</bitWidth>
32123 </field>
32124 <field>
32125 <name>FB18</name>
32126 <description>Filter bits</description>
32127 <bitOffset>18</bitOffset>
32128 <bitWidth>1</bitWidth>
32129 </field>
32130 <field>
32131 <name>FB19</name>
32132 <description>Filter bits</description>
32133 <bitOffset>19</bitOffset>
32134 <bitWidth>1</bitWidth>
32135 </field>
32136 <field>
32137 <name>FB20</name>
32138 <description>Filter bits</description>
32139 <bitOffset>20</bitOffset>
32140 <bitWidth>1</bitWidth>
32141 </field>
32142 <field>
32143 <name>FB21</name>
32144 <description>Filter bits</description>
32145 <bitOffset>21</bitOffset>
32146 <bitWidth>1</bitWidth>
32147 </field>
32148 <field>
32149 <name>FB22</name>
32150 <description>Filter bits</description>
32151 <bitOffset>22</bitOffset>
32152 <bitWidth>1</bitWidth>
32153 </field>
32154 <field>
32155 <name>FB23</name>
32156 <description>Filter bits</description>
32157 <bitOffset>23</bitOffset>
32158 <bitWidth>1</bitWidth>
32159 </field>
32160 <field>
32161 <name>FB24</name>
32162 <description>Filter bits</description>
32163 <bitOffset>24</bitOffset>
32164 <bitWidth>1</bitWidth>
32165 </field>
32166 <field>
32167 <name>FB25</name>
32168 <description>Filter bits</description>
32169 <bitOffset>25</bitOffset>
32170 <bitWidth>1</bitWidth>
32171 </field>
32172 <field>
32173 <name>FB26</name>
32174 <description>Filter bits</description>
32175 <bitOffset>26</bitOffset>
32176 <bitWidth>1</bitWidth>
32177 </field>
32178 <field>
32179 <name>FB27</name>
32180 <description>Filter bits</description>
32181 <bitOffset>27</bitOffset>
32182 <bitWidth>1</bitWidth>
32183 </field>
32184 <field>
32185 <name>FB28</name>
32186 <description>Filter bits</description>
32187 <bitOffset>28</bitOffset>
32188 <bitWidth>1</bitWidth>
32189 </field>
32190 <field>
32191 <name>FB29</name>
32192 <description>Filter bits</description>
32193 <bitOffset>29</bitOffset>
32194 <bitWidth>1</bitWidth>
32195 </field>
32196 <field>
32197 <name>FB30</name>
32198 <description>Filter bits</description>
32199 <bitOffset>30</bitOffset>
32200 <bitWidth>1</bitWidth>
32201 </field>
32202 <field>
32203 <name>FB31</name>
32204 <description>Filter bits</description>
32205 <bitOffset>31</bitOffset>
32206 <bitWidth>1</bitWidth>
32207 </field>
32208 </fields>
32209 </register>
32210 <register>
32211 <name>F9R1</name>
32212 <displayName>F9R1</displayName>
32213 <description>Filter bank 9 register 1</description>
32214 <addressOffset>0x288</addressOffset>
32215 <size>0x20</size>
32216 <access>read-write</access>
32217 <resetValue>0x00000000</resetValue>
32218 <fields>
32219 <field>
32220 <name>FB0</name>
32221 <description>Filter bits</description>
32222 <bitOffset>0</bitOffset>
32223 <bitWidth>1</bitWidth>
32224 </field>
32225 <field>
32226 <name>FB1</name>
32227 <description>Filter bits</description>
32228 <bitOffset>1</bitOffset>
32229 <bitWidth>1</bitWidth>
32230 </field>
32231 <field>
32232 <name>FB2</name>
32233 <description>Filter bits</description>
32234 <bitOffset>2</bitOffset>
32235 <bitWidth>1</bitWidth>
32236 </field>
32237 <field>
32238 <name>FB3</name>
32239 <description>Filter bits</description>
32240 <bitOffset>3</bitOffset>
32241 <bitWidth>1</bitWidth>
32242 </field>
32243 <field>
32244 <name>FB4</name>
32245 <description>Filter bits</description>
32246 <bitOffset>4</bitOffset>
32247 <bitWidth>1</bitWidth>
32248 </field>
32249 <field>
32250 <name>FB5</name>
32251 <description>Filter bits</description>
32252 <bitOffset>5</bitOffset>
32253 <bitWidth>1</bitWidth>
32254 </field>
32255 <field>
32256 <name>FB6</name>
32257 <description>Filter bits</description>
32258 <bitOffset>6</bitOffset>
32259 <bitWidth>1</bitWidth>
32260 </field>
32261 <field>
32262 <name>FB7</name>
32263 <description>Filter bits</description>
32264 <bitOffset>7</bitOffset>
32265 <bitWidth>1</bitWidth>
32266 </field>
32267 <field>
32268 <name>FB8</name>
32269 <description>Filter bits</description>
32270 <bitOffset>8</bitOffset>
32271 <bitWidth>1</bitWidth>
32272 </field>
32273 <field>
32274 <name>FB9</name>
32275 <description>Filter bits</description>
32276 <bitOffset>9</bitOffset>
32277 <bitWidth>1</bitWidth>
32278 </field>
32279 <field>
32280 <name>FB10</name>
32281 <description>Filter bits</description>
32282 <bitOffset>10</bitOffset>
32283 <bitWidth>1</bitWidth>
32284 </field>
32285 <field>
32286 <name>FB11</name>
32287 <description>Filter bits</description>
32288 <bitOffset>11</bitOffset>
32289 <bitWidth>1</bitWidth>
32290 </field>
32291 <field>
32292 <name>FB12</name>
32293 <description>Filter bits</description>
32294 <bitOffset>12</bitOffset>
32295 <bitWidth>1</bitWidth>
32296 </field>
32297 <field>
32298 <name>FB13</name>
32299 <description>Filter bits</description>
32300 <bitOffset>13</bitOffset>
32301 <bitWidth>1</bitWidth>
32302 </field>
32303 <field>
32304 <name>FB14</name>
32305 <description>Filter bits</description>
32306 <bitOffset>14</bitOffset>
32307 <bitWidth>1</bitWidth>
32308 </field>
32309 <field>
32310 <name>FB15</name>
32311 <description>Filter bits</description>
32312 <bitOffset>15</bitOffset>
32313 <bitWidth>1</bitWidth>
32314 </field>
32315 <field>
32316 <name>FB16</name>
32317 <description>Filter bits</description>
32318 <bitOffset>16</bitOffset>
32319 <bitWidth>1</bitWidth>
32320 </field>
32321 <field>
32322 <name>FB17</name>
32323 <description>Filter bits</description>
32324 <bitOffset>17</bitOffset>
32325 <bitWidth>1</bitWidth>
32326 </field>
32327 <field>
32328 <name>FB18</name>
32329 <description>Filter bits</description>
32330 <bitOffset>18</bitOffset>
32331 <bitWidth>1</bitWidth>
32332 </field>
32333 <field>
32334 <name>FB19</name>
32335 <description>Filter bits</description>
32336 <bitOffset>19</bitOffset>
32337 <bitWidth>1</bitWidth>
32338 </field>
32339 <field>
32340 <name>FB20</name>
32341 <description>Filter bits</description>
32342 <bitOffset>20</bitOffset>
32343 <bitWidth>1</bitWidth>
32344 </field>
32345 <field>
32346 <name>FB21</name>
32347 <description>Filter bits</description>
32348 <bitOffset>21</bitOffset>
32349 <bitWidth>1</bitWidth>
32350 </field>
32351 <field>
32352 <name>FB22</name>
32353 <description>Filter bits</description>
32354 <bitOffset>22</bitOffset>
32355 <bitWidth>1</bitWidth>
32356 </field>
32357 <field>
32358 <name>FB23</name>
32359 <description>Filter bits</description>
32360 <bitOffset>23</bitOffset>
32361 <bitWidth>1</bitWidth>
32362 </field>
32363 <field>
32364 <name>FB24</name>
32365 <description>Filter bits</description>
32366 <bitOffset>24</bitOffset>
32367 <bitWidth>1</bitWidth>
32368 </field>
32369 <field>
32370 <name>FB25</name>
32371 <description>Filter bits</description>
32372 <bitOffset>25</bitOffset>
32373 <bitWidth>1</bitWidth>
32374 </field>
32375 <field>
32376 <name>FB26</name>
32377 <description>Filter bits</description>
32378 <bitOffset>26</bitOffset>
32379 <bitWidth>1</bitWidth>
32380 </field>
32381 <field>
32382 <name>FB27</name>
32383 <description>Filter bits</description>
32384 <bitOffset>27</bitOffset>
32385 <bitWidth>1</bitWidth>
32386 </field>
32387 <field>
32388 <name>FB28</name>
32389 <description>Filter bits</description>
32390 <bitOffset>28</bitOffset>
32391 <bitWidth>1</bitWidth>
32392 </field>
32393 <field>
32394 <name>FB29</name>
32395 <description>Filter bits</description>
32396 <bitOffset>29</bitOffset>
32397 <bitWidth>1</bitWidth>
32398 </field>
32399 <field>
32400 <name>FB30</name>
32401 <description>Filter bits</description>
32402 <bitOffset>30</bitOffset>
32403 <bitWidth>1</bitWidth>
32404 </field>
32405 <field>
32406 <name>FB31</name>
32407 <description>Filter bits</description>
32408 <bitOffset>31</bitOffset>
32409 <bitWidth>1</bitWidth>
32410 </field>
32411 </fields>
32412 </register>
32413 <register>
32414 <name>F9R2</name>
32415 <displayName>F9R2</displayName>
32416 <description>Filter bank 9 register 2</description>
32417 <addressOffset>0x28C</addressOffset>
32418 <size>0x20</size>
32419 <access>read-write</access>
32420 <resetValue>0x00000000</resetValue>
32421 <fields>
32422 <field>
32423 <name>FB0</name>
32424 <description>Filter bits</description>
32425 <bitOffset>0</bitOffset>
32426 <bitWidth>1</bitWidth>
32427 </field>
32428 <field>
32429 <name>FB1</name>
32430 <description>Filter bits</description>
32431 <bitOffset>1</bitOffset>
32432 <bitWidth>1</bitWidth>
32433 </field>
32434 <field>
32435 <name>FB2</name>
32436 <description>Filter bits</description>
32437 <bitOffset>2</bitOffset>
32438 <bitWidth>1</bitWidth>
32439 </field>
32440 <field>
32441 <name>FB3</name>
32442 <description>Filter bits</description>
32443 <bitOffset>3</bitOffset>
32444 <bitWidth>1</bitWidth>
32445 </field>
32446 <field>
32447 <name>FB4</name>
32448 <description>Filter bits</description>
32449 <bitOffset>4</bitOffset>
32450 <bitWidth>1</bitWidth>
32451 </field>
32452 <field>
32453 <name>FB5</name>
32454 <description>Filter bits</description>
32455 <bitOffset>5</bitOffset>
32456 <bitWidth>1</bitWidth>
32457 </field>
32458 <field>
32459 <name>FB6</name>
32460 <description>Filter bits</description>
32461 <bitOffset>6</bitOffset>
32462 <bitWidth>1</bitWidth>
32463 </field>
32464 <field>
32465 <name>FB7</name>
32466 <description>Filter bits</description>
32467 <bitOffset>7</bitOffset>
32468 <bitWidth>1</bitWidth>
32469 </field>
32470 <field>
32471 <name>FB8</name>
32472 <description>Filter bits</description>
32473 <bitOffset>8</bitOffset>
32474 <bitWidth>1</bitWidth>
32475 </field>
32476 <field>
32477 <name>FB9</name>
32478 <description>Filter bits</description>
32479 <bitOffset>9</bitOffset>
32480 <bitWidth>1</bitWidth>
32481 </field>
32482 <field>
32483 <name>FB10</name>
32484 <description>Filter bits</description>
32485 <bitOffset>10</bitOffset>
32486 <bitWidth>1</bitWidth>
32487 </field>
32488 <field>
32489 <name>FB11</name>
32490 <description>Filter bits</description>
32491 <bitOffset>11</bitOffset>
32492 <bitWidth>1</bitWidth>
32493 </field>
32494 <field>
32495 <name>FB12</name>
32496 <description>Filter bits</description>
32497 <bitOffset>12</bitOffset>
32498 <bitWidth>1</bitWidth>
32499 </field>
32500 <field>
32501 <name>FB13</name>
32502 <description>Filter bits</description>
32503 <bitOffset>13</bitOffset>
32504 <bitWidth>1</bitWidth>
32505 </field>
32506 <field>
32507 <name>FB14</name>
32508 <description>Filter bits</description>
32509 <bitOffset>14</bitOffset>
32510 <bitWidth>1</bitWidth>
32511 </field>
32512 <field>
32513 <name>FB15</name>
32514 <description>Filter bits</description>
32515 <bitOffset>15</bitOffset>
32516 <bitWidth>1</bitWidth>
32517 </field>
32518 <field>
32519 <name>FB16</name>
32520 <description>Filter bits</description>
32521 <bitOffset>16</bitOffset>
32522 <bitWidth>1</bitWidth>
32523 </field>
32524 <field>
32525 <name>FB17</name>
32526 <description>Filter bits</description>
32527 <bitOffset>17</bitOffset>
32528 <bitWidth>1</bitWidth>
32529 </field>
32530 <field>
32531 <name>FB18</name>
32532 <description>Filter bits</description>
32533 <bitOffset>18</bitOffset>
32534 <bitWidth>1</bitWidth>
32535 </field>
32536 <field>
32537 <name>FB19</name>
32538 <description>Filter bits</description>
32539 <bitOffset>19</bitOffset>
32540 <bitWidth>1</bitWidth>
32541 </field>
32542 <field>
32543 <name>FB20</name>
32544 <description>Filter bits</description>
32545 <bitOffset>20</bitOffset>
32546 <bitWidth>1</bitWidth>
32547 </field>
32548 <field>
32549 <name>FB21</name>
32550 <description>Filter bits</description>
32551 <bitOffset>21</bitOffset>
32552 <bitWidth>1</bitWidth>
32553 </field>
32554 <field>
32555 <name>FB22</name>
32556 <description>Filter bits</description>
32557 <bitOffset>22</bitOffset>
32558 <bitWidth>1</bitWidth>
32559 </field>
32560 <field>
32561 <name>FB23</name>
32562 <description>Filter bits</description>
32563 <bitOffset>23</bitOffset>
32564 <bitWidth>1</bitWidth>
32565 </field>
32566 <field>
32567 <name>FB24</name>
32568 <description>Filter bits</description>
32569 <bitOffset>24</bitOffset>
32570 <bitWidth>1</bitWidth>
32571 </field>
32572 <field>
32573 <name>FB25</name>
32574 <description>Filter bits</description>
32575 <bitOffset>25</bitOffset>
32576 <bitWidth>1</bitWidth>
32577 </field>
32578 <field>
32579 <name>FB26</name>
32580 <description>Filter bits</description>
32581 <bitOffset>26</bitOffset>
32582 <bitWidth>1</bitWidth>
32583 </field>
32584 <field>
32585 <name>FB27</name>
32586 <description>Filter bits</description>
32587 <bitOffset>27</bitOffset>
32588 <bitWidth>1</bitWidth>
32589 </field>
32590 <field>
32591 <name>FB28</name>
32592 <description>Filter bits</description>
32593 <bitOffset>28</bitOffset>
32594 <bitWidth>1</bitWidth>
32595 </field>
32596 <field>
32597 <name>FB29</name>
32598 <description>Filter bits</description>
32599 <bitOffset>29</bitOffset>
32600 <bitWidth>1</bitWidth>
32601 </field>
32602 <field>
32603 <name>FB30</name>
32604 <description>Filter bits</description>
32605 <bitOffset>30</bitOffset>
32606 <bitWidth>1</bitWidth>
32607 </field>
32608 <field>
32609 <name>FB31</name>
32610 <description>Filter bits</description>
32611 <bitOffset>31</bitOffset>
32612 <bitWidth>1</bitWidth>
32613 </field>
32614 </fields>
32615 </register>
32616 <register>
32617 <name>F10R1</name>
32618 <displayName>F10R1</displayName>
32619 <description>Filter bank 10 register 1</description>
32620 <addressOffset>0x290</addressOffset>
32621 <size>0x20</size>
32622 <access>read-write</access>
32623 <resetValue>0x00000000</resetValue>
32624 <fields>
32625 <field>
32626 <name>FB0</name>
32627 <description>Filter bits</description>
32628 <bitOffset>0</bitOffset>
32629 <bitWidth>1</bitWidth>
32630 </field>
32631 <field>
32632 <name>FB1</name>
32633 <description>Filter bits</description>
32634 <bitOffset>1</bitOffset>
32635 <bitWidth>1</bitWidth>
32636 </field>
32637 <field>
32638 <name>FB2</name>
32639 <description>Filter bits</description>
32640 <bitOffset>2</bitOffset>
32641 <bitWidth>1</bitWidth>
32642 </field>
32643 <field>
32644 <name>FB3</name>
32645 <description>Filter bits</description>
32646 <bitOffset>3</bitOffset>
32647 <bitWidth>1</bitWidth>
32648 </field>
32649 <field>
32650 <name>FB4</name>
32651 <description>Filter bits</description>
32652 <bitOffset>4</bitOffset>
32653 <bitWidth>1</bitWidth>
32654 </field>
32655 <field>
32656 <name>FB5</name>
32657 <description>Filter bits</description>
32658 <bitOffset>5</bitOffset>
32659 <bitWidth>1</bitWidth>
32660 </field>
32661 <field>
32662 <name>FB6</name>
32663 <description>Filter bits</description>
32664 <bitOffset>6</bitOffset>
32665 <bitWidth>1</bitWidth>
32666 </field>
32667 <field>
32668 <name>FB7</name>
32669 <description>Filter bits</description>
32670 <bitOffset>7</bitOffset>
32671 <bitWidth>1</bitWidth>
32672 </field>
32673 <field>
32674 <name>FB8</name>
32675 <description>Filter bits</description>
32676 <bitOffset>8</bitOffset>
32677 <bitWidth>1</bitWidth>
32678 </field>
32679 <field>
32680 <name>FB9</name>
32681 <description>Filter bits</description>
32682 <bitOffset>9</bitOffset>
32683 <bitWidth>1</bitWidth>
32684 </field>
32685 <field>
32686 <name>FB10</name>
32687 <description>Filter bits</description>
32688 <bitOffset>10</bitOffset>
32689 <bitWidth>1</bitWidth>
32690 </field>
32691 <field>
32692 <name>FB11</name>
32693 <description>Filter bits</description>
32694 <bitOffset>11</bitOffset>
32695 <bitWidth>1</bitWidth>
32696 </field>
32697 <field>
32698 <name>FB12</name>
32699 <description>Filter bits</description>
32700 <bitOffset>12</bitOffset>
32701 <bitWidth>1</bitWidth>
32702 </field>
32703 <field>
32704 <name>FB13</name>
32705 <description>Filter bits</description>
32706 <bitOffset>13</bitOffset>
32707 <bitWidth>1</bitWidth>
32708 </field>
32709 <field>
32710 <name>FB14</name>
32711 <description>Filter bits</description>
32712 <bitOffset>14</bitOffset>
32713 <bitWidth>1</bitWidth>
32714 </field>
32715 <field>
32716 <name>FB15</name>
32717 <description>Filter bits</description>
32718 <bitOffset>15</bitOffset>
32719 <bitWidth>1</bitWidth>
32720 </field>
32721 <field>
32722 <name>FB16</name>
32723 <description>Filter bits</description>
32724 <bitOffset>16</bitOffset>
32725 <bitWidth>1</bitWidth>
32726 </field>
32727 <field>
32728 <name>FB17</name>
32729 <description>Filter bits</description>
32730 <bitOffset>17</bitOffset>
32731 <bitWidth>1</bitWidth>
32732 </field>
32733 <field>
32734 <name>FB18</name>
32735 <description>Filter bits</description>
32736 <bitOffset>18</bitOffset>
32737 <bitWidth>1</bitWidth>
32738 </field>
32739 <field>
32740 <name>FB19</name>
32741 <description>Filter bits</description>
32742 <bitOffset>19</bitOffset>
32743 <bitWidth>1</bitWidth>
32744 </field>
32745 <field>
32746 <name>FB20</name>
32747 <description>Filter bits</description>
32748 <bitOffset>20</bitOffset>
32749 <bitWidth>1</bitWidth>
32750 </field>
32751 <field>
32752 <name>FB21</name>
32753 <description>Filter bits</description>
32754 <bitOffset>21</bitOffset>
32755 <bitWidth>1</bitWidth>
32756 </field>
32757 <field>
32758 <name>FB22</name>
32759 <description>Filter bits</description>
32760 <bitOffset>22</bitOffset>
32761 <bitWidth>1</bitWidth>
32762 </field>
32763 <field>
32764 <name>FB23</name>
32765 <description>Filter bits</description>
32766 <bitOffset>23</bitOffset>
32767 <bitWidth>1</bitWidth>
32768 </field>
32769 <field>
32770 <name>FB24</name>
32771 <description>Filter bits</description>
32772 <bitOffset>24</bitOffset>
32773 <bitWidth>1</bitWidth>
32774 </field>
32775 <field>
32776 <name>FB25</name>
32777 <description>Filter bits</description>
32778 <bitOffset>25</bitOffset>
32779 <bitWidth>1</bitWidth>
32780 </field>
32781 <field>
32782 <name>FB26</name>
32783 <description>Filter bits</description>
32784 <bitOffset>26</bitOffset>
32785 <bitWidth>1</bitWidth>
32786 </field>
32787 <field>
32788 <name>FB27</name>
32789 <description>Filter bits</description>
32790 <bitOffset>27</bitOffset>
32791 <bitWidth>1</bitWidth>
32792 </field>
32793 <field>
32794 <name>FB28</name>
32795 <description>Filter bits</description>
32796 <bitOffset>28</bitOffset>
32797 <bitWidth>1</bitWidth>
32798 </field>
32799 <field>
32800 <name>FB29</name>
32801 <description>Filter bits</description>
32802 <bitOffset>29</bitOffset>
32803 <bitWidth>1</bitWidth>
32804 </field>
32805 <field>
32806 <name>FB30</name>
32807 <description>Filter bits</description>
32808 <bitOffset>30</bitOffset>
32809 <bitWidth>1</bitWidth>
32810 </field>
32811 <field>
32812 <name>FB31</name>
32813 <description>Filter bits</description>
32814 <bitOffset>31</bitOffset>
32815 <bitWidth>1</bitWidth>
32816 </field>
32817 </fields>
32818 </register>
32819 <register>
32820 <name>F10R2</name>
32821 <displayName>F10R2</displayName>
32822 <description>Filter bank 10 register 2</description>
32823 <addressOffset>0x294</addressOffset>
32824 <size>0x20</size>
32825 <access>read-write</access>
32826 <resetValue>0x00000000</resetValue>
32827 <fields>
32828 <field>
32829 <name>FB0</name>
32830 <description>Filter bits</description>
32831 <bitOffset>0</bitOffset>
32832 <bitWidth>1</bitWidth>
32833 </field>
32834 <field>
32835 <name>FB1</name>
32836 <description>Filter bits</description>
32837 <bitOffset>1</bitOffset>
32838 <bitWidth>1</bitWidth>
32839 </field>
32840 <field>
32841 <name>FB2</name>
32842 <description>Filter bits</description>
32843 <bitOffset>2</bitOffset>
32844 <bitWidth>1</bitWidth>
32845 </field>
32846 <field>
32847 <name>FB3</name>
32848 <description>Filter bits</description>
32849 <bitOffset>3</bitOffset>
32850 <bitWidth>1</bitWidth>
32851 </field>
32852 <field>
32853 <name>FB4</name>
32854 <description>Filter bits</description>
32855 <bitOffset>4</bitOffset>
32856 <bitWidth>1</bitWidth>
32857 </field>
32858 <field>
32859 <name>FB5</name>
32860 <description>Filter bits</description>
32861 <bitOffset>5</bitOffset>
32862 <bitWidth>1</bitWidth>
32863 </field>
32864 <field>
32865 <name>FB6</name>
32866 <description>Filter bits</description>
32867 <bitOffset>6</bitOffset>
32868 <bitWidth>1</bitWidth>
32869 </field>
32870 <field>
32871 <name>FB7</name>
32872 <description>Filter bits</description>
32873 <bitOffset>7</bitOffset>
32874 <bitWidth>1</bitWidth>
32875 </field>
32876 <field>
32877 <name>FB8</name>
32878 <description>Filter bits</description>
32879 <bitOffset>8</bitOffset>
32880 <bitWidth>1</bitWidth>
32881 </field>
32882 <field>
32883 <name>FB9</name>
32884 <description>Filter bits</description>
32885 <bitOffset>9</bitOffset>
32886 <bitWidth>1</bitWidth>
32887 </field>
32888 <field>
32889 <name>FB10</name>
32890 <description>Filter bits</description>
32891 <bitOffset>10</bitOffset>
32892 <bitWidth>1</bitWidth>
32893 </field>
32894 <field>
32895 <name>FB11</name>
32896 <description>Filter bits</description>
32897 <bitOffset>11</bitOffset>
32898 <bitWidth>1</bitWidth>
32899 </field>
32900 <field>
32901 <name>FB12</name>
32902 <description>Filter bits</description>
32903 <bitOffset>12</bitOffset>
32904 <bitWidth>1</bitWidth>
32905 </field>
32906 <field>
32907 <name>FB13</name>
32908 <description>Filter bits</description>
32909 <bitOffset>13</bitOffset>
32910 <bitWidth>1</bitWidth>
32911 </field>
32912 <field>
32913 <name>FB14</name>
32914 <description>Filter bits</description>
32915 <bitOffset>14</bitOffset>
32916 <bitWidth>1</bitWidth>
32917 </field>
32918 <field>
32919 <name>FB15</name>
32920 <description>Filter bits</description>
32921 <bitOffset>15</bitOffset>
32922 <bitWidth>1</bitWidth>
32923 </field>
32924 <field>
32925 <name>FB16</name>
32926 <description>Filter bits</description>
32927 <bitOffset>16</bitOffset>
32928 <bitWidth>1</bitWidth>
32929 </field>
32930 <field>
32931 <name>FB17</name>
32932 <description>Filter bits</description>
32933 <bitOffset>17</bitOffset>
32934 <bitWidth>1</bitWidth>
32935 </field>
32936 <field>
32937 <name>FB18</name>
32938 <description>Filter bits</description>
32939 <bitOffset>18</bitOffset>
32940 <bitWidth>1</bitWidth>
32941 </field>
32942 <field>
32943 <name>FB19</name>
32944 <description>Filter bits</description>
32945 <bitOffset>19</bitOffset>
32946 <bitWidth>1</bitWidth>
32947 </field>
32948 <field>
32949 <name>FB20</name>
32950 <description>Filter bits</description>
32951 <bitOffset>20</bitOffset>
32952 <bitWidth>1</bitWidth>
32953 </field>
32954 <field>
32955 <name>FB21</name>
32956 <description>Filter bits</description>
32957 <bitOffset>21</bitOffset>
32958 <bitWidth>1</bitWidth>
32959 </field>
32960 <field>
32961 <name>FB22</name>
32962 <description>Filter bits</description>
32963 <bitOffset>22</bitOffset>
32964 <bitWidth>1</bitWidth>
32965 </field>
32966 <field>
32967 <name>FB23</name>
32968 <description>Filter bits</description>
32969 <bitOffset>23</bitOffset>
32970 <bitWidth>1</bitWidth>
32971 </field>
32972 <field>
32973 <name>FB24</name>
32974 <description>Filter bits</description>
32975 <bitOffset>24</bitOffset>
32976 <bitWidth>1</bitWidth>
32977 </field>
32978 <field>
32979 <name>FB25</name>
32980 <description>Filter bits</description>
32981 <bitOffset>25</bitOffset>
32982 <bitWidth>1</bitWidth>
32983 </field>
32984 <field>
32985 <name>FB26</name>
32986 <description>Filter bits</description>
32987 <bitOffset>26</bitOffset>
32988 <bitWidth>1</bitWidth>
32989 </field>
32990 <field>
32991 <name>FB27</name>
32992 <description>Filter bits</description>
32993 <bitOffset>27</bitOffset>
32994 <bitWidth>1</bitWidth>
32995 </field>
32996 <field>
32997 <name>FB28</name>
32998 <description>Filter bits</description>
32999 <bitOffset>28</bitOffset>
33000 <bitWidth>1</bitWidth>
33001 </field>
33002 <field>
33003 <name>FB29</name>
33004 <description>Filter bits</description>
33005 <bitOffset>29</bitOffset>
33006 <bitWidth>1</bitWidth>
33007 </field>
33008 <field>
33009 <name>FB30</name>
33010 <description>Filter bits</description>
33011 <bitOffset>30</bitOffset>
33012 <bitWidth>1</bitWidth>
33013 </field>
33014 <field>
33015 <name>FB31</name>
33016 <description>Filter bits</description>
33017 <bitOffset>31</bitOffset>
33018 <bitWidth>1</bitWidth>
33019 </field>
33020 </fields>
33021 </register>
33022 <register>
33023 <name>F11R1</name>
33024 <displayName>F11R1</displayName>
33025 <description>Filter bank 11 register 1</description>
33026 <addressOffset>0x298</addressOffset>
33027 <size>0x20</size>
33028 <access>read-write</access>
33029 <resetValue>0x00000000</resetValue>
33030 <fields>
33031 <field>
33032 <name>FB0</name>
33033 <description>Filter bits</description>
33034 <bitOffset>0</bitOffset>
33035 <bitWidth>1</bitWidth>
33036 </field>
33037 <field>
33038 <name>FB1</name>
33039 <description>Filter bits</description>
33040 <bitOffset>1</bitOffset>
33041 <bitWidth>1</bitWidth>
33042 </field>
33043 <field>
33044 <name>FB2</name>
33045 <description>Filter bits</description>
33046 <bitOffset>2</bitOffset>
33047 <bitWidth>1</bitWidth>
33048 </field>
33049 <field>
33050 <name>FB3</name>
33051 <description>Filter bits</description>
33052 <bitOffset>3</bitOffset>
33053 <bitWidth>1</bitWidth>
33054 </field>
33055 <field>
33056 <name>FB4</name>
33057 <description>Filter bits</description>
33058 <bitOffset>4</bitOffset>
33059 <bitWidth>1</bitWidth>
33060 </field>
33061 <field>
33062 <name>FB5</name>
33063 <description>Filter bits</description>
33064 <bitOffset>5</bitOffset>
33065 <bitWidth>1</bitWidth>
33066 </field>
33067 <field>
33068 <name>FB6</name>
33069 <description>Filter bits</description>
33070 <bitOffset>6</bitOffset>
33071 <bitWidth>1</bitWidth>
33072 </field>
33073 <field>
33074 <name>FB7</name>
33075 <description>Filter bits</description>
33076 <bitOffset>7</bitOffset>
33077 <bitWidth>1</bitWidth>
33078 </field>
33079 <field>
33080 <name>FB8</name>
33081 <description>Filter bits</description>
33082 <bitOffset>8</bitOffset>
33083 <bitWidth>1</bitWidth>
33084 </field>
33085 <field>
33086 <name>FB9</name>
33087 <description>Filter bits</description>
33088 <bitOffset>9</bitOffset>
33089 <bitWidth>1</bitWidth>
33090 </field>
33091 <field>
33092 <name>FB10</name>
33093 <description>Filter bits</description>
33094 <bitOffset>10</bitOffset>
33095 <bitWidth>1</bitWidth>
33096 </field>
33097 <field>
33098 <name>FB11</name>
33099 <description>Filter bits</description>
33100 <bitOffset>11</bitOffset>
33101 <bitWidth>1</bitWidth>
33102 </field>
33103 <field>
33104 <name>FB12</name>
33105 <description>Filter bits</description>
33106 <bitOffset>12</bitOffset>
33107 <bitWidth>1</bitWidth>
33108 </field>
33109 <field>
33110 <name>FB13</name>
33111 <description>Filter bits</description>
33112 <bitOffset>13</bitOffset>
33113 <bitWidth>1</bitWidth>
33114 </field>
33115 <field>
33116 <name>FB14</name>
33117 <description>Filter bits</description>
33118 <bitOffset>14</bitOffset>
33119 <bitWidth>1</bitWidth>
33120 </field>
33121 <field>
33122 <name>FB15</name>
33123 <description>Filter bits</description>
33124 <bitOffset>15</bitOffset>
33125 <bitWidth>1</bitWidth>
33126 </field>
33127 <field>
33128 <name>FB16</name>
33129 <description>Filter bits</description>
33130 <bitOffset>16</bitOffset>
33131 <bitWidth>1</bitWidth>
33132 </field>
33133 <field>
33134 <name>FB17</name>
33135 <description>Filter bits</description>
33136 <bitOffset>17</bitOffset>
33137 <bitWidth>1</bitWidth>
33138 </field>
33139 <field>
33140 <name>FB18</name>
33141 <description>Filter bits</description>
33142 <bitOffset>18</bitOffset>
33143 <bitWidth>1</bitWidth>
33144 </field>
33145 <field>
33146 <name>FB19</name>
33147 <description>Filter bits</description>
33148 <bitOffset>19</bitOffset>
33149 <bitWidth>1</bitWidth>
33150 </field>
33151 <field>
33152 <name>FB20</name>
33153 <description>Filter bits</description>
33154 <bitOffset>20</bitOffset>
33155 <bitWidth>1</bitWidth>
33156 </field>
33157 <field>
33158 <name>FB21</name>
33159 <description>Filter bits</description>
33160 <bitOffset>21</bitOffset>
33161 <bitWidth>1</bitWidth>
33162 </field>
33163 <field>
33164 <name>FB22</name>
33165 <description>Filter bits</description>
33166 <bitOffset>22</bitOffset>
33167 <bitWidth>1</bitWidth>
33168 </field>
33169 <field>
33170 <name>FB23</name>
33171 <description>Filter bits</description>
33172 <bitOffset>23</bitOffset>
33173 <bitWidth>1</bitWidth>
33174 </field>
33175 <field>
33176 <name>FB24</name>
33177 <description>Filter bits</description>
33178 <bitOffset>24</bitOffset>
33179 <bitWidth>1</bitWidth>
33180 </field>
33181 <field>
33182 <name>FB25</name>
33183 <description>Filter bits</description>
33184 <bitOffset>25</bitOffset>
33185 <bitWidth>1</bitWidth>
33186 </field>
33187 <field>
33188 <name>FB26</name>
33189 <description>Filter bits</description>
33190 <bitOffset>26</bitOffset>
33191 <bitWidth>1</bitWidth>
33192 </field>
33193 <field>
33194 <name>FB27</name>
33195 <description>Filter bits</description>
33196 <bitOffset>27</bitOffset>
33197 <bitWidth>1</bitWidth>
33198 </field>
33199 <field>
33200 <name>FB28</name>
33201 <description>Filter bits</description>
33202 <bitOffset>28</bitOffset>
33203 <bitWidth>1</bitWidth>
33204 </field>
33205 <field>
33206 <name>FB29</name>
33207 <description>Filter bits</description>
33208 <bitOffset>29</bitOffset>
33209 <bitWidth>1</bitWidth>
33210 </field>
33211 <field>
33212 <name>FB30</name>
33213 <description>Filter bits</description>
33214 <bitOffset>30</bitOffset>
33215 <bitWidth>1</bitWidth>
33216 </field>
33217 <field>
33218 <name>FB31</name>
33219 <description>Filter bits</description>
33220 <bitOffset>31</bitOffset>
33221 <bitWidth>1</bitWidth>
33222 </field>
33223 </fields>
33224 </register>
33225 <register>
33226 <name>F11R2</name>
33227 <displayName>F11R2</displayName>
33228 <description>Filter bank 11 register 2</description>
33229 <addressOffset>0x29C</addressOffset>
33230 <size>0x20</size>
33231 <access>read-write</access>
33232 <resetValue>0x00000000</resetValue>
33233 <fields>
33234 <field>
33235 <name>FB0</name>
33236 <description>Filter bits</description>
33237 <bitOffset>0</bitOffset>
33238 <bitWidth>1</bitWidth>
33239 </field>
33240 <field>
33241 <name>FB1</name>
33242 <description>Filter bits</description>
33243 <bitOffset>1</bitOffset>
33244 <bitWidth>1</bitWidth>
33245 </field>
33246 <field>
33247 <name>FB2</name>
33248 <description>Filter bits</description>
33249 <bitOffset>2</bitOffset>
33250 <bitWidth>1</bitWidth>
33251 </field>
33252 <field>
33253 <name>FB3</name>
33254 <description>Filter bits</description>
33255 <bitOffset>3</bitOffset>
33256 <bitWidth>1</bitWidth>
33257 </field>
33258 <field>
33259 <name>FB4</name>
33260 <description>Filter bits</description>
33261 <bitOffset>4</bitOffset>
33262 <bitWidth>1</bitWidth>
33263 </field>
33264 <field>
33265 <name>FB5</name>
33266 <description>Filter bits</description>
33267 <bitOffset>5</bitOffset>
33268 <bitWidth>1</bitWidth>
33269 </field>
33270 <field>
33271 <name>FB6</name>
33272 <description>Filter bits</description>
33273 <bitOffset>6</bitOffset>
33274 <bitWidth>1</bitWidth>
33275 </field>
33276 <field>
33277 <name>FB7</name>
33278 <description>Filter bits</description>
33279 <bitOffset>7</bitOffset>
33280 <bitWidth>1</bitWidth>
33281 </field>
33282 <field>
33283 <name>FB8</name>
33284 <description>Filter bits</description>
33285 <bitOffset>8</bitOffset>
33286 <bitWidth>1</bitWidth>
33287 </field>
33288 <field>
33289 <name>FB9</name>
33290 <description>Filter bits</description>
33291 <bitOffset>9</bitOffset>
33292 <bitWidth>1</bitWidth>
33293 </field>
33294 <field>
33295 <name>FB10</name>
33296 <description>Filter bits</description>
33297 <bitOffset>10</bitOffset>
33298 <bitWidth>1</bitWidth>
33299 </field>
33300 <field>
33301 <name>FB11</name>
33302 <description>Filter bits</description>
33303 <bitOffset>11</bitOffset>
33304 <bitWidth>1</bitWidth>
33305 </field>
33306 <field>
33307 <name>FB12</name>
33308 <description>Filter bits</description>
33309 <bitOffset>12</bitOffset>
33310 <bitWidth>1</bitWidth>
33311 </field>
33312 <field>
33313 <name>FB13</name>
33314 <description>Filter bits</description>
33315 <bitOffset>13</bitOffset>
33316 <bitWidth>1</bitWidth>
33317 </field>
33318 <field>
33319 <name>FB14</name>
33320 <description>Filter bits</description>
33321 <bitOffset>14</bitOffset>
33322 <bitWidth>1</bitWidth>
33323 </field>
33324 <field>
33325 <name>FB15</name>
33326 <description>Filter bits</description>
33327 <bitOffset>15</bitOffset>
33328 <bitWidth>1</bitWidth>
33329 </field>
33330 <field>
33331 <name>FB16</name>
33332 <description>Filter bits</description>
33333 <bitOffset>16</bitOffset>
33334 <bitWidth>1</bitWidth>
33335 </field>
33336 <field>
33337 <name>FB17</name>
33338 <description>Filter bits</description>
33339 <bitOffset>17</bitOffset>
33340 <bitWidth>1</bitWidth>
33341 </field>
33342 <field>
33343 <name>FB18</name>
33344 <description>Filter bits</description>
33345 <bitOffset>18</bitOffset>
33346 <bitWidth>1</bitWidth>
33347 </field>
33348 <field>
33349 <name>FB19</name>
33350 <description>Filter bits</description>
33351 <bitOffset>19</bitOffset>
33352 <bitWidth>1</bitWidth>
33353 </field>
33354 <field>
33355 <name>FB20</name>
33356 <description>Filter bits</description>
33357 <bitOffset>20</bitOffset>
33358 <bitWidth>1</bitWidth>
33359 </field>
33360 <field>
33361 <name>FB21</name>
33362 <description>Filter bits</description>
33363 <bitOffset>21</bitOffset>
33364 <bitWidth>1</bitWidth>
33365 </field>
33366 <field>
33367 <name>FB22</name>
33368 <description>Filter bits</description>
33369 <bitOffset>22</bitOffset>
33370 <bitWidth>1</bitWidth>
33371 </field>
33372 <field>
33373 <name>FB23</name>
33374 <description>Filter bits</description>
33375 <bitOffset>23</bitOffset>
33376 <bitWidth>1</bitWidth>
33377 </field>
33378 <field>
33379 <name>FB24</name>
33380 <description>Filter bits</description>
33381 <bitOffset>24</bitOffset>
33382 <bitWidth>1</bitWidth>
33383 </field>
33384 <field>
33385 <name>FB25</name>
33386 <description>Filter bits</description>
33387 <bitOffset>25</bitOffset>
33388 <bitWidth>1</bitWidth>
33389 </field>
33390 <field>
33391 <name>FB26</name>
33392 <description>Filter bits</description>
33393 <bitOffset>26</bitOffset>
33394 <bitWidth>1</bitWidth>
33395 </field>
33396 <field>
33397 <name>FB27</name>
33398 <description>Filter bits</description>
33399 <bitOffset>27</bitOffset>
33400 <bitWidth>1</bitWidth>
33401 </field>
33402 <field>
33403 <name>FB28</name>
33404 <description>Filter bits</description>
33405 <bitOffset>28</bitOffset>
33406 <bitWidth>1</bitWidth>
33407 </field>
33408 <field>
33409 <name>FB29</name>
33410 <description>Filter bits</description>
33411 <bitOffset>29</bitOffset>
33412 <bitWidth>1</bitWidth>
33413 </field>
33414 <field>
33415 <name>FB30</name>
33416 <description>Filter bits</description>
33417 <bitOffset>30</bitOffset>
33418 <bitWidth>1</bitWidth>
33419 </field>
33420 <field>
33421 <name>FB31</name>
33422 <description>Filter bits</description>
33423 <bitOffset>31</bitOffset>
33424 <bitWidth>1</bitWidth>
33425 </field>
33426 </fields>
33427 </register>
33428 <register>
33429 <name>F12R1</name>
33430 <displayName>F12R1</displayName>
33431 <description>Filter bank 4 register 1</description>
33432 <addressOffset>0x2A0</addressOffset>
33433 <size>0x20</size>
33434 <access>read-write</access>
33435 <resetValue>0x00000000</resetValue>
33436 <fields>
33437 <field>
33438 <name>FB0</name>
33439 <description>Filter bits</description>
33440 <bitOffset>0</bitOffset>
33441 <bitWidth>1</bitWidth>
33442 </field>
33443 <field>
33444 <name>FB1</name>
33445 <description>Filter bits</description>
33446 <bitOffset>1</bitOffset>
33447 <bitWidth>1</bitWidth>
33448 </field>
33449 <field>
33450 <name>FB2</name>
33451 <description>Filter bits</description>
33452 <bitOffset>2</bitOffset>
33453 <bitWidth>1</bitWidth>
33454 </field>
33455 <field>
33456 <name>FB3</name>
33457 <description>Filter bits</description>
33458 <bitOffset>3</bitOffset>
33459 <bitWidth>1</bitWidth>
33460 </field>
33461 <field>
33462 <name>FB4</name>
33463 <description>Filter bits</description>
33464 <bitOffset>4</bitOffset>
33465 <bitWidth>1</bitWidth>
33466 </field>
33467 <field>
33468 <name>FB5</name>
33469 <description>Filter bits</description>
33470 <bitOffset>5</bitOffset>
33471 <bitWidth>1</bitWidth>
33472 </field>
33473 <field>
33474 <name>FB6</name>
33475 <description>Filter bits</description>
33476 <bitOffset>6</bitOffset>
33477 <bitWidth>1</bitWidth>
33478 </field>
33479 <field>
33480 <name>FB7</name>
33481 <description>Filter bits</description>
33482 <bitOffset>7</bitOffset>
33483 <bitWidth>1</bitWidth>
33484 </field>
33485 <field>
33486 <name>FB8</name>
33487 <description>Filter bits</description>
33488 <bitOffset>8</bitOffset>
33489 <bitWidth>1</bitWidth>
33490 </field>
33491 <field>
33492 <name>FB9</name>
33493 <description>Filter bits</description>
33494 <bitOffset>9</bitOffset>
33495 <bitWidth>1</bitWidth>
33496 </field>
33497 <field>
33498 <name>FB10</name>
33499 <description>Filter bits</description>
33500 <bitOffset>10</bitOffset>
33501 <bitWidth>1</bitWidth>
33502 </field>
33503 <field>
33504 <name>FB11</name>
33505 <description>Filter bits</description>
33506 <bitOffset>11</bitOffset>
33507 <bitWidth>1</bitWidth>
33508 </field>
33509 <field>
33510 <name>FB12</name>
33511 <description>Filter bits</description>
33512 <bitOffset>12</bitOffset>
33513 <bitWidth>1</bitWidth>
33514 </field>
33515 <field>
33516 <name>FB13</name>
33517 <description>Filter bits</description>
33518 <bitOffset>13</bitOffset>
33519 <bitWidth>1</bitWidth>
33520 </field>
33521 <field>
33522 <name>FB14</name>
33523 <description>Filter bits</description>
33524 <bitOffset>14</bitOffset>
33525 <bitWidth>1</bitWidth>
33526 </field>
33527 <field>
33528 <name>FB15</name>
33529 <description>Filter bits</description>
33530 <bitOffset>15</bitOffset>
33531 <bitWidth>1</bitWidth>
33532 </field>
33533 <field>
33534 <name>FB16</name>
33535 <description>Filter bits</description>
33536 <bitOffset>16</bitOffset>
33537 <bitWidth>1</bitWidth>
33538 </field>
33539 <field>
33540 <name>FB17</name>
33541 <description>Filter bits</description>
33542 <bitOffset>17</bitOffset>
33543 <bitWidth>1</bitWidth>
33544 </field>
33545 <field>
33546 <name>FB18</name>
33547 <description>Filter bits</description>
33548 <bitOffset>18</bitOffset>
33549 <bitWidth>1</bitWidth>
33550 </field>
33551 <field>
33552 <name>FB19</name>
33553 <description>Filter bits</description>
33554 <bitOffset>19</bitOffset>
33555 <bitWidth>1</bitWidth>
33556 </field>
33557 <field>
33558 <name>FB20</name>
33559 <description>Filter bits</description>
33560 <bitOffset>20</bitOffset>
33561 <bitWidth>1</bitWidth>
33562 </field>
33563 <field>
33564 <name>FB21</name>
33565 <description>Filter bits</description>
33566 <bitOffset>21</bitOffset>
33567 <bitWidth>1</bitWidth>
33568 </field>
33569 <field>
33570 <name>FB22</name>
33571 <description>Filter bits</description>
33572 <bitOffset>22</bitOffset>
33573 <bitWidth>1</bitWidth>
33574 </field>
33575 <field>
33576 <name>FB23</name>
33577 <description>Filter bits</description>
33578 <bitOffset>23</bitOffset>
33579 <bitWidth>1</bitWidth>
33580 </field>
33581 <field>
33582 <name>FB24</name>
33583 <description>Filter bits</description>
33584 <bitOffset>24</bitOffset>
33585 <bitWidth>1</bitWidth>
33586 </field>
33587 <field>
33588 <name>FB25</name>
33589 <description>Filter bits</description>
33590 <bitOffset>25</bitOffset>
33591 <bitWidth>1</bitWidth>
33592 </field>
33593 <field>
33594 <name>FB26</name>
33595 <description>Filter bits</description>
33596 <bitOffset>26</bitOffset>
33597 <bitWidth>1</bitWidth>
33598 </field>
33599 <field>
33600 <name>FB27</name>
33601 <description>Filter bits</description>
33602 <bitOffset>27</bitOffset>
33603 <bitWidth>1</bitWidth>
33604 </field>
33605 <field>
33606 <name>FB28</name>
33607 <description>Filter bits</description>
33608 <bitOffset>28</bitOffset>
33609 <bitWidth>1</bitWidth>
33610 </field>
33611 <field>
33612 <name>FB29</name>
33613 <description>Filter bits</description>
33614 <bitOffset>29</bitOffset>
33615 <bitWidth>1</bitWidth>
33616 </field>
33617 <field>
33618 <name>FB30</name>
33619 <description>Filter bits</description>
33620 <bitOffset>30</bitOffset>
33621 <bitWidth>1</bitWidth>
33622 </field>
33623 <field>
33624 <name>FB31</name>
33625 <description>Filter bits</description>
33626 <bitOffset>31</bitOffset>
33627 <bitWidth>1</bitWidth>
33628 </field>
33629 </fields>
33630 </register>
33631 <register>
33632 <name>F12R2</name>
33633 <displayName>F12R2</displayName>
33634 <description>Filter bank 12 register 2</description>
33635 <addressOffset>0x2A4</addressOffset>
33636 <size>0x20</size>
33637 <access>read-write</access>
33638 <resetValue>0x00000000</resetValue>
33639 <fields>
33640 <field>
33641 <name>FB0</name>
33642 <description>Filter bits</description>
33643 <bitOffset>0</bitOffset>
33644 <bitWidth>1</bitWidth>
33645 </field>
33646 <field>
33647 <name>FB1</name>
33648 <description>Filter bits</description>
33649 <bitOffset>1</bitOffset>
33650 <bitWidth>1</bitWidth>
33651 </field>
33652 <field>
33653 <name>FB2</name>
33654 <description>Filter bits</description>
33655 <bitOffset>2</bitOffset>
33656 <bitWidth>1</bitWidth>
33657 </field>
33658 <field>
33659 <name>FB3</name>
33660 <description>Filter bits</description>
33661 <bitOffset>3</bitOffset>
33662 <bitWidth>1</bitWidth>
33663 </field>
33664 <field>
33665 <name>FB4</name>
33666 <description>Filter bits</description>
33667 <bitOffset>4</bitOffset>
33668 <bitWidth>1</bitWidth>
33669 </field>
33670 <field>
33671 <name>FB5</name>
33672 <description>Filter bits</description>
33673 <bitOffset>5</bitOffset>
33674 <bitWidth>1</bitWidth>
33675 </field>
33676 <field>
33677 <name>FB6</name>
33678 <description>Filter bits</description>
33679 <bitOffset>6</bitOffset>
33680 <bitWidth>1</bitWidth>
33681 </field>
33682 <field>
33683 <name>FB7</name>
33684 <description>Filter bits</description>
33685 <bitOffset>7</bitOffset>
33686 <bitWidth>1</bitWidth>
33687 </field>
33688 <field>
33689 <name>FB8</name>
33690 <description>Filter bits</description>
33691 <bitOffset>8</bitOffset>
33692 <bitWidth>1</bitWidth>
33693 </field>
33694 <field>
33695 <name>FB9</name>
33696 <description>Filter bits</description>
33697 <bitOffset>9</bitOffset>
33698 <bitWidth>1</bitWidth>
33699 </field>
33700 <field>
33701 <name>FB10</name>
33702 <description>Filter bits</description>
33703 <bitOffset>10</bitOffset>
33704 <bitWidth>1</bitWidth>
33705 </field>
33706 <field>
33707 <name>FB11</name>
33708 <description>Filter bits</description>
33709 <bitOffset>11</bitOffset>
33710 <bitWidth>1</bitWidth>
33711 </field>
33712 <field>
33713 <name>FB12</name>
33714 <description>Filter bits</description>
33715 <bitOffset>12</bitOffset>
33716 <bitWidth>1</bitWidth>
33717 </field>
33718 <field>
33719 <name>FB13</name>
33720 <description>Filter bits</description>
33721 <bitOffset>13</bitOffset>
33722 <bitWidth>1</bitWidth>
33723 </field>
33724 <field>
33725 <name>FB14</name>
33726 <description>Filter bits</description>
33727 <bitOffset>14</bitOffset>
33728 <bitWidth>1</bitWidth>
33729 </field>
33730 <field>
33731 <name>FB15</name>
33732 <description>Filter bits</description>
33733 <bitOffset>15</bitOffset>
33734 <bitWidth>1</bitWidth>
33735 </field>
33736 <field>
33737 <name>FB16</name>
33738 <description>Filter bits</description>
33739 <bitOffset>16</bitOffset>
33740 <bitWidth>1</bitWidth>
33741 </field>
33742 <field>
33743 <name>FB17</name>
33744 <description>Filter bits</description>
33745 <bitOffset>17</bitOffset>
33746 <bitWidth>1</bitWidth>
33747 </field>
33748 <field>
33749 <name>FB18</name>
33750 <description>Filter bits</description>
33751 <bitOffset>18</bitOffset>
33752 <bitWidth>1</bitWidth>
33753 </field>
33754 <field>
33755 <name>FB19</name>
33756 <description>Filter bits</description>
33757 <bitOffset>19</bitOffset>
33758 <bitWidth>1</bitWidth>
33759 </field>
33760 <field>
33761 <name>FB20</name>
33762 <description>Filter bits</description>
33763 <bitOffset>20</bitOffset>
33764 <bitWidth>1</bitWidth>
33765 </field>
33766 <field>
33767 <name>FB21</name>
33768 <description>Filter bits</description>
33769 <bitOffset>21</bitOffset>
33770 <bitWidth>1</bitWidth>
33771 </field>
33772 <field>
33773 <name>FB22</name>
33774 <description>Filter bits</description>
33775 <bitOffset>22</bitOffset>
33776 <bitWidth>1</bitWidth>
33777 </field>
33778 <field>
33779 <name>FB23</name>
33780 <description>Filter bits</description>
33781 <bitOffset>23</bitOffset>
33782 <bitWidth>1</bitWidth>
33783 </field>
33784 <field>
33785 <name>FB24</name>
33786 <description>Filter bits</description>
33787 <bitOffset>24</bitOffset>
33788 <bitWidth>1</bitWidth>
33789 </field>
33790 <field>
33791 <name>FB25</name>
33792 <description>Filter bits</description>
33793 <bitOffset>25</bitOffset>
33794 <bitWidth>1</bitWidth>
33795 </field>
33796 <field>
33797 <name>FB26</name>
33798 <description>Filter bits</description>
33799 <bitOffset>26</bitOffset>
33800 <bitWidth>1</bitWidth>
33801 </field>
33802 <field>
33803 <name>FB27</name>
33804 <description>Filter bits</description>
33805 <bitOffset>27</bitOffset>
33806 <bitWidth>1</bitWidth>
33807 </field>
33808 <field>
33809 <name>FB28</name>
33810 <description>Filter bits</description>
33811 <bitOffset>28</bitOffset>
33812 <bitWidth>1</bitWidth>
33813 </field>
33814 <field>
33815 <name>FB29</name>
33816 <description>Filter bits</description>
33817 <bitOffset>29</bitOffset>
33818 <bitWidth>1</bitWidth>
33819 </field>
33820 <field>
33821 <name>FB30</name>
33822 <description>Filter bits</description>
33823 <bitOffset>30</bitOffset>
33824 <bitWidth>1</bitWidth>
33825 </field>
33826 <field>
33827 <name>FB31</name>
33828 <description>Filter bits</description>
33829 <bitOffset>31</bitOffset>
33830 <bitWidth>1</bitWidth>
33831 </field>
33832 </fields>
33833 </register>
33834 <register>
33835 <name>F13R1</name>
33836 <displayName>F13R1</displayName>
33837 <description>Filter bank 13 register 1</description>
33838 <addressOffset>0x2A8</addressOffset>
33839 <size>0x20</size>
33840 <access>read-write</access>
33841 <resetValue>0x00000000</resetValue>
33842 <fields>
33843 <field>
33844 <name>FB0</name>
33845 <description>Filter bits</description>
33846 <bitOffset>0</bitOffset>
33847 <bitWidth>1</bitWidth>
33848 </field>
33849 <field>
33850 <name>FB1</name>
33851 <description>Filter bits</description>
33852 <bitOffset>1</bitOffset>
33853 <bitWidth>1</bitWidth>
33854 </field>
33855 <field>
33856 <name>FB2</name>
33857 <description>Filter bits</description>
33858 <bitOffset>2</bitOffset>
33859 <bitWidth>1</bitWidth>
33860 </field>
33861 <field>
33862 <name>FB3</name>
33863 <description>Filter bits</description>
33864 <bitOffset>3</bitOffset>
33865 <bitWidth>1</bitWidth>
33866 </field>
33867 <field>
33868 <name>FB4</name>
33869 <description>Filter bits</description>
33870 <bitOffset>4</bitOffset>
33871 <bitWidth>1</bitWidth>
33872 </field>
33873 <field>
33874 <name>FB5</name>
33875 <description>Filter bits</description>
33876 <bitOffset>5</bitOffset>
33877 <bitWidth>1</bitWidth>
33878 </field>
33879 <field>
33880 <name>FB6</name>
33881 <description>Filter bits</description>
33882 <bitOffset>6</bitOffset>
33883 <bitWidth>1</bitWidth>
33884 </field>
33885 <field>
33886 <name>FB7</name>
33887 <description>Filter bits</description>
33888 <bitOffset>7</bitOffset>
33889 <bitWidth>1</bitWidth>
33890 </field>
33891 <field>
33892 <name>FB8</name>
33893 <description>Filter bits</description>
33894 <bitOffset>8</bitOffset>
33895 <bitWidth>1</bitWidth>
33896 </field>
33897 <field>
33898 <name>FB9</name>
33899 <description>Filter bits</description>
33900 <bitOffset>9</bitOffset>
33901 <bitWidth>1</bitWidth>
33902 </field>
33903 <field>
33904 <name>FB10</name>
33905 <description>Filter bits</description>
33906 <bitOffset>10</bitOffset>
33907 <bitWidth>1</bitWidth>
33908 </field>
33909 <field>
33910 <name>FB11</name>
33911 <description>Filter bits</description>
33912 <bitOffset>11</bitOffset>
33913 <bitWidth>1</bitWidth>
33914 </field>
33915 <field>
33916 <name>FB12</name>
33917 <description>Filter bits</description>
33918 <bitOffset>12</bitOffset>
33919 <bitWidth>1</bitWidth>
33920 </field>
33921 <field>
33922 <name>FB13</name>
33923 <description>Filter bits</description>
33924 <bitOffset>13</bitOffset>
33925 <bitWidth>1</bitWidth>
33926 </field>
33927 <field>
33928 <name>FB14</name>
33929 <description>Filter bits</description>
33930 <bitOffset>14</bitOffset>
33931 <bitWidth>1</bitWidth>
33932 </field>
33933 <field>
33934 <name>FB15</name>
33935 <description>Filter bits</description>
33936 <bitOffset>15</bitOffset>
33937 <bitWidth>1</bitWidth>
33938 </field>
33939 <field>
33940 <name>FB16</name>
33941 <description>Filter bits</description>
33942 <bitOffset>16</bitOffset>
33943 <bitWidth>1</bitWidth>
33944 </field>
33945 <field>
33946 <name>FB17</name>
33947 <description>Filter bits</description>
33948 <bitOffset>17</bitOffset>
33949 <bitWidth>1</bitWidth>
33950 </field>
33951 <field>
33952 <name>FB18</name>
33953 <description>Filter bits</description>
33954 <bitOffset>18</bitOffset>
33955 <bitWidth>1</bitWidth>
33956 </field>
33957 <field>
33958 <name>FB19</name>
33959 <description>Filter bits</description>
33960 <bitOffset>19</bitOffset>
33961 <bitWidth>1</bitWidth>
33962 </field>
33963 <field>
33964 <name>FB20</name>
33965 <description>Filter bits</description>
33966 <bitOffset>20</bitOffset>
33967 <bitWidth>1</bitWidth>
33968 </field>
33969 <field>
33970 <name>FB21</name>
33971 <description>Filter bits</description>
33972 <bitOffset>21</bitOffset>
33973 <bitWidth>1</bitWidth>
33974 </field>
33975 <field>
33976 <name>FB22</name>
33977 <description>Filter bits</description>
33978 <bitOffset>22</bitOffset>
33979 <bitWidth>1</bitWidth>
33980 </field>
33981 <field>
33982 <name>FB23</name>
33983 <description>Filter bits</description>
33984 <bitOffset>23</bitOffset>
33985 <bitWidth>1</bitWidth>
33986 </field>
33987 <field>
33988 <name>FB24</name>
33989 <description>Filter bits</description>
33990 <bitOffset>24</bitOffset>
33991 <bitWidth>1</bitWidth>
33992 </field>
33993 <field>
33994 <name>FB25</name>
33995 <description>Filter bits</description>
33996 <bitOffset>25</bitOffset>
33997 <bitWidth>1</bitWidth>
33998 </field>
33999 <field>
34000 <name>FB26</name>
34001 <description>Filter bits</description>
34002 <bitOffset>26</bitOffset>
34003 <bitWidth>1</bitWidth>
34004 </field>
34005 <field>
34006 <name>FB27</name>
34007 <description>Filter bits</description>
34008 <bitOffset>27</bitOffset>
34009 <bitWidth>1</bitWidth>
34010 </field>
34011 <field>
34012 <name>FB28</name>
34013 <description>Filter bits</description>
34014 <bitOffset>28</bitOffset>
34015 <bitWidth>1</bitWidth>
34016 </field>
34017 <field>
34018 <name>FB29</name>
34019 <description>Filter bits</description>
34020 <bitOffset>29</bitOffset>
34021 <bitWidth>1</bitWidth>
34022 </field>
34023 <field>
34024 <name>FB30</name>
34025 <description>Filter bits</description>
34026 <bitOffset>30</bitOffset>
34027 <bitWidth>1</bitWidth>
34028 </field>
34029 <field>
34030 <name>FB31</name>
34031 <description>Filter bits</description>
34032 <bitOffset>31</bitOffset>
34033 <bitWidth>1</bitWidth>
34034 </field>
34035 </fields>
34036 </register>
34037 <register>
34038 <name>F13R2</name>
34039 <displayName>F13R2</displayName>
34040 <description>Filter bank 13 register 2</description>
34041 <addressOffset>0x2AC</addressOffset>
34042 <size>0x20</size>
34043 <access>read-write</access>
34044 <resetValue>0x00000000</resetValue>
34045 <fields>
34046 <field>
34047 <name>FB0</name>
34048 <description>Filter bits</description>
34049 <bitOffset>0</bitOffset>
34050 <bitWidth>1</bitWidth>
34051 </field>
34052 <field>
34053 <name>FB1</name>
34054 <description>Filter bits</description>
34055 <bitOffset>1</bitOffset>
34056 <bitWidth>1</bitWidth>
34057 </field>
34058 <field>
34059 <name>FB2</name>
34060 <description>Filter bits</description>
34061 <bitOffset>2</bitOffset>
34062 <bitWidth>1</bitWidth>
34063 </field>
34064 <field>
34065 <name>FB3</name>
34066 <description>Filter bits</description>
34067 <bitOffset>3</bitOffset>
34068 <bitWidth>1</bitWidth>
34069 </field>
34070 <field>
34071 <name>FB4</name>
34072 <description>Filter bits</description>
34073 <bitOffset>4</bitOffset>
34074 <bitWidth>1</bitWidth>
34075 </field>
34076 <field>
34077 <name>FB5</name>
34078 <description>Filter bits</description>
34079 <bitOffset>5</bitOffset>
34080 <bitWidth>1</bitWidth>
34081 </field>
34082 <field>
34083 <name>FB6</name>
34084 <description>Filter bits</description>
34085 <bitOffset>6</bitOffset>
34086 <bitWidth>1</bitWidth>
34087 </field>
34088 <field>
34089 <name>FB7</name>
34090 <description>Filter bits</description>
34091 <bitOffset>7</bitOffset>
34092 <bitWidth>1</bitWidth>
34093 </field>
34094 <field>
34095 <name>FB8</name>
34096 <description>Filter bits</description>
34097 <bitOffset>8</bitOffset>
34098 <bitWidth>1</bitWidth>
34099 </field>
34100 <field>
34101 <name>FB9</name>
34102 <description>Filter bits</description>
34103 <bitOffset>9</bitOffset>
34104 <bitWidth>1</bitWidth>
34105 </field>
34106 <field>
34107 <name>FB10</name>
34108 <description>Filter bits</description>
34109 <bitOffset>10</bitOffset>
34110 <bitWidth>1</bitWidth>
34111 </field>
34112 <field>
34113 <name>FB11</name>
34114 <description>Filter bits</description>
34115 <bitOffset>11</bitOffset>
34116 <bitWidth>1</bitWidth>
34117 </field>
34118 <field>
34119 <name>FB12</name>
34120 <description>Filter bits</description>
34121 <bitOffset>12</bitOffset>
34122 <bitWidth>1</bitWidth>
34123 </field>
34124 <field>
34125 <name>FB13</name>
34126 <description>Filter bits</description>
34127 <bitOffset>13</bitOffset>
34128 <bitWidth>1</bitWidth>
34129 </field>
34130 <field>
34131 <name>FB14</name>
34132 <description>Filter bits</description>
34133 <bitOffset>14</bitOffset>
34134 <bitWidth>1</bitWidth>
34135 </field>
34136 <field>
34137 <name>FB15</name>
34138 <description>Filter bits</description>
34139 <bitOffset>15</bitOffset>
34140 <bitWidth>1</bitWidth>
34141 </field>
34142 <field>
34143 <name>FB16</name>
34144 <description>Filter bits</description>
34145 <bitOffset>16</bitOffset>
34146 <bitWidth>1</bitWidth>
34147 </field>
34148 <field>
34149 <name>FB17</name>
34150 <description>Filter bits</description>
34151 <bitOffset>17</bitOffset>
34152 <bitWidth>1</bitWidth>
34153 </field>
34154 <field>
34155 <name>FB18</name>
34156 <description>Filter bits</description>
34157 <bitOffset>18</bitOffset>
34158 <bitWidth>1</bitWidth>
34159 </field>
34160 <field>
34161 <name>FB19</name>
34162 <description>Filter bits</description>
34163 <bitOffset>19</bitOffset>
34164 <bitWidth>1</bitWidth>
34165 </field>
34166 <field>
34167 <name>FB20</name>
34168 <description>Filter bits</description>
34169 <bitOffset>20</bitOffset>
34170 <bitWidth>1</bitWidth>
34171 </field>
34172 <field>
34173 <name>FB21</name>
34174 <description>Filter bits</description>
34175 <bitOffset>21</bitOffset>
34176 <bitWidth>1</bitWidth>
34177 </field>
34178 <field>
34179 <name>FB22</name>
34180 <description>Filter bits</description>
34181 <bitOffset>22</bitOffset>
34182 <bitWidth>1</bitWidth>
34183 </field>
34184 <field>
34185 <name>FB23</name>
34186 <description>Filter bits</description>
34187 <bitOffset>23</bitOffset>
34188 <bitWidth>1</bitWidth>
34189 </field>
34190 <field>
34191 <name>FB24</name>
34192 <description>Filter bits</description>
34193 <bitOffset>24</bitOffset>
34194 <bitWidth>1</bitWidth>
34195 </field>
34196 <field>
34197 <name>FB25</name>
34198 <description>Filter bits</description>
34199 <bitOffset>25</bitOffset>
34200 <bitWidth>1</bitWidth>
34201 </field>
34202 <field>
34203 <name>FB26</name>
34204 <description>Filter bits</description>
34205 <bitOffset>26</bitOffset>
34206 <bitWidth>1</bitWidth>
34207 </field>
34208 <field>
34209 <name>FB27</name>
34210 <description>Filter bits</description>
34211 <bitOffset>27</bitOffset>
34212 <bitWidth>1</bitWidth>
34213 </field>
34214 <field>
34215 <name>FB28</name>
34216 <description>Filter bits</description>
34217 <bitOffset>28</bitOffset>
34218 <bitWidth>1</bitWidth>
34219 </field>
34220 <field>
34221 <name>FB29</name>
34222 <description>Filter bits</description>
34223 <bitOffset>29</bitOffset>
34224 <bitWidth>1</bitWidth>
34225 </field>
34226 <field>
34227 <name>FB30</name>
34228 <description>Filter bits</description>
34229 <bitOffset>30</bitOffset>
34230 <bitWidth>1</bitWidth>
34231 </field>
34232 <field>
34233 <name>FB31</name>
34234 <description>Filter bits</description>
34235 <bitOffset>31</bitOffset>
34236 <bitWidth>1</bitWidth>
34237 </field>
34238 </fields>
34239 </register>
34240 <register>
34241 <name>F14R1</name>
34242 <displayName>F14R1</displayName>
34243 <description>Filter bank 14 register 1</description>
34244 <addressOffset>0x2B0</addressOffset>
34245 <size>0x20</size>
34246 <access>read-write</access>
34247 <resetValue>0x00000000</resetValue>
34248 <fields>
34249 <field>
34250 <name>FB0</name>
34251 <description>Filter bits</description>
34252 <bitOffset>0</bitOffset>
34253 <bitWidth>1</bitWidth>
34254 </field>
34255 <field>
34256 <name>FB1</name>
34257 <description>Filter bits</description>
34258 <bitOffset>1</bitOffset>
34259 <bitWidth>1</bitWidth>
34260 </field>
34261 <field>
34262 <name>FB2</name>
34263 <description>Filter bits</description>
34264 <bitOffset>2</bitOffset>
34265 <bitWidth>1</bitWidth>
34266 </field>
34267 <field>
34268 <name>FB3</name>
34269 <description>Filter bits</description>
34270 <bitOffset>3</bitOffset>
34271 <bitWidth>1</bitWidth>
34272 </field>
34273 <field>
34274 <name>FB4</name>
34275 <description>Filter bits</description>
34276 <bitOffset>4</bitOffset>
34277 <bitWidth>1</bitWidth>
34278 </field>
34279 <field>
34280 <name>FB5</name>
34281 <description>Filter bits</description>
34282 <bitOffset>5</bitOffset>
34283 <bitWidth>1</bitWidth>
34284 </field>
34285 <field>
34286 <name>FB6</name>
34287 <description>Filter bits</description>
34288 <bitOffset>6</bitOffset>
34289 <bitWidth>1</bitWidth>
34290 </field>
34291 <field>
34292 <name>FB7</name>
34293 <description>Filter bits</description>
34294 <bitOffset>7</bitOffset>
34295 <bitWidth>1</bitWidth>
34296 </field>
34297 <field>
34298 <name>FB8</name>
34299 <description>Filter bits</description>
34300 <bitOffset>8</bitOffset>
34301 <bitWidth>1</bitWidth>
34302 </field>
34303 <field>
34304 <name>FB9</name>
34305 <description>Filter bits</description>
34306 <bitOffset>9</bitOffset>
34307 <bitWidth>1</bitWidth>
34308 </field>
34309 <field>
34310 <name>FB10</name>
34311 <description>Filter bits</description>
34312 <bitOffset>10</bitOffset>
34313 <bitWidth>1</bitWidth>
34314 </field>
34315 <field>
34316 <name>FB11</name>
34317 <description>Filter bits</description>
34318 <bitOffset>11</bitOffset>
34319 <bitWidth>1</bitWidth>
34320 </field>
34321 <field>
34322 <name>FB12</name>
34323 <description>Filter bits</description>
34324 <bitOffset>12</bitOffset>
34325 <bitWidth>1</bitWidth>
34326 </field>
34327 <field>
34328 <name>FB13</name>
34329 <description>Filter bits</description>
34330 <bitOffset>13</bitOffset>
34331 <bitWidth>1</bitWidth>
34332 </field>
34333 <field>
34334 <name>FB14</name>
34335 <description>Filter bits</description>
34336 <bitOffset>14</bitOffset>
34337 <bitWidth>1</bitWidth>
34338 </field>
34339 <field>
34340 <name>FB15</name>
34341 <description>Filter bits</description>
34342 <bitOffset>15</bitOffset>
34343 <bitWidth>1</bitWidth>
34344 </field>
34345 <field>
34346 <name>FB16</name>
34347 <description>Filter bits</description>
34348 <bitOffset>16</bitOffset>
34349 <bitWidth>1</bitWidth>
34350 </field>
34351 <field>
34352 <name>FB17</name>
34353 <description>Filter bits</description>
34354 <bitOffset>17</bitOffset>
34355 <bitWidth>1</bitWidth>
34356 </field>
34357 <field>
34358 <name>FB18</name>
34359 <description>Filter bits</description>
34360 <bitOffset>18</bitOffset>
34361 <bitWidth>1</bitWidth>
34362 </field>
34363 <field>
34364 <name>FB19</name>
34365 <description>Filter bits</description>
34366 <bitOffset>19</bitOffset>
34367 <bitWidth>1</bitWidth>
34368 </field>
34369 <field>
34370 <name>FB20</name>
34371 <description>Filter bits</description>
34372 <bitOffset>20</bitOffset>
34373 <bitWidth>1</bitWidth>
34374 </field>
34375 <field>
34376 <name>FB21</name>
34377 <description>Filter bits</description>
34378 <bitOffset>21</bitOffset>
34379 <bitWidth>1</bitWidth>
34380 </field>
34381 <field>
34382 <name>FB22</name>
34383 <description>Filter bits</description>
34384 <bitOffset>22</bitOffset>
34385 <bitWidth>1</bitWidth>
34386 </field>
34387 <field>
34388 <name>FB23</name>
34389 <description>Filter bits</description>
34390 <bitOffset>23</bitOffset>
34391 <bitWidth>1</bitWidth>
34392 </field>
34393 <field>
34394 <name>FB24</name>
34395 <description>Filter bits</description>
34396 <bitOffset>24</bitOffset>
34397 <bitWidth>1</bitWidth>
34398 </field>
34399 <field>
34400 <name>FB25</name>
34401 <description>Filter bits</description>
34402 <bitOffset>25</bitOffset>
34403 <bitWidth>1</bitWidth>
34404 </field>
34405 <field>
34406 <name>FB26</name>
34407 <description>Filter bits</description>
34408 <bitOffset>26</bitOffset>
34409 <bitWidth>1</bitWidth>
34410 </field>
34411 <field>
34412 <name>FB27</name>
34413 <description>Filter bits</description>
34414 <bitOffset>27</bitOffset>
34415 <bitWidth>1</bitWidth>
34416 </field>
34417 <field>
34418 <name>FB28</name>
34419 <description>Filter bits</description>
34420 <bitOffset>28</bitOffset>
34421 <bitWidth>1</bitWidth>
34422 </field>
34423 <field>
34424 <name>FB29</name>
34425 <description>Filter bits</description>
34426 <bitOffset>29</bitOffset>
34427 <bitWidth>1</bitWidth>
34428 </field>
34429 <field>
34430 <name>FB30</name>
34431 <description>Filter bits</description>
34432 <bitOffset>30</bitOffset>
34433 <bitWidth>1</bitWidth>
34434 </field>
34435 <field>
34436 <name>FB31</name>
34437 <description>Filter bits</description>
34438 <bitOffset>31</bitOffset>
34439 <bitWidth>1</bitWidth>
34440 </field>
34441 </fields>
34442 </register>
34443 <register>
34444 <name>F14R2</name>
34445 <displayName>F14R2</displayName>
34446 <description>Filter bank 14 register 2</description>
34447 <addressOffset>0x2B4</addressOffset>
34448 <size>0x20</size>
34449 <access>read-write</access>
34450 <resetValue>0x00000000</resetValue>
34451 <fields>
34452 <field>
34453 <name>FB0</name>
34454 <description>Filter bits</description>
34455 <bitOffset>0</bitOffset>
34456 <bitWidth>1</bitWidth>
34457 </field>
34458 <field>
34459 <name>FB1</name>
34460 <description>Filter bits</description>
34461 <bitOffset>1</bitOffset>
34462 <bitWidth>1</bitWidth>
34463 </field>
34464 <field>
34465 <name>FB2</name>
34466 <description>Filter bits</description>
34467 <bitOffset>2</bitOffset>
34468 <bitWidth>1</bitWidth>
34469 </field>
34470 <field>
34471 <name>FB3</name>
34472 <description>Filter bits</description>
34473 <bitOffset>3</bitOffset>
34474 <bitWidth>1</bitWidth>
34475 </field>
34476 <field>
34477 <name>FB4</name>
34478 <description>Filter bits</description>
34479 <bitOffset>4</bitOffset>
34480 <bitWidth>1</bitWidth>
34481 </field>
34482 <field>
34483 <name>FB5</name>
34484 <description>Filter bits</description>
34485 <bitOffset>5</bitOffset>
34486 <bitWidth>1</bitWidth>
34487 </field>
34488 <field>
34489 <name>FB6</name>
34490 <description>Filter bits</description>
34491 <bitOffset>6</bitOffset>
34492 <bitWidth>1</bitWidth>
34493 </field>
34494 <field>
34495 <name>FB7</name>
34496 <description>Filter bits</description>
34497 <bitOffset>7</bitOffset>
34498 <bitWidth>1</bitWidth>
34499 </field>
34500 <field>
34501 <name>FB8</name>
34502 <description>Filter bits</description>
34503 <bitOffset>8</bitOffset>
34504 <bitWidth>1</bitWidth>
34505 </field>
34506 <field>
34507 <name>FB9</name>
34508 <description>Filter bits</description>
34509 <bitOffset>9</bitOffset>
34510 <bitWidth>1</bitWidth>
34511 </field>
34512 <field>
34513 <name>FB10</name>
34514 <description>Filter bits</description>
34515 <bitOffset>10</bitOffset>
34516 <bitWidth>1</bitWidth>
34517 </field>
34518 <field>
34519 <name>FB11</name>
34520 <description>Filter bits</description>
34521 <bitOffset>11</bitOffset>
34522 <bitWidth>1</bitWidth>
34523 </field>
34524 <field>
34525 <name>FB12</name>
34526 <description>Filter bits</description>
34527 <bitOffset>12</bitOffset>
34528 <bitWidth>1</bitWidth>
34529 </field>
34530 <field>
34531 <name>FB13</name>
34532 <description>Filter bits</description>
34533 <bitOffset>13</bitOffset>
34534 <bitWidth>1</bitWidth>
34535 </field>
34536 <field>
34537 <name>FB14</name>
34538 <description>Filter bits</description>
34539 <bitOffset>14</bitOffset>
34540 <bitWidth>1</bitWidth>
34541 </field>
34542 <field>
34543 <name>FB15</name>
34544 <description>Filter bits</description>
34545 <bitOffset>15</bitOffset>
34546 <bitWidth>1</bitWidth>
34547 </field>
34548 <field>
34549 <name>FB16</name>
34550 <description>Filter bits</description>
34551 <bitOffset>16</bitOffset>
34552 <bitWidth>1</bitWidth>
34553 </field>
34554 <field>
34555 <name>FB17</name>
34556 <description>Filter bits</description>
34557 <bitOffset>17</bitOffset>
34558 <bitWidth>1</bitWidth>
34559 </field>
34560 <field>
34561 <name>FB18</name>
34562 <description>Filter bits</description>
34563 <bitOffset>18</bitOffset>
34564 <bitWidth>1</bitWidth>
34565 </field>
34566 <field>
34567 <name>FB19</name>
34568 <description>Filter bits</description>
34569 <bitOffset>19</bitOffset>
34570 <bitWidth>1</bitWidth>
34571 </field>
34572 <field>
34573 <name>FB20</name>
34574 <description>Filter bits</description>
34575 <bitOffset>20</bitOffset>
34576 <bitWidth>1</bitWidth>
34577 </field>
34578 <field>
34579 <name>FB21</name>
34580 <description>Filter bits</description>
34581 <bitOffset>21</bitOffset>
34582 <bitWidth>1</bitWidth>
34583 </field>
34584 <field>
34585 <name>FB22</name>
34586 <description>Filter bits</description>
34587 <bitOffset>22</bitOffset>
34588 <bitWidth>1</bitWidth>
34589 </field>
34590 <field>
34591 <name>FB23</name>
34592 <description>Filter bits</description>
34593 <bitOffset>23</bitOffset>
34594 <bitWidth>1</bitWidth>
34595 </field>
34596 <field>
34597 <name>FB24</name>
34598 <description>Filter bits</description>
34599 <bitOffset>24</bitOffset>
34600 <bitWidth>1</bitWidth>
34601 </field>
34602 <field>
34603 <name>FB25</name>
34604 <description>Filter bits</description>
34605 <bitOffset>25</bitOffset>
34606 <bitWidth>1</bitWidth>
34607 </field>
34608 <field>
34609 <name>FB26</name>
34610 <description>Filter bits</description>
34611 <bitOffset>26</bitOffset>
34612 <bitWidth>1</bitWidth>
34613 </field>
34614 <field>
34615 <name>FB27</name>
34616 <description>Filter bits</description>
34617 <bitOffset>27</bitOffset>
34618 <bitWidth>1</bitWidth>
34619 </field>
34620 <field>
34621 <name>FB28</name>
34622 <description>Filter bits</description>
34623 <bitOffset>28</bitOffset>
34624 <bitWidth>1</bitWidth>
34625 </field>
34626 <field>
34627 <name>FB29</name>
34628 <description>Filter bits</description>
34629 <bitOffset>29</bitOffset>
34630 <bitWidth>1</bitWidth>
34631 </field>
34632 <field>
34633 <name>FB30</name>
34634 <description>Filter bits</description>
34635 <bitOffset>30</bitOffset>
34636 <bitWidth>1</bitWidth>
34637 </field>
34638 <field>
34639 <name>FB31</name>
34640 <description>Filter bits</description>
34641 <bitOffset>31</bitOffset>
34642 <bitWidth>1</bitWidth>
34643 </field>
34644 </fields>
34645 </register>
34646 <register>
34647 <name>F15R1</name>
34648 <displayName>F15R1</displayName>
34649 <description>Filter bank 15 register 1</description>
34650 <addressOffset>0x2B8</addressOffset>
34651 <size>0x20</size>
34652 <access>read-write</access>
34653 <resetValue>0x00000000</resetValue>
34654 <fields>
34655 <field>
34656 <name>FB0</name>
34657 <description>Filter bits</description>
34658 <bitOffset>0</bitOffset>
34659 <bitWidth>1</bitWidth>
34660 </field>
34661 <field>
34662 <name>FB1</name>
34663 <description>Filter bits</description>
34664 <bitOffset>1</bitOffset>
34665 <bitWidth>1</bitWidth>
34666 </field>
34667 <field>
34668 <name>FB2</name>
34669 <description>Filter bits</description>
34670 <bitOffset>2</bitOffset>
34671 <bitWidth>1</bitWidth>
34672 </field>
34673 <field>
34674 <name>FB3</name>
34675 <description>Filter bits</description>
34676 <bitOffset>3</bitOffset>
34677 <bitWidth>1</bitWidth>
34678 </field>
34679 <field>
34680 <name>FB4</name>
34681 <description>Filter bits</description>
34682 <bitOffset>4</bitOffset>
34683 <bitWidth>1</bitWidth>
34684 </field>
34685 <field>
34686 <name>FB5</name>
34687 <description>Filter bits</description>
34688 <bitOffset>5</bitOffset>
34689 <bitWidth>1</bitWidth>
34690 </field>
34691 <field>
34692 <name>FB6</name>
34693 <description>Filter bits</description>
34694 <bitOffset>6</bitOffset>
34695 <bitWidth>1</bitWidth>
34696 </field>
34697 <field>
34698 <name>FB7</name>
34699 <description>Filter bits</description>
34700 <bitOffset>7</bitOffset>
34701 <bitWidth>1</bitWidth>
34702 </field>
34703 <field>
34704 <name>FB8</name>
34705 <description>Filter bits</description>
34706 <bitOffset>8</bitOffset>
34707 <bitWidth>1</bitWidth>
34708 </field>
34709 <field>
34710 <name>FB9</name>
34711 <description>Filter bits</description>
34712 <bitOffset>9</bitOffset>
34713 <bitWidth>1</bitWidth>
34714 </field>
34715 <field>
34716 <name>FB10</name>
34717 <description>Filter bits</description>
34718 <bitOffset>10</bitOffset>
34719 <bitWidth>1</bitWidth>
34720 </field>
34721 <field>
34722 <name>FB11</name>
34723 <description>Filter bits</description>
34724 <bitOffset>11</bitOffset>
34725 <bitWidth>1</bitWidth>
34726 </field>
34727 <field>
34728 <name>FB12</name>
34729 <description>Filter bits</description>
34730 <bitOffset>12</bitOffset>
34731 <bitWidth>1</bitWidth>
34732 </field>
34733 <field>
34734 <name>FB13</name>
34735 <description>Filter bits</description>
34736 <bitOffset>13</bitOffset>
34737 <bitWidth>1</bitWidth>
34738 </field>
34739 <field>
34740 <name>FB14</name>
34741 <description>Filter bits</description>
34742 <bitOffset>14</bitOffset>
34743 <bitWidth>1</bitWidth>
34744 </field>
34745 <field>
34746 <name>FB15</name>
34747 <description>Filter bits</description>
34748 <bitOffset>15</bitOffset>
34749 <bitWidth>1</bitWidth>
34750 </field>
34751 <field>
34752 <name>FB16</name>
34753 <description>Filter bits</description>
34754 <bitOffset>16</bitOffset>
34755 <bitWidth>1</bitWidth>
34756 </field>
34757 <field>
34758 <name>FB17</name>
34759 <description>Filter bits</description>
34760 <bitOffset>17</bitOffset>
34761 <bitWidth>1</bitWidth>
34762 </field>
34763 <field>
34764 <name>FB18</name>
34765 <description>Filter bits</description>
34766 <bitOffset>18</bitOffset>
34767 <bitWidth>1</bitWidth>
34768 </field>
34769 <field>
34770 <name>FB19</name>
34771 <description>Filter bits</description>
34772 <bitOffset>19</bitOffset>
34773 <bitWidth>1</bitWidth>
34774 </field>
34775 <field>
34776 <name>FB20</name>
34777 <description>Filter bits</description>
34778 <bitOffset>20</bitOffset>
34779 <bitWidth>1</bitWidth>
34780 </field>
34781 <field>
34782 <name>FB21</name>
34783 <description>Filter bits</description>
34784 <bitOffset>21</bitOffset>
34785 <bitWidth>1</bitWidth>
34786 </field>
34787 <field>
34788 <name>FB22</name>
34789 <description>Filter bits</description>
34790 <bitOffset>22</bitOffset>
34791 <bitWidth>1</bitWidth>
34792 </field>
34793 <field>
34794 <name>FB23</name>
34795 <description>Filter bits</description>
34796 <bitOffset>23</bitOffset>
34797 <bitWidth>1</bitWidth>
34798 </field>
34799 <field>
34800 <name>FB24</name>
34801 <description>Filter bits</description>
34802 <bitOffset>24</bitOffset>
34803 <bitWidth>1</bitWidth>
34804 </field>
34805 <field>
34806 <name>FB25</name>
34807 <description>Filter bits</description>
34808 <bitOffset>25</bitOffset>
34809 <bitWidth>1</bitWidth>
34810 </field>
34811 <field>
34812 <name>FB26</name>
34813 <description>Filter bits</description>
34814 <bitOffset>26</bitOffset>
34815 <bitWidth>1</bitWidth>
34816 </field>
34817 <field>
34818 <name>FB27</name>
34819 <description>Filter bits</description>
34820 <bitOffset>27</bitOffset>
34821 <bitWidth>1</bitWidth>
34822 </field>
34823 <field>
34824 <name>FB28</name>
34825 <description>Filter bits</description>
34826 <bitOffset>28</bitOffset>
34827 <bitWidth>1</bitWidth>
34828 </field>
34829 <field>
34830 <name>FB29</name>
34831 <description>Filter bits</description>
34832 <bitOffset>29</bitOffset>
34833 <bitWidth>1</bitWidth>
34834 </field>
34835 <field>
34836 <name>FB30</name>
34837 <description>Filter bits</description>
34838 <bitOffset>30</bitOffset>
34839 <bitWidth>1</bitWidth>
34840 </field>
34841 <field>
34842 <name>FB31</name>
34843 <description>Filter bits</description>
34844 <bitOffset>31</bitOffset>
34845 <bitWidth>1</bitWidth>
34846 </field>
34847 </fields>
34848 </register>
34849 <register>
34850 <name>F15R2</name>
34851 <displayName>F15R2</displayName>
34852 <description>Filter bank 15 register 2</description>
34853 <addressOffset>0x2BC</addressOffset>
34854 <size>0x20</size>
34855 <access>read-write</access>
34856 <resetValue>0x00000000</resetValue>
34857 <fields>
34858 <field>
34859 <name>FB0</name>
34860 <description>Filter bits</description>
34861 <bitOffset>0</bitOffset>
34862 <bitWidth>1</bitWidth>
34863 </field>
34864 <field>
34865 <name>FB1</name>
34866 <description>Filter bits</description>
34867 <bitOffset>1</bitOffset>
34868 <bitWidth>1</bitWidth>
34869 </field>
34870 <field>
34871 <name>FB2</name>
34872 <description>Filter bits</description>
34873 <bitOffset>2</bitOffset>
34874 <bitWidth>1</bitWidth>
34875 </field>
34876 <field>
34877 <name>FB3</name>
34878 <description>Filter bits</description>
34879 <bitOffset>3</bitOffset>
34880 <bitWidth>1</bitWidth>
34881 </field>
34882 <field>
34883 <name>FB4</name>
34884 <description>Filter bits</description>
34885 <bitOffset>4</bitOffset>
34886 <bitWidth>1</bitWidth>
34887 </field>
34888 <field>
34889 <name>FB5</name>
34890 <description>Filter bits</description>
34891 <bitOffset>5</bitOffset>
34892 <bitWidth>1</bitWidth>
34893 </field>
34894 <field>
34895 <name>FB6</name>
34896 <description>Filter bits</description>
34897 <bitOffset>6</bitOffset>
34898 <bitWidth>1</bitWidth>
34899 </field>
34900 <field>
34901 <name>FB7</name>
34902 <description>Filter bits</description>
34903 <bitOffset>7</bitOffset>
34904 <bitWidth>1</bitWidth>
34905 </field>
34906 <field>
34907 <name>FB8</name>
34908 <description>Filter bits</description>
34909 <bitOffset>8</bitOffset>
34910 <bitWidth>1</bitWidth>
34911 </field>
34912 <field>
34913 <name>FB9</name>
34914 <description>Filter bits</description>
34915 <bitOffset>9</bitOffset>
34916 <bitWidth>1</bitWidth>
34917 </field>
34918 <field>
34919 <name>FB10</name>
34920 <description>Filter bits</description>
34921 <bitOffset>10</bitOffset>
34922 <bitWidth>1</bitWidth>
34923 </field>
34924 <field>
34925 <name>FB11</name>
34926 <description>Filter bits</description>
34927 <bitOffset>11</bitOffset>
34928 <bitWidth>1</bitWidth>
34929 </field>
34930 <field>
34931 <name>FB12</name>
34932 <description>Filter bits</description>
34933 <bitOffset>12</bitOffset>
34934 <bitWidth>1</bitWidth>
34935 </field>
34936 <field>
34937 <name>FB13</name>
34938 <description>Filter bits</description>
34939 <bitOffset>13</bitOffset>
34940 <bitWidth>1</bitWidth>
34941 </field>
34942 <field>
34943 <name>FB14</name>
34944 <description>Filter bits</description>
34945 <bitOffset>14</bitOffset>
34946 <bitWidth>1</bitWidth>
34947 </field>
34948 <field>
34949 <name>FB15</name>
34950 <description>Filter bits</description>
34951 <bitOffset>15</bitOffset>
34952 <bitWidth>1</bitWidth>
34953 </field>
34954 <field>
34955 <name>FB16</name>
34956 <description>Filter bits</description>
34957 <bitOffset>16</bitOffset>
34958 <bitWidth>1</bitWidth>
34959 </field>
34960 <field>
34961 <name>FB17</name>
34962 <description>Filter bits</description>
34963 <bitOffset>17</bitOffset>
34964 <bitWidth>1</bitWidth>
34965 </field>
34966 <field>
34967 <name>FB18</name>
34968 <description>Filter bits</description>
34969 <bitOffset>18</bitOffset>
34970 <bitWidth>1</bitWidth>
34971 </field>
34972 <field>
34973 <name>FB19</name>
34974 <description>Filter bits</description>
34975 <bitOffset>19</bitOffset>
34976 <bitWidth>1</bitWidth>
34977 </field>
34978 <field>
34979 <name>FB20</name>
34980 <description>Filter bits</description>
34981 <bitOffset>20</bitOffset>
34982 <bitWidth>1</bitWidth>
34983 </field>
34984 <field>
34985 <name>FB21</name>
34986 <description>Filter bits</description>
34987 <bitOffset>21</bitOffset>
34988 <bitWidth>1</bitWidth>
34989 </field>
34990 <field>
34991 <name>FB22</name>
34992 <description>Filter bits</description>
34993 <bitOffset>22</bitOffset>
34994 <bitWidth>1</bitWidth>
34995 </field>
34996 <field>
34997 <name>FB23</name>
34998 <description>Filter bits</description>
34999 <bitOffset>23</bitOffset>
35000 <bitWidth>1</bitWidth>
35001 </field>
35002 <field>
35003 <name>FB24</name>
35004 <description>Filter bits</description>
35005 <bitOffset>24</bitOffset>
35006 <bitWidth>1</bitWidth>
35007 </field>
35008 <field>
35009 <name>FB25</name>
35010 <description>Filter bits</description>
35011 <bitOffset>25</bitOffset>
35012 <bitWidth>1</bitWidth>
35013 </field>
35014 <field>
35015 <name>FB26</name>
35016 <description>Filter bits</description>
35017 <bitOffset>26</bitOffset>
35018 <bitWidth>1</bitWidth>
35019 </field>
35020 <field>
35021 <name>FB27</name>
35022 <description>Filter bits</description>
35023 <bitOffset>27</bitOffset>
35024 <bitWidth>1</bitWidth>
35025 </field>
35026 <field>
35027 <name>FB28</name>
35028 <description>Filter bits</description>
35029 <bitOffset>28</bitOffset>
35030 <bitWidth>1</bitWidth>
35031 </field>
35032 <field>
35033 <name>FB29</name>
35034 <description>Filter bits</description>
35035 <bitOffset>29</bitOffset>
35036 <bitWidth>1</bitWidth>
35037 </field>
35038 <field>
35039 <name>FB30</name>
35040 <description>Filter bits</description>
35041 <bitOffset>30</bitOffset>
35042 <bitWidth>1</bitWidth>
35043 </field>
35044 <field>
35045 <name>FB31</name>
35046 <description>Filter bits</description>
35047 <bitOffset>31</bitOffset>
35048 <bitWidth>1</bitWidth>
35049 </field>
35050 </fields>
35051 </register>
35052 <register>
35053 <name>F16R1</name>
35054 <displayName>F16R1</displayName>
35055 <description>Filter bank 16 register 1</description>
35056 <addressOffset>0x2C0</addressOffset>
35057 <size>0x20</size>
35058 <access>read-write</access>
35059 <resetValue>0x00000000</resetValue>
35060 <fields>
35061 <field>
35062 <name>FB0</name>
35063 <description>Filter bits</description>
35064 <bitOffset>0</bitOffset>
35065 <bitWidth>1</bitWidth>
35066 </field>
35067 <field>
35068 <name>FB1</name>
35069 <description>Filter bits</description>
35070 <bitOffset>1</bitOffset>
35071 <bitWidth>1</bitWidth>
35072 </field>
35073 <field>
35074 <name>FB2</name>
35075 <description>Filter bits</description>
35076 <bitOffset>2</bitOffset>
35077 <bitWidth>1</bitWidth>
35078 </field>
35079 <field>
35080 <name>FB3</name>
35081 <description>Filter bits</description>
35082 <bitOffset>3</bitOffset>
35083 <bitWidth>1</bitWidth>
35084 </field>
35085 <field>
35086 <name>FB4</name>
35087 <description>Filter bits</description>
35088 <bitOffset>4</bitOffset>
35089 <bitWidth>1</bitWidth>
35090 </field>
35091 <field>
35092 <name>FB5</name>
35093 <description>Filter bits</description>
35094 <bitOffset>5</bitOffset>
35095 <bitWidth>1</bitWidth>
35096 </field>
35097 <field>
35098 <name>FB6</name>
35099 <description>Filter bits</description>
35100 <bitOffset>6</bitOffset>
35101 <bitWidth>1</bitWidth>
35102 </field>
35103 <field>
35104 <name>FB7</name>
35105 <description>Filter bits</description>
35106 <bitOffset>7</bitOffset>
35107 <bitWidth>1</bitWidth>
35108 </field>
35109 <field>
35110 <name>FB8</name>
35111 <description>Filter bits</description>
35112 <bitOffset>8</bitOffset>
35113 <bitWidth>1</bitWidth>
35114 </field>
35115 <field>
35116 <name>FB9</name>
35117 <description>Filter bits</description>
35118 <bitOffset>9</bitOffset>
35119 <bitWidth>1</bitWidth>
35120 </field>
35121 <field>
35122 <name>FB10</name>
35123 <description>Filter bits</description>
35124 <bitOffset>10</bitOffset>
35125 <bitWidth>1</bitWidth>
35126 </field>
35127 <field>
35128 <name>FB11</name>
35129 <description>Filter bits</description>
35130 <bitOffset>11</bitOffset>
35131 <bitWidth>1</bitWidth>
35132 </field>
35133 <field>
35134 <name>FB12</name>
35135 <description>Filter bits</description>
35136 <bitOffset>12</bitOffset>
35137 <bitWidth>1</bitWidth>
35138 </field>
35139 <field>
35140 <name>FB13</name>
35141 <description>Filter bits</description>
35142 <bitOffset>13</bitOffset>
35143 <bitWidth>1</bitWidth>
35144 </field>
35145 <field>
35146 <name>FB14</name>
35147 <description>Filter bits</description>
35148 <bitOffset>14</bitOffset>
35149 <bitWidth>1</bitWidth>
35150 </field>
35151 <field>
35152 <name>FB15</name>
35153 <description>Filter bits</description>
35154 <bitOffset>15</bitOffset>
35155 <bitWidth>1</bitWidth>
35156 </field>
35157 <field>
35158 <name>FB16</name>
35159 <description>Filter bits</description>
35160 <bitOffset>16</bitOffset>
35161 <bitWidth>1</bitWidth>
35162 </field>
35163 <field>
35164 <name>FB17</name>
35165 <description>Filter bits</description>
35166 <bitOffset>17</bitOffset>
35167 <bitWidth>1</bitWidth>
35168 </field>
35169 <field>
35170 <name>FB18</name>
35171 <description>Filter bits</description>
35172 <bitOffset>18</bitOffset>
35173 <bitWidth>1</bitWidth>
35174 </field>
35175 <field>
35176 <name>FB19</name>
35177 <description>Filter bits</description>
35178 <bitOffset>19</bitOffset>
35179 <bitWidth>1</bitWidth>
35180 </field>
35181 <field>
35182 <name>FB20</name>
35183 <description>Filter bits</description>
35184 <bitOffset>20</bitOffset>
35185 <bitWidth>1</bitWidth>
35186 </field>
35187 <field>
35188 <name>FB21</name>
35189 <description>Filter bits</description>
35190 <bitOffset>21</bitOffset>
35191 <bitWidth>1</bitWidth>
35192 </field>
35193 <field>
35194 <name>FB22</name>
35195 <description>Filter bits</description>
35196 <bitOffset>22</bitOffset>
35197 <bitWidth>1</bitWidth>
35198 </field>
35199 <field>
35200 <name>FB23</name>
35201 <description>Filter bits</description>
35202 <bitOffset>23</bitOffset>
35203 <bitWidth>1</bitWidth>
35204 </field>
35205 <field>
35206 <name>FB24</name>
35207 <description>Filter bits</description>
35208 <bitOffset>24</bitOffset>
35209 <bitWidth>1</bitWidth>
35210 </field>
35211 <field>
35212 <name>FB25</name>
35213 <description>Filter bits</description>
35214 <bitOffset>25</bitOffset>
35215 <bitWidth>1</bitWidth>
35216 </field>
35217 <field>
35218 <name>FB26</name>
35219 <description>Filter bits</description>
35220 <bitOffset>26</bitOffset>
35221 <bitWidth>1</bitWidth>
35222 </field>
35223 <field>
35224 <name>FB27</name>
35225 <description>Filter bits</description>
35226 <bitOffset>27</bitOffset>
35227 <bitWidth>1</bitWidth>
35228 </field>
35229 <field>
35230 <name>FB28</name>
35231 <description>Filter bits</description>
35232 <bitOffset>28</bitOffset>
35233 <bitWidth>1</bitWidth>
35234 </field>
35235 <field>
35236 <name>FB29</name>
35237 <description>Filter bits</description>
35238 <bitOffset>29</bitOffset>
35239 <bitWidth>1</bitWidth>
35240 </field>
35241 <field>
35242 <name>FB30</name>
35243 <description>Filter bits</description>
35244 <bitOffset>30</bitOffset>
35245 <bitWidth>1</bitWidth>
35246 </field>
35247 <field>
35248 <name>FB31</name>
35249 <description>Filter bits</description>
35250 <bitOffset>31</bitOffset>
35251 <bitWidth>1</bitWidth>
35252 </field>
35253 </fields>
35254 </register>
35255 <register>
35256 <name>F16R2</name>
35257 <displayName>F16R2</displayName>
35258 <description>Filter bank 16 register 2</description>
35259 <addressOffset>0x2C4</addressOffset>
35260 <size>0x20</size>
35261 <access>read-write</access>
35262 <resetValue>0x00000000</resetValue>
35263 <fields>
35264 <field>
35265 <name>FB0</name>
35266 <description>Filter bits</description>
35267 <bitOffset>0</bitOffset>
35268 <bitWidth>1</bitWidth>
35269 </field>
35270 <field>
35271 <name>FB1</name>
35272 <description>Filter bits</description>
35273 <bitOffset>1</bitOffset>
35274 <bitWidth>1</bitWidth>
35275 </field>
35276 <field>
35277 <name>FB2</name>
35278 <description>Filter bits</description>
35279 <bitOffset>2</bitOffset>
35280 <bitWidth>1</bitWidth>
35281 </field>
35282 <field>
35283 <name>FB3</name>
35284 <description>Filter bits</description>
35285 <bitOffset>3</bitOffset>
35286 <bitWidth>1</bitWidth>
35287 </field>
35288 <field>
35289 <name>FB4</name>
35290 <description>Filter bits</description>
35291 <bitOffset>4</bitOffset>
35292 <bitWidth>1</bitWidth>
35293 </field>
35294 <field>
35295 <name>FB5</name>
35296 <description>Filter bits</description>
35297 <bitOffset>5</bitOffset>
35298 <bitWidth>1</bitWidth>
35299 </field>
35300 <field>
35301 <name>FB6</name>
35302 <description>Filter bits</description>
35303 <bitOffset>6</bitOffset>
35304 <bitWidth>1</bitWidth>
35305 </field>
35306 <field>
35307 <name>FB7</name>
35308 <description>Filter bits</description>
35309 <bitOffset>7</bitOffset>
35310 <bitWidth>1</bitWidth>
35311 </field>
35312 <field>
35313 <name>FB8</name>
35314 <description>Filter bits</description>
35315 <bitOffset>8</bitOffset>
35316 <bitWidth>1</bitWidth>
35317 </field>
35318 <field>
35319 <name>FB9</name>
35320 <description>Filter bits</description>
35321 <bitOffset>9</bitOffset>
35322 <bitWidth>1</bitWidth>
35323 </field>
35324 <field>
35325 <name>FB10</name>
35326 <description>Filter bits</description>
35327 <bitOffset>10</bitOffset>
35328 <bitWidth>1</bitWidth>
35329 </field>
35330 <field>
35331 <name>FB11</name>
35332 <description>Filter bits</description>
35333 <bitOffset>11</bitOffset>
35334 <bitWidth>1</bitWidth>
35335 </field>
35336 <field>
35337 <name>FB12</name>
35338 <description>Filter bits</description>
35339 <bitOffset>12</bitOffset>
35340 <bitWidth>1</bitWidth>
35341 </field>
35342 <field>
35343 <name>FB13</name>
35344 <description>Filter bits</description>
35345 <bitOffset>13</bitOffset>
35346 <bitWidth>1</bitWidth>
35347 </field>
35348 <field>
35349 <name>FB14</name>
35350 <description>Filter bits</description>
35351 <bitOffset>14</bitOffset>
35352 <bitWidth>1</bitWidth>
35353 </field>
35354 <field>
35355 <name>FB15</name>
35356 <description>Filter bits</description>
35357 <bitOffset>15</bitOffset>
35358 <bitWidth>1</bitWidth>
35359 </field>
35360 <field>
35361 <name>FB16</name>
35362 <description>Filter bits</description>
35363 <bitOffset>16</bitOffset>
35364 <bitWidth>1</bitWidth>
35365 </field>
35366 <field>
35367 <name>FB17</name>
35368 <description>Filter bits</description>
35369 <bitOffset>17</bitOffset>
35370 <bitWidth>1</bitWidth>
35371 </field>
35372 <field>
35373 <name>FB18</name>
35374 <description>Filter bits</description>
35375 <bitOffset>18</bitOffset>
35376 <bitWidth>1</bitWidth>
35377 </field>
35378 <field>
35379 <name>FB19</name>
35380 <description>Filter bits</description>
35381 <bitOffset>19</bitOffset>
35382 <bitWidth>1</bitWidth>
35383 </field>
35384 <field>
35385 <name>FB20</name>
35386 <description>Filter bits</description>
35387 <bitOffset>20</bitOffset>
35388 <bitWidth>1</bitWidth>
35389 </field>
35390 <field>
35391 <name>FB21</name>
35392 <description>Filter bits</description>
35393 <bitOffset>21</bitOffset>
35394 <bitWidth>1</bitWidth>
35395 </field>
35396 <field>
35397 <name>FB22</name>
35398 <description>Filter bits</description>
35399 <bitOffset>22</bitOffset>
35400 <bitWidth>1</bitWidth>
35401 </field>
35402 <field>
35403 <name>FB23</name>
35404 <description>Filter bits</description>
35405 <bitOffset>23</bitOffset>
35406 <bitWidth>1</bitWidth>
35407 </field>
35408 <field>
35409 <name>FB24</name>
35410 <description>Filter bits</description>
35411 <bitOffset>24</bitOffset>
35412 <bitWidth>1</bitWidth>
35413 </field>
35414 <field>
35415 <name>FB25</name>
35416 <description>Filter bits</description>
35417 <bitOffset>25</bitOffset>
35418 <bitWidth>1</bitWidth>
35419 </field>
35420 <field>
35421 <name>FB26</name>
35422 <description>Filter bits</description>
35423 <bitOffset>26</bitOffset>
35424 <bitWidth>1</bitWidth>
35425 </field>
35426 <field>
35427 <name>FB27</name>
35428 <description>Filter bits</description>
35429 <bitOffset>27</bitOffset>
35430 <bitWidth>1</bitWidth>
35431 </field>
35432 <field>
35433 <name>FB28</name>
35434 <description>Filter bits</description>
35435 <bitOffset>28</bitOffset>
35436 <bitWidth>1</bitWidth>
35437 </field>
35438 <field>
35439 <name>FB29</name>
35440 <description>Filter bits</description>
35441 <bitOffset>29</bitOffset>
35442 <bitWidth>1</bitWidth>
35443 </field>
35444 <field>
35445 <name>FB30</name>
35446 <description>Filter bits</description>
35447 <bitOffset>30</bitOffset>
35448 <bitWidth>1</bitWidth>
35449 </field>
35450 <field>
35451 <name>FB31</name>
35452 <description>Filter bits</description>
35453 <bitOffset>31</bitOffset>
35454 <bitWidth>1</bitWidth>
35455 </field>
35456 </fields>
35457 </register>
35458 <register>
35459 <name>F17R1</name>
35460 <displayName>F17R1</displayName>
35461 <description>Filter bank 17 register 1</description>
35462 <addressOffset>0x2C8</addressOffset>
35463 <size>0x20</size>
35464 <access>read-write</access>
35465 <resetValue>0x00000000</resetValue>
35466 <fields>
35467 <field>
35468 <name>FB0</name>
35469 <description>Filter bits</description>
35470 <bitOffset>0</bitOffset>
35471 <bitWidth>1</bitWidth>
35472 </field>
35473 <field>
35474 <name>FB1</name>
35475 <description>Filter bits</description>
35476 <bitOffset>1</bitOffset>
35477 <bitWidth>1</bitWidth>
35478 </field>
35479 <field>
35480 <name>FB2</name>
35481 <description>Filter bits</description>
35482 <bitOffset>2</bitOffset>
35483 <bitWidth>1</bitWidth>
35484 </field>
35485 <field>
35486 <name>FB3</name>
35487 <description>Filter bits</description>
35488 <bitOffset>3</bitOffset>
35489 <bitWidth>1</bitWidth>
35490 </field>
35491 <field>
35492 <name>FB4</name>
35493 <description>Filter bits</description>
35494 <bitOffset>4</bitOffset>
35495 <bitWidth>1</bitWidth>
35496 </field>
35497 <field>
35498 <name>FB5</name>
35499 <description>Filter bits</description>
35500 <bitOffset>5</bitOffset>
35501 <bitWidth>1</bitWidth>
35502 </field>
35503 <field>
35504 <name>FB6</name>
35505 <description>Filter bits</description>
35506 <bitOffset>6</bitOffset>
35507 <bitWidth>1</bitWidth>
35508 </field>
35509 <field>
35510 <name>FB7</name>
35511 <description>Filter bits</description>
35512 <bitOffset>7</bitOffset>
35513 <bitWidth>1</bitWidth>
35514 </field>
35515 <field>
35516 <name>FB8</name>
35517 <description>Filter bits</description>
35518 <bitOffset>8</bitOffset>
35519 <bitWidth>1</bitWidth>
35520 </field>
35521 <field>
35522 <name>FB9</name>
35523 <description>Filter bits</description>
35524 <bitOffset>9</bitOffset>
35525 <bitWidth>1</bitWidth>
35526 </field>
35527 <field>
35528 <name>FB10</name>
35529 <description>Filter bits</description>
35530 <bitOffset>10</bitOffset>
35531 <bitWidth>1</bitWidth>
35532 </field>
35533 <field>
35534 <name>FB11</name>
35535 <description>Filter bits</description>
35536 <bitOffset>11</bitOffset>
35537 <bitWidth>1</bitWidth>
35538 </field>
35539 <field>
35540 <name>FB12</name>
35541 <description>Filter bits</description>
35542 <bitOffset>12</bitOffset>
35543 <bitWidth>1</bitWidth>
35544 </field>
35545 <field>
35546 <name>FB13</name>
35547 <description>Filter bits</description>
35548 <bitOffset>13</bitOffset>
35549 <bitWidth>1</bitWidth>
35550 </field>
35551 <field>
35552 <name>FB14</name>
35553 <description>Filter bits</description>
35554 <bitOffset>14</bitOffset>
35555 <bitWidth>1</bitWidth>
35556 </field>
35557 <field>
35558 <name>FB15</name>
35559 <description>Filter bits</description>
35560 <bitOffset>15</bitOffset>
35561 <bitWidth>1</bitWidth>
35562 </field>
35563 <field>
35564 <name>FB16</name>
35565 <description>Filter bits</description>
35566 <bitOffset>16</bitOffset>
35567 <bitWidth>1</bitWidth>
35568 </field>
35569 <field>
35570 <name>FB17</name>
35571 <description>Filter bits</description>
35572 <bitOffset>17</bitOffset>
35573 <bitWidth>1</bitWidth>
35574 </field>
35575 <field>
35576 <name>FB18</name>
35577 <description>Filter bits</description>
35578 <bitOffset>18</bitOffset>
35579 <bitWidth>1</bitWidth>
35580 </field>
35581 <field>
35582 <name>FB19</name>
35583 <description>Filter bits</description>
35584 <bitOffset>19</bitOffset>
35585 <bitWidth>1</bitWidth>
35586 </field>
35587 <field>
35588 <name>FB20</name>
35589 <description>Filter bits</description>
35590 <bitOffset>20</bitOffset>
35591 <bitWidth>1</bitWidth>
35592 </field>
35593 <field>
35594 <name>FB21</name>
35595 <description>Filter bits</description>
35596 <bitOffset>21</bitOffset>
35597 <bitWidth>1</bitWidth>
35598 </field>
35599 <field>
35600 <name>FB22</name>
35601 <description>Filter bits</description>
35602 <bitOffset>22</bitOffset>
35603 <bitWidth>1</bitWidth>
35604 </field>
35605 <field>
35606 <name>FB23</name>
35607 <description>Filter bits</description>
35608 <bitOffset>23</bitOffset>
35609 <bitWidth>1</bitWidth>
35610 </field>
35611 <field>
35612 <name>FB24</name>
35613 <description>Filter bits</description>
35614 <bitOffset>24</bitOffset>
35615 <bitWidth>1</bitWidth>
35616 </field>
35617 <field>
35618 <name>FB25</name>
35619 <description>Filter bits</description>
35620 <bitOffset>25</bitOffset>
35621 <bitWidth>1</bitWidth>
35622 </field>
35623 <field>
35624 <name>FB26</name>
35625 <description>Filter bits</description>
35626 <bitOffset>26</bitOffset>
35627 <bitWidth>1</bitWidth>
35628 </field>
35629 <field>
35630 <name>FB27</name>
35631 <description>Filter bits</description>
35632 <bitOffset>27</bitOffset>
35633 <bitWidth>1</bitWidth>
35634 </field>
35635 <field>
35636 <name>FB28</name>
35637 <description>Filter bits</description>
35638 <bitOffset>28</bitOffset>
35639 <bitWidth>1</bitWidth>
35640 </field>
35641 <field>
35642 <name>FB29</name>
35643 <description>Filter bits</description>
35644 <bitOffset>29</bitOffset>
35645 <bitWidth>1</bitWidth>
35646 </field>
35647 <field>
35648 <name>FB30</name>
35649 <description>Filter bits</description>
35650 <bitOffset>30</bitOffset>
35651 <bitWidth>1</bitWidth>
35652 </field>
35653 <field>
35654 <name>FB31</name>
35655 <description>Filter bits</description>
35656 <bitOffset>31</bitOffset>
35657 <bitWidth>1</bitWidth>
35658 </field>
35659 </fields>
35660 </register>
35661 <register>
35662 <name>F17R2</name>
35663 <displayName>F17R2</displayName>
35664 <description>Filter bank 17 register 2</description>
35665 <addressOffset>0x2CC</addressOffset>
35666 <size>0x20</size>
35667 <access>read-write</access>
35668 <resetValue>0x00000000</resetValue>
35669 <fields>
35670 <field>
35671 <name>FB0</name>
35672 <description>Filter bits</description>
35673 <bitOffset>0</bitOffset>
35674 <bitWidth>1</bitWidth>
35675 </field>
35676 <field>
35677 <name>FB1</name>
35678 <description>Filter bits</description>
35679 <bitOffset>1</bitOffset>
35680 <bitWidth>1</bitWidth>
35681 </field>
35682 <field>
35683 <name>FB2</name>
35684 <description>Filter bits</description>
35685 <bitOffset>2</bitOffset>
35686 <bitWidth>1</bitWidth>
35687 </field>
35688 <field>
35689 <name>FB3</name>
35690 <description>Filter bits</description>
35691 <bitOffset>3</bitOffset>
35692 <bitWidth>1</bitWidth>
35693 </field>
35694 <field>
35695 <name>FB4</name>
35696 <description>Filter bits</description>
35697 <bitOffset>4</bitOffset>
35698 <bitWidth>1</bitWidth>
35699 </field>
35700 <field>
35701 <name>FB5</name>
35702 <description>Filter bits</description>
35703 <bitOffset>5</bitOffset>
35704 <bitWidth>1</bitWidth>
35705 </field>
35706 <field>
35707 <name>FB6</name>
35708 <description>Filter bits</description>
35709 <bitOffset>6</bitOffset>
35710 <bitWidth>1</bitWidth>
35711 </field>
35712 <field>
35713 <name>FB7</name>
35714 <description>Filter bits</description>
35715 <bitOffset>7</bitOffset>
35716 <bitWidth>1</bitWidth>
35717 </field>
35718 <field>
35719 <name>FB8</name>
35720 <description>Filter bits</description>
35721 <bitOffset>8</bitOffset>
35722 <bitWidth>1</bitWidth>
35723 </field>
35724 <field>
35725 <name>FB9</name>
35726 <description>Filter bits</description>
35727 <bitOffset>9</bitOffset>
35728 <bitWidth>1</bitWidth>
35729 </field>
35730 <field>
35731 <name>FB10</name>
35732 <description>Filter bits</description>
35733 <bitOffset>10</bitOffset>
35734 <bitWidth>1</bitWidth>
35735 </field>
35736 <field>
35737 <name>FB11</name>
35738 <description>Filter bits</description>
35739 <bitOffset>11</bitOffset>
35740 <bitWidth>1</bitWidth>
35741 </field>
35742 <field>
35743 <name>FB12</name>
35744 <description>Filter bits</description>
35745 <bitOffset>12</bitOffset>
35746 <bitWidth>1</bitWidth>
35747 </field>
35748 <field>
35749 <name>FB13</name>
35750 <description>Filter bits</description>
35751 <bitOffset>13</bitOffset>
35752 <bitWidth>1</bitWidth>
35753 </field>
35754 <field>
35755 <name>FB14</name>
35756 <description>Filter bits</description>
35757 <bitOffset>14</bitOffset>
35758 <bitWidth>1</bitWidth>
35759 </field>
35760 <field>
35761 <name>FB15</name>
35762 <description>Filter bits</description>
35763 <bitOffset>15</bitOffset>
35764 <bitWidth>1</bitWidth>
35765 </field>
35766 <field>
35767 <name>FB16</name>
35768 <description>Filter bits</description>
35769 <bitOffset>16</bitOffset>
35770 <bitWidth>1</bitWidth>
35771 </field>
35772 <field>
35773 <name>FB17</name>
35774 <description>Filter bits</description>
35775 <bitOffset>17</bitOffset>
35776 <bitWidth>1</bitWidth>
35777 </field>
35778 <field>
35779 <name>FB18</name>
35780 <description>Filter bits</description>
35781 <bitOffset>18</bitOffset>
35782 <bitWidth>1</bitWidth>
35783 </field>
35784 <field>
35785 <name>FB19</name>
35786 <description>Filter bits</description>
35787 <bitOffset>19</bitOffset>
35788 <bitWidth>1</bitWidth>
35789 </field>
35790 <field>
35791 <name>FB20</name>
35792 <description>Filter bits</description>
35793 <bitOffset>20</bitOffset>
35794 <bitWidth>1</bitWidth>
35795 </field>
35796 <field>
35797 <name>FB21</name>
35798 <description>Filter bits</description>
35799 <bitOffset>21</bitOffset>
35800 <bitWidth>1</bitWidth>
35801 </field>
35802 <field>
35803 <name>FB22</name>
35804 <description>Filter bits</description>
35805 <bitOffset>22</bitOffset>
35806 <bitWidth>1</bitWidth>
35807 </field>
35808 <field>
35809 <name>FB23</name>
35810 <description>Filter bits</description>
35811 <bitOffset>23</bitOffset>
35812 <bitWidth>1</bitWidth>
35813 </field>
35814 <field>
35815 <name>FB24</name>
35816 <description>Filter bits</description>
35817 <bitOffset>24</bitOffset>
35818 <bitWidth>1</bitWidth>
35819 </field>
35820 <field>
35821 <name>FB25</name>
35822 <description>Filter bits</description>
35823 <bitOffset>25</bitOffset>
35824 <bitWidth>1</bitWidth>
35825 </field>
35826 <field>
35827 <name>FB26</name>
35828 <description>Filter bits</description>
35829 <bitOffset>26</bitOffset>
35830 <bitWidth>1</bitWidth>
35831 </field>
35832 <field>
35833 <name>FB27</name>
35834 <description>Filter bits</description>
35835 <bitOffset>27</bitOffset>
35836 <bitWidth>1</bitWidth>
35837 </field>
35838 <field>
35839 <name>FB28</name>
35840 <description>Filter bits</description>
35841 <bitOffset>28</bitOffset>
35842 <bitWidth>1</bitWidth>
35843 </field>
35844 <field>
35845 <name>FB29</name>
35846 <description>Filter bits</description>
35847 <bitOffset>29</bitOffset>
35848 <bitWidth>1</bitWidth>
35849 </field>
35850 <field>
35851 <name>FB30</name>
35852 <description>Filter bits</description>
35853 <bitOffset>30</bitOffset>
35854 <bitWidth>1</bitWidth>
35855 </field>
35856 <field>
35857 <name>FB31</name>
35858 <description>Filter bits</description>
35859 <bitOffset>31</bitOffset>
35860 <bitWidth>1</bitWidth>
35861 </field>
35862 </fields>
35863 </register>
35864 <register>
35865 <name>F18R1</name>
35866 <displayName>F18R1</displayName>
35867 <description>Filter bank 18 register 1</description>
35868 <addressOffset>0x2D0</addressOffset>
35869 <size>0x20</size>
35870 <access>read-write</access>
35871 <resetValue>0x00000000</resetValue>
35872 <fields>
35873 <field>
35874 <name>FB0</name>
35875 <description>Filter bits</description>
35876 <bitOffset>0</bitOffset>
35877 <bitWidth>1</bitWidth>
35878 </field>
35879 <field>
35880 <name>FB1</name>
35881 <description>Filter bits</description>
35882 <bitOffset>1</bitOffset>
35883 <bitWidth>1</bitWidth>
35884 </field>
35885 <field>
35886 <name>FB2</name>
35887 <description>Filter bits</description>
35888 <bitOffset>2</bitOffset>
35889 <bitWidth>1</bitWidth>
35890 </field>
35891 <field>
35892 <name>FB3</name>
35893 <description>Filter bits</description>
35894 <bitOffset>3</bitOffset>
35895 <bitWidth>1</bitWidth>
35896 </field>
35897 <field>
35898 <name>FB4</name>
35899 <description>Filter bits</description>
35900 <bitOffset>4</bitOffset>
35901 <bitWidth>1</bitWidth>
35902 </field>
35903 <field>
35904 <name>FB5</name>
35905 <description>Filter bits</description>
35906 <bitOffset>5</bitOffset>
35907 <bitWidth>1</bitWidth>
35908 </field>
35909 <field>
35910 <name>FB6</name>
35911 <description>Filter bits</description>
35912 <bitOffset>6</bitOffset>
35913 <bitWidth>1</bitWidth>
35914 </field>
35915 <field>
35916 <name>FB7</name>
35917 <description>Filter bits</description>
35918 <bitOffset>7</bitOffset>
35919 <bitWidth>1</bitWidth>
35920 </field>
35921 <field>
35922 <name>FB8</name>
35923 <description>Filter bits</description>
35924 <bitOffset>8</bitOffset>
35925 <bitWidth>1</bitWidth>
35926 </field>
35927 <field>
35928 <name>FB9</name>
35929 <description>Filter bits</description>
35930 <bitOffset>9</bitOffset>
35931 <bitWidth>1</bitWidth>
35932 </field>
35933 <field>
35934 <name>FB10</name>
35935 <description>Filter bits</description>
35936 <bitOffset>10</bitOffset>
35937 <bitWidth>1</bitWidth>
35938 </field>
35939 <field>
35940 <name>FB11</name>
35941 <description>Filter bits</description>
35942 <bitOffset>11</bitOffset>
35943 <bitWidth>1</bitWidth>
35944 </field>
35945 <field>
35946 <name>FB12</name>
35947 <description>Filter bits</description>
35948 <bitOffset>12</bitOffset>
35949 <bitWidth>1</bitWidth>
35950 </field>
35951 <field>
35952 <name>FB13</name>
35953 <description>Filter bits</description>
35954 <bitOffset>13</bitOffset>
35955 <bitWidth>1</bitWidth>
35956 </field>
35957 <field>
35958 <name>FB14</name>
35959 <description>Filter bits</description>
35960 <bitOffset>14</bitOffset>
35961 <bitWidth>1</bitWidth>
35962 </field>
35963 <field>
35964 <name>FB15</name>
35965 <description>Filter bits</description>
35966 <bitOffset>15</bitOffset>
35967 <bitWidth>1</bitWidth>
35968 </field>
35969 <field>
35970 <name>FB16</name>
35971 <description>Filter bits</description>
35972 <bitOffset>16</bitOffset>
35973 <bitWidth>1</bitWidth>
35974 </field>
35975 <field>
35976 <name>FB17</name>
35977 <description>Filter bits</description>
35978 <bitOffset>17</bitOffset>
35979 <bitWidth>1</bitWidth>
35980 </field>
35981 <field>
35982 <name>FB18</name>
35983 <description>Filter bits</description>
35984 <bitOffset>18</bitOffset>
35985 <bitWidth>1</bitWidth>
35986 </field>
35987 <field>
35988 <name>FB19</name>
35989 <description>Filter bits</description>
35990 <bitOffset>19</bitOffset>
35991 <bitWidth>1</bitWidth>
35992 </field>
35993 <field>
35994 <name>FB20</name>
35995 <description>Filter bits</description>
35996 <bitOffset>20</bitOffset>
35997 <bitWidth>1</bitWidth>
35998 </field>
35999 <field>
36000 <name>FB21</name>
36001 <description>Filter bits</description>
36002 <bitOffset>21</bitOffset>
36003 <bitWidth>1</bitWidth>
36004 </field>
36005 <field>
36006 <name>FB22</name>
36007 <description>Filter bits</description>
36008 <bitOffset>22</bitOffset>
36009 <bitWidth>1</bitWidth>
36010 </field>
36011 <field>
36012 <name>FB23</name>
36013 <description>Filter bits</description>
36014 <bitOffset>23</bitOffset>
36015 <bitWidth>1</bitWidth>
36016 </field>
36017 <field>
36018 <name>FB24</name>
36019 <description>Filter bits</description>
36020 <bitOffset>24</bitOffset>
36021 <bitWidth>1</bitWidth>
36022 </field>
36023 <field>
36024 <name>FB25</name>
36025 <description>Filter bits</description>
36026 <bitOffset>25</bitOffset>
36027 <bitWidth>1</bitWidth>
36028 </field>
36029 <field>
36030 <name>FB26</name>
36031 <description>Filter bits</description>
36032 <bitOffset>26</bitOffset>
36033 <bitWidth>1</bitWidth>
36034 </field>
36035 <field>
36036 <name>FB27</name>
36037 <description>Filter bits</description>
36038 <bitOffset>27</bitOffset>
36039 <bitWidth>1</bitWidth>
36040 </field>
36041 <field>
36042 <name>FB28</name>
36043 <description>Filter bits</description>
36044 <bitOffset>28</bitOffset>
36045 <bitWidth>1</bitWidth>
36046 </field>
36047 <field>
36048 <name>FB29</name>
36049 <description>Filter bits</description>
36050 <bitOffset>29</bitOffset>
36051 <bitWidth>1</bitWidth>
36052 </field>
36053 <field>
36054 <name>FB30</name>
36055 <description>Filter bits</description>
36056 <bitOffset>30</bitOffset>
36057 <bitWidth>1</bitWidth>
36058 </field>
36059 <field>
36060 <name>FB31</name>
36061 <description>Filter bits</description>
36062 <bitOffset>31</bitOffset>
36063 <bitWidth>1</bitWidth>
36064 </field>
36065 </fields>
36066 </register>
36067 <register>
36068 <name>F18R2</name>
36069 <displayName>F18R2</displayName>
36070 <description>Filter bank 18 register 2</description>
36071 <addressOffset>0x2D4</addressOffset>
36072 <size>0x20</size>
36073 <access>read-write</access>
36074 <resetValue>0x00000000</resetValue>
36075 <fields>
36076 <field>
36077 <name>FB0</name>
36078 <description>Filter bits</description>
36079 <bitOffset>0</bitOffset>
36080 <bitWidth>1</bitWidth>
36081 </field>
36082 <field>
36083 <name>FB1</name>
36084 <description>Filter bits</description>
36085 <bitOffset>1</bitOffset>
36086 <bitWidth>1</bitWidth>
36087 </field>
36088 <field>
36089 <name>FB2</name>
36090 <description>Filter bits</description>
36091 <bitOffset>2</bitOffset>
36092 <bitWidth>1</bitWidth>
36093 </field>
36094 <field>
36095 <name>FB3</name>
36096 <description>Filter bits</description>
36097 <bitOffset>3</bitOffset>
36098 <bitWidth>1</bitWidth>
36099 </field>
36100 <field>
36101 <name>FB4</name>
36102 <description>Filter bits</description>
36103 <bitOffset>4</bitOffset>
36104 <bitWidth>1</bitWidth>
36105 </field>
36106 <field>
36107 <name>FB5</name>
36108 <description>Filter bits</description>
36109 <bitOffset>5</bitOffset>
36110 <bitWidth>1</bitWidth>
36111 </field>
36112 <field>
36113 <name>FB6</name>
36114 <description>Filter bits</description>
36115 <bitOffset>6</bitOffset>
36116 <bitWidth>1</bitWidth>
36117 </field>
36118 <field>
36119 <name>FB7</name>
36120 <description>Filter bits</description>
36121 <bitOffset>7</bitOffset>
36122 <bitWidth>1</bitWidth>
36123 </field>
36124 <field>
36125 <name>FB8</name>
36126 <description>Filter bits</description>
36127 <bitOffset>8</bitOffset>
36128 <bitWidth>1</bitWidth>
36129 </field>
36130 <field>
36131 <name>FB9</name>
36132 <description>Filter bits</description>
36133 <bitOffset>9</bitOffset>
36134 <bitWidth>1</bitWidth>
36135 </field>
36136 <field>
36137 <name>FB10</name>
36138 <description>Filter bits</description>
36139 <bitOffset>10</bitOffset>
36140 <bitWidth>1</bitWidth>
36141 </field>
36142 <field>
36143 <name>FB11</name>
36144 <description>Filter bits</description>
36145 <bitOffset>11</bitOffset>
36146 <bitWidth>1</bitWidth>
36147 </field>
36148 <field>
36149 <name>FB12</name>
36150 <description>Filter bits</description>
36151 <bitOffset>12</bitOffset>
36152 <bitWidth>1</bitWidth>
36153 </field>
36154 <field>
36155 <name>FB13</name>
36156 <description>Filter bits</description>
36157 <bitOffset>13</bitOffset>
36158 <bitWidth>1</bitWidth>
36159 </field>
36160 <field>
36161 <name>FB14</name>
36162 <description>Filter bits</description>
36163 <bitOffset>14</bitOffset>
36164 <bitWidth>1</bitWidth>
36165 </field>
36166 <field>
36167 <name>FB15</name>
36168 <description>Filter bits</description>
36169 <bitOffset>15</bitOffset>
36170 <bitWidth>1</bitWidth>
36171 </field>
36172 <field>
36173 <name>FB16</name>
36174 <description>Filter bits</description>
36175 <bitOffset>16</bitOffset>
36176 <bitWidth>1</bitWidth>
36177 </field>
36178 <field>
36179 <name>FB17</name>
36180 <description>Filter bits</description>
36181 <bitOffset>17</bitOffset>
36182 <bitWidth>1</bitWidth>
36183 </field>
36184 <field>
36185 <name>FB18</name>
36186 <description>Filter bits</description>
36187 <bitOffset>18</bitOffset>
36188 <bitWidth>1</bitWidth>
36189 </field>
36190 <field>
36191 <name>FB19</name>
36192 <description>Filter bits</description>
36193 <bitOffset>19</bitOffset>
36194 <bitWidth>1</bitWidth>
36195 </field>
36196 <field>
36197 <name>FB20</name>
36198 <description>Filter bits</description>
36199 <bitOffset>20</bitOffset>
36200 <bitWidth>1</bitWidth>
36201 </field>
36202 <field>
36203 <name>FB21</name>
36204 <description>Filter bits</description>
36205 <bitOffset>21</bitOffset>
36206 <bitWidth>1</bitWidth>
36207 </field>
36208 <field>
36209 <name>FB22</name>
36210 <description>Filter bits</description>
36211 <bitOffset>22</bitOffset>
36212 <bitWidth>1</bitWidth>
36213 </field>
36214 <field>
36215 <name>FB23</name>
36216 <description>Filter bits</description>
36217 <bitOffset>23</bitOffset>
36218 <bitWidth>1</bitWidth>
36219 </field>
36220 <field>
36221 <name>FB24</name>
36222 <description>Filter bits</description>
36223 <bitOffset>24</bitOffset>
36224 <bitWidth>1</bitWidth>
36225 </field>
36226 <field>
36227 <name>FB25</name>
36228 <description>Filter bits</description>
36229 <bitOffset>25</bitOffset>
36230 <bitWidth>1</bitWidth>
36231 </field>
36232 <field>
36233 <name>FB26</name>
36234 <description>Filter bits</description>
36235 <bitOffset>26</bitOffset>
36236 <bitWidth>1</bitWidth>
36237 </field>
36238 <field>
36239 <name>FB27</name>
36240 <description>Filter bits</description>
36241 <bitOffset>27</bitOffset>
36242 <bitWidth>1</bitWidth>
36243 </field>
36244 <field>
36245 <name>FB28</name>
36246 <description>Filter bits</description>
36247 <bitOffset>28</bitOffset>
36248 <bitWidth>1</bitWidth>
36249 </field>
36250 <field>
36251 <name>FB29</name>
36252 <description>Filter bits</description>
36253 <bitOffset>29</bitOffset>
36254 <bitWidth>1</bitWidth>
36255 </field>
36256 <field>
36257 <name>FB30</name>
36258 <description>Filter bits</description>
36259 <bitOffset>30</bitOffset>
36260 <bitWidth>1</bitWidth>
36261 </field>
36262 <field>
36263 <name>FB31</name>
36264 <description>Filter bits</description>
36265 <bitOffset>31</bitOffset>
36266 <bitWidth>1</bitWidth>
36267 </field>
36268 </fields>
36269 </register>
36270 <register>
36271 <name>F19R1</name>
36272 <displayName>F19R1</displayName>
36273 <description>Filter bank 19 register 1</description>
36274 <addressOffset>0x2D8</addressOffset>
36275 <size>0x20</size>
36276 <access>read-write</access>
36277 <resetValue>0x00000000</resetValue>
36278 <fields>
36279 <field>
36280 <name>FB0</name>
36281 <description>Filter bits</description>
36282 <bitOffset>0</bitOffset>
36283 <bitWidth>1</bitWidth>
36284 </field>
36285 <field>
36286 <name>FB1</name>
36287 <description>Filter bits</description>
36288 <bitOffset>1</bitOffset>
36289 <bitWidth>1</bitWidth>
36290 </field>
36291 <field>
36292 <name>FB2</name>
36293 <description>Filter bits</description>
36294 <bitOffset>2</bitOffset>
36295 <bitWidth>1</bitWidth>
36296 </field>
36297 <field>
36298 <name>FB3</name>
36299 <description>Filter bits</description>
36300 <bitOffset>3</bitOffset>
36301 <bitWidth>1</bitWidth>
36302 </field>
36303 <field>
36304 <name>FB4</name>
36305 <description>Filter bits</description>
36306 <bitOffset>4</bitOffset>
36307 <bitWidth>1</bitWidth>
36308 </field>
36309 <field>
36310 <name>FB5</name>
36311 <description>Filter bits</description>
36312 <bitOffset>5</bitOffset>
36313 <bitWidth>1</bitWidth>
36314 </field>
36315 <field>
36316 <name>FB6</name>
36317 <description>Filter bits</description>
36318 <bitOffset>6</bitOffset>
36319 <bitWidth>1</bitWidth>
36320 </field>
36321 <field>
36322 <name>FB7</name>
36323 <description>Filter bits</description>
36324 <bitOffset>7</bitOffset>
36325 <bitWidth>1</bitWidth>
36326 </field>
36327 <field>
36328 <name>FB8</name>
36329 <description>Filter bits</description>
36330 <bitOffset>8</bitOffset>
36331 <bitWidth>1</bitWidth>
36332 </field>
36333 <field>
36334 <name>FB9</name>
36335 <description>Filter bits</description>
36336 <bitOffset>9</bitOffset>
36337 <bitWidth>1</bitWidth>
36338 </field>
36339 <field>
36340 <name>FB10</name>
36341 <description>Filter bits</description>
36342 <bitOffset>10</bitOffset>
36343 <bitWidth>1</bitWidth>
36344 </field>
36345 <field>
36346 <name>FB11</name>
36347 <description>Filter bits</description>
36348 <bitOffset>11</bitOffset>
36349 <bitWidth>1</bitWidth>
36350 </field>
36351 <field>
36352 <name>FB12</name>
36353 <description>Filter bits</description>
36354 <bitOffset>12</bitOffset>
36355 <bitWidth>1</bitWidth>
36356 </field>
36357 <field>
36358 <name>FB13</name>
36359 <description>Filter bits</description>
36360 <bitOffset>13</bitOffset>
36361 <bitWidth>1</bitWidth>
36362 </field>
36363 <field>
36364 <name>FB14</name>
36365 <description>Filter bits</description>
36366 <bitOffset>14</bitOffset>
36367 <bitWidth>1</bitWidth>
36368 </field>
36369 <field>
36370 <name>FB15</name>
36371 <description>Filter bits</description>
36372 <bitOffset>15</bitOffset>
36373 <bitWidth>1</bitWidth>
36374 </field>
36375 <field>
36376 <name>FB16</name>
36377 <description>Filter bits</description>
36378 <bitOffset>16</bitOffset>
36379 <bitWidth>1</bitWidth>
36380 </field>
36381 <field>
36382 <name>FB17</name>
36383 <description>Filter bits</description>
36384 <bitOffset>17</bitOffset>
36385 <bitWidth>1</bitWidth>
36386 </field>
36387 <field>
36388 <name>FB18</name>
36389 <description>Filter bits</description>
36390 <bitOffset>18</bitOffset>
36391 <bitWidth>1</bitWidth>
36392 </field>
36393 <field>
36394 <name>FB19</name>
36395 <description>Filter bits</description>
36396 <bitOffset>19</bitOffset>
36397 <bitWidth>1</bitWidth>
36398 </field>
36399 <field>
36400 <name>FB20</name>
36401 <description>Filter bits</description>
36402 <bitOffset>20</bitOffset>
36403 <bitWidth>1</bitWidth>
36404 </field>
36405 <field>
36406 <name>FB21</name>
36407 <description>Filter bits</description>
36408 <bitOffset>21</bitOffset>
36409 <bitWidth>1</bitWidth>
36410 </field>
36411 <field>
36412 <name>FB22</name>
36413 <description>Filter bits</description>
36414 <bitOffset>22</bitOffset>
36415 <bitWidth>1</bitWidth>
36416 </field>
36417 <field>
36418 <name>FB23</name>
36419 <description>Filter bits</description>
36420 <bitOffset>23</bitOffset>
36421 <bitWidth>1</bitWidth>
36422 </field>
36423 <field>
36424 <name>FB24</name>
36425 <description>Filter bits</description>
36426 <bitOffset>24</bitOffset>
36427 <bitWidth>1</bitWidth>
36428 </field>
36429 <field>
36430 <name>FB25</name>
36431 <description>Filter bits</description>
36432 <bitOffset>25</bitOffset>
36433 <bitWidth>1</bitWidth>
36434 </field>
36435 <field>
36436 <name>FB26</name>
36437 <description>Filter bits</description>
36438 <bitOffset>26</bitOffset>
36439 <bitWidth>1</bitWidth>
36440 </field>
36441 <field>
36442 <name>FB27</name>
36443 <description>Filter bits</description>
36444 <bitOffset>27</bitOffset>
36445 <bitWidth>1</bitWidth>
36446 </field>
36447 <field>
36448 <name>FB28</name>
36449 <description>Filter bits</description>
36450 <bitOffset>28</bitOffset>
36451 <bitWidth>1</bitWidth>
36452 </field>
36453 <field>
36454 <name>FB29</name>
36455 <description>Filter bits</description>
36456 <bitOffset>29</bitOffset>
36457 <bitWidth>1</bitWidth>
36458 </field>
36459 <field>
36460 <name>FB30</name>
36461 <description>Filter bits</description>
36462 <bitOffset>30</bitOffset>
36463 <bitWidth>1</bitWidth>
36464 </field>
36465 <field>
36466 <name>FB31</name>
36467 <description>Filter bits</description>
36468 <bitOffset>31</bitOffset>
36469 <bitWidth>1</bitWidth>
36470 </field>
36471 </fields>
36472 </register>
36473 <register>
36474 <name>F19R2</name>
36475 <displayName>F19R2</displayName>
36476 <description>Filter bank 19 register 2</description>
36477 <addressOffset>0x2DC</addressOffset>
36478 <size>0x20</size>
36479 <access>read-write</access>
36480 <resetValue>0x00000000</resetValue>
36481 <fields>
36482 <field>
36483 <name>FB0</name>
36484 <description>Filter bits</description>
36485 <bitOffset>0</bitOffset>
36486 <bitWidth>1</bitWidth>
36487 </field>
36488 <field>
36489 <name>FB1</name>
36490 <description>Filter bits</description>
36491 <bitOffset>1</bitOffset>
36492 <bitWidth>1</bitWidth>
36493 </field>
36494 <field>
36495 <name>FB2</name>
36496 <description>Filter bits</description>
36497 <bitOffset>2</bitOffset>
36498 <bitWidth>1</bitWidth>
36499 </field>
36500 <field>
36501 <name>FB3</name>
36502 <description>Filter bits</description>
36503 <bitOffset>3</bitOffset>
36504 <bitWidth>1</bitWidth>
36505 </field>
36506 <field>
36507 <name>FB4</name>
36508 <description>Filter bits</description>
36509 <bitOffset>4</bitOffset>
36510 <bitWidth>1</bitWidth>
36511 </field>
36512 <field>
36513 <name>FB5</name>
36514 <description>Filter bits</description>
36515 <bitOffset>5</bitOffset>
36516 <bitWidth>1</bitWidth>
36517 </field>
36518 <field>
36519 <name>FB6</name>
36520 <description>Filter bits</description>
36521 <bitOffset>6</bitOffset>
36522 <bitWidth>1</bitWidth>
36523 </field>
36524 <field>
36525 <name>FB7</name>
36526 <description>Filter bits</description>
36527 <bitOffset>7</bitOffset>
36528 <bitWidth>1</bitWidth>
36529 </field>
36530 <field>
36531 <name>FB8</name>
36532 <description>Filter bits</description>
36533 <bitOffset>8</bitOffset>
36534 <bitWidth>1</bitWidth>
36535 </field>
36536 <field>
36537 <name>FB9</name>
36538 <description>Filter bits</description>
36539 <bitOffset>9</bitOffset>
36540 <bitWidth>1</bitWidth>
36541 </field>
36542 <field>
36543 <name>FB10</name>
36544 <description>Filter bits</description>
36545 <bitOffset>10</bitOffset>
36546 <bitWidth>1</bitWidth>
36547 </field>
36548 <field>
36549 <name>FB11</name>
36550 <description>Filter bits</description>
36551 <bitOffset>11</bitOffset>
36552 <bitWidth>1</bitWidth>
36553 </field>
36554 <field>
36555 <name>FB12</name>
36556 <description>Filter bits</description>
36557 <bitOffset>12</bitOffset>
36558 <bitWidth>1</bitWidth>
36559 </field>
36560 <field>
36561 <name>FB13</name>
36562 <description>Filter bits</description>
36563 <bitOffset>13</bitOffset>
36564 <bitWidth>1</bitWidth>
36565 </field>
36566 <field>
36567 <name>FB14</name>
36568 <description>Filter bits</description>
36569 <bitOffset>14</bitOffset>
36570 <bitWidth>1</bitWidth>
36571 </field>
36572 <field>
36573 <name>FB15</name>
36574 <description>Filter bits</description>
36575 <bitOffset>15</bitOffset>
36576 <bitWidth>1</bitWidth>
36577 </field>
36578 <field>
36579 <name>FB16</name>
36580 <description>Filter bits</description>
36581 <bitOffset>16</bitOffset>
36582 <bitWidth>1</bitWidth>
36583 </field>
36584 <field>
36585 <name>FB17</name>
36586 <description>Filter bits</description>
36587 <bitOffset>17</bitOffset>
36588 <bitWidth>1</bitWidth>
36589 </field>
36590 <field>
36591 <name>FB18</name>
36592 <description>Filter bits</description>
36593 <bitOffset>18</bitOffset>
36594 <bitWidth>1</bitWidth>
36595 </field>
36596 <field>
36597 <name>FB19</name>
36598 <description>Filter bits</description>
36599 <bitOffset>19</bitOffset>
36600 <bitWidth>1</bitWidth>
36601 </field>
36602 <field>
36603 <name>FB20</name>
36604 <description>Filter bits</description>
36605 <bitOffset>20</bitOffset>
36606 <bitWidth>1</bitWidth>
36607 </field>
36608 <field>
36609 <name>FB21</name>
36610 <description>Filter bits</description>
36611 <bitOffset>21</bitOffset>
36612 <bitWidth>1</bitWidth>
36613 </field>
36614 <field>
36615 <name>FB22</name>
36616 <description>Filter bits</description>
36617 <bitOffset>22</bitOffset>
36618 <bitWidth>1</bitWidth>
36619 </field>
36620 <field>
36621 <name>FB23</name>
36622 <description>Filter bits</description>
36623 <bitOffset>23</bitOffset>
36624 <bitWidth>1</bitWidth>
36625 </field>
36626 <field>
36627 <name>FB24</name>
36628 <description>Filter bits</description>
36629 <bitOffset>24</bitOffset>
36630 <bitWidth>1</bitWidth>
36631 </field>
36632 <field>
36633 <name>FB25</name>
36634 <description>Filter bits</description>
36635 <bitOffset>25</bitOffset>
36636 <bitWidth>1</bitWidth>
36637 </field>
36638 <field>
36639 <name>FB26</name>
36640 <description>Filter bits</description>
36641 <bitOffset>26</bitOffset>
36642 <bitWidth>1</bitWidth>
36643 </field>
36644 <field>
36645 <name>FB27</name>
36646 <description>Filter bits</description>
36647 <bitOffset>27</bitOffset>
36648 <bitWidth>1</bitWidth>
36649 </field>
36650 <field>
36651 <name>FB28</name>
36652 <description>Filter bits</description>
36653 <bitOffset>28</bitOffset>
36654 <bitWidth>1</bitWidth>
36655 </field>
36656 <field>
36657 <name>FB29</name>
36658 <description>Filter bits</description>
36659 <bitOffset>29</bitOffset>
36660 <bitWidth>1</bitWidth>
36661 </field>
36662 <field>
36663 <name>FB30</name>
36664 <description>Filter bits</description>
36665 <bitOffset>30</bitOffset>
36666 <bitWidth>1</bitWidth>
36667 </field>
36668 <field>
36669 <name>FB31</name>
36670 <description>Filter bits</description>
36671 <bitOffset>31</bitOffset>
36672 <bitWidth>1</bitWidth>
36673 </field>
36674 </fields>
36675 </register>
36676 <register>
36677 <name>F20R1</name>
36678 <displayName>F20R1</displayName>
36679 <description>Filter bank 20 register 1</description>
36680 <addressOffset>0x2E0</addressOffset>
36681 <size>0x20</size>
36682 <access>read-write</access>
36683 <resetValue>0x00000000</resetValue>
36684 <fields>
36685 <field>
36686 <name>FB0</name>
36687 <description>Filter bits</description>
36688 <bitOffset>0</bitOffset>
36689 <bitWidth>1</bitWidth>
36690 </field>
36691 <field>
36692 <name>FB1</name>
36693 <description>Filter bits</description>
36694 <bitOffset>1</bitOffset>
36695 <bitWidth>1</bitWidth>
36696 </field>
36697 <field>
36698 <name>FB2</name>
36699 <description>Filter bits</description>
36700 <bitOffset>2</bitOffset>
36701 <bitWidth>1</bitWidth>
36702 </field>
36703 <field>
36704 <name>FB3</name>
36705 <description>Filter bits</description>
36706 <bitOffset>3</bitOffset>
36707 <bitWidth>1</bitWidth>
36708 </field>
36709 <field>
36710 <name>FB4</name>
36711 <description>Filter bits</description>
36712 <bitOffset>4</bitOffset>
36713 <bitWidth>1</bitWidth>
36714 </field>
36715 <field>
36716 <name>FB5</name>
36717 <description>Filter bits</description>
36718 <bitOffset>5</bitOffset>
36719 <bitWidth>1</bitWidth>
36720 </field>
36721 <field>
36722 <name>FB6</name>
36723 <description>Filter bits</description>
36724 <bitOffset>6</bitOffset>
36725 <bitWidth>1</bitWidth>
36726 </field>
36727 <field>
36728 <name>FB7</name>
36729 <description>Filter bits</description>
36730 <bitOffset>7</bitOffset>
36731 <bitWidth>1</bitWidth>
36732 </field>
36733 <field>
36734 <name>FB8</name>
36735 <description>Filter bits</description>
36736 <bitOffset>8</bitOffset>
36737 <bitWidth>1</bitWidth>
36738 </field>
36739 <field>
36740 <name>FB9</name>
36741 <description>Filter bits</description>
36742 <bitOffset>9</bitOffset>
36743 <bitWidth>1</bitWidth>
36744 </field>
36745 <field>
36746 <name>FB10</name>
36747 <description>Filter bits</description>
36748 <bitOffset>10</bitOffset>
36749 <bitWidth>1</bitWidth>
36750 </field>
36751 <field>
36752 <name>FB11</name>
36753 <description>Filter bits</description>
36754 <bitOffset>11</bitOffset>
36755 <bitWidth>1</bitWidth>
36756 </field>
36757 <field>
36758 <name>FB12</name>
36759 <description>Filter bits</description>
36760 <bitOffset>12</bitOffset>
36761 <bitWidth>1</bitWidth>
36762 </field>
36763 <field>
36764 <name>FB13</name>
36765 <description>Filter bits</description>
36766 <bitOffset>13</bitOffset>
36767 <bitWidth>1</bitWidth>
36768 </field>
36769 <field>
36770 <name>FB14</name>
36771 <description>Filter bits</description>
36772 <bitOffset>14</bitOffset>
36773 <bitWidth>1</bitWidth>
36774 </field>
36775 <field>
36776 <name>FB15</name>
36777 <description>Filter bits</description>
36778 <bitOffset>15</bitOffset>
36779 <bitWidth>1</bitWidth>
36780 </field>
36781 <field>
36782 <name>FB16</name>
36783 <description>Filter bits</description>
36784 <bitOffset>16</bitOffset>
36785 <bitWidth>1</bitWidth>
36786 </field>
36787 <field>
36788 <name>FB17</name>
36789 <description>Filter bits</description>
36790 <bitOffset>17</bitOffset>
36791 <bitWidth>1</bitWidth>
36792 </field>
36793 <field>
36794 <name>FB18</name>
36795 <description>Filter bits</description>
36796 <bitOffset>18</bitOffset>
36797 <bitWidth>1</bitWidth>
36798 </field>
36799 <field>
36800 <name>FB19</name>
36801 <description>Filter bits</description>
36802 <bitOffset>19</bitOffset>
36803 <bitWidth>1</bitWidth>
36804 </field>
36805 <field>
36806 <name>FB20</name>
36807 <description>Filter bits</description>
36808 <bitOffset>20</bitOffset>
36809 <bitWidth>1</bitWidth>
36810 </field>
36811 <field>
36812 <name>FB21</name>
36813 <description>Filter bits</description>
36814 <bitOffset>21</bitOffset>
36815 <bitWidth>1</bitWidth>
36816 </field>
36817 <field>
36818 <name>FB22</name>
36819 <description>Filter bits</description>
36820 <bitOffset>22</bitOffset>
36821 <bitWidth>1</bitWidth>
36822 </field>
36823 <field>
36824 <name>FB23</name>
36825 <description>Filter bits</description>
36826 <bitOffset>23</bitOffset>
36827 <bitWidth>1</bitWidth>
36828 </field>
36829 <field>
36830 <name>FB24</name>
36831 <description>Filter bits</description>
36832 <bitOffset>24</bitOffset>
36833 <bitWidth>1</bitWidth>
36834 </field>
36835 <field>
36836 <name>FB25</name>
36837 <description>Filter bits</description>
36838 <bitOffset>25</bitOffset>
36839 <bitWidth>1</bitWidth>
36840 </field>
36841 <field>
36842 <name>FB26</name>
36843 <description>Filter bits</description>
36844 <bitOffset>26</bitOffset>
36845 <bitWidth>1</bitWidth>
36846 </field>
36847 <field>
36848 <name>FB27</name>
36849 <description>Filter bits</description>
36850 <bitOffset>27</bitOffset>
36851 <bitWidth>1</bitWidth>
36852 </field>
36853 <field>
36854 <name>FB28</name>
36855 <description>Filter bits</description>
36856 <bitOffset>28</bitOffset>
36857 <bitWidth>1</bitWidth>
36858 </field>
36859 <field>
36860 <name>FB29</name>
36861 <description>Filter bits</description>
36862 <bitOffset>29</bitOffset>
36863 <bitWidth>1</bitWidth>
36864 </field>
36865 <field>
36866 <name>FB30</name>
36867 <description>Filter bits</description>
36868 <bitOffset>30</bitOffset>
36869 <bitWidth>1</bitWidth>
36870 </field>
36871 <field>
36872 <name>FB31</name>
36873 <description>Filter bits</description>
36874 <bitOffset>31</bitOffset>
36875 <bitWidth>1</bitWidth>
36876 </field>
36877 </fields>
36878 </register>
36879 <register>
36880 <name>F20R2</name>
36881 <displayName>F20R2</displayName>
36882 <description>Filter bank 20 register 2</description>
36883 <addressOffset>0x2E4</addressOffset>
36884 <size>0x20</size>
36885 <access>read-write</access>
36886 <resetValue>0x00000000</resetValue>
36887 <fields>
36888 <field>
36889 <name>FB0</name>
36890 <description>Filter bits</description>
36891 <bitOffset>0</bitOffset>
36892 <bitWidth>1</bitWidth>
36893 </field>
36894 <field>
36895 <name>FB1</name>
36896 <description>Filter bits</description>
36897 <bitOffset>1</bitOffset>
36898 <bitWidth>1</bitWidth>
36899 </field>
36900 <field>
36901 <name>FB2</name>
36902 <description>Filter bits</description>
36903 <bitOffset>2</bitOffset>
36904 <bitWidth>1</bitWidth>
36905 </field>
36906 <field>
36907 <name>FB3</name>
36908 <description>Filter bits</description>
36909 <bitOffset>3</bitOffset>
36910 <bitWidth>1</bitWidth>
36911 </field>
36912 <field>
36913 <name>FB4</name>
36914 <description>Filter bits</description>
36915 <bitOffset>4</bitOffset>
36916 <bitWidth>1</bitWidth>
36917 </field>
36918 <field>
36919 <name>FB5</name>
36920 <description>Filter bits</description>
36921 <bitOffset>5</bitOffset>
36922 <bitWidth>1</bitWidth>
36923 </field>
36924 <field>
36925 <name>FB6</name>
36926 <description>Filter bits</description>
36927 <bitOffset>6</bitOffset>
36928 <bitWidth>1</bitWidth>
36929 </field>
36930 <field>
36931 <name>FB7</name>
36932 <description>Filter bits</description>
36933 <bitOffset>7</bitOffset>
36934 <bitWidth>1</bitWidth>
36935 </field>
36936 <field>
36937 <name>FB8</name>
36938 <description>Filter bits</description>
36939 <bitOffset>8</bitOffset>
36940 <bitWidth>1</bitWidth>
36941 </field>
36942 <field>
36943 <name>FB9</name>
36944 <description>Filter bits</description>
36945 <bitOffset>9</bitOffset>
36946 <bitWidth>1</bitWidth>
36947 </field>
36948 <field>
36949 <name>FB10</name>
36950 <description>Filter bits</description>
36951 <bitOffset>10</bitOffset>
36952 <bitWidth>1</bitWidth>
36953 </field>
36954 <field>
36955 <name>FB11</name>
36956 <description>Filter bits</description>
36957 <bitOffset>11</bitOffset>
36958 <bitWidth>1</bitWidth>
36959 </field>
36960 <field>
36961 <name>FB12</name>
36962 <description>Filter bits</description>
36963 <bitOffset>12</bitOffset>
36964 <bitWidth>1</bitWidth>
36965 </field>
36966 <field>
36967 <name>FB13</name>
36968 <description>Filter bits</description>
36969 <bitOffset>13</bitOffset>
36970 <bitWidth>1</bitWidth>
36971 </field>
36972 <field>
36973 <name>FB14</name>
36974 <description>Filter bits</description>
36975 <bitOffset>14</bitOffset>
36976 <bitWidth>1</bitWidth>
36977 </field>
36978 <field>
36979 <name>FB15</name>
36980 <description>Filter bits</description>
36981 <bitOffset>15</bitOffset>
36982 <bitWidth>1</bitWidth>
36983 </field>
36984 <field>
36985 <name>FB16</name>
36986 <description>Filter bits</description>
36987 <bitOffset>16</bitOffset>
36988 <bitWidth>1</bitWidth>
36989 </field>
36990 <field>
36991 <name>FB17</name>
36992 <description>Filter bits</description>
36993 <bitOffset>17</bitOffset>
36994 <bitWidth>1</bitWidth>
36995 </field>
36996 <field>
36997 <name>FB18</name>
36998 <description>Filter bits</description>
36999 <bitOffset>18</bitOffset>
37000 <bitWidth>1</bitWidth>
37001 </field>
37002 <field>
37003 <name>FB19</name>
37004 <description>Filter bits</description>
37005 <bitOffset>19</bitOffset>
37006 <bitWidth>1</bitWidth>
37007 </field>
37008 <field>
37009 <name>FB20</name>
37010 <description>Filter bits</description>
37011 <bitOffset>20</bitOffset>
37012 <bitWidth>1</bitWidth>
37013 </field>
37014 <field>
37015 <name>FB21</name>
37016 <description>Filter bits</description>
37017 <bitOffset>21</bitOffset>
37018 <bitWidth>1</bitWidth>
37019 </field>
37020 <field>
37021 <name>FB22</name>
37022 <description>Filter bits</description>
37023 <bitOffset>22</bitOffset>
37024 <bitWidth>1</bitWidth>
37025 </field>
37026 <field>
37027 <name>FB23</name>
37028 <description>Filter bits</description>
37029 <bitOffset>23</bitOffset>
37030 <bitWidth>1</bitWidth>
37031 </field>
37032 <field>
37033 <name>FB24</name>
37034 <description>Filter bits</description>
37035 <bitOffset>24</bitOffset>
37036 <bitWidth>1</bitWidth>
37037 </field>
37038 <field>
37039 <name>FB25</name>
37040 <description>Filter bits</description>
37041 <bitOffset>25</bitOffset>
37042 <bitWidth>1</bitWidth>
37043 </field>
37044 <field>
37045 <name>FB26</name>
37046 <description>Filter bits</description>
37047 <bitOffset>26</bitOffset>
37048 <bitWidth>1</bitWidth>
37049 </field>
37050 <field>
37051 <name>FB27</name>
37052 <description>Filter bits</description>
37053 <bitOffset>27</bitOffset>
37054 <bitWidth>1</bitWidth>
37055 </field>
37056 <field>
37057 <name>FB28</name>
37058 <description>Filter bits</description>
37059 <bitOffset>28</bitOffset>
37060 <bitWidth>1</bitWidth>
37061 </field>
37062 <field>
37063 <name>FB29</name>
37064 <description>Filter bits</description>
37065 <bitOffset>29</bitOffset>
37066 <bitWidth>1</bitWidth>
37067 </field>
37068 <field>
37069 <name>FB30</name>
37070 <description>Filter bits</description>
37071 <bitOffset>30</bitOffset>
37072 <bitWidth>1</bitWidth>
37073 </field>
37074 <field>
37075 <name>FB31</name>
37076 <description>Filter bits</description>
37077 <bitOffset>31</bitOffset>
37078 <bitWidth>1</bitWidth>
37079 </field>
37080 </fields>
37081 </register>
37082 <register>
37083 <name>F21R1</name>
37084 <displayName>F21R1</displayName>
37085 <description>Filter bank 21 register 1</description>
37086 <addressOffset>0x2E8</addressOffset>
37087 <size>0x20</size>
37088 <access>read-write</access>
37089 <resetValue>0x00000000</resetValue>
37090 <fields>
37091 <field>
37092 <name>FB0</name>
37093 <description>Filter bits</description>
37094 <bitOffset>0</bitOffset>
37095 <bitWidth>1</bitWidth>
37096 </field>
37097 <field>
37098 <name>FB1</name>
37099 <description>Filter bits</description>
37100 <bitOffset>1</bitOffset>
37101 <bitWidth>1</bitWidth>
37102 </field>
37103 <field>
37104 <name>FB2</name>
37105 <description>Filter bits</description>
37106 <bitOffset>2</bitOffset>
37107 <bitWidth>1</bitWidth>
37108 </field>
37109 <field>
37110 <name>FB3</name>
37111 <description>Filter bits</description>
37112 <bitOffset>3</bitOffset>
37113 <bitWidth>1</bitWidth>
37114 </field>
37115 <field>
37116 <name>FB4</name>
37117 <description>Filter bits</description>
37118 <bitOffset>4</bitOffset>
37119 <bitWidth>1</bitWidth>
37120 </field>
37121 <field>
37122 <name>FB5</name>
37123 <description>Filter bits</description>
37124 <bitOffset>5</bitOffset>
37125 <bitWidth>1</bitWidth>
37126 </field>
37127 <field>
37128 <name>FB6</name>
37129 <description>Filter bits</description>
37130 <bitOffset>6</bitOffset>
37131 <bitWidth>1</bitWidth>
37132 </field>
37133 <field>
37134 <name>FB7</name>
37135 <description>Filter bits</description>
37136 <bitOffset>7</bitOffset>
37137 <bitWidth>1</bitWidth>
37138 </field>
37139 <field>
37140 <name>FB8</name>
37141 <description>Filter bits</description>
37142 <bitOffset>8</bitOffset>
37143 <bitWidth>1</bitWidth>
37144 </field>
37145 <field>
37146 <name>FB9</name>
37147 <description>Filter bits</description>
37148 <bitOffset>9</bitOffset>
37149 <bitWidth>1</bitWidth>
37150 </field>
37151 <field>
37152 <name>FB10</name>
37153 <description>Filter bits</description>
37154 <bitOffset>10</bitOffset>
37155 <bitWidth>1</bitWidth>
37156 </field>
37157 <field>
37158 <name>FB11</name>
37159 <description>Filter bits</description>
37160 <bitOffset>11</bitOffset>
37161 <bitWidth>1</bitWidth>
37162 </field>
37163 <field>
37164 <name>FB12</name>
37165 <description>Filter bits</description>
37166 <bitOffset>12</bitOffset>
37167 <bitWidth>1</bitWidth>
37168 </field>
37169 <field>
37170 <name>FB13</name>
37171 <description>Filter bits</description>
37172 <bitOffset>13</bitOffset>
37173 <bitWidth>1</bitWidth>
37174 </field>
37175 <field>
37176 <name>FB14</name>
37177 <description>Filter bits</description>
37178 <bitOffset>14</bitOffset>
37179 <bitWidth>1</bitWidth>
37180 </field>
37181 <field>
37182 <name>FB15</name>
37183 <description>Filter bits</description>
37184 <bitOffset>15</bitOffset>
37185 <bitWidth>1</bitWidth>
37186 </field>
37187 <field>
37188 <name>FB16</name>
37189 <description>Filter bits</description>
37190 <bitOffset>16</bitOffset>
37191 <bitWidth>1</bitWidth>
37192 </field>
37193 <field>
37194 <name>FB17</name>
37195 <description>Filter bits</description>
37196 <bitOffset>17</bitOffset>
37197 <bitWidth>1</bitWidth>
37198 </field>
37199 <field>
37200 <name>FB18</name>
37201 <description>Filter bits</description>
37202 <bitOffset>18</bitOffset>
37203 <bitWidth>1</bitWidth>
37204 </field>
37205 <field>
37206 <name>FB19</name>
37207 <description>Filter bits</description>
37208 <bitOffset>19</bitOffset>
37209 <bitWidth>1</bitWidth>
37210 </field>
37211 <field>
37212 <name>FB20</name>
37213 <description>Filter bits</description>
37214 <bitOffset>20</bitOffset>
37215 <bitWidth>1</bitWidth>
37216 </field>
37217 <field>
37218 <name>FB21</name>
37219 <description>Filter bits</description>
37220 <bitOffset>21</bitOffset>
37221 <bitWidth>1</bitWidth>
37222 </field>
37223 <field>
37224 <name>FB22</name>
37225 <description>Filter bits</description>
37226 <bitOffset>22</bitOffset>
37227 <bitWidth>1</bitWidth>
37228 </field>
37229 <field>
37230 <name>FB23</name>
37231 <description>Filter bits</description>
37232 <bitOffset>23</bitOffset>
37233 <bitWidth>1</bitWidth>
37234 </field>
37235 <field>
37236 <name>FB24</name>
37237 <description>Filter bits</description>
37238 <bitOffset>24</bitOffset>
37239 <bitWidth>1</bitWidth>
37240 </field>
37241 <field>
37242 <name>FB25</name>
37243 <description>Filter bits</description>
37244 <bitOffset>25</bitOffset>
37245 <bitWidth>1</bitWidth>
37246 </field>
37247 <field>
37248 <name>FB26</name>
37249 <description>Filter bits</description>
37250 <bitOffset>26</bitOffset>
37251 <bitWidth>1</bitWidth>
37252 </field>
37253 <field>
37254 <name>FB27</name>
37255 <description>Filter bits</description>
37256 <bitOffset>27</bitOffset>
37257 <bitWidth>1</bitWidth>
37258 </field>
37259 <field>
37260 <name>FB28</name>
37261 <description>Filter bits</description>
37262 <bitOffset>28</bitOffset>
37263 <bitWidth>1</bitWidth>
37264 </field>
37265 <field>
37266 <name>FB29</name>
37267 <description>Filter bits</description>
37268 <bitOffset>29</bitOffset>
37269 <bitWidth>1</bitWidth>
37270 </field>
37271 <field>
37272 <name>FB30</name>
37273 <description>Filter bits</description>
37274 <bitOffset>30</bitOffset>
37275 <bitWidth>1</bitWidth>
37276 </field>
37277 <field>
37278 <name>FB31</name>
37279 <description>Filter bits</description>
37280 <bitOffset>31</bitOffset>
37281 <bitWidth>1</bitWidth>
37282 </field>
37283 </fields>
37284 </register>
37285 <register>
37286 <name>F21R2</name>
37287 <displayName>F21R2</displayName>
37288 <description>Filter bank 21 register 2</description>
37289 <addressOffset>0x2EC</addressOffset>
37290 <size>0x20</size>
37291 <access>read-write</access>
37292 <resetValue>0x00000000</resetValue>
37293 <fields>
37294 <field>
37295 <name>FB0</name>
37296 <description>Filter bits</description>
37297 <bitOffset>0</bitOffset>
37298 <bitWidth>1</bitWidth>
37299 </field>
37300 <field>
37301 <name>FB1</name>
37302 <description>Filter bits</description>
37303 <bitOffset>1</bitOffset>
37304 <bitWidth>1</bitWidth>
37305 </field>
37306 <field>
37307 <name>FB2</name>
37308 <description>Filter bits</description>
37309 <bitOffset>2</bitOffset>
37310 <bitWidth>1</bitWidth>
37311 </field>
37312 <field>
37313 <name>FB3</name>
37314 <description>Filter bits</description>
37315 <bitOffset>3</bitOffset>
37316 <bitWidth>1</bitWidth>
37317 </field>
37318 <field>
37319 <name>FB4</name>
37320 <description>Filter bits</description>
37321 <bitOffset>4</bitOffset>
37322 <bitWidth>1</bitWidth>
37323 </field>
37324 <field>
37325 <name>FB5</name>
37326 <description>Filter bits</description>
37327 <bitOffset>5</bitOffset>
37328 <bitWidth>1</bitWidth>
37329 </field>
37330 <field>
37331 <name>FB6</name>
37332 <description>Filter bits</description>
37333 <bitOffset>6</bitOffset>
37334 <bitWidth>1</bitWidth>
37335 </field>
37336 <field>
37337 <name>FB7</name>
37338 <description>Filter bits</description>
37339 <bitOffset>7</bitOffset>
37340 <bitWidth>1</bitWidth>
37341 </field>
37342 <field>
37343 <name>FB8</name>
37344 <description>Filter bits</description>
37345 <bitOffset>8</bitOffset>
37346 <bitWidth>1</bitWidth>
37347 </field>
37348 <field>
37349 <name>FB9</name>
37350 <description>Filter bits</description>
37351 <bitOffset>9</bitOffset>
37352 <bitWidth>1</bitWidth>
37353 </field>
37354 <field>
37355 <name>FB10</name>
37356 <description>Filter bits</description>
37357 <bitOffset>10</bitOffset>
37358 <bitWidth>1</bitWidth>
37359 </field>
37360 <field>
37361 <name>FB11</name>
37362 <description>Filter bits</description>
37363 <bitOffset>11</bitOffset>
37364 <bitWidth>1</bitWidth>
37365 </field>
37366 <field>
37367 <name>FB12</name>
37368 <description>Filter bits</description>
37369 <bitOffset>12</bitOffset>
37370 <bitWidth>1</bitWidth>
37371 </field>
37372 <field>
37373 <name>FB13</name>
37374 <description>Filter bits</description>
37375 <bitOffset>13</bitOffset>
37376 <bitWidth>1</bitWidth>
37377 </field>
37378 <field>
37379 <name>FB14</name>
37380 <description>Filter bits</description>
37381 <bitOffset>14</bitOffset>
37382 <bitWidth>1</bitWidth>
37383 </field>
37384 <field>
37385 <name>FB15</name>
37386 <description>Filter bits</description>
37387 <bitOffset>15</bitOffset>
37388 <bitWidth>1</bitWidth>
37389 </field>
37390 <field>
37391 <name>FB16</name>
37392 <description>Filter bits</description>
37393 <bitOffset>16</bitOffset>
37394 <bitWidth>1</bitWidth>
37395 </field>
37396 <field>
37397 <name>FB17</name>
37398 <description>Filter bits</description>
37399 <bitOffset>17</bitOffset>
37400 <bitWidth>1</bitWidth>
37401 </field>
37402 <field>
37403 <name>FB18</name>
37404 <description>Filter bits</description>
37405 <bitOffset>18</bitOffset>
37406 <bitWidth>1</bitWidth>
37407 </field>
37408 <field>
37409 <name>FB19</name>
37410 <description>Filter bits</description>
37411 <bitOffset>19</bitOffset>
37412 <bitWidth>1</bitWidth>
37413 </field>
37414 <field>
37415 <name>FB20</name>
37416 <description>Filter bits</description>
37417 <bitOffset>20</bitOffset>
37418 <bitWidth>1</bitWidth>
37419 </field>
37420 <field>
37421 <name>FB21</name>
37422 <description>Filter bits</description>
37423 <bitOffset>21</bitOffset>
37424 <bitWidth>1</bitWidth>
37425 </field>
37426 <field>
37427 <name>FB22</name>
37428 <description>Filter bits</description>
37429 <bitOffset>22</bitOffset>
37430 <bitWidth>1</bitWidth>
37431 </field>
37432 <field>
37433 <name>FB23</name>
37434 <description>Filter bits</description>
37435 <bitOffset>23</bitOffset>
37436 <bitWidth>1</bitWidth>
37437 </field>
37438 <field>
37439 <name>FB24</name>
37440 <description>Filter bits</description>
37441 <bitOffset>24</bitOffset>
37442 <bitWidth>1</bitWidth>
37443 </field>
37444 <field>
37445 <name>FB25</name>
37446 <description>Filter bits</description>
37447 <bitOffset>25</bitOffset>
37448 <bitWidth>1</bitWidth>
37449 </field>
37450 <field>
37451 <name>FB26</name>
37452 <description>Filter bits</description>
37453 <bitOffset>26</bitOffset>
37454 <bitWidth>1</bitWidth>
37455 </field>
37456 <field>
37457 <name>FB27</name>
37458 <description>Filter bits</description>
37459 <bitOffset>27</bitOffset>
37460 <bitWidth>1</bitWidth>
37461 </field>
37462 <field>
37463 <name>FB28</name>
37464 <description>Filter bits</description>
37465 <bitOffset>28</bitOffset>
37466 <bitWidth>1</bitWidth>
37467 </field>
37468 <field>
37469 <name>FB29</name>
37470 <description>Filter bits</description>
37471 <bitOffset>29</bitOffset>
37472 <bitWidth>1</bitWidth>
37473 </field>
37474 <field>
37475 <name>FB30</name>
37476 <description>Filter bits</description>
37477 <bitOffset>30</bitOffset>
37478 <bitWidth>1</bitWidth>
37479 </field>
37480 <field>
37481 <name>FB31</name>
37482 <description>Filter bits</description>
37483 <bitOffset>31</bitOffset>
37484 <bitWidth>1</bitWidth>
37485 </field>
37486 </fields>
37487 </register>
37488 <register>
37489 <name>F22R1</name>
37490 <displayName>F22R1</displayName>
37491 <description>Filter bank 22 register 1</description>
37492 <addressOffset>0x2F0</addressOffset>
37493 <size>0x20</size>
37494 <access>read-write</access>
37495 <resetValue>0x00000000</resetValue>
37496 <fields>
37497 <field>
37498 <name>FB0</name>
37499 <description>Filter bits</description>
37500 <bitOffset>0</bitOffset>
37501 <bitWidth>1</bitWidth>
37502 </field>
37503 <field>
37504 <name>FB1</name>
37505 <description>Filter bits</description>
37506 <bitOffset>1</bitOffset>
37507 <bitWidth>1</bitWidth>
37508 </field>
37509 <field>
37510 <name>FB2</name>
37511 <description>Filter bits</description>
37512 <bitOffset>2</bitOffset>
37513 <bitWidth>1</bitWidth>
37514 </field>
37515 <field>
37516 <name>FB3</name>
37517 <description>Filter bits</description>
37518 <bitOffset>3</bitOffset>
37519 <bitWidth>1</bitWidth>
37520 </field>
37521 <field>
37522 <name>FB4</name>
37523 <description>Filter bits</description>
37524 <bitOffset>4</bitOffset>
37525 <bitWidth>1</bitWidth>
37526 </field>
37527 <field>
37528 <name>FB5</name>
37529 <description>Filter bits</description>
37530 <bitOffset>5</bitOffset>
37531 <bitWidth>1</bitWidth>
37532 </field>
37533 <field>
37534 <name>FB6</name>
37535 <description>Filter bits</description>
37536 <bitOffset>6</bitOffset>
37537 <bitWidth>1</bitWidth>
37538 </field>
37539 <field>
37540 <name>FB7</name>
37541 <description>Filter bits</description>
37542 <bitOffset>7</bitOffset>
37543 <bitWidth>1</bitWidth>
37544 </field>
37545 <field>
37546 <name>FB8</name>
37547 <description>Filter bits</description>
37548 <bitOffset>8</bitOffset>
37549 <bitWidth>1</bitWidth>
37550 </field>
37551 <field>
37552 <name>FB9</name>
37553 <description>Filter bits</description>
37554 <bitOffset>9</bitOffset>
37555 <bitWidth>1</bitWidth>
37556 </field>
37557 <field>
37558 <name>FB10</name>
37559 <description>Filter bits</description>
37560 <bitOffset>10</bitOffset>
37561 <bitWidth>1</bitWidth>
37562 </field>
37563 <field>
37564 <name>FB11</name>
37565 <description>Filter bits</description>
37566 <bitOffset>11</bitOffset>
37567 <bitWidth>1</bitWidth>
37568 </field>
37569 <field>
37570 <name>FB12</name>
37571 <description>Filter bits</description>
37572 <bitOffset>12</bitOffset>
37573 <bitWidth>1</bitWidth>
37574 </field>
37575 <field>
37576 <name>FB13</name>
37577 <description>Filter bits</description>
37578 <bitOffset>13</bitOffset>
37579 <bitWidth>1</bitWidth>
37580 </field>
37581 <field>
37582 <name>FB14</name>
37583 <description>Filter bits</description>
37584 <bitOffset>14</bitOffset>
37585 <bitWidth>1</bitWidth>
37586 </field>
37587 <field>
37588 <name>FB15</name>
37589 <description>Filter bits</description>
37590 <bitOffset>15</bitOffset>
37591 <bitWidth>1</bitWidth>
37592 </field>
37593 <field>
37594 <name>FB16</name>
37595 <description>Filter bits</description>
37596 <bitOffset>16</bitOffset>
37597 <bitWidth>1</bitWidth>
37598 </field>
37599 <field>
37600 <name>FB17</name>
37601 <description>Filter bits</description>
37602 <bitOffset>17</bitOffset>
37603 <bitWidth>1</bitWidth>
37604 </field>
37605 <field>
37606 <name>FB18</name>
37607 <description>Filter bits</description>
37608 <bitOffset>18</bitOffset>
37609 <bitWidth>1</bitWidth>
37610 </field>
37611 <field>
37612 <name>FB19</name>
37613 <description>Filter bits</description>
37614 <bitOffset>19</bitOffset>
37615 <bitWidth>1</bitWidth>
37616 </field>
37617 <field>
37618 <name>FB20</name>
37619 <description>Filter bits</description>
37620 <bitOffset>20</bitOffset>
37621 <bitWidth>1</bitWidth>
37622 </field>
37623 <field>
37624 <name>FB21</name>
37625 <description>Filter bits</description>
37626 <bitOffset>21</bitOffset>
37627 <bitWidth>1</bitWidth>
37628 </field>
37629 <field>
37630 <name>FB22</name>
37631 <description>Filter bits</description>
37632 <bitOffset>22</bitOffset>
37633 <bitWidth>1</bitWidth>
37634 </field>
37635 <field>
37636 <name>FB23</name>
37637 <description>Filter bits</description>
37638 <bitOffset>23</bitOffset>
37639 <bitWidth>1</bitWidth>
37640 </field>
37641 <field>
37642 <name>FB24</name>
37643 <description>Filter bits</description>
37644 <bitOffset>24</bitOffset>
37645 <bitWidth>1</bitWidth>
37646 </field>
37647 <field>
37648 <name>FB25</name>
37649 <description>Filter bits</description>
37650 <bitOffset>25</bitOffset>
37651 <bitWidth>1</bitWidth>
37652 </field>
37653 <field>
37654 <name>FB26</name>
37655 <description>Filter bits</description>
37656 <bitOffset>26</bitOffset>
37657 <bitWidth>1</bitWidth>
37658 </field>
37659 <field>
37660 <name>FB27</name>
37661 <description>Filter bits</description>
37662 <bitOffset>27</bitOffset>
37663 <bitWidth>1</bitWidth>
37664 </field>
37665 <field>
37666 <name>FB28</name>
37667 <description>Filter bits</description>
37668 <bitOffset>28</bitOffset>
37669 <bitWidth>1</bitWidth>
37670 </field>
37671 <field>
37672 <name>FB29</name>
37673 <description>Filter bits</description>
37674 <bitOffset>29</bitOffset>
37675 <bitWidth>1</bitWidth>
37676 </field>
37677 <field>
37678 <name>FB30</name>
37679 <description>Filter bits</description>
37680 <bitOffset>30</bitOffset>
37681 <bitWidth>1</bitWidth>
37682 </field>
37683 <field>
37684 <name>FB31</name>
37685 <description>Filter bits</description>
37686 <bitOffset>31</bitOffset>
37687 <bitWidth>1</bitWidth>
37688 </field>
37689 </fields>
37690 </register>
37691 <register>
37692 <name>F22R2</name>
37693 <displayName>F22R2</displayName>
37694 <description>Filter bank 22 register 2</description>
37695 <addressOffset>0x2F4</addressOffset>
37696 <size>0x20</size>
37697 <access>read-write</access>
37698 <resetValue>0x00000000</resetValue>
37699 <fields>
37700 <field>
37701 <name>FB0</name>
37702 <description>Filter bits</description>
37703 <bitOffset>0</bitOffset>
37704 <bitWidth>1</bitWidth>
37705 </field>
37706 <field>
37707 <name>FB1</name>
37708 <description>Filter bits</description>
37709 <bitOffset>1</bitOffset>
37710 <bitWidth>1</bitWidth>
37711 </field>
37712 <field>
37713 <name>FB2</name>
37714 <description>Filter bits</description>
37715 <bitOffset>2</bitOffset>
37716 <bitWidth>1</bitWidth>
37717 </field>
37718 <field>
37719 <name>FB3</name>
37720 <description>Filter bits</description>
37721 <bitOffset>3</bitOffset>
37722 <bitWidth>1</bitWidth>
37723 </field>
37724 <field>
37725 <name>FB4</name>
37726 <description>Filter bits</description>
37727 <bitOffset>4</bitOffset>
37728 <bitWidth>1</bitWidth>
37729 </field>
37730 <field>
37731 <name>FB5</name>
37732 <description>Filter bits</description>
37733 <bitOffset>5</bitOffset>
37734 <bitWidth>1</bitWidth>
37735 </field>
37736 <field>
37737 <name>FB6</name>
37738 <description>Filter bits</description>
37739 <bitOffset>6</bitOffset>
37740 <bitWidth>1</bitWidth>
37741 </field>
37742 <field>
37743 <name>FB7</name>
37744 <description>Filter bits</description>
37745 <bitOffset>7</bitOffset>
37746 <bitWidth>1</bitWidth>
37747 </field>
37748 <field>
37749 <name>FB8</name>
37750 <description>Filter bits</description>
37751 <bitOffset>8</bitOffset>
37752 <bitWidth>1</bitWidth>
37753 </field>
37754 <field>
37755 <name>FB9</name>
37756 <description>Filter bits</description>
37757 <bitOffset>9</bitOffset>
37758 <bitWidth>1</bitWidth>
37759 </field>
37760 <field>
37761 <name>FB10</name>
37762 <description>Filter bits</description>
37763 <bitOffset>10</bitOffset>
37764 <bitWidth>1</bitWidth>
37765 </field>
37766 <field>
37767 <name>FB11</name>
37768 <description>Filter bits</description>
37769 <bitOffset>11</bitOffset>
37770 <bitWidth>1</bitWidth>
37771 </field>
37772 <field>
37773 <name>FB12</name>
37774 <description>Filter bits</description>
37775 <bitOffset>12</bitOffset>
37776 <bitWidth>1</bitWidth>
37777 </field>
37778 <field>
37779 <name>FB13</name>
37780 <description>Filter bits</description>
37781 <bitOffset>13</bitOffset>
37782 <bitWidth>1</bitWidth>
37783 </field>
37784 <field>
37785 <name>FB14</name>
37786 <description>Filter bits</description>
37787 <bitOffset>14</bitOffset>
37788 <bitWidth>1</bitWidth>
37789 </field>
37790 <field>
37791 <name>FB15</name>
37792 <description>Filter bits</description>
37793 <bitOffset>15</bitOffset>
37794 <bitWidth>1</bitWidth>
37795 </field>
37796 <field>
37797 <name>FB16</name>
37798 <description>Filter bits</description>
37799 <bitOffset>16</bitOffset>
37800 <bitWidth>1</bitWidth>
37801 </field>
37802 <field>
37803 <name>FB17</name>
37804 <description>Filter bits</description>
37805 <bitOffset>17</bitOffset>
37806 <bitWidth>1</bitWidth>
37807 </field>
37808 <field>
37809 <name>FB18</name>
37810 <description>Filter bits</description>
37811 <bitOffset>18</bitOffset>
37812 <bitWidth>1</bitWidth>
37813 </field>
37814 <field>
37815 <name>FB19</name>
37816 <description>Filter bits</description>
37817 <bitOffset>19</bitOffset>
37818 <bitWidth>1</bitWidth>
37819 </field>
37820 <field>
37821 <name>FB20</name>
37822 <description>Filter bits</description>
37823 <bitOffset>20</bitOffset>
37824 <bitWidth>1</bitWidth>
37825 </field>
37826 <field>
37827 <name>FB21</name>
37828 <description>Filter bits</description>
37829 <bitOffset>21</bitOffset>
37830 <bitWidth>1</bitWidth>
37831 </field>
37832 <field>
37833 <name>FB22</name>
37834 <description>Filter bits</description>
37835 <bitOffset>22</bitOffset>
37836 <bitWidth>1</bitWidth>
37837 </field>
37838 <field>
37839 <name>FB23</name>
37840 <description>Filter bits</description>
37841 <bitOffset>23</bitOffset>
37842 <bitWidth>1</bitWidth>
37843 </field>
37844 <field>
37845 <name>FB24</name>
37846 <description>Filter bits</description>
37847 <bitOffset>24</bitOffset>
37848 <bitWidth>1</bitWidth>
37849 </field>
37850 <field>
37851 <name>FB25</name>
37852 <description>Filter bits</description>
37853 <bitOffset>25</bitOffset>
37854 <bitWidth>1</bitWidth>
37855 </field>
37856 <field>
37857 <name>FB26</name>
37858 <description>Filter bits</description>
37859 <bitOffset>26</bitOffset>
37860 <bitWidth>1</bitWidth>
37861 </field>
37862 <field>
37863 <name>FB27</name>
37864 <description>Filter bits</description>
37865 <bitOffset>27</bitOffset>
37866 <bitWidth>1</bitWidth>
37867 </field>
37868 <field>
37869 <name>FB28</name>
37870 <description>Filter bits</description>
37871 <bitOffset>28</bitOffset>
37872 <bitWidth>1</bitWidth>
37873 </field>
37874 <field>
37875 <name>FB29</name>
37876 <description>Filter bits</description>
37877 <bitOffset>29</bitOffset>
37878 <bitWidth>1</bitWidth>
37879 </field>
37880 <field>
37881 <name>FB30</name>
37882 <description>Filter bits</description>
37883 <bitOffset>30</bitOffset>
37884 <bitWidth>1</bitWidth>
37885 </field>
37886 <field>
37887 <name>FB31</name>
37888 <description>Filter bits</description>
37889 <bitOffset>31</bitOffset>
37890 <bitWidth>1</bitWidth>
37891 </field>
37892 </fields>
37893 </register>
37894 <register>
37895 <name>F23R1</name>
37896 <displayName>F23R1</displayName>
37897 <description>Filter bank 23 register 1</description>
37898 <addressOffset>0x2F8</addressOffset>
37899 <size>0x20</size>
37900 <access>read-write</access>
37901 <resetValue>0x00000000</resetValue>
37902 <fields>
37903 <field>
37904 <name>FB0</name>
37905 <description>Filter bits</description>
37906 <bitOffset>0</bitOffset>
37907 <bitWidth>1</bitWidth>
37908 </field>
37909 <field>
37910 <name>FB1</name>
37911 <description>Filter bits</description>
37912 <bitOffset>1</bitOffset>
37913 <bitWidth>1</bitWidth>
37914 </field>
37915 <field>
37916 <name>FB2</name>
37917 <description>Filter bits</description>
37918 <bitOffset>2</bitOffset>
37919 <bitWidth>1</bitWidth>
37920 </field>
37921 <field>
37922 <name>FB3</name>
37923 <description>Filter bits</description>
37924 <bitOffset>3</bitOffset>
37925 <bitWidth>1</bitWidth>
37926 </field>
37927 <field>
37928 <name>FB4</name>
37929 <description>Filter bits</description>
37930 <bitOffset>4</bitOffset>
37931 <bitWidth>1</bitWidth>
37932 </field>
37933 <field>
37934 <name>FB5</name>
37935 <description>Filter bits</description>
37936 <bitOffset>5</bitOffset>
37937 <bitWidth>1</bitWidth>
37938 </field>
37939 <field>
37940 <name>FB6</name>
37941 <description>Filter bits</description>
37942 <bitOffset>6</bitOffset>
37943 <bitWidth>1</bitWidth>
37944 </field>
37945 <field>
37946 <name>FB7</name>
37947 <description>Filter bits</description>
37948 <bitOffset>7</bitOffset>
37949 <bitWidth>1</bitWidth>
37950 </field>
37951 <field>
37952 <name>FB8</name>
37953 <description>Filter bits</description>
37954 <bitOffset>8</bitOffset>
37955 <bitWidth>1</bitWidth>
37956 </field>
37957 <field>
37958 <name>FB9</name>
37959 <description>Filter bits</description>
37960 <bitOffset>9</bitOffset>
37961 <bitWidth>1</bitWidth>
37962 </field>
37963 <field>
37964 <name>FB10</name>
37965 <description>Filter bits</description>
37966 <bitOffset>10</bitOffset>
37967 <bitWidth>1</bitWidth>
37968 </field>
37969 <field>
37970 <name>FB11</name>
37971 <description>Filter bits</description>
37972 <bitOffset>11</bitOffset>
37973 <bitWidth>1</bitWidth>
37974 </field>
37975 <field>
37976 <name>FB12</name>
37977 <description>Filter bits</description>
37978 <bitOffset>12</bitOffset>
37979 <bitWidth>1</bitWidth>
37980 </field>
37981 <field>
37982 <name>FB13</name>
37983 <description>Filter bits</description>
37984 <bitOffset>13</bitOffset>
37985 <bitWidth>1</bitWidth>
37986 </field>
37987 <field>
37988 <name>FB14</name>
37989 <description>Filter bits</description>
37990 <bitOffset>14</bitOffset>
37991 <bitWidth>1</bitWidth>
37992 </field>
37993 <field>
37994 <name>FB15</name>
37995 <description>Filter bits</description>
37996 <bitOffset>15</bitOffset>
37997 <bitWidth>1</bitWidth>
37998 </field>
37999 <field>
38000 <name>FB16</name>
38001 <description>Filter bits</description>
38002 <bitOffset>16</bitOffset>
38003 <bitWidth>1</bitWidth>
38004 </field>
38005 <field>
38006 <name>FB17</name>
38007 <description>Filter bits</description>
38008 <bitOffset>17</bitOffset>
38009 <bitWidth>1</bitWidth>
38010 </field>
38011 <field>
38012 <name>FB18</name>
38013 <description>Filter bits</description>
38014 <bitOffset>18</bitOffset>
38015 <bitWidth>1</bitWidth>
38016 </field>
38017 <field>
38018 <name>FB19</name>
38019 <description>Filter bits</description>
38020 <bitOffset>19</bitOffset>
38021 <bitWidth>1</bitWidth>
38022 </field>
38023 <field>
38024 <name>FB20</name>
38025 <description>Filter bits</description>
38026 <bitOffset>20</bitOffset>
38027 <bitWidth>1</bitWidth>
38028 </field>
38029 <field>
38030 <name>FB21</name>
38031 <description>Filter bits</description>
38032 <bitOffset>21</bitOffset>
38033 <bitWidth>1</bitWidth>
38034 </field>
38035 <field>
38036 <name>FB22</name>
38037 <description>Filter bits</description>
38038 <bitOffset>22</bitOffset>
38039 <bitWidth>1</bitWidth>
38040 </field>
38041 <field>
38042 <name>FB23</name>
38043 <description>Filter bits</description>
38044 <bitOffset>23</bitOffset>
38045 <bitWidth>1</bitWidth>
38046 </field>
38047 <field>
38048 <name>FB24</name>
38049 <description>Filter bits</description>
38050 <bitOffset>24</bitOffset>
38051 <bitWidth>1</bitWidth>
38052 </field>
38053 <field>
38054 <name>FB25</name>
38055 <description>Filter bits</description>
38056 <bitOffset>25</bitOffset>
38057 <bitWidth>1</bitWidth>
38058 </field>
38059 <field>
38060 <name>FB26</name>
38061 <description>Filter bits</description>
38062 <bitOffset>26</bitOffset>
38063 <bitWidth>1</bitWidth>
38064 </field>
38065 <field>
38066 <name>FB27</name>
38067 <description>Filter bits</description>
38068 <bitOffset>27</bitOffset>
38069 <bitWidth>1</bitWidth>
38070 </field>
38071 <field>
38072 <name>FB28</name>
38073 <description>Filter bits</description>
38074 <bitOffset>28</bitOffset>
38075 <bitWidth>1</bitWidth>
38076 </field>
38077 <field>
38078 <name>FB29</name>
38079 <description>Filter bits</description>
38080 <bitOffset>29</bitOffset>
38081 <bitWidth>1</bitWidth>
38082 </field>
38083 <field>
38084 <name>FB30</name>
38085 <description>Filter bits</description>
38086 <bitOffset>30</bitOffset>
38087 <bitWidth>1</bitWidth>
38088 </field>
38089 <field>
38090 <name>FB31</name>
38091 <description>Filter bits</description>
38092 <bitOffset>31</bitOffset>
38093 <bitWidth>1</bitWidth>
38094 </field>
38095 </fields>
38096 </register>
38097 <register>
38098 <name>F23R2</name>
38099 <displayName>F23R2</displayName>
38100 <description>Filter bank 23 register 2</description>
38101 <addressOffset>0x2FC</addressOffset>
38102 <size>0x20</size>
38103 <access>read-write</access>
38104 <resetValue>0x00000000</resetValue>
38105 <fields>
38106 <field>
38107 <name>FB0</name>
38108 <description>Filter bits</description>
38109 <bitOffset>0</bitOffset>
38110 <bitWidth>1</bitWidth>
38111 </field>
38112 <field>
38113 <name>FB1</name>
38114 <description>Filter bits</description>
38115 <bitOffset>1</bitOffset>
38116 <bitWidth>1</bitWidth>
38117 </field>
38118 <field>
38119 <name>FB2</name>
38120 <description>Filter bits</description>
38121 <bitOffset>2</bitOffset>
38122 <bitWidth>1</bitWidth>
38123 </field>
38124 <field>
38125 <name>FB3</name>
38126 <description>Filter bits</description>
38127 <bitOffset>3</bitOffset>
38128 <bitWidth>1</bitWidth>
38129 </field>
38130 <field>
38131 <name>FB4</name>
38132 <description>Filter bits</description>
38133 <bitOffset>4</bitOffset>
38134 <bitWidth>1</bitWidth>
38135 </field>
38136 <field>
38137 <name>FB5</name>
38138 <description>Filter bits</description>
38139 <bitOffset>5</bitOffset>
38140 <bitWidth>1</bitWidth>
38141 </field>
38142 <field>
38143 <name>FB6</name>
38144 <description>Filter bits</description>
38145 <bitOffset>6</bitOffset>
38146 <bitWidth>1</bitWidth>
38147 </field>
38148 <field>
38149 <name>FB7</name>
38150 <description>Filter bits</description>
38151 <bitOffset>7</bitOffset>
38152 <bitWidth>1</bitWidth>
38153 </field>
38154 <field>
38155 <name>FB8</name>
38156 <description>Filter bits</description>
38157 <bitOffset>8</bitOffset>
38158 <bitWidth>1</bitWidth>
38159 </field>
38160 <field>
38161 <name>FB9</name>
38162 <description>Filter bits</description>
38163 <bitOffset>9</bitOffset>
38164 <bitWidth>1</bitWidth>
38165 </field>
38166 <field>
38167 <name>FB10</name>
38168 <description>Filter bits</description>
38169 <bitOffset>10</bitOffset>
38170 <bitWidth>1</bitWidth>
38171 </field>
38172 <field>
38173 <name>FB11</name>
38174 <description>Filter bits</description>
38175 <bitOffset>11</bitOffset>
38176 <bitWidth>1</bitWidth>
38177 </field>
38178 <field>
38179 <name>FB12</name>
38180 <description>Filter bits</description>
38181 <bitOffset>12</bitOffset>
38182 <bitWidth>1</bitWidth>
38183 </field>
38184 <field>
38185 <name>FB13</name>
38186 <description>Filter bits</description>
38187 <bitOffset>13</bitOffset>
38188 <bitWidth>1</bitWidth>
38189 </field>
38190 <field>
38191 <name>FB14</name>
38192 <description>Filter bits</description>
38193 <bitOffset>14</bitOffset>
38194 <bitWidth>1</bitWidth>
38195 </field>
38196 <field>
38197 <name>FB15</name>
38198 <description>Filter bits</description>
38199 <bitOffset>15</bitOffset>
38200 <bitWidth>1</bitWidth>
38201 </field>
38202 <field>
38203 <name>FB16</name>
38204 <description>Filter bits</description>
38205 <bitOffset>16</bitOffset>
38206 <bitWidth>1</bitWidth>
38207 </field>
38208 <field>
38209 <name>FB17</name>
38210 <description>Filter bits</description>
38211 <bitOffset>17</bitOffset>
38212 <bitWidth>1</bitWidth>
38213 </field>
38214 <field>
38215 <name>FB18</name>
38216 <description>Filter bits</description>
38217 <bitOffset>18</bitOffset>
38218 <bitWidth>1</bitWidth>
38219 </field>
38220 <field>
38221 <name>FB19</name>
38222 <description>Filter bits</description>
38223 <bitOffset>19</bitOffset>
38224 <bitWidth>1</bitWidth>
38225 </field>
38226 <field>
38227 <name>FB20</name>
38228 <description>Filter bits</description>
38229 <bitOffset>20</bitOffset>
38230 <bitWidth>1</bitWidth>
38231 </field>
38232 <field>
38233 <name>FB21</name>
38234 <description>Filter bits</description>
38235 <bitOffset>21</bitOffset>
38236 <bitWidth>1</bitWidth>
38237 </field>
38238 <field>
38239 <name>FB22</name>
38240 <description>Filter bits</description>
38241 <bitOffset>22</bitOffset>
38242 <bitWidth>1</bitWidth>
38243 </field>
38244 <field>
38245 <name>FB23</name>
38246 <description>Filter bits</description>
38247 <bitOffset>23</bitOffset>
38248 <bitWidth>1</bitWidth>
38249 </field>
38250 <field>
38251 <name>FB24</name>
38252 <description>Filter bits</description>
38253 <bitOffset>24</bitOffset>
38254 <bitWidth>1</bitWidth>
38255 </field>
38256 <field>
38257 <name>FB25</name>
38258 <description>Filter bits</description>
38259 <bitOffset>25</bitOffset>
38260 <bitWidth>1</bitWidth>
38261 </field>
38262 <field>
38263 <name>FB26</name>
38264 <description>Filter bits</description>
38265 <bitOffset>26</bitOffset>
38266 <bitWidth>1</bitWidth>
38267 </field>
38268 <field>
38269 <name>FB27</name>
38270 <description>Filter bits</description>
38271 <bitOffset>27</bitOffset>
38272 <bitWidth>1</bitWidth>
38273 </field>
38274 <field>
38275 <name>FB28</name>
38276 <description>Filter bits</description>
38277 <bitOffset>28</bitOffset>
38278 <bitWidth>1</bitWidth>
38279 </field>
38280 <field>
38281 <name>FB29</name>
38282 <description>Filter bits</description>
38283 <bitOffset>29</bitOffset>
38284 <bitWidth>1</bitWidth>
38285 </field>
38286 <field>
38287 <name>FB30</name>
38288 <description>Filter bits</description>
38289 <bitOffset>30</bitOffset>
38290 <bitWidth>1</bitWidth>
38291 </field>
38292 <field>
38293 <name>FB31</name>
38294 <description>Filter bits</description>
38295 <bitOffset>31</bitOffset>
38296 <bitWidth>1</bitWidth>
38297 </field>
38298 </fields>
38299 </register>
38300 <register>
38301 <name>F24R1</name>
38302 <displayName>F24R1</displayName>
38303 <description>Filter bank 24 register 1</description>
38304 <addressOffset>0x300</addressOffset>
38305 <size>0x20</size>
38306 <access>read-write</access>
38307 <resetValue>0x00000000</resetValue>
38308 <fields>
38309 <field>
38310 <name>FB0</name>
38311 <description>Filter bits</description>
38312 <bitOffset>0</bitOffset>
38313 <bitWidth>1</bitWidth>
38314 </field>
38315 <field>
38316 <name>FB1</name>
38317 <description>Filter bits</description>
38318 <bitOffset>1</bitOffset>
38319 <bitWidth>1</bitWidth>
38320 </field>
38321 <field>
38322 <name>FB2</name>
38323 <description>Filter bits</description>
38324 <bitOffset>2</bitOffset>
38325 <bitWidth>1</bitWidth>
38326 </field>
38327 <field>
38328 <name>FB3</name>
38329 <description>Filter bits</description>
38330 <bitOffset>3</bitOffset>
38331 <bitWidth>1</bitWidth>
38332 </field>
38333 <field>
38334 <name>FB4</name>
38335 <description>Filter bits</description>
38336 <bitOffset>4</bitOffset>
38337 <bitWidth>1</bitWidth>
38338 </field>
38339 <field>
38340 <name>FB5</name>
38341 <description>Filter bits</description>
38342 <bitOffset>5</bitOffset>
38343 <bitWidth>1</bitWidth>
38344 </field>
38345 <field>
38346 <name>FB6</name>
38347 <description>Filter bits</description>
38348 <bitOffset>6</bitOffset>
38349 <bitWidth>1</bitWidth>
38350 </field>
38351 <field>
38352 <name>FB7</name>
38353 <description>Filter bits</description>
38354 <bitOffset>7</bitOffset>
38355 <bitWidth>1</bitWidth>
38356 </field>
38357 <field>
38358 <name>FB8</name>
38359 <description>Filter bits</description>
38360 <bitOffset>8</bitOffset>
38361 <bitWidth>1</bitWidth>
38362 </field>
38363 <field>
38364 <name>FB9</name>
38365 <description>Filter bits</description>
38366 <bitOffset>9</bitOffset>
38367 <bitWidth>1</bitWidth>
38368 </field>
38369 <field>
38370 <name>FB10</name>
38371 <description>Filter bits</description>
38372 <bitOffset>10</bitOffset>
38373 <bitWidth>1</bitWidth>
38374 </field>
38375 <field>
38376 <name>FB11</name>
38377 <description>Filter bits</description>
38378 <bitOffset>11</bitOffset>
38379 <bitWidth>1</bitWidth>
38380 </field>
38381 <field>
38382 <name>FB12</name>
38383 <description>Filter bits</description>
38384 <bitOffset>12</bitOffset>
38385 <bitWidth>1</bitWidth>
38386 </field>
38387 <field>
38388 <name>FB13</name>
38389 <description>Filter bits</description>
38390 <bitOffset>13</bitOffset>
38391 <bitWidth>1</bitWidth>
38392 </field>
38393 <field>
38394 <name>FB14</name>
38395 <description>Filter bits</description>
38396 <bitOffset>14</bitOffset>
38397 <bitWidth>1</bitWidth>
38398 </field>
38399 <field>
38400 <name>FB15</name>
38401 <description>Filter bits</description>
38402 <bitOffset>15</bitOffset>
38403 <bitWidth>1</bitWidth>
38404 </field>
38405 <field>
38406 <name>FB16</name>
38407 <description>Filter bits</description>
38408 <bitOffset>16</bitOffset>
38409 <bitWidth>1</bitWidth>
38410 </field>
38411 <field>
38412 <name>FB17</name>
38413 <description>Filter bits</description>
38414 <bitOffset>17</bitOffset>
38415 <bitWidth>1</bitWidth>
38416 </field>
38417 <field>
38418 <name>FB18</name>
38419 <description>Filter bits</description>
38420 <bitOffset>18</bitOffset>
38421 <bitWidth>1</bitWidth>
38422 </field>
38423 <field>
38424 <name>FB19</name>
38425 <description>Filter bits</description>
38426 <bitOffset>19</bitOffset>
38427 <bitWidth>1</bitWidth>
38428 </field>
38429 <field>
38430 <name>FB20</name>
38431 <description>Filter bits</description>
38432 <bitOffset>20</bitOffset>
38433 <bitWidth>1</bitWidth>
38434 </field>
38435 <field>
38436 <name>FB21</name>
38437 <description>Filter bits</description>
38438 <bitOffset>21</bitOffset>
38439 <bitWidth>1</bitWidth>
38440 </field>
38441 <field>
38442 <name>FB22</name>
38443 <description>Filter bits</description>
38444 <bitOffset>22</bitOffset>
38445 <bitWidth>1</bitWidth>
38446 </field>
38447 <field>
38448 <name>FB23</name>
38449 <description>Filter bits</description>
38450 <bitOffset>23</bitOffset>
38451 <bitWidth>1</bitWidth>
38452 </field>
38453 <field>
38454 <name>FB24</name>
38455 <description>Filter bits</description>
38456 <bitOffset>24</bitOffset>
38457 <bitWidth>1</bitWidth>
38458 </field>
38459 <field>
38460 <name>FB25</name>
38461 <description>Filter bits</description>
38462 <bitOffset>25</bitOffset>
38463 <bitWidth>1</bitWidth>
38464 </field>
38465 <field>
38466 <name>FB26</name>
38467 <description>Filter bits</description>
38468 <bitOffset>26</bitOffset>
38469 <bitWidth>1</bitWidth>
38470 </field>
38471 <field>
38472 <name>FB27</name>
38473 <description>Filter bits</description>
38474 <bitOffset>27</bitOffset>
38475 <bitWidth>1</bitWidth>
38476 </field>
38477 <field>
38478 <name>FB28</name>
38479 <description>Filter bits</description>
38480 <bitOffset>28</bitOffset>
38481 <bitWidth>1</bitWidth>
38482 </field>
38483 <field>
38484 <name>FB29</name>
38485 <description>Filter bits</description>
38486 <bitOffset>29</bitOffset>
38487 <bitWidth>1</bitWidth>
38488 </field>
38489 <field>
38490 <name>FB30</name>
38491 <description>Filter bits</description>
38492 <bitOffset>30</bitOffset>
38493 <bitWidth>1</bitWidth>
38494 </field>
38495 <field>
38496 <name>FB31</name>
38497 <description>Filter bits</description>
38498 <bitOffset>31</bitOffset>
38499 <bitWidth>1</bitWidth>
38500 </field>
38501 </fields>
38502 </register>
38503 <register>
38504 <name>F24R2</name>
38505 <displayName>F24R2</displayName>
38506 <description>Filter bank 24 register 2</description>
38507 <addressOffset>0x304</addressOffset>
38508 <size>0x20</size>
38509 <access>read-write</access>
38510 <resetValue>0x00000000</resetValue>
38511 <fields>
38512 <field>
38513 <name>FB0</name>
38514 <description>Filter bits</description>
38515 <bitOffset>0</bitOffset>
38516 <bitWidth>1</bitWidth>
38517 </field>
38518 <field>
38519 <name>FB1</name>
38520 <description>Filter bits</description>
38521 <bitOffset>1</bitOffset>
38522 <bitWidth>1</bitWidth>
38523 </field>
38524 <field>
38525 <name>FB2</name>
38526 <description>Filter bits</description>
38527 <bitOffset>2</bitOffset>
38528 <bitWidth>1</bitWidth>
38529 </field>
38530 <field>
38531 <name>FB3</name>
38532 <description>Filter bits</description>
38533 <bitOffset>3</bitOffset>
38534 <bitWidth>1</bitWidth>
38535 </field>
38536 <field>
38537 <name>FB4</name>
38538 <description>Filter bits</description>
38539 <bitOffset>4</bitOffset>
38540 <bitWidth>1</bitWidth>
38541 </field>
38542 <field>
38543 <name>FB5</name>
38544 <description>Filter bits</description>
38545 <bitOffset>5</bitOffset>
38546 <bitWidth>1</bitWidth>
38547 </field>
38548 <field>
38549 <name>FB6</name>
38550 <description>Filter bits</description>
38551 <bitOffset>6</bitOffset>
38552 <bitWidth>1</bitWidth>
38553 </field>
38554 <field>
38555 <name>FB7</name>
38556 <description>Filter bits</description>
38557 <bitOffset>7</bitOffset>
38558 <bitWidth>1</bitWidth>
38559 </field>
38560 <field>
38561 <name>FB8</name>
38562 <description>Filter bits</description>
38563 <bitOffset>8</bitOffset>
38564 <bitWidth>1</bitWidth>
38565 </field>
38566 <field>
38567 <name>FB9</name>
38568 <description>Filter bits</description>
38569 <bitOffset>9</bitOffset>
38570 <bitWidth>1</bitWidth>
38571 </field>
38572 <field>
38573 <name>FB10</name>
38574 <description>Filter bits</description>
38575 <bitOffset>10</bitOffset>
38576 <bitWidth>1</bitWidth>
38577 </field>
38578 <field>
38579 <name>FB11</name>
38580 <description>Filter bits</description>
38581 <bitOffset>11</bitOffset>
38582 <bitWidth>1</bitWidth>
38583 </field>
38584 <field>
38585 <name>FB12</name>
38586 <description>Filter bits</description>
38587 <bitOffset>12</bitOffset>
38588 <bitWidth>1</bitWidth>
38589 </field>
38590 <field>
38591 <name>FB13</name>
38592 <description>Filter bits</description>
38593 <bitOffset>13</bitOffset>
38594 <bitWidth>1</bitWidth>
38595 </field>
38596 <field>
38597 <name>FB14</name>
38598 <description>Filter bits</description>
38599 <bitOffset>14</bitOffset>
38600 <bitWidth>1</bitWidth>
38601 </field>
38602 <field>
38603 <name>FB15</name>
38604 <description>Filter bits</description>
38605 <bitOffset>15</bitOffset>
38606 <bitWidth>1</bitWidth>
38607 </field>
38608 <field>
38609 <name>FB16</name>
38610 <description>Filter bits</description>
38611 <bitOffset>16</bitOffset>
38612 <bitWidth>1</bitWidth>
38613 </field>
38614 <field>
38615 <name>FB17</name>
38616 <description>Filter bits</description>
38617 <bitOffset>17</bitOffset>
38618 <bitWidth>1</bitWidth>
38619 </field>
38620 <field>
38621 <name>FB18</name>
38622 <description>Filter bits</description>
38623 <bitOffset>18</bitOffset>
38624 <bitWidth>1</bitWidth>
38625 </field>
38626 <field>
38627 <name>FB19</name>
38628 <description>Filter bits</description>
38629 <bitOffset>19</bitOffset>
38630 <bitWidth>1</bitWidth>
38631 </field>
38632 <field>
38633 <name>FB20</name>
38634 <description>Filter bits</description>
38635 <bitOffset>20</bitOffset>
38636 <bitWidth>1</bitWidth>
38637 </field>
38638 <field>
38639 <name>FB21</name>
38640 <description>Filter bits</description>
38641 <bitOffset>21</bitOffset>
38642 <bitWidth>1</bitWidth>
38643 </field>
38644 <field>
38645 <name>FB22</name>
38646 <description>Filter bits</description>
38647 <bitOffset>22</bitOffset>
38648 <bitWidth>1</bitWidth>
38649 </field>
38650 <field>
38651 <name>FB23</name>
38652 <description>Filter bits</description>
38653 <bitOffset>23</bitOffset>
38654 <bitWidth>1</bitWidth>
38655 </field>
38656 <field>
38657 <name>FB24</name>
38658 <description>Filter bits</description>
38659 <bitOffset>24</bitOffset>
38660 <bitWidth>1</bitWidth>
38661 </field>
38662 <field>
38663 <name>FB25</name>
38664 <description>Filter bits</description>
38665 <bitOffset>25</bitOffset>
38666 <bitWidth>1</bitWidth>
38667 </field>
38668 <field>
38669 <name>FB26</name>
38670 <description>Filter bits</description>
38671 <bitOffset>26</bitOffset>
38672 <bitWidth>1</bitWidth>
38673 </field>
38674 <field>
38675 <name>FB27</name>
38676 <description>Filter bits</description>
38677 <bitOffset>27</bitOffset>
38678 <bitWidth>1</bitWidth>
38679 </field>
38680 <field>
38681 <name>FB28</name>
38682 <description>Filter bits</description>
38683 <bitOffset>28</bitOffset>
38684 <bitWidth>1</bitWidth>
38685 </field>
38686 <field>
38687 <name>FB29</name>
38688 <description>Filter bits</description>
38689 <bitOffset>29</bitOffset>
38690 <bitWidth>1</bitWidth>
38691 </field>
38692 <field>
38693 <name>FB30</name>
38694 <description>Filter bits</description>
38695 <bitOffset>30</bitOffset>
38696 <bitWidth>1</bitWidth>
38697 </field>
38698 <field>
38699 <name>FB31</name>
38700 <description>Filter bits</description>
38701 <bitOffset>31</bitOffset>
38702 <bitWidth>1</bitWidth>
38703 </field>
38704 </fields>
38705 </register>
38706 <register>
38707 <name>F25R1</name>
38708 <displayName>F25R1</displayName>
38709 <description>Filter bank 25 register 1</description>
38710 <addressOffset>0x308</addressOffset>
38711 <size>0x20</size>
38712 <access>read-write</access>
38713 <resetValue>0x00000000</resetValue>
38714 <fields>
38715 <field>
38716 <name>FB0</name>
38717 <description>Filter bits</description>
38718 <bitOffset>0</bitOffset>
38719 <bitWidth>1</bitWidth>
38720 </field>
38721 <field>
38722 <name>FB1</name>
38723 <description>Filter bits</description>
38724 <bitOffset>1</bitOffset>
38725 <bitWidth>1</bitWidth>
38726 </field>
38727 <field>
38728 <name>FB2</name>
38729 <description>Filter bits</description>
38730 <bitOffset>2</bitOffset>
38731 <bitWidth>1</bitWidth>
38732 </field>
38733 <field>
38734 <name>FB3</name>
38735 <description>Filter bits</description>
38736 <bitOffset>3</bitOffset>
38737 <bitWidth>1</bitWidth>
38738 </field>
38739 <field>
38740 <name>FB4</name>
38741 <description>Filter bits</description>
38742 <bitOffset>4</bitOffset>
38743 <bitWidth>1</bitWidth>
38744 </field>
38745 <field>
38746 <name>FB5</name>
38747 <description>Filter bits</description>
38748 <bitOffset>5</bitOffset>
38749 <bitWidth>1</bitWidth>
38750 </field>
38751 <field>
38752 <name>FB6</name>
38753 <description>Filter bits</description>
38754 <bitOffset>6</bitOffset>
38755 <bitWidth>1</bitWidth>
38756 </field>
38757 <field>
38758 <name>FB7</name>
38759 <description>Filter bits</description>
38760 <bitOffset>7</bitOffset>
38761 <bitWidth>1</bitWidth>
38762 </field>
38763 <field>
38764 <name>FB8</name>
38765 <description>Filter bits</description>
38766 <bitOffset>8</bitOffset>
38767 <bitWidth>1</bitWidth>
38768 </field>
38769 <field>
38770 <name>FB9</name>
38771 <description>Filter bits</description>
38772 <bitOffset>9</bitOffset>
38773 <bitWidth>1</bitWidth>
38774 </field>
38775 <field>
38776 <name>FB10</name>
38777 <description>Filter bits</description>
38778 <bitOffset>10</bitOffset>
38779 <bitWidth>1</bitWidth>
38780 </field>
38781 <field>
38782 <name>FB11</name>
38783 <description>Filter bits</description>
38784 <bitOffset>11</bitOffset>
38785 <bitWidth>1</bitWidth>
38786 </field>
38787 <field>
38788 <name>FB12</name>
38789 <description>Filter bits</description>
38790 <bitOffset>12</bitOffset>
38791 <bitWidth>1</bitWidth>
38792 </field>
38793 <field>
38794 <name>FB13</name>
38795 <description>Filter bits</description>
38796 <bitOffset>13</bitOffset>
38797 <bitWidth>1</bitWidth>
38798 </field>
38799 <field>
38800 <name>FB14</name>
38801 <description>Filter bits</description>
38802 <bitOffset>14</bitOffset>
38803 <bitWidth>1</bitWidth>
38804 </field>
38805 <field>
38806 <name>FB15</name>
38807 <description>Filter bits</description>
38808 <bitOffset>15</bitOffset>
38809 <bitWidth>1</bitWidth>
38810 </field>
38811 <field>
38812 <name>FB16</name>
38813 <description>Filter bits</description>
38814 <bitOffset>16</bitOffset>
38815 <bitWidth>1</bitWidth>
38816 </field>
38817 <field>
38818 <name>FB17</name>
38819 <description>Filter bits</description>
38820 <bitOffset>17</bitOffset>
38821 <bitWidth>1</bitWidth>
38822 </field>
38823 <field>
38824 <name>FB18</name>
38825 <description>Filter bits</description>
38826 <bitOffset>18</bitOffset>
38827 <bitWidth>1</bitWidth>
38828 </field>
38829 <field>
38830 <name>FB19</name>
38831 <description>Filter bits</description>
38832 <bitOffset>19</bitOffset>
38833 <bitWidth>1</bitWidth>
38834 </field>
38835 <field>
38836 <name>FB20</name>
38837 <description>Filter bits</description>
38838 <bitOffset>20</bitOffset>
38839 <bitWidth>1</bitWidth>
38840 </field>
38841 <field>
38842 <name>FB21</name>
38843 <description>Filter bits</description>
38844 <bitOffset>21</bitOffset>
38845 <bitWidth>1</bitWidth>
38846 </field>
38847 <field>
38848 <name>FB22</name>
38849 <description>Filter bits</description>
38850 <bitOffset>22</bitOffset>
38851 <bitWidth>1</bitWidth>
38852 </field>
38853 <field>
38854 <name>FB23</name>
38855 <description>Filter bits</description>
38856 <bitOffset>23</bitOffset>
38857 <bitWidth>1</bitWidth>
38858 </field>
38859 <field>
38860 <name>FB24</name>
38861 <description>Filter bits</description>
38862 <bitOffset>24</bitOffset>
38863 <bitWidth>1</bitWidth>
38864 </field>
38865 <field>
38866 <name>FB25</name>
38867 <description>Filter bits</description>
38868 <bitOffset>25</bitOffset>
38869 <bitWidth>1</bitWidth>
38870 </field>
38871 <field>
38872 <name>FB26</name>
38873 <description>Filter bits</description>
38874 <bitOffset>26</bitOffset>
38875 <bitWidth>1</bitWidth>
38876 </field>
38877 <field>
38878 <name>FB27</name>
38879 <description>Filter bits</description>
38880 <bitOffset>27</bitOffset>
38881 <bitWidth>1</bitWidth>
38882 </field>
38883 <field>
38884 <name>FB28</name>
38885 <description>Filter bits</description>
38886 <bitOffset>28</bitOffset>
38887 <bitWidth>1</bitWidth>
38888 </field>
38889 <field>
38890 <name>FB29</name>
38891 <description>Filter bits</description>
38892 <bitOffset>29</bitOffset>
38893 <bitWidth>1</bitWidth>
38894 </field>
38895 <field>
38896 <name>FB30</name>
38897 <description>Filter bits</description>
38898 <bitOffset>30</bitOffset>
38899 <bitWidth>1</bitWidth>
38900 </field>
38901 <field>
38902 <name>FB31</name>
38903 <description>Filter bits</description>
38904 <bitOffset>31</bitOffset>
38905 <bitWidth>1</bitWidth>
38906 </field>
38907 </fields>
38908 </register>
38909 <register>
38910 <name>F25R2</name>
38911 <displayName>F25R2</displayName>
38912 <description>Filter bank 25 register 2</description>
38913 <addressOffset>0x30C</addressOffset>
38914 <size>0x20</size>
38915 <access>read-write</access>
38916 <resetValue>0x00000000</resetValue>
38917 <fields>
38918 <field>
38919 <name>FB0</name>
38920 <description>Filter bits</description>
38921 <bitOffset>0</bitOffset>
38922 <bitWidth>1</bitWidth>
38923 </field>
38924 <field>
38925 <name>FB1</name>
38926 <description>Filter bits</description>
38927 <bitOffset>1</bitOffset>
38928 <bitWidth>1</bitWidth>
38929 </field>
38930 <field>
38931 <name>FB2</name>
38932 <description>Filter bits</description>
38933 <bitOffset>2</bitOffset>
38934 <bitWidth>1</bitWidth>
38935 </field>
38936 <field>
38937 <name>FB3</name>
38938 <description>Filter bits</description>
38939 <bitOffset>3</bitOffset>
38940 <bitWidth>1</bitWidth>
38941 </field>
38942 <field>
38943 <name>FB4</name>
38944 <description>Filter bits</description>
38945 <bitOffset>4</bitOffset>
38946 <bitWidth>1</bitWidth>
38947 </field>
38948 <field>
38949 <name>FB5</name>
38950 <description>Filter bits</description>
38951 <bitOffset>5</bitOffset>
38952 <bitWidth>1</bitWidth>
38953 </field>
38954 <field>
38955 <name>FB6</name>
38956 <description>Filter bits</description>
38957 <bitOffset>6</bitOffset>
38958 <bitWidth>1</bitWidth>
38959 </field>
38960 <field>
38961 <name>FB7</name>
38962 <description>Filter bits</description>
38963 <bitOffset>7</bitOffset>
38964 <bitWidth>1</bitWidth>
38965 </field>
38966 <field>
38967 <name>FB8</name>
38968 <description>Filter bits</description>
38969 <bitOffset>8</bitOffset>
38970 <bitWidth>1</bitWidth>
38971 </field>
38972 <field>
38973 <name>FB9</name>
38974 <description>Filter bits</description>
38975 <bitOffset>9</bitOffset>
38976 <bitWidth>1</bitWidth>
38977 </field>
38978 <field>
38979 <name>FB10</name>
38980 <description>Filter bits</description>
38981 <bitOffset>10</bitOffset>
38982 <bitWidth>1</bitWidth>
38983 </field>
38984 <field>
38985 <name>FB11</name>
38986 <description>Filter bits</description>
38987 <bitOffset>11</bitOffset>
38988 <bitWidth>1</bitWidth>
38989 </field>
38990 <field>
38991 <name>FB12</name>
38992 <description>Filter bits</description>
38993 <bitOffset>12</bitOffset>
38994 <bitWidth>1</bitWidth>
38995 </field>
38996 <field>
38997 <name>FB13</name>
38998 <description>Filter bits</description>
38999 <bitOffset>13</bitOffset>
39000 <bitWidth>1</bitWidth>
39001 </field>
39002 <field>
39003 <name>FB14</name>
39004 <description>Filter bits</description>
39005 <bitOffset>14</bitOffset>
39006 <bitWidth>1</bitWidth>
39007 </field>
39008 <field>
39009 <name>FB15</name>
39010 <description>Filter bits</description>
39011 <bitOffset>15</bitOffset>
39012 <bitWidth>1</bitWidth>
39013 </field>
39014 <field>
39015 <name>FB16</name>
39016 <description>Filter bits</description>
39017 <bitOffset>16</bitOffset>
39018 <bitWidth>1</bitWidth>
39019 </field>
39020 <field>
39021 <name>FB17</name>
39022 <description>Filter bits</description>
39023 <bitOffset>17</bitOffset>
39024 <bitWidth>1</bitWidth>
39025 </field>
39026 <field>
39027 <name>FB18</name>
39028 <description>Filter bits</description>
39029 <bitOffset>18</bitOffset>
39030 <bitWidth>1</bitWidth>
39031 </field>
39032 <field>
39033 <name>FB19</name>
39034 <description>Filter bits</description>
39035 <bitOffset>19</bitOffset>
39036 <bitWidth>1</bitWidth>
39037 </field>
39038 <field>
39039 <name>FB20</name>
39040 <description>Filter bits</description>
39041 <bitOffset>20</bitOffset>
39042 <bitWidth>1</bitWidth>
39043 </field>
39044 <field>
39045 <name>FB21</name>
39046 <description>Filter bits</description>
39047 <bitOffset>21</bitOffset>
39048 <bitWidth>1</bitWidth>
39049 </field>
39050 <field>
39051 <name>FB22</name>
39052 <description>Filter bits</description>
39053 <bitOffset>22</bitOffset>
39054 <bitWidth>1</bitWidth>
39055 </field>
39056 <field>
39057 <name>FB23</name>
39058 <description>Filter bits</description>
39059 <bitOffset>23</bitOffset>
39060 <bitWidth>1</bitWidth>
39061 </field>
39062 <field>
39063 <name>FB24</name>
39064 <description>Filter bits</description>
39065 <bitOffset>24</bitOffset>
39066 <bitWidth>1</bitWidth>
39067 </field>
39068 <field>
39069 <name>FB25</name>
39070 <description>Filter bits</description>
39071 <bitOffset>25</bitOffset>
39072 <bitWidth>1</bitWidth>
39073 </field>
39074 <field>
39075 <name>FB26</name>
39076 <description>Filter bits</description>
39077 <bitOffset>26</bitOffset>
39078 <bitWidth>1</bitWidth>
39079 </field>
39080 <field>
39081 <name>FB27</name>
39082 <description>Filter bits</description>
39083 <bitOffset>27</bitOffset>
39084 <bitWidth>1</bitWidth>
39085 </field>
39086 <field>
39087 <name>FB28</name>
39088 <description>Filter bits</description>
39089 <bitOffset>28</bitOffset>
39090 <bitWidth>1</bitWidth>
39091 </field>
39092 <field>
39093 <name>FB29</name>
39094 <description>Filter bits</description>
39095 <bitOffset>29</bitOffset>
39096 <bitWidth>1</bitWidth>
39097 </field>
39098 <field>
39099 <name>FB30</name>
39100 <description>Filter bits</description>
39101 <bitOffset>30</bitOffset>
39102 <bitWidth>1</bitWidth>
39103 </field>
39104 <field>
39105 <name>FB31</name>
39106 <description>Filter bits</description>
39107 <bitOffset>31</bitOffset>
39108 <bitWidth>1</bitWidth>
39109 </field>
39110 </fields>
39111 </register>
39112 <register>
39113 <name>F26R1</name>
39114 <displayName>F26R1</displayName>
39115 <description>Filter bank 26 register 1</description>
39116 <addressOffset>0x310</addressOffset>
39117 <size>0x20</size>
39118 <access>read-write</access>
39119 <resetValue>0x00000000</resetValue>
39120 <fields>
39121 <field>
39122 <name>FB0</name>
39123 <description>Filter bits</description>
39124 <bitOffset>0</bitOffset>
39125 <bitWidth>1</bitWidth>
39126 </field>
39127 <field>
39128 <name>FB1</name>
39129 <description>Filter bits</description>
39130 <bitOffset>1</bitOffset>
39131 <bitWidth>1</bitWidth>
39132 </field>
39133 <field>
39134 <name>FB2</name>
39135 <description>Filter bits</description>
39136 <bitOffset>2</bitOffset>
39137 <bitWidth>1</bitWidth>
39138 </field>
39139 <field>
39140 <name>FB3</name>
39141 <description>Filter bits</description>
39142 <bitOffset>3</bitOffset>
39143 <bitWidth>1</bitWidth>
39144 </field>
39145 <field>
39146 <name>FB4</name>
39147 <description>Filter bits</description>
39148 <bitOffset>4</bitOffset>
39149 <bitWidth>1</bitWidth>
39150 </field>
39151 <field>
39152 <name>FB5</name>
39153 <description>Filter bits</description>
39154 <bitOffset>5</bitOffset>
39155 <bitWidth>1</bitWidth>
39156 </field>
39157 <field>
39158 <name>FB6</name>
39159 <description>Filter bits</description>
39160 <bitOffset>6</bitOffset>
39161 <bitWidth>1</bitWidth>
39162 </field>
39163 <field>
39164 <name>FB7</name>
39165 <description>Filter bits</description>
39166 <bitOffset>7</bitOffset>
39167 <bitWidth>1</bitWidth>
39168 </field>
39169 <field>
39170 <name>FB8</name>
39171 <description>Filter bits</description>
39172 <bitOffset>8</bitOffset>
39173 <bitWidth>1</bitWidth>
39174 </field>
39175 <field>
39176 <name>FB9</name>
39177 <description>Filter bits</description>
39178 <bitOffset>9</bitOffset>
39179 <bitWidth>1</bitWidth>
39180 </field>
39181 <field>
39182 <name>FB10</name>
39183 <description>Filter bits</description>
39184 <bitOffset>10</bitOffset>
39185 <bitWidth>1</bitWidth>
39186 </field>
39187 <field>
39188 <name>FB11</name>
39189 <description>Filter bits</description>
39190 <bitOffset>11</bitOffset>
39191 <bitWidth>1</bitWidth>
39192 </field>
39193 <field>
39194 <name>FB12</name>
39195 <description>Filter bits</description>
39196 <bitOffset>12</bitOffset>
39197 <bitWidth>1</bitWidth>
39198 </field>
39199 <field>
39200 <name>FB13</name>
39201 <description>Filter bits</description>
39202 <bitOffset>13</bitOffset>
39203 <bitWidth>1</bitWidth>
39204 </field>
39205 <field>
39206 <name>FB14</name>
39207 <description>Filter bits</description>
39208 <bitOffset>14</bitOffset>
39209 <bitWidth>1</bitWidth>
39210 </field>
39211 <field>
39212 <name>FB15</name>
39213 <description>Filter bits</description>
39214 <bitOffset>15</bitOffset>
39215 <bitWidth>1</bitWidth>
39216 </field>
39217 <field>
39218 <name>FB16</name>
39219 <description>Filter bits</description>
39220 <bitOffset>16</bitOffset>
39221 <bitWidth>1</bitWidth>
39222 </field>
39223 <field>
39224 <name>FB17</name>
39225 <description>Filter bits</description>
39226 <bitOffset>17</bitOffset>
39227 <bitWidth>1</bitWidth>
39228 </field>
39229 <field>
39230 <name>FB18</name>
39231 <description>Filter bits</description>
39232 <bitOffset>18</bitOffset>
39233 <bitWidth>1</bitWidth>
39234 </field>
39235 <field>
39236 <name>FB19</name>
39237 <description>Filter bits</description>
39238 <bitOffset>19</bitOffset>
39239 <bitWidth>1</bitWidth>
39240 </field>
39241 <field>
39242 <name>FB20</name>
39243 <description>Filter bits</description>
39244 <bitOffset>20</bitOffset>
39245 <bitWidth>1</bitWidth>
39246 </field>
39247 <field>
39248 <name>FB21</name>
39249 <description>Filter bits</description>
39250 <bitOffset>21</bitOffset>
39251 <bitWidth>1</bitWidth>
39252 </field>
39253 <field>
39254 <name>FB22</name>
39255 <description>Filter bits</description>
39256 <bitOffset>22</bitOffset>
39257 <bitWidth>1</bitWidth>
39258 </field>
39259 <field>
39260 <name>FB23</name>
39261 <description>Filter bits</description>
39262 <bitOffset>23</bitOffset>
39263 <bitWidth>1</bitWidth>
39264 </field>
39265 <field>
39266 <name>FB24</name>
39267 <description>Filter bits</description>
39268 <bitOffset>24</bitOffset>
39269 <bitWidth>1</bitWidth>
39270 </field>
39271 <field>
39272 <name>FB25</name>
39273 <description>Filter bits</description>
39274 <bitOffset>25</bitOffset>
39275 <bitWidth>1</bitWidth>
39276 </field>
39277 <field>
39278 <name>FB26</name>
39279 <description>Filter bits</description>
39280 <bitOffset>26</bitOffset>
39281 <bitWidth>1</bitWidth>
39282 </field>
39283 <field>
39284 <name>FB27</name>
39285 <description>Filter bits</description>
39286 <bitOffset>27</bitOffset>
39287 <bitWidth>1</bitWidth>
39288 </field>
39289 <field>
39290 <name>FB28</name>
39291 <description>Filter bits</description>
39292 <bitOffset>28</bitOffset>
39293 <bitWidth>1</bitWidth>
39294 </field>
39295 <field>
39296 <name>FB29</name>
39297 <description>Filter bits</description>
39298 <bitOffset>29</bitOffset>
39299 <bitWidth>1</bitWidth>
39300 </field>
39301 <field>
39302 <name>FB30</name>
39303 <description>Filter bits</description>
39304 <bitOffset>30</bitOffset>
39305 <bitWidth>1</bitWidth>
39306 </field>
39307 <field>
39308 <name>FB31</name>
39309 <description>Filter bits</description>
39310 <bitOffset>31</bitOffset>
39311 <bitWidth>1</bitWidth>
39312 </field>
39313 </fields>
39314 </register>
39315 <register>
39316 <name>F26R2</name>
39317 <displayName>F26R2</displayName>
39318 <description>Filter bank 26 register 2</description>
39319 <addressOffset>0x314</addressOffset>
39320 <size>0x20</size>
39321 <access>read-write</access>
39322 <resetValue>0x00000000</resetValue>
39323 <fields>
39324 <field>
39325 <name>FB0</name>
39326 <description>Filter bits</description>
39327 <bitOffset>0</bitOffset>
39328 <bitWidth>1</bitWidth>
39329 </field>
39330 <field>
39331 <name>FB1</name>
39332 <description>Filter bits</description>
39333 <bitOffset>1</bitOffset>
39334 <bitWidth>1</bitWidth>
39335 </field>
39336 <field>
39337 <name>FB2</name>
39338 <description>Filter bits</description>
39339 <bitOffset>2</bitOffset>
39340 <bitWidth>1</bitWidth>
39341 </field>
39342 <field>
39343 <name>FB3</name>
39344 <description>Filter bits</description>
39345 <bitOffset>3</bitOffset>
39346 <bitWidth>1</bitWidth>
39347 </field>
39348 <field>
39349 <name>FB4</name>
39350 <description>Filter bits</description>
39351 <bitOffset>4</bitOffset>
39352 <bitWidth>1</bitWidth>
39353 </field>
39354 <field>
39355 <name>FB5</name>
39356 <description>Filter bits</description>
39357 <bitOffset>5</bitOffset>
39358 <bitWidth>1</bitWidth>
39359 </field>
39360 <field>
39361 <name>FB6</name>
39362 <description>Filter bits</description>
39363 <bitOffset>6</bitOffset>
39364 <bitWidth>1</bitWidth>
39365 </field>
39366 <field>
39367 <name>FB7</name>
39368 <description>Filter bits</description>
39369 <bitOffset>7</bitOffset>
39370 <bitWidth>1</bitWidth>
39371 </field>
39372 <field>
39373 <name>FB8</name>
39374 <description>Filter bits</description>
39375 <bitOffset>8</bitOffset>
39376 <bitWidth>1</bitWidth>
39377 </field>
39378 <field>
39379 <name>FB9</name>
39380 <description>Filter bits</description>
39381 <bitOffset>9</bitOffset>
39382 <bitWidth>1</bitWidth>
39383 </field>
39384 <field>
39385 <name>FB10</name>
39386 <description>Filter bits</description>
39387 <bitOffset>10</bitOffset>
39388 <bitWidth>1</bitWidth>
39389 </field>
39390 <field>
39391 <name>FB11</name>
39392 <description>Filter bits</description>
39393 <bitOffset>11</bitOffset>
39394 <bitWidth>1</bitWidth>
39395 </field>
39396 <field>
39397 <name>FB12</name>
39398 <description>Filter bits</description>
39399 <bitOffset>12</bitOffset>
39400 <bitWidth>1</bitWidth>
39401 </field>
39402 <field>
39403 <name>FB13</name>
39404 <description>Filter bits</description>
39405 <bitOffset>13</bitOffset>
39406 <bitWidth>1</bitWidth>
39407 </field>
39408 <field>
39409 <name>FB14</name>
39410 <description>Filter bits</description>
39411 <bitOffset>14</bitOffset>
39412 <bitWidth>1</bitWidth>
39413 </field>
39414 <field>
39415 <name>FB15</name>
39416 <description>Filter bits</description>
39417 <bitOffset>15</bitOffset>
39418 <bitWidth>1</bitWidth>
39419 </field>
39420 <field>
39421 <name>FB16</name>
39422 <description>Filter bits</description>
39423 <bitOffset>16</bitOffset>
39424 <bitWidth>1</bitWidth>
39425 </field>
39426 <field>
39427 <name>FB17</name>
39428 <description>Filter bits</description>
39429 <bitOffset>17</bitOffset>
39430 <bitWidth>1</bitWidth>
39431 </field>
39432 <field>
39433 <name>FB18</name>
39434 <description>Filter bits</description>
39435 <bitOffset>18</bitOffset>
39436 <bitWidth>1</bitWidth>
39437 </field>
39438 <field>
39439 <name>FB19</name>
39440 <description>Filter bits</description>
39441 <bitOffset>19</bitOffset>
39442 <bitWidth>1</bitWidth>
39443 </field>
39444 <field>
39445 <name>FB20</name>
39446 <description>Filter bits</description>
39447 <bitOffset>20</bitOffset>
39448 <bitWidth>1</bitWidth>
39449 </field>
39450 <field>
39451 <name>FB21</name>
39452 <description>Filter bits</description>
39453 <bitOffset>21</bitOffset>
39454 <bitWidth>1</bitWidth>
39455 </field>
39456 <field>
39457 <name>FB22</name>
39458 <description>Filter bits</description>
39459 <bitOffset>22</bitOffset>
39460 <bitWidth>1</bitWidth>
39461 </field>
39462 <field>
39463 <name>FB23</name>
39464 <description>Filter bits</description>
39465 <bitOffset>23</bitOffset>
39466 <bitWidth>1</bitWidth>
39467 </field>
39468 <field>
39469 <name>FB24</name>
39470 <description>Filter bits</description>
39471 <bitOffset>24</bitOffset>
39472 <bitWidth>1</bitWidth>
39473 </field>
39474 <field>
39475 <name>FB25</name>
39476 <description>Filter bits</description>
39477 <bitOffset>25</bitOffset>
39478 <bitWidth>1</bitWidth>
39479 </field>
39480 <field>
39481 <name>FB26</name>
39482 <description>Filter bits</description>
39483 <bitOffset>26</bitOffset>
39484 <bitWidth>1</bitWidth>
39485 </field>
39486 <field>
39487 <name>FB27</name>
39488 <description>Filter bits</description>
39489 <bitOffset>27</bitOffset>
39490 <bitWidth>1</bitWidth>
39491 </field>
39492 <field>
39493 <name>FB28</name>
39494 <description>Filter bits</description>
39495 <bitOffset>28</bitOffset>
39496 <bitWidth>1</bitWidth>
39497 </field>
39498 <field>
39499 <name>FB29</name>
39500 <description>Filter bits</description>
39501 <bitOffset>29</bitOffset>
39502 <bitWidth>1</bitWidth>
39503 </field>
39504 <field>
39505 <name>FB30</name>
39506 <description>Filter bits</description>
39507 <bitOffset>30</bitOffset>
39508 <bitWidth>1</bitWidth>
39509 </field>
39510 <field>
39511 <name>FB31</name>
39512 <description>Filter bits</description>
39513 <bitOffset>31</bitOffset>
39514 <bitWidth>1</bitWidth>
39515 </field>
39516 </fields>
39517 </register>
39518 <register>
39519 <name>F27R1</name>
39520 <displayName>F27R1</displayName>
39521 <description>Filter bank 27 register 1</description>
39522 <addressOffset>0x318</addressOffset>
39523 <size>0x20</size>
39524 <access>read-write</access>
39525 <resetValue>0x00000000</resetValue>
39526 <fields>
39527 <field>
39528 <name>FB0</name>
39529 <description>Filter bits</description>
39530 <bitOffset>0</bitOffset>
39531 <bitWidth>1</bitWidth>
39532 </field>
39533 <field>
39534 <name>FB1</name>
39535 <description>Filter bits</description>
39536 <bitOffset>1</bitOffset>
39537 <bitWidth>1</bitWidth>
39538 </field>
39539 <field>
39540 <name>FB2</name>
39541 <description>Filter bits</description>
39542 <bitOffset>2</bitOffset>
39543 <bitWidth>1</bitWidth>
39544 </field>
39545 <field>
39546 <name>FB3</name>
39547 <description>Filter bits</description>
39548 <bitOffset>3</bitOffset>
39549 <bitWidth>1</bitWidth>
39550 </field>
39551 <field>
39552 <name>FB4</name>
39553 <description>Filter bits</description>
39554 <bitOffset>4</bitOffset>
39555 <bitWidth>1</bitWidth>
39556 </field>
39557 <field>
39558 <name>FB5</name>
39559 <description>Filter bits</description>
39560 <bitOffset>5</bitOffset>
39561 <bitWidth>1</bitWidth>
39562 </field>
39563 <field>
39564 <name>FB6</name>
39565 <description>Filter bits</description>
39566 <bitOffset>6</bitOffset>
39567 <bitWidth>1</bitWidth>
39568 </field>
39569 <field>
39570 <name>FB7</name>
39571 <description>Filter bits</description>
39572 <bitOffset>7</bitOffset>
39573 <bitWidth>1</bitWidth>
39574 </field>
39575 <field>
39576 <name>FB8</name>
39577 <description>Filter bits</description>
39578 <bitOffset>8</bitOffset>
39579 <bitWidth>1</bitWidth>
39580 </field>
39581 <field>
39582 <name>FB9</name>
39583 <description>Filter bits</description>
39584 <bitOffset>9</bitOffset>
39585 <bitWidth>1</bitWidth>
39586 </field>
39587 <field>
39588 <name>FB10</name>
39589 <description>Filter bits</description>
39590 <bitOffset>10</bitOffset>
39591 <bitWidth>1</bitWidth>
39592 </field>
39593 <field>
39594 <name>FB11</name>
39595 <description>Filter bits</description>
39596 <bitOffset>11</bitOffset>
39597 <bitWidth>1</bitWidth>
39598 </field>
39599 <field>
39600 <name>FB12</name>
39601 <description>Filter bits</description>
39602 <bitOffset>12</bitOffset>
39603 <bitWidth>1</bitWidth>
39604 </field>
39605 <field>
39606 <name>FB13</name>
39607 <description>Filter bits</description>
39608 <bitOffset>13</bitOffset>
39609 <bitWidth>1</bitWidth>
39610 </field>
39611 <field>
39612 <name>FB14</name>
39613 <description>Filter bits</description>
39614 <bitOffset>14</bitOffset>
39615 <bitWidth>1</bitWidth>
39616 </field>
39617 <field>
39618 <name>FB15</name>
39619 <description>Filter bits</description>
39620 <bitOffset>15</bitOffset>
39621 <bitWidth>1</bitWidth>
39622 </field>
39623 <field>
39624 <name>FB16</name>
39625 <description>Filter bits</description>
39626 <bitOffset>16</bitOffset>
39627 <bitWidth>1</bitWidth>
39628 </field>
39629 <field>
39630 <name>FB17</name>
39631 <description>Filter bits</description>
39632 <bitOffset>17</bitOffset>
39633 <bitWidth>1</bitWidth>
39634 </field>
39635 <field>
39636 <name>FB18</name>
39637 <description>Filter bits</description>
39638 <bitOffset>18</bitOffset>
39639 <bitWidth>1</bitWidth>
39640 </field>
39641 <field>
39642 <name>FB19</name>
39643 <description>Filter bits</description>
39644 <bitOffset>19</bitOffset>
39645 <bitWidth>1</bitWidth>
39646 </field>
39647 <field>
39648 <name>FB20</name>
39649 <description>Filter bits</description>
39650 <bitOffset>20</bitOffset>
39651 <bitWidth>1</bitWidth>
39652 </field>
39653 <field>
39654 <name>FB21</name>
39655 <description>Filter bits</description>
39656 <bitOffset>21</bitOffset>
39657 <bitWidth>1</bitWidth>
39658 </field>
39659 <field>
39660 <name>FB22</name>
39661 <description>Filter bits</description>
39662 <bitOffset>22</bitOffset>
39663 <bitWidth>1</bitWidth>
39664 </field>
39665 <field>
39666 <name>FB23</name>
39667 <description>Filter bits</description>
39668 <bitOffset>23</bitOffset>
39669 <bitWidth>1</bitWidth>
39670 </field>
39671 <field>
39672 <name>FB24</name>
39673 <description>Filter bits</description>
39674 <bitOffset>24</bitOffset>
39675 <bitWidth>1</bitWidth>
39676 </field>
39677 <field>
39678 <name>FB25</name>
39679 <description>Filter bits</description>
39680 <bitOffset>25</bitOffset>
39681 <bitWidth>1</bitWidth>
39682 </field>
39683 <field>
39684 <name>FB26</name>
39685 <description>Filter bits</description>
39686 <bitOffset>26</bitOffset>
39687 <bitWidth>1</bitWidth>
39688 </field>
39689 <field>
39690 <name>FB27</name>
39691 <description>Filter bits</description>
39692 <bitOffset>27</bitOffset>
39693 <bitWidth>1</bitWidth>
39694 </field>
39695 <field>
39696 <name>FB28</name>
39697 <description>Filter bits</description>
39698 <bitOffset>28</bitOffset>
39699 <bitWidth>1</bitWidth>
39700 </field>
39701 <field>
39702 <name>FB29</name>
39703 <description>Filter bits</description>
39704 <bitOffset>29</bitOffset>
39705 <bitWidth>1</bitWidth>
39706 </field>
39707 <field>
39708 <name>FB30</name>
39709 <description>Filter bits</description>
39710 <bitOffset>30</bitOffset>
39711 <bitWidth>1</bitWidth>
39712 </field>
39713 <field>
39714 <name>FB31</name>
39715 <description>Filter bits</description>
39716 <bitOffset>31</bitOffset>
39717 <bitWidth>1</bitWidth>
39718 </field>
39719 </fields>
39720 </register>
39721 <register>
39722 <name>F27R2</name>
39723 <displayName>F27R2</displayName>
39724 <description>Filter bank 27 register 2</description>
39725 <addressOffset>0x31C</addressOffset>
39726 <size>0x20</size>
39727 <access>read-write</access>
39728 <resetValue>0x00000000</resetValue>
39729 <fields>
39730 <field>
39731 <name>FB0</name>
39732 <description>Filter bits</description>
39733 <bitOffset>0</bitOffset>
39734 <bitWidth>1</bitWidth>
39735 </field>
39736 <field>
39737 <name>FB1</name>
39738 <description>Filter bits</description>
39739 <bitOffset>1</bitOffset>
39740 <bitWidth>1</bitWidth>
39741 </field>
39742 <field>
39743 <name>FB2</name>
39744 <description>Filter bits</description>
39745 <bitOffset>2</bitOffset>
39746 <bitWidth>1</bitWidth>
39747 </field>
39748 <field>
39749 <name>FB3</name>
39750 <description>Filter bits</description>
39751 <bitOffset>3</bitOffset>
39752 <bitWidth>1</bitWidth>
39753 </field>
39754 <field>
39755 <name>FB4</name>
39756 <description>Filter bits</description>
39757 <bitOffset>4</bitOffset>
39758 <bitWidth>1</bitWidth>
39759 </field>
39760 <field>
39761 <name>FB5</name>
39762 <description>Filter bits</description>
39763 <bitOffset>5</bitOffset>
39764 <bitWidth>1</bitWidth>
39765 </field>
39766 <field>
39767 <name>FB6</name>
39768 <description>Filter bits</description>
39769 <bitOffset>6</bitOffset>
39770 <bitWidth>1</bitWidth>
39771 </field>
39772 <field>
39773 <name>FB7</name>
39774 <description>Filter bits</description>
39775 <bitOffset>7</bitOffset>
39776 <bitWidth>1</bitWidth>
39777 </field>
39778 <field>
39779 <name>FB8</name>
39780 <description>Filter bits</description>
39781 <bitOffset>8</bitOffset>
39782 <bitWidth>1</bitWidth>
39783 </field>
39784 <field>
39785 <name>FB9</name>
39786 <description>Filter bits</description>
39787 <bitOffset>9</bitOffset>
39788 <bitWidth>1</bitWidth>
39789 </field>
39790 <field>
39791 <name>FB10</name>
39792 <description>Filter bits</description>
39793 <bitOffset>10</bitOffset>
39794 <bitWidth>1</bitWidth>
39795 </field>
39796 <field>
39797 <name>FB11</name>
39798 <description>Filter bits</description>
39799 <bitOffset>11</bitOffset>
39800 <bitWidth>1</bitWidth>
39801 </field>
39802 <field>
39803 <name>FB12</name>
39804 <description>Filter bits</description>
39805 <bitOffset>12</bitOffset>
39806 <bitWidth>1</bitWidth>
39807 </field>
39808 <field>
39809 <name>FB13</name>
39810 <description>Filter bits</description>
39811 <bitOffset>13</bitOffset>
39812 <bitWidth>1</bitWidth>
39813 </field>
39814 <field>
39815 <name>FB14</name>
39816 <description>Filter bits</description>
39817 <bitOffset>14</bitOffset>
39818 <bitWidth>1</bitWidth>
39819 </field>
39820 <field>
39821 <name>FB15</name>
39822 <description>Filter bits</description>
39823 <bitOffset>15</bitOffset>
39824 <bitWidth>1</bitWidth>
39825 </field>
39826 <field>
39827 <name>FB16</name>
39828 <description>Filter bits</description>
39829 <bitOffset>16</bitOffset>
39830 <bitWidth>1</bitWidth>
39831 </field>
39832 <field>
39833 <name>FB17</name>
39834 <description>Filter bits</description>
39835 <bitOffset>17</bitOffset>
39836 <bitWidth>1</bitWidth>
39837 </field>
39838 <field>
39839 <name>FB18</name>
39840 <description>Filter bits</description>
39841 <bitOffset>18</bitOffset>
39842 <bitWidth>1</bitWidth>
39843 </field>
39844 <field>
39845 <name>FB19</name>
39846 <description>Filter bits</description>
39847 <bitOffset>19</bitOffset>
39848 <bitWidth>1</bitWidth>
39849 </field>
39850 <field>
39851 <name>FB20</name>
39852 <description>Filter bits</description>
39853 <bitOffset>20</bitOffset>
39854 <bitWidth>1</bitWidth>
39855 </field>
39856 <field>
39857 <name>FB21</name>
39858 <description>Filter bits</description>
39859 <bitOffset>21</bitOffset>
39860 <bitWidth>1</bitWidth>
39861 </field>
39862 <field>
39863 <name>FB22</name>
39864 <description>Filter bits</description>
39865 <bitOffset>22</bitOffset>
39866 <bitWidth>1</bitWidth>
39867 </field>
39868 <field>
39869 <name>FB23</name>
39870 <description>Filter bits</description>
39871 <bitOffset>23</bitOffset>
39872 <bitWidth>1</bitWidth>
39873 </field>
39874 <field>
39875 <name>FB24</name>
39876 <description>Filter bits</description>
39877 <bitOffset>24</bitOffset>
39878 <bitWidth>1</bitWidth>
39879 </field>
39880 <field>
39881 <name>FB25</name>
39882 <description>Filter bits</description>
39883 <bitOffset>25</bitOffset>
39884 <bitWidth>1</bitWidth>
39885 </field>
39886 <field>
39887 <name>FB26</name>
39888 <description>Filter bits</description>
39889 <bitOffset>26</bitOffset>
39890 <bitWidth>1</bitWidth>
39891 </field>
39892 <field>
39893 <name>FB27</name>
39894 <description>Filter bits</description>
39895 <bitOffset>27</bitOffset>
39896 <bitWidth>1</bitWidth>
39897 </field>
39898 <field>
39899 <name>FB28</name>
39900 <description>Filter bits</description>
39901 <bitOffset>28</bitOffset>
39902 <bitWidth>1</bitWidth>
39903 </field>
39904 <field>
39905 <name>FB29</name>
39906 <description>Filter bits</description>
39907 <bitOffset>29</bitOffset>
39908 <bitWidth>1</bitWidth>
39909 </field>
39910 <field>
39911 <name>FB30</name>
39912 <description>Filter bits</description>
39913 <bitOffset>30</bitOffset>
39914 <bitWidth>1</bitWidth>
39915 </field>
39916 <field>
39917 <name>FB31</name>
39918 <description>Filter bits</description>
39919 <bitOffset>31</bitOffset>
39920 <bitWidth>1</bitWidth>
39921 </field>
39922 </fields>
39923 </register>
39924 </registers>
39925 </peripheral>
39926 <peripheral derivedFrom="CAN1">
39927 <name>CAN2</name>
39928 <baseAddress>0x40006800</baseAddress>
39929 <interrupt>
39930 <name>CAN2_TX</name>
39931 <description>CAN2 TX interrupts</description>
39932 <value>63</value>
39933 </interrupt>
39934 <interrupt>
39935 <name>CAN2_RX0</name>
39936 <description>CAN2 RX0 interrupts</description>
39937 <value>64</value>
39938 </interrupt>
39939 <interrupt>
39940 <name>CAN2_RX1</name>
39941 <description>CAN2 RX1 interrupts</description>
39942 <value>65</value>
39943 </interrupt>
39944 <interrupt>
39945 <name>CAN2_SCE</name>
39946 <description>CAN2 SCE interrupt</description>
39947 <value>66</value>
39948 </interrupt>
39949 </peripheral>
39950 <peripheral>
39951 <name>FLASH</name>
39952 <description>FLASH</description>
39953 <groupName>FLASH</groupName>
39954 <baseAddress>0x40023C00</baseAddress>
39955 <addressBlock>
39956 <offset>0x0</offset>
39957 <size>0x400</size>
39958 <usage>registers</usage>
39959 </addressBlock>
39960 <interrupt>
39961 <name>FLASH</name>
39962 <description>Flash global interrupt</description>
39963 <value>4</value>
39964 </interrupt>
39965 <registers>
39966 <register>
39967 <name>ACR</name>
39968 <displayName>ACR</displayName>
39969 <description>Flash access control register</description>
39970 <addressOffset>0x0</addressOffset>
39971 <size>0x20</size>
39972 <access>read-write</access>
39973 <resetValue>0x00000000</resetValue>
39974 <fields>
39975 <field>
39976 <name>LATENCY</name>
39977 <description>Latency</description>
39978 <bitOffset>0</bitOffset>
39979 <bitWidth>4</bitWidth>
39980 </field>
39981 <field>
39982 <name>PRFTEN</name>
39983 <description>Prefetch enable</description>
39984 <bitOffset>8</bitOffset>
39985 <bitWidth>1</bitWidth>
39986 </field>
39987 <field>
39988 <name>ARTEN</name>
39989 <description>ART Accelerator Enable</description>
39990 <bitOffset>9</bitOffset>
39991 <bitWidth>1</bitWidth>
39992 </field>
39993 <field>
39994 <name>ARTRST</name>
39995 <description>ART Accelerator reset</description>
39996 <bitOffset>11</bitOffset>
39997 <bitWidth>1</bitWidth>
39998 </field>
39999 </fields>
40000 </register>
40001 <register>
40002 <name>KEYR</name>
40003 <displayName>KEYR</displayName>
40004 <description>Flash key register</description>
40005 <addressOffset>0x4</addressOffset>
40006 <size>0x20</size>
40007 <access>write-only</access>
40008 <resetValue>0x00000000</resetValue>
40009 <fields>
40010 <field>
40011 <name>KEY</name>
40012 <description>FPEC key</description>
40013 <bitOffset>0</bitOffset>
40014 <bitWidth>32</bitWidth>
40015 </field>
40016 </fields>
40017 </register>
40018 <register>
40019 <name>OPTKEYR</name>
40020 <displayName>OPTKEYR</displayName>
40021 <description>Flash option key register</description>
40022 <addressOffset>0x8</addressOffset>
40023 <size>0x20</size>
40024 <access>write-only</access>
40025 <resetValue>0x00000000</resetValue>
40026 <fields>
40027 <field>
40028 <name>OPTKEY</name>
40029 <description>Option byte key</description>
40030 <bitOffset>0</bitOffset>
40031 <bitWidth>32</bitWidth>
40032 </field>
40033 </fields>
40034 </register>
40035 <register>
40036 <name>SR</name>
40037 <displayName>SR</displayName>
40038 <description>Status register</description>
40039 <addressOffset>0xC</addressOffset>
40040 <size>0x20</size>
40041 <resetValue>0x00000000</resetValue>
40042 <fields>
40043 <field>
40044 <name>EOP</name>
40045 <description>End of operation</description>
40046 <bitOffset>0</bitOffset>
40047 <bitWidth>1</bitWidth>
40048 <access>read-write</access>
40049 </field>
40050 <field>
40051 <name>OPERR</name>
40052 <description>Operation error</description>
40053 <bitOffset>1</bitOffset>
40054 <bitWidth>1</bitWidth>
40055 <access>read-write</access>
40056 </field>
40057 <field>
40058 <name>WRPERR</name>
40059 <description>Write protection error</description>
40060 <bitOffset>4</bitOffset>
40061 <bitWidth>1</bitWidth>
40062 <access>read-write</access>
40063 </field>
40064 <field>
40065 <name>PGAERR</name>
40066 <description>Programming alignment
40067 error</description>
40068 <bitOffset>5</bitOffset>
40069 <bitWidth>1</bitWidth>
40070 <access>read-write</access>
40071 </field>
40072 <field>
40073 <name>PGPERR</name>
40074 <description>Programming parallelism
40075 error</description>
40076 <bitOffset>6</bitOffset>
40077 <bitWidth>1</bitWidth>
40078 <access>read-write</access>
40079 </field>
40080 <field>
40081 <name>PGSERR</name>
40082 <description>Programming sequence error</description>
40083 <bitOffset>7</bitOffset>
40084 <bitWidth>1</bitWidth>
40085 <access>read-write</access>
40086 </field>
40087 <field>
40088 <name>BSY</name>
40089 <description>Busy</description>
40090 <bitOffset>16</bitOffset>
40091 <bitWidth>1</bitWidth>
40092 <access>read-only</access>
40093 </field>
40094 </fields>
40095 </register>
40096 <register>
40097 <name>CR</name>
40098 <displayName>CR</displayName>
40099 <description>Control register</description>
40100 <addressOffset>0x10</addressOffset>
40101 <size>0x20</size>
40102 <access>read-write</access>
40103 <resetValue>0x80000000</resetValue>
40104 <fields>
40105 <field>
40106 <name>PG</name>
40107 <description>Programming</description>
40108 <bitOffset>0</bitOffset>
40109 <bitWidth>1</bitWidth>
40110 </field>
40111 <field>
40112 <name>SER</name>
40113 <description>Sector Erase</description>
40114 <bitOffset>1</bitOffset>
40115 <bitWidth>1</bitWidth>
40116 </field>
40117 <field>
40118 <name>MER</name>
40119 <description>Mass Erase of sectors 0 to
40120 11</description>
40121 <bitOffset>2</bitOffset>
40122 <bitWidth>1</bitWidth>
40123 </field>
40124 <field>
40125 <name>SNB</name>
40126 <description>Sector number</description>
40127 <bitOffset>3</bitOffset>
40128 <bitWidth>5</bitWidth>
40129 </field>
40130 <field>
40131 <name>PSIZE</name>
40132 <description>Program size</description>
40133 <bitOffset>8</bitOffset>
40134 <bitWidth>2</bitWidth>
40135 </field>
40136 <field>
40137 <name>MER1</name>
40138 <description>Mass Erase of sectors 12 to
40139 23</description>
40140 <bitOffset>15</bitOffset>
40141 <bitWidth>1</bitWidth>
40142 </field>
40143 <field>
40144 <name>STRT</name>
40145 <description>Start</description>
40146 <bitOffset>16</bitOffset>
40147 <bitWidth>1</bitWidth>
40148 </field>
40149 <field>
40150 <name>EOPIE</name>
40151 <description>End of operation interrupt
40152 enable</description>
40153 <bitOffset>24</bitOffset>
40154 <bitWidth>1</bitWidth>
40155 </field>
40156 <field>
40157 <name>ERRIE</name>
40158 <description>Error interrupt enable</description>
40159 <bitOffset>25</bitOffset>
40160 <bitWidth>1</bitWidth>
40161 </field>
40162 <field>
40163 <name>LOCK</name>
40164 <description>Lock</description>
40165 <bitOffset>31</bitOffset>
40166 <bitWidth>1</bitWidth>
40167 </field>
40168 </fields>
40169 </register>
40170 <register>
40171 <name>OPTCR</name>
40172 <displayName>OPTCR</displayName>
40173 <description>Flash option control register</description>
40174 <addressOffset>0x14</addressOffset>
40175 <size>0x20</size>
40176 <access>read-write</access>
40177 <resetValue>0x0FFFAAED</resetValue>
40178 <fields>
40179 <field>
40180 <name>OPTLOCK</name>
40181 <description>Option lock</description>
40182 <bitOffset>0</bitOffset>
40183 <bitWidth>1</bitWidth>
40184 </field>
40185 <field>
40186 <name>OPTSTRT</name>
40187 <description>Option start</description>
40188 <bitOffset>1</bitOffset>
40189 <bitWidth>1</bitWidth>
40190 </field>
40191 <field>
40192 <name>BOR_LEV</name>
40193 <description>BOR reset Level</description>
40194 <bitOffset>2</bitOffset>
40195 <bitWidth>2</bitWidth>
40196 </field>
40197 <field>
40198 <name>WWDG_SW</name>
40199 <description>User option bytes</description>
40200 <bitOffset>4</bitOffset>
40201 <bitWidth>1</bitWidth>
40202 </field>
40203 <field>
40204 <name>IWDG_SW</name>
40205 <description>User option bytes</description>
40206 <bitOffset>5</bitOffset>
40207 <bitWidth>1</bitWidth>
40208 </field>
40209 <field>
40210 <name>nRST_STOP</name>
40211 <description>User option bytes</description>
40212 <bitOffset>6</bitOffset>
40213 <bitWidth>1</bitWidth>
40214 </field>
40215 <field>
40216 <name>nRST_STDBY</name>
40217 <description>User option bytes</description>
40218 <bitOffset>7</bitOffset>
40219 <bitWidth>1</bitWidth>
40220 </field>
40221 <field>
40222 <name>RDP</name>
40223 <description>Read protect</description>
40224 <bitOffset>8</bitOffset>
40225 <bitWidth>8</bitWidth>
40226 </field>
40227 <field>
40228 <name>nWRP</name>
40229 <description>Not write protect</description>
40230 <bitOffset>16</bitOffset>
40231 <bitWidth>8</bitWidth>
40232 </field>
40233 <field>
40234 <name>IWDG_STDBY</name>
40235 <description>Independent watchdog counter freeze in
40236 standby mode</description>
40237 <bitOffset>30</bitOffset>
40238 <bitWidth>1</bitWidth>
40239 </field>
40240 <field>
40241 <name>IWDG_STOP</name>
40242 <description>Independent watchdog counter freeze in
40243 Stop mode</description>
40244 <bitOffset>31</bitOffset>
40245 <bitWidth>1</bitWidth>
40246 </field>
40247 </fields>
40248 </register>
40249 <register>
40250 <name>OPTCR1</name>
40251 <displayName>OPTCR1</displayName>
40252 <description>Flash option control register
40253 1</description>
40254 <addressOffset>0x18</addressOffset>
40255 <size>0x20</size>
40256 <access>read-write</access>
40257 <resetValue>0x0FFF0000</resetValue>
40258 <fields>
40259 <field>
40260 <name>BOOT_ADD0</name>
40261 <description>Boot base address when Boot pin
40262 =0</description>
40263 <bitOffset>0</bitOffset>
40264 <bitWidth>16</bitWidth>
40265 </field>
40266 <field>
40267 <name>BOOT_ADD1</name>
40268 <description>Boot base address when Boot pin
40269 =1</description>
40270 <bitOffset>16</bitOffset>
40271 <bitWidth>16</bitWidth>
40272 </field>
40273 </fields>
40274 </register>
40275 </registers>
40276 </peripheral>
40277 <peripheral>
40278 <name>EXTI</name>
40279 <description>External interrupt/event
40280 controller</description>
40281 <groupName>EXTI</groupName>
40282 <baseAddress>0x40013C00</baseAddress>
40283 <addressBlock>
40284 <offset>0x0</offset>
40285 <size>0x400</size>
40286 <usage>registers</usage>
40287 </addressBlock>
40288 <interrupt>
40289 <name>TAMP_STAMP</name>
40290 <description>Tamper and TimeStamp interrupts through the
40291 EXTI line</description>
40292 <value>2</value>
40293 </interrupt>
40294 <interrupt>
40295 <name>EXTI0</name>
40296 <description>EXTI Line0 interrupt</description>
40297 <value>6</value>
40298 </interrupt>
40299 <interrupt>
40300 <name>EXTI1</name>
40301 <description>EXTI Line1 interrupt</description>
40302 <value>7</value>
40303 </interrupt>
40304 <interrupt>
40305 <name>EXTI2</name>
40306 <description>EXTI Line2 interrupt</description>
40307 <value>8</value>
40308 </interrupt>
40309 <interrupt>
40310 <name>EXTI3</name>
40311 <description>EXTI Line3 interrupt</description>
40312 <value>9</value>
40313 </interrupt>
40314 <interrupt>
40315 <name>EXTI4</name>
40316 <description>EXTI Line4 interrupt</description>
40317 <value>10</value>
40318 </interrupt>
40319 <interrupt>
40320 <name>EXTI9_5</name>
40321 <description>EXTI Line[9:5] interrupts</description>
40322 <value>23</value>
40323 </interrupt>
40324 <interrupt>
40325 <name>EXTI15_10</name>
40326 <description>EXTI Line[15:10] interrupts</description>
40327 <value>40</value>
40328 </interrupt>
40329 <registers>
40330 <register>
40331 <name>IMR</name>
40332 <displayName>IMR</displayName>
40333 <description>Interrupt mask register
40334 (EXTI_IMR)</description>
40335 <addressOffset>0x0</addressOffset>
40336 <size>0x20</size>
40337 <access>read-write</access>
40338 <resetValue>0x00000000</resetValue>
40339 <fields>
40340 <field>
40341 <name>MR0</name>
40342 <description>Interrupt Mask on line 0</description>
40343 <bitOffset>0</bitOffset>
40344 <bitWidth>1</bitWidth>
40345 </field>
40346 <field>
40347 <name>MR1</name>
40348 <description>Interrupt Mask on line 1</description>
40349 <bitOffset>1</bitOffset>
40350 <bitWidth>1</bitWidth>
40351 </field>
40352 <field>
40353 <name>MR2</name>
40354 <description>Interrupt Mask on line 2</description>
40355 <bitOffset>2</bitOffset>
40356 <bitWidth>1</bitWidth>
40357 </field>
40358 <field>
40359 <name>MR3</name>
40360 <description>Interrupt Mask on line 3</description>
40361 <bitOffset>3</bitOffset>
40362 <bitWidth>1</bitWidth>
40363 </field>
40364 <field>
40365 <name>MR4</name>
40366 <description>Interrupt Mask on line 4</description>
40367 <bitOffset>4</bitOffset>
40368 <bitWidth>1</bitWidth>
40369 </field>
40370 <field>
40371 <name>MR5</name>
40372 <description>Interrupt Mask on line 5</description>
40373 <bitOffset>5</bitOffset>
40374 <bitWidth>1</bitWidth>
40375 </field>
40376 <field>
40377 <name>MR6</name>
40378 <description>Interrupt Mask on line 6</description>
40379 <bitOffset>6</bitOffset>
40380 <bitWidth>1</bitWidth>
40381 </field>
40382 <field>
40383 <name>MR7</name>
40384 <description>Interrupt Mask on line 7</description>
40385 <bitOffset>7</bitOffset>
40386 <bitWidth>1</bitWidth>
40387 </field>
40388 <field>
40389 <name>MR8</name>
40390 <description>Interrupt Mask on line 8</description>
40391 <bitOffset>8</bitOffset>
40392 <bitWidth>1</bitWidth>
40393 </field>
40394 <field>
40395 <name>MR9</name>
40396 <description>Interrupt Mask on line 9</description>
40397 <bitOffset>9</bitOffset>
40398 <bitWidth>1</bitWidth>
40399 </field>
40400 <field>
40401 <name>MR10</name>
40402 <description>Interrupt Mask on line 10</description>
40403 <bitOffset>10</bitOffset>
40404 <bitWidth>1</bitWidth>
40405 </field>
40406 <field>
40407 <name>MR11</name>
40408 <description>Interrupt Mask on line 11</description>
40409 <bitOffset>11</bitOffset>
40410 <bitWidth>1</bitWidth>
40411 </field>
40412 <field>
40413 <name>MR12</name>
40414 <description>Interrupt Mask on line 12</description>
40415 <bitOffset>12</bitOffset>
40416 <bitWidth>1</bitWidth>
40417 </field>
40418 <field>
40419 <name>MR13</name>
40420 <description>Interrupt Mask on line 13</description>
40421 <bitOffset>13</bitOffset>
40422 <bitWidth>1</bitWidth>
40423 </field>
40424 <field>
40425 <name>MR14</name>
40426 <description>Interrupt Mask on line 14</description>
40427 <bitOffset>14</bitOffset>
40428 <bitWidth>1</bitWidth>
40429 </field>
40430 <field>
40431 <name>MR15</name>
40432 <description>Interrupt Mask on line 15</description>
40433 <bitOffset>15</bitOffset>
40434 <bitWidth>1</bitWidth>
40435 </field>
40436 <field>
40437 <name>MR16</name>
40438 <description>Interrupt Mask on line 16</description>
40439 <bitOffset>16</bitOffset>
40440 <bitWidth>1</bitWidth>
40441 </field>
40442 <field>
40443 <name>MR17</name>
40444 <description>Interrupt Mask on line 17</description>
40445 <bitOffset>17</bitOffset>
40446 <bitWidth>1</bitWidth>
40447 </field>
40448 <field>
40449 <name>MR18</name>
40450 <description>Interrupt Mask on line 18</description>
40451 <bitOffset>18</bitOffset>
40452 <bitWidth>1</bitWidth>
40453 </field>
40454 <field>
40455 <name>MR19</name>
40456 <description>Interrupt Mask on line 19</description>
40457 <bitOffset>19</bitOffset>
40458 <bitWidth>1</bitWidth>
40459 </field>
40460 <field>
40461 <name>MR20</name>
40462 <description>Interrupt Mask on line 20</description>
40463 <bitOffset>20</bitOffset>
40464 <bitWidth>1</bitWidth>
40465 </field>
40466 <field>
40467 <name>MR21</name>
40468 <description>Interrupt Mask on line 21</description>
40469 <bitOffset>21</bitOffset>
40470 <bitWidth>1</bitWidth>
40471 </field>
40472 <field>
40473 <name>MR22</name>
40474 <description>Interrupt Mask on line 22</description>
40475 <bitOffset>22</bitOffset>
40476 <bitWidth>1</bitWidth>
40477 </field>
40478 </fields>
40479 </register>
40480 <register>
40481 <name>EMR</name>
40482 <displayName>EMR</displayName>
40483 <description>Event mask register (EXTI_EMR)</description>
40484 <addressOffset>0x4</addressOffset>
40485 <size>0x20</size>
40486 <access>read-write</access>
40487 <resetValue>0x00000000</resetValue>
40488 <fields>
40489 <field>
40490 <name>MR0</name>
40491 <description>Event Mask on line 0</description>
40492 <bitOffset>0</bitOffset>
40493 <bitWidth>1</bitWidth>
40494 </field>
40495 <field>
40496 <name>MR1</name>
40497 <description>Event Mask on line 1</description>
40498 <bitOffset>1</bitOffset>
40499 <bitWidth>1</bitWidth>
40500 </field>
40501 <field>
40502 <name>MR2</name>
40503 <description>Event Mask on line 2</description>
40504 <bitOffset>2</bitOffset>
40505 <bitWidth>1</bitWidth>
40506 </field>
40507 <field>
40508 <name>MR3</name>
40509 <description>Event Mask on line 3</description>
40510 <bitOffset>3</bitOffset>
40511 <bitWidth>1</bitWidth>
40512 </field>
40513 <field>
40514 <name>MR4</name>
40515 <description>Event Mask on line 4</description>
40516 <bitOffset>4</bitOffset>
40517 <bitWidth>1</bitWidth>
40518 </field>
40519 <field>
40520 <name>MR5</name>
40521 <description>Event Mask on line 5</description>
40522 <bitOffset>5</bitOffset>
40523 <bitWidth>1</bitWidth>
40524 </field>
40525 <field>
40526 <name>MR6</name>
40527 <description>Event Mask on line 6</description>
40528 <bitOffset>6</bitOffset>
40529 <bitWidth>1</bitWidth>
40530 </field>
40531 <field>
40532 <name>MR7</name>
40533 <description>Event Mask on line 7</description>
40534 <bitOffset>7</bitOffset>
40535 <bitWidth>1</bitWidth>
40536 </field>
40537 <field>
40538 <name>MR8</name>
40539 <description>Event Mask on line 8</description>
40540 <bitOffset>8</bitOffset>
40541 <bitWidth>1</bitWidth>
40542 </field>
40543 <field>
40544 <name>MR9</name>
40545 <description>Event Mask on line 9</description>
40546 <bitOffset>9</bitOffset>
40547 <bitWidth>1</bitWidth>
40548 </field>
40549 <field>
40550 <name>MR10</name>
40551 <description>Event Mask on line 10</description>
40552 <bitOffset>10</bitOffset>
40553 <bitWidth>1</bitWidth>
40554 </field>
40555 <field>
40556 <name>MR11</name>
40557 <description>Event Mask on line 11</description>
40558 <bitOffset>11</bitOffset>
40559 <bitWidth>1</bitWidth>
40560 </field>
40561 <field>
40562 <name>MR12</name>
40563 <description>Event Mask on line 12</description>
40564 <bitOffset>12</bitOffset>
40565 <bitWidth>1</bitWidth>
40566 </field>
40567 <field>
40568 <name>MR13</name>
40569 <description>Event Mask on line 13</description>
40570 <bitOffset>13</bitOffset>
40571 <bitWidth>1</bitWidth>
40572 </field>
40573 <field>
40574 <name>MR14</name>
40575 <description>Event Mask on line 14</description>
40576 <bitOffset>14</bitOffset>
40577 <bitWidth>1</bitWidth>
40578 </field>
40579 <field>
40580 <name>MR15</name>
40581 <description>Event Mask on line 15</description>
40582 <bitOffset>15</bitOffset>
40583 <bitWidth>1</bitWidth>
40584 </field>
40585 <field>
40586 <name>MR16</name>
40587 <description>Event Mask on line 16</description>
40588 <bitOffset>16</bitOffset>
40589 <bitWidth>1</bitWidth>
40590 </field>
40591 <field>
40592 <name>MR17</name>
40593 <description>Event Mask on line 17</description>
40594 <bitOffset>17</bitOffset>
40595 <bitWidth>1</bitWidth>
40596 </field>
40597 <field>
40598 <name>MR18</name>
40599 <description>Event Mask on line 18</description>
40600 <bitOffset>18</bitOffset>
40601 <bitWidth>1</bitWidth>
40602 </field>
40603 <field>
40604 <name>MR19</name>
40605 <description>Event Mask on line 19</description>
40606 <bitOffset>19</bitOffset>
40607 <bitWidth>1</bitWidth>
40608 </field>
40609 <field>
40610 <name>MR20</name>
40611 <description>Event Mask on line 20</description>
40612 <bitOffset>20</bitOffset>
40613 <bitWidth>1</bitWidth>
40614 </field>
40615 <field>
40616 <name>MR21</name>
40617 <description>Event Mask on line 21</description>
40618 <bitOffset>21</bitOffset>
40619 <bitWidth>1</bitWidth>
40620 </field>
40621 <field>
40622 <name>MR22</name>
40623 <description>Event Mask on line 22</description>
40624 <bitOffset>22</bitOffset>
40625 <bitWidth>1</bitWidth>
40626 </field>
40627 </fields>
40628 </register>
40629 <register>
40630 <name>RTSR</name>
40631 <displayName>RTSR</displayName>
40632 <description>Rising Trigger selection register
40633 (EXTI_RTSR)</description>
40634 <addressOffset>0x8</addressOffset>
40635 <size>0x20</size>
40636 <access>read-write</access>
40637 <resetValue>0x00000000</resetValue>
40638 <fields>
40639 <field>
40640 <name>TR0</name>
40641 <description>Rising trigger event configuration of
40642 line 0</description>
40643 <bitOffset>0</bitOffset>
40644 <bitWidth>1</bitWidth>
40645 </field>
40646 <field>
40647 <name>TR1</name>
40648 <description>Rising trigger event configuration of
40649 line 1</description>
40650 <bitOffset>1</bitOffset>
40651 <bitWidth>1</bitWidth>
40652 </field>
40653 <field>
40654 <name>TR2</name>
40655 <description>Rising trigger event configuration of
40656 line 2</description>
40657 <bitOffset>2</bitOffset>
40658 <bitWidth>1</bitWidth>
40659 </field>
40660 <field>
40661 <name>TR3</name>
40662 <description>Rising trigger event configuration of
40663 line 3</description>
40664 <bitOffset>3</bitOffset>
40665 <bitWidth>1</bitWidth>
40666 </field>
40667 <field>
40668 <name>TR4</name>
40669 <description>Rising trigger event configuration of
40670 line 4</description>
40671 <bitOffset>4</bitOffset>
40672 <bitWidth>1</bitWidth>
40673 </field>
40674 <field>
40675 <name>TR5</name>
40676 <description>Rising trigger event configuration of
40677 line 5</description>
40678 <bitOffset>5</bitOffset>
40679 <bitWidth>1</bitWidth>
40680 </field>
40681 <field>
40682 <name>TR6</name>
40683 <description>Rising trigger event configuration of
40684 line 6</description>
40685 <bitOffset>6</bitOffset>
40686 <bitWidth>1</bitWidth>
40687 </field>
40688 <field>
40689 <name>TR7</name>
40690 <description>Rising trigger event configuration of
40691 line 7</description>
40692 <bitOffset>7</bitOffset>
40693 <bitWidth>1</bitWidth>
40694 </field>
40695 <field>
40696 <name>TR8</name>
40697 <description>Rising trigger event configuration of
40698 line 8</description>
40699 <bitOffset>8</bitOffset>
40700 <bitWidth>1</bitWidth>
40701 </field>
40702 <field>
40703 <name>TR9</name>
40704 <description>Rising trigger event configuration of
40705 line 9</description>
40706 <bitOffset>9</bitOffset>
40707 <bitWidth>1</bitWidth>
40708 </field>
40709 <field>
40710 <name>TR10</name>
40711 <description>Rising trigger event configuration of
40712 line 10</description>
40713 <bitOffset>10</bitOffset>
40714 <bitWidth>1</bitWidth>
40715 </field>
40716 <field>
40717 <name>TR11</name>
40718 <description>Rising trigger event configuration of
40719 line 11</description>
40720 <bitOffset>11</bitOffset>
40721 <bitWidth>1</bitWidth>
40722 </field>
40723 <field>
40724 <name>TR12</name>
40725 <description>Rising trigger event configuration of
40726 line 12</description>
40727 <bitOffset>12</bitOffset>
40728 <bitWidth>1</bitWidth>
40729 </field>
40730 <field>
40731 <name>TR13</name>
40732 <description>Rising trigger event configuration of
40733 line 13</description>
40734 <bitOffset>13</bitOffset>
40735 <bitWidth>1</bitWidth>
40736 </field>
40737 <field>
40738 <name>TR14</name>
40739 <description>Rising trigger event configuration of
40740 line 14</description>
40741 <bitOffset>14</bitOffset>
40742 <bitWidth>1</bitWidth>
40743 </field>
40744 <field>
40745 <name>TR15</name>
40746 <description>Rising trigger event configuration of
40747 line 15</description>
40748 <bitOffset>15</bitOffset>
40749 <bitWidth>1</bitWidth>
40750 </field>
40751 <field>
40752 <name>TR16</name>
40753 <description>Rising trigger event configuration of
40754 line 16</description>
40755 <bitOffset>16</bitOffset>
40756 <bitWidth>1</bitWidth>
40757 </field>
40758 <field>
40759 <name>TR17</name>
40760 <description>Rising trigger event configuration of
40761 line 17</description>
40762 <bitOffset>17</bitOffset>
40763 <bitWidth>1</bitWidth>
40764 </field>
40765 <field>
40766 <name>TR18</name>
40767 <description>Rising trigger event configuration of
40768 line 18</description>
40769 <bitOffset>18</bitOffset>
40770 <bitWidth>1</bitWidth>
40771 </field>
40772 <field>
40773 <name>TR19</name>
40774 <description>Rising trigger event configuration of
40775 line 19</description>
40776 <bitOffset>19</bitOffset>
40777 <bitWidth>1</bitWidth>
40778 </field>
40779 <field>
40780 <name>TR20</name>
40781 <description>Rising trigger event configuration of
40782 line 20</description>
40783 <bitOffset>20</bitOffset>
40784 <bitWidth>1</bitWidth>
40785 </field>
40786 <field>
40787 <name>TR21</name>
40788 <description>Rising trigger event configuration of
40789 line 21</description>
40790 <bitOffset>21</bitOffset>
40791 <bitWidth>1</bitWidth>
40792 </field>
40793 <field>
40794 <name>TR22</name>
40795 <description>Rising trigger event configuration of
40796 line 22</description>
40797 <bitOffset>22</bitOffset>
40798 <bitWidth>1</bitWidth>
40799 </field>
40800 </fields>
40801 </register>
40802 <register>
40803 <name>FTSR</name>
40804 <displayName>FTSR</displayName>
40805 <description>Falling Trigger selection register
40806 (EXTI_FTSR)</description>
40807 <addressOffset>0xC</addressOffset>
40808 <size>0x20</size>
40809 <access>read-write</access>
40810 <resetValue>0x00000000</resetValue>
40811 <fields>
40812 <field>
40813 <name>TR0</name>
40814 <description>Falling trigger event configuration of
40815 line 0</description>
40816 <bitOffset>0</bitOffset>
40817 <bitWidth>1</bitWidth>
40818 </field>
40819 <field>
40820 <name>TR1</name>
40821 <description>Falling trigger event configuration of
40822 line 1</description>
40823 <bitOffset>1</bitOffset>
40824 <bitWidth>1</bitWidth>
40825 </field>
40826 <field>
40827 <name>TR2</name>
40828 <description>Falling trigger event configuration of
40829 line 2</description>
40830 <bitOffset>2</bitOffset>
40831 <bitWidth>1</bitWidth>
40832 </field>
40833 <field>
40834 <name>TR3</name>
40835 <description>Falling trigger event configuration of
40836 line 3</description>
40837 <bitOffset>3</bitOffset>
40838 <bitWidth>1</bitWidth>
40839 </field>
40840 <field>
40841 <name>TR4</name>
40842 <description>Falling trigger event configuration of
40843 line 4</description>
40844 <bitOffset>4</bitOffset>
40845 <bitWidth>1</bitWidth>
40846 </field>
40847 <field>
40848 <name>TR5</name>
40849 <description>Falling trigger event configuration of
40850 line 5</description>
40851 <bitOffset>5</bitOffset>
40852 <bitWidth>1</bitWidth>
40853 </field>
40854 <field>
40855 <name>TR6</name>
40856 <description>Falling trigger event configuration of
40857 line 6</description>
40858 <bitOffset>6</bitOffset>
40859 <bitWidth>1</bitWidth>
40860 </field>
40861 <field>
40862 <name>TR7</name>
40863 <description>Falling trigger event configuration of
40864 line 7</description>
40865 <bitOffset>7</bitOffset>
40866 <bitWidth>1</bitWidth>
40867 </field>
40868 <field>
40869 <name>TR8</name>
40870 <description>Falling trigger event configuration of
40871 line 8</description>
40872 <bitOffset>8</bitOffset>
40873 <bitWidth>1</bitWidth>
40874 </field>
40875 <field>
40876 <name>TR9</name>
40877 <description>Falling trigger event configuration of
40878 line 9</description>
40879 <bitOffset>9</bitOffset>
40880 <bitWidth>1</bitWidth>
40881 </field>
40882 <field>
40883 <name>TR10</name>
40884 <description>Falling trigger event configuration of
40885 line 10</description>
40886 <bitOffset>10</bitOffset>
40887 <bitWidth>1</bitWidth>
40888 </field>
40889 <field>
40890 <name>TR11</name>
40891 <description>Falling trigger event configuration of
40892 line 11</description>
40893 <bitOffset>11</bitOffset>
40894 <bitWidth>1</bitWidth>
40895 </field>
40896 <field>
40897 <name>TR12</name>
40898 <description>Falling trigger event configuration of
40899 line 12</description>
40900 <bitOffset>12</bitOffset>
40901 <bitWidth>1</bitWidth>
40902 </field>
40903 <field>
40904 <name>TR13</name>
40905 <description>Falling trigger event configuration of
40906 line 13</description>
40907 <bitOffset>13</bitOffset>
40908 <bitWidth>1</bitWidth>
40909 </field>
40910 <field>
40911 <name>TR14</name>
40912 <description>Falling trigger event configuration of
40913 line 14</description>
40914 <bitOffset>14</bitOffset>
40915 <bitWidth>1</bitWidth>
40916 </field>
40917 <field>
40918 <name>TR15</name>
40919 <description>Falling trigger event configuration of
40920 line 15</description>
40921 <bitOffset>15</bitOffset>
40922 <bitWidth>1</bitWidth>
40923 </field>
40924 <field>
40925 <name>TR16</name>
40926 <description>Falling trigger event configuration of
40927 line 16</description>
40928 <bitOffset>16</bitOffset>
40929 <bitWidth>1</bitWidth>
40930 </field>
40931 <field>
40932 <name>TR17</name>
40933 <description>Falling trigger event configuration of
40934 line 17</description>
40935 <bitOffset>17</bitOffset>
40936 <bitWidth>1</bitWidth>
40937 </field>
40938 <field>
40939 <name>TR18</name>
40940 <description>Falling trigger event configuration of
40941 line 18</description>
40942 <bitOffset>18</bitOffset>
40943 <bitWidth>1</bitWidth>
40944 </field>
40945 <field>
40946 <name>TR19</name>
40947 <description>Falling trigger event configuration of
40948 line 19</description>
40949 <bitOffset>19</bitOffset>
40950 <bitWidth>1</bitWidth>
40951 </field>
40952 <field>
40953 <name>TR20</name>
40954 <description>Falling trigger event configuration of
40955 line 20</description>
40956 <bitOffset>20</bitOffset>
40957 <bitWidth>1</bitWidth>
40958 </field>
40959 <field>
40960 <name>TR21</name>
40961 <description>Falling trigger event configuration of
40962 line 21</description>
40963 <bitOffset>21</bitOffset>
40964 <bitWidth>1</bitWidth>
40965 </field>
40966 <field>
40967 <name>TR22</name>
40968 <description>Falling trigger event configuration of
40969 line 22</description>
40970 <bitOffset>22</bitOffset>
40971 <bitWidth>1</bitWidth>
40972 </field>
40973 </fields>
40974 </register>
40975 <register>
40976 <name>SWIER</name>
40977 <displayName>SWIER</displayName>
40978 <description>Software interrupt event register
40979 (EXTI_SWIER)</description>
40980 <addressOffset>0x10</addressOffset>
40981 <size>0x20</size>
40982 <access>read-write</access>
40983 <resetValue>0x00000000</resetValue>
40984 <fields>
40985 <field>
40986 <name>SWIER0</name>
40987 <description>Software Interrupt on line
40988 0</description>
40989 <bitOffset>0</bitOffset>
40990 <bitWidth>1</bitWidth>
40991 </field>
40992 <field>
40993 <name>SWIER1</name>
40994 <description>Software Interrupt on line
40995 1</description>
40996 <bitOffset>1</bitOffset>
40997 <bitWidth>1</bitWidth>
40998 </field>
40999 <field>
41000 <name>SWIER2</name>
41001 <description>Software Interrupt on line
41002 2</description>
41003 <bitOffset>2</bitOffset>
41004 <bitWidth>1</bitWidth>
41005 </field>
41006 <field>
41007 <name>SWIER3</name>
41008 <description>Software Interrupt on line
41009 3</description>
41010 <bitOffset>3</bitOffset>
41011 <bitWidth>1</bitWidth>
41012 </field>
41013 <field>
41014 <name>SWIER4</name>
41015 <description>Software Interrupt on line
41016 4</description>
41017 <bitOffset>4</bitOffset>
41018 <bitWidth>1</bitWidth>
41019 </field>
41020 <field>
41021 <name>SWIER5</name>
41022 <description>Software Interrupt on line
41023 5</description>
41024 <bitOffset>5</bitOffset>
41025 <bitWidth>1</bitWidth>
41026 </field>
41027 <field>
41028 <name>SWIER6</name>
41029 <description>Software Interrupt on line
41030 6</description>
41031 <bitOffset>6</bitOffset>
41032 <bitWidth>1</bitWidth>
41033 </field>
41034 <field>
41035 <name>SWIER7</name>
41036 <description>Software Interrupt on line
41037 7</description>
41038 <bitOffset>7</bitOffset>
41039 <bitWidth>1</bitWidth>
41040 </field>
41041 <field>
41042 <name>SWIER8</name>
41043 <description>Software Interrupt on line
41044 8</description>
41045 <bitOffset>8</bitOffset>
41046 <bitWidth>1</bitWidth>
41047 </field>
41048 <field>
41049 <name>SWIER9</name>
41050 <description>Software Interrupt on line
41051 9</description>
41052 <bitOffset>9</bitOffset>
41053 <bitWidth>1</bitWidth>
41054 </field>
41055 <field>
41056 <name>SWIER10</name>
41057 <description>Software Interrupt on line
41058 10</description>
41059 <bitOffset>10</bitOffset>
41060 <bitWidth>1</bitWidth>
41061 </field>
41062 <field>
41063 <name>SWIER11</name>
41064 <description>Software Interrupt on line
41065 11</description>
41066 <bitOffset>11</bitOffset>
41067 <bitWidth>1</bitWidth>
41068 </field>
41069 <field>
41070 <name>SWIER12</name>
41071 <description>Software Interrupt on line
41072 12</description>
41073 <bitOffset>12</bitOffset>
41074 <bitWidth>1</bitWidth>
41075 </field>
41076 <field>
41077 <name>SWIER13</name>
41078 <description>Software Interrupt on line
41079 13</description>
41080 <bitOffset>13</bitOffset>
41081 <bitWidth>1</bitWidth>
41082 </field>
41083 <field>
41084 <name>SWIER14</name>
41085 <description>Software Interrupt on line
41086 14</description>
41087 <bitOffset>14</bitOffset>
41088 <bitWidth>1</bitWidth>
41089 </field>
41090 <field>
41091 <name>SWIER15</name>
41092 <description>Software Interrupt on line
41093 15</description>
41094 <bitOffset>15</bitOffset>
41095 <bitWidth>1</bitWidth>
41096 </field>
41097 <field>
41098 <name>SWIER16</name>
41099 <description>Software Interrupt on line
41100 16</description>
41101 <bitOffset>16</bitOffset>
41102 <bitWidth>1</bitWidth>
41103 </field>
41104 <field>
41105 <name>SWIER17</name>
41106 <description>Software Interrupt on line
41107 17</description>
41108 <bitOffset>17</bitOffset>
41109 <bitWidth>1</bitWidth>
41110 </field>
41111 <field>
41112 <name>SWIER18</name>
41113 <description>Software Interrupt on line
41114 18</description>
41115 <bitOffset>18</bitOffset>
41116 <bitWidth>1</bitWidth>
41117 </field>
41118 <field>
41119 <name>SWIER19</name>
41120 <description>Software Interrupt on line
41121 19</description>
41122 <bitOffset>19</bitOffset>
41123 <bitWidth>1</bitWidth>
41124 </field>
41125 <field>
41126 <name>SWIER20</name>
41127 <description>Software Interrupt on line
41128 20</description>
41129 <bitOffset>20</bitOffset>
41130 <bitWidth>1</bitWidth>
41131 </field>
41132 <field>
41133 <name>SWIER21</name>
41134 <description>Software Interrupt on line
41135 21</description>
41136 <bitOffset>21</bitOffset>
41137 <bitWidth>1</bitWidth>
41138 </field>
41139 <field>
41140 <name>SWIER22</name>
41141 <description>Software Interrupt on line
41142 22</description>
41143 <bitOffset>22</bitOffset>
41144 <bitWidth>1</bitWidth>
41145 </field>
41146 </fields>
41147 </register>
41148 <register>
41149 <name>PR</name>
41150 <displayName>PR</displayName>
41151 <description>Pending register (EXTI_PR)</description>
41152 <addressOffset>0x14</addressOffset>
41153 <size>0x20</size>
41154 <access>read-write</access>
41155 <resetValue>0x00000000</resetValue>
41156 <fields>
41157 <field>
41158 <name>PR0</name>
41159 <description>Pending bit 0</description>
41160 <bitOffset>0</bitOffset>
41161 <bitWidth>1</bitWidth>
41162 </field>
41163 <field>
41164 <name>PR1</name>
41165 <description>Pending bit 1</description>
41166 <bitOffset>1</bitOffset>
41167 <bitWidth>1</bitWidth>
41168 </field>
41169 <field>
41170 <name>PR2</name>
41171 <description>Pending bit 2</description>
41172 <bitOffset>2</bitOffset>
41173 <bitWidth>1</bitWidth>
41174 </field>
41175 <field>
41176 <name>PR3</name>
41177 <description>Pending bit 3</description>
41178 <bitOffset>3</bitOffset>
41179 <bitWidth>1</bitWidth>
41180 </field>
41181 <field>
41182 <name>PR4</name>
41183 <description>Pending bit 4</description>
41184 <bitOffset>4</bitOffset>
41185 <bitWidth>1</bitWidth>
41186 </field>
41187 <field>
41188 <name>PR5</name>
41189 <description>Pending bit 5</description>
41190 <bitOffset>5</bitOffset>
41191 <bitWidth>1</bitWidth>
41192 </field>
41193 <field>
41194 <name>PR6</name>
41195 <description>Pending bit 6</description>
41196 <bitOffset>6</bitOffset>
41197 <bitWidth>1</bitWidth>
41198 </field>
41199 <field>
41200 <name>PR7</name>
41201 <description>Pending bit 7</description>
41202 <bitOffset>7</bitOffset>
41203 <bitWidth>1</bitWidth>
41204 </field>
41205 <field>
41206 <name>PR8</name>
41207 <description>Pending bit 8</description>
41208 <bitOffset>8</bitOffset>
41209 <bitWidth>1</bitWidth>
41210 </field>
41211 <field>
41212 <name>PR9</name>
41213 <description>Pending bit 9</description>
41214 <bitOffset>9</bitOffset>
41215 <bitWidth>1</bitWidth>
41216 </field>
41217 <field>
41218 <name>PR10</name>
41219 <description>Pending bit 10</description>
41220 <bitOffset>10</bitOffset>
41221 <bitWidth>1</bitWidth>
41222 </field>
41223 <field>
41224 <name>PR11</name>
41225 <description>Pending bit 11</description>
41226 <bitOffset>11</bitOffset>
41227 <bitWidth>1</bitWidth>
41228 </field>
41229 <field>
41230 <name>PR12</name>
41231 <description>Pending bit 12</description>
41232 <bitOffset>12</bitOffset>
41233 <bitWidth>1</bitWidth>
41234 </field>
41235 <field>
41236 <name>PR13</name>
41237 <description>Pending bit 13</description>
41238 <bitOffset>13</bitOffset>
41239 <bitWidth>1</bitWidth>
41240 </field>
41241 <field>
41242 <name>PR14</name>
41243 <description>Pending bit 14</description>
41244 <bitOffset>14</bitOffset>
41245 <bitWidth>1</bitWidth>
41246 </field>
41247 <field>
41248 <name>PR15</name>
41249 <description>Pending bit 15</description>
41250 <bitOffset>15</bitOffset>
41251 <bitWidth>1</bitWidth>
41252 </field>
41253 <field>
41254 <name>PR16</name>
41255 <description>Pending bit 16</description>
41256 <bitOffset>16</bitOffset>
41257 <bitWidth>1</bitWidth>
41258 </field>
41259 <field>
41260 <name>PR17</name>
41261 <description>Pending bit 17</description>
41262 <bitOffset>17</bitOffset>
41263 <bitWidth>1</bitWidth>
41264 </field>
41265 <field>
41266 <name>PR18</name>
41267 <description>Pending bit 18</description>
41268 <bitOffset>18</bitOffset>
41269 <bitWidth>1</bitWidth>
41270 </field>
41271 <field>
41272 <name>PR19</name>
41273 <description>Pending bit 19</description>
41274 <bitOffset>19</bitOffset>
41275 <bitWidth>1</bitWidth>
41276 </field>
41277 <field>
41278 <name>PR20</name>
41279 <description>Pending bit 20</description>
41280 <bitOffset>20</bitOffset>
41281 <bitWidth>1</bitWidth>
41282 </field>
41283 <field>
41284 <name>PR21</name>
41285 <description>Pending bit 21</description>
41286 <bitOffset>21</bitOffset>
41287 <bitWidth>1</bitWidth>
41288 </field>
41289 <field>
41290 <name>PR22</name>
41291 <description>Pending bit 22</description>
41292 <bitOffset>22</bitOffset>
41293 <bitWidth>1</bitWidth>
41294 </field>
41295 </fields>
41296 </register>
41297 </registers>
41298 </peripheral>
41299 <peripheral>
41300 <name>LTDC</name>
41301 <description>LCD-TFT Controller</description>
41302 <groupName>LTDC</groupName>
41303 <baseAddress>0x40016800</baseAddress>
41304 <addressBlock>
41305 <offset>0x0</offset>
41306 <size>0x400</size>
41307 <usage>registers</usage>
41308 </addressBlock>
41309 <interrupt>
41310 <name>LCD_TFT</name>
41311 <description>LTDC global interrupt</description>
41312 <value>88</value>
41313 </interrupt>
41314 <interrupt>
41315 <name>LTDC_ER</name>
41316 <description>LTDC Error global interrupt</description>
41317 <value>89</value>
41318 </interrupt>
41319 <registers>
41320 <register>
41321 <name>SSCR</name>
41322 <displayName>SSCR</displayName>
41323 <description>Synchronization Size Configuration
41324 Register</description>
41325 <addressOffset>0x8</addressOffset>
41326 <size>0x20</size>
41327 <access>read-write</access>
41328 <resetValue>0x00000000</resetValue>
41329 <fields>
41330 <field>
41331 <name>HSW</name>
41332 <description>Horizontal Synchronization Width (in
41333 units of pixel clock period)</description>
41334 <bitOffset>16</bitOffset>
41335 <bitWidth>10</bitWidth>
41336 </field>
41337 <field>
41338 <name>VSH</name>
41339 <description>Vertical Synchronization Height (in
41340 units of horizontal scan line)</description>
41341 <bitOffset>0</bitOffset>
41342 <bitWidth>11</bitWidth>
41343 </field>
41344 </fields>
41345 </register>
41346 <register>
41347 <name>BPCR</name>
41348 <displayName>BPCR</displayName>
41349 <description>Back Porch Configuration
41350 Register</description>
41351 <addressOffset>0xC</addressOffset>
41352 <size>0x20</size>
41353 <access>read-write</access>
41354 <resetValue>0x00000000</resetValue>
41355 <fields>
41356 <field>
41357 <name>AHBP</name>
41358 <description>Accumulated Horizontal back porch (in
41359 units of pixel clock period)</description>
41360 <bitOffset>16</bitOffset>
41361 <bitWidth>10</bitWidth>
41362 </field>
41363 <field>
41364 <name>AVBP</name>
41365 <description>Accumulated Vertical back porch (in
41366 units of horizontal scan line)</description>
41367 <bitOffset>0</bitOffset>
41368 <bitWidth>11</bitWidth>
41369 </field>
41370 </fields>
41371 </register>
41372 <register>
41373 <name>AWCR</name>
41374 <displayName>AWCR</displayName>
41375 <description>Active Width Configuration
41376 Register</description>
41377 <addressOffset>0x10</addressOffset>
41378 <size>0x20</size>
41379 <access>read-write</access>
41380 <resetValue>0x00000000</resetValue>
41381 <fields>
41382 <field>
41383 <name>AAV</name>
41384 <description>AAV</description>
41385 <bitOffset>16</bitOffset>
41386 <bitWidth>10</bitWidth>
41387 </field>
41388 <field>
41389 <name>AAH</name>
41390 <description>Accumulated Active Height (in units of
41391 horizontal scan line)</description>
41392 <bitOffset>0</bitOffset>
41393 <bitWidth>11</bitWidth>
41394 </field>
41395 </fields>
41396 </register>
41397 <register>
41398 <name>TWCR</name>
41399 <displayName>TWCR</displayName>
41400 <description>Total Width Configuration
41401 Register</description>
41402 <addressOffset>0x14</addressOffset>
41403 <size>0x20</size>
41404 <access>read-write</access>
41405 <resetValue>0x00000000</resetValue>
41406 <fields>
41407 <field>
41408 <name>TOTALW</name>
41409 <description>Total Width (in units of pixel clock
41410 period)</description>
41411 <bitOffset>16</bitOffset>
41412 <bitWidth>10</bitWidth>
41413 </field>
41414 <field>
41415 <name>TOTALH</name>
41416 <description>Total Height (in units of horizontal
41417 scan line)</description>
41418 <bitOffset>0</bitOffset>
41419 <bitWidth>11</bitWidth>
41420 </field>
41421 </fields>
41422 </register>
41423 <register>
41424 <name>GCR</name>
41425 <displayName>GCR</displayName>
41426 <description>Global Control Register</description>
41427 <addressOffset>0x18</addressOffset>
41428 <size>0x20</size>
41429 <resetValue>0x00002220</resetValue>
41430 <fields>
41431 <field>
41432 <name>HSPOL</name>
41433 <description>Horizontal Synchronization
41434 Polarity</description>
41435 <bitOffset>31</bitOffset>
41436 <bitWidth>1</bitWidth>
41437 <access>read-write</access>
41438 </field>
41439 <field>
41440 <name>VSPOL</name>
41441 <description>Vertical Synchronization
41442 Polarity</description>
41443 <bitOffset>30</bitOffset>
41444 <bitWidth>1</bitWidth>
41445 <access>read-write</access>
41446 </field>
41447 <field>
41448 <name>DEPOL</name>
41449 <description>Data Enable Polarity</description>
41450 <bitOffset>29</bitOffset>
41451 <bitWidth>1</bitWidth>
41452 <access>read-write</access>
41453 </field>
41454 <field>
41455 <name>PCPOL</name>
41456 <description>Pixel Clock Polarity</description>
41457 <bitOffset>28</bitOffset>
41458 <bitWidth>1</bitWidth>
41459 <access>read-write</access>
41460 </field>
41461 <field>
41462 <name>DEN</name>
41463 <description>Dither Enable</description>
41464 <bitOffset>16</bitOffset>
41465 <bitWidth>1</bitWidth>
41466 <access>read-write</access>
41467 </field>
41468 <field>
41469 <name>DRW</name>
41470 <description>Dither Red Width</description>
41471 <bitOffset>12</bitOffset>
41472 <bitWidth>3</bitWidth>
41473 <access>read-only</access>
41474 </field>
41475 <field>
41476 <name>DGW</name>
41477 <description>Dither Green Width</description>
41478 <bitOffset>8</bitOffset>
41479 <bitWidth>3</bitWidth>
41480 <access>read-only</access>
41481 </field>
41482 <field>
41483 <name>DBW</name>
41484 <description>Dither Blue Width</description>
41485 <bitOffset>4</bitOffset>
41486 <bitWidth>3</bitWidth>
41487 <access>read-only</access>
41488 </field>
41489 <field>
41490 <name>LTDCEN</name>
41491 <description>LCD-TFT controller enable
41492 bit</description>
41493 <bitOffset>0</bitOffset>
41494 <bitWidth>1</bitWidth>
41495 <access>read-write</access>
41496 </field>
41497 </fields>
41498 </register>
41499 <register>
41500 <name>SRCR</name>
41501 <displayName>SRCR</displayName>
41502 <description>Shadow Reload Configuration
41503 Register</description>
41504 <addressOffset>0x24</addressOffset>
41505 <size>0x20</size>
41506 <access>read-write</access>
41507 <resetValue>0x00000000</resetValue>
41508 <fields>
41509 <field>
41510 <name>VBR</name>
41511 <description>Vertical Blanking Reload</description>
41512 <bitOffset>1</bitOffset>
41513 <bitWidth>1</bitWidth>
41514 </field>
41515 <field>
41516 <name>IMR</name>
41517 <description>Immediate Reload</description>
41518 <bitOffset>0</bitOffset>
41519 <bitWidth>1</bitWidth>
41520 </field>
41521 </fields>
41522 </register>
41523 <register>
41524 <name>BCCR</name>
41525 <displayName>BCCR</displayName>
41526 <description>Background Color Configuration
41527 Register</description>
41528 <addressOffset>0x2C</addressOffset>
41529 <size>0x20</size>
41530 <access>read-write</access>
41531 <resetValue>0x00000000</resetValue>
41532 <fields>
41533 <field>
41534 <name>BC</name>
41535 <description>Background Color Red value</description>
41536 <bitOffset>0</bitOffset>
41537 <bitWidth>24</bitWidth>
41538 </field>
41539 </fields>
41540 </register>
41541 <register>
41542 <name>IER</name>
41543 <displayName>IER</displayName>
41544 <description>Interrupt Enable Register</description>
41545 <addressOffset>0x34</addressOffset>
41546 <size>0x20</size>
41547 <access>read-write</access>
41548 <resetValue>0x00000000</resetValue>
41549 <fields>
41550 <field>
41551 <name>RRIE</name>
41552 <description>Register Reload interrupt
41553 enable</description>
41554 <bitOffset>3</bitOffset>
41555 <bitWidth>1</bitWidth>
41556 </field>
41557 <field>
41558 <name>TERRIE</name>
41559 <description>Transfer Error Interrupt
41560 Enable</description>
41561 <bitOffset>2</bitOffset>
41562 <bitWidth>1</bitWidth>
41563 </field>
41564 <field>
41565 <name>FUIE</name>
41566 <description>FIFO Underrun Interrupt
41567 Enable</description>
41568 <bitOffset>1</bitOffset>
41569 <bitWidth>1</bitWidth>
41570 </field>
41571 <field>
41572 <name>LIE</name>
41573 <description>Line Interrupt Enable</description>
41574 <bitOffset>0</bitOffset>
41575 <bitWidth>1</bitWidth>
41576 </field>
41577 </fields>
41578 </register>
41579 <register>
41580 <name>ISR</name>
41581 <displayName>ISR</displayName>
41582 <description>Interrupt Status Register</description>
41583 <addressOffset>0x38</addressOffset>
41584 <size>0x20</size>
41585 <access>read-only</access>
41586 <resetValue>0x00000000</resetValue>
41587 <fields>
41588 <field>
41589 <name>RRIF</name>
41590 <description>Register Reload Interrupt
41591 Flag</description>
41592 <bitOffset>3</bitOffset>
41593 <bitWidth>1</bitWidth>
41594 </field>
41595 <field>
41596 <name>TERRIF</name>
41597 <description>Transfer Error interrupt
41598 flag</description>
41599 <bitOffset>2</bitOffset>
41600 <bitWidth>1</bitWidth>
41601 </field>
41602 <field>
41603 <name>FUIF</name>
41604 <description>FIFO Underrun Interrupt
41605 flag</description>
41606 <bitOffset>1</bitOffset>
41607 <bitWidth>1</bitWidth>
41608 </field>
41609 <field>
41610 <name>LIF</name>
41611 <description>Line Interrupt flag</description>
41612 <bitOffset>0</bitOffset>
41613 <bitWidth>1</bitWidth>
41614 </field>
41615 </fields>
41616 </register>
41617 <register>
41618 <name>ICR</name>
41619 <displayName>ICR</displayName>
41620 <description>Interrupt Clear Register</description>
41621 <addressOffset>0x3C</addressOffset>
41622 <size>0x20</size>
41623 <access>write-only</access>
41624 <resetValue>0x00000000</resetValue>
41625 <fields>
41626 <field>
41627 <name>CRRIF</name>
41628 <description>Clears Register Reload Interrupt
41629 Flag</description>
41630 <bitOffset>3</bitOffset>
41631 <bitWidth>1</bitWidth>
41632 </field>
41633 <field>
41634 <name>CTERRIF</name>
41635 <description>Clears the Transfer Error Interrupt
41636 Flag</description>
41637 <bitOffset>2</bitOffset>
41638 <bitWidth>1</bitWidth>
41639 </field>
41640 <field>
41641 <name>CFUIF</name>
41642 <description>Clears the FIFO Underrun Interrupt
41643 flag</description>
41644 <bitOffset>1</bitOffset>
41645 <bitWidth>1</bitWidth>
41646 </field>
41647 <field>
41648 <name>CLIF</name>
41649 <description>Clears the Line Interrupt
41650 Flag</description>
41651 <bitOffset>0</bitOffset>
41652 <bitWidth>1</bitWidth>
41653 </field>
41654 </fields>
41655 </register>
41656 <register>
41657 <name>LIPCR</name>
41658 <displayName>LIPCR</displayName>
41659 <description>Line Interrupt Position Configuration
41660 Register</description>
41661 <addressOffset>0x40</addressOffset>
41662 <size>0x20</size>
41663 <access>read-write</access>
41664 <resetValue>0x00000000</resetValue>
41665 <fields>
41666 <field>
41667 <name>LIPOS</name>
41668 <description>Line Interrupt Position</description>
41669 <bitOffset>0</bitOffset>
41670 <bitWidth>11</bitWidth>
41671 </field>
41672 </fields>
41673 </register>
41674 <register>
41675 <name>CPSR</name>
41676 <displayName>CPSR</displayName>
41677 <description>Current Position Status
41678 Register</description>
41679 <addressOffset>0x44</addressOffset>
41680 <size>0x20</size>
41681 <access>read-only</access>
41682 <resetValue>0x00000000</resetValue>
41683 <fields>
41684 <field>
41685 <name>CXPOS</name>
41686 <description>Current X Position</description>
41687 <bitOffset>16</bitOffset>
41688 <bitWidth>16</bitWidth>
41689 </field>
41690 <field>
41691 <name>CYPOS</name>
41692 <description>Current Y Position</description>
41693 <bitOffset>0</bitOffset>
41694 <bitWidth>16</bitWidth>
41695 </field>
41696 </fields>
41697 </register>
41698 <register>
41699 <name>CDSR</name>
41700 <displayName>CDSR</displayName>
41701 <description>Current Display Status
41702 Register</description>
41703 <addressOffset>0x48</addressOffset>
41704 <size>0x20</size>
41705 <access>read-only</access>
41706 <resetValue>0x0000000F</resetValue>
41707 <fields>
41708 <field>
41709 <name>HSYNCS</name>
41710 <description>Horizontal Synchronization display
41711 Status</description>
41712 <bitOffset>3</bitOffset>
41713 <bitWidth>1</bitWidth>
41714 </field>
41715 <field>
41716 <name>VSYNCS</name>
41717 <description>Vertical Synchronization display
41718 Status</description>
41719 <bitOffset>2</bitOffset>
41720 <bitWidth>1</bitWidth>
41721 </field>
41722 <field>
41723 <name>HDES</name>
41724 <description>Horizontal Data Enable display
41725 Status</description>
41726 <bitOffset>1</bitOffset>
41727 <bitWidth>1</bitWidth>
41728 </field>
41729 <field>
41730 <name>VDES</name>
41731 <description>Vertical Data Enable display
41732 Status</description>
41733 <bitOffset>0</bitOffset>
41734 <bitWidth>1</bitWidth>
41735 </field>
41736 </fields>
41737 </register>
41738 <register>
41739 <name>L1CR</name>
41740 <displayName>L1CR</displayName>
41741 <description>Layerx Control Register</description>
41742 <addressOffset>0x84</addressOffset>
41743 <size>0x20</size>
41744 <access>read-write</access>
41745 <resetValue>0x00000000</resetValue>
41746 <fields>
41747 <field>
41748 <name>CLUTEN</name>
41749 <description>Color Look-Up Table Enable</description>
41750 <bitOffset>4</bitOffset>
41751 <bitWidth>1</bitWidth>
41752 </field>
41753 <field>
41754 <name>COLKEN</name>
41755 <description>Color Keying Enable</description>
41756 <bitOffset>1</bitOffset>
41757 <bitWidth>1</bitWidth>
41758 </field>
41759 <field>
41760 <name>LEN</name>
41761 <description>Layer Enable</description>
41762 <bitOffset>0</bitOffset>
41763 <bitWidth>1</bitWidth>
41764 </field>
41765 </fields>
41766 </register>
41767 <register>
41768 <name>L1WHPCR</name>
41769 <displayName>L1WHPCR</displayName>
41770 <description>Layerx Window Horizontal Position
41771 Configuration Register</description>
41772 <addressOffset>0x88</addressOffset>
41773 <size>0x20</size>
41774 <access>read-write</access>
41775 <resetValue>0x00000000</resetValue>
41776 <fields>
41777 <field>
41778 <name>WHSPPOS</name>
41779 <description>Window Horizontal Stop
41780 Position</description>
41781 <bitOffset>16</bitOffset>
41782 <bitWidth>12</bitWidth>
41783 </field>
41784 <field>
41785 <name>WHSTPOS</name>
41786 <description>Window Horizontal Start
41787 Position</description>
41788 <bitOffset>0</bitOffset>
41789 <bitWidth>12</bitWidth>
41790 </field>
41791 </fields>
41792 </register>
41793 <register>
41794 <name>L1WVPCR</name>
41795 <displayName>L1WVPCR</displayName>
41796 <description>Layerx Window Vertical Position
41797 Configuration Register</description>
41798 <addressOffset>0x8C</addressOffset>
41799 <size>0x20</size>
41800 <access>read-write</access>
41801 <resetValue>0x00000000</resetValue>
41802 <fields>
41803 <field>
41804 <name>WVSPPOS</name>
41805 <description>Window Vertical Stop
41806 Position</description>
41807 <bitOffset>16</bitOffset>
41808 <bitWidth>11</bitWidth>
41809 </field>
41810 <field>
41811 <name>WVSTPOS</name>
41812 <description>Window Vertical Start
41813 Position</description>
41814 <bitOffset>0</bitOffset>
41815 <bitWidth>11</bitWidth>
41816 </field>
41817 </fields>
41818 </register>
41819 <register>
41820 <name>L1CKCR</name>
41821 <displayName>L1CKCR</displayName>
41822 <description>Layerx Color Keying Configuration
41823 Register</description>
41824 <addressOffset>0x90</addressOffset>
41825 <size>0x20</size>
41826 <access>read-write</access>
41827 <resetValue>0x00000000</resetValue>
41828 <fields>
41829 <field>
41830 <name>CKRED</name>
41831 <description>Color Key Red value</description>
41832 <bitOffset>16</bitOffset>
41833 <bitWidth>8</bitWidth>
41834 </field>
41835 <field>
41836 <name>CKGREEN</name>
41837 <description>Color Key Green value</description>
41838 <bitOffset>8</bitOffset>
41839 <bitWidth>8</bitWidth>
41840 </field>
41841 <field>
41842 <name>CKBLUE</name>
41843 <description>Color Key Blue value</description>
41844 <bitOffset>0</bitOffset>
41845 <bitWidth>8</bitWidth>
41846 </field>
41847 </fields>
41848 </register>
41849 <register>
41850 <name>L1PFCR</name>
41851 <displayName>L1PFCR</displayName>
41852 <description>Layerx Pixel Format Configuration
41853 Register</description>
41854 <addressOffset>0x94</addressOffset>
41855 <size>0x20</size>
41856 <access>read-write</access>
41857 <resetValue>0x00000000</resetValue>
41858 <fields>
41859 <field>
41860 <name>PF</name>
41861 <description>Pixel Format</description>
41862 <bitOffset>0</bitOffset>
41863 <bitWidth>3</bitWidth>
41864 </field>
41865 </fields>
41866 </register>
41867 <register>
41868 <name>L1CACR</name>
41869 <displayName>L1CACR</displayName>
41870 <description>Layerx Constant Alpha Configuration
41871 Register</description>
41872 <addressOffset>0x98</addressOffset>
41873 <size>0x20</size>
41874 <access>read-write</access>
41875 <resetValue>0x00000000</resetValue>
41876 <fields>
41877 <field>
41878 <name>CONSTA</name>
41879 <description>Constant Alpha</description>
41880 <bitOffset>0</bitOffset>
41881 <bitWidth>8</bitWidth>
41882 </field>
41883 </fields>
41884 </register>
41885 <register>
41886 <name>L1DCCR</name>
41887 <displayName>L1DCCR</displayName>
41888 <description>Layerx Default Color Configuration
41889 Register</description>
41890 <addressOffset>0x9C</addressOffset>
41891 <size>0x20</size>
41892 <access>read-write</access>
41893 <resetValue>0x00000000</resetValue>
41894 <fields>
41895 <field>
41896 <name>DCALPHA</name>
41897 <description>Default Color Alpha</description>
41898 <bitOffset>24</bitOffset>
41899 <bitWidth>8</bitWidth>
41900 </field>
41901 <field>
41902 <name>DCRED</name>
41903 <description>Default Color Red</description>
41904 <bitOffset>16</bitOffset>
41905 <bitWidth>8</bitWidth>
41906 </field>
41907 <field>
41908 <name>DCGREEN</name>
41909 <description>Default Color Green</description>
41910 <bitOffset>8</bitOffset>
41911 <bitWidth>8</bitWidth>
41912 </field>
41913 <field>
41914 <name>DCBLUE</name>
41915 <description>Default Color Blue</description>
41916 <bitOffset>0</bitOffset>
41917 <bitWidth>8</bitWidth>
41918 </field>
41919 </fields>
41920 </register>
41921 <register>
41922 <name>L1BFCR</name>
41923 <displayName>L1BFCR</displayName>
41924 <description>Layerx Blending Factors Configuration
41925 Register</description>
41926 <addressOffset>0xA0</addressOffset>
41927 <size>0x20</size>
41928 <access>read-write</access>
41929 <resetValue>0x00000607</resetValue>
41930 <fields>
41931 <field>
41932 <name>BF1</name>
41933 <description>Blending Factor 1</description>
41934 <bitOffset>8</bitOffset>
41935 <bitWidth>3</bitWidth>
41936 </field>
41937 <field>
41938 <name>BF2</name>
41939 <description>Blending Factor 2</description>
41940 <bitOffset>0</bitOffset>
41941 <bitWidth>3</bitWidth>
41942 </field>
41943 </fields>
41944 </register>
41945 <register>
41946 <name>L1CFBAR</name>
41947 <displayName>L1CFBAR</displayName>
41948 <description>Layerx Color Frame Buffer Address
41949 Register</description>
41950 <addressOffset>0xAC</addressOffset>
41951 <size>0x20</size>
41952 <access>read-write</access>
41953 <resetValue>0x00000000</resetValue>
41954 <fields>
41955 <field>
41956 <name>CFBADD</name>
41957 <description>Color Frame Buffer Start
41958 Address</description>
41959 <bitOffset>0</bitOffset>
41960 <bitWidth>32</bitWidth>
41961 </field>
41962 </fields>
41963 </register>
41964 <register>
41965 <name>L1CFBLR</name>
41966 <displayName>L1CFBLR</displayName>
41967 <description>Layerx Color Frame Buffer Length
41968 Register</description>
41969 <addressOffset>0xB0</addressOffset>
41970 <size>0x20</size>
41971 <access>read-write</access>
41972 <resetValue>0x00000000</resetValue>
41973 <fields>
41974 <field>
41975 <name>CFBP</name>
41976 <description>Color Frame Buffer Pitch in
41977 bytes</description>
41978 <bitOffset>16</bitOffset>
41979 <bitWidth>13</bitWidth>
41980 </field>
41981 <field>
41982 <name>CFBLL</name>
41983 <description>Color Frame Buffer Line
41984 Length</description>
41985 <bitOffset>0</bitOffset>
41986 <bitWidth>13</bitWidth>
41987 </field>
41988 </fields>
41989 </register>
41990 <register>
41991 <name>L1CFBLNR</name>
41992 <displayName>L1CFBLNR</displayName>
41993 <description>Layerx ColorFrame Buffer Line Number
41994 Register</description>
41995 <addressOffset>0xB4</addressOffset>
41996 <size>0x20</size>
41997 <access>read-write</access>
41998 <resetValue>0x00000000</resetValue>
41999 <fields>
42000 <field>
42001 <name>CFBLNBR</name>
42002 <description>Frame Buffer Line Number</description>
42003 <bitOffset>0</bitOffset>
42004 <bitWidth>11</bitWidth>
42005 </field>
42006 </fields>
42007 </register>
42008 <register>
42009 <name>L1CLUTWR</name>
42010 <displayName>L1CLUTWR</displayName>
42011 <description>Layerx CLUT Write Register</description>
42012 <addressOffset>0xC4</addressOffset>
42013 <size>0x20</size>
42014 <access>write-only</access>
42015 <resetValue>0x00000000</resetValue>
42016 <fields>
42017 <field>
42018 <name>CLUTADD</name>
42019 <description>CLUT Address</description>
42020 <bitOffset>24</bitOffset>
42021 <bitWidth>8</bitWidth>
42022 </field>
42023 <field>
42024 <name>RED</name>
42025 <description>Red value</description>
42026 <bitOffset>16</bitOffset>
42027 <bitWidth>8</bitWidth>
42028 </field>
42029 <field>
42030 <name>GREEN</name>
42031 <description>Green value</description>
42032 <bitOffset>8</bitOffset>
42033 <bitWidth>8</bitWidth>
42034 </field>
42035 <field>
42036 <name>BLUE</name>
42037 <description>Blue value</description>
42038 <bitOffset>0</bitOffset>
42039 <bitWidth>8</bitWidth>
42040 </field>
42041 </fields>
42042 </register>
42043 <register>
42044 <name>L2CR</name>
42045 <displayName>L2CR</displayName>
42046 <description>Layerx Control Register</description>
42047 <addressOffset>0x104</addressOffset>
42048 <size>0x20</size>
42049 <access>read-write</access>
42050 <resetValue>0x00000000</resetValue>
42051 <fields>
42052 <field>
42053 <name>CLUTEN</name>
42054 <description>Color Look-Up Table Enable</description>
42055 <bitOffset>4</bitOffset>
42056 <bitWidth>1</bitWidth>
42057 </field>
42058 <field>
42059 <name>COLKEN</name>
42060 <description>Color Keying Enable</description>
42061 <bitOffset>1</bitOffset>
42062 <bitWidth>1</bitWidth>
42063 </field>
42064 <field>
42065 <name>LEN</name>
42066 <description>Layer Enable</description>
42067 <bitOffset>0</bitOffset>
42068 <bitWidth>1</bitWidth>
42069 </field>
42070 </fields>
42071 </register>
42072 <register>
42073 <name>L2WHPCR</name>
42074 <displayName>L2WHPCR</displayName>
42075 <description>Layerx Window Horizontal Position
42076 Configuration Register</description>
42077 <addressOffset>0x108</addressOffset>
42078 <size>0x20</size>
42079 <access>read-write</access>
42080 <resetValue>0x00000000</resetValue>
42081 <fields>
42082 <field>
42083 <name>WHSPPOS</name>
42084 <description>Window Horizontal Stop
42085 Position</description>
42086 <bitOffset>16</bitOffset>
42087 <bitWidth>12</bitWidth>
42088 </field>
42089 <field>
42090 <name>WHSTPOS</name>
42091 <description>Window Horizontal Start
42092 Position</description>
42093 <bitOffset>0</bitOffset>
42094 <bitWidth>12</bitWidth>
42095 </field>
42096 </fields>
42097 </register>
42098 <register>
42099 <name>L2WVPCR</name>
42100 <displayName>L2WVPCR</displayName>
42101 <description>Layerx Window Vertical Position
42102 Configuration Register</description>
42103 <addressOffset>0x10C</addressOffset>
42104 <size>0x20</size>
42105 <access>read-write</access>
42106 <resetValue>0x00000000</resetValue>
42107 <fields>
42108 <field>
42109 <name>WVSPPOS</name>
42110 <description>Window Vertical Stop
42111 Position</description>
42112 <bitOffset>16</bitOffset>
42113 <bitWidth>11</bitWidth>
42114 </field>
42115 <field>
42116 <name>WVSTPOS</name>
42117 <description>Window Vertical Start
42118 Position</description>
42119 <bitOffset>0</bitOffset>
42120 <bitWidth>11</bitWidth>
42121 </field>
42122 </fields>
42123 </register>
42124 <register>
42125 <name>L2CKCR</name>
42126 <displayName>L2CKCR</displayName>
42127 <description>Layerx Color Keying Configuration
42128 Register</description>
42129 <addressOffset>0x110</addressOffset>
42130 <size>0x20</size>
42131 <access>read-write</access>
42132 <resetValue>0x00000000</resetValue>
42133 <fields>
42134 <field>
42135 <name>CKRED</name>
42136 <description>Color Key Red value</description>
42137 <bitOffset>15</bitOffset>
42138 <bitWidth>9</bitWidth>
42139 </field>
42140 <field>
42141 <name>CKGREEN</name>
42142 <description>Color Key Green value</description>
42143 <bitOffset>8</bitOffset>
42144 <bitWidth>7</bitWidth>
42145 </field>
42146 <field>
42147 <name>CKBLUE</name>
42148 <description>Color Key Blue value</description>
42149 <bitOffset>0</bitOffset>
42150 <bitWidth>8</bitWidth>
42151 </field>
42152 </fields>
42153 </register>
42154 <register>
42155 <name>L2PFCR</name>
42156 <displayName>L2PFCR</displayName>
42157 <description>Layerx Pixel Format Configuration
42158 Register</description>
42159 <addressOffset>0x114</addressOffset>
42160 <size>0x20</size>
42161 <access>read-write</access>
42162 <resetValue>0x00000000</resetValue>
42163 <fields>
42164 <field>
42165 <name>PF</name>
42166 <description>Pixel Format</description>
42167 <bitOffset>0</bitOffset>
42168 <bitWidth>3</bitWidth>
42169 </field>
42170 </fields>
42171 </register>
42172 <register>
42173 <name>L2CACR</name>
42174 <displayName>L2CACR</displayName>
42175 <description>Layerx Constant Alpha Configuration
42176 Register</description>
42177 <addressOffset>0x118</addressOffset>
42178 <size>0x20</size>
42179 <access>read-write</access>
42180 <resetValue>0x00000000</resetValue>
42181 <fields>
42182 <field>
42183 <name>CONSTA</name>
42184 <description>Constant Alpha</description>
42185 <bitOffset>0</bitOffset>
42186 <bitWidth>8</bitWidth>
42187 </field>
42188 </fields>
42189 </register>
42190 <register>
42191 <name>L2DCCR</name>
42192 <displayName>L2DCCR</displayName>
42193 <description>Layerx Default Color Configuration
42194 Register</description>
42195 <addressOffset>0x11C</addressOffset>
42196 <size>0x20</size>
42197 <access>read-write</access>
42198 <resetValue>0x00000000</resetValue>
42199 <fields>
42200 <field>
42201 <name>DCALPHA</name>
42202 <description>Default Color Alpha</description>
42203 <bitOffset>24</bitOffset>
42204 <bitWidth>8</bitWidth>
42205 </field>
42206 <field>
42207 <name>DCRED</name>
42208 <description>Default Color Red</description>
42209 <bitOffset>16</bitOffset>
42210 <bitWidth>8</bitWidth>
42211 </field>
42212 <field>
42213 <name>DCGREEN</name>
42214 <description>Default Color Green</description>
42215 <bitOffset>8</bitOffset>
42216 <bitWidth>8</bitWidth>
42217 </field>
42218 <field>
42219 <name>DCBLUE</name>
42220 <description>Default Color Blue</description>
42221 <bitOffset>0</bitOffset>
42222 <bitWidth>8</bitWidth>
42223 </field>
42224 </fields>
42225 </register>
42226 <register>
42227 <name>L2BFCR</name>
42228 <displayName>L2BFCR</displayName>
42229 <description>Layerx Blending Factors Configuration
42230 Register</description>
42231 <addressOffset>0x120</addressOffset>
42232 <size>0x20</size>
42233 <access>read-write</access>
42234 <resetValue>0x00000607</resetValue>
42235 <fields>
42236 <field>
42237 <name>BF1</name>
42238 <description>Blending Factor 1</description>
42239 <bitOffset>8</bitOffset>
42240 <bitWidth>3</bitWidth>
42241 </field>
42242 <field>
42243 <name>BF2</name>
42244 <description>Blending Factor 2</description>
42245 <bitOffset>0</bitOffset>
42246 <bitWidth>3</bitWidth>
42247 </field>
42248 </fields>
42249 </register>
42250 <register>
42251 <name>L2CFBAR</name>
42252 <displayName>L2CFBAR</displayName>
42253 <description>Layerx Color Frame Buffer Address
42254 Register</description>
42255 <addressOffset>0x12C</addressOffset>
42256 <size>0x20</size>
42257 <access>read-write</access>
42258 <resetValue>0x00000000</resetValue>
42259 <fields>
42260 <field>
42261 <name>CFBADD</name>
42262 <description>Color Frame Buffer Start
42263 Address</description>
42264 <bitOffset>0</bitOffset>
42265 <bitWidth>32</bitWidth>
42266 </field>
42267 </fields>
42268 </register>
42269 <register>
42270 <name>L2CFBLR</name>
42271 <displayName>L2CFBLR</displayName>
42272 <description>Layerx Color Frame Buffer Length
42273 Register</description>
42274 <addressOffset>0x130</addressOffset>
42275 <size>0x20</size>
42276 <access>read-write</access>
42277 <resetValue>0x00000000</resetValue>
42278 <fields>
42279 <field>
42280 <name>CFBP</name>
42281 <description>Color Frame Buffer Pitch in
42282 bytes</description>
42283 <bitOffset>16</bitOffset>
42284 <bitWidth>13</bitWidth>
42285 </field>
42286 <field>
42287 <name>CFBLL</name>
42288 <description>Color Frame Buffer Line
42289 Length</description>
42290 <bitOffset>0</bitOffset>
42291 <bitWidth>13</bitWidth>
42292 </field>
42293 </fields>
42294 </register>
42295 <register>
42296 <name>L2CFBLNR</name>
42297 <displayName>L2CFBLNR</displayName>
42298 <description>Layerx ColorFrame Buffer Line Number
42299 Register</description>
42300 <addressOffset>0x134</addressOffset>
42301 <size>0x20</size>
42302 <access>read-write</access>
42303 <resetValue>0x00000000</resetValue>
42304 <fields>
42305 <field>
42306 <name>CFBLNBR</name>
42307 <description>Frame Buffer Line Number</description>
42308 <bitOffset>0</bitOffset>
42309 <bitWidth>11</bitWidth>
42310 </field>
42311 </fields>
42312 </register>
42313 <register>
42314 <name>L2CLUTWR</name>
42315 <displayName>L2CLUTWR</displayName>
42316 <description>Layerx CLUT Write Register</description>
42317 <addressOffset>0x144</addressOffset>
42318 <size>0x20</size>
42319 <access>write-only</access>
42320 <resetValue>0x00000000</resetValue>
42321 <fields>
42322 <field>
42323 <name>CLUTADD</name>
42324 <description>CLUT Address</description>
42325 <bitOffset>24</bitOffset>
42326 <bitWidth>8</bitWidth>
42327 </field>
42328 <field>
42329 <name>RED</name>
42330 <description>Red value</description>
42331 <bitOffset>16</bitOffset>
42332 <bitWidth>8</bitWidth>
42333 </field>
42334 <field>
42335 <name>GREEN</name>
42336 <description>Green value</description>
42337 <bitOffset>8</bitOffset>
42338 <bitWidth>8</bitWidth>
42339 </field>
42340 <field>
42341 <name>BLUE</name>
42342 <description>Blue value</description>
42343 <bitOffset>0</bitOffset>
42344 <bitWidth>8</bitWidth>
42345 </field>
42346 </fields>
42347 </register>
42348 </registers>
42349 </peripheral>
42350 <peripheral>
42351 <name>SAI1</name>
42352 <description>Serial audio interface</description>
42353 <groupName>SAI</groupName>
42354 <baseAddress>0x40015800</baseAddress>
42355 <addressBlock>
42356 <offset>0x0</offset>
42357 <size>0x400</size>
42358 <usage>registers</usage>
42359 </addressBlock>
42360 <interrupt>
42361 <name>SAI1</name>
42362 <description>SAI1 global interrupt</description>
42363 <value>87</value>
42364 </interrupt>
42365 <registers>
42366 <register>
42367 <name>BCR1</name>
42368 <displayName>BCR1</displayName>
42369 <description>BConfiguration register 1</description>
42370 <addressOffset>0x24</addressOffset>
42371 <size>0x20</size>
42372 <access>read-write</access>
42373 <resetValue>0x00000040</resetValue>
42374 <fields>
42375 <field>
42376 <name>MCJDIV</name>
42377 <description>Master clock divider</description>
42378 <bitOffset>20</bitOffset>
42379 <bitWidth>4</bitWidth>
42380 </field>
42381 <field>
42382 <name>NODIV</name>
42383 <description>No divider</description>
42384 <bitOffset>19</bitOffset>
42385 <bitWidth>1</bitWidth>
42386 </field>
42387 <field>
42388 <name>DMAEN</name>
42389 <description>DMA enable</description>
42390 <bitOffset>17</bitOffset>
42391 <bitWidth>1</bitWidth>
42392 </field>
42393 <field>
42394 <name>SAIBEN</name>
42395 <description>Audio block B enable</description>
42396 <bitOffset>16</bitOffset>
42397 <bitWidth>1</bitWidth>
42398 </field>
42399 <field>
42400 <name>OutDri</name>
42401 <description>Output drive</description>
42402 <bitOffset>13</bitOffset>
42403 <bitWidth>1</bitWidth>
42404 </field>
42405 <field>
42406 <name>MONO</name>
42407 <description>Mono mode</description>
42408 <bitOffset>12</bitOffset>
42409 <bitWidth>1</bitWidth>
42410 </field>
42411 <field>
42412 <name>SYNCEN</name>
42413 <description>Synchronization enable</description>
42414 <bitOffset>10</bitOffset>
42415 <bitWidth>2</bitWidth>
42416 </field>
42417 <field>
42418 <name>CKSTR</name>
42419 <description>Clock strobing edge</description>
42420 <bitOffset>9</bitOffset>
42421 <bitWidth>1</bitWidth>
42422 </field>
42423 <field>
42424 <name>LSBFIRST</name>
42425 <description>Least significant bit
42426 first</description>
42427 <bitOffset>8</bitOffset>
42428 <bitWidth>1</bitWidth>
42429 </field>
42430 <field>
42431 <name>DS</name>
42432 <description>Data size</description>
42433 <bitOffset>5</bitOffset>
42434 <bitWidth>3</bitWidth>
42435 </field>
42436 <field>
42437 <name>PRTCFG</name>
42438 <description>Protocol configuration</description>
42439 <bitOffset>2</bitOffset>
42440 <bitWidth>2</bitWidth>
42441 </field>
42442 <field>
42443 <name>MODE</name>
42444 <description>Audio block mode</description>
42445 <bitOffset>0</bitOffset>
42446 <bitWidth>2</bitWidth>
42447 </field>
42448 </fields>
42449 </register>
42450 <register>
42451 <name>BCR2</name>
42452 <displayName>BCR2</displayName>
42453 <description>BConfiguration register 2</description>
42454 <addressOffset>0x28</addressOffset>
42455 <size>0x20</size>
42456 <access>read-write</access>
42457 <resetValue>0x00000000</resetValue>
42458 <fields>
42459 <field>
42460 <name>COMP</name>
42461 <description>Companding mode</description>
42462 <bitOffset>14</bitOffset>
42463 <bitWidth>2</bitWidth>
42464 </field>
42465 <field>
42466 <name>CPL</name>
42467 <description>Complement bit</description>
42468 <bitOffset>13</bitOffset>
42469 <bitWidth>1</bitWidth>
42470 </field>
42471 <field>
42472 <name>MUTECN</name>
42473 <description>Mute counter</description>
42474 <bitOffset>7</bitOffset>
42475 <bitWidth>6</bitWidth>
42476 </field>
42477 <field>
42478 <name>MUTEVAL</name>
42479 <description>Mute value</description>
42480 <bitOffset>6</bitOffset>
42481 <bitWidth>1</bitWidth>
42482 </field>
42483 <field>
42484 <name>MUTE</name>
42485 <description>Mute</description>
42486 <bitOffset>5</bitOffset>
42487 <bitWidth>1</bitWidth>
42488 </field>
42489 <field>
42490 <name>TRIS</name>
42491 <description>Tristate management on data
42492 line</description>
42493 <bitOffset>4</bitOffset>
42494 <bitWidth>1</bitWidth>
42495 </field>
42496 <field>
42497 <name>FFLUS</name>
42498 <description>FIFO flush</description>
42499 <bitOffset>3</bitOffset>
42500 <bitWidth>1</bitWidth>
42501 </field>
42502 <field>
42503 <name>FTH</name>
42504 <description>FIFO threshold</description>
42505 <bitOffset>0</bitOffset>
42506 <bitWidth>3</bitWidth>
42507 </field>
42508 </fields>
42509 </register>
42510 <register>
42511 <name>BFRCR</name>
42512 <displayName>BFRCR</displayName>
42513 <description>BFRCR</description>
42514 <addressOffset>0x2C</addressOffset>
42515 <size>0x20</size>
42516 <access>read-write</access>
42517 <resetValue>0x00000007</resetValue>
42518 <fields>
42519 <field>
42520 <name>FSOFF</name>
42521 <description>Frame synchronization
42522 offset</description>
42523 <bitOffset>18</bitOffset>
42524 <bitWidth>1</bitWidth>
42525 </field>
42526 <field>
42527 <name>FSPOL</name>
42528 <description>Frame synchronization
42529 polarity</description>
42530 <bitOffset>17</bitOffset>
42531 <bitWidth>1</bitWidth>
42532 </field>
42533 <field>
42534 <name>FSDEF</name>
42535 <description>Frame synchronization
42536 definition</description>
42537 <bitOffset>16</bitOffset>
42538 <bitWidth>1</bitWidth>
42539 </field>
42540 <field>
42541 <name>FSALL</name>
42542 <description>Frame synchronization active level
42543 length</description>
42544 <bitOffset>8</bitOffset>
42545 <bitWidth>7</bitWidth>
42546 </field>
42547 <field>
42548 <name>FRL</name>
42549 <description>Frame length</description>
42550 <bitOffset>0</bitOffset>
42551 <bitWidth>8</bitWidth>
42552 </field>
42553 </fields>
42554 </register>
42555 <register>
42556 <name>BSLOTR</name>
42557 <displayName>BSLOTR</displayName>
42558 <description>BSlot register</description>
42559 <addressOffset>0x30</addressOffset>
42560 <size>0x20</size>
42561 <access>read-write</access>
42562 <resetValue>0x00000000</resetValue>
42563 <fields>
42564 <field>
42565 <name>SLOTEN</name>
42566 <description>Slot enable</description>
42567 <bitOffset>16</bitOffset>
42568 <bitWidth>16</bitWidth>
42569 </field>
42570 <field>
42571 <name>NBSLOT</name>
42572 <description>Number of slots in an audio
42573 frame</description>
42574 <bitOffset>8</bitOffset>
42575 <bitWidth>4</bitWidth>
42576 </field>
42577 <field>
42578 <name>SLOTSZ</name>
42579 <description>Slot size</description>
42580 <bitOffset>6</bitOffset>
42581 <bitWidth>2</bitWidth>
42582 </field>
42583 <field>
42584 <name>FBOFF</name>
42585 <description>First bit offset</description>
42586 <bitOffset>0</bitOffset>
42587 <bitWidth>5</bitWidth>
42588 </field>
42589 </fields>
42590 </register>
42591 <register>
42592 <name>BIM</name>
42593 <displayName>BIM</displayName>
42594 <description>BInterrupt mask register2</description>
42595 <addressOffset>0x34</addressOffset>
42596 <size>0x20</size>
42597 <access>read-write</access>
42598 <resetValue>0x00000000</resetValue>
42599 <fields>
42600 <field>
42601 <name>LFSDETIE</name>
42602 <description>Late frame synchronization detection
42603 interrupt enable</description>
42604 <bitOffset>6</bitOffset>
42605 <bitWidth>1</bitWidth>
42606 </field>
42607 <field>
42608 <name>AFSDETIE</name>
42609 <description>Anticipated frame synchronization
42610 detection interrupt enable</description>
42611 <bitOffset>5</bitOffset>
42612 <bitWidth>1</bitWidth>
42613 </field>
42614 <field>
42615 <name>CNRDYIE</name>
42616 <description>Codec not ready interrupt
42617 enable</description>
42618 <bitOffset>4</bitOffset>
42619 <bitWidth>1</bitWidth>
42620 </field>
42621 <field>
42622 <name>FREQIE</name>
42623 <description>FIFO request interrupt
42624 enable</description>
42625 <bitOffset>3</bitOffset>
42626 <bitWidth>1</bitWidth>
42627 </field>
42628 <field>
42629 <name>WCKCFG</name>
42630 <description>Wrong clock configuration interrupt
42631 enable</description>
42632 <bitOffset>2</bitOffset>
42633 <bitWidth>1</bitWidth>
42634 </field>
42635 <field>
42636 <name>MUTEDET</name>
42637 <description>Mute detection interrupt
42638 enable</description>
42639 <bitOffset>1</bitOffset>
42640 <bitWidth>1</bitWidth>
42641 </field>
42642 <field>
42643 <name>OVRUDRIE</name>
42644 <description>Overrun/underrun interrupt
42645 enable</description>
42646 <bitOffset>0</bitOffset>
42647 <bitWidth>1</bitWidth>
42648 </field>
42649 </fields>
42650 </register>
42651 <register>
42652 <name>BSR</name>
42653 <displayName>BSR</displayName>
42654 <description>BStatus register</description>
42655 <addressOffset>0x38</addressOffset>
42656 <size>0x20</size>
42657 <access>read-only</access>
42658 <resetValue>0x00000000</resetValue>
42659 <fields>
42660 <field>
42661 <name>FLVL</name>
42662 <description>FIFO level threshold</description>
42663 <bitOffset>16</bitOffset>
42664 <bitWidth>3</bitWidth>
42665 </field>
42666 <field>
42667 <name>LFSDET</name>
42668 <description>Late frame synchronization
42669 detection</description>
42670 <bitOffset>6</bitOffset>
42671 <bitWidth>1</bitWidth>
42672 </field>
42673 <field>
42674 <name>AFSDET</name>
42675 <description>Anticipated frame synchronization
42676 detection</description>
42677 <bitOffset>5</bitOffset>
42678 <bitWidth>1</bitWidth>
42679 </field>
42680 <field>
42681 <name>CNRDY</name>
42682 <description>Codec not ready</description>
42683 <bitOffset>4</bitOffset>
42684 <bitWidth>1</bitWidth>
42685 </field>
42686 <field>
42687 <name>FREQ</name>
42688 <description>FIFO request</description>
42689 <bitOffset>3</bitOffset>
42690 <bitWidth>1</bitWidth>
42691 </field>
42692 <field>
42693 <name>WCKCFG</name>
42694 <description>Wrong clock configuration
42695 flag</description>
42696 <bitOffset>2</bitOffset>
42697 <bitWidth>1</bitWidth>
42698 </field>
42699 <field>
42700 <name>MUTEDET</name>
42701 <description>Mute detection</description>
42702 <bitOffset>1</bitOffset>
42703 <bitWidth>1</bitWidth>
42704 </field>
42705 <field>
42706 <name>OVRUDR</name>
42707 <description>Overrun / underrun</description>
42708 <bitOffset>0</bitOffset>
42709 <bitWidth>1</bitWidth>
42710 </field>
42711 </fields>
42712 </register>
42713 <register>
42714 <name>BCLRFR</name>
42715 <displayName>BCLRFR</displayName>
42716 <description>BClear flag register</description>
42717 <addressOffset>0x3C</addressOffset>
42718 <size>0x20</size>
42719 <access>write-only</access>
42720 <resetValue>0x00000000</resetValue>
42721 <fields>
42722 <field>
42723 <name>LFSDET</name>
42724 <description>Clear late frame synchronization
42725 detection flag</description>
42726 <bitOffset>6</bitOffset>
42727 <bitWidth>1</bitWidth>
42728 </field>
42729 <field>
42730 <name>CAFSDET</name>
42731 <description>Clear anticipated frame synchronization
42732 detection flag</description>
42733 <bitOffset>5</bitOffset>
42734 <bitWidth>1</bitWidth>
42735 </field>
42736 <field>
42737 <name>CNRDY</name>
42738 <description>Clear codec not ready flag</description>
42739 <bitOffset>4</bitOffset>
42740 <bitWidth>1</bitWidth>
42741 </field>
42742 <field>
42743 <name>WCKCFG</name>
42744 <description>Clear wrong clock configuration
42745 flag</description>
42746 <bitOffset>2</bitOffset>
42747 <bitWidth>1</bitWidth>
42748 </field>
42749 <field>
42750 <name>MUTEDET</name>
42751 <description>Mute detection flag</description>
42752 <bitOffset>1</bitOffset>
42753 <bitWidth>1</bitWidth>
42754 </field>
42755 <field>
42756 <name>OVRUDR</name>
42757 <description>Clear overrun / underrun</description>
42758 <bitOffset>0</bitOffset>
42759 <bitWidth>1</bitWidth>
42760 </field>
42761 </fields>
42762 </register>
42763 <register>
42764 <name>BDR</name>
42765 <displayName>BDR</displayName>
42766 <description>BData register</description>
42767 <addressOffset>0x40</addressOffset>
42768 <size>0x20</size>
42769 <access>read-write</access>
42770 <resetValue>0x00000000</resetValue>
42771 <fields>
42772 <field>
42773 <name>DATA</name>
42774 <description>Data</description>
42775 <bitOffset>0</bitOffset>
42776 <bitWidth>32</bitWidth>
42777 </field>
42778 </fields>
42779 </register>
42780 <register>
42781 <name>ACR1</name>
42782 <displayName>ACR1</displayName>
42783 <description>AConfiguration register 1</description>
42784 <addressOffset>0x4</addressOffset>
42785 <size>0x20</size>
42786 <access>read-write</access>
42787 <resetValue>0x00000040</resetValue>
42788 <fields>
42789 <field>
42790 <name>MCJDIV</name>
42791 <description>Master clock divider</description>
42792 <bitOffset>20</bitOffset>
42793 <bitWidth>4</bitWidth>
42794 </field>
42795 <field>
42796 <name>NODIV</name>
42797 <description>No divider</description>
42798 <bitOffset>19</bitOffset>
42799 <bitWidth>1</bitWidth>
42800 </field>
42801 <field>
42802 <name>DMAEN</name>
42803 <description>DMA enable</description>
42804 <bitOffset>17</bitOffset>
42805 <bitWidth>1</bitWidth>
42806 </field>
42807 <field>
42808 <name>SAIAEN</name>
42809 <description>Audio block A enable</description>
42810 <bitOffset>16</bitOffset>
42811 <bitWidth>1</bitWidth>
42812 </field>
42813 <field>
42814 <name>OutDri</name>
42815 <description>Output drive</description>
42816 <bitOffset>13</bitOffset>
42817 <bitWidth>1</bitWidth>
42818 </field>
42819 <field>
42820 <name>MONO</name>
42821 <description>Mono mode</description>
42822 <bitOffset>12</bitOffset>
42823 <bitWidth>1</bitWidth>
42824 </field>
42825 <field>
42826 <name>SYNCEN</name>
42827 <description>Synchronization enable</description>
42828 <bitOffset>10</bitOffset>
42829 <bitWidth>2</bitWidth>
42830 </field>
42831 <field>
42832 <name>CKSTR</name>
42833 <description>Clock strobing edge</description>
42834 <bitOffset>9</bitOffset>
42835 <bitWidth>1</bitWidth>
42836 </field>
42837 <field>
42838 <name>LSBFIRST</name>
42839 <description>Least significant bit
42840 first</description>
42841 <bitOffset>8</bitOffset>
42842 <bitWidth>1</bitWidth>
42843 </field>
42844 <field>
42845 <name>DS</name>
42846 <description>Data size</description>
42847 <bitOffset>5</bitOffset>
42848 <bitWidth>3</bitWidth>
42849 </field>
42850 <field>
42851 <name>PRTCFG</name>
42852 <description>Protocol configuration</description>
42853 <bitOffset>2</bitOffset>
42854 <bitWidth>2</bitWidth>
42855 </field>
42856 <field>
42857 <name>MODE</name>
42858 <description>Audio block mode</description>
42859 <bitOffset>0</bitOffset>
42860 <bitWidth>2</bitWidth>
42861 </field>
42862 </fields>
42863 </register>
42864 <register>
42865 <name>ACR2</name>
42866 <displayName>ACR2</displayName>
42867 <description>AConfiguration register 2</description>
42868 <addressOffset>0x8</addressOffset>
42869 <size>0x20</size>
42870 <access>read-write</access>
42871 <resetValue>0x00000000</resetValue>
42872 <fields>
42873 <field>
42874 <name>COMP</name>
42875 <description>Companding mode</description>
42876 <bitOffset>14</bitOffset>
42877 <bitWidth>2</bitWidth>
42878 </field>
42879 <field>
42880 <name>CPL</name>
42881 <description>Complement bit</description>
42882 <bitOffset>13</bitOffset>
42883 <bitWidth>1</bitWidth>
42884 </field>
42885 <field>
42886 <name>MUTECN</name>
42887 <description>Mute counter</description>
42888 <bitOffset>7</bitOffset>
42889 <bitWidth>6</bitWidth>
42890 </field>
42891 <field>
42892 <name>MUTEVAL</name>
42893 <description>Mute value</description>
42894 <bitOffset>6</bitOffset>
42895 <bitWidth>1</bitWidth>
42896 </field>
42897 <field>
42898 <name>MUTE</name>
42899 <description>Mute</description>
42900 <bitOffset>5</bitOffset>
42901 <bitWidth>1</bitWidth>
42902 </field>
42903 <field>
42904 <name>TRIS</name>
42905 <description>Tristate management on data
42906 line</description>
42907 <bitOffset>4</bitOffset>
42908 <bitWidth>1</bitWidth>
42909 </field>
42910 <field>
42911 <name>FFLUS</name>
42912 <description>FIFO flush</description>
42913 <bitOffset>3</bitOffset>
42914 <bitWidth>1</bitWidth>
42915 </field>
42916 <field>
42917 <name>FTH</name>
42918 <description>FIFO threshold</description>
42919 <bitOffset>0</bitOffset>
42920 <bitWidth>3</bitWidth>
42921 </field>
42922 </fields>
42923 </register>
42924 <register>
42925 <name>AFRCR</name>
42926 <displayName>AFRCR</displayName>
42927 <description>AFRCR</description>
42928 <addressOffset>0xC</addressOffset>
42929 <size>0x20</size>
42930 <access>read-write</access>
42931 <resetValue>0x00000007</resetValue>
42932 <fields>
42933 <field>
42934 <name>FSOFF</name>
42935 <description>Frame synchronization
42936 offset</description>
42937 <bitOffset>18</bitOffset>
42938 <bitWidth>1</bitWidth>
42939 </field>
42940 <field>
42941 <name>FSPOL</name>
42942 <description>Frame synchronization
42943 polarity</description>
42944 <bitOffset>17</bitOffset>
42945 <bitWidth>1</bitWidth>
42946 </field>
42947 <field>
42948 <name>FSDEF</name>
42949 <description>Frame synchronization
42950 definition</description>
42951 <bitOffset>16</bitOffset>
42952 <bitWidth>1</bitWidth>
42953 </field>
42954 <field>
42955 <name>FSALL</name>
42956 <description>Frame synchronization active level
42957 length</description>
42958 <bitOffset>8</bitOffset>
42959 <bitWidth>7</bitWidth>
42960 </field>
42961 <field>
42962 <name>FRL</name>
42963 <description>Frame length</description>
42964 <bitOffset>0</bitOffset>
42965 <bitWidth>8</bitWidth>
42966 </field>
42967 </fields>
42968 </register>
42969 <register>
42970 <name>ASLOTR</name>
42971 <displayName>ASLOTR</displayName>
42972 <description>ASlot register</description>
42973 <addressOffset>0x10</addressOffset>
42974 <size>0x20</size>
42975 <access>read-write</access>
42976 <resetValue>0x00000000</resetValue>
42977 <fields>
42978 <field>
42979 <name>SLOTEN</name>
42980 <description>Slot enable</description>
42981 <bitOffset>16</bitOffset>
42982 <bitWidth>16</bitWidth>
42983 </field>
42984 <field>
42985 <name>NBSLOT</name>
42986 <description>Number of slots in an audio
42987 frame</description>
42988 <bitOffset>8</bitOffset>
42989 <bitWidth>4</bitWidth>
42990 </field>
42991 <field>
42992 <name>SLOTSZ</name>
42993 <description>Slot size</description>
42994 <bitOffset>6</bitOffset>
42995 <bitWidth>2</bitWidth>
42996 </field>
42997 <field>
42998 <name>FBOFF</name>
42999 <description>First bit offset</description>
43000 <bitOffset>0</bitOffset>
43001 <bitWidth>5</bitWidth>
43002 </field>
43003 </fields>
43004 </register>
43005 <register>
43006 <name>AIM</name>
43007 <displayName>AIM</displayName>
43008 <description>AInterrupt mask register2</description>
43009 <addressOffset>0x14</addressOffset>
43010 <size>0x20</size>
43011 <access>read-write</access>
43012 <resetValue>0x00000000</resetValue>
43013 <fields>
43014 <field>
43015 <name>LFSDET</name>
43016 <description>Late frame synchronization detection
43017 interrupt enable</description>
43018 <bitOffset>6</bitOffset>
43019 <bitWidth>1</bitWidth>
43020 </field>
43021 <field>
43022 <name>AFSDETIE</name>
43023 <description>Anticipated frame synchronization
43024 detection interrupt enable</description>
43025 <bitOffset>5</bitOffset>
43026 <bitWidth>1</bitWidth>
43027 </field>
43028 <field>
43029 <name>CNRDYIE</name>
43030 <description>Codec not ready interrupt
43031 enable</description>
43032 <bitOffset>4</bitOffset>
43033 <bitWidth>1</bitWidth>
43034 </field>
43035 <field>
43036 <name>FREQIE</name>
43037 <description>FIFO request interrupt
43038 enable</description>
43039 <bitOffset>3</bitOffset>
43040 <bitWidth>1</bitWidth>
43041 </field>
43042 <field>
43043 <name>WCKCFG</name>
43044 <description>Wrong clock configuration interrupt
43045 enable</description>
43046 <bitOffset>2</bitOffset>
43047 <bitWidth>1</bitWidth>
43048 </field>
43049 <field>
43050 <name>MUTEDET</name>
43051 <description>Mute detection interrupt
43052 enable</description>
43053 <bitOffset>1</bitOffset>
43054 <bitWidth>1</bitWidth>
43055 </field>
43056 <field>
43057 <name>OVRUDRIE</name>
43058 <description>Overrun/underrun interrupt
43059 enable</description>
43060 <bitOffset>0</bitOffset>
43061 <bitWidth>1</bitWidth>
43062 </field>
43063 </fields>
43064 </register>
43065 <register>
43066 <name>ASR</name>
43067 <displayName>ASR</displayName>
43068 <description>AStatus register</description>
43069 <addressOffset>0x18</addressOffset>
43070 <size>0x20</size>
43071 <access>read-write</access>
43072 <resetValue>0x00000000</resetValue>
43073 <fields>
43074 <field>
43075 <name>FLVL</name>
43076 <description>FIFO level threshold</description>
43077 <bitOffset>16</bitOffset>
43078 <bitWidth>3</bitWidth>
43079 </field>
43080 <field>
43081 <name>LFSDET</name>
43082 <description>Late frame synchronization
43083 detection</description>
43084 <bitOffset>6</bitOffset>
43085 <bitWidth>1</bitWidth>
43086 </field>
43087 <field>
43088 <name>AFSDET</name>
43089 <description>Anticipated frame synchronization
43090 detection</description>
43091 <bitOffset>5</bitOffset>
43092 <bitWidth>1</bitWidth>
43093 </field>
43094 <field>
43095 <name>CNRDY</name>
43096 <description>Codec not ready</description>
43097 <bitOffset>4</bitOffset>
43098 <bitWidth>1</bitWidth>
43099 </field>
43100 <field>
43101 <name>FREQ</name>
43102 <description>FIFO request</description>
43103 <bitOffset>3</bitOffset>
43104 <bitWidth>1</bitWidth>
43105 </field>
43106 <field>
43107 <name>WCKCFG</name>
43108 <description>Wrong clock configuration flag. This bit
43109 is read only.</description>
43110 <bitOffset>2</bitOffset>
43111 <bitWidth>1</bitWidth>
43112 </field>
43113 <field>
43114 <name>MUTEDET</name>
43115 <description>Mute detection</description>
43116 <bitOffset>1</bitOffset>
43117 <bitWidth>1</bitWidth>
43118 </field>
43119 <field>
43120 <name>OVRUDR</name>
43121 <description>Overrun / underrun</description>
43122 <bitOffset>0</bitOffset>
43123 <bitWidth>1</bitWidth>
43124 </field>
43125 </fields>
43126 </register>
43127 <register>
43128 <name>ACLRFR</name>
43129 <displayName>ACLRFR</displayName>
43130 <description>AClear flag register</description>
43131 <addressOffset>0x1C</addressOffset>
43132 <size>0x20</size>
43133 <access>read-write</access>
43134 <resetValue>0x00000000</resetValue>
43135 <fields>
43136 <field>
43137 <name>LFSDET</name>
43138 <description>Clear late frame synchronization
43139 detection flag</description>
43140 <bitOffset>6</bitOffset>
43141 <bitWidth>1</bitWidth>
43142 </field>
43143 <field>
43144 <name>CAFSDET</name>
43145 <description>Clear anticipated frame synchronization
43146 detection flag.</description>
43147 <bitOffset>5</bitOffset>
43148 <bitWidth>1</bitWidth>
43149 </field>
43150 <field>
43151 <name>CNRDY</name>
43152 <description>Clear codec not ready flag</description>
43153 <bitOffset>4</bitOffset>
43154 <bitWidth>1</bitWidth>
43155 </field>
43156 <field>
43157 <name>WCKCFG</name>
43158 <description>Clear wrong clock configuration
43159 flag</description>
43160 <bitOffset>2</bitOffset>
43161 <bitWidth>1</bitWidth>
43162 </field>
43163 <field>
43164 <name>MUTEDET</name>
43165 <description>Mute detection flag</description>
43166 <bitOffset>1</bitOffset>
43167 <bitWidth>1</bitWidth>
43168 </field>
43169 <field>
43170 <name>OVRUDR</name>
43171 <description>Clear overrun / underrun</description>
43172 <bitOffset>0</bitOffset>
43173 <bitWidth>1</bitWidth>
43174 </field>
43175 </fields>
43176 </register>
43177 <register>
43178 <name>ADR</name>
43179 <displayName>ADR</displayName>
43180 <description>AData register</description>
43181 <addressOffset>0x20</addressOffset>
43182 <size>0x20</size>
43183 <access>read-write</access>
43184 <resetValue>0x00000000</resetValue>
43185 <fields>
43186 <field>
43187 <name>DATA</name>
43188 <description>Data</description>
43189 <bitOffset>0</bitOffset>
43190 <bitWidth>32</bitWidth>
43191 </field>
43192 </fields>
43193 </register>
43194 <register>
43195 <name>GCR</name>
43196 <displayName>GCR</displayName>
43197 <description>Global configuration register</description>
43198 <addressOffset>0x0</addressOffset>
43199 <size>0x20</size>
43200 <access>read-write</access>
43201 <resetValue>0x00000000</resetValue>
43202 <fields>
43203 <field>
43204 <name>SYNCIN</name>
43205 <description>Synchronization inputs</description>
43206 <bitOffset>0</bitOffset>
43207 <bitWidth>2</bitWidth>
43208 </field>
43209 <field>
43210 <name>SYNCOUT</name>
43211 <description>Synchronization outputs</description>
43212 <bitOffset>4</bitOffset>
43213 <bitWidth>2</bitWidth>
43214 </field>
43215 </fields>
43216 </register>
43217 </registers>
43218 </peripheral>
43219 <peripheral derivedFrom="SAI1">
43220 <name>SAI2</name>
43221 <baseAddress>0x40015C00</baseAddress>
43222 </peripheral>
43223 <peripheral>
43224 <name>DMA2D</name>
43225 <description>DMA2D controller</description>
43226 <groupName>DMA2D</groupName>
43227 <baseAddress>0x4002B000</baseAddress>
43228 <addressBlock>
43229 <offset>0x0</offset>
43230 <size>0xC00</size>
43231 <usage>registers</usage>
43232 </addressBlock>
43233 <interrupt>
43234 <name>DMA2D</name>
43235 <description>DMA2D global interrupt</description>
43236 <value>90</value>
43237 </interrupt>
43238 <registers>
43239 <register>
43240 <name>CR</name>
43241 <displayName>CR</displayName>
43242 <description>control register</description>
43243 <addressOffset>0x0</addressOffset>
43244 <size>0x20</size>
43245 <access>read-write</access>
43246 <resetValue>0x00000000</resetValue>
43247 <fields>
43248 <field>
43249 <name>MODE</name>
43250 <description>DMA2D mode</description>
43251 <bitOffset>16</bitOffset>
43252 <bitWidth>2</bitWidth>
43253 </field>
43254 <field>
43255 <name>CEIE</name>
43256 <description>Configuration Error Interrupt
43257 Enable</description>
43258 <bitOffset>13</bitOffset>
43259 <bitWidth>1</bitWidth>
43260 </field>
43261 <field>
43262 <name>CTCIE</name>
43263 <description>CLUT transfer complete interrupt
43264 enable</description>
43265 <bitOffset>12</bitOffset>
43266 <bitWidth>1</bitWidth>
43267 </field>
43268 <field>
43269 <name>CAEIE</name>
43270 <description>CLUT access error interrupt
43271 enable</description>
43272 <bitOffset>11</bitOffset>
43273 <bitWidth>1</bitWidth>
43274 </field>
43275 <field>
43276 <name>TWIE</name>
43277 <description>Transfer watermark interrupt
43278 enable</description>
43279 <bitOffset>10</bitOffset>
43280 <bitWidth>1</bitWidth>
43281 </field>
43282 <field>
43283 <name>TCIE</name>
43284 <description>Transfer complete interrupt
43285 enable</description>
43286 <bitOffset>9</bitOffset>
43287 <bitWidth>1</bitWidth>
43288 </field>
43289 <field>
43290 <name>TEIE</name>
43291 <description>Transfer error interrupt
43292 enable</description>
43293 <bitOffset>8</bitOffset>
43294 <bitWidth>1</bitWidth>
43295 </field>
43296 <field>
43297 <name>ABORT</name>
43298 <description>Abort</description>
43299 <bitOffset>2</bitOffset>
43300 <bitWidth>1</bitWidth>
43301 </field>
43302 <field>
43303 <name>SUSP</name>
43304 <description>Suspend</description>
43305 <bitOffset>1</bitOffset>
43306 <bitWidth>1</bitWidth>
43307 </field>
43308 <field>
43309 <name>START</name>
43310 <description>Start</description>
43311 <bitOffset>0</bitOffset>
43312 <bitWidth>1</bitWidth>
43313 </field>
43314 </fields>
43315 </register>
43316 <register>
43317 <name>ISR</name>
43318 <displayName>ISR</displayName>
43319 <description>Interrupt Status Register</description>
43320 <addressOffset>0x4</addressOffset>
43321 <size>0x20</size>
43322 <access>read-only</access>
43323 <resetValue>0x00000000</resetValue>
43324 <fields>
43325 <field>
43326 <name>CEIF</name>
43327 <description>Configuration error interrupt
43328 flag</description>
43329 <bitOffset>5</bitOffset>
43330 <bitWidth>1</bitWidth>
43331 </field>
43332 <field>
43333 <name>CTCIF</name>
43334 <description>CLUT transfer complete interrupt
43335 flag</description>
43336 <bitOffset>4</bitOffset>
43337 <bitWidth>1</bitWidth>
43338 </field>
43339 <field>
43340 <name>CAEIF</name>
43341 <description>CLUT access error interrupt
43342 flag</description>
43343 <bitOffset>3</bitOffset>
43344 <bitWidth>1</bitWidth>
43345 </field>
43346 <field>
43347 <name>TWIF</name>
43348 <description>Transfer watermark interrupt
43349 flag</description>
43350 <bitOffset>2</bitOffset>
43351 <bitWidth>1</bitWidth>
43352 </field>
43353 <field>
43354 <name>TCIF</name>
43355 <description>Transfer complete interrupt
43356 flag</description>
43357 <bitOffset>1</bitOffset>
43358 <bitWidth>1</bitWidth>
43359 </field>
43360 <field>
43361 <name>TEIF</name>
43362 <description>Transfer error interrupt
43363 flag</description>
43364 <bitOffset>0</bitOffset>
43365 <bitWidth>1</bitWidth>
43366 </field>
43367 </fields>
43368 </register>
43369 <register>
43370 <name>IFCR</name>
43371 <displayName>IFCR</displayName>
43372 <description>interrupt flag clear register</description>
43373 <addressOffset>0x8</addressOffset>
43374 <size>0x20</size>
43375 <access>read-write</access>
43376 <resetValue>0x00000000</resetValue>
43377 <fields>
43378 <field>
43379 <name>CCEIF</name>
43380 <description>Clear configuration error interrupt
43381 flag</description>
43382 <bitOffset>5</bitOffset>
43383 <bitWidth>1</bitWidth>
43384 </field>
43385 <field>
43386 <name>CCTCIF</name>
43387 <description>Clear CLUT transfer complete interrupt
43388 flag</description>
43389 <bitOffset>4</bitOffset>
43390 <bitWidth>1</bitWidth>
43391 </field>
43392 <field>
43393 <name>CAECIF</name>
43394 <description>Clear CLUT access error interrupt
43395 flag</description>
43396 <bitOffset>3</bitOffset>
43397 <bitWidth>1</bitWidth>
43398 </field>
43399 <field>
43400 <name>CTWIF</name>
43401 <description>Clear transfer watermark interrupt
43402 flag</description>
43403 <bitOffset>2</bitOffset>
43404 <bitWidth>1</bitWidth>
43405 </field>
43406 <field>
43407 <name>CTCIF</name>
43408 <description>Clear transfer complete interrupt
43409 flag</description>
43410 <bitOffset>1</bitOffset>
43411 <bitWidth>1</bitWidth>
43412 </field>
43413 <field>
43414 <name>CTEIF</name>
43415 <description>Clear Transfer error interrupt
43416 flag</description>
43417 <bitOffset>0</bitOffset>
43418 <bitWidth>1</bitWidth>
43419 </field>
43420 </fields>
43421 </register>
43422 <register>
43423 <name>FGMAR</name>
43424 <displayName>FGMAR</displayName>
43425 <description>foreground memory address
43426 register</description>
43427 <addressOffset>0xC</addressOffset>
43428 <size>0x20</size>
43429 <access>read-write</access>
43430 <resetValue>0x00000000</resetValue>
43431 <fields>
43432 <field>
43433 <name>MA</name>
43434 <description>Memory address</description>
43435 <bitOffset>0</bitOffset>
43436 <bitWidth>32</bitWidth>
43437 </field>
43438 </fields>
43439 </register>
43440 <register>
43441 <name>FGOR</name>
43442 <displayName>FGOR</displayName>
43443 <description>foreground offset register</description>
43444 <addressOffset>0x10</addressOffset>
43445 <size>0x20</size>
43446 <access>read-write</access>
43447 <resetValue>0x00000000</resetValue>
43448 <fields>
43449 <field>
43450 <name>LO</name>
43451 <description>Line offset</description>
43452 <bitOffset>0</bitOffset>
43453 <bitWidth>14</bitWidth>
43454 </field>
43455 </fields>
43456 </register>
43457 <register>
43458 <name>BGMAR</name>
43459 <displayName>BGMAR</displayName>
43460 <description>background memory address
43461 register</description>
43462 <addressOffset>0x14</addressOffset>
43463 <size>0x20</size>
43464 <access>read-write</access>
43465 <resetValue>0x00000000</resetValue>
43466 <fields>
43467 <field>
43468 <name>MA</name>
43469 <description>Memory address</description>
43470 <bitOffset>0</bitOffset>
43471 <bitWidth>32</bitWidth>
43472 </field>
43473 </fields>
43474 </register>
43475 <register>
43476 <name>BGOR</name>
43477 <displayName>BGOR</displayName>
43478 <description>background offset register</description>
43479 <addressOffset>0x18</addressOffset>
43480 <size>0x20</size>
43481 <access>read-write</access>
43482 <resetValue>0x00000000</resetValue>
43483 <fields>
43484 <field>
43485 <name>LO</name>
43486 <description>Line offset</description>
43487 <bitOffset>0</bitOffset>
43488 <bitWidth>14</bitWidth>
43489 </field>
43490 </fields>
43491 </register>
43492 <register>
43493 <name>FGPFCCR</name>
43494 <displayName>FGPFCCR</displayName>
43495 <description>foreground PFC control
43496 register</description>
43497 <addressOffset>0x1C</addressOffset>
43498 <size>0x20</size>
43499 <access>read-write</access>
43500 <resetValue>0x00000000</resetValue>
43501 <fields>
43502 <field>
43503 <name>ALPHA</name>
43504 <description>Alpha value</description>
43505 <bitOffset>24</bitOffset>
43506 <bitWidth>8</bitWidth>
43507 </field>
43508 <field>
43509 <name>AM</name>
43510 <description>Alpha mode</description>
43511 <bitOffset>16</bitOffset>
43512 <bitWidth>2</bitWidth>
43513 </field>
43514 <field>
43515 <name>CS</name>
43516 <description>CLUT size</description>
43517 <bitOffset>8</bitOffset>
43518 <bitWidth>8</bitWidth>
43519 </field>
43520 <field>
43521 <name>START</name>
43522 <description>Start</description>
43523 <bitOffset>5</bitOffset>
43524 <bitWidth>1</bitWidth>
43525 </field>
43526 <field>
43527 <name>CCM</name>
43528 <description>CLUT color mode</description>
43529 <bitOffset>4</bitOffset>
43530 <bitWidth>1</bitWidth>
43531 </field>
43532 <field>
43533 <name>CM</name>
43534 <description>Color mode</description>
43535 <bitOffset>0</bitOffset>
43536 <bitWidth>4</bitWidth>
43537 </field>
43538 </fields>
43539 </register>
43540 <register>
43541 <name>FGCOLR</name>
43542 <displayName>FGCOLR</displayName>
43543 <description>foreground color register</description>
43544 <addressOffset>0x20</addressOffset>
43545 <size>0x20</size>
43546 <access>read-write</access>
43547 <resetValue>0x00000000</resetValue>
43548 <fields>
43549 <field>
43550 <name>RED</name>
43551 <description>Red Value</description>
43552 <bitOffset>16</bitOffset>
43553 <bitWidth>8</bitWidth>
43554 </field>
43555 <field>
43556 <name>GREEN</name>
43557 <description>Green Value</description>
43558 <bitOffset>8</bitOffset>
43559 <bitWidth>8</bitWidth>
43560 </field>
43561 <field>
43562 <name>BLUE</name>
43563 <description>Blue Value</description>
43564 <bitOffset>0</bitOffset>
43565 <bitWidth>8</bitWidth>
43566 </field>
43567 </fields>
43568 </register>
43569 <register>
43570 <name>BGPFCCR</name>
43571 <displayName>BGPFCCR</displayName>
43572 <description>background PFC control
43573 register</description>
43574 <addressOffset>0x24</addressOffset>
43575 <size>0x20</size>
43576 <access>read-write</access>
43577 <resetValue>0x00000000</resetValue>
43578 <fields>
43579 <field>
43580 <name>ALPHA</name>
43581 <description>Alpha value</description>
43582 <bitOffset>24</bitOffset>
43583 <bitWidth>8</bitWidth>
43584 </field>
43585 <field>
43586 <name>AM</name>
43587 <description>Alpha mode</description>
43588 <bitOffset>16</bitOffset>
43589 <bitWidth>2</bitWidth>
43590 </field>
43591 <field>
43592 <name>CS</name>
43593 <description>CLUT size</description>
43594 <bitOffset>8</bitOffset>
43595 <bitWidth>8</bitWidth>
43596 </field>
43597 <field>
43598 <name>START</name>
43599 <description>Start</description>
43600 <bitOffset>5</bitOffset>
43601 <bitWidth>1</bitWidth>
43602 </field>
43603 <field>
43604 <name>CCM</name>
43605 <description>CLUT Color mode</description>
43606 <bitOffset>4</bitOffset>
43607 <bitWidth>1</bitWidth>
43608 </field>
43609 <field>
43610 <name>CM</name>
43611 <description>Color mode</description>
43612 <bitOffset>0</bitOffset>
43613 <bitWidth>4</bitWidth>
43614 </field>
43615 </fields>
43616 </register>
43617 <register>
43618 <name>BGCOLR</name>
43619 <displayName>BGCOLR</displayName>
43620 <description>background color register</description>
43621 <addressOffset>0x28</addressOffset>
43622 <size>0x20</size>
43623 <access>read-write</access>
43624 <resetValue>0x00000000</resetValue>
43625 <fields>
43626 <field>
43627 <name>RED</name>
43628 <description>Red Value</description>
43629 <bitOffset>16</bitOffset>
43630 <bitWidth>8</bitWidth>
43631 </field>
43632 <field>
43633 <name>GREEN</name>
43634 <description>Green Value</description>
43635 <bitOffset>8</bitOffset>
43636 <bitWidth>8</bitWidth>
43637 </field>
43638 <field>
43639 <name>BLUE</name>
43640 <description>Blue Value</description>
43641 <bitOffset>0</bitOffset>
43642 <bitWidth>8</bitWidth>
43643 </field>
43644 </fields>
43645 </register>
43646 <register>
43647 <name>FGCMAR</name>
43648 <displayName>FGCMAR</displayName>
43649 <description>foreground CLUT memory address
43650 register</description>
43651 <addressOffset>0x2C</addressOffset>
43652 <size>0x20</size>
43653 <access>read-write</access>
43654 <resetValue>0x00000000</resetValue>
43655 <fields>
43656 <field>
43657 <name>MA</name>
43658 <description>Memory Address</description>
43659 <bitOffset>0</bitOffset>
43660 <bitWidth>32</bitWidth>
43661 </field>
43662 </fields>
43663 </register>
43664 <register>
43665 <name>BGCMAR</name>
43666 <displayName>BGCMAR</displayName>
43667 <description>background CLUT memory address
43668 register</description>
43669 <addressOffset>0x30</addressOffset>
43670 <size>0x20</size>
43671 <access>read-write</access>
43672 <resetValue>0x00000000</resetValue>
43673 <fields>
43674 <field>
43675 <name>MA</name>
43676 <description>Memory address</description>
43677 <bitOffset>0</bitOffset>
43678 <bitWidth>32</bitWidth>
43679 </field>
43680 </fields>
43681 </register>
43682 <register>
43683 <name>OPFCCR</name>
43684 <displayName>OPFCCR</displayName>
43685 <description>output PFC control register</description>
43686 <addressOffset>0x34</addressOffset>
43687 <size>0x20</size>
43688 <access>read-write</access>
43689 <resetValue>0x00000000</resetValue>
43690 <fields>
43691 <field>
43692 <name>CM</name>
43693 <description>Color mode</description>
43694 <bitOffset>0</bitOffset>
43695 <bitWidth>3</bitWidth>
43696 </field>
43697 </fields>
43698 </register>
43699 <register>
43700 <name>OCOLR</name>
43701 <displayName>OCOLR</displayName>
43702 <description>output color register</description>
43703 <addressOffset>0x38</addressOffset>
43704 <size>0x20</size>
43705 <access>read-write</access>
43706 <resetValue>0x00000000</resetValue>
43707 <fields>
43708 <field>
43709 <name>APLHA</name>
43710 <description>Alpha Channel Value</description>
43711 <bitOffset>24</bitOffset>
43712 <bitWidth>8</bitWidth>
43713 </field>
43714 <field>
43715 <name>RED</name>
43716 <description>Red Value</description>
43717 <bitOffset>16</bitOffset>
43718 <bitWidth>8</bitWidth>
43719 </field>
43720 <field>
43721 <name>GREEN</name>
43722 <description>Green Value</description>
43723 <bitOffset>8</bitOffset>
43724 <bitWidth>8</bitWidth>
43725 </field>
43726 <field>
43727 <name>BLUE</name>
43728 <description>Blue Value</description>
43729 <bitOffset>0</bitOffset>
43730 <bitWidth>8</bitWidth>
43731 </field>
43732 </fields>
43733 </register>
43734 <register>
43735 <name>OMAR</name>
43736 <displayName>OMAR</displayName>
43737 <description>output memory address register</description>
43738 <addressOffset>0x3C</addressOffset>
43739 <size>0x20</size>
43740 <access>read-write</access>
43741 <resetValue>0x00000000</resetValue>
43742 <fields>
43743 <field>
43744 <name>MA</name>
43745 <description>Memory Address</description>
43746 <bitOffset>0</bitOffset>
43747 <bitWidth>32</bitWidth>
43748 </field>
43749 </fields>
43750 </register>
43751 <register>
43752 <name>OOR</name>
43753 <displayName>OOR</displayName>
43754 <description>output offset register</description>
43755 <addressOffset>0x40</addressOffset>
43756 <size>0x20</size>
43757 <access>read-write</access>
43758 <resetValue>0x00000000</resetValue>
43759 <fields>
43760 <field>
43761 <name>LO</name>
43762 <description>Line Offset</description>
43763 <bitOffset>0</bitOffset>
43764 <bitWidth>14</bitWidth>
43765 </field>
43766 </fields>
43767 </register>
43768 <register>
43769 <name>NLR</name>
43770 <displayName>NLR</displayName>
43771 <description>number of line register</description>
43772 <addressOffset>0x44</addressOffset>
43773 <size>0x20</size>
43774 <access>read-write</access>
43775 <resetValue>0x00000000</resetValue>
43776 <fields>
43777 <field>
43778 <name>PL</name>
43779 <description>Pixel per lines</description>
43780 <bitOffset>16</bitOffset>
43781 <bitWidth>14</bitWidth>
43782 </field>
43783 <field>
43784 <name>NL</name>
43785 <description>Number of lines</description>
43786 <bitOffset>0</bitOffset>
43787 <bitWidth>16</bitWidth>
43788 </field>
43789 </fields>
43790 </register>
43791 <register>
43792 <name>LWR</name>
43793 <displayName>LWR</displayName>
43794 <description>line watermark register</description>
43795 <addressOffset>0x48</addressOffset>
43796 <size>0x20</size>
43797 <access>read-write</access>
43798 <resetValue>0x00000000</resetValue>
43799 <fields>
43800 <field>
43801 <name>LW</name>
43802 <description>Line watermark</description>
43803 <bitOffset>0</bitOffset>
43804 <bitWidth>16</bitWidth>
43805 </field>
43806 </fields>
43807 </register>
43808 <register>
43809 <name>AMTCR</name>
43810 <displayName>AMTCR</displayName>
43811 <description>AHB master timer configuration
43812 register</description>
43813 <addressOffset>0x4C</addressOffset>
43814 <size>0x20</size>
43815 <access>read-write</access>
43816 <resetValue>0x00000000</resetValue>
43817 <fields>
43818 <field>
43819 <name>DT</name>
43820 <description>Dead Time</description>
43821 <bitOffset>8</bitOffset>
43822 <bitWidth>8</bitWidth>
43823 </field>
43824 <field>
43825 <name>EN</name>
43826 <description>Enable</description>
43827 <bitOffset>0</bitOffset>
43828 <bitWidth>1</bitWidth>
43829 </field>
43830 </fields>
43831 </register>
43832 <register>
43833 <name>FGCLUT</name>
43834 <displayName>FGCLUT</displayName>
43835 <description>FGCLUT</description>
43836 <addressOffset>0x400</addressOffset>
43837 <size>0x20</size>
43838 <access>read-write</access>
43839 <resetValue>0x00000000</resetValue>
43840 <fields>
43841 <field>
43842 <name>APLHA</name>
43843 <description>APLHA</description>
43844 <bitOffset>24</bitOffset>
43845 <bitWidth>8</bitWidth>
43846 </field>
43847 <field>
43848 <name>RED</name>
43849 <description>RED</description>
43850 <bitOffset>16</bitOffset>
43851 <bitWidth>8</bitWidth>
43852 </field>
43853 <field>
43854 <name>GREEN</name>
43855 <description>GREEN</description>
43856 <bitOffset>8</bitOffset>
43857 <bitWidth>8</bitWidth>
43858 </field>
43859 <field>
43860 <name>BLUE</name>
43861 <description>BLUE</description>
43862 <bitOffset>0</bitOffset>
43863 <bitWidth>8</bitWidth>
43864 </field>
43865 </fields>
43866 </register>
43867 <register>
43868 <name>BGCLUT</name>
43869 <displayName>BGCLUT</displayName>
43870 <description>BGCLUT</description>
43871 <addressOffset>0x800</addressOffset>
43872 <size>0x20</size>
43873 <access>read-write</access>
43874 <resetValue>0x00000000</resetValue>
43875 <fields>
43876 <field>
43877 <name>APLHA</name>
43878 <description>APLHA</description>
43879 <bitOffset>24</bitOffset>
43880 <bitWidth>8</bitWidth>
43881 </field>
43882 <field>
43883 <name>RED</name>
43884 <description>RED</description>
43885 <bitOffset>16</bitOffset>
43886 <bitWidth>8</bitWidth>
43887 </field>
43888 <field>
43889 <name>GREEN</name>
43890 <description>GREEN</description>
43891 <bitOffset>8</bitOffset>
43892 <bitWidth>8</bitWidth>
43893 </field>
43894 <field>
43895 <name>BLUE</name>
43896 <description>BLUE</description>
43897 <bitOffset>0</bitOffset>
43898 <bitWidth>8</bitWidth>
43899 </field>
43900 </fields>
43901 </register>
43902 </registers>
43903 </peripheral>
43904 <peripheral>
43905 <name>QUADSPI</name>
43906 <description>QuadSPI interface</description>
43907 <groupName>QUADSPI</groupName>
43908 <baseAddress>0xA0001000</baseAddress>
43909 <addressBlock>
43910 <offset>0x0</offset>
43911 <size>0x1000</size>
43912 <usage>registers</usage>
43913 </addressBlock>
43914 <registers>
43915 <register>
43916 <name>CR</name>
43917 <displayName>CR</displayName>
43918 <description>control register</description>
43919 <addressOffset>0x0</addressOffset>
43920 <size>0x20</size>
43921 <access>read-write</access>
43922 <resetValue>0x00000000</resetValue>
43923 <fields>
43924 <field>
43925 <name>PRESCALER</name>
43926 <description>Clock prescaler</description>
43927 <bitOffset>24</bitOffset>
43928 <bitWidth>8</bitWidth>
43929 </field>
43930 <field>
43931 <name>PMM</name>
43932 <description>Polling match mode</description>
43933 <bitOffset>23</bitOffset>
43934 <bitWidth>1</bitWidth>
43935 </field>
43936 <field>
43937 <name>APMS</name>
43938 <description>Automatic poll mode stop</description>
43939 <bitOffset>22</bitOffset>
43940 <bitWidth>1</bitWidth>
43941 </field>
43942 <field>
43943 <name>TOIE</name>
43944 <description>TimeOut interrupt enable</description>
43945 <bitOffset>20</bitOffset>
43946 <bitWidth>1</bitWidth>
43947 </field>
43948 <field>
43949 <name>SMIE</name>
43950 <description>Status match interrupt
43951 enable</description>
43952 <bitOffset>19</bitOffset>
43953 <bitWidth>1</bitWidth>
43954 </field>
43955 <field>
43956 <name>FTIE</name>
43957 <description>FIFO threshold interrupt
43958 enable</description>
43959 <bitOffset>18</bitOffset>
43960 <bitWidth>1</bitWidth>
43961 </field>
43962 <field>
43963 <name>TCIE</name>
43964 <description>Transfer complete interrupt
43965 enable</description>
43966 <bitOffset>17</bitOffset>
43967 <bitWidth>1</bitWidth>
43968 </field>
43969 <field>
43970 <name>TEIE</name>
43971 <description>Transfer error interrupt
43972 enable</description>
43973 <bitOffset>16</bitOffset>
43974 <bitWidth>1</bitWidth>
43975 </field>
43976 <field>
43977 <name>FTHRES</name>
43978 <description>IFO threshold level</description>
43979 <bitOffset>8</bitOffset>
43980 <bitWidth>5</bitWidth>
43981 </field>
43982 <field>
43983 <name>FSEL</name>
43984 <description>FLASH memory selection</description>
43985 <bitOffset>7</bitOffset>
43986 <bitWidth>1</bitWidth>
43987 </field>
43988 <field>
43989 <name>DFM</name>
43990 <description>Dual-flash mode</description>
43991 <bitOffset>6</bitOffset>
43992 <bitWidth>1</bitWidth>
43993 </field>
43994 <field>
43995 <name>SSHIFT</name>
43996 <description>Sample shift</description>
43997 <bitOffset>4</bitOffset>
43998 <bitWidth>1</bitWidth>
43999 </field>
44000 <field>
44001 <name>TCEN</name>
44002 <description>Timeout counter enable</description>
44003 <bitOffset>3</bitOffset>
44004 <bitWidth>1</bitWidth>
44005 </field>
44006 <field>
44007 <name>DMAEN</name>
44008 <description>DMA enable</description>
44009 <bitOffset>2</bitOffset>
44010 <bitWidth>1</bitWidth>
44011 </field>
44012 <field>
44013 <name>ABORT</name>
44014 <description>Abort request</description>
44015 <bitOffset>1</bitOffset>
44016 <bitWidth>1</bitWidth>
44017 </field>
44018 <field>
44019 <name>EN</name>
44020 <description>Enable</description>
44021 <bitOffset>0</bitOffset>
44022 <bitWidth>1</bitWidth>
44023 </field>
44024 </fields>
44025 </register>
44026 <register>
44027 <name>DCR</name>
44028 <displayName>DCR</displayName>
44029 <description>device configuration register</description>
44030 <addressOffset>0x4</addressOffset>
44031 <size>0x20</size>
44032 <access>read-write</access>
44033 <resetValue>0x00000000</resetValue>
44034 <fields>
44035 <field>
44036 <name>FSIZE</name>
44037 <description>FLASH memory size</description>
44038 <bitOffset>16</bitOffset>
44039 <bitWidth>5</bitWidth>
44040 </field>
44041 <field>
44042 <name>CSHT</name>
44043 <description>Chip select high time</description>
44044 <bitOffset>8</bitOffset>
44045 <bitWidth>3</bitWidth>
44046 </field>
44047 <field>
44048 <name>CKMODE</name>
44049 <description>Mode 0 / mode 3</description>
44050 <bitOffset>0</bitOffset>
44051 <bitWidth>1</bitWidth>
44052 </field>
44053 </fields>
44054 </register>
44055 <register>
44056 <name>SR</name>
44057 <displayName>SR</displayName>
44058 <description>status register</description>
44059 <addressOffset>0x8</addressOffset>
44060 <size>0x20</size>
44061 <access>read-only</access>
44062 <resetValue>0x00000000</resetValue>
44063 <fields>
44064 <field>
44065 <name>FLEVEL</name>
44066 <description>FIFO level</description>
44067 <bitOffset>8</bitOffset>
44068 <bitWidth>7</bitWidth>
44069 </field>
44070 <field>
44071 <name>BUSY</name>
44072 <description>Busy</description>
44073 <bitOffset>5</bitOffset>
44074 <bitWidth>1</bitWidth>
44075 </field>
44076 <field>
44077 <name>TOF</name>
44078 <description>Timeout flag</description>
44079 <bitOffset>4</bitOffset>
44080 <bitWidth>1</bitWidth>
44081 </field>
44082 <field>
44083 <name>SMF</name>
44084 <description>Status match flag</description>
44085 <bitOffset>3</bitOffset>
44086 <bitWidth>1</bitWidth>
44087 </field>
44088 <field>
44089 <name>FTF</name>
44090 <description>FIFO threshold flag</description>
44091 <bitOffset>2</bitOffset>
44092 <bitWidth>1</bitWidth>
44093 </field>
44094 <field>
44095 <name>TCF</name>
44096 <description>Transfer complete flag</description>
44097 <bitOffset>1</bitOffset>
44098 <bitWidth>1</bitWidth>
44099 </field>
44100 <field>
44101 <name>TEF</name>
44102 <description>Transfer error flag</description>
44103 <bitOffset>0</bitOffset>
44104 <bitWidth>1</bitWidth>
44105 </field>
44106 </fields>
44107 </register>
44108 <register>
44109 <name>FCR</name>
44110 <displayName>FCR</displayName>
44111 <description>flag clear register</description>
44112 <addressOffset>0xC</addressOffset>
44113 <size>0x20</size>
44114 <access>read-write</access>
44115 <resetValue>0x00000000</resetValue>
44116 <fields>
44117 <field>
44118 <name>CTOF</name>
44119 <description>Clear timeout flag</description>
44120 <bitOffset>4</bitOffset>
44121 <bitWidth>1</bitWidth>
44122 </field>
44123 <field>
44124 <name>CSMF</name>
44125 <description>Clear status match flag</description>
44126 <bitOffset>3</bitOffset>
44127 <bitWidth>1</bitWidth>
44128 </field>
44129 <field>
44130 <name>CTCF</name>
44131 <description>Clear transfer complete
44132 flag</description>
44133 <bitOffset>1</bitOffset>
44134 <bitWidth>1</bitWidth>
44135 </field>
44136 <field>
44137 <name>CTEF</name>
44138 <description>Clear transfer error flag</description>
44139 <bitOffset>0</bitOffset>
44140 <bitWidth>1</bitWidth>
44141 </field>
44142 </fields>
44143 </register>
44144 <register>
44145 <name>DLR</name>
44146 <displayName>DLR</displayName>
44147 <description>data length register</description>
44148 <addressOffset>0x10</addressOffset>
44149 <size>0x20</size>
44150 <access>read-write</access>
44151 <resetValue>0x00000000</resetValue>
44152 <fields>
44153 <field>
44154 <name>DL</name>
44155 <description>Data length</description>
44156 <bitOffset>0</bitOffset>
44157 <bitWidth>32</bitWidth>
44158 </field>
44159 </fields>
44160 </register>
44161 <register>
44162 <name>CCR</name>
44163 <displayName>CCR</displayName>
44164 <description>communication configuration
44165 register</description>
44166 <addressOffset>0x14</addressOffset>
44167 <size>0x20</size>
44168 <access>read-write</access>
44169 <resetValue>0x00000000</resetValue>
44170 <fields>
44171 <field>
44172 <name>DDRM</name>
44173 <description>Double data rate mode</description>
44174 <bitOffset>31</bitOffset>
44175 <bitWidth>1</bitWidth>
44176 </field>
44177 <field>
44178 <name>DHHC</name>
44179 <description>DDR hold half cycle</description>
44180 <bitOffset>30</bitOffset>
44181 <bitWidth>1</bitWidth>
44182 </field>
44183 <field>
44184 <name>SIOO</name>
44185 <description>Send instruction only once
44186 mode</description>
44187 <bitOffset>28</bitOffset>
44188 <bitWidth>1</bitWidth>
44189 </field>
44190 <field>
44191 <name>FMODE</name>
44192 <description>Functional mode</description>
44193 <bitOffset>26</bitOffset>
44194 <bitWidth>2</bitWidth>
44195 </field>
44196 <field>
44197 <name>DMODE</name>
44198 <description>Data mode</description>
44199 <bitOffset>24</bitOffset>
44200 <bitWidth>2</bitWidth>
44201 </field>
44202 <field>
44203 <name>DCYC</name>
44204 <description>Number of dummy cycles</description>
44205 <bitOffset>18</bitOffset>
44206 <bitWidth>5</bitWidth>
44207 </field>
44208 <field>
44209 <name>ABSIZE</name>
44210 <description>Alternate bytes size</description>
44211 <bitOffset>16</bitOffset>
44212 <bitWidth>2</bitWidth>
44213 </field>
44214 <field>
44215 <name>ABMODE</name>
44216 <description>Alternate bytes mode</description>
44217 <bitOffset>14</bitOffset>
44218 <bitWidth>2</bitWidth>
44219 </field>
44220 <field>
44221 <name>ADSIZE</name>
44222 <description>Address size</description>
44223 <bitOffset>12</bitOffset>
44224 <bitWidth>2</bitWidth>
44225 </field>
44226 <field>
44227 <name>ADMODE</name>
44228 <description>Address mode</description>
44229 <bitOffset>10</bitOffset>
44230 <bitWidth>2</bitWidth>
44231 </field>
44232 <field>
44233 <name>IMODE</name>
44234 <description>Instruction mode</description>
44235 <bitOffset>8</bitOffset>
44236 <bitWidth>2</bitWidth>
44237 </field>
44238 <field>
44239 <name>INSTRUCTION</name>
44240 <description>Instruction</description>
44241 <bitOffset>0</bitOffset>
44242 <bitWidth>8</bitWidth>
44243 </field>
44244 </fields>
44245 </register>
44246 <register>
44247 <name>AR</name>
44248 <displayName>AR</displayName>
44249 <description>address register</description>
44250 <addressOffset>0x18</addressOffset>
44251 <size>0x20</size>
44252 <access>read-write</access>
44253 <resetValue>0x00000000</resetValue>
44254 <fields>
44255 <field>
44256 <name>ADDRESS</name>
44257 <description>Address</description>
44258 <bitOffset>0</bitOffset>
44259 <bitWidth>32</bitWidth>
44260 </field>
44261 </fields>
44262 </register>
44263 <register>
44264 <name>ABR</name>
44265 <displayName>ABR</displayName>
44266 <description>ABR</description>
44267 <addressOffset>0x1C</addressOffset>
44268 <size>0x20</size>
44269 <access>read-write</access>
44270 <resetValue>0x00000000</resetValue>
44271 <fields>
44272 <field>
44273 <name>ALTERNATE</name>
44274 <description>ALTERNATE</description>
44275 <bitOffset>0</bitOffset>
44276 <bitWidth>32</bitWidth>
44277 </field>
44278 </fields>
44279 </register>
44280 <register>
44281 <name>DR</name>
44282 <displayName>DR</displayName>
44283 <description>data register</description>
44284 <addressOffset>0x20</addressOffset>
44285 <size>0x20</size>
44286 <access>read-write</access>
44287 <resetValue>0x00000000</resetValue>
44288 <fields>
44289 <field>
44290 <name>DATA</name>
44291 <description>Data</description>
44292 <bitOffset>0</bitOffset>
44293 <bitWidth>32</bitWidth>
44294 </field>
44295 </fields>
44296 </register>
44297 <register>
44298 <name>PSMKR</name>
44299 <displayName>PSMKR</displayName>
44300 <description>polling status mask register</description>
44301 <addressOffset>0x24</addressOffset>
44302 <size>0x20</size>
44303 <access>read-write</access>
44304 <resetValue>0x00000000</resetValue>
44305 <fields>
44306 <field>
44307 <name>MASK</name>
44308 <description>Status mask</description>
44309 <bitOffset>0</bitOffset>
44310 <bitWidth>32</bitWidth>
44311 </field>
44312 </fields>
44313 </register>
44314 <register>
44315 <name>PSMAR</name>
44316 <displayName>PSMAR</displayName>
44317 <description>polling status match register</description>
44318 <addressOffset>0x28</addressOffset>
44319 <size>0x20</size>
44320 <access>read-write</access>
44321 <resetValue>0x00000000</resetValue>
44322 <fields>
44323 <field>
44324 <name>MATCH</name>
44325 <description>Status match</description>
44326 <bitOffset>0</bitOffset>
44327 <bitWidth>32</bitWidth>
44328 </field>
44329 </fields>
44330 </register>
44331 <register>
44332 <name>PIR</name>
44333 <displayName>PIR</displayName>
44334 <description>polling interval register</description>
44335 <addressOffset>0x2C</addressOffset>
44336 <size>0x20</size>
44337 <access>read-write</access>
44338 <resetValue>0x00000000</resetValue>
44339 <fields>
44340 <field>
44341 <name>INTERVAL</name>
44342 <description>Polling interval</description>
44343 <bitOffset>0</bitOffset>
44344 <bitWidth>16</bitWidth>
44345 </field>
44346 </fields>
44347 </register>
44348 <register>
44349 <name>LPTR</name>
44350 <displayName>LPTR</displayName>
44351 <description>low-power timeout register</description>
44352 <addressOffset>0x30</addressOffset>
44353 <size>0x20</size>
44354 <access>read-write</access>
44355 <resetValue>0x00000000</resetValue>
44356 <fields>
44357 <field>
44358 <name>TIMEOUT</name>
44359 <description>Timeout period</description>
44360 <bitOffset>0</bitOffset>
44361 <bitWidth>16</bitWidth>
44362 </field>
44363 </fields>
44364 </register>
44365 </registers>
44366 </peripheral>
44367 <peripheral>
44368 <name>CEC</name>
44369 <description>HDMI-CEC controller</description>
44370 <groupName>CEC</groupName>
44371 <baseAddress>0x40006C00</baseAddress>
44372 <addressBlock>
44373 <offset>0x0</offset>
44374 <size>0x400</size>
44375 <usage>registers</usage>
44376 </addressBlock>
44377 <registers>
44378 <register>
44379 <name>CR</name>
44380 <displayName>CR</displayName>
44381 <description>control register</description>
44382 <addressOffset>0x0</addressOffset>
44383 <size>0x20</size>
44384 <access>read-write</access>
44385 <resetValue>0x00000000</resetValue>
44386 <fields>
44387 <field>
44388 <name>TXEOM</name>
44389 <description>Tx End Of Message</description>
44390 <bitOffset>2</bitOffset>
44391 <bitWidth>1</bitWidth>
44392 </field>
44393 <field>
44394 <name>TXSOM</name>
44395 <description>Tx start of message</description>
44396 <bitOffset>1</bitOffset>
44397 <bitWidth>1</bitWidth>
44398 </field>
44399 <field>
44400 <name>CECEN</name>
44401 <description>CEC Enable</description>
44402 <bitOffset>0</bitOffset>
44403 <bitWidth>1</bitWidth>
44404 </field>
44405 </fields>
44406 </register>
44407 <register>
44408 <name>CFGR</name>
44409 <displayName>CFGR</displayName>
44410 <description>configuration register</description>
44411 <addressOffset>0x4</addressOffset>
44412 <size>0x20</size>
44413 <access>read-write</access>
44414 <resetValue>0x00000000</resetValue>
44415 <fields>
44416 <field>
44417 <name>SFT</name>
44418 <description>Signal Free Time</description>
44419 <bitOffset>0</bitOffset>
44420 <bitWidth>3</bitWidth>
44421 </field>
44422 <field>
44423 <name>RXTOL</name>
44424 <description>Rx-Tolerance</description>
44425 <bitOffset>3</bitOffset>
44426 <bitWidth>1</bitWidth>
44427 </field>
44428 <field>
44429 <name>BRESTP</name>
44430 <description>Rx-stop on bit rising
44431 error</description>
44432 <bitOffset>4</bitOffset>
44433 <bitWidth>1</bitWidth>
44434 </field>
44435 <field>
44436 <name>BREGEN</name>
44437 <description>Generate error-bit on bit rising
44438 error</description>
44439 <bitOffset>5</bitOffset>
44440 <bitWidth>1</bitWidth>
44441 </field>
44442 <field>
44443 <name>LBPEGEN</name>
44444 <description>Generate Error-Bit on Long Bit Period
44445 Error</description>
44446 <bitOffset>6</bitOffset>
44447 <bitWidth>1</bitWidth>
44448 </field>
44449 <field>
44450 <name>BRDNOGEN</name>
44451 <description>Avoid Error-Bit Generation in
44452 Broadcast</description>
44453 <bitOffset>7</bitOffset>
44454 <bitWidth>1</bitWidth>
44455 </field>
44456 <field>
44457 <name>SFTOP</name>
44458 <description>SFT Option Bit</description>
44459 <bitOffset>8</bitOffset>
44460 <bitWidth>1</bitWidth>
44461 </field>
44462 <field>
44463 <name>OAR</name>
44464 <description>Own addresses
44465 configuration</description>
44466 <bitOffset>16</bitOffset>
44467 <bitWidth>15</bitWidth>
44468 </field>
44469 <field>
44470 <name>LSTN</name>
44471 <description>Listen mode</description>
44472 <bitOffset>31</bitOffset>
44473 <bitWidth>1</bitWidth>
44474 </field>
44475 </fields>
44476 </register>
44477 <register>
44478 <name>TXDR</name>
44479 <displayName>TXDR</displayName>
44480 <description>Tx data register</description>
44481 <addressOffset>0x8</addressOffset>
44482 <size>0x20</size>
44483 <access>write-only</access>
44484 <resetValue>0x00000000</resetValue>
44485 <fields>
44486 <field>
44487 <name>TXD</name>
44488 <description>Tx Data register</description>
44489 <bitOffset>0</bitOffset>
44490 <bitWidth>8</bitWidth>
44491 </field>
44492 </fields>
44493 </register>
44494 <register>
44495 <name>RXDR</name>
44496 <displayName>RXDR</displayName>
44497 <description>Rx Data Register</description>
44498 <addressOffset>0xC</addressOffset>
44499 <size>0x20</size>
44500 <access>read-only</access>
44501 <resetValue>0x00000000</resetValue>
44502 <fields>
44503 <field>
44504 <name>RXDR</name>
44505 <description>CEC Rx Data Register</description>
44506 <bitOffset>0</bitOffset>
44507 <bitWidth>8</bitWidth>
44508 </field>
44509 </fields>
44510 </register>
44511 <register>
44512 <name>ISR</name>
44513 <displayName>ISR</displayName>
44514 <description>Interrupt and Status Register</description>
44515 <addressOffset>0x10</addressOffset>
44516 <size>0x20</size>
44517 <access>read-write</access>
44518 <resetValue>0x00000000</resetValue>
44519 <fields>
44520 <field>
44521 <name>TXACKE</name>
44522 <description>Tx-Missing acknowledge
44523 error</description>
44524 <bitOffset>12</bitOffset>
44525 <bitWidth>1</bitWidth>
44526 </field>
44527 <field>
44528 <name>TXERR</name>
44529 <description>Tx-Error</description>
44530 <bitOffset>11</bitOffset>
44531 <bitWidth>1</bitWidth>
44532 </field>
44533 <field>
44534 <name>TXUDR</name>
44535 <description>Tx-Buffer Underrun</description>
44536 <bitOffset>10</bitOffset>
44537 <bitWidth>1</bitWidth>
44538 </field>
44539 <field>
44540 <name>TXEND</name>
44541 <description>End of Transmission</description>
44542 <bitOffset>9</bitOffset>
44543 <bitWidth>1</bitWidth>
44544 </field>
44545 <field>
44546 <name>TXBR</name>
44547 <description>Tx-Byte Request</description>
44548 <bitOffset>8</bitOffset>
44549 <bitWidth>1</bitWidth>
44550 </field>
44551 <field>
44552 <name>ARBLST</name>
44553 <description>Arbitration Lost</description>
44554 <bitOffset>7</bitOffset>
44555 <bitWidth>1</bitWidth>
44556 </field>
44557 <field>
44558 <name>RXACKE</name>
44559 <description>Rx-Missing Acknowledge</description>
44560 <bitOffset>6</bitOffset>
44561 <bitWidth>1</bitWidth>
44562 </field>
44563 <field>
44564 <name>LBPE</name>
44565 <description>Rx-Long Bit Period Error</description>
44566 <bitOffset>5</bitOffset>
44567 <bitWidth>1</bitWidth>
44568 </field>
44569 <field>
44570 <name>SBPE</name>
44571 <description>Rx-Short Bit period error</description>
44572 <bitOffset>4</bitOffset>
44573 <bitWidth>1</bitWidth>
44574 </field>
44575 <field>
44576 <name>BRE</name>
44577 <description>Rx-Bit rising error</description>
44578 <bitOffset>3</bitOffset>
44579 <bitWidth>1</bitWidth>
44580 </field>
44581 <field>
44582 <name>RXOVR</name>
44583 <description>Rx-Overrun</description>
44584 <bitOffset>2</bitOffset>
44585 <bitWidth>1</bitWidth>
44586 </field>
44587 <field>
44588 <name>RXEND</name>
44589 <description>End Of Reception</description>
44590 <bitOffset>1</bitOffset>
44591 <bitWidth>1</bitWidth>
44592 </field>
44593 <field>
44594 <name>RXBR</name>
44595 <description>Rx-Byte Received</description>
44596 <bitOffset>0</bitOffset>
44597 <bitWidth>1</bitWidth>
44598 </field>
44599 </fields>
44600 </register>
44601 <register>
44602 <name>IER</name>
44603 <displayName>IER</displayName>
44604 <description>interrupt enable register</description>
44605 <addressOffset>0x14</addressOffset>
44606 <size>0x20</size>
44607 <access>read-write</access>
44608 <resetValue>0x00000000</resetValue>
44609 <fields>
44610 <field>
44611 <name>TXACKIE</name>
44612 <description>Tx-Missing Acknowledge Error Interrupt
44613 Enable</description>
44614 <bitOffset>12</bitOffset>
44615 <bitWidth>1</bitWidth>
44616 </field>
44617 <field>
44618 <name>TXERRIE</name>
44619 <description>Tx-Error Interrupt Enable</description>
44620 <bitOffset>11</bitOffset>
44621 <bitWidth>1</bitWidth>
44622 </field>
44623 <field>
44624 <name>TXUDRIE</name>
44625 <description>Tx-Underrun interrupt
44626 enable</description>
44627 <bitOffset>10</bitOffset>
44628 <bitWidth>1</bitWidth>
44629 </field>
44630 <field>
44631 <name>TXENDIE</name>
44632 <description>Tx-End of message interrupt
44633 enable</description>
44634 <bitOffset>9</bitOffset>
44635 <bitWidth>1</bitWidth>
44636 </field>
44637 <field>
44638 <name>TXBRIE</name>
44639 <description>Tx-Byte Request Interrupt
44640 Enable</description>
44641 <bitOffset>8</bitOffset>
44642 <bitWidth>1</bitWidth>
44643 </field>
44644 <field>
44645 <name>ARBLSTIE</name>
44646 <description>Arbitration Lost Interrupt
44647 Enable</description>
44648 <bitOffset>7</bitOffset>
44649 <bitWidth>1</bitWidth>
44650 </field>
44651 <field>
44652 <name>RXACKIE</name>
44653 <description>Rx-Missing Acknowledge Error Interrupt
44654 Enable</description>
44655 <bitOffset>6</bitOffset>
44656 <bitWidth>1</bitWidth>
44657 </field>
44658 <field>
44659 <name>LBPEIE</name>
44660 <description>Long Bit Period Error Interrupt
44661 Enable</description>
44662 <bitOffset>5</bitOffset>
44663 <bitWidth>1</bitWidth>
44664 </field>
44665 <field>
44666 <name>SBPEIE</name>
44667 <description>Short Bit Period Error Interrupt
44668 Enable</description>
44669 <bitOffset>4</bitOffset>
44670 <bitWidth>1</bitWidth>
44671 </field>
44672 <field>
44673 <name>BREIE</name>
44674 <description>Bit Rising Error Interrupt
44675 Enable</description>
44676 <bitOffset>3</bitOffset>
44677 <bitWidth>1</bitWidth>
44678 </field>
44679 <field>
44680 <name>RXOVRIE</name>
44681 <description>Rx-Buffer Overrun Interrupt
44682 Enable</description>
44683 <bitOffset>2</bitOffset>
44684 <bitWidth>1</bitWidth>
44685 </field>
44686 <field>
44687 <name>RXENDIE</name>
44688 <description>End Of Reception Interrupt
44689 Enable</description>
44690 <bitOffset>1</bitOffset>
44691 <bitWidth>1</bitWidth>
44692 </field>
44693 <field>
44694 <name>RXBRIE</name>
44695 <description>Rx-Byte Received Interrupt
44696 Enable</description>
44697 <bitOffset>0</bitOffset>
44698 <bitWidth>1</bitWidth>
44699 </field>
44700 </fields>
44701 </register>
44702 </registers>
44703 </peripheral>
44704 <peripheral>
44705 <name>SPDIF_RX</name>
44706 <description>Receiver Interface</description>
44707 <groupName>SPDIF_RX</groupName>
44708 <baseAddress>0x40004000</baseAddress>
44709 <addressBlock>
44710 <offset>0x0</offset>
44711 <size>0x400</size>
44712 <usage>registers</usage>
44713 </addressBlock>
44714 <registers>
44715 <register>
44716 <name>CR</name>
44717 <displayName>CR</displayName>
44718 <description>Control register</description>
44719 <addressOffset>0x0</addressOffset>
44720 <size>0x20</size>
44721 <access>read-write</access>
44722 <resetValue>0x00000000</resetValue>
44723 <fields>
44724 <field>
44725 <name>SPDIFEN</name>
44726 <description>Peripheral Block Enable</description>
44727 <bitOffset>0</bitOffset>
44728 <bitWidth>2</bitWidth>
44729 </field>
44730 <field>
44731 <name>RXDMAEN</name>
44732 <description>Receiver DMA ENable for data
44733 flow</description>
44734 <bitOffset>2</bitOffset>
44735 <bitWidth>1</bitWidth>
44736 </field>
44737 <field>
44738 <name>RXSTEO</name>
44739 <description>STerEO Mode</description>
44740 <bitOffset>3</bitOffset>
44741 <bitWidth>1</bitWidth>
44742 </field>
44743 <field>
44744 <name>DRFMT</name>
44745 <description>RX Data format</description>
44746 <bitOffset>4</bitOffset>
44747 <bitWidth>2</bitWidth>
44748 </field>
44749 <field>
44750 <name>PMSK</name>
44751 <description>Mask Parity error bit</description>
44752 <bitOffset>6</bitOffset>
44753 <bitWidth>1</bitWidth>
44754 </field>
44755 <field>
44756 <name>VMSK</name>
44757 <description>Mask of Validity bit</description>
44758 <bitOffset>7</bitOffset>
44759 <bitWidth>1</bitWidth>
44760 </field>
44761 <field>
44762 <name>CUMSK</name>
44763 <description>Mask of channel status and user
44764 bits</description>
44765 <bitOffset>8</bitOffset>
44766 <bitWidth>1</bitWidth>
44767 </field>
44768 <field>
44769 <name>PTMSK</name>
44770 <description>Mask of Preamble Type bits</description>
44771 <bitOffset>9</bitOffset>
44772 <bitWidth>1</bitWidth>
44773 </field>
44774 <field>
44775 <name>CBDMAEN</name>
44776 <description>Control Buffer DMA ENable for control
44777 flow</description>
44778 <bitOffset>10</bitOffset>
44779 <bitWidth>1</bitWidth>
44780 </field>
44781 <field>
44782 <name>CHSEL</name>
44783 <description>Channel Selection</description>
44784 <bitOffset>11</bitOffset>
44785 <bitWidth>1</bitWidth>
44786 </field>
44787 <field>
44788 <name>NBTR</name>
44789 <description>Maximum allowed re-tries during
44790 synchronization phase</description>
44791 <bitOffset>12</bitOffset>
44792 <bitWidth>2</bitWidth>
44793 </field>
44794 <field>
44795 <name>WFA</name>
44796 <description>Wait For Activity</description>
44797 <bitOffset>14</bitOffset>
44798 <bitWidth>1</bitWidth>
44799 </field>
44800 <field>
44801 <name>INSEL</name>
44802 <description>input selection</description>
44803 <bitOffset>16</bitOffset>
44804 <bitWidth>3</bitWidth>
44805 </field>
44806 </fields>
44807 </register>
44808 <register>
44809 <name>IMR</name>
44810 <displayName>IMR</displayName>
44811 <description>Interrupt mask register</description>
44812 <addressOffset>0x4</addressOffset>
44813 <size>0x20</size>
44814 <access>read-write</access>
44815 <resetValue>0x00000000</resetValue>
44816 <fields>
44817 <field>
44818 <name>RXNEIE</name>
44819 <description>RXNE interrupt enable</description>
44820 <bitOffset>0</bitOffset>
44821 <bitWidth>1</bitWidth>
44822 </field>
44823 <field>
44824 <name>CSRNEIE</name>
44825 <description>Control Buffer Ready Interrupt
44826 Enable</description>
44827 <bitOffset>1</bitOffset>
44828 <bitWidth>1</bitWidth>
44829 </field>
44830 <field>
44831 <name>PERRIE</name>
44832 <description>Parity error interrupt
44833 enable</description>
44834 <bitOffset>2</bitOffset>
44835 <bitWidth>1</bitWidth>
44836 </field>
44837 <field>
44838 <name>OVRIE</name>
44839 <description>Overrun error Interrupt
44840 Enable</description>
44841 <bitOffset>3</bitOffset>
44842 <bitWidth>1</bitWidth>
44843 </field>
44844 <field>
44845 <name>SBLKIE</name>
44846 <description>Synchronization Block Detected Interrupt
44847 Enable</description>
44848 <bitOffset>4</bitOffset>
44849 <bitWidth>1</bitWidth>
44850 </field>
44851 <field>
44852 <name>SYNCDIE</name>
44853 <description>Synchronization Done</description>
44854 <bitOffset>5</bitOffset>
44855 <bitWidth>1</bitWidth>
44856 </field>
44857 <field>
44858 <name>IFEIE</name>
44859 <description>Serial Interface Error Interrupt
44860 Enable</description>
44861 <bitOffset>6</bitOffset>
44862 <bitWidth>1</bitWidth>
44863 </field>
44864 </fields>
44865 </register>
44866 <register>
44867 <name>SR</name>
44868 <displayName>SR</displayName>
44869 <description>Status register</description>
44870 <addressOffset>0x8</addressOffset>
44871 <size>0x20</size>
44872 <access>read-only</access>
44873 <resetValue>0x00000000</resetValue>
44874 <fields>
44875 <field>
44876 <name>RXNE</name>
44877 <description>Read data register not
44878 empty</description>
44879 <bitOffset>0</bitOffset>
44880 <bitWidth>1</bitWidth>
44881 </field>
44882 <field>
44883 <name>CSRNE</name>
44884 <description>Control Buffer register is not
44885 empty</description>
44886 <bitOffset>1</bitOffset>
44887 <bitWidth>1</bitWidth>
44888 </field>
44889 <field>
44890 <name>PERR</name>
44891 <description>Parity error</description>
44892 <bitOffset>2</bitOffset>
44893 <bitWidth>1</bitWidth>
44894 </field>
44895 <field>
44896 <name>OVR</name>
44897 <description>Overrun error</description>
44898 <bitOffset>3</bitOffset>
44899 <bitWidth>1</bitWidth>
44900 </field>
44901 <field>
44902 <name>SBD</name>
44903 <description>Synchronization Block
44904 Detected</description>
44905 <bitOffset>4</bitOffset>
44906 <bitWidth>1</bitWidth>
44907 </field>
44908 <field>
44909 <name>SYNCD</name>
44910 <description>Synchronization Done</description>
44911 <bitOffset>5</bitOffset>
44912 <bitWidth>1</bitWidth>
44913 </field>
44914 <field>
44915 <name>FERR</name>
44916 <description>Framing error</description>
44917 <bitOffset>6</bitOffset>
44918 <bitWidth>1</bitWidth>
44919 </field>
44920 <field>
44921 <name>SERR</name>
44922 <description>Synchronization error</description>
44923 <bitOffset>7</bitOffset>
44924 <bitWidth>1</bitWidth>
44925 </field>
44926 <field>
44927 <name>TERR</name>
44928 <description>Time-out error</description>
44929 <bitOffset>8</bitOffset>
44930 <bitWidth>1</bitWidth>
44931 </field>
44932 <field>
44933 <name>WIDTH5</name>
44934 <description>Duration of 5 symbols counted with
44935 SPDIF_CLK</description>
44936 <bitOffset>16</bitOffset>
44937 <bitWidth>15</bitWidth>
44938 </field>
44939 </fields>
44940 </register>
44941 <register>
44942 <name>IFCR</name>
44943 <displayName>IFCR</displayName>
44944 <description>Interrupt Flag Clear register</description>
44945 <addressOffset>0xC</addressOffset>
44946 <size>0x20</size>
44947 <access>write-only</access>
44948 <resetValue>0x00000000</resetValue>
44949 <fields>
44950 <field>
44951 <name>PERRCF</name>
44952 <description>Clears the Parity error
44953 flag</description>
44954 <bitOffset>2</bitOffset>
44955 <bitWidth>1</bitWidth>
44956 </field>
44957 <field>
44958 <name>OVRCF</name>
44959 <description>Clears the Overrun error
44960 flag</description>
44961 <bitOffset>3</bitOffset>
44962 <bitWidth>1</bitWidth>
44963 </field>
44964 <field>
44965 <name>SBDCF</name>
44966 <description>Clears the Synchronization Block
44967 Detected flag</description>
44968 <bitOffset>4</bitOffset>
44969 <bitWidth>1</bitWidth>
44970 </field>
44971 <field>
44972 <name>SYNCDCF</name>
44973 <description>Clears the Synchronization Done
44974 flag</description>
44975 <bitOffset>5</bitOffset>
44976 <bitWidth>1</bitWidth>
44977 </field>
44978 </fields>
44979 </register>
44980 <register>
44981 <name>DR</name>
44982 <displayName>DR</displayName>
44983 <description>Data input register</description>
44984 <addressOffset>0x10</addressOffset>
44985 <size>0x20</size>
44986 <access>read-only</access>
44987 <resetValue>0x00000000</resetValue>
44988 <fields>
44989 <field>
44990 <name>DR</name>
44991 <description>Parity Error bit</description>
44992 <bitOffset>0</bitOffset>
44993 <bitWidth>24</bitWidth>
44994 </field>
44995 <field>
44996 <name>PE</name>
44997 <description>Parity Error bit</description>
44998 <bitOffset>24</bitOffset>
44999 <bitWidth>1</bitWidth>
45000 </field>
45001 <field>
45002 <name>V</name>
45003 <description>Validity bit</description>
45004 <bitOffset>25</bitOffset>
45005 <bitWidth>1</bitWidth>
45006 </field>
45007 <field>
45008 <name>U</name>
45009 <description>User bit</description>
45010 <bitOffset>26</bitOffset>
45011 <bitWidth>1</bitWidth>
45012 </field>
45013 <field>
45014 <name>C</name>
45015 <description>Channel Status bit</description>
45016 <bitOffset>27</bitOffset>
45017 <bitWidth>1</bitWidth>
45018 </field>
45019 <field>
45020 <name>PT</name>
45021 <description>Preamble Type</description>
45022 <bitOffset>28</bitOffset>
45023 <bitWidth>2</bitWidth>
45024 </field>
45025 </fields>
45026 </register>
45027 <register>
45028 <name>CSR</name>
45029 <displayName>CSR</displayName>
45030 <description>Channel Status register</description>
45031 <addressOffset>0x14</addressOffset>
45032 <size>0x20</size>
45033 <access>read-only</access>
45034 <resetValue>0x00000000</resetValue>
45035 <fields>
45036 <field>
45037 <name>USR</name>
45038 <description>User data information</description>
45039 <bitOffset>0</bitOffset>
45040 <bitWidth>16</bitWidth>
45041 </field>
45042 <field>
45043 <name>CS</name>
45044 <description>Channel A status
45045 information</description>
45046 <bitOffset>16</bitOffset>
45047 <bitWidth>8</bitWidth>
45048 </field>
45049 <field>
45050 <name>SOB</name>
45051 <description>Start Of Block</description>
45052 <bitOffset>24</bitOffset>
45053 <bitWidth>1</bitWidth>
45054 </field>
45055 </fields>
45056 </register>
45057 <register>
45058 <name>DIR</name>
45059 <displayName>DIR</displayName>
45060 <description>Debug Information register</description>
45061 <addressOffset>0x18</addressOffset>
45062 <size>0x20</size>
45063 <access>read-only</access>
45064 <resetValue>0x00000000</resetValue>
45065 <fields>
45066 <field>
45067 <name>THI</name>
45068 <description>Threshold HIGH</description>
45069 <bitOffset>0</bitOffset>
45070 <bitWidth>13</bitWidth>
45071 </field>
45072 <field>
45073 <name>TLO</name>
45074 <description>Threshold LOW</description>
45075 <bitOffset>16</bitOffset>
45076 <bitWidth>13</bitWidth>
45077 </field>
45078 </fields>
45079 </register>
45080 </registers>
45081 </peripheral>
45082 <peripheral>
45083 <name>SDMMC1</name>
45084 <description>Secure digital input/output
45085 interface</description>
45086 <groupName>SDMMC</groupName>
45087 <baseAddress>0x40012C00</baseAddress>
45088 <addressBlock>
45089 <offset>0x0</offset>
45090 <size>0x400</size>
45091 <usage>registers</usage>
45092 </addressBlock>
45093 <interrupt>
45094 <name>SDMMC1</name>
45095 <description>SDMMC1 global interrupt</description>
45096 <value>49</value>
45097 </interrupt>
45098 <registers>
45099 <register>
45100 <name>POWER</name>
45101 <displayName>POWER</displayName>
45102 <description>power control register</description>
45103 <addressOffset>0x0</addressOffset>
45104 <size>0x20</size>
45105 <access>read-write</access>
45106 <resetValue>0x00000000</resetValue>
45107 <fields>
45108 <field>
45109 <name>PWRCTRL</name>
45110 <description>PWRCTRL</description>
45111 <bitOffset>0</bitOffset>
45112 <bitWidth>2</bitWidth>
45113 </field>
45114 </fields>
45115 </register>
45116 <register>
45117 <name>CLKCR</name>
45118 <displayName>CLKCR</displayName>
45119 <description>SDI clock control register</description>
45120 <addressOffset>0x4</addressOffset>
45121 <size>0x20</size>
45122 <access>read-write</access>
45123 <resetValue>0x00000000</resetValue>
45124 <fields>
45125 <field>
45126 <name>HWFC_EN</name>
45127 <description>HW Flow Control enable</description>
45128 <bitOffset>14</bitOffset>
45129 <bitWidth>1</bitWidth>
45130 </field>
45131 <field>
45132 <name>NEGEDGE</name>
45133 <description>SDIO_CK dephasing selection
45134 bit</description>
45135 <bitOffset>13</bitOffset>
45136 <bitWidth>1</bitWidth>
45137 </field>
45138 <field>
45139 <name>WIDBUS</name>
45140 <description>Wide bus mode enable bit</description>
45141 <bitOffset>11</bitOffset>
45142 <bitWidth>2</bitWidth>
45143 </field>
45144 <field>
45145 <name>BYPASS</name>
45146 <description>Clock divider bypass enable
45147 bit</description>
45148 <bitOffset>10</bitOffset>
45149 <bitWidth>1</bitWidth>
45150 </field>
45151 <field>
45152 <name>PWRSAV</name>
45153 <description>Power saving configuration
45154 bit</description>
45155 <bitOffset>9</bitOffset>
45156 <bitWidth>1</bitWidth>
45157 </field>
45158 <field>
45159 <name>CLKEN</name>
45160 <description>Clock enable bit</description>
45161 <bitOffset>8</bitOffset>
45162 <bitWidth>1</bitWidth>
45163 </field>
45164 <field>
45165 <name>CLKDIV</name>
45166 <description>Clock divide factor</description>
45167 <bitOffset>0</bitOffset>
45168 <bitWidth>8</bitWidth>
45169 </field>
45170 </fields>
45171 </register>
45172 <register>
45173 <name>ARG</name>
45174 <displayName>ARG</displayName>
45175 <description>argument register</description>
45176 <addressOffset>0x8</addressOffset>
45177 <size>0x20</size>
45178 <access>read-write</access>
45179 <resetValue>0x00000000</resetValue>
45180 <fields>
45181 <field>
45182 <name>CMDARG</name>
45183 <description>Command argument</description>
45184 <bitOffset>0</bitOffset>
45185 <bitWidth>32</bitWidth>
45186 </field>
45187 </fields>
45188 </register>
45189 <register>
45190 <name>CMD</name>
45191 <displayName>CMD</displayName>
45192 <description>command register</description>
45193 <addressOffset>0xC</addressOffset>
45194 <size>0x20</size>
45195 <access>read-write</access>
45196 <resetValue>0x00000000</resetValue>
45197 <fields>
45198 <field>
45199 <name>CE_ATACMD</name>
45200 <description>CE-ATA command</description>
45201 <bitOffset>14</bitOffset>
45202 <bitWidth>1</bitWidth>
45203 </field>
45204 <field>
45205 <name>nIEN</name>
45206 <description>not Interrupt Enable</description>
45207 <bitOffset>13</bitOffset>
45208 <bitWidth>1</bitWidth>
45209 </field>
45210 <field>
45211 <name>ENCMDcompl</name>
45212 <description>Enable CMD completion</description>
45213 <bitOffset>12</bitOffset>
45214 <bitWidth>1</bitWidth>
45215 </field>
45216 <field>
45217 <name>SDIOSuspend</name>
45218 <description>SD I/O suspend command</description>
45219 <bitOffset>11</bitOffset>
45220 <bitWidth>1</bitWidth>
45221 </field>
45222 <field>
45223 <name>CPSMEN</name>
45224 <description>Command path state machine (CPSM) Enable
45225 bit</description>
45226 <bitOffset>10</bitOffset>
45227 <bitWidth>1</bitWidth>
45228 </field>
45229 <field>
45230 <name>WAITPEND</name>
45231 <description>CPSM Waits for ends of data transfer
45232 (CmdPend internal signal)</description>
45233 <bitOffset>9</bitOffset>
45234 <bitWidth>1</bitWidth>
45235 </field>
45236 <field>
45237 <name>WAITINT</name>
45238 <description>CPSM waits for interrupt
45239 request</description>
45240 <bitOffset>8</bitOffset>
45241 <bitWidth>1</bitWidth>
45242 </field>
45243 <field>
45244 <name>WAITRESP</name>
45245 <description>Wait for response bits</description>
45246 <bitOffset>6</bitOffset>
45247 <bitWidth>2</bitWidth>
45248 </field>
45249 <field>
45250 <name>CMDINDEX</name>
45251 <description>Command index</description>
45252 <bitOffset>0</bitOffset>
45253 <bitWidth>6</bitWidth>
45254 </field>
45255 </fields>
45256 </register>
45257 <register>
45258 <name>RESPCMD</name>
45259 <displayName>RESPCMD</displayName>
45260 <description>command response register</description>
45261 <addressOffset>0x10</addressOffset>
45262 <size>0x20</size>
45263 <access>read-only</access>
45264 <resetValue>0x00000000</resetValue>
45265 <fields>
45266 <field>
45267 <name>RESPCMD</name>
45268 <description>Response command index</description>
45269 <bitOffset>0</bitOffset>
45270 <bitWidth>6</bitWidth>
45271 </field>
45272 </fields>
45273 </register>
45274 <register>
45275 <name>RESP1</name>
45276 <displayName>RESP1</displayName>
45277 <description>response 1..4 register</description>
45278 <addressOffset>0x14</addressOffset>
45279 <size>0x20</size>
45280 <access>read-only</access>
45281 <resetValue>0x00000000</resetValue>
45282 <fields>
45283 <field>
45284 <name>CARDSTATUS1</name>
45285 <description>see Table 132</description>
45286 <bitOffset>0</bitOffset>
45287 <bitWidth>32</bitWidth>
45288 </field>
45289 </fields>
45290 </register>
45291 <register>
45292 <name>RESP2</name>
45293 <displayName>RESP2</displayName>
45294 <description>response 1..4 register</description>
45295 <addressOffset>0x18</addressOffset>
45296 <size>0x20</size>
45297 <access>read-only</access>
45298 <resetValue>0x00000000</resetValue>
45299 <fields>
45300 <field>
45301 <name>CARDSTATUS2</name>
45302 <description>see Table 132</description>
45303 <bitOffset>0</bitOffset>
45304 <bitWidth>32</bitWidth>
45305 </field>
45306 </fields>
45307 </register>
45308 <register>
45309 <name>RESP3</name>
45310 <displayName>RESP3</displayName>
45311 <description>response 1..4 register</description>
45312 <addressOffset>0x1C</addressOffset>
45313 <size>0x20</size>
45314 <access>read-only</access>
45315 <resetValue>0x00000000</resetValue>
45316 <fields>
45317 <field>
45318 <name>CARDSTATUS3</name>
45319 <description>see Table 132</description>
45320 <bitOffset>0</bitOffset>
45321 <bitWidth>32</bitWidth>
45322 </field>
45323 </fields>
45324 </register>
45325 <register>
45326 <name>RESP4</name>
45327 <displayName>RESP4</displayName>
45328 <description>response 1..4 register</description>
45329 <addressOffset>0x20</addressOffset>
45330 <size>0x20</size>
45331 <access>read-only</access>
45332 <resetValue>0x00000000</resetValue>
45333 <fields>
45334 <field>
45335 <name>CARDSTATUS4</name>
45336 <description>see Table 132</description>
45337 <bitOffset>0</bitOffset>
45338 <bitWidth>32</bitWidth>
45339 </field>
45340 </fields>
45341 </register>
45342 <register>
45343 <name>DTIMER</name>
45344 <displayName>DTIMER</displayName>
45345 <description>data timer register</description>
45346 <addressOffset>0x24</addressOffset>
45347 <size>0x20</size>
45348 <access>read-write</access>
45349 <resetValue>0x00000000</resetValue>
45350 <fields>
45351 <field>
45352 <name>DATATIME</name>
45353 <description>Data timeout period</description>
45354 <bitOffset>0</bitOffset>
45355 <bitWidth>32</bitWidth>
45356 </field>
45357 </fields>
45358 </register>
45359 <register>
45360 <name>DLEN</name>
45361 <displayName>DLEN</displayName>
45362 <description>data length register</description>
45363 <addressOffset>0x28</addressOffset>
45364 <size>0x20</size>
45365 <access>read-write</access>
45366 <resetValue>0x00000000</resetValue>
45367 <fields>
45368 <field>
45369 <name>DATALENGTH</name>
45370 <description>Data length value</description>
45371 <bitOffset>0</bitOffset>
45372 <bitWidth>25</bitWidth>
45373 </field>
45374 </fields>
45375 </register>
45376 <register>
45377 <name>DCTRL</name>
45378 <displayName>DCTRL</displayName>
45379 <description>data control register</description>
45380 <addressOffset>0x2C</addressOffset>
45381 <size>0x20</size>
45382 <access>read-write</access>
45383 <resetValue>0x00000000</resetValue>
45384 <fields>
45385 <field>
45386 <name>SDIOEN</name>
45387 <description>SD I/O enable functions</description>
45388 <bitOffset>11</bitOffset>
45389 <bitWidth>1</bitWidth>
45390 </field>
45391 <field>
45392 <name>RWMOD</name>
45393 <description>Read wait mode</description>
45394 <bitOffset>10</bitOffset>
45395 <bitWidth>1</bitWidth>
45396 </field>
45397 <field>
45398 <name>RWSTOP</name>
45399 <description>Read wait stop</description>
45400 <bitOffset>9</bitOffset>
45401 <bitWidth>1</bitWidth>
45402 </field>
45403 <field>
45404 <name>RWSTART</name>
45405 <description>Read wait start</description>
45406 <bitOffset>8</bitOffset>
45407 <bitWidth>1</bitWidth>
45408 </field>
45409 <field>
45410 <name>DBLOCKSIZE</name>
45411 <description>Data block size</description>
45412 <bitOffset>4</bitOffset>
45413 <bitWidth>4</bitWidth>
45414 </field>
45415 <field>
45416 <name>DMAEN</name>
45417 <description>DMA enable bit</description>
45418 <bitOffset>3</bitOffset>
45419 <bitWidth>1</bitWidth>
45420 </field>
45421 <field>
45422 <name>DTMODE</name>
45423 <description>Data transfer mode selection 1: Stream
45424 or SDIO multibyte data transfer</description>
45425 <bitOffset>2</bitOffset>
45426 <bitWidth>1</bitWidth>
45427 </field>
45428 <field>
45429 <name>DTDIR</name>
45430 <description>Data transfer direction
45431 selection</description>
45432 <bitOffset>1</bitOffset>
45433 <bitWidth>1</bitWidth>
45434 </field>
45435 <field>
45436 <name>DTEN</name>
45437 <description>DTEN</description>
45438 <bitOffset>0</bitOffset>
45439 <bitWidth>1</bitWidth>
45440 </field>
45441 </fields>
45442 </register>
45443 <register>
45444 <name>DCOUNT</name>
45445 <displayName>DCOUNT</displayName>
45446 <description>data counter register</description>
45447 <addressOffset>0x30</addressOffset>
45448 <size>0x20</size>
45449 <access>read-only</access>
45450 <resetValue>0x00000000</resetValue>
45451 <fields>
45452 <field>
45453 <name>DATACOUNT</name>
45454 <description>Data count value</description>
45455 <bitOffset>0</bitOffset>
45456 <bitWidth>25</bitWidth>
45457 </field>
45458 </fields>
45459 </register>
45460 <register>
45461 <name>STA</name>
45462 <displayName>STA</displayName>
45463 <description>status register</description>
45464 <addressOffset>0x34</addressOffset>
45465 <size>0x20</size>
45466 <access>read-only</access>
45467 <resetValue>0x00000000</resetValue>
45468 <fields>
45469 <field>
45470 <name>CEATAEND</name>
45471 <description>CE-ATA command completion signal
45472 received for CMD61</description>
45473 <bitOffset>23</bitOffset>
45474 <bitWidth>1</bitWidth>
45475 </field>
45476 <field>
45477 <name>SDIOIT</name>
45478 <description>SDIO interrupt received</description>
45479 <bitOffset>22</bitOffset>
45480 <bitWidth>1</bitWidth>
45481 </field>
45482 <field>
45483 <name>RXDAVL</name>
45484 <description>Data available in receive
45485 FIFO</description>
45486 <bitOffset>21</bitOffset>
45487 <bitWidth>1</bitWidth>
45488 </field>
45489 <field>
45490 <name>TXDAVL</name>
45491 <description>Data available in transmit
45492 FIFO</description>
45493 <bitOffset>20</bitOffset>
45494 <bitWidth>1</bitWidth>
45495 </field>
45496 <field>
45497 <name>RXFIFOE</name>
45498 <description>Receive FIFO empty</description>
45499 <bitOffset>19</bitOffset>
45500 <bitWidth>1</bitWidth>
45501 </field>
45502 <field>
45503 <name>TXFIFOE</name>
45504 <description>Transmit FIFO empty</description>
45505 <bitOffset>18</bitOffset>
45506 <bitWidth>1</bitWidth>
45507 </field>
45508 <field>
45509 <name>RXFIFOF</name>
45510 <description>Receive FIFO full</description>
45511 <bitOffset>17</bitOffset>
45512 <bitWidth>1</bitWidth>
45513 </field>
45514 <field>
45515 <name>TXFIFOF</name>
45516 <description>Transmit FIFO full</description>
45517 <bitOffset>16</bitOffset>
45518 <bitWidth>1</bitWidth>
45519 </field>
45520 <field>
45521 <name>RXFIFOHF</name>
45522 <description>Receive FIFO half full: there are at
45523 least 8 words in the FIFO</description>
45524 <bitOffset>15</bitOffset>
45525 <bitWidth>1</bitWidth>
45526 </field>
45527 <field>
45528 <name>TXFIFOHE</name>
45529 <description>Transmit FIFO half empty: at least 8
45530 words can be written into the FIFO</description>
45531 <bitOffset>14</bitOffset>
45532 <bitWidth>1</bitWidth>
45533 </field>
45534 <field>
45535 <name>RXACT</name>
45536 <description>Data receive in progress</description>
45537 <bitOffset>13</bitOffset>
45538 <bitWidth>1</bitWidth>
45539 </field>
45540 <field>
45541 <name>TXACT</name>
45542 <description>Data transmit in progress</description>
45543 <bitOffset>12</bitOffset>
45544 <bitWidth>1</bitWidth>
45545 </field>
45546 <field>
45547 <name>CMDACT</name>
45548 <description>Command transfer in
45549 progress</description>
45550 <bitOffset>11</bitOffset>
45551 <bitWidth>1</bitWidth>
45552 </field>
45553 <field>
45554 <name>DBCKEND</name>
45555 <description>Data block sent/received (CRC check
45556 passed)</description>
45557 <bitOffset>10</bitOffset>
45558 <bitWidth>1</bitWidth>
45559 </field>
45560 <field>
45561 <name>STBITERR</name>
45562 <description>Start bit not detected on all data
45563 signals in wide bus mode</description>
45564 <bitOffset>9</bitOffset>
45565 <bitWidth>1</bitWidth>
45566 </field>
45567 <field>
45568 <name>DATAEND</name>
45569 <description>Data end (data counter, SDIDCOUNT, is
45570 zero)</description>
45571 <bitOffset>8</bitOffset>
45572 <bitWidth>1</bitWidth>
45573 </field>
45574 <field>
45575 <name>CMDSENT</name>
45576 <description>Command sent (no response
45577 required)</description>
45578 <bitOffset>7</bitOffset>
45579 <bitWidth>1</bitWidth>
45580 </field>
45581 <field>
45582 <name>CMDREND</name>
45583 <description>Command response received (CRC check
45584 passed)</description>
45585 <bitOffset>6</bitOffset>
45586 <bitWidth>1</bitWidth>
45587 </field>
45588 <field>
45589 <name>RXOVERR</name>
45590 <description>Received FIFO overrun
45591 error</description>
45592 <bitOffset>5</bitOffset>
45593 <bitWidth>1</bitWidth>
45594 </field>
45595 <field>
45596 <name>TXUNDERR</name>
45597 <description>Transmit FIFO underrun
45598 error</description>
45599 <bitOffset>4</bitOffset>
45600 <bitWidth>1</bitWidth>
45601 </field>
45602 <field>
45603 <name>DTIMEOUT</name>
45604 <description>Data timeout</description>
45605 <bitOffset>3</bitOffset>
45606 <bitWidth>1</bitWidth>
45607 </field>
45608 <field>
45609 <name>CTIMEOUT</name>
45610 <description>Command response timeout</description>
45611 <bitOffset>2</bitOffset>
45612 <bitWidth>1</bitWidth>
45613 </field>
45614 <field>
45615 <name>DCRCFAIL</name>
45616 <description>Data block sent/received (CRC check
45617 failed)</description>
45618 <bitOffset>1</bitOffset>
45619 <bitWidth>1</bitWidth>
45620 </field>
45621 <field>
45622 <name>CCRCFAIL</name>
45623 <description>Command response received (CRC check
45624 failed)</description>
45625 <bitOffset>0</bitOffset>
45626 <bitWidth>1</bitWidth>
45627 </field>
45628 </fields>
45629 </register>
45630 <register>
45631 <name>ICR</name>
45632 <displayName>ICR</displayName>
45633 <description>interrupt clear register</description>
45634 <addressOffset>0x38</addressOffset>
45635 <size>0x20</size>
45636 <access>read-write</access>
45637 <resetValue>0x00000000</resetValue>
45638 <fields>
45639 <field>
45640 <name>CEATAENDC</name>
45641 <description>CEATAEND flag clear bit</description>
45642 <bitOffset>23</bitOffset>
45643 <bitWidth>1</bitWidth>
45644 </field>
45645 <field>
45646 <name>SDIOITC</name>
45647 <description>SDIOIT flag clear bit</description>
45648 <bitOffset>22</bitOffset>
45649 <bitWidth>1</bitWidth>
45650 </field>
45651 <field>
45652 <name>DBCKENDC</name>
45653 <description>DBCKEND flag clear bit</description>
45654 <bitOffset>10</bitOffset>
45655 <bitWidth>1</bitWidth>
45656 </field>
45657 <field>
45658 <name>STBITERRC</name>
45659 <description>STBITERR flag clear bit</description>
45660 <bitOffset>9</bitOffset>
45661 <bitWidth>1</bitWidth>
45662 </field>
45663 <field>
45664 <name>DATAENDC</name>
45665 <description>DATAEND flag clear bit</description>
45666 <bitOffset>8</bitOffset>
45667 <bitWidth>1</bitWidth>
45668 </field>
45669 <field>
45670 <name>CMDSENTC</name>
45671 <description>CMDSENT flag clear bit</description>
45672 <bitOffset>7</bitOffset>
45673 <bitWidth>1</bitWidth>
45674 </field>
45675 <field>
45676 <name>CMDRENDC</name>
45677 <description>CMDREND flag clear bit</description>
45678 <bitOffset>6</bitOffset>
45679 <bitWidth>1</bitWidth>
45680 </field>
45681 <field>
45682 <name>RXOVERRC</name>
45683 <description>RXOVERR flag clear bit</description>
45684 <bitOffset>5</bitOffset>
45685 <bitWidth>1</bitWidth>
45686 </field>
45687 <field>
45688 <name>TXUNDERRC</name>
45689 <description>TXUNDERR flag clear bit</description>
45690 <bitOffset>4</bitOffset>
45691 <bitWidth>1</bitWidth>
45692 </field>
45693 <field>
45694 <name>DTIMEOUTC</name>
45695 <description>DTIMEOUT flag clear bit</description>
45696 <bitOffset>3</bitOffset>
45697 <bitWidth>1</bitWidth>
45698 </field>
45699 <field>
45700 <name>CTIMEOUTC</name>
45701 <description>CTIMEOUT flag clear bit</description>
45702 <bitOffset>2</bitOffset>
45703 <bitWidth>1</bitWidth>
45704 </field>
45705 <field>
45706 <name>DCRCFAILC</name>
45707 <description>DCRCFAIL flag clear bit</description>
45708 <bitOffset>1</bitOffset>
45709 <bitWidth>1</bitWidth>
45710 </field>
45711 <field>
45712 <name>CCRCFAILC</name>
45713 <description>CCRCFAIL flag clear bit</description>
45714 <bitOffset>0</bitOffset>
45715 <bitWidth>1</bitWidth>
45716 </field>
45717 </fields>
45718 </register>
45719 <register>
45720 <name>MASK</name>
45721 <displayName>MASK</displayName>
45722 <description>mask register</description>
45723 <addressOffset>0x3C</addressOffset>
45724 <size>0x20</size>
45725 <access>read-write</access>
45726 <resetValue>0x00000000</resetValue>
45727 <fields>
45728 <field>
45729 <name>CEATAENDIE</name>
45730 <description>CE-ATA command completion signal
45731 received interrupt enable</description>
45732 <bitOffset>23</bitOffset>
45733 <bitWidth>1</bitWidth>
45734 </field>
45735 <field>
45736 <name>SDIOITIE</name>
45737 <description>SDIO mode interrupt received interrupt
45738 enable</description>
45739 <bitOffset>22</bitOffset>
45740 <bitWidth>1</bitWidth>
45741 </field>
45742 <field>
45743 <name>RXDAVLIE</name>
45744 <description>Data available in Rx FIFO interrupt
45745 enable</description>
45746 <bitOffset>21</bitOffset>
45747 <bitWidth>1</bitWidth>
45748 </field>
45749 <field>
45750 <name>TXDAVLIE</name>
45751 <description>Data available in Tx FIFO interrupt
45752 enable</description>
45753 <bitOffset>20</bitOffset>
45754 <bitWidth>1</bitWidth>
45755 </field>
45756 <field>
45757 <name>RXFIFOEIE</name>
45758 <description>Rx FIFO empty interrupt
45759 enable</description>
45760 <bitOffset>19</bitOffset>
45761 <bitWidth>1</bitWidth>
45762 </field>
45763 <field>
45764 <name>TXFIFOEIE</name>
45765 <description>Tx FIFO empty interrupt
45766 enable</description>
45767 <bitOffset>18</bitOffset>
45768 <bitWidth>1</bitWidth>
45769 </field>
45770 <field>
45771 <name>RXFIFOFIE</name>
45772 <description>Rx FIFO full interrupt
45773 enable</description>
45774 <bitOffset>17</bitOffset>
45775 <bitWidth>1</bitWidth>
45776 </field>
45777 <field>
45778 <name>TXFIFOFIE</name>
45779 <description>Tx FIFO full interrupt
45780 enable</description>
45781 <bitOffset>16</bitOffset>
45782 <bitWidth>1</bitWidth>
45783 </field>
45784 <field>
45785 <name>RXFIFOHFIE</name>
45786 <description>Rx FIFO half full interrupt
45787 enable</description>
45788 <bitOffset>15</bitOffset>
45789 <bitWidth>1</bitWidth>
45790 </field>
45791 <field>
45792 <name>TXFIFOHEIE</name>
45793 <description>Tx FIFO half empty interrupt
45794 enable</description>
45795 <bitOffset>14</bitOffset>
45796 <bitWidth>1</bitWidth>
45797 </field>
45798 <field>
45799 <name>RXACTIE</name>
45800 <description>Data receive acting interrupt
45801 enable</description>
45802 <bitOffset>13</bitOffset>
45803 <bitWidth>1</bitWidth>
45804 </field>
45805 <field>
45806 <name>TXACTIE</name>
45807 <description>Data transmit acting interrupt
45808 enable</description>
45809 <bitOffset>12</bitOffset>
45810 <bitWidth>1</bitWidth>
45811 </field>
45812 <field>
45813 <name>CMDACTIE</name>
45814 <description>Command acting interrupt
45815 enable</description>
45816 <bitOffset>11</bitOffset>
45817 <bitWidth>1</bitWidth>
45818 </field>
45819 <field>
45820 <name>DBCKENDIE</name>
45821 <description>Data block end interrupt
45822 enable</description>
45823 <bitOffset>10</bitOffset>
45824 <bitWidth>1</bitWidth>
45825 </field>
45826 <field>
45827 <name>STBITERRIE</name>
45828 <description>Start bit error interrupt
45829 enable</description>
45830 <bitOffset>9</bitOffset>
45831 <bitWidth>1</bitWidth>
45832 </field>
45833 <field>
45834 <name>DATAENDIE</name>
45835 <description>Data end interrupt enable</description>
45836 <bitOffset>8</bitOffset>
45837 <bitWidth>1</bitWidth>
45838 </field>
45839 <field>
45840 <name>CMDSENTIE</name>
45841 <description>Command sent interrupt
45842 enable</description>
45843 <bitOffset>7</bitOffset>
45844 <bitWidth>1</bitWidth>
45845 </field>
45846 <field>
45847 <name>CMDRENDIE</name>
45848 <description>Command response received interrupt
45849 enable</description>
45850 <bitOffset>6</bitOffset>
45851 <bitWidth>1</bitWidth>
45852 </field>
45853 <field>
45854 <name>RXOVERRIE</name>
45855 <description>Rx FIFO overrun error interrupt
45856 enable</description>
45857 <bitOffset>5</bitOffset>
45858 <bitWidth>1</bitWidth>
45859 </field>
45860 <field>
45861 <name>TXUNDERRIE</name>
45862 <description>Tx FIFO underrun error interrupt
45863 enable</description>
45864 <bitOffset>4</bitOffset>
45865 <bitWidth>1</bitWidth>
45866 </field>
45867 <field>
45868 <name>DTIMEOUTIE</name>
45869 <description>Data timeout interrupt
45870 enable</description>
45871 <bitOffset>3</bitOffset>
45872 <bitWidth>1</bitWidth>
45873 </field>
45874 <field>
45875 <name>CTIMEOUTIE</name>
45876 <description>Command timeout interrupt
45877 enable</description>
45878 <bitOffset>2</bitOffset>
45879 <bitWidth>1</bitWidth>
45880 </field>
45881 <field>
45882 <name>DCRCFAILIE</name>
45883 <description>Data CRC fail interrupt
45884 enable</description>
45885 <bitOffset>1</bitOffset>
45886 <bitWidth>1</bitWidth>
45887 </field>
45888 <field>
45889 <name>CCRCFAILIE</name>
45890 <description>Command CRC fail interrupt
45891 enable</description>
45892 <bitOffset>0</bitOffset>
45893 <bitWidth>1</bitWidth>
45894 </field>
45895 </fields>
45896 </register>
45897 <register>
45898 <name>FIFOCNT</name>
45899 <displayName>FIFOCNT</displayName>
45900 <description>FIFO counter register</description>
45901 <addressOffset>0x48</addressOffset>
45902 <size>0x20</size>
45903 <access>read-only</access>
45904 <resetValue>0x00000000</resetValue>
45905 <fields>
45906 <field>
45907 <name>FIFOCOUNT</name>
45908 <description>Remaining number of words to be written
45909 to or read from the FIFO</description>
45910 <bitOffset>0</bitOffset>
45911 <bitWidth>24</bitWidth>
45912 </field>
45913 </fields>
45914 </register>
45915 <register>
45916 <name>FIFO</name>
45917 <displayName>FIFO</displayName>
45918 <description>data FIFO register</description>
45919 <addressOffset>0x80</addressOffset>
45920 <size>0x20</size>
45921 <access>read-write</access>
45922 <resetValue>0x00000000</resetValue>
45923 <fields>
45924 <field>
45925 <name>FIFOData</name>
45926 <description>Receive and transmit FIFO
45927 data</description>
45928 <bitOffset>0</bitOffset>
45929 <bitWidth>32</bitWidth>
45930 </field>
45931 </fields>
45932 </register>
45933 </registers>
45934 </peripheral>
45935 <peripheral>
45936 <name>LPTIM1</name>
45937 <description>Low power timer</description>
45938 <groupName>LPTIM</groupName>
45939 <baseAddress>0x40002400</baseAddress>
45940 <addressBlock>
45941 <offset>0x0</offset>
45942 <size>0x400</size>
45943 <usage>registers</usage>
45944 </addressBlock>
45945 <registers>
45946 <register>
45947 <name>ISR</name>
45948 <displayName>ISR</displayName>
45949 <description>Interrupt and Status Register</description>
45950 <addressOffset>0x0</addressOffset>
45951 <size>0x20</size>
45952 <access>read-only</access>
45953 <resetValue>0x00000000</resetValue>
45954 <fields>
45955 <field>
45956 <name>DOWN</name>
45957 <description>Counter direction change up to
45958 down</description>
45959 <bitOffset>6</bitOffset>
45960 <bitWidth>1</bitWidth>
45961 </field>
45962 <field>
45963 <name>UP</name>
45964 <description>Counter direction change down to
45965 up</description>
45966 <bitOffset>5</bitOffset>
45967 <bitWidth>1</bitWidth>
45968 </field>
45969 <field>
45970 <name>ARROK</name>
45971 <description>Autoreload register update
45972 OK</description>
45973 <bitOffset>4</bitOffset>
45974 <bitWidth>1</bitWidth>
45975 </field>
45976 <field>
45977 <name>CMPOK</name>
45978 <description>Compare register update OK</description>
45979 <bitOffset>3</bitOffset>
45980 <bitWidth>1</bitWidth>
45981 </field>
45982 <field>
45983 <name>EXTTRIG</name>
45984 <description>External trigger edge
45985 event</description>
45986 <bitOffset>2</bitOffset>
45987 <bitWidth>1</bitWidth>
45988 </field>
45989 <field>
45990 <name>ARRM</name>
45991 <description>Autoreload match</description>
45992 <bitOffset>1</bitOffset>
45993 <bitWidth>1</bitWidth>
45994 </field>
45995 <field>
45996 <name>CMPM</name>
45997 <description>Compare match</description>
45998 <bitOffset>0</bitOffset>
45999 <bitWidth>1</bitWidth>
46000 </field>
46001 </fields>
46002 </register>
46003 <register>
46004 <name>ICR</name>
46005 <displayName>ICR</displayName>
46006 <description>Interrupt Clear Register</description>
46007 <addressOffset>0x4</addressOffset>
46008 <size>0x20</size>
46009 <access>write-only</access>
46010 <resetValue>0x00000000</resetValue>
46011 <fields>
46012 <field>
46013 <name>DOWNCF</name>
46014 <description>Direction change to down Clear
46015 Flag</description>
46016 <bitOffset>6</bitOffset>
46017 <bitWidth>1</bitWidth>
46018 </field>
46019 <field>
46020 <name>UPCF</name>
46021 <description>Direction change to UP Clear
46022 Flag</description>
46023 <bitOffset>5</bitOffset>
46024 <bitWidth>1</bitWidth>
46025 </field>
46026 <field>
46027 <name>ARROKCF</name>
46028 <description>Autoreload register update OK Clear
46029 Flag</description>
46030 <bitOffset>4</bitOffset>
46031 <bitWidth>1</bitWidth>
46032 </field>
46033 <field>
46034 <name>CMPOKCF</name>
46035 <description>Compare register update OK Clear
46036 Flag</description>
46037 <bitOffset>3</bitOffset>
46038 <bitWidth>1</bitWidth>
46039 </field>
46040 <field>
46041 <name>EXTTRIGCF</name>
46042 <description>External trigger valid edge Clear
46043 Flag</description>
46044 <bitOffset>2</bitOffset>
46045 <bitWidth>1</bitWidth>
46046 </field>
46047 <field>
46048 <name>ARRMCF</name>
46049 <description>Autoreload match Clear
46050 Flag</description>
46051 <bitOffset>1</bitOffset>
46052 <bitWidth>1</bitWidth>
46053 </field>
46054 <field>
46055 <name>CMPMCF</name>
46056 <description>compare match Clear Flag</description>
46057 <bitOffset>0</bitOffset>
46058 <bitWidth>1</bitWidth>
46059 </field>
46060 </fields>
46061 </register>
46062 <register>
46063 <name>IER</name>
46064 <displayName>IER</displayName>
46065 <description>Interrupt Enable Register</description>
46066 <addressOffset>0x8</addressOffset>
46067 <size>0x20</size>
46068 <access>read-write</access>
46069 <resetValue>0x00000000</resetValue>
46070 <fields>
46071 <field>
46072 <name>DOWNIE</name>
46073 <description>Direction change to down Interrupt
46074 Enable</description>
46075 <bitOffset>6</bitOffset>
46076 <bitWidth>1</bitWidth>
46077 </field>
46078 <field>
46079 <name>UPIE</name>
46080 <description>Direction change to UP Interrupt
46081 Enable</description>
46082 <bitOffset>5</bitOffset>
46083 <bitWidth>1</bitWidth>
46084 </field>
46085 <field>
46086 <name>ARROKIE</name>
46087 <description>Autoreload register update OK Interrupt
46088 Enable</description>
46089 <bitOffset>4</bitOffset>
46090 <bitWidth>1</bitWidth>
46091 </field>
46092 <field>
46093 <name>CMPOKIE</name>
46094 <description>Compare register update OK Interrupt
46095 Enable</description>
46096 <bitOffset>3</bitOffset>
46097 <bitWidth>1</bitWidth>
46098 </field>
46099 <field>
46100 <name>EXTTRIGIE</name>
46101 <description>External trigger valid edge Interrupt
46102 Enable</description>
46103 <bitOffset>2</bitOffset>
46104 <bitWidth>1</bitWidth>
46105 </field>
46106 <field>
46107 <name>ARRMIE</name>
46108 <description>Autoreload match Interrupt
46109 Enable</description>
46110 <bitOffset>1</bitOffset>
46111 <bitWidth>1</bitWidth>
46112 </field>
46113 <field>
46114 <name>CMPMIE</name>
46115 <description>Compare match Interrupt
46116 Enable</description>
46117 <bitOffset>0</bitOffset>
46118 <bitWidth>1</bitWidth>
46119 </field>
46120 </fields>
46121 </register>
46122 <register>
46123 <name>CFGR</name>
46124 <displayName>CFGR</displayName>
46125 <description>Configuration Register</description>
46126 <addressOffset>0xC</addressOffset>
46127 <size>0x20</size>
46128 <access>read-write</access>
46129 <resetValue>0x00000000</resetValue>
46130 <fields>
46131 <field>
46132 <name>ENC</name>
46133 <description>Encoder mode enable</description>
46134 <bitOffset>24</bitOffset>
46135 <bitWidth>1</bitWidth>
46136 </field>
46137 <field>
46138 <name>COUNTMODE</name>
46139 <description>counter mode enabled</description>
46140 <bitOffset>23</bitOffset>
46141 <bitWidth>1</bitWidth>
46142 </field>
46143 <field>
46144 <name>PRELOAD</name>
46145 <description>Registers update mode</description>
46146 <bitOffset>22</bitOffset>
46147 <bitWidth>1</bitWidth>
46148 </field>
46149 <field>
46150 <name>WAVPOL</name>
46151 <description>Waveform shape polarity</description>
46152 <bitOffset>21</bitOffset>
46153 <bitWidth>1</bitWidth>
46154 </field>
46155 <field>
46156 <name>WAVE</name>
46157 <description>Waveform shape</description>
46158 <bitOffset>20</bitOffset>
46159 <bitWidth>1</bitWidth>
46160 </field>
46161 <field>
46162 <name>TIMOUT</name>
46163 <description>Timeout enable</description>
46164 <bitOffset>19</bitOffset>
46165 <bitWidth>1</bitWidth>
46166 </field>
46167 <field>
46168 <name>TRIGEN</name>
46169 <description>Trigger enable and
46170 polarity</description>
46171 <bitOffset>17</bitOffset>
46172 <bitWidth>2</bitWidth>
46173 </field>
46174 <field>
46175 <name>TRIGSEL</name>
46176 <description>Trigger selector</description>
46177 <bitOffset>13</bitOffset>
46178 <bitWidth>3</bitWidth>
46179 </field>
46180 <field>
46181 <name>PRESC</name>
46182 <description>Clock prescaler</description>
46183 <bitOffset>9</bitOffset>
46184 <bitWidth>3</bitWidth>
46185 </field>
46186 <field>
46187 <name>TRGFLT</name>
46188 <description>Configurable digital filter for
46189 trigger</description>
46190 <bitOffset>6</bitOffset>
46191 <bitWidth>2</bitWidth>
46192 </field>
46193 <field>
46194 <name>CKFLT</name>
46195 <description>Configurable digital filter for external
46196 clock</description>
46197 <bitOffset>3</bitOffset>
46198 <bitWidth>2</bitWidth>
46199 </field>
46200 <field>
46201 <name>CKPOL</name>
46202 <description>Clock Polarity</description>
46203 <bitOffset>1</bitOffset>
46204 <bitWidth>2</bitWidth>
46205 </field>
46206 <field>
46207 <name>CKSEL</name>
46208 <description>Clock selector</description>
46209 <bitOffset>0</bitOffset>
46210 <bitWidth>1</bitWidth>
46211 </field>
46212 </fields>
46213 </register>
46214 <register>
46215 <name>CR</name>
46216 <displayName>CR</displayName>
46217 <description>Control Register</description>
46218 <addressOffset>0x10</addressOffset>
46219 <size>0x20</size>
46220 <access>read-write</access>
46221 <resetValue>0x00000000</resetValue>
46222 <fields>
46223 <field>
46224 <name>CNTSTRT</name>
46225 <description>Timer start in continuous
46226 mode</description>
46227 <bitOffset>2</bitOffset>
46228 <bitWidth>1</bitWidth>
46229 </field>
46230 <field>
46231 <name>SNGSTRT</name>
46232 <description>LPTIM start in single mode</description>
46233 <bitOffset>1</bitOffset>
46234 <bitWidth>1</bitWidth>
46235 </field>
46236 <field>
46237 <name>ENABLE</name>
46238 <description>LPTIM Enable</description>
46239 <bitOffset>0</bitOffset>
46240 <bitWidth>1</bitWidth>
46241 </field>
46242 </fields>
46243 </register>
46244 <register>
46245 <name>CMP</name>
46246 <displayName>CMP</displayName>
46247 <description>Compare Register</description>
46248 <addressOffset>0x14</addressOffset>
46249 <size>0x20</size>
46250 <access>read-write</access>
46251 <resetValue>0x00000000</resetValue>
46252 <fields>
46253 <field>
46254 <name>CMP</name>
46255 <description>Compare value</description>
46256 <bitOffset>0</bitOffset>
46257 <bitWidth>16</bitWidth>
46258 </field>
46259 </fields>
46260 </register>
46261 <register>
46262 <name>ARR</name>
46263 <displayName>ARR</displayName>
46264 <description>Autoreload Register</description>
46265 <addressOffset>0x18</addressOffset>
46266 <size>0x20</size>
46267 <access>read-write</access>
46268 <resetValue>0x00000001</resetValue>
46269 <fields>
46270 <field>
46271 <name>ARR</name>
46272 <description>Auto reload value</description>
46273 <bitOffset>0</bitOffset>
46274 <bitWidth>16</bitWidth>
46275 </field>
46276 </fields>
46277 </register>
46278 <register>
46279 <name>CNT</name>
46280 <displayName>CNT</displayName>
46281 <description>Counter Register</description>
46282 <addressOffset>0x1C</addressOffset>
46283 <size>0x20</size>
46284 <access>read-only</access>
46285 <resetValue>0x00000000</resetValue>
46286 <fields>
46287 <field>
46288 <name>CNT</name>
46289 <description>Counter value</description>
46290 <bitOffset>0</bitOffset>
46291 <bitWidth>16</bitWidth>
46292 </field>
46293 </fields>
46294 </register>
46295 </registers>
46296 </peripheral>
46297 <peripheral>
46298 <name>I2C1</name>
46299 <description>Inter-integrated circuit</description>
46300 <groupName>I2C</groupName>
46301 <baseAddress>0x40005400</baseAddress>
46302 <addressBlock>
46303 <offset>0x0</offset>
46304 <size>0x400</size>
46305 <usage>registers</usage>
46306 </addressBlock>
46307 <interrupt>
46308 <name>I2C1_EV</name>
46309 <description>I2C1 event interrupt</description>
46310 <value>31</value>
46311 </interrupt>
46312 <interrupt>
46313 <name>I2C1_ER</name>
46314 <description>I2C1 error interrupt</description>
46315 <value>32</value>
46316 </interrupt>
46317 <registers>
46318 <register>
46319 <name>CR1</name>
46320 <displayName>CR1</displayName>
46321 <description>Control register 1</description>
46322 <addressOffset>0x0</addressOffset>
46323 <size>0x20</size>
46324 <access>read-write</access>
46325 <resetValue>0x00000000</resetValue>
46326 <fields>
46327 <field>
46328 <name>PE</name>
46329 <description>Peripheral enable</description>
46330 <bitOffset>0</bitOffset>
46331 <bitWidth>1</bitWidth>
46332 </field>
46333 <field>
46334 <name>TXIE</name>
46335 <description>TX Interrupt enable</description>
46336 <bitOffset>1</bitOffset>
46337 <bitWidth>1</bitWidth>
46338 </field>
46339 <field>
46340 <name>RXIE</name>
46341 <description>RX Interrupt enable</description>
46342 <bitOffset>2</bitOffset>
46343 <bitWidth>1</bitWidth>
46344 </field>
46345 <field>
46346 <name>ADDRIE</name>
46347 <description>Address match interrupt enable (slave
46348 only)</description>
46349 <bitOffset>3</bitOffset>
46350 <bitWidth>1</bitWidth>
46351 </field>
46352 <field>
46353 <name>NACKIE</name>
46354 <description>Not acknowledge received interrupt
46355 enable</description>
46356 <bitOffset>4</bitOffset>
46357 <bitWidth>1</bitWidth>
46358 </field>
46359 <field>
46360 <name>STOPIE</name>
46361 <description>STOP detection Interrupt
46362 enable</description>
46363 <bitOffset>5</bitOffset>
46364 <bitWidth>1</bitWidth>
46365 </field>
46366 <field>
46367 <name>TCIE</name>
46368 <description>Transfer Complete interrupt
46369 enable</description>
46370 <bitOffset>6</bitOffset>
46371 <bitWidth>1</bitWidth>
46372 </field>
46373 <field>
46374 <name>ERRIE</name>
46375 <description>Error interrupts enable</description>
46376 <bitOffset>7</bitOffset>
46377 <bitWidth>1</bitWidth>
46378 </field>
46379 <field>
46380 <name>DNF</name>
46381 <description>Digital noise filter</description>
46382 <bitOffset>8</bitOffset>
46383 <bitWidth>4</bitWidth>
46384 </field>
46385 <field>
46386 <name>ANFOFF</name>
46387 <description>Analog noise filter OFF</description>
46388 <bitOffset>12</bitOffset>
46389 <bitWidth>1</bitWidth>
46390 </field>
46391 <field>
46392 <name>TXDMAEN</name>
46393 <description>DMA transmission requests
46394 enable</description>
46395 <bitOffset>14</bitOffset>
46396 <bitWidth>1</bitWidth>
46397 </field>
46398 <field>
46399 <name>RXDMAEN</name>
46400 <description>DMA reception requests
46401 enable</description>
46402 <bitOffset>15</bitOffset>
46403 <bitWidth>1</bitWidth>
46404 </field>
46405 <field>
46406 <name>SBC</name>
46407 <description>Slave byte control</description>
46408 <bitOffset>16</bitOffset>
46409 <bitWidth>1</bitWidth>
46410 </field>
46411 <field>
46412 <name>NOSTRETCH</name>
46413 <description>Clock stretching disable</description>
46414 <bitOffset>17</bitOffset>
46415 <bitWidth>1</bitWidth>
46416 </field>
46417 <field>
46418 <name>WUPEN</name>
46419 <description>Wakeup from STOP enable</description>
46420 <bitOffset>18</bitOffset>
46421 <bitWidth>1</bitWidth>
46422 </field>
46423 <field>
46424 <name>GCEN</name>
46425 <description>General call enable</description>
46426 <bitOffset>19</bitOffset>
46427 <bitWidth>1</bitWidth>
46428 </field>
46429 <field>
46430 <name>SMBHEN</name>
46431 <description>SMBus Host address enable</description>
46432 <bitOffset>20</bitOffset>
46433 <bitWidth>1</bitWidth>
46434 </field>
46435 <field>
46436 <name>SMBDEN</name>
46437 <description>SMBus Device Default address
46438 enable</description>
46439 <bitOffset>21</bitOffset>
46440 <bitWidth>1</bitWidth>
46441 </field>
46442 <field>
46443 <name>ALERTEN</name>
46444 <description>SMBUS alert enable</description>
46445 <bitOffset>22</bitOffset>
46446 <bitWidth>1</bitWidth>
46447 </field>
46448 <field>
46449 <name>PECEN</name>
46450 <description>PEC enable</description>
46451 <bitOffset>23</bitOffset>
46452 <bitWidth>1</bitWidth>
46453 </field>
46454 </fields>
46455 </register>
46456 <register>
46457 <name>CR2</name>
46458 <displayName>CR2</displayName>
46459 <description>Control register 2</description>
46460 <addressOffset>0x4</addressOffset>
46461 <size>0x20</size>
46462 <access>read-write</access>
46463 <resetValue>0x00000000</resetValue>
46464 <fields>
46465 <field>
46466 <name>PECBYTE</name>
46467 <description>Packet error checking byte</description>
46468 <bitOffset>26</bitOffset>
46469 <bitWidth>1</bitWidth>
46470 </field>
46471 <field>
46472 <name>AUTOEND</name>
46473 <description>Automatic end mode (master
46474 mode)</description>
46475 <bitOffset>25</bitOffset>
46476 <bitWidth>1</bitWidth>
46477 </field>
46478 <field>
46479 <name>RELOAD</name>
46480 <description>NBYTES reload mode</description>
46481 <bitOffset>24</bitOffset>
46482 <bitWidth>1</bitWidth>
46483 </field>
46484 <field>
46485 <name>NBYTES</name>
46486 <description>Number of bytes</description>
46487 <bitOffset>16</bitOffset>
46488 <bitWidth>8</bitWidth>
46489 </field>
46490 <field>
46491 <name>NACK</name>
46492 <description>NACK generation (slave
46493 mode)</description>
46494 <bitOffset>15</bitOffset>
46495 <bitWidth>1</bitWidth>
46496 </field>
46497 <field>
46498 <name>STOP</name>
46499 <description>Stop generation (master
46500 mode)</description>
46501 <bitOffset>14</bitOffset>
46502 <bitWidth>1</bitWidth>
46503 </field>
46504 <field>
46505 <name>START</name>
46506 <description>Start generation</description>
46507 <bitOffset>13</bitOffset>
46508 <bitWidth>1</bitWidth>
46509 </field>
46510 <field>
46511 <name>HEAD10R</name>
46512 <description>10-bit address header only read
46513 direction (master receiver mode)</description>
46514 <bitOffset>12</bitOffset>
46515 <bitWidth>1</bitWidth>
46516 </field>
46517 <field>
46518 <name>ADD10</name>
46519 <description>10-bit addressing mode (master
46520 mode)</description>
46521 <bitOffset>11</bitOffset>
46522 <bitWidth>1</bitWidth>
46523 </field>
46524 <field>
46525 <name>RD_WRN</name>
46526 <description>Transfer direction (master
46527 mode)</description>
46528 <bitOffset>10</bitOffset>
46529 <bitWidth>1</bitWidth>
46530 </field>
46531 <field>
46532 <name>SADD</name>
46533 <description>Slave address bit (master
46534 mode)</description>
46535 <bitOffset>0</bitOffset>
46536 <bitWidth>10</bitWidth>
46537 </field>
46538 </fields>
46539 </register>
46540 <register>
46541 <name>OAR1</name>
46542 <displayName>OAR1</displayName>
46543 <description>Own address register 1</description>
46544 <addressOffset>0x8</addressOffset>
46545 <size>0x20</size>
46546 <access>read-write</access>
46547 <resetValue>0x00000000</resetValue>
46548 <fields>
46549 <field>
46550 <name>OA1</name>
46551 <description>Interface address</description>
46552 <bitOffset>0</bitOffset>
46553 <bitWidth>10</bitWidth>
46554 </field>
46555 <field>
46556 <name>OA1MODE</name>
46557 <description>Own Address 1 10-bit mode</description>
46558 <bitOffset>10</bitOffset>
46559 <bitWidth>1</bitWidth>
46560 </field>
46561 <field>
46562 <name>OA1EN</name>
46563 <description>Own Address 1 enable</description>
46564 <bitOffset>15</bitOffset>
46565 <bitWidth>1</bitWidth>
46566 </field>
46567 </fields>
46568 </register>
46569 <register>
46570 <name>OAR2</name>
46571 <displayName>OAR2</displayName>
46572 <description>Own address register 2</description>
46573 <addressOffset>0xC</addressOffset>
46574 <size>0x20</size>
46575 <access>read-write</access>
46576 <resetValue>0x00000000</resetValue>
46577 <fields>
46578 <field>
46579 <name>OA2</name>
46580 <description>Interface address</description>
46581 <bitOffset>1</bitOffset>
46582 <bitWidth>7</bitWidth>
46583 </field>
46584 <field>
46585 <name>OA2MSK</name>
46586 <description>Own Address 2 masks</description>
46587 <bitOffset>8</bitOffset>
46588 <bitWidth>3</bitWidth>
46589 </field>
46590 <field>
46591 <name>OA2EN</name>
46592 <description>Own Address 2 enable</description>
46593 <bitOffset>15</bitOffset>
46594 <bitWidth>1</bitWidth>
46595 </field>
46596 </fields>
46597 </register>
46598 <register>
46599 <name>TIMINGR</name>
46600 <displayName>TIMINGR</displayName>
46601 <description>Timing register</description>
46602 <addressOffset>0x10</addressOffset>
46603 <size>0x20</size>
46604 <access>read-write</access>
46605 <resetValue>0x00000000</resetValue>
46606 <fields>
46607 <field>
46608 <name>SCLL</name>
46609 <description>SCL low period (master
46610 mode)</description>
46611 <bitOffset>0</bitOffset>
46612 <bitWidth>8</bitWidth>
46613 </field>
46614 <field>
46615 <name>SCLH</name>
46616 <description>SCL high period (master
46617 mode)</description>
46618 <bitOffset>8</bitOffset>
46619 <bitWidth>8</bitWidth>
46620 </field>
46621 <field>
46622 <name>SDADEL</name>
46623 <description>Data hold time</description>
46624 <bitOffset>16</bitOffset>
46625 <bitWidth>4</bitWidth>
46626 </field>
46627 <field>
46628 <name>SCLDEL</name>
46629 <description>Data setup time</description>
46630 <bitOffset>20</bitOffset>
46631 <bitWidth>4</bitWidth>
46632 </field>
46633 <field>
46634 <name>PRESC</name>
46635 <description>Timing prescaler</description>
46636 <bitOffset>28</bitOffset>
46637 <bitWidth>4</bitWidth>
46638 </field>
46639 </fields>
46640 </register>
46641 <register>
46642 <name>TIMEOUTR</name>
46643 <displayName>TIMEOUTR</displayName>
46644 <description>Status register 1</description>
46645 <addressOffset>0x14</addressOffset>
46646 <size>0x20</size>
46647 <access>read-write</access>
46648 <resetValue>0x00000000</resetValue>
46649 <fields>
46650 <field>
46651 <name>TIMEOUTA</name>
46652 <description>Bus timeout A</description>
46653 <bitOffset>0</bitOffset>
46654 <bitWidth>12</bitWidth>
46655 </field>
46656 <field>
46657 <name>TIDLE</name>
46658 <description>Idle clock timeout
46659 detection</description>
46660 <bitOffset>12</bitOffset>
46661 <bitWidth>1</bitWidth>
46662 </field>
46663 <field>
46664 <name>TIMOUTEN</name>
46665 <description>Clock timeout enable</description>
46666 <bitOffset>15</bitOffset>
46667 <bitWidth>1</bitWidth>
46668 </field>
46669 <field>
46670 <name>TIMEOUTB</name>
46671 <description>Bus timeout B</description>
46672 <bitOffset>16</bitOffset>
46673 <bitWidth>12</bitWidth>
46674 </field>
46675 <field>
46676 <name>TEXTEN</name>
46677 <description>Extended clock timeout
46678 enable</description>
46679 <bitOffset>31</bitOffset>
46680 <bitWidth>1</bitWidth>
46681 </field>
46682 </fields>
46683 </register>
46684 <register>
46685 <name>ISR</name>
46686 <displayName>ISR</displayName>
46687 <description>Interrupt and Status register</description>
46688 <addressOffset>0x18</addressOffset>
46689 <size>0x20</size>
46690 <resetValue>0x00000001</resetValue>
46691 <fields>
46692 <field>
46693 <name>ADDCODE</name>
46694 <description>Address match code (Slave
46695 mode)</description>
46696 <bitOffset>17</bitOffset>
46697 <bitWidth>7</bitWidth>
46698 <access>read-only</access>
46699 </field>
46700 <field>
46701 <name>DIR</name>
46702 <description>Transfer direction (Slave
46703 mode)</description>
46704 <bitOffset>16</bitOffset>
46705 <bitWidth>1</bitWidth>
46706 <access>read-only</access>
46707 </field>
46708 <field>
46709 <name>BUSY</name>
46710 <description>Bus busy</description>
46711 <bitOffset>15</bitOffset>
46712 <bitWidth>1</bitWidth>
46713 <access>read-only</access>
46714 </field>
46715 <field>
46716 <name>ALERT</name>
46717 <description>SMBus alert</description>
46718 <bitOffset>13</bitOffset>
46719 <bitWidth>1</bitWidth>
46720 <access>read-only</access>
46721 </field>
46722 <field>
46723 <name>TIMEOUT</name>
46724 <description>Timeout or t_low detection
46725 flag</description>
46726 <bitOffset>12</bitOffset>
46727 <bitWidth>1</bitWidth>
46728 <access>read-only</access>
46729 </field>
46730 <field>
46731 <name>PECERR</name>
46732 <description>PEC Error in reception</description>
46733 <bitOffset>11</bitOffset>
46734 <bitWidth>1</bitWidth>
46735 <access>read-only</access>
46736 </field>
46737 <field>
46738 <name>OVR</name>
46739 <description>Overrun/Underrun (slave
46740 mode)</description>
46741 <bitOffset>10</bitOffset>
46742 <bitWidth>1</bitWidth>
46743 <access>read-only</access>
46744 </field>
46745 <field>
46746 <name>ARLO</name>
46747 <description>Arbitration lost</description>
46748 <bitOffset>9</bitOffset>
46749 <bitWidth>1</bitWidth>
46750 <access>read-only</access>
46751 </field>
46752 <field>
46753 <name>BERR</name>
46754 <description>Bus error</description>
46755 <bitOffset>8</bitOffset>
46756 <bitWidth>1</bitWidth>
46757 <access>read-only</access>
46758 </field>
46759 <field>
46760 <name>TCR</name>
46761 <description>Transfer Complete Reload</description>
46762 <bitOffset>7</bitOffset>
46763 <bitWidth>1</bitWidth>
46764 <access>read-only</access>
46765 </field>
46766 <field>
46767 <name>TC</name>
46768 <description>Transfer Complete (master
46769 mode)</description>
46770 <bitOffset>6</bitOffset>
46771 <bitWidth>1</bitWidth>
46772 <access>read-only</access>
46773 </field>
46774 <field>
46775 <name>STOPF</name>
46776 <description>Stop detection flag</description>
46777 <bitOffset>5</bitOffset>
46778 <bitWidth>1</bitWidth>
46779 <access>read-only</access>
46780 </field>
46781 <field>
46782 <name>NACKF</name>
46783 <description>Not acknowledge received
46784 flag</description>
46785 <bitOffset>4</bitOffset>
46786 <bitWidth>1</bitWidth>
46787 <access>read-only</access>
46788 </field>
46789 <field>
46790 <name>ADDR</name>
46791 <description>Address matched (slave
46792 mode)</description>
46793 <bitOffset>3</bitOffset>
46794 <bitWidth>1</bitWidth>
46795 <access>read-only</access>
46796 </field>
46797 <field>
46798 <name>RXNE</name>
46799 <description>Receive data register not empty
46800 (receivers)</description>
46801 <bitOffset>2</bitOffset>
46802 <bitWidth>1</bitWidth>
46803 <access>read-only</access>
46804 </field>
46805 <field>
46806 <name>TXIS</name>
46807 <description>Transmit interrupt status
46808 (transmitters)</description>
46809 <bitOffset>1</bitOffset>
46810 <bitWidth>1</bitWidth>
46811 <access>read-write</access>
46812 </field>
46813 <field>
46814 <name>TXE</name>
46815 <description>Transmit data register empty
46816 (transmitters)</description>
46817 <bitOffset>0</bitOffset>
46818 <bitWidth>1</bitWidth>
46819 <access>read-write</access>
46820 </field>
46821 </fields>
46822 </register>
46823 <register>
46824 <name>ICR</name>
46825 <displayName>ICR</displayName>
46826 <description>Interrupt clear register</description>
46827 <addressOffset>0x1C</addressOffset>
46828 <size>0x20</size>
46829 <access>write-only</access>
46830 <resetValue>0x00000000</resetValue>
46831 <fields>
46832 <field>
46833 <name>ALERTCF</name>
46834 <description>Alert flag clear</description>
46835 <bitOffset>13</bitOffset>
46836 <bitWidth>1</bitWidth>
46837 </field>
46838 <field>
46839 <name>TIMOUTCF</name>
46840 <description>Timeout detection flag
46841 clear</description>
46842 <bitOffset>12</bitOffset>
46843 <bitWidth>1</bitWidth>
46844 </field>
46845 <field>
46846 <name>PECCF</name>
46847 <description>PEC Error flag clear</description>
46848 <bitOffset>11</bitOffset>
46849 <bitWidth>1</bitWidth>
46850 </field>
46851 <field>
46852 <name>OVRCF</name>
46853 <description>Overrun/Underrun flag
46854 clear</description>
46855 <bitOffset>10</bitOffset>
46856 <bitWidth>1</bitWidth>
46857 </field>
46858 <field>
46859 <name>ARLOCF</name>
46860 <description>Arbitration lost flag
46861 clear</description>
46862 <bitOffset>9</bitOffset>
46863 <bitWidth>1</bitWidth>
46864 </field>
46865 <field>
46866 <name>BERRCF</name>
46867 <description>Bus error flag clear</description>
46868 <bitOffset>8</bitOffset>
46869 <bitWidth>1</bitWidth>
46870 </field>
46871 <field>
46872 <name>STOPCF</name>
46873 <description>Stop detection flag clear</description>
46874 <bitOffset>5</bitOffset>
46875 <bitWidth>1</bitWidth>
46876 </field>
46877 <field>
46878 <name>NACKCF</name>
46879 <description>Not Acknowledge flag clear</description>
46880 <bitOffset>4</bitOffset>
46881 <bitWidth>1</bitWidth>
46882 </field>
46883 <field>
46884 <name>ADDRCF</name>
46885 <description>Address Matched flag clear</description>
46886 <bitOffset>3</bitOffset>
46887 <bitWidth>1</bitWidth>
46888 </field>
46889 </fields>
46890 </register>
46891 <register>
46892 <name>PECR</name>
46893 <displayName>PECR</displayName>
46894 <description>PEC register</description>
46895 <addressOffset>0x20</addressOffset>
46896 <size>0x20</size>
46897 <access>read-only</access>
46898 <resetValue>0x00000000</resetValue>
46899 <fields>
46900 <field>
46901 <name>PEC</name>
46902 <description>Packet error checking
46903 register</description>
46904 <bitOffset>0</bitOffset>
46905 <bitWidth>8</bitWidth>
46906 </field>
46907 </fields>
46908 </register>
46909 <register>
46910 <name>RXDR</name>
46911 <displayName>RXDR</displayName>
46912 <description>Receive data register</description>
46913 <addressOffset>0x24</addressOffset>
46914 <size>0x20</size>
46915 <access>read-only</access>
46916 <resetValue>0x00000000</resetValue>
46917 <fields>
46918 <field>
46919 <name>RXDATA</name>
46920 <description>8-bit receive data</description>
46921 <bitOffset>0</bitOffset>
46922 <bitWidth>8</bitWidth>
46923 </field>
46924 </fields>
46925 </register>
46926 <register>
46927 <name>TXDR</name>
46928 <displayName>TXDR</displayName>
46929 <description>Transmit data register</description>
46930 <addressOffset>0x28</addressOffset>
46931 <size>0x20</size>
46932 <access>read-write</access>
46933 <resetValue>0x00000000</resetValue>
46934 <fields>
46935 <field>
46936 <name>TXDATA</name>
46937 <description>8-bit transmit data</description>
46938 <bitOffset>0</bitOffset>
46939 <bitWidth>8</bitWidth>
46940 </field>
46941 </fields>
46942 </register>
46943 </registers>
46944 </peripheral>
46945 <peripheral derivedFrom="I2C1">
46946 <name>I2C2</name>
46947 <baseAddress>0x40005800</baseAddress>
46948 </peripheral>
46949 <peripheral derivedFrom="I2C1">
46950 <name>I2C3</name>
46951 <baseAddress>0x40005C00</baseAddress>
46952 </peripheral>
46953 <peripheral derivedFrom="I2C1">
46954 <name>I2C4</name>
46955 <baseAddress>0x40006000</baseAddress>
46956 </peripheral>
46957 <peripheral>
46958 <name>RTC</name>
46959 <description>Real-time clock</description>
46960 <groupName>RTC</groupName>
46961 <baseAddress>0x40002800</baseAddress>
46962 <addressBlock>
46963 <offset>0x0</offset>
46964 <size>0x400</size>
46965 <usage>registers</usage>
46966 </addressBlock>
46967 <interrupt>
46968 <name>RTC_WKUP</name>
46969 <description>RTC Tamper or TimeStamp /CSS on LSE through
46970 EXTI line 19 interrupts</description>
46971 <value>3</value>
46972 </interrupt>
46973 <interrupt>
46974 <name>RTC_ALARM</name>
46975 <description>RTC alarms through EXTI line 18
46976 interrupts</description>
46977 <value>41</value>
46978 </interrupt>
46979 <registers>
46980 <register>
46981 <name>TR</name>
46982 <displayName>TR</displayName>
46983 <description>time register</description>
46984 <addressOffset>0x0</addressOffset>
46985 <size>0x20</size>
46986 <access>read-write</access>
46987 <resetValue>0x00000000</resetValue>
46988 <fields>
46989 <field>
46990 <name>PM</name>
46991 <description>AM/PM notation</description>
46992 <bitOffset>22</bitOffset>
46993 <bitWidth>1</bitWidth>
46994 </field>
46995 <field>
46996 <name>HT</name>
46997 <description>Hour tens in BCD format</description>
46998 <bitOffset>20</bitOffset>
46999 <bitWidth>2</bitWidth>
47000 </field>
47001 <field>
47002 <name>HU</name>
47003 <description>Hour units in BCD format</description>
47004 <bitOffset>16</bitOffset>
47005 <bitWidth>4</bitWidth>
47006 </field>
47007 <field>
47008 <name>MNT</name>
47009 <description>Minute tens in BCD format</description>
47010 <bitOffset>12</bitOffset>
47011 <bitWidth>3</bitWidth>
47012 </field>
47013 <field>
47014 <name>MNU</name>
47015 <description>Minute units in BCD format</description>
47016 <bitOffset>8</bitOffset>
47017 <bitWidth>4</bitWidth>
47018 </field>
47019 <field>
47020 <name>ST</name>
47021 <description>Second tens in BCD format</description>
47022 <bitOffset>4</bitOffset>
47023 <bitWidth>3</bitWidth>
47024 </field>
47025 <field>
47026 <name>SU</name>
47027 <description>Second units in BCD format</description>
47028 <bitOffset>0</bitOffset>
47029 <bitWidth>4</bitWidth>
47030 </field>
47031 </fields>
47032 </register>
47033 <register>
47034 <name>DR</name>
47035 <displayName>DR</displayName>
47036 <description>date register</description>
47037 <addressOffset>0x4</addressOffset>
47038 <size>0x20</size>
47039 <access>read-write</access>
47040 <resetValue>0x00002101</resetValue>
47041 <fields>
47042 <field>
47043 <name>YT</name>
47044 <description>Year tens in BCD format</description>
47045 <bitOffset>20</bitOffset>
47046 <bitWidth>4</bitWidth>
47047 </field>
47048 <field>
47049 <name>YU</name>
47050 <description>Year units in BCD format</description>
47051 <bitOffset>16</bitOffset>
47052 <bitWidth>4</bitWidth>
47053 </field>
47054 <field>
47055 <name>WDU</name>
47056 <description>Week day units</description>
47057 <bitOffset>13</bitOffset>
47058 <bitWidth>3</bitWidth>
47059 </field>
47060 <field>
47061 <name>MT</name>
47062 <description>Month tens in BCD format</description>
47063 <bitOffset>12</bitOffset>
47064 <bitWidth>1</bitWidth>
47065 </field>
47066 <field>
47067 <name>MU</name>
47068 <description>Month units in BCD format</description>
47069 <bitOffset>8</bitOffset>
47070 <bitWidth>4</bitWidth>
47071 </field>
47072 <field>
47073 <name>DT</name>
47074 <description>Date tens in BCD format</description>
47075 <bitOffset>4</bitOffset>
47076 <bitWidth>2</bitWidth>
47077 </field>
47078 <field>
47079 <name>DU</name>
47080 <description>Date units in BCD format</description>
47081 <bitOffset>0</bitOffset>
47082 <bitWidth>4</bitWidth>
47083 </field>
47084 </fields>
47085 </register>
47086 <register>
47087 <name>CR</name>
47088 <displayName>CR</displayName>
47089 <description>control register</description>
47090 <addressOffset>0x8</addressOffset>
47091 <size>0x20</size>
47092 <access>read-write</access>
47093 <resetValue>0x00000000</resetValue>
47094 <fields>
47095 <field>
47096 <name>WCKSEL</name>
47097 <description>Wakeup clock selection</description>
47098 <bitOffset>0</bitOffset>
47099 <bitWidth>3</bitWidth>
47100 </field>
47101 <field>
47102 <name>TSEDGE</name>
47103 <description>Time-stamp event active
47104 edge</description>
47105 <bitOffset>3</bitOffset>
47106 <bitWidth>1</bitWidth>
47107 </field>
47108 <field>
47109 <name>REFCKON</name>
47110 <description>Reference clock detection enable (50 or
47111 60 Hz)</description>
47112 <bitOffset>4</bitOffset>
47113 <bitWidth>1</bitWidth>
47114 </field>
47115 <field>
47116 <name>BYPSHAD</name>
47117 <description>Bypass the shadow
47118 registers</description>
47119 <bitOffset>5</bitOffset>
47120 <bitWidth>1</bitWidth>
47121 </field>
47122 <field>
47123 <name>FMT</name>
47124 <description>Hour format</description>
47125 <bitOffset>6</bitOffset>
47126 <bitWidth>1</bitWidth>
47127 </field>
47128 <field>
47129 <name>ALRAE</name>
47130 <description>Alarm A enable</description>
47131 <bitOffset>8</bitOffset>
47132 <bitWidth>1</bitWidth>
47133 </field>
47134 <field>
47135 <name>ALRBE</name>
47136 <description>Alarm B enable</description>
47137 <bitOffset>9</bitOffset>
47138 <bitWidth>1</bitWidth>
47139 </field>
47140 <field>
47141 <name>WUTE</name>
47142 <description>Wakeup timer enable</description>
47143 <bitOffset>10</bitOffset>
47144 <bitWidth>1</bitWidth>
47145 </field>
47146 <field>
47147 <name>TSE</name>
47148 <description>Time stamp enable</description>
47149 <bitOffset>11</bitOffset>
47150 <bitWidth>1</bitWidth>
47151 </field>
47152 <field>
47153 <name>ALRAIE</name>
47154 <description>Alarm A interrupt enable</description>
47155 <bitOffset>12</bitOffset>
47156 <bitWidth>1</bitWidth>
47157 </field>
47158 <field>
47159 <name>ALRBIE</name>
47160 <description>Alarm B interrupt enable</description>
47161 <bitOffset>13</bitOffset>
47162 <bitWidth>1</bitWidth>
47163 </field>
47164 <field>
47165 <name>WUTIE</name>
47166 <description>Wakeup timer interrupt
47167 enable</description>
47168 <bitOffset>14</bitOffset>
47169 <bitWidth>1</bitWidth>
47170 </field>
47171 <field>
47172 <name>TSIE</name>
47173 <description>Time-stamp interrupt
47174 enable</description>
47175 <bitOffset>15</bitOffset>
47176 <bitWidth>1</bitWidth>
47177 </field>
47178 <field>
47179 <name>ADD1H</name>
47180 <description>Add 1 hour (summer time
47181 change)</description>
47182 <bitOffset>16</bitOffset>
47183 <bitWidth>1</bitWidth>
47184 </field>
47185 <field>
47186 <name>SUB1H</name>
47187 <description>Subtract 1 hour (winter time
47188 change)</description>
47189 <bitOffset>17</bitOffset>
47190 <bitWidth>1</bitWidth>
47191 </field>
47192 <field>
47193 <name>BKP</name>
47194 <description>Backup</description>
47195 <bitOffset>18</bitOffset>
47196 <bitWidth>1</bitWidth>
47197 </field>
47198 <field>
47199 <name>COSEL</name>
47200 <description>Calibration output
47201 selection</description>
47202 <bitOffset>19</bitOffset>
47203 <bitWidth>1</bitWidth>
47204 </field>
47205 <field>
47206 <name>POL</name>
47207 <description>Output polarity</description>
47208 <bitOffset>20</bitOffset>
47209 <bitWidth>1</bitWidth>
47210 </field>
47211 <field>
47212 <name>OSEL</name>
47213 <description>Output selection</description>
47214 <bitOffset>21</bitOffset>
47215 <bitWidth>2</bitWidth>
47216 </field>
47217 <field>
47218 <name>COE</name>
47219 <description>Calibration output enable</description>
47220 <bitOffset>23</bitOffset>
47221 <bitWidth>1</bitWidth>
47222 </field>
47223 <field>
47224 <name>ITSE</name>
47225 <description>timestamp on internal event
47226 enable</description>
47227 <bitOffset>24</bitOffset>
47228 <bitWidth>1</bitWidth>
47229 </field>
47230 </fields>
47231 </register>
47232 <register>
47233 <name>ISR</name>
47234 <displayName>ISR</displayName>
47235 <description>initialization and status
47236 register</description>
47237 <addressOffset>0xC</addressOffset>
47238 <size>0x20</size>
47239 <resetValue>0x00000007</resetValue>
47240 <fields>
47241 <field>
47242 <name>ALRAWF</name>
47243 <description>Alarm A write flag</description>
47244 <bitOffset>0</bitOffset>
47245 <bitWidth>1</bitWidth>
47246 <access>read-only</access>
47247 </field>
47248 <field>
47249 <name>ALRBWF</name>
47250 <description>Alarm B write flag</description>
47251 <bitOffset>1</bitOffset>
47252 <bitWidth>1</bitWidth>
47253 <access>read-only</access>
47254 </field>
47255 <field>
47256 <name>WUTWF</name>
47257 <description>Wakeup timer write flag</description>
47258 <bitOffset>2</bitOffset>
47259 <bitWidth>1</bitWidth>
47260 <access>read-only</access>
47261 </field>
47262 <field>
47263 <name>SHPF</name>
47264 <description>Shift operation pending</description>
47265 <bitOffset>3</bitOffset>
47266 <bitWidth>1</bitWidth>
47267 <access>read-write</access>
47268 </field>
47269 <field>
47270 <name>INITS</name>
47271 <description>Initialization status flag</description>
47272 <bitOffset>4</bitOffset>
47273 <bitWidth>1</bitWidth>
47274 <access>read-only</access>
47275 </field>
47276 <field>
47277 <name>RSF</name>
47278 <description>Registers synchronization
47279 flag</description>
47280 <bitOffset>5</bitOffset>
47281 <bitWidth>1</bitWidth>
47282 <access>read-write</access>
47283 </field>
47284 <field>
47285 <name>INITF</name>
47286 <description>Initialization flag</description>
47287 <bitOffset>6</bitOffset>
47288 <bitWidth>1</bitWidth>
47289 <access>read-only</access>
47290 </field>
47291 <field>
47292 <name>INIT</name>
47293 <description>Initialization mode</description>
47294 <bitOffset>7</bitOffset>
47295 <bitWidth>1</bitWidth>
47296 <access>read-write</access>
47297 </field>
47298 <field>
47299 <name>ALRAF</name>
47300 <description>Alarm A flag</description>
47301 <bitOffset>8</bitOffset>
47302 <bitWidth>1</bitWidth>
47303 <access>read-write</access>
47304 </field>
47305 <field>
47306 <name>ALRBF</name>
47307 <description>Alarm B flag</description>
47308 <bitOffset>9</bitOffset>
47309 <bitWidth>1</bitWidth>
47310 <access>read-write</access>
47311 </field>
47312 <field>
47313 <name>WUTF</name>
47314 <description>Wakeup timer flag</description>
47315 <bitOffset>10</bitOffset>
47316 <bitWidth>1</bitWidth>
47317 <access>read-write</access>
47318 </field>
47319 <field>
47320 <name>TSF</name>
47321 <description>Time-stamp flag</description>
47322 <bitOffset>11</bitOffset>
47323 <bitWidth>1</bitWidth>
47324 <access>read-write</access>
47325 </field>
47326 <field>
47327 <name>TSOVF</name>
47328 <description>Time-stamp overflow flag</description>
47329 <bitOffset>12</bitOffset>
47330 <bitWidth>1</bitWidth>
47331 <access>read-write</access>
47332 </field>
47333 <field>
47334 <name>TAMP1F</name>
47335 <description>Tamper detection flag</description>
47336 <bitOffset>13</bitOffset>
47337 <bitWidth>1</bitWidth>
47338 <access>read-write</access>
47339 </field>
47340 <field>
47341 <name>TAMP2F</name>
47342 <description>RTC_TAMP2 detection flag</description>
47343 <bitOffset>14</bitOffset>
47344 <bitWidth>1</bitWidth>
47345 <access>read-write</access>
47346 </field>
47347 <field>
47348 <name>TAMP3F</name>
47349 <description>RTC_TAMP3 detection flag</description>
47350 <bitOffset>15</bitOffset>
47351 <bitWidth>1</bitWidth>
47352 <access>read-write</access>
47353 </field>
47354 <field>
47355 <name>RECALPF</name>
47356 <description>Recalibration pending Flag</description>
47357 <bitOffset>16</bitOffset>
47358 <bitWidth>1</bitWidth>
47359 <access>read-only</access>
47360 </field>
47361 </fields>
47362 </register>
47363 <register>
47364 <name>PRER</name>
47365 <displayName>PRER</displayName>
47366 <description>prescaler register</description>
47367 <addressOffset>0x10</addressOffset>
47368 <size>0x20</size>
47369 <access>read-write</access>
47370 <resetValue>0x007F00FF</resetValue>
47371 <fields>
47372 <field>
47373 <name>PREDIV_A</name>
47374 <description>Asynchronous prescaler
47375 factor</description>
47376 <bitOffset>16</bitOffset>
47377 <bitWidth>7</bitWidth>
47378 </field>
47379 <field>
47380 <name>PREDIV_S</name>
47381 <description>Synchronous prescaler
47382 factor</description>
47383 <bitOffset>0</bitOffset>
47384 <bitWidth>15</bitWidth>
47385 </field>
47386 </fields>
47387 </register>
47388 <register>
47389 <name>WUTR</name>
47390 <displayName>WUTR</displayName>
47391 <description>wakeup timer register</description>
47392 <addressOffset>0x14</addressOffset>
47393 <size>0x20</size>
47394 <access>read-write</access>
47395 <resetValue>0x0000FFFF</resetValue>
47396 <fields>
47397 <field>
47398 <name>WUT</name>
47399 <description>Wakeup auto-reload value
47400 bits</description>
47401 <bitOffset>0</bitOffset>
47402 <bitWidth>16</bitWidth>
47403 </field>
47404 </fields>
47405 </register>
47406 <register>
47407 <name>ALRMAR</name>
47408 <displayName>ALRMAR</displayName>
47409 <description>alarm A register</description>
47410 <addressOffset>0x1C</addressOffset>
47411 <size>0x20</size>
47412 <access>read-write</access>
47413 <resetValue>0x00000000</resetValue>
47414 <fields>
47415 <field>
47416 <name>MSK4</name>
47417 <description>Alarm A date mask</description>
47418 <bitOffset>31</bitOffset>
47419 <bitWidth>1</bitWidth>
47420 </field>
47421 <field>
47422 <name>WDSEL</name>
47423 <description>Week day selection</description>
47424 <bitOffset>30</bitOffset>
47425 <bitWidth>1</bitWidth>
47426 </field>
47427 <field>
47428 <name>DT</name>
47429 <description>Date tens in BCD format</description>
47430 <bitOffset>28</bitOffset>
47431 <bitWidth>2</bitWidth>
47432 </field>
47433 <field>
47434 <name>DU</name>
47435 <description>Date units or day in BCD
47436 format</description>
47437 <bitOffset>24</bitOffset>
47438 <bitWidth>4</bitWidth>
47439 </field>
47440 <field>
47441 <name>MSK3</name>
47442 <description>Alarm A hours mask</description>
47443 <bitOffset>23</bitOffset>
47444 <bitWidth>1</bitWidth>
47445 </field>
47446 <field>
47447 <name>PM</name>
47448 <description>AM/PM notation</description>
47449 <bitOffset>22</bitOffset>
47450 <bitWidth>1</bitWidth>
47451 </field>
47452 <field>
47453 <name>HT</name>
47454 <description>Hour tens in BCD format</description>
47455 <bitOffset>20</bitOffset>
47456 <bitWidth>2</bitWidth>
47457 </field>
47458 <field>
47459 <name>HU</name>
47460 <description>Hour units in BCD format</description>
47461 <bitOffset>16</bitOffset>
47462 <bitWidth>4</bitWidth>
47463 </field>
47464 <field>
47465 <name>MSK2</name>
47466 <description>Alarm A minutes mask</description>
47467 <bitOffset>15</bitOffset>
47468 <bitWidth>1</bitWidth>
47469 </field>
47470 <field>
47471 <name>MNT</name>
47472 <description>Minute tens in BCD format</description>
47473 <bitOffset>12</bitOffset>
47474 <bitWidth>3</bitWidth>
47475 </field>
47476 <field>
47477 <name>MNU</name>
47478 <description>Minute units in BCD format</description>
47479 <bitOffset>8</bitOffset>
47480 <bitWidth>4</bitWidth>
47481 </field>
47482 <field>
47483 <name>MSK1</name>
47484 <description>Alarm A seconds mask</description>
47485 <bitOffset>7</bitOffset>
47486 <bitWidth>1</bitWidth>
47487 </field>
47488 <field>
47489 <name>ST</name>
47490 <description>Second tens in BCD format</description>
47491 <bitOffset>4</bitOffset>
47492 <bitWidth>3</bitWidth>
47493 </field>
47494 <field>
47495 <name>SU</name>
47496 <description>Second units in BCD format</description>
47497 <bitOffset>0</bitOffset>
47498 <bitWidth>4</bitWidth>
47499 </field>
47500 </fields>
47501 </register>
47502 <register>
47503 <name>ALRMBR</name>
47504 <displayName>ALRMBR</displayName>
47505 <description>alarm B register</description>
47506 <addressOffset>0x20</addressOffset>
47507 <size>0x20</size>
47508 <access>read-write</access>
47509 <resetValue>0x00000000</resetValue>
47510 <fields>
47511 <field>
47512 <name>MSK4</name>
47513 <description>Alarm B date mask</description>
47514 <bitOffset>31</bitOffset>
47515 <bitWidth>1</bitWidth>
47516 </field>
47517 <field>
47518 <name>WDSEL</name>
47519 <description>Week day selection</description>
47520 <bitOffset>30</bitOffset>
47521 <bitWidth>1</bitWidth>
47522 </field>
47523 <field>
47524 <name>DT</name>
47525 <description>Date tens in BCD format</description>
47526 <bitOffset>28</bitOffset>
47527 <bitWidth>2</bitWidth>
47528 </field>
47529 <field>
47530 <name>DU</name>
47531 <description>Date units or day in BCD
47532 format</description>
47533 <bitOffset>24</bitOffset>
47534 <bitWidth>4</bitWidth>
47535 </field>
47536 <field>
47537 <name>MSK3</name>
47538 <description>Alarm B hours mask</description>
47539 <bitOffset>23</bitOffset>
47540 <bitWidth>1</bitWidth>
47541 </field>
47542 <field>
47543 <name>PM</name>
47544 <description>AM/PM notation</description>
47545 <bitOffset>22</bitOffset>
47546 <bitWidth>1</bitWidth>
47547 </field>
47548 <field>
47549 <name>HT</name>
47550 <description>Hour tens in BCD format</description>
47551 <bitOffset>20</bitOffset>
47552 <bitWidth>2</bitWidth>
47553 </field>
47554 <field>
47555 <name>HU</name>
47556 <description>Hour units in BCD format</description>
47557 <bitOffset>16</bitOffset>
47558 <bitWidth>4</bitWidth>
47559 </field>
47560 <field>
47561 <name>MSK2</name>
47562 <description>Alarm B minutes mask</description>
47563 <bitOffset>15</bitOffset>
47564 <bitWidth>1</bitWidth>
47565 </field>
47566 <field>
47567 <name>MNT</name>
47568 <description>Minute tens in BCD format</description>
47569 <bitOffset>12</bitOffset>
47570 <bitWidth>3</bitWidth>
47571 </field>
47572 <field>
47573 <name>MNU</name>
47574 <description>Minute units in BCD format</description>
47575 <bitOffset>8</bitOffset>
47576 <bitWidth>4</bitWidth>
47577 </field>
47578 <field>
47579 <name>MSK1</name>
47580 <description>Alarm B seconds mask</description>
47581 <bitOffset>7</bitOffset>
47582 <bitWidth>1</bitWidth>
47583 </field>
47584 <field>
47585 <name>ST</name>
47586 <description>Second tens in BCD format</description>
47587 <bitOffset>4</bitOffset>
47588 <bitWidth>3</bitWidth>
47589 </field>
47590 <field>
47591 <name>SU</name>
47592 <description>Second units in BCD format</description>
47593 <bitOffset>0</bitOffset>
47594 <bitWidth>4</bitWidth>
47595 </field>
47596 </fields>
47597 </register>
47598 <register>
47599 <name>WPR</name>
47600 <displayName>WPR</displayName>
47601 <description>write protection register</description>
47602 <addressOffset>0x24</addressOffset>
47603 <size>0x20</size>
47604 <access>write-only</access>
47605 <resetValue>0x00000000</resetValue>
47606 <fields>
47607 <field>
47608 <name>KEY</name>
47609 <description>Write protection key</description>
47610 <bitOffset>0</bitOffset>
47611 <bitWidth>8</bitWidth>
47612 </field>
47613 </fields>
47614 </register>
47615 <register>
47616 <name>SSR</name>
47617 <displayName>SSR</displayName>
47618 <description>sub second register</description>
47619 <addressOffset>0x28</addressOffset>
47620 <size>0x20</size>
47621 <access>read-only</access>
47622 <resetValue>0x00000000</resetValue>
47623 <fields>
47624 <field>
47625 <name>SS</name>
47626 <description>Sub second value</description>
47627 <bitOffset>0</bitOffset>
47628 <bitWidth>16</bitWidth>
47629 </field>
47630 </fields>
47631 </register>
47632 <register>
47633 <name>SHIFTR</name>
47634 <displayName>SHIFTR</displayName>
47635 <description>shift control register</description>
47636 <addressOffset>0x2C</addressOffset>
47637 <size>0x20</size>
47638 <access>write-only</access>
47639 <resetValue>0x00000000</resetValue>
47640 <fields>
47641 <field>
47642 <name>ADD1S</name>
47643 <description>Add one second</description>
47644 <bitOffset>31</bitOffset>
47645 <bitWidth>1</bitWidth>
47646 </field>
47647 <field>
47648 <name>SUBFS</name>
47649 <description>Subtract a fraction of a
47650 second</description>
47651 <bitOffset>0</bitOffset>
47652 <bitWidth>15</bitWidth>
47653 </field>
47654 </fields>
47655 </register>
47656 <register>
47657 <name>TSTR</name>
47658 <displayName>TSTR</displayName>
47659 <description>time stamp time register</description>
47660 <addressOffset>0x30</addressOffset>
47661 <size>0x20</size>
47662 <access>read-only</access>
47663 <resetValue>0x00000000</resetValue>
47664 <fields>
47665 <field>
47666 <name>SU</name>
47667 <description>Second units in BCD format</description>
47668 <bitOffset>0</bitOffset>
47669 <bitWidth>4</bitWidth>
47670 </field>
47671 <field>
47672 <name>ST</name>
47673 <description>Second tens in BCD format</description>
47674 <bitOffset>4</bitOffset>
47675 <bitWidth>3</bitWidth>
47676 </field>
47677 <field>
47678 <name>MNU</name>
47679 <description>Minute units in BCD format</description>
47680 <bitOffset>8</bitOffset>
47681 <bitWidth>4</bitWidth>
47682 </field>
47683 <field>
47684 <name>MNT</name>
47685 <description>Minute tens in BCD format</description>
47686 <bitOffset>12</bitOffset>
47687 <bitWidth>3</bitWidth>
47688 </field>
47689 <field>
47690 <name>HU</name>
47691 <description>Hour units in BCD format</description>
47692 <bitOffset>16</bitOffset>
47693 <bitWidth>4</bitWidth>
47694 </field>
47695 <field>
47696 <name>HT</name>
47697 <description>Hour tens in BCD format</description>
47698 <bitOffset>20</bitOffset>
47699 <bitWidth>2</bitWidth>
47700 </field>
47701 <field>
47702 <name>PM</name>
47703 <description>AM/PM notation</description>
47704 <bitOffset>22</bitOffset>
47705 <bitWidth>1</bitWidth>
47706 </field>
47707 </fields>
47708 </register>
47709 <register>
47710 <name>TSDR</name>
47711 <displayName>TSDR</displayName>
47712 <description>time stamp date register</description>
47713 <addressOffset>0x34</addressOffset>
47714 <size>0x20</size>
47715 <access>read-only</access>
47716 <resetValue>0x00000000</resetValue>
47717 <fields>
47718 <field>
47719 <name>WDU</name>
47720 <description>Week day units</description>
47721 <bitOffset>13</bitOffset>
47722 <bitWidth>3</bitWidth>
47723 </field>
47724 <field>
47725 <name>MT</name>
47726 <description>Month tens in BCD format</description>
47727 <bitOffset>12</bitOffset>
47728 <bitWidth>1</bitWidth>
47729 </field>
47730 <field>
47731 <name>MU</name>
47732 <description>Month units in BCD format</description>
47733 <bitOffset>8</bitOffset>
47734 <bitWidth>4</bitWidth>
47735 </field>
47736 <field>
47737 <name>DT</name>
47738 <description>Date tens in BCD format</description>
47739 <bitOffset>4</bitOffset>
47740 <bitWidth>2</bitWidth>
47741 </field>
47742 <field>
47743 <name>DU</name>
47744 <description>Date units in BCD format</description>
47745 <bitOffset>0</bitOffset>
47746 <bitWidth>4</bitWidth>
47747 </field>
47748 </fields>
47749 </register>
47750 <register>
47751 <name>TSSSR</name>
47752 <displayName>TSSSR</displayName>
47753 <description>timestamp sub second register</description>
47754 <addressOffset>0x38</addressOffset>
47755 <size>0x20</size>
47756 <access>read-only</access>
47757 <resetValue>0x00000000</resetValue>
47758 <fields>
47759 <field>
47760 <name>SS</name>
47761 <description>Sub second value</description>
47762 <bitOffset>0</bitOffset>
47763 <bitWidth>16</bitWidth>
47764 </field>
47765 </fields>
47766 </register>
47767 <register>
47768 <name>CALR</name>
47769 <displayName>CALR</displayName>
47770 <description>calibration register</description>
47771 <addressOffset>0x3C</addressOffset>
47772 <size>0x20</size>
47773 <access>read-write</access>
47774 <resetValue>0x00000000</resetValue>
47775 <fields>
47776 <field>
47777 <name>CALP</name>
47778 <description>Increase frequency of RTC by 488.5
47779 ppm</description>
47780 <bitOffset>15</bitOffset>
47781 <bitWidth>1</bitWidth>
47782 </field>
47783 <field>
47784 <name>CALW8</name>
47785 <description>Use an 8-second calibration cycle
47786 period</description>
47787 <bitOffset>14</bitOffset>
47788 <bitWidth>1</bitWidth>
47789 </field>
47790 <field>
47791 <name>CALW16</name>
47792 <description>Use a 16-second calibration cycle
47793 period</description>
47794 <bitOffset>13</bitOffset>
47795 <bitWidth>1</bitWidth>
47796 </field>
47797 <field>
47798 <name>CALM</name>
47799 <description>Calibration minus</description>
47800 <bitOffset>0</bitOffset>
47801 <bitWidth>9</bitWidth>
47802 </field>
47803 </fields>
47804 </register>
47805 <register>
47806 <name>TAMPCR</name>
47807 <displayName>TAMPCR</displayName>
47808 <description>tamper configuration register</description>
47809 <addressOffset>0x40</addressOffset>
47810 <size>0x20</size>
47811 <access>read-write</access>
47812 <resetValue>0x00000000</resetValue>
47813 <fields>
47814 <field>
47815 <name>TAMP1E</name>
47816 <description>Tamper 1 detection enable</description>
47817 <bitOffset>0</bitOffset>
47818 <bitWidth>1</bitWidth>
47819 </field>
47820 <field>
47821 <name>TAMP1TRG</name>
47822 <description>Active level for tamper 1</description>
47823 <bitOffset>1</bitOffset>
47824 <bitWidth>1</bitWidth>
47825 </field>
47826 <field>
47827 <name>TAMPIE</name>
47828 <description>Tamper interrupt enable</description>
47829 <bitOffset>2</bitOffset>
47830 <bitWidth>1</bitWidth>
47831 </field>
47832 <field>
47833 <name>TAMP2E</name>
47834 <description>Tamper 2 detection enable</description>
47835 <bitOffset>3</bitOffset>
47836 <bitWidth>1</bitWidth>
47837 </field>
47838 <field>
47839 <name>TAMP2TRG</name>
47840 <description>Active level for tamper 2</description>
47841 <bitOffset>4</bitOffset>
47842 <bitWidth>1</bitWidth>
47843 </field>
47844 <field>
47845 <name>TAMP3E</name>
47846 <description>Tamper 3 detection enable</description>
47847 <bitOffset>5</bitOffset>
47848 <bitWidth>1</bitWidth>
47849 </field>
47850 <field>
47851 <name>TAMP3TRG</name>
47852 <description>Active level for tamper 3</description>
47853 <bitOffset>6</bitOffset>
47854 <bitWidth>1</bitWidth>
47855 </field>
47856 <field>
47857 <name>TAMPTS</name>
47858 <description>Activate timestamp on tamper detection
47859 event</description>
47860 <bitOffset>7</bitOffset>
47861 <bitWidth>1</bitWidth>
47862 </field>
47863 <field>
47864 <name>TAMPFREQ</name>
47865 <description>Tamper sampling frequency</description>
47866 <bitOffset>8</bitOffset>
47867 <bitWidth>3</bitWidth>
47868 </field>
47869 <field>
47870 <name>TAMPFLT</name>
47871 <description>Tamper filter count</description>
47872 <bitOffset>11</bitOffset>
47873 <bitWidth>2</bitWidth>
47874 </field>
47875 <field>
47876 <name>TAMPPRCH</name>
47877 <description>Tamper precharge duration</description>
47878 <bitOffset>13</bitOffset>
47879 <bitWidth>2</bitWidth>
47880 </field>
47881 <field>
47882 <name>TAMPPUDIS</name>
47883 <description>TAMPER pull-up disable</description>
47884 <bitOffset>15</bitOffset>
47885 <bitWidth>1</bitWidth>
47886 </field>
47887 <field>
47888 <name>TAMP1IE</name>
47889 <description>Tamper 1 interrupt enable</description>
47890 <bitOffset>16</bitOffset>
47891 <bitWidth>1</bitWidth>
47892 </field>
47893 <field>
47894 <name>TAMP1NOERASE</name>
47895 <description>Tamper 1 no erase</description>
47896 <bitOffset>17</bitOffset>
47897 <bitWidth>1</bitWidth>
47898 </field>
47899 <field>
47900 <name>TAMP1MF</name>
47901 <description>Tamper 1 mask flag</description>
47902 <bitOffset>18</bitOffset>
47903 <bitWidth>1</bitWidth>
47904 </field>
47905 <field>
47906 <name>TAMP2IE</name>
47907 <description>Tamper 2 interrupt enable</description>
47908 <bitOffset>19</bitOffset>
47909 <bitWidth>1</bitWidth>
47910 </field>
47911 <field>
47912 <name>TAMP2NOERASE</name>
47913 <description>Tamper 2 no erase</description>
47914 <bitOffset>20</bitOffset>
47915 <bitWidth>1</bitWidth>
47916 </field>
47917 <field>
47918 <name>TAMP2MF</name>
47919 <description>Tamper 2 mask flag</description>
47920 <bitOffset>21</bitOffset>
47921 <bitWidth>1</bitWidth>
47922 </field>
47923 <field>
47924 <name>TAMP3IE</name>
47925 <description>Tamper 3 interrupt enable</description>
47926 <bitOffset>22</bitOffset>
47927 <bitWidth>1</bitWidth>
47928 </field>
47929 <field>
47930 <name>TAMP3NOERASE</name>
47931 <description>Tamper 3 no erase</description>
47932 <bitOffset>23</bitOffset>
47933 <bitWidth>1</bitWidth>
47934 </field>
47935 <field>
47936 <name>TAMP3MF</name>
47937 <description>Tamper 3 mask flag</description>
47938 <bitOffset>24</bitOffset>
47939 <bitWidth>1</bitWidth>
47940 </field>
47941 </fields>
47942 </register>
47943 <register>
47944 <name>ALRMASSR</name>
47945 <displayName>ALRMASSR</displayName>
47946 <description>alarm A sub second register</description>
47947 <addressOffset>0x44</addressOffset>
47948 <size>0x20</size>
47949 <access>read-write</access>
47950 <resetValue>0x00000000</resetValue>
47951 <fields>
47952 <field>
47953 <name>MASKSS</name>
47954 <description>Mask the most-significant bits starting
47955 at this bit</description>
47956 <bitOffset>24</bitOffset>
47957 <bitWidth>4</bitWidth>
47958 </field>
47959 <field>
47960 <name>SS</name>
47961 <description>Sub seconds value</description>
47962 <bitOffset>0</bitOffset>
47963 <bitWidth>15</bitWidth>
47964 </field>
47965 </fields>
47966 </register>
47967 <register>
47968 <name>ALRMBSSR</name>
47969 <displayName>ALRMBSSR</displayName>
47970 <description>alarm B sub second register</description>
47971 <addressOffset>0x48</addressOffset>
47972 <size>0x20</size>
47973 <access>read-write</access>
47974 <resetValue>0x00000000</resetValue>
47975 <fields>
47976 <field>
47977 <name>MASKSS</name>
47978 <description>Mask the most-significant bits starting
47979 at this bit</description>
47980 <bitOffset>24</bitOffset>
47981 <bitWidth>4</bitWidth>
47982 </field>
47983 <field>
47984 <name>SS</name>
47985 <description>Sub seconds value</description>
47986 <bitOffset>0</bitOffset>
47987 <bitWidth>15</bitWidth>
47988 </field>
47989 </fields>
47990 </register>
47991 <register>
47992 <name>OR</name>
47993 <displayName>OR</displayName>
47994 <description>option register</description>
47995 <addressOffset>0x4C</addressOffset>
47996 <size>0x20</size>
47997 <access>read-write</access>
47998 <resetValue>0x00000000</resetValue>
47999 <fields>
48000 <field>
48001 <name>RTC_ALARM_TYPE</name>
48002 <description>RTC_ALARM on PC13 output
48003 type</description>
48004 <bitOffset>0</bitOffset>
48005 <bitWidth>1</bitWidth>
48006 </field>
48007 <field>
48008 <name>RTC_OUT_RMP</name>
48009 <description>RTC_OUT remap</description>
48010 <bitOffset>1</bitOffset>
48011 <bitWidth>1</bitWidth>
48012 </field>
48013 </fields>
48014 </register>
48015 <register>
48016 <name>BKP0R</name>
48017 <displayName>BKP0R</displayName>
48018 <description>backup register</description>
48019 <addressOffset>0x50</addressOffset>
48020 <size>0x20</size>
48021 <access>read-write</access>
48022 <resetValue>0x00000000</resetValue>
48023 <fields>
48024 <field>
48025 <name>BKP</name>
48026 <description>BKP</description>
48027 <bitOffset>0</bitOffset>
48028 <bitWidth>32</bitWidth>
48029 </field>
48030 </fields>
48031 </register>
48032 <register>
48033 <name>BKP1R</name>
48034 <displayName>BKP1R</displayName>
48035 <description>backup register</description>
48036 <addressOffset>0x54</addressOffset>
48037 <size>0x20</size>
48038 <access>read-write</access>
48039 <resetValue>0x00000000</resetValue>
48040 <fields>
48041 <field>
48042 <name>BKP</name>
48043 <description>BKP</description>
48044 <bitOffset>0</bitOffset>
48045 <bitWidth>32</bitWidth>
48046 </field>
48047 </fields>
48048 </register>
48049 <register>
48050 <name>BKP2R</name>
48051 <displayName>BKP2R</displayName>
48052 <description>backup register</description>
48053 <addressOffset>0x58</addressOffset>
48054 <size>0x20</size>
48055 <access>read-write</access>
48056 <resetValue>0x00000000</resetValue>
48057 <fields>
48058 <field>
48059 <name>BKP</name>
48060 <description>BKP</description>
48061 <bitOffset>0</bitOffset>
48062 <bitWidth>32</bitWidth>
48063 </field>
48064 </fields>
48065 </register>
48066 <register>
48067 <name>BKP3R</name>
48068 <displayName>BKP3R</displayName>
48069 <description>backup register</description>
48070 <addressOffset>0x5C</addressOffset>
48071 <size>0x20</size>
48072 <access>read-write</access>
48073 <resetValue>0x00000000</resetValue>
48074 <fields>
48075 <field>
48076 <name>BKP</name>
48077 <description>BKP</description>
48078 <bitOffset>0</bitOffset>
48079 <bitWidth>32</bitWidth>
48080 </field>
48081 </fields>
48082 </register>
48083 <register>
48084 <name>BKP4R</name>
48085 <displayName>BKP4R</displayName>
48086 <description>backup register</description>
48087 <addressOffset>0x60</addressOffset>
48088 <size>0x20</size>
48089 <access>read-write</access>
48090 <resetValue>0x00000000</resetValue>
48091 <fields>
48092 <field>
48093 <name>BKP</name>
48094 <description>BKP</description>
48095 <bitOffset>0</bitOffset>
48096 <bitWidth>32</bitWidth>
48097 </field>
48098 </fields>
48099 </register>
48100 <register>
48101 <name>BKP5R</name>
48102 <displayName>BKP5R</displayName>
48103 <description>backup register</description>
48104 <addressOffset>0x64</addressOffset>
48105 <size>0x20</size>
48106 <access>read-write</access>
48107 <resetValue>0x00000000</resetValue>
48108 <fields>
48109 <field>
48110 <name>BKP</name>
48111 <description>BKP</description>
48112 <bitOffset>0</bitOffset>
48113 <bitWidth>32</bitWidth>
48114 </field>
48115 </fields>
48116 </register>
48117 <register>
48118 <name>BKP6R</name>
48119 <displayName>BKP6R</displayName>
48120 <description>backup register</description>
48121 <addressOffset>0x68</addressOffset>
48122 <size>0x20</size>
48123 <access>read-write</access>
48124 <resetValue>0x00000000</resetValue>
48125 <fields>
48126 <field>
48127 <name>BKP</name>
48128 <description>BKP</description>
48129 <bitOffset>0</bitOffset>
48130 <bitWidth>32</bitWidth>
48131 </field>
48132 </fields>
48133 </register>
48134 <register>
48135 <name>BKP7R</name>
48136 <displayName>BKP7R</displayName>
48137 <description>backup register</description>
48138 <addressOffset>0x6C</addressOffset>
48139 <size>0x20</size>
48140 <access>read-write</access>
48141 <resetValue>0x00000000</resetValue>
48142 <fields>
48143 <field>
48144 <name>BKP</name>
48145 <description>BKP</description>
48146 <bitOffset>0</bitOffset>
48147 <bitWidth>32</bitWidth>
48148 </field>
48149 </fields>
48150 </register>
48151 <register>
48152 <name>BKP8R</name>
48153 <displayName>BKP8R</displayName>
48154 <description>backup register</description>
48155 <addressOffset>0x70</addressOffset>
48156 <size>0x20</size>
48157 <access>read-write</access>
48158 <resetValue>0x00000000</resetValue>
48159 <fields>
48160 <field>
48161 <name>BKP</name>
48162 <description>BKP</description>
48163 <bitOffset>0</bitOffset>
48164 <bitWidth>32</bitWidth>
48165 </field>
48166 </fields>
48167 </register>
48168 <register>
48169 <name>BKP9R</name>
48170 <displayName>BKP9R</displayName>
48171 <description>backup register</description>
48172 <addressOffset>0x74</addressOffset>
48173 <size>0x20</size>
48174 <access>read-write</access>
48175 <resetValue>0x00000000</resetValue>
48176 <fields>
48177 <field>
48178 <name>BKP</name>
48179 <description>BKP</description>
48180 <bitOffset>0</bitOffset>
48181 <bitWidth>32</bitWidth>
48182 </field>
48183 </fields>
48184 </register>
48185 <register>
48186 <name>BKP10R</name>
48187 <displayName>BKP10R</displayName>
48188 <description>backup register</description>
48189 <addressOffset>0x78</addressOffset>
48190 <size>0x20</size>
48191 <access>read-write</access>
48192 <resetValue>0x00000000</resetValue>
48193 <fields>
48194 <field>
48195 <name>BKP</name>
48196 <description>BKP</description>
48197 <bitOffset>0</bitOffset>
48198 <bitWidth>32</bitWidth>
48199 </field>
48200 </fields>
48201 </register>
48202 <register>
48203 <name>BKP11R</name>
48204 <displayName>BKP11R</displayName>
48205 <description>backup register</description>
48206 <addressOffset>0x7C</addressOffset>
48207 <size>0x20</size>
48208 <access>read-write</access>
48209 <resetValue>0x00000000</resetValue>
48210 <fields>
48211 <field>
48212 <name>BKP</name>
48213 <description>BKP</description>
48214 <bitOffset>0</bitOffset>
48215 <bitWidth>32</bitWidth>
48216 </field>
48217 </fields>
48218 </register>
48219 <register>
48220 <name>BKP12R</name>
48221 <displayName>BKP12R</displayName>
48222 <description>backup register</description>
48223 <addressOffset>0x80</addressOffset>
48224 <size>0x20</size>
48225 <access>read-write</access>
48226 <resetValue>0x00000000</resetValue>
48227 <fields>
48228 <field>
48229 <name>BKP</name>
48230 <description>BKP</description>
48231 <bitOffset>0</bitOffset>
48232 <bitWidth>32</bitWidth>
48233 </field>
48234 </fields>
48235 </register>
48236 <register>
48237 <name>BKP13R</name>
48238 <displayName>BKP13R</displayName>
48239 <description>backup register</description>
48240 <addressOffset>0x84</addressOffset>
48241 <size>0x20</size>
48242 <access>read-write</access>
48243 <resetValue>0x00000000</resetValue>
48244 <fields>
48245 <field>
48246 <name>BKP</name>
48247 <description>BKP</description>
48248 <bitOffset>0</bitOffset>
48249 <bitWidth>32</bitWidth>
48250 </field>
48251 </fields>
48252 </register>
48253 <register>
48254 <name>BKP14R</name>
48255 <displayName>BKP14R</displayName>
48256 <description>backup register</description>
48257 <addressOffset>0x88</addressOffset>
48258 <size>0x20</size>
48259 <access>read-write</access>
48260 <resetValue>0x00000000</resetValue>
48261 <fields>
48262 <field>
48263 <name>BKP</name>
48264 <description>BKP</description>
48265 <bitOffset>0</bitOffset>
48266 <bitWidth>32</bitWidth>
48267 </field>
48268 </fields>
48269 </register>
48270 <register>
48271 <name>BKP15R</name>
48272 <displayName>BKP15R</displayName>
48273 <description>backup register</description>
48274 <addressOffset>0x8C</addressOffset>
48275 <size>0x20</size>
48276 <access>read-write</access>
48277 <resetValue>0x00000000</resetValue>
48278 <fields>
48279 <field>
48280 <name>BKP</name>
48281 <description>BKP</description>
48282 <bitOffset>0</bitOffset>
48283 <bitWidth>32</bitWidth>
48284 </field>
48285 </fields>
48286 </register>
48287 <register>
48288 <name>BKP16R</name>
48289 <displayName>BKP16R</displayName>
48290 <description>backup register</description>
48291 <addressOffset>0x90</addressOffset>
48292 <size>0x20</size>
48293 <access>read-write</access>
48294 <resetValue>0x00000000</resetValue>
48295 <fields>
48296 <field>
48297 <name>BKP</name>
48298 <description>BKP</description>
48299 <bitOffset>0</bitOffset>
48300 <bitWidth>32</bitWidth>
48301 </field>
48302 </fields>
48303 </register>
48304 <register>
48305 <name>BKP17R</name>
48306 <displayName>BKP17R</displayName>
48307 <description>backup register</description>
48308 <addressOffset>0x94</addressOffset>
48309 <size>0x20</size>
48310 <access>read-write</access>
48311 <resetValue>0x00000000</resetValue>
48312 <fields>
48313 <field>
48314 <name>BKP</name>
48315 <description>BKP</description>
48316 <bitOffset>0</bitOffset>
48317 <bitWidth>32</bitWidth>
48318 </field>
48319 </fields>
48320 </register>
48321 <register>
48322 <name>BKP18R</name>
48323 <displayName>BKP18R</displayName>
48324 <description>backup register</description>
48325 <addressOffset>0x98</addressOffset>
48326 <size>0x20</size>
48327 <access>read-write</access>
48328 <resetValue>0x00000000</resetValue>
48329 <fields>
48330 <field>
48331 <name>BKP</name>
48332 <description>BKP</description>
48333 <bitOffset>0</bitOffset>
48334 <bitWidth>32</bitWidth>
48335 </field>
48336 </fields>
48337 </register>
48338 <register>
48339 <name>BKP19R</name>
48340 <displayName>BKP19R</displayName>
48341 <description>backup register</description>
48342 <addressOffset>0x9C</addressOffset>
48343 <size>0x20</size>
48344 <access>read-write</access>
48345 <resetValue>0x00000000</resetValue>
48346 <fields>
48347 <field>
48348 <name>BKP</name>
48349 <description>BKP</description>
48350 <bitOffset>0</bitOffset>
48351 <bitWidth>32</bitWidth>
48352 </field>
48353 </fields>
48354 </register>
48355 <register>
48356 <name>BKP20R</name>
48357 <displayName>BKP20R</displayName>
48358 <description>backup register</description>
48359 <addressOffset>0xA0</addressOffset>
48360 <size>0x20</size>
48361 <access>read-write</access>
48362 <resetValue>0x00000000</resetValue>
48363 <fields>
48364 <field>
48365 <name>BKP</name>
48366 <description>BKP</description>
48367 <bitOffset>0</bitOffset>
48368 <bitWidth>32</bitWidth>
48369 </field>
48370 </fields>
48371 </register>
48372 <register>
48373 <name>BKP21R</name>
48374 <displayName>BKP21R</displayName>
48375 <description>backup register</description>
48376 <addressOffset>0xA4</addressOffset>
48377 <size>0x20</size>
48378 <access>read-write</access>
48379 <resetValue>0x00000000</resetValue>
48380 <fields>
48381 <field>
48382 <name>BKP</name>
48383 <description>BKP</description>
48384 <bitOffset>0</bitOffset>
48385 <bitWidth>32</bitWidth>
48386 </field>
48387 </fields>
48388 </register>
48389 <register>
48390 <name>BKP22R</name>
48391 <displayName>BKP22R</displayName>
48392 <description>backup register</description>
48393 <addressOffset>0xA8</addressOffset>
48394 <size>0x20</size>
48395 <access>read-write</access>
48396 <resetValue>0x00000000</resetValue>
48397 <fields>
48398 <field>
48399 <name>BKP</name>
48400 <description>BKP</description>
48401 <bitOffset>0</bitOffset>
48402 <bitWidth>32</bitWidth>
48403 </field>
48404 </fields>
48405 </register>
48406 <register>
48407 <name>BKP23R</name>
48408 <displayName>BKP23R</displayName>
48409 <description>backup register</description>
48410 <addressOffset>0xAC</addressOffset>
48411 <size>0x20</size>
48412 <access>read-write</access>
48413 <resetValue>0x00000000</resetValue>
48414 <fields>
48415 <field>
48416 <name>BKP</name>
48417 <description>BKP</description>
48418 <bitOffset>0</bitOffset>
48419 <bitWidth>32</bitWidth>
48420 </field>
48421 </fields>
48422 </register>
48423 <register>
48424 <name>BKP24R</name>
48425 <displayName>BKP24R</displayName>
48426 <description>backup register</description>
48427 <addressOffset>0xB0</addressOffset>
48428 <size>0x20</size>
48429 <access>read-write</access>
48430 <resetValue>0x00000000</resetValue>
48431 <fields>
48432 <field>
48433 <name>BKP</name>
48434 <description>BKP</description>
48435 <bitOffset>0</bitOffset>
48436 <bitWidth>32</bitWidth>
48437 </field>
48438 </fields>
48439 </register>
48440 <register>
48441 <name>BKP25R</name>
48442 <displayName>BKP25R</displayName>
48443 <description>backup register</description>
48444 <addressOffset>0xB4</addressOffset>
48445 <size>0x20</size>
48446 <access>read-write</access>
48447 <resetValue>0x00000000</resetValue>
48448 <fields>
48449 <field>
48450 <name>BKP</name>
48451 <description>BKP</description>
48452 <bitOffset>0</bitOffset>
48453 <bitWidth>32</bitWidth>
48454 </field>
48455 </fields>
48456 </register>
48457 <register>
48458 <name>BKP26R</name>
48459 <displayName>BKP26R</displayName>
48460 <description>backup register</description>
48461 <addressOffset>0xB8</addressOffset>
48462 <size>0x20</size>
48463 <access>read-write</access>
48464 <resetValue>0x00000000</resetValue>
48465 <fields>
48466 <field>
48467 <name>BKP</name>
48468 <description>BKP</description>
48469 <bitOffset>0</bitOffset>
48470 <bitWidth>32</bitWidth>
48471 </field>
48472 </fields>
48473 </register>
48474 <register>
48475 <name>BKP27R</name>
48476 <displayName>BKP27R</displayName>
48477 <description>backup register</description>
48478 <addressOffset>0xBC</addressOffset>
48479 <size>0x20</size>
48480 <access>read-write</access>
48481 <resetValue>0x00000000</resetValue>
48482 <fields>
48483 <field>
48484 <name>BKP</name>
48485 <description>BKP</description>
48486 <bitOffset>0</bitOffset>
48487 <bitWidth>32</bitWidth>
48488 </field>
48489 </fields>
48490 </register>
48491 <register>
48492 <name>BKP28R</name>
48493 <displayName>BKP28R</displayName>
48494 <description>backup register</description>
48495 <addressOffset>0xC0</addressOffset>
48496 <size>0x20</size>
48497 <access>read-write</access>
48498 <resetValue>0x00000000</resetValue>
48499 <fields>
48500 <field>
48501 <name>BKP</name>
48502 <description>BKP</description>
48503 <bitOffset>0</bitOffset>
48504 <bitWidth>32</bitWidth>
48505 </field>
48506 </fields>
48507 </register>
48508 <register>
48509 <name>BKP29R</name>
48510 <displayName>BKP29R</displayName>
48511 <description>backup register</description>
48512 <addressOffset>0xC4</addressOffset>
48513 <size>0x20</size>
48514 <access>read-write</access>
48515 <resetValue>0x00000000</resetValue>
48516 <fields>
48517 <field>
48518 <name>BKP</name>
48519 <description>BKP</description>
48520 <bitOffset>0</bitOffset>
48521 <bitWidth>32</bitWidth>
48522 </field>
48523 </fields>
48524 </register>
48525 <register>
48526 <name>BKP30R</name>
48527 <displayName>BKP30R</displayName>
48528 <description>backup register</description>
48529 <addressOffset>0xC8</addressOffset>
48530 <size>0x20</size>
48531 <access>read-write</access>
48532 <resetValue>0x00000000</resetValue>
48533 <fields>
48534 <field>
48535 <name>BKP</name>
48536 <description>BKP</description>
48537 <bitOffset>0</bitOffset>
48538 <bitWidth>32</bitWidth>
48539 </field>
48540 </fields>
48541 </register>
48542 <register>
48543 <name>BKP31R</name>
48544 <displayName>BKP31R</displayName>
48545 <description>backup register</description>
48546 <addressOffset>0xCC</addressOffset>
48547 <size>0x20</size>
48548 <access>read-write</access>
48549 <resetValue>0x00000000</resetValue>
48550 <fields>
48551 <field>
48552 <name>BKP</name>
48553 <description>BKP</description>
48554 <bitOffset>0</bitOffset>
48555 <bitWidth>32</bitWidth>
48556 </field>
48557 </fields>
48558 </register>
48559 </registers>
48560 </peripheral>
48561 <peripheral>
48562 <name>USART6</name>
48563 <description>Universal synchronous asynchronous receiver
48564 transmitter</description>
48565 <groupName>USART</groupName>
48566 <baseAddress>0x40011400</baseAddress>
48567 <addressBlock>
48568 <offset>0x0</offset>
48569 <size>0x400</size>
48570 <usage>registers</usage>
48571 </addressBlock>
48572 <registers>
48573 <register>
48574 <name>CR1</name>
48575 <displayName>CR1</displayName>
48576 <description>Control register 1</description>
48577 <addressOffset>0x0</addressOffset>
48578 <size>0x20</size>
48579 <access>read-write</access>
48580 <resetValue>0x0000</resetValue>
48581 <fields>
48582 <field>
48583 <name>M1</name>
48584 <description>Word length</description>
48585 <bitOffset>28</bitOffset>
48586 <bitWidth>1</bitWidth>
48587 </field>
48588 <field>
48589 <name>EOBIE</name>
48590 <description>End of Block interrupt
48591 enable</description>
48592 <bitOffset>27</bitOffset>
48593 <bitWidth>1</bitWidth>
48594 </field>
48595 <field>
48596 <name>RTOIE</name>
48597 <description>Receiver timeout interrupt
48598 enable</description>
48599 <bitOffset>26</bitOffset>
48600 <bitWidth>1</bitWidth>
48601 </field>
48602 <field>
48603 <name>DEAT4</name>
48604 <description>Driver Enable assertion
48605 time</description>
48606 <bitOffset>25</bitOffset>
48607 <bitWidth>1</bitWidth>
48608 </field>
48609 <field>
48610 <name>DEAT3</name>
48611 <description>DEAT3</description>
48612 <bitOffset>24</bitOffset>
48613 <bitWidth>1</bitWidth>
48614 </field>
48615 <field>
48616 <name>DEAT2</name>
48617 <description>DEAT2</description>
48618 <bitOffset>23</bitOffset>
48619 <bitWidth>1</bitWidth>
48620 </field>
48621 <field>
48622 <name>DEAT1</name>
48623 <description>DEAT1</description>
48624 <bitOffset>22</bitOffset>
48625 <bitWidth>1</bitWidth>
48626 </field>
48627 <field>
48628 <name>DEAT0</name>
48629 <description>DEAT0</description>
48630 <bitOffset>21</bitOffset>
48631 <bitWidth>1</bitWidth>
48632 </field>
48633 <field>
48634 <name>DEDT4</name>
48635 <description>Driver Enable de-assertion
48636 time</description>
48637 <bitOffset>20</bitOffset>
48638 <bitWidth>1</bitWidth>
48639 </field>
48640 <field>
48641 <name>DEDT3</name>
48642 <description>DEDT3</description>
48643 <bitOffset>19</bitOffset>
48644 <bitWidth>1</bitWidth>
48645 </field>
48646 <field>
48647 <name>DEDT2</name>
48648 <description>DEDT2</description>
48649 <bitOffset>18</bitOffset>
48650 <bitWidth>1</bitWidth>
48651 </field>
48652 <field>
48653 <name>DEDT1</name>
48654 <description>DEDT1</description>
48655 <bitOffset>17</bitOffset>
48656 <bitWidth>1</bitWidth>
48657 </field>
48658 <field>
48659 <name>DEDT0</name>
48660 <description>DEDT0</description>
48661 <bitOffset>16</bitOffset>
48662 <bitWidth>1</bitWidth>
48663 </field>
48664 <field>
48665 <name>OVER8</name>
48666 <description>Oversampling mode</description>
48667 <bitOffset>15</bitOffset>
48668 <bitWidth>1</bitWidth>
48669 </field>
48670 <field>
48671 <name>CMIE</name>
48672 <description>Character match interrupt
48673 enable</description>
48674 <bitOffset>14</bitOffset>
48675 <bitWidth>1</bitWidth>
48676 </field>
48677 <field>
48678 <name>MME</name>
48679 <description>Mute mode enable</description>
48680 <bitOffset>13</bitOffset>
48681 <bitWidth>1</bitWidth>
48682 </field>
48683 <field>
48684 <name>M0</name>
48685 <description>Word length</description>
48686 <bitOffset>12</bitOffset>
48687 <bitWidth>1</bitWidth>
48688 </field>
48689 <field>
48690 <name>WAKE</name>
48691 <description>Receiver wakeup method</description>
48692 <bitOffset>11</bitOffset>
48693 <bitWidth>1</bitWidth>
48694 </field>
48695 <field>
48696 <name>PCE</name>
48697 <description>Parity control enable</description>
48698 <bitOffset>10</bitOffset>
48699 <bitWidth>1</bitWidth>
48700 </field>
48701 <field>
48702 <name>PS</name>
48703 <description>Parity selection</description>
48704 <bitOffset>9</bitOffset>
48705 <bitWidth>1</bitWidth>
48706 </field>
48707 <field>
48708 <name>PEIE</name>
48709 <description>PE interrupt enable</description>
48710 <bitOffset>8</bitOffset>
48711 <bitWidth>1</bitWidth>
48712 </field>
48713 <field>
48714 <name>TXEIE</name>
48715 <description>interrupt enable</description>
48716 <bitOffset>7</bitOffset>
48717 <bitWidth>1</bitWidth>
48718 </field>
48719 <field>
48720 <name>TCIE</name>
48721 <description>Transmission complete interrupt
48722 enable</description>
48723 <bitOffset>6</bitOffset>
48724 <bitWidth>1</bitWidth>
48725 </field>
48726 <field>
48727 <name>RXNEIE</name>
48728 <description>RXNE interrupt enable</description>
48729 <bitOffset>5</bitOffset>
48730 <bitWidth>1</bitWidth>
48731 </field>
48732 <field>
48733 <name>IDLEIE</name>
48734 <description>IDLE interrupt enable</description>
48735 <bitOffset>4</bitOffset>
48736 <bitWidth>1</bitWidth>
48737 </field>
48738 <field>
48739 <name>TE</name>
48740 <description>Transmitter enable</description>
48741 <bitOffset>3</bitOffset>
48742 <bitWidth>1</bitWidth>
48743 </field>
48744 <field>
48745 <name>RE</name>
48746 <description>Receiver enable</description>
48747 <bitOffset>2</bitOffset>
48748 <bitWidth>1</bitWidth>
48749 </field>
48750 <field>
48751 <name>UESM</name>
48752 <description>USART enable in Stop mode</description>
48753 <bitOffset>1</bitOffset>
48754 <bitWidth>1</bitWidth>
48755 </field>
48756 <field>
48757 <name>UE</name>
48758 <description>USART enable</description>
48759 <bitOffset>0</bitOffset>
48760 <bitWidth>1</bitWidth>
48761 </field>
48762 </fields>
48763 </register>
48764 <register>
48765 <name>CR2</name>
48766 <displayName>CR2</displayName>
48767 <description>Control register 2</description>
48768 <addressOffset>0x4</addressOffset>
48769 <size>0x20</size>
48770 <access>read-write</access>
48771 <resetValue>0x0000</resetValue>
48772 <fields>
48773 <field>
48774 <name>ADD4_7</name>
48775 <description>Address of the USART node</description>
48776 <bitOffset>28</bitOffset>
48777 <bitWidth>4</bitWidth>
48778 </field>
48779 <field>
48780 <name>ADD0_3</name>
48781 <description>Address of the USART node</description>
48782 <bitOffset>24</bitOffset>
48783 <bitWidth>4</bitWidth>
48784 </field>
48785 <field>
48786 <name>RTOEN</name>
48787 <description>Receiver timeout enable</description>
48788 <bitOffset>23</bitOffset>
48789 <bitWidth>1</bitWidth>
48790 </field>
48791 <field>
48792 <name>ABRMOD1</name>
48793 <description>Auto baud rate mode</description>
48794 <bitOffset>22</bitOffset>
48795 <bitWidth>1</bitWidth>
48796 </field>
48797 <field>
48798 <name>ABRMOD0</name>
48799 <description>ABRMOD0</description>
48800 <bitOffset>21</bitOffset>
48801 <bitWidth>1</bitWidth>
48802 </field>
48803 <field>
48804 <name>ABREN</name>
48805 <description>Auto baud rate enable</description>
48806 <bitOffset>20</bitOffset>
48807 <bitWidth>1</bitWidth>
48808 </field>
48809 <field>
48810 <name>MSBFIRST</name>
48811 <description>Most significant bit first</description>
48812 <bitOffset>19</bitOffset>
48813 <bitWidth>1</bitWidth>
48814 </field>
48815 <field>
48816 <name>TAINV</name>
48817 <description>Binary data inversion</description>
48818 <bitOffset>18</bitOffset>
48819 <bitWidth>1</bitWidth>
48820 </field>
48821 <field>
48822 <name>TXINV</name>
48823 <description>TX pin active level
48824 inversion</description>
48825 <bitOffset>17</bitOffset>
48826 <bitWidth>1</bitWidth>
48827 </field>
48828 <field>
48829 <name>RXINV</name>
48830 <description>RX pin active level
48831 inversion</description>
48832 <bitOffset>16</bitOffset>
48833 <bitWidth>1</bitWidth>
48834 </field>
48835 <field>
48836 <name>SWAP</name>
48837 <description>Swap TX/RX pins</description>
48838 <bitOffset>15</bitOffset>
48839 <bitWidth>1</bitWidth>
48840 </field>
48841 <field>
48842 <name>LINEN</name>
48843 <description>LIN mode enable</description>
48844 <bitOffset>14</bitOffset>
48845 <bitWidth>1</bitWidth>
48846 </field>
48847 <field>
48848 <name>STOP</name>
48849 <description>STOP bits</description>
48850 <bitOffset>12</bitOffset>
48851 <bitWidth>2</bitWidth>
48852 </field>
48853 <field>
48854 <name>CLKEN</name>
48855 <description>Clock enable</description>
48856 <bitOffset>11</bitOffset>
48857 <bitWidth>1</bitWidth>
48858 </field>
48859 <field>
48860 <name>CPOL</name>
48861 <description>Clock polarity</description>
48862 <bitOffset>10</bitOffset>
48863 <bitWidth>1</bitWidth>
48864 </field>
48865 <field>
48866 <name>CPHA</name>
48867 <description>Clock phase</description>
48868 <bitOffset>9</bitOffset>
48869 <bitWidth>1</bitWidth>
48870 </field>
48871 <field>
48872 <name>LBCL</name>
48873 <description>Last bit clock pulse</description>
48874 <bitOffset>8</bitOffset>
48875 <bitWidth>1</bitWidth>
48876 </field>
48877 <field>
48878 <name>LBDIE</name>
48879 <description>LIN break detection interrupt
48880 enable</description>
48881 <bitOffset>6</bitOffset>
48882 <bitWidth>1</bitWidth>
48883 </field>
48884 <field>
48885 <name>LBDL</name>
48886 <description>LIN break detection length</description>
48887 <bitOffset>5</bitOffset>
48888 <bitWidth>1</bitWidth>
48889 </field>
48890 <field>
48891 <name>ADDM7</name>
48892 <description>7-bit Address Detection/4-bit Address
48893 Detection</description>
48894 <bitOffset>4</bitOffset>
48895 <bitWidth>1</bitWidth>
48896 </field>
48897 </fields>
48898 </register>
48899 <register>
48900 <name>CR3</name>
48901 <displayName>CR3</displayName>
48902 <description>Control register 3</description>
48903 <addressOffset>0x8</addressOffset>
48904 <size>0x20</size>
48905 <access>read-write</access>
48906 <resetValue>0x0000</resetValue>
48907 <fields>
48908 <field>
48909 <name>WUFIE</name>
48910 <description>Wakeup from Stop mode interrupt
48911 enable</description>
48912 <bitOffset>22</bitOffset>
48913 <bitWidth>1</bitWidth>
48914 </field>
48915 <field>
48916 <name>WUS</name>
48917 <description>Wakeup from Stop mode interrupt flag
48918 selection</description>
48919 <bitOffset>20</bitOffset>
48920 <bitWidth>2</bitWidth>
48921 </field>
48922 <field>
48923 <name>SCARCNT</name>
48924 <description>Smartcard auto-retry count</description>
48925 <bitOffset>17</bitOffset>
48926 <bitWidth>3</bitWidth>
48927 </field>
48928 <field>
48929 <name>DEP</name>
48930 <description>Driver enable polarity
48931 selection</description>
48932 <bitOffset>15</bitOffset>
48933 <bitWidth>1</bitWidth>
48934 </field>
48935 <field>
48936 <name>DEM</name>
48937 <description>Driver enable mode</description>
48938 <bitOffset>14</bitOffset>
48939 <bitWidth>1</bitWidth>
48940 </field>
48941 <field>
48942 <name>DDRE</name>
48943 <description>DMA Disable on Reception
48944 Error</description>
48945 <bitOffset>13</bitOffset>
48946 <bitWidth>1</bitWidth>
48947 </field>
48948 <field>
48949 <name>OVRDIS</name>
48950 <description>Overrun Disable</description>
48951 <bitOffset>12</bitOffset>
48952 <bitWidth>1</bitWidth>
48953 </field>
48954 <field>
48955 <name>ONEBIT</name>
48956 <description>One sample bit method
48957 enable</description>
48958 <bitOffset>11</bitOffset>
48959 <bitWidth>1</bitWidth>
48960 </field>
48961 <field>
48962 <name>CTSIE</name>
48963 <description>CTS interrupt enable</description>
48964 <bitOffset>10</bitOffset>
48965 <bitWidth>1</bitWidth>
48966 </field>
48967 <field>
48968 <name>CTSE</name>
48969 <description>CTS enable</description>
48970 <bitOffset>9</bitOffset>
48971 <bitWidth>1</bitWidth>
48972 </field>
48973 <field>
48974 <name>RTSE</name>
48975 <description>RTS enable</description>
48976 <bitOffset>8</bitOffset>
48977 <bitWidth>1</bitWidth>
48978 </field>
48979 <field>
48980 <name>DMAT</name>
48981 <description>DMA enable transmitter</description>
48982 <bitOffset>7</bitOffset>
48983 <bitWidth>1</bitWidth>
48984 </field>
48985 <field>
48986 <name>DMAR</name>
48987 <description>DMA enable receiver</description>
48988 <bitOffset>6</bitOffset>
48989 <bitWidth>1</bitWidth>
48990 </field>
48991 <field>
48992 <name>SCEN</name>
48993 <description>Smartcard mode enable</description>
48994 <bitOffset>5</bitOffset>
48995 <bitWidth>1</bitWidth>
48996 </field>
48997 <field>
48998 <name>NACK</name>
48999 <description>Smartcard NACK enable</description>
49000 <bitOffset>4</bitOffset>
49001 <bitWidth>1</bitWidth>
49002 </field>
49003 <field>
49004 <name>HDSEL</name>
49005 <description>Half-duplex selection</description>
49006 <bitOffset>3</bitOffset>
49007 <bitWidth>1</bitWidth>
49008 </field>
49009 <field>
49010 <name>IRLP</name>
49011 <description>Ir low-power</description>
49012 <bitOffset>2</bitOffset>
49013 <bitWidth>1</bitWidth>
49014 </field>
49015 <field>
49016 <name>IREN</name>
49017 <description>Ir mode enable</description>
49018 <bitOffset>1</bitOffset>
49019 <bitWidth>1</bitWidth>
49020 </field>
49021 <field>
49022 <name>EIE</name>
49023 <description>Error interrupt enable</description>
49024 <bitOffset>0</bitOffset>
49025 <bitWidth>1</bitWidth>
49026 </field>
49027 </fields>
49028 </register>
49029 <register>
49030 <name>BRR</name>
49031 <displayName>BRR</displayName>
49032 <description>Baud rate register</description>
49033 <addressOffset>0xC</addressOffset>
49034 <size>0x20</size>
49035 <access>read-write</access>
49036 <resetValue>0x0000</resetValue>
49037 <fields>
49038 <field>
49039 <name>DIV_Mantissa</name>
49040 <description>DIV_Mantissa</description>
49041 <bitOffset>4</bitOffset>
49042 <bitWidth>12</bitWidth>
49043 </field>
49044 <field>
49045 <name>DIV_Fraction</name>
49046 <description>DIV_Fraction</description>
49047 <bitOffset>0</bitOffset>
49048 <bitWidth>4</bitWidth>
49049 </field>
49050 </fields>
49051 </register>
49052 <register>
49053 <name>GTPR</name>
49054 <displayName>GTPR</displayName>
49055 <description>Guard time and prescaler
49056 register</description>
49057 <addressOffset>0x10</addressOffset>
49058 <size>0x20</size>
49059 <access>read-write</access>
49060 <resetValue>0x0000</resetValue>
49061 <fields>
49062 <field>
49063 <name>GT</name>
49064 <description>Guard time value</description>
49065 <bitOffset>8</bitOffset>
49066 <bitWidth>8</bitWidth>
49067 </field>
49068 <field>
49069 <name>PSC</name>
49070 <description>Prescaler value</description>
49071 <bitOffset>0</bitOffset>
49072 <bitWidth>8</bitWidth>
49073 </field>
49074 </fields>
49075 </register>
49076 <register>
49077 <name>RTOR</name>
49078 <displayName>RTOR</displayName>
49079 <description>Receiver timeout register</description>
49080 <addressOffset>0x14</addressOffset>
49081 <size>0x20</size>
49082 <access>read-write</access>
49083 <resetValue>0x0000</resetValue>
49084 <fields>
49085 <field>
49086 <name>BLEN</name>
49087 <description>Block Length</description>
49088 <bitOffset>24</bitOffset>
49089 <bitWidth>8</bitWidth>
49090 </field>
49091 <field>
49092 <name>RTO</name>
49093 <description>Receiver timeout value</description>
49094 <bitOffset>0</bitOffset>
49095 <bitWidth>24</bitWidth>
49096 </field>
49097 </fields>
49098 </register>
49099 <register>
49100 <name>RQR</name>
49101 <displayName>RQR</displayName>
49102 <description>Request register</description>
49103 <addressOffset>0x18</addressOffset>
49104 <size>0x20</size>
49105 <access>write-only</access>
49106 <resetValue>0x0000</resetValue>
49107 <fields>
49108 <field>
49109 <name>TXFRQ</name>
49110 <description>Transmit data flush
49111 request</description>
49112 <bitOffset>4</bitOffset>
49113 <bitWidth>1</bitWidth>
49114 </field>
49115 <field>
49116 <name>RXFRQ</name>
49117 <description>Receive data flush request</description>
49118 <bitOffset>3</bitOffset>
49119 <bitWidth>1</bitWidth>
49120 </field>
49121 <field>
49122 <name>MMRQ</name>
49123 <description>Mute mode request</description>
49124 <bitOffset>2</bitOffset>
49125 <bitWidth>1</bitWidth>
49126 </field>
49127 <field>
49128 <name>SBKRQ</name>
49129 <description>Send break request</description>
49130 <bitOffset>1</bitOffset>
49131 <bitWidth>1</bitWidth>
49132 </field>
49133 <field>
49134 <name>ABRRQ</name>
49135 <description>Auto baud rate request</description>
49136 <bitOffset>0</bitOffset>
49137 <bitWidth>1</bitWidth>
49138 </field>
49139 </fields>
49140 </register>
49141 <register>
49142 <name>ISR</name>
49143 <displayName>ISR</displayName>
49144 <description>Interrupt &amp; status
49145 register</description>
49146 <addressOffset>0x1C</addressOffset>
49147 <size>0x20</size>
49148 <access>read-only</access>
49149 <resetValue>0x00C0</resetValue>
49150 <fields>
49151 <field>
49152 <name>REACK</name>
49153 <description>REACK</description>
49154 <bitOffset>22</bitOffset>
49155 <bitWidth>1</bitWidth>
49156 </field>
49157 <field>
49158 <name>TEACK</name>
49159 <description>TEACK</description>
49160 <bitOffset>21</bitOffset>
49161 <bitWidth>1</bitWidth>
49162 </field>
49163 <field>
49164 <name>WUF</name>
49165 <description>WUF</description>
49166 <bitOffset>20</bitOffset>
49167 <bitWidth>1</bitWidth>
49168 </field>
49169 <field>
49170 <name>RWU</name>
49171 <description>RWU</description>
49172 <bitOffset>19</bitOffset>
49173 <bitWidth>1</bitWidth>
49174 </field>
49175 <field>
49176 <name>SBKF</name>
49177 <description>SBKF</description>
49178 <bitOffset>18</bitOffset>
49179 <bitWidth>1</bitWidth>
49180 </field>
49181 <field>
49182 <name>CMF</name>
49183 <description>CMF</description>
49184 <bitOffset>17</bitOffset>
49185 <bitWidth>1</bitWidth>
49186 </field>
49187 <field>
49188 <name>BUSY</name>
49189 <description>BUSY</description>
49190 <bitOffset>16</bitOffset>
49191 <bitWidth>1</bitWidth>
49192 </field>
49193 <field>
49194 <name>ABRF</name>
49195 <description>ABRF</description>
49196 <bitOffset>15</bitOffset>
49197 <bitWidth>1</bitWidth>
49198 </field>
49199 <field>
49200 <name>ABRE</name>
49201 <description>ABRE</description>
49202 <bitOffset>14</bitOffset>
49203 <bitWidth>1</bitWidth>
49204 </field>
49205 <field>
49206 <name>EOBF</name>
49207 <description>EOBF</description>
49208 <bitOffset>12</bitOffset>
49209 <bitWidth>1</bitWidth>
49210 </field>
49211 <field>
49212 <name>RTOF</name>
49213 <description>RTOF</description>
49214 <bitOffset>11</bitOffset>
49215 <bitWidth>1</bitWidth>
49216 </field>
49217 <field>
49218 <name>CTS</name>
49219 <description>CTS</description>
49220 <bitOffset>10</bitOffset>
49221 <bitWidth>1</bitWidth>
49222 </field>
49223 <field>
49224 <name>CTSIF</name>
49225 <description>CTSIF</description>
49226 <bitOffset>9</bitOffset>
49227 <bitWidth>1</bitWidth>
49228 </field>
49229 <field>
49230 <name>LBDF</name>
49231 <description>LBDF</description>
49232 <bitOffset>8</bitOffset>
49233 <bitWidth>1</bitWidth>
49234 </field>
49235 <field>
49236 <name>TXE</name>
49237 <description>TXE</description>
49238 <bitOffset>7</bitOffset>
49239 <bitWidth>1</bitWidth>
49240 </field>
49241 <field>
49242 <name>TC</name>
49243 <description>TC</description>
49244 <bitOffset>6</bitOffset>
49245 <bitWidth>1</bitWidth>
49246 </field>
49247 <field>
49248 <name>RXNE</name>
49249 <description>RXNE</description>
49250 <bitOffset>5</bitOffset>
49251 <bitWidth>1</bitWidth>
49252 </field>
49253 <field>
49254 <name>IDLE</name>
49255 <description>IDLE</description>
49256 <bitOffset>4</bitOffset>
49257 <bitWidth>1</bitWidth>
49258 </field>
49259 <field>
49260 <name>ORE</name>
49261 <description>ORE</description>
49262 <bitOffset>3</bitOffset>
49263 <bitWidth>1</bitWidth>
49264 </field>
49265 <field>
49266 <name>NF</name>
49267 <description>NF</description>
49268 <bitOffset>2</bitOffset>
49269 <bitWidth>1</bitWidth>
49270 </field>
49271 <field>
49272 <name>FE</name>
49273 <description>FE</description>
49274 <bitOffset>1</bitOffset>
49275 <bitWidth>1</bitWidth>
49276 </field>
49277 <field>
49278 <name>PE</name>
49279 <description>PE</description>
49280 <bitOffset>0</bitOffset>
49281 <bitWidth>1</bitWidth>
49282 </field>
49283 </fields>
49284 </register>
49285 <register>
49286 <name>ICR</name>
49287 <displayName>ICR</displayName>
49288 <description>Interrupt flag clear register</description>
49289 <addressOffset>0x20</addressOffset>
49290 <size>0x20</size>
49291 <access>write-only</access>
49292 <resetValue>0x0000</resetValue>
49293 <fields>
49294 <field>
49295 <name>WUCF</name>
49296 <description>Wakeup from Stop mode clear
49297 flag</description>
49298 <bitOffset>20</bitOffset>
49299 <bitWidth>1</bitWidth>
49300 </field>
49301 <field>
49302 <name>CMCF</name>
49303 <description>Character match clear flag</description>
49304 <bitOffset>17</bitOffset>
49305 <bitWidth>1</bitWidth>
49306 </field>
49307 <field>
49308 <name>EOBCF</name>
49309 <description>End of block clear flag</description>
49310 <bitOffset>12</bitOffset>
49311 <bitWidth>1</bitWidth>
49312 </field>
49313 <field>
49314 <name>RTOCF</name>
49315 <description>Receiver timeout clear
49316 flag</description>
49317 <bitOffset>11</bitOffset>
49318 <bitWidth>1</bitWidth>
49319 </field>
49320 <field>
49321 <name>CTSCF</name>
49322 <description>CTS clear flag</description>
49323 <bitOffset>9</bitOffset>
49324 <bitWidth>1</bitWidth>
49325 </field>
49326 <field>
49327 <name>LBDCF</name>
49328 <description>LIN break detection clear
49329 flag</description>
49330 <bitOffset>8</bitOffset>
49331 <bitWidth>1</bitWidth>
49332 </field>
49333 <field>
49334 <name>TCCF</name>
49335 <description>Transmission complete clear
49336 flag</description>
49337 <bitOffset>6</bitOffset>
49338 <bitWidth>1</bitWidth>
49339 </field>
49340 <field>
49341 <name>IDLECF</name>
49342 <description>Idle line detected clear
49343 flag</description>
49344 <bitOffset>4</bitOffset>
49345 <bitWidth>1</bitWidth>
49346 </field>
49347 <field>
49348 <name>ORECF</name>
49349 <description>Overrun error clear flag</description>
49350 <bitOffset>3</bitOffset>
49351 <bitWidth>1</bitWidth>
49352 </field>
49353 <field>
49354 <name>NCF</name>
49355 <description>Noise detected clear flag</description>
49356 <bitOffset>2</bitOffset>
49357 <bitWidth>1</bitWidth>
49358 </field>
49359 <field>
49360 <name>FECF</name>
49361 <description>Framing error clear flag</description>
49362 <bitOffset>1</bitOffset>
49363 <bitWidth>1</bitWidth>
49364 </field>
49365 <field>
49366 <name>PECF</name>
49367 <description>Parity error clear flag</description>
49368 <bitOffset>0</bitOffset>
49369 <bitWidth>1</bitWidth>
49370 </field>
49371 </fields>
49372 </register>
49373 <register>
49374 <name>RDR</name>
49375 <displayName>RDR</displayName>
49376 <description>Receive data register</description>
49377 <addressOffset>0x24</addressOffset>
49378 <size>0x20</size>
49379 <access>read-only</access>
49380 <resetValue>0x0000</resetValue>
49381 <fields>
49382 <field>
49383 <name>RDR</name>
49384 <description>Receive data value</description>
49385 <bitOffset>0</bitOffset>
49386 <bitWidth>9</bitWidth>
49387 </field>
49388 </fields>
49389 </register>
49390 <register>
49391 <name>TDR</name>
49392 <displayName>TDR</displayName>
49393 <description>Transmit data register</description>
49394 <addressOffset>0x28</addressOffset>
49395 <size>0x20</size>
49396 <access>read-write</access>
49397 <resetValue>0x0000</resetValue>
49398 <fields>
49399 <field>
49400 <name>TDR</name>
49401 <description>Transmit data value</description>
49402 <bitOffset>0</bitOffset>
49403 <bitWidth>9</bitWidth>
49404 </field>
49405 </fields>
49406 </register>
49407 </registers>
49408 </peripheral>
49409 <peripheral derivedFrom="USART6">
49410 <name>USART1</name>
49411 <baseAddress>0x40011000</baseAddress>
49412 <interrupt>
49413 <name>USART1</name>
49414 <description>USART1 global interrupt</description>
49415 <value>37</value>
49416 </interrupt>
49417 </peripheral>
49418 <peripheral derivedFrom="USART6">
49419 <name>USART3</name>
49420 <baseAddress>0x40004800</baseAddress>
49421 <interrupt>
49422 <name>USART3</name>
49423 <description>USART3 global interrupt</description>
49424 <value>39</value>
49425 </interrupt>
49426 </peripheral>
49427 <peripheral derivedFrom="USART6">
49428 <name>USART2</name>
49429 <baseAddress>0x40004400</baseAddress>
49430 <interrupt>
49431 <name>USART2</name>
49432 <description>USART2 global interrupt</description>
49433 <value>38</value>
49434 </interrupt>
49435 </peripheral>
49436 <peripheral derivedFrom="USART6">
49437 <name>UART5</name>
49438 <baseAddress>0x40005000</baseAddress>
49439 <interrupt>
49440 <name>UART5</name>
49441 <description>UART5 global interrupt</description>
49442 <value>53</value>
49443 </interrupt>
49444 </peripheral>
49445 <peripheral derivedFrom="USART6">
49446 <name>UART4</name>
49447 <baseAddress>0x40004C00</baseAddress>
49448 </peripheral>
49449 <peripheral derivedFrom="USART6">
49450 <name>UART8</name>
49451 <baseAddress>0x40007C00</baseAddress>
49452 <interrupt>
49453 <name>UART8</name>
49454 <description>UART 8 global interrupt</description>
49455 <value>83</value>
49456 </interrupt>
49457 </peripheral>
49458 <peripheral derivedFrom="USART6">
49459 <name>UART7</name>
49460 <baseAddress>0x40007800</baseAddress>
49461 </peripheral>
49462 <peripheral>
49463 <name>OTG_FS_GLOBAL</name>
49464 <description>USB on the go full speed</description>
49465 <groupName>USB_OTG_FS</groupName>
49466 <baseAddress>0x50000000</baseAddress>
49467 <addressBlock>
49468 <offset>0x0</offset>
49469 <size>0x400</size>
49470 <usage>registers</usage>
49471 </addressBlock>
49472 <registers>
49473 <register>
49474 <name>OTG_FS_GOTGCTL</name>
49475 <displayName>OTG_FS_GOTGCTL</displayName>
49476 <description>OTG_FS control and status register
49477 (OTG_FS_GOTGCTL)</description>
49478 <addressOffset>0x0</addressOffset>
49479 <size>0x20</size>
49480 <resetValue>0x00000800</resetValue>
49481 <fields>
49482 <field>
49483 <name>SRQSCS</name>
49484 <description>Session request success</description>
49485 <bitOffset>0</bitOffset>
49486 <bitWidth>1</bitWidth>
49487 <access>read-only</access>
49488 </field>
49489 <field>
49490 <name>SRQ</name>
49491 <description>Session request</description>
49492 <bitOffset>1</bitOffset>
49493 <bitWidth>1</bitWidth>
49494 <access>read-write</access>
49495 </field>
49496 <field>
49497 <name>HNGSCS</name>
49498 <description>Host negotiation success</description>
49499 <bitOffset>8</bitOffset>
49500 <bitWidth>1</bitWidth>
49501 <access>read-only</access>
49502 </field>
49503 <field>
49504 <name>HNPRQ</name>
49505 <description>HNP request</description>
49506 <bitOffset>9</bitOffset>
49507 <bitWidth>1</bitWidth>
49508 <access>read-write</access>
49509 </field>
49510 <field>
49511 <name>HSHNPEN</name>
49512 <description>Host set HNP enable</description>
49513 <bitOffset>10</bitOffset>
49514 <bitWidth>1</bitWidth>
49515 <access>read-write</access>
49516 </field>
49517 <field>
49518 <name>DHNPEN</name>
49519 <description>Device HNP enabled</description>
49520 <bitOffset>11</bitOffset>
49521 <bitWidth>1</bitWidth>
49522 <access>read-write</access>
49523 </field>
49524 <field>
49525 <name>CIDSTS</name>
49526 <description>Connector ID status</description>
49527 <bitOffset>16</bitOffset>
49528 <bitWidth>1</bitWidth>
49529 <access>read-only</access>
49530 </field>
49531 <field>
49532 <name>DBCT</name>
49533 <description>Long/short debounce time</description>
49534 <bitOffset>17</bitOffset>
49535 <bitWidth>1</bitWidth>
49536 <access>read-only</access>
49537 </field>
49538 <field>
49539 <name>ASVLD</name>
49540 <description>A-session valid</description>
49541 <bitOffset>18</bitOffset>
49542 <bitWidth>1</bitWidth>
49543 <access>read-only</access>
49544 </field>
49545 <field>
49546 <name>BSVLD</name>
49547 <description>B-session valid</description>
49548 <bitOffset>19</bitOffset>
49549 <bitWidth>1</bitWidth>
49550 <access>read-only</access>
49551 </field>
49552 <field>
49553 <name>VBVALOEN</name>
49554 <description>VBUS valid override enable</description>
49555 <bitOffset>2</bitOffset>
49556 <bitWidth>1</bitWidth>
49557 <access>read-write</access>
49558 </field>
49559 <field>
49560 <name>VBVALOVAL</name>
49561 <description>VBUS valid override value</description>
49562 <bitOffset>3</bitOffset>
49563 <bitWidth>1</bitWidth>
49564 <access>read-write</access>
49565 </field>
49566 <field>
49567 <name>AVALOEN</name>
49568 <description>A-peripheral session valid override
49569 enable</description>
49570 <bitOffset>4</bitOffset>
49571 <bitWidth>1</bitWidth>
49572 <access>read-write</access>
49573 </field>
49574 <field>
49575 <name>AVALOVAL</name>
49576 <description>A-peripheral session valid override
49577 value</description>
49578 <bitOffset>5</bitOffset>
49579 <bitWidth>1</bitWidth>
49580 <access>read-write</access>
49581 </field>
49582 <field>
49583 <name>BVALOEN</name>
49584 <description>B-peripheral session valid override
49585 enable</description>
49586 <bitOffset>6</bitOffset>
49587 <bitWidth>1</bitWidth>
49588 <access>read-write</access>
49589 </field>
49590 <field>
49591 <name>BVALOVAL</name>
49592 <description>B-peripheral session valid override
49593 value</description>
49594 <bitOffset>7</bitOffset>
49595 <bitWidth>1</bitWidth>
49596 <access>read-write</access>
49597 </field>
49598 <field>
49599 <name>EHEN</name>
49600 <description>Embedded host enable</description>
49601 <bitOffset>12</bitOffset>
49602 <bitWidth>1</bitWidth>
49603 <access>read-write</access>
49604 </field>
49605 <field>
49606 <name>OTGVER</name>
49607 <description>OTG version</description>
49608 <bitOffset>20</bitOffset>
49609 <bitWidth>1</bitWidth>
49610 <access>read-write</access>
49611 </field>
49612 </fields>
49613 </register>
49614 <register>
49615 <name>OTG_FS_GOTGINT</name>
49616 <displayName>OTG_FS_GOTGINT</displayName>
49617 <description>OTG_FS interrupt register
49618 (OTG_FS_GOTGINT)</description>
49619 <addressOffset>0x4</addressOffset>
49620 <size>0x20</size>
49621 <access>read-write</access>
49622 <resetValue>0x00000000</resetValue>
49623 <fields>
49624 <field>
49625 <name>SEDET</name>
49626 <description>Session end detected</description>
49627 <bitOffset>2</bitOffset>
49628 <bitWidth>1</bitWidth>
49629 </field>
49630 <field>
49631 <name>SRSSCHG</name>
49632 <description>Session request success status
49633 change</description>
49634 <bitOffset>8</bitOffset>
49635 <bitWidth>1</bitWidth>
49636 </field>
49637 <field>
49638 <name>HNSSCHG</name>
49639 <description>Host negotiation success status
49640 change</description>
49641 <bitOffset>9</bitOffset>
49642 <bitWidth>1</bitWidth>
49643 </field>
49644 <field>
49645 <name>HNGDET</name>
49646 <description>Host negotiation detected</description>
49647 <bitOffset>17</bitOffset>
49648 <bitWidth>1</bitWidth>
49649 </field>
49650 <field>
49651 <name>ADTOCHG</name>
49652 <description>A-device timeout change</description>
49653 <bitOffset>18</bitOffset>
49654 <bitWidth>1</bitWidth>
49655 </field>
49656 <field>
49657 <name>DBCDNE</name>
49658 <description>Debounce done</description>
49659 <bitOffset>19</bitOffset>
49660 <bitWidth>1</bitWidth>
49661 </field>
49662 <field>
49663 <name>IDCHNG</name>
49664 <description>ID input pin changed</description>
49665 <bitOffset>20</bitOffset>
49666 <bitWidth>1</bitWidth>
49667 </field>
49668 </fields>
49669 </register>
49670 <register>
49671 <name>OTG_FS_GAHBCFG</name>
49672 <displayName>OTG_FS_GAHBCFG</displayName>
49673 <description>OTG_FS AHB configuration register
49674 (OTG_FS_GAHBCFG)</description>
49675 <addressOffset>0x8</addressOffset>
49676 <size>0x20</size>
49677 <access>read-write</access>
49678 <resetValue>0x00000000</resetValue>
49679 <fields>
49680 <field>
49681 <name>GINT</name>
49682 <description>Global interrupt mask</description>
49683 <bitOffset>0</bitOffset>
49684 <bitWidth>1</bitWidth>
49685 </field>
49686 <field>
49687 <name>TXFELVL</name>
49688 <description>TxFIFO empty level</description>
49689 <bitOffset>7</bitOffset>
49690 <bitWidth>1</bitWidth>
49691 </field>
49692 <field>
49693 <name>PTXFELVL</name>
49694 <description>Periodic TxFIFO empty
49695 level</description>
49696 <bitOffset>8</bitOffset>
49697 <bitWidth>1</bitWidth>
49698 </field>
49699 </fields>
49700 </register>
49701 <register>
49702 <name>OTG_FS_GUSBCFG</name>
49703 <displayName>OTG_FS_GUSBCFG</displayName>
49704 <description>OTG_FS USB configuration register
49705 (OTG_FS_GUSBCFG)</description>
49706 <addressOffset>0xC</addressOffset>
49707 <size>0x20</size>
49708 <resetValue>0x00000A00</resetValue>
49709 <fields>
49710 <field>
49711 <name>TOCAL</name>
49712 <description>FS timeout calibration</description>
49713 <bitOffset>0</bitOffset>
49714 <bitWidth>3</bitWidth>
49715 <access>read-write</access>
49716 </field>
49717 <field>
49718 <name>PHYSEL</name>
49719 <description>Full Speed serial transceiver
49720 select</description>
49721 <bitOffset>6</bitOffset>
49722 <bitWidth>1</bitWidth>
49723 <access>write-only</access>
49724 </field>
49725 <field>
49726 <name>SRPCAP</name>
49727 <description>SRP-capable</description>
49728 <bitOffset>8</bitOffset>
49729 <bitWidth>1</bitWidth>
49730 <access>read-write</access>
49731 </field>
49732 <field>
49733 <name>HNPCAP</name>
49734 <description>HNP-capable</description>
49735 <bitOffset>9</bitOffset>
49736 <bitWidth>1</bitWidth>
49737 <access>read-write</access>
49738 </field>
49739 <field>
49740 <name>TRDT</name>
49741 <description>USB turnaround time</description>
49742 <bitOffset>10</bitOffset>
49743 <bitWidth>4</bitWidth>
49744 <access>read-write</access>
49745 </field>
49746 <field>
49747 <name>FHMOD</name>
49748 <description>Force host mode</description>
49749 <bitOffset>29</bitOffset>
49750 <bitWidth>1</bitWidth>
49751 <access>read-write</access>
49752 </field>
49753 <field>
49754 <name>FDMOD</name>
49755 <description>Force device mode</description>
49756 <bitOffset>30</bitOffset>
49757 <bitWidth>1</bitWidth>
49758 <access>read-write</access>
49759 </field>
49760 </fields>
49761 </register>
49762 <register>
49763 <name>OTG_FS_GRSTCTL</name>
49764 <displayName>OTG_FS_GRSTCTL</displayName>
49765 <description>OTG_FS reset register
49766 (OTG_FS_GRSTCTL)</description>
49767 <addressOffset>0x10</addressOffset>
49768 <size>0x20</size>
49769 <resetValue>0x20000000</resetValue>
49770 <fields>
49771 <field>
49772 <name>CSRST</name>
49773 <description>Core soft reset</description>
49774 <bitOffset>0</bitOffset>
49775 <bitWidth>1</bitWidth>
49776 <access>read-write</access>
49777 </field>
49778 <field>
49779 <name>HSRST</name>
49780 <description>HCLK soft reset</description>
49781 <bitOffset>1</bitOffset>
49782 <bitWidth>1</bitWidth>
49783 <access>read-write</access>
49784 </field>
49785 <field>
49786 <name>FCRST</name>
49787 <description>Host frame counter reset</description>
49788 <bitOffset>2</bitOffset>
49789 <bitWidth>1</bitWidth>
49790 <access>read-write</access>
49791 </field>
49792 <field>
49793 <name>RXFFLSH</name>
49794 <description>RxFIFO flush</description>
49795 <bitOffset>4</bitOffset>
49796 <bitWidth>1</bitWidth>
49797 <access>read-write</access>
49798 </field>
49799 <field>
49800 <name>TXFFLSH</name>
49801 <description>TxFIFO flush</description>
49802 <bitOffset>5</bitOffset>
49803 <bitWidth>1</bitWidth>
49804 <access>read-write</access>
49805 </field>
49806 <field>
49807 <name>TXFNUM</name>
49808 <description>TxFIFO number</description>
49809 <bitOffset>6</bitOffset>
49810 <bitWidth>5</bitWidth>
49811 <access>read-write</access>
49812 </field>
49813 <field>
49814 <name>AHBIDL</name>
49815 <description>AHB master idle</description>
49816 <bitOffset>31</bitOffset>
49817 <bitWidth>1</bitWidth>
49818 <access>read-only</access>
49819 </field>
49820 </fields>
49821 </register>
49822 <register>
49823 <name>OTG_FS_GINTSTS</name>
49824 <displayName>OTG_FS_GINTSTS</displayName>
49825 <description>OTG_FS core interrupt register
49826 (OTG_FS_GINTSTS)</description>
49827 <addressOffset>0x14</addressOffset>
49828 <size>0x20</size>
49829 <resetValue>0x04000020</resetValue>
49830 <fields>
49831 <field>
49832 <name>CMOD</name>
49833 <description>Current mode of operation</description>
49834 <bitOffset>0</bitOffset>
49835 <bitWidth>1</bitWidth>
49836 <access>read-only</access>
49837 </field>
49838 <field>
49839 <name>MMIS</name>
49840 <description>Mode mismatch interrupt</description>
49841 <bitOffset>1</bitOffset>
49842 <bitWidth>1</bitWidth>
49843 <access>read-write</access>
49844 </field>
49845 <field>
49846 <name>OTGINT</name>
49847 <description>OTG interrupt</description>
49848 <bitOffset>2</bitOffset>
49849 <bitWidth>1</bitWidth>
49850 <access>read-only</access>
49851 </field>
49852 <field>
49853 <name>SOF</name>
49854 <description>Start of frame</description>
49855 <bitOffset>3</bitOffset>
49856 <bitWidth>1</bitWidth>
49857 <access>read-write</access>
49858 </field>
49859 <field>
49860 <name>RXFLVL</name>
49861 <description>RxFIFO non-empty</description>
49862 <bitOffset>4</bitOffset>
49863 <bitWidth>1</bitWidth>
49864 <access>read-only</access>
49865 </field>
49866 <field>
49867 <name>NPTXFE</name>
49868 <description>Non-periodic TxFIFO empty</description>
49869 <bitOffset>5</bitOffset>
49870 <bitWidth>1</bitWidth>
49871 <access>read-only</access>
49872 </field>
49873 <field>
49874 <name>GINAKEFF</name>
49875 <description>Global IN non-periodic NAK
49876 effective</description>
49877 <bitOffset>6</bitOffset>
49878 <bitWidth>1</bitWidth>
49879 <access>read-only</access>
49880 </field>
49881 <field>
49882 <name>GOUTNAKEFF</name>
49883 <description>Global OUT NAK effective</description>
49884 <bitOffset>7</bitOffset>
49885 <bitWidth>1</bitWidth>
49886 <access>read-only</access>
49887 </field>
49888 <field>
49889 <name>ESUSP</name>
49890 <description>Early suspend</description>
49891 <bitOffset>10</bitOffset>
49892 <bitWidth>1</bitWidth>
49893 <access>read-write</access>
49894 </field>
49895 <field>
49896 <name>USBSUSP</name>
49897 <description>USB suspend</description>
49898 <bitOffset>11</bitOffset>
49899 <bitWidth>1</bitWidth>
49900 <access>read-write</access>
49901 </field>
49902 <field>
49903 <name>USBRST</name>
49904 <description>USB reset</description>
49905 <bitOffset>12</bitOffset>
49906 <bitWidth>1</bitWidth>
49907 <access>read-write</access>
49908 </field>
49909 <field>
49910 <name>ENUMDNE</name>
49911 <description>Enumeration done</description>
49912 <bitOffset>13</bitOffset>
49913 <bitWidth>1</bitWidth>
49914 <access>read-write</access>
49915 </field>
49916 <field>
49917 <name>ISOODRP</name>
49918 <description>Isochronous OUT packet dropped
49919 interrupt</description>
49920 <bitOffset>14</bitOffset>
49921 <bitWidth>1</bitWidth>
49922 <access>read-write</access>
49923 </field>
49924 <field>
49925 <name>EOPF</name>
49926 <description>End of periodic frame
49927 interrupt</description>
49928 <bitOffset>15</bitOffset>
49929 <bitWidth>1</bitWidth>
49930 <access>read-write</access>
49931 </field>
49932 <field>
49933 <name>IEPINT</name>
49934 <description>IN endpoint interrupt</description>
49935 <bitOffset>18</bitOffset>
49936 <bitWidth>1</bitWidth>
49937 <access>read-only</access>
49938 </field>
49939 <field>
49940 <name>OEPINT</name>
49941 <description>OUT endpoint interrupt</description>
49942 <bitOffset>19</bitOffset>
49943 <bitWidth>1</bitWidth>
49944 <access>read-only</access>
49945 </field>
49946 <field>
49947 <name>IISOIXFR</name>
49948 <description>Incomplete isochronous IN
49949 transfer</description>
49950 <bitOffset>20</bitOffset>
49951 <bitWidth>1</bitWidth>
49952 <access>read-write</access>
49953 </field>
49954 <field>
49955 <name>IPXFR_INCOMPISOOUT</name>
49956 <description>Incomplete periodic transfer(Host
49957 mode)/Incomplete isochronous OUT transfer(Device
49958 mode)</description>
49959 <bitOffset>21</bitOffset>
49960 <bitWidth>1</bitWidth>
49961 <access>read-write</access>
49962 </field>
49963 <field>
49964 <name>HPRTINT</name>
49965 <description>Host port interrupt</description>
49966 <bitOffset>24</bitOffset>
49967 <bitWidth>1</bitWidth>
49968 <access>read-only</access>
49969 </field>
49970 <field>
49971 <name>HCINT</name>
49972 <description>Host channels interrupt</description>
49973 <bitOffset>25</bitOffset>
49974 <bitWidth>1</bitWidth>
49975 <access>read-only</access>
49976 </field>
49977 <field>
49978 <name>PTXFE</name>
49979 <description>Periodic TxFIFO empty</description>
49980 <bitOffset>26</bitOffset>
49981 <bitWidth>1</bitWidth>
49982 <access>read-only</access>
49983 </field>
49984 <field>
49985 <name>CIDSCHG</name>
49986 <description>Connector ID status change</description>
49987 <bitOffset>28</bitOffset>
49988 <bitWidth>1</bitWidth>
49989 <access>read-write</access>
49990 </field>
49991 <field>
49992 <name>DISCINT</name>
49993 <description>Disconnect detected
49994 interrupt</description>
49995 <bitOffset>29</bitOffset>
49996 <bitWidth>1</bitWidth>
49997 <access>read-write</access>
49998 </field>
49999 <field>
50000 <name>SRQINT</name>
50001 <description>Session request/new session detected
50002 interrupt</description>
50003 <bitOffset>30</bitOffset>
50004 <bitWidth>1</bitWidth>
50005 <access>read-write</access>
50006 </field>
50007 <field>
50008 <name>WKUPINT</name>
50009 <description>Resume/remote wakeup detected
50010 interrupt</description>
50011 <bitOffset>31</bitOffset>
50012 <bitWidth>1</bitWidth>
50013 <access>read-write</access>
50014 </field>
50015 <field>
50016 <name>RSTDET</name>
50017 <description>Reset detected interrupt</description>
50018 <bitOffset>23</bitOffset>
50019 <bitWidth>1</bitWidth>
50020 <access>read-write</access>
50021 </field>
50022 </fields>
50023 </register>
50024 <register>
50025 <name>OTG_FS_GINTMSK</name>
50026 <displayName>OTG_FS_GINTMSK</displayName>
50027 <description>OTG_FS interrupt mask register
50028 (OTG_FS_GINTMSK)</description>
50029 <addressOffset>0x18</addressOffset>
50030 <size>0x20</size>
50031 <resetValue>0x00000000</resetValue>
50032 <fields>
50033 <field>
50034 <name>MMISM</name>
50035 <description>Mode mismatch interrupt
50036 mask</description>
50037 <bitOffset>1</bitOffset>
50038 <bitWidth>1</bitWidth>
50039 <access>read-write</access>
50040 </field>
50041 <field>
50042 <name>OTGINT</name>
50043 <description>OTG interrupt mask</description>
50044 <bitOffset>2</bitOffset>
50045 <bitWidth>1</bitWidth>
50046 <access>read-write</access>
50047 </field>
50048 <field>
50049 <name>SOFM</name>
50050 <description>Start of frame mask</description>
50051 <bitOffset>3</bitOffset>
50052 <bitWidth>1</bitWidth>
50053 <access>read-write</access>
50054 </field>
50055 <field>
50056 <name>RXFLVLM</name>
50057 <description>Receive FIFO non-empty
50058 mask</description>
50059 <bitOffset>4</bitOffset>
50060 <bitWidth>1</bitWidth>
50061 <access>read-write</access>
50062 </field>
50063 <field>
50064 <name>NPTXFEM</name>
50065 <description>Non-periodic TxFIFO empty
50066 mask</description>
50067 <bitOffset>5</bitOffset>
50068 <bitWidth>1</bitWidth>
50069 <access>read-write</access>
50070 </field>
50071 <field>
50072 <name>GINAKEFFM</name>
50073 <description>Global non-periodic IN NAK effective
50074 mask</description>
50075 <bitOffset>6</bitOffset>
50076 <bitWidth>1</bitWidth>
50077 <access>read-write</access>
50078 </field>
50079 <field>
50080 <name>GONAKEFFM</name>
50081 <description>Global OUT NAK effective
50082 mask</description>
50083 <bitOffset>7</bitOffset>
50084 <bitWidth>1</bitWidth>
50085 <access>read-write</access>
50086 </field>
50087 <field>
50088 <name>ESUSPM</name>
50089 <description>Early suspend mask</description>
50090 <bitOffset>10</bitOffset>
50091 <bitWidth>1</bitWidth>
50092 <access>read-write</access>
50093 </field>
50094 <field>
50095 <name>USBSUSPM</name>
50096 <description>USB suspend mask</description>
50097 <bitOffset>11</bitOffset>
50098 <bitWidth>1</bitWidth>
50099 <access>read-write</access>
50100 </field>
50101 <field>
50102 <name>USBRST</name>
50103 <description>USB reset mask</description>
50104 <bitOffset>12</bitOffset>
50105 <bitWidth>1</bitWidth>
50106 <access>read-write</access>
50107 </field>
50108 <field>
50109 <name>ENUMDNEM</name>
50110 <description>Enumeration done mask</description>
50111 <bitOffset>13</bitOffset>
50112 <bitWidth>1</bitWidth>
50113 <access>read-write</access>
50114 </field>
50115 <field>
50116 <name>ISOODRPM</name>
50117 <description>Isochronous OUT packet dropped interrupt
50118 mask</description>
50119 <bitOffset>14</bitOffset>
50120 <bitWidth>1</bitWidth>
50121 <access>read-write</access>
50122 </field>
50123 <field>
50124 <name>EOPFM</name>
50125 <description>End of periodic frame interrupt
50126 mask</description>
50127 <bitOffset>15</bitOffset>
50128 <bitWidth>1</bitWidth>
50129 <access>read-write</access>
50130 </field>
50131 <field>
50132 <name>IEPINT</name>
50133 <description>IN endpoints interrupt
50134 mask</description>
50135 <bitOffset>18</bitOffset>
50136 <bitWidth>1</bitWidth>
50137 <access>read-write</access>
50138 </field>
50139 <field>
50140 <name>OEPINT</name>
50141 <description>OUT endpoints interrupt
50142 mask</description>
50143 <bitOffset>19</bitOffset>
50144 <bitWidth>1</bitWidth>
50145 <access>read-write</access>
50146 </field>
50147 <field>
50148 <name>IISOIXFRM</name>
50149 <description>Incomplete isochronous IN transfer
50150 mask</description>
50151 <bitOffset>20</bitOffset>
50152 <bitWidth>1</bitWidth>
50153 <access>read-write</access>
50154 </field>
50155 <field>
50156 <name>IPXFRM_IISOOXFRM</name>
50157 <description>Incomplete periodic transfer mask(Host
50158 mode)/Incomplete isochronous OUT transfer mask(Device
50159 mode)</description>
50160 <bitOffset>21</bitOffset>
50161 <bitWidth>1</bitWidth>
50162 <access>read-write</access>
50163 </field>
50164 <field>
50165 <name>PRTIM</name>
50166 <description>Host port interrupt mask</description>
50167 <bitOffset>24</bitOffset>
50168 <bitWidth>1</bitWidth>
50169 <access>read-only</access>
50170 </field>
50171 <field>
50172 <name>HCIM</name>
50173 <description>Host channels interrupt
50174 mask</description>
50175 <bitOffset>25</bitOffset>
50176 <bitWidth>1</bitWidth>
50177 <access>read-write</access>
50178 </field>
50179 <field>
50180 <name>PTXFEM</name>
50181 <description>Periodic TxFIFO empty mask</description>
50182 <bitOffset>26</bitOffset>
50183 <bitWidth>1</bitWidth>
50184 <access>read-write</access>
50185 </field>
50186 <field>
50187 <name>CIDSCHGM</name>
50188 <description>Connector ID status change
50189 mask</description>
50190 <bitOffset>28</bitOffset>
50191 <bitWidth>1</bitWidth>
50192 <access>read-write</access>
50193 </field>
50194 <field>
50195 <name>DISCINT</name>
50196 <description>Disconnect detected interrupt
50197 mask</description>
50198 <bitOffset>29</bitOffset>
50199 <bitWidth>1</bitWidth>
50200 <access>read-write</access>
50201 </field>
50202 <field>
50203 <name>SRQIM</name>
50204 <description>Session request/new session detected
50205 interrupt mask</description>
50206 <bitOffset>30</bitOffset>
50207 <bitWidth>1</bitWidth>
50208 <access>read-write</access>
50209 </field>
50210 <field>
50211 <name>WUIM</name>
50212 <description>Resume/remote wakeup detected interrupt
50213 mask</description>
50214 <bitOffset>31</bitOffset>
50215 <bitWidth>1</bitWidth>
50216 <access>read-write</access>
50217 </field>
50218 <field>
50219 <name>RSTDETM</name>
50220 <description>Reset detected interrupt
50221 mask</description>
50222 <bitOffset>23</bitOffset>
50223 <bitWidth>1</bitWidth>
50224 <access>read-write</access>
50225 </field>
50226 <field>
50227 <name>LPMIN</name>
50228 <description>LPM interrupt mask</description>
50229 <bitOffset>27</bitOffset>
50230 <bitWidth>1</bitWidth>
50231 <access>read-write</access>
50232 </field>
50233 </fields>
50234 </register>
50235 <register>
50236 <name>OTG_FS_GRXSTSR_Device</name>
50237 <displayName>OTG_FS_GRXSTSR_Device</displayName>
50238 <description>OTG_FS Receive status debug read(Device
50239 mode)</description>
50240 <addressOffset>0x1C</addressOffset>
50241 <size>0x20</size>
50242 <access>read-only</access>
50243 <resetValue>0x00000000</resetValue>
50244 <fields>
50245 <field>
50246 <name>EPNUM</name>
50247 <description>Endpoint number</description>
50248 <bitOffset>0</bitOffset>
50249 <bitWidth>4</bitWidth>
50250 </field>
50251 <field>
50252 <name>BCNT</name>
50253 <description>Byte count</description>
50254 <bitOffset>4</bitOffset>
50255 <bitWidth>11</bitWidth>
50256 </field>
50257 <field>
50258 <name>DPID</name>
50259 <description>Data PID</description>
50260 <bitOffset>15</bitOffset>
50261 <bitWidth>2</bitWidth>
50262 </field>
50263 <field>
50264 <name>PKTSTS</name>
50265 <description>Packet status</description>
50266 <bitOffset>17</bitOffset>
50267 <bitWidth>4</bitWidth>
50268 </field>
50269 <field>
50270 <name>FRMNUM</name>
50271 <description>Frame number</description>
50272 <bitOffset>21</bitOffset>
50273 <bitWidth>4</bitWidth>
50274 </field>
50275 </fields>
50276 </register>
50277 <register>
50278 <name>OTG_FS_GRXSTSR_Host</name>
50279 <displayName>OTG_FS_GRXSTSR_Host</displayName>
50280 <description>OTG_FS Receive status debug read(Host
50281 mode)</description>
50282 <alternateRegister>OTG_FS_GRXSTSR_Device</alternateRegister>
50283 <addressOffset>0x1C</addressOffset>
50284 <size>0x20</size>
50285 <access>read-only</access>
50286 <resetValue>0x00000000</resetValue>
50287 <fields>
50288 <field>
50289 <name>CHNUM</name>
50290 <description>Endpoint number</description>
50291 <bitOffset>0</bitOffset>
50292 <bitWidth>4</bitWidth>
50293 </field>
50294 <field>
50295 <name>BCNT</name>
50296 <description>Byte count</description>
50297 <bitOffset>4</bitOffset>
50298 <bitWidth>11</bitWidth>
50299 </field>
50300 <field>
50301 <name>DPID</name>
50302 <description>Data PID</description>
50303 <bitOffset>15</bitOffset>
50304 <bitWidth>2</bitWidth>
50305 </field>
50306 <field>
50307 <name>PKTSTS</name>
50308 <description>Packet status</description>
50309 <bitOffset>17</bitOffset>
50310 <bitWidth>4</bitWidth>
50311 </field>
50312 </fields>
50313 </register>
50314 <register>
50315 <name>OTG_FS_GRXFSIZ</name>
50316 <displayName>OTG_FS_GRXFSIZ</displayName>
50317 <description>OTG_FS Receive FIFO size register
50318 (OTG_FS_GRXFSIZ)</description>
50319 <addressOffset>0x24</addressOffset>
50320 <size>0x20</size>
50321 <access>read-write</access>
50322 <resetValue>0x00000200</resetValue>
50323 <fields>
50324 <field>
50325 <name>RXFD</name>
50326 <description>RxFIFO depth</description>
50327 <bitOffset>0</bitOffset>
50328 <bitWidth>16</bitWidth>
50329 </field>
50330 </fields>
50331 </register>
50332 <register>
50333 <name>OTG_FS_DIEPTXF0_Device</name>
50334 <displayName>OTG_FS_DIEPTXF0_Device</displayName>
50335 <description>OTG_FS Endpoint 0 Transmit FIFO
50336 size</description>
50337 <addressOffset>0x28</addressOffset>
50338 <size>0x20</size>
50339 <access>read-write</access>
50340 <resetValue>0x00000200</resetValue>
50341 <fields>
50342 <field>
50343 <name>TX0FSA</name>
50344 <description>Endpoint 0 transmit RAM start
50345 address</description>
50346 <bitOffset>0</bitOffset>
50347 <bitWidth>16</bitWidth>
50348 </field>
50349 <field>
50350 <name>TX0FD</name>
50351 <description>Endpoint 0 TxFIFO depth</description>
50352 <bitOffset>16</bitOffset>
50353 <bitWidth>16</bitWidth>
50354 </field>
50355 </fields>
50356 </register>
50357 <register>
50358 <name>OTG_FS_HNPTXFSIZ_Host</name>
50359 <displayName>OTG_FS_HNPTXFSIZ_Host</displayName>
50360 <description>OTG_FS Host non-periodic transmit FIFO size
50361 register</description>
50362 <alternateRegister>OTG_FS_DIEPTXF0_Device</alternateRegister>
50363 <addressOffset>0x28</addressOffset>
50364 <size>0x20</size>
50365 <access>read-write</access>
50366 <resetValue>0x00000200</resetValue>
50367 <fields>
50368 <field>
50369 <name>NPTXFSA</name>
50370 <description>Non-periodic transmit RAM start
50371 address</description>
50372 <bitOffset>0</bitOffset>
50373 <bitWidth>16</bitWidth>
50374 </field>
50375 <field>
50376 <name>NPTXFD</name>
50377 <description>Non-periodic TxFIFO depth</description>
50378 <bitOffset>16</bitOffset>
50379 <bitWidth>16</bitWidth>
50380 </field>
50381 </fields>
50382 </register>
50383 <register>
50384 <name>OTG_FS_HNPTXSTS</name>
50385 <displayName>OTG_FS_HNPTXSTS</displayName>
50386 <description>OTG_FS non-periodic transmit FIFO/queue
50387 status register (OTG_FS_GNPTXSTS)</description>
50388 <addressOffset>0x2C</addressOffset>
50389 <size>0x20</size>
50390 <access>read-only</access>
50391 <resetValue>0x00080200</resetValue>
50392 <fields>
50393 <field>
50394 <name>NPTXFSAV</name>
50395 <description>Non-periodic TxFIFO space
50396 available</description>
50397 <bitOffset>0</bitOffset>
50398 <bitWidth>16</bitWidth>
50399 </field>
50400 <field>
50401 <name>NPTQXSAV</name>
50402 <description>Non-periodic transmit request queue
50403 space available</description>
50404 <bitOffset>16</bitOffset>
50405 <bitWidth>8</bitWidth>
50406 </field>
50407 <field>
50408 <name>NPTXQTOP</name>
50409 <description>Top of the non-periodic transmit request
50410 queue</description>
50411 <bitOffset>24</bitOffset>
50412 <bitWidth>7</bitWidth>
50413 </field>
50414 </fields>
50415 </register>
50416 <register>
50417 <name>OTG_FS_GCCFG</name>
50418 <displayName>OTG_FS_GCCFG</displayName>
50419 <description>OTG_FS general core configuration register
50420 (OTG_FS_GCCFG)</description>
50421 <addressOffset>0x38</addressOffset>
50422 <size>0x20</size>
50423 <access>read-write</access>
50424 <resetValue>0x00000000</resetValue>
50425 <fields>
50426 <field>
50427 <name>PWRDWN</name>
50428 <description>Power down</description>
50429 <bitOffset>16</bitOffset>
50430 <bitWidth>1</bitWidth>
50431 </field>
50432 <field>
50433 <name>BCDEN</name>
50434 <description>Battery charging detector (BCD)
50435 enable</description>
50436 <bitOffset>17</bitOffset>
50437 <bitWidth>1</bitWidth>
50438 </field>
50439 <field>
50440 <name>DCDEN</name>
50441 <description>Data contact detection (DCD) mode
50442 enable</description>
50443 <bitOffset>18</bitOffset>
50444 <bitWidth>1</bitWidth>
50445 </field>
50446 <field>
50447 <name>PDEN</name>
50448 <description>Primary detection (PD) mode
50449 enable</description>
50450 <bitOffset>19</bitOffset>
50451 <bitWidth>1</bitWidth>
50452 </field>
50453 <field>
50454 <name>SDEN</name>
50455 <description>Secondary detection (SD) mode
50456 enable</description>
50457 <bitOffset>20</bitOffset>
50458 <bitWidth>1</bitWidth>
50459 </field>
50460 <field>
50461 <name>VBDEN</name>
50462 <description>USB VBUS detection enable</description>
50463 <bitOffset>21</bitOffset>
50464 <bitWidth>1</bitWidth>
50465 </field>
50466 <field>
50467 <name>DCDET</name>
50468 <description>Data contact detection (DCD)
50469 status</description>
50470 <bitOffset>0</bitOffset>
50471 <bitWidth>1</bitWidth>
50472 </field>
50473 <field>
50474 <name>PDET</name>
50475 <description>Primary detection (PD)
50476 status</description>
50477 <bitOffset>1</bitOffset>
50478 <bitWidth>1</bitWidth>
50479 </field>
50480 <field>
50481 <name>SDET</name>
50482 <description>Secondary detection (SD)
50483 status</description>
50484 <bitOffset>2</bitOffset>
50485 <bitWidth>1</bitWidth>
50486 </field>
50487 <field>
50488 <name>PS2DET</name>
50489 <description>DM pull-up detection
50490 status</description>
50491 <bitOffset>3</bitOffset>
50492 <bitWidth>1</bitWidth>
50493 </field>
50494 </fields>
50495 </register>
50496 <register>
50497 <name>OTG_FS_CID</name>
50498 <displayName>OTG_FS_CID</displayName>
50499 <description>core ID register</description>
50500 <addressOffset>0x3C</addressOffset>
50501 <size>0x20</size>
50502 <access>read-write</access>
50503 <resetValue>0x00001000</resetValue>
50504 <fields>
50505 <field>
50506 <name>PRODUCT_ID</name>
50507 <description>Product ID field</description>
50508 <bitOffset>0</bitOffset>
50509 <bitWidth>32</bitWidth>
50510 </field>
50511 </fields>
50512 </register>
50513 <register>
50514 <name>OTG_FS_HPTXFSIZ</name>
50515 <displayName>OTG_FS_HPTXFSIZ</displayName>
50516 <description>OTG_FS Host periodic transmit FIFO size
50517 register (OTG_FS_HPTXFSIZ)</description>
50518 <addressOffset>0x100</addressOffset>
50519 <size>0x20</size>
50520 <access>read-write</access>
50521 <resetValue>0x02000600</resetValue>
50522 <fields>
50523 <field>
50524 <name>PTXSA</name>
50525 <description>Host periodic TxFIFO start
50526 address</description>
50527 <bitOffset>0</bitOffset>
50528 <bitWidth>16</bitWidth>
50529 </field>
50530 <field>
50531 <name>PTXFSIZ</name>
50532 <description>Host periodic TxFIFO depth</description>
50533 <bitOffset>16</bitOffset>
50534 <bitWidth>16</bitWidth>
50535 </field>
50536 </fields>
50537 </register>
50538 <register>
50539 <name>OTG_FS_DIEPTXF1</name>
50540 <displayName>OTG_FS_DIEPTXF1</displayName>
50541 <description>OTG_FS device IN endpoint transmit FIFO size
50542 register (OTG_FS_DIEPTXF1)</description>
50543 <addressOffset>0x104</addressOffset>
50544 <size>0x20</size>
50545 <access>read-write</access>
50546 <resetValue>0x02000400</resetValue>
50547 <fields>
50548 <field>
50549 <name>INEPTXSA</name>
50550 <description>IN endpoint FIFO2 transmit RAM start
50551 address</description>
50552 <bitOffset>0</bitOffset>
50553 <bitWidth>16</bitWidth>
50554 </field>
50555 <field>
50556 <name>INEPTXFD</name>
50557 <description>IN endpoint TxFIFO depth</description>
50558 <bitOffset>16</bitOffset>
50559 <bitWidth>16</bitWidth>
50560 </field>
50561 </fields>
50562 </register>
50563 <register>
50564 <name>OTG_FS_DIEPTXF2</name>
50565 <displayName>OTG_FS_DIEPTXF2</displayName>
50566 <description>OTG_FS device IN endpoint transmit FIFO size
50567 register (OTG_FS_DIEPTXF2)</description>
50568 <addressOffset>0x108</addressOffset>
50569 <size>0x20</size>
50570 <access>read-write</access>
50571 <resetValue>0x02000400</resetValue>
50572 <fields>
50573 <field>
50574 <name>INEPTXSA</name>
50575 <description>IN endpoint FIFO3 transmit RAM start
50576 address</description>
50577 <bitOffset>0</bitOffset>
50578 <bitWidth>16</bitWidth>
50579 </field>
50580 <field>
50581 <name>INEPTXFD</name>
50582 <description>IN endpoint TxFIFO depth</description>
50583 <bitOffset>16</bitOffset>
50584 <bitWidth>16</bitWidth>
50585 </field>
50586 </fields>
50587 </register>
50588 <register>
50589 <name>OTG_FS_DIEPTXF3</name>
50590 <displayName>OTG_FS_DIEPTXF3</displayName>
50591 <description>OTG_FS device IN endpoint transmit FIFO size
50592 register (OTG_FS_DIEPTXF3)</description>
50593 <addressOffset>0x10C</addressOffset>
50594 <size>0x20</size>
50595 <access>read-write</access>
50596 <resetValue>0x02000400</resetValue>
50597 <fields>
50598 <field>
50599 <name>INEPTXSA</name>
50600 <description>IN endpoint FIFO4 transmit RAM start
50601 address</description>
50602 <bitOffset>0</bitOffset>
50603 <bitWidth>16</bitWidth>
50604 </field>
50605 <field>
50606 <name>INEPTXFD</name>
50607 <description>IN endpoint TxFIFO depth</description>
50608 <bitOffset>16</bitOffset>
50609 <bitWidth>16</bitWidth>
50610 </field>
50611 </fields>
50612 </register>
50613 <register>
50614 <name>OTG_FS_GRXSTSP_Device</name>
50615 <displayName>OTG_FS_GRXSTSP_Device</displayName>
50616 <description>OTG status read and pop register (Device
50617 mode)</description>
50618 <addressOffset>0x20</addressOffset>
50619 <size>0x20</size>
50620 <access>read-only</access>
50621 <resetValue>0x02000400</resetValue>
50622 <fields>
50623 <field>
50624 <name>EPNUM</name>
50625 <description>Endpoint number</description>
50626 <bitOffset>0</bitOffset>
50627 <bitWidth>4</bitWidth>
50628 </field>
50629 <field>
50630 <name>BCNT</name>
50631 <description>Byte count</description>
50632 <bitOffset>4</bitOffset>
50633 <bitWidth>11</bitWidth>
50634 </field>
50635 <field>
50636 <name>DPID</name>
50637 <description>Data PID</description>
50638 <bitOffset>15</bitOffset>
50639 <bitWidth>2</bitWidth>
50640 </field>
50641 <field>
50642 <name>PKTSTS</name>
50643 <description>Packet status</description>
50644 <bitOffset>17</bitOffset>
50645 <bitWidth>4</bitWidth>
50646 </field>
50647 <field>
50648 <name>FRMNUM</name>
50649 <description>Frame number</description>
50650 <bitOffset>21</bitOffset>
50651 <bitWidth>4</bitWidth>
50652 </field>
50653 </fields>
50654 </register>
50655 <register>
50656 <name>OTG_FS_GRXSTSP_Host</name>
50657 <displayName>OTG_FS_GRXSTSP_Host</displayName>
50658 <description>OTG status read and pop register (Host
50659 mode)</description>
50660 <alternateRegister>OTG_FS_GRXSTSP_Device</alternateRegister>
50661 <addressOffset>0x20</addressOffset>
50662 <size>0x20</size>
50663 <access>read-only</access>
50664 <resetValue>0x02000400</resetValue>
50665 <fields>
50666 <field>
50667 <name>CHNUM</name>
50668 <description>Channel number</description>
50669 <bitOffset>0</bitOffset>
50670 <bitWidth>4</bitWidth>
50671 </field>
50672 <field>
50673 <name>BCNT</name>
50674 <description>Byte count</description>
50675 <bitOffset>4</bitOffset>
50676 <bitWidth>11</bitWidth>
50677 </field>
50678 <field>
50679 <name>DPID</name>
50680 <description>Data PID</description>
50681 <bitOffset>15</bitOffset>
50682 <bitWidth>2</bitWidth>
50683 </field>
50684 <field>
50685 <name>PKTSTS</name>
50686 <description>Packet status</description>
50687 <bitOffset>17</bitOffset>
50688 <bitWidth>4</bitWidth>
50689 </field>
50690 </fields>
50691 </register>
50692 <register>
50693 <name>OTG_FS_GI2CCTL</name>
50694 <displayName>OTG_FS_GI2CCTL</displayName>
50695 <description>OTG I2C access register</description>
50696 <addressOffset>0x30</addressOffset>
50697 <size>0x20</size>
50698 <access>read-write</access>
50699 <resetValue>0x02000400</resetValue>
50700 <fields>
50701 <field>
50702 <name>RWDATA</name>
50703 <description>I2C Read/Write Data</description>
50704 <bitOffset>0</bitOffset>
50705 <bitWidth>8</bitWidth>
50706 </field>
50707 <field>
50708 <name>REGADDR</name>
50709 <description>I2C Register Address</description>
50710 <bitOffset>8</bitOffset>
50711 <bitWidth>8</bitWidth>
50712 </field>
50713 <field>
50714 <name>ADDR</name>
50715 <description>I2C Address</description>
50716 <bitOffset>16</bitOffset>
50717 <bitWidth>7</bitWidth>
50718 </field>
50719 <field>
50720 <name>I2CEN</name>
50721 <description>I2C Enable</description>
50722 <bitOffset>23</bitOffset>
50723 <bitWidth>1</bitWidth>
50724 </field>
50725 <field>
50726 <name>ACK</name>
50727 <description>I2C ACK</description>
50728 <bitOffset>24</bitOffset>
50729 <bitWidth>1</bitWidth>
50730 </field>
50731 <field>
50732 <name>I2CDEVADR</name>
50733 <description>I2C Device Address</description>
50734 <bitOffset>26</bitOffset>
50735 <bitWidth>2</bitWidth>
50736 </field>
50737 <field>
50738 <name>I2CDATSE0</name>
50739 <description>I2C DatSe0 USB mode</description>
50740 <bitOffset>28</bitOffset>
50741 <bitWidth>1</bitWidth>
50742 </field>
50743 <field>
50744 <name>RW</name>
50745 <description>Read/Write Indicator</description>
50746 <bitOffset>30</bitOffset>
50747 <bitWidth>1</bitWidth>
50748 </field>
50749 <field>
50750 <name>BSYDNE</name>
50751 <description>I2C Busy/Done</description>
50752 <bitOffset>31</bitOffset>
50753 <bitWidth>1</bitWidth>
50754 </field>
50755 </fields>
50756 </register>
50757 <register>
50758 <name>OTG_FS_GPWRDN</name>
50759 <displayName>OTG_FS_GPWRDN</displayName>
50760 <description>OTG power down register</description>
50761 <addressOffset>0x58</addressOffset>
50762 <size>0x20</size>
50763 <access>read-write</access>
50764 <resetValue>0x02000400</resetValue>
50765 <fields>
50766 <field>
50767 <name>ADPMEN</name>
50768 <description>ADP module enable</description>
50769 <bitOffset>0</bitOffset>
50770 <bitWidth>1</bitWidth>
50771 </field>
50772 <field>
50773 <name>ADPIF</name>
50774 <description>ADP interrupt flag</description>
50775 <bitOffset>23</bitOffset>
50776 <bitWidth>1</bitWidth>
50777 </field>
50778 </fields>
50779 </register>
50780 <register>
50781 <name>OTG_FS_GADPCTL</name>
50782 <displayName>OTG_FS_GADPCTL</displayName>
50783 <description>OTG ADP timer, control and status
50784 register</description>
50785 <addressOffset>0x60</addressOffset>
50786 <size>0x20</size>
50787 <resetValue>0x02000400</resetValue>
50788 <fields>
50789 <field>
50790 <name>PRBDSCHG</name>
50791 <description>Probe discharge</description>
50792 <bitOffset>0</bitOffset>
50793 <bitWidth>2</bitWidth>
50794 <access>read-write</access>
50795 </field>
50796 <field>
50797 <name>PRBDELTA</name>
50798 <description>Probe delta</description>
50799 <bitOffset>2</bitOffset>
50800 <bitWidth>2</bitWidth>
50801 <access>read-write</access>
50802 </field>
50803 <field>
50804 <name>PRBPER</name>
50805 <description>Probe period</description>
50806 <bitOffset>4</bitOffset>
50807 <bitWidth>2</bitWidth>
50808 <access>read-write</access>
50809 </field>
50810 <field>
50811 <name>RTIM</name>
50812 <description>Ramp time</description>
50813 <bitOffset>6</bitOffset>
50814 <bitWidth>11</bitWidth>
50815 <access>read-only</access>
50816 </field>
50817 <field>
50818 <name>ENAPRB</name>
50819 <description>Enable probe</description>
50820 <bitOffset>17</bitOffset>
50821 <bitWidth>1</bitWidth>
50822 <access>read-write</access>
50823 </field>
50824 <field>
50825 <name>ENASNS</name>
50826 <description>Enable sense</description>
50827 <bitOffset>18</bitOffset>
50828 <bitWidth>1</bitWidth>
50829 <access>read-write</access>
50830 </field>
50831 <field>
50832 <name>ADPRST</name>
50833 <description>ADP reset</description>
50834 <bitOffset>19</bitOffset>
50835 <bitWidth>1</bitWidth>
50836 <access>read-only</access>
50837 </field>
50838 <field>
50839 <name>ADPEN</name>
50840 <description>ADP enable</description>
50841 <bitOffset>20</bitOffset>
50842 <bitWidth>1</bitWidth>
50843 <access>read-write</access>
50844 </field>
50845 <field>
50846 <name>ADPPRBIF</name>
50847 <description>ADP probe interrupt flag</description>
50848 <bitOffset>21</bitOffset>
50849 <bitWidth>1</bitWidth>
50850 <access>read-write</access>
50851 </field>
50852 <field>
50853 <name>ADPSNSIF</name>
50854 <description>ADP sense interrupt flag</description>
50855 <bitOffset>22</bitOffset>
50856 <bitWidth>1</bitWidth>
50857 <access>read-write</access>
50858 </field>
50859 <field>
50860 <name>ADPTOIF</name>
50861 <description>ADP timeout interrupt flag</description>
50862 <bitOffset>23</bitOffset>
50863 <bitWidth>1</bitWidth>
50864 <access>read-write</access>
50865 </field>
50866 <field>
50867 <name>ADPPRBIM</name>
50868 <description>ADP probe interrupt mask</description>
50869 <bitOffset>24</bitOffset>
50870 <bitWidth>1</bitWidth>
50871 <access>read-write</access>
50872 </field>
50873 <field>
50874 <name>ADPSNSIM</name>
50875 <description>ADP sense interrupt mask</description>
50876 <bitOffset>25</bitOffset>
50877 <bitWidth>1</bitWidth>
50878 <access>read-write</access>
50879 </field>
50880 <field>
50881 <name>ADPTOIM</name>
50882 <description>ADP timeout interrupt mask</description>
50883 <bitOffset>26</bitOffset>
50884 <bitWidth>1</bitWidth>
50885 <access>read-write</access>
50886 </field>
50887 <field>
50888 <name>AR</name>
50889 <description>Access request</description>
50890 <bitOffset>27</bitOffset>
50891 <bitWidth>2</bitWidth>
50892 <access>read-write</access>
50893 </field>
50894 </fields>
50895 </register>
50896 <register>
50897 <name>OTG_FS_DIEPTXF4</name>
50898 <displayName>OTG_FS_DIEPTXF4</displayName>
50899 <description>OTG_FS device IN endpoint transmit FIFO size
50900 register (OTG_FS_DIEPTXF4)</description>
50901 <addressOffset>0x110</addressOffset>
50902 <size>0x20</size>
50903 <access>read-write</access>
50904 <resetValue>0x02000400</resetValue>
50905 <fields>
50906 <field>
50907 <name>INEPTXSA</name>
50908 <description>IN endpoint FIFOx transmit RAM start
50909 address</description>
50910 <bitOffset>0</bitOffset>
50911 <bitWidth>16</bitWidth>
50912 </field>
50913 <field>
50914 <name>INEPTXFD</name>
50915 <description>IN endpoint Tx FIFO depth</description>
50916 <bitOffset>16</bitOffset>
50917 <bitWidth>16</bitWidth>
50918 </field>
50919 </fields>
50920 </register>
50921 <register>
50922 <name>OTG_FS_DIEPTXF5</name>
50923 <displayName>OTG_FS_DIEPTXF5</displayName>
50924 <description>OTG_FS device IN endpoint transmit FIFO size
50925 register (OTG_FS_DIEPTXF5)</description>
50926 <addressOffset>0x114</addressOffset>
50927 <size>0x20</size>
50928 <access>read-write</access>
50929 <resetValue>0x02000400</resetValue>
50930 <fields>
50931 <field>
50932 <name>INEPTXSA</name>
50933 <description>IN endpoint FIFOx transmit RAM start
50934 address</description>
50935 <bitOffset>0</bitOffset>
50936 <bitWidth>16</bitWidth>
50937 </field>
50938 <field>
50939 <name>INEPTXFD</name>
50940 <description>IN endpoint Tx FIFO depth</description>
50941 <bitOffset>16</bitOffset>
50942 <bitWidth>16</bitWidth>
50943 </field>
50944 </fields>
50945 </register>
50946 <register>
50947 <name>OTG_FS_GLPMCFG</name>
50948 <displayName>OTG_FS_GLPMCFG</displayName>
50949 <description>OTG core LPM configuration
50950 register</description>
50951 <addressOffset>0x54</addressOffset>
50952 <size>0x20</size>
50953 <resetValue>0x02000400</resetValue>
50954 <fields>
50955 <field>
50956 <name>LPMEN</name>
50957 <description>LPM support enable</description>
50958 <bitOffset>0</bitOffset>
50959 <bitWidth>1</bitWidth>
50960 <access>read-write</access>
50961 </field>
50962 <field>
50963 <name>LPMACK</name>
50964 <description>LPM token acknowledge
50965 enable</description>
50966 <bitOffset>1</bitOffset>
50967 <bitWidth>1</bitWidth>
50968 <access>read-write</access>
50969 </field>
50970 <field>
50971 <name>BESL</name>
50972 <description>Best effort service
50973 latency</description>
50974 <bitOffset>2</bitOffset>
50975 <bitWidth>4</bitWidth>
50976 <access>read-write</access>
50977 </field>
50978 <field>
50979 <name>REMWAKE</name>
50980 <description>bRemoteWake value</description>
50981 <bitOffset>6</bitOffset>
50982 <bitWidth>1</bitWidth>
50983 <access>read-write</access>
50984 </field>
50985 <field>
50986 <name>L1SSEN</name>
50987 <description>L1 Shallow Sleep enable</description>
50988 <bitOffset>7</bitOffset>
50989 <bitWidth>1</bitWidth>
50990 <access>read-write</access>
50991 </field>
50992 <field>
50993 <name>BESLTHRS</name>
50994 <description>BESL threshold</description>
50995 <bitOffset>8</bitOffset>
50996 <bitWidth>4</bitWidth>
50997 <access>read-write</access>
50998 </field>
50999 <field>
51000 <name>L1DSEN</name>
51001 <description>L1 deep sleep enable</description>
51002 <bitOffset>12</bitOffset>
51003 <bitWidth>1</bitWidth>
51004 <access>read-write</access>
51005 </field>
51006 <field>
51007 <name>LPMRST</name>
51008 <description>LPM response</description>
51009 <bitOffset>13</bitOffset>
51010 <bitWidth>2</bitWidth>
51011 <access>read-only</access>
51012 </field>
51013 <field>
51014 <name>SLPSTS</name>
51015 <description>Port sleep status</description>
51016 <bitOffset>15</bitOffset>
51017 <bitWidth>1</bitWidth>
51018 <access>read-only</access>
51019 </field>
51020 <field>
51021 <name>L1RSMOK</name>
51022 <description>Sleep State Resume OK</description>
51023 <bitOffset>16</bitOffset>
51024 <bitWidth>1</bitWidth>
51025 <access>read-only</access>
51026 </field>
51027 <field>
51028 <name>LPMCHIDX</name>
51029 <description>LPM Channel Index</description>
51030 <bitOffset>17</bitOffset>
51031 <bitWidth>4</bitWidth>
51032 <access>read-write</access>
51033 </field>
51034 <field>
51035 <name>LPMRCNT</name>
51036 <description>LPM retry count</description>
51037 <bitOffset>21</bitOffset>
51038 <bitWidth>3</bitWidth>
51039 <access>read-write</access>
51040 </field>
51041 <field>
51042 <name>SNDLPM</name>
51043 <description>Send LPM transaction</description>
51044 <bitOffset>24</bitOffset>
51045 <bitWidth>1</bitWidth>
51046 <access>read-write</access>
51047 </field>
51048 <field>
51049 <name>LPMRCNTSTS</name>
51050 <description>LPM retry count status</description>
51051 <bitOffset>25</bitOffset>
51052 <bitWidth>3</bitWidth>
51053 <access>read-only</access>
51054 </field>
51055 <field>
51056 <name>ENBESL</name>
51057 <description>Enable best effort service
51058 latency</description>
51059 <bitOffset>28</bitOffset>
51060 <bitWidth>1</bitWidth>
51061 <access>read-write</access>
51062 </field>
51063 </fields>
51064 </register>
51065 </registers>
51066 </peripheral>
51067 <peripheral>
51068 <name>OTG_FS_HOST</name>
51069 <description>USB on the go full speed</description>
51070 <groupName>USB_OTG_FS</groupName>
51071 <baseAddress>0x50000400</baseAddress>
51072 <addressBlock>
51073 <offset>0x0</offset>
51074 <size>0x400</size>
51075 <usage>registers</usage>
51076 </addressBlock>
51077 <registers>
51078 <register>
51079 <name>OTG_FS_HCFG</name>
51080 <displayName>OTG_FS_HCFG</displayName>
51081 <description>OTG_FS host configuration register
51082 (OTG_FS_HCFG)</description>
51083 <addressOffset>0x0</addressOffset>
51084 <size>0x20</size>
51085 <resetValue>0x00000000</resetValue>
51086 <fields>
51087 <field>
51088 <name>FSLSPCS</name>
51089 <description>FS/LS PHY clock select</description>
51090 <bitOffset>0</bitOffset>
51091 <bitWidth>2</bitWidth>
51092 <access>read-write</access>
51093 </field>
51094 <field>
51095 <name>FSLSS</name>
51096 <description>FS- and LS-only support</description>
51097 <bitOffset>2</bitOffset>
51098 <bitWidth>1</bitWidth>
51099 <access>read-only</access>
51100 </field>
51101 </fields>
51102 </register>
51103 <register>
51104 <name>OTG_FS_HFIR</name>
51105 <displayName>OTG_FS_HFIR</displayName>
51106 <description>OTG_FS Host frame interval
51107 register</description>
51108 <addressOffset>0x4</addressOffset>
51109 <size>0x20</size>
51110 <access>read-write</access>
51111 <resetValue>0x0000EA60</resetValue>
51112 <fields>
51113 <field>
51114 <name>FRIVL</name>
51115 <description>Frame interval</description>
51116 <bitOffset>0</bitOffset>
51117 <bitWidth>16</bitWidth>
51118 </field>
51119 </fields>
51120 </register>
51121 <register>
51122 <name>OTG_FS_HFNUM</name>
51123 <displayName>OTG_FS_HFNUM</displayName>
51124 <description>OTG_FS host frame number/frame time
51125 remaining register (OTG_FS_HFNUM)</description>
51126 <addressOffset>0x8</addressOffset>
51127 <size>0x20</size>
51128 <access>read-only</access>
51129 <resetValue>0x00003FFF</resetValue>
51130 <fields>
51131 <field>
51132 <name>FRNUM</name>
51133 <description>Frame number</description>
51134 <bitOffset>0</bitOffset>
51135 <bitWidth>16</bitWidth>
51136 </field>
51137 <field>
51138 <name>FTREM</name>
51139 <description>Frame time remaining</description>
51140 <bitOffset>16</bitOffset>
51141 <bitWidth>16</bitWidth>
51142 </field>
51143 </fields>
51144 </register>
51145 <register>
51146 <name>OTG_FS_HPTXSTS</name>
51147 <displayName>OTG_FS_HPTXSTS</displayName>
51148 <description>OTG_FS_Host periodic transmit FIFO/queue
51149 status register (OTG_FS_HPTXSTS)</description>
51150 <addressOffset>0x10</addressOffset>
51151 <size>0x20</size>
51152 <resetValue>0x00080100</resetValue>
51153 <fields>
51154 <field>
51155 <name>PTXFSAVL</name>
51156 <description>Periodic transmit data FIFO space
51157 available</description>
51158 <bitOffset>0</bitOffset>
51159 <bitWidth>16</bitWidth>
51160 <access>read-write</access>
51161 </field>
51162 <field>
51163 <name>PTXQSAV</name>
51164 <description>Periodic transmit request queue space
51165 available</description>
51166 <bitOffset>16</bitOffset>
51167 <bitWidth>8</bitWidth>
51168 <access>read-only</access>
51169 </field>
51170 <field>
51171 <name>PTXQTOP</name>
51172 <description>Top of the periodic transmit request
51173 queue</description>
51174 <bitOffset>24</bitOffset>
51175 <bitWidth>8</bitWidth>
51176 <access>read-only</access>
51177 </field>
51178 </fields>
51179 </register>
51180 <register>
51181 <name>OTG_FS_HAINT</name>
51182 <displayName>OTG_FS_HAINT</displayName>
51183 <description>OTG_FS Host all channels interrupt
51184 register</description>
51185 <addressOffset>0x14</addressOffset>
51186 <size>0x20</size>
51187 <access>read-only</access>
51188 <resetValue>0x00000000</resetValue>
51189 <fields>
51190 <field>
51191 <name>HAINT</name>
51192 <description>Channel interrupts</description>
51193 <bitOffset>0</bitOffset>
51194 <bitWidth>16</bitWidth>
51195 </field>
51196 </fields>
51197 </register>
51198 <register>
51199 <name>OTG_FS_HAINTMSK</name>
51200 <displayName>OTG_FS_HAINTMSK</displayName>
51201 <description>OTG_FS host all channels interrupt mask
51202 register</description>
51203 <addressOffset>0x18</addressOffset>
51204 <size>0x20</size>
51205 <access>read-write</access>
51206 <resetValue>0x00000000</resetValue>
51207 <fields>
51208 <field>
51209 <name>HAINTM</name>
51210 <description>Channel interrupt mask</description>
51211 <bitOffset>0</bitOffset>
51212 <bitWidth>16</bitWidth>
51213 </field>
51214 </fields>
51215 </register>
51216 <register>
51217 <name>OTG_FS_HPRT</name>
51218 <displayName>OTG_FS_HPRT</displayName>
51219 <description>OTG_FS host port control and status register
51220 (OTG_FS_HPRT)</description>
51221 <addressOffset>0x40</addressOffset>
51222 <size>0x20</size>
51223 <resetValue>0x00000000</resetValue>
51224 <fields>
51225 <field>
51226 <name>PCSTS</name>
51227 <description>Port connect status</description>
51228 <bitOffset>0</bitOffset>
51229 <bitWidth>1</bitWidth>
51230 <access>read-only</access>
51231 </field>
51232 <field>
51233 <name>PCDET</name>
51234 <description>Port connect detected</description>
51235 <bitOffset>1</bitOffset>
51236 <bitWidth>1</bitWidth>
51237 <access>read-write</access>
51238 </field>
51239 <field>
51240 <name>PENA</name>
51241 <description>Port enable</description>
51242 <bitOffset>2</bitOffset>
51243 <bitWidth>1</bitWidth>
51244 <access>read-write</access>
51245 </field>
51246 <field>
51247 <name>PENCHNG</name>
51248 <description>Port enable/disable change</description>
51249 <bitOffset>3</bitOffset>
51250 <bitWidth>1</bitWidth>
51251 <access>read-write</access>
51252 </field>
51253 <field>
51254 <name>POCA</name>
51255 <description>Port overcurrent active</description>
51256 <bitOffset>4</bitOffset>
51257 <bitWidth>1</bitWidth>
51258 <access>read-only</access>
51259 </field>
51260 <field>
51261 <name>POCCHNG</name>
51262 <description>Port overcurrent change</description>
51263 <bitOffset>5</bitOffset>
51264 <bitWidth>1</bitWidth>
51265 <access>read-write</access>
51266 </field>
51267 <field>
51268 <name>PRES</name>
51269 <description>Port resume</description>
51270 <bitOffset>6</bitOffset>
51271 <bitWidth>1</bitWidth>
51272 <access>read-write</access>
51273 </field>
51274 <field>
51275 <name>PSUSP</name>
51276 <description>Port suspend</description>
51277 <bitOffset>7</bitOffset>
51278 <bitWidth>1</bitWidth>
51279 <access>read-write</access>
51280 </field>
51281 <field>
51282 <name>PRST</name>
51283 <description>Port reset</description>
51284 <bitOffset>8</bitOffset>
51285 <bitWidth>1</bitWidth>
51286 <access>read-write</access>
51287 </field>
51288 <field>
51289 <name>PLSTS</name>
51290 <description>Port line status</description>
51291 <bitOffset>10</bitOffset>
51292 <bitWidth>2</bitWidth>
51293 <access>read-only</access>
51294 </field>
51295 <field>
51296 <name>PPWR</name>
51297 <description>Port power</description>
51298 <bitOffset>12</bitOffset>
51299 <bitWidth>1</bitWidth>
51300 <access>read-write</access>
51301 </field>
51302 <field>
51303 <name>PTCTL</name>
51304 <description>Port test control</description>
51305 <bitOffset>13</bitOffset>
51306 <bitWidth>4</bitWidth>
51307 <access>read-write</access>
51308 </field>
51309 <field>
51310 <name>PSPD</name>
51311 <description>Port speed</description>
51312 <bitOffset>17</bitOffset>
51313 <bitWidth>2</bitWidth>
51314 <access>read-only</access>
51315 </field>
51316 </fields>
51317 </register>
51318 <register>
51319 <name>OTG_FS_HCCHAR0</name>
51320 <displayName>OTG_FS_HCCHAR0</displayName>
51321 <description>OTG_FS host channel-0 characteristics
51322 register (OTG_FS_HCCHAR0)</description>
51323 <addressOffset>0x100</addressOffset>
51324 <size>0x20</size>
51325 <access>read-write</access>
51326 <resetValue>0x00000000</resetValue>
51327 <fields>
51328 <field>
51329 <name>MPSIZ</name>
51330 <description>Maximum packet size</description>
51331 <bitOffset>0</bitOffset>
51332 <bitWidth>11</bitWidth>
51333 </field>
51334 <field>
51335 <name>EPNUM</name>
51336 <description>Endpoint number</description>
51337 <bitOffset>11</bitOffset>
51338 <bitWidth>4</bitWidth>
51339 </field>
51340 <field>
51341 <name>EPDIR</name>
51342 <description>Endpoint direction</description>
51343 <bitOffset>15</bitOffset>
51344 <bitWidth>1</bitWidth>
51345 </field>
51346 <field>
51347 <name>LSDEV</name>
51348 <description>Low-speed device</description>
51349 <bitOffset>17</bitOffset>
51350 <bitWidth>1</bitWidth>
51351 </field>
51352 <field>
51353 <name>EPTYP</name>
51354 <description>Endpoint type</description>
51355 <bitOffset>18</bitOffset>
51356 <bitWidth>2</bitWidth>
51357 </field>
51358 <field>
51359 <name>MCNT</name>
51360 <description>Multicount</description>
51361 <bitOffset>20</bitOffset>
51362 <bitWidth>2</bitWidth>
51363 </field>
51364 <field>
51365 <name>DAD</name>
51366 <description>Device address</description>
51367 <bitOffset>22</bitOffset>
51368 <bitWidth>7</bitWidth>
51369 </field>
51370 <field>
51371 <name>ODDFRM</name>
51372 <description>Odd frame</description>
51373 <bitOffset>29</bitOffset>
51374 <bitWidth>1</bitWidth>
51375 </field>
51376 <field>
51377 <name>CHDIS</name>
51378 <description>Channel disable</description>
51379 <bitOffset>30</bitOffset>
51380 <bitWidth>1</bitWidth>
51381 </field>
51382 <field>
51383 <name>CHENA</name>
51384 <description>Channel enable</description>
51385 <bitOffset>31</bitOffset>
51386 <bitWidth>1</bitWidth>
51387 </field>
51388 </fields>
51389 </register>
51390 <register>
51391 <name>OTG_FS_HCCHAR1</name>
51392 <displayName>OTG_FS_HCCHAR1</displayName>
51393 <description>OTG_FS host channel-1 characteristics
51394 register (OTG_FS_HCCHAR1)</description>
51395 <addressOffset>0x120</addressOffset>
51396 <size>0x20</size>
51397 <access>read-write</access>
51398 <resetValue>0x00000000</resetValue>
51399 <fields>
51400 <field>
51401 <name>MPSIZ</name>
51402 <description>Maximum packet size</description>
51403 <bitOffset>0</bitOffset>
51404 <bitWidth>11</bitWidth>
51405 </field>
51406 <field>
51407 <name>EPNUM</name>
51408 <description>Endpoint number</description>
51409 <bitOffset>11</bitOffset>
51410 <bitWidth>4</bitWidth>
51411 </field>
51412 <field>
51413 <name>EPDIR</name>
51414 <description>Endpoint direction</description>
51415 <bitOffset>15</bitOffset>
51416 <bitWidth>1</bitWidth>
51417 </field>
51418 <field>
51419 <name>LSDEV</name>
51420 <description>Low-speed device</description>
51421 <bitOffset>17</bitOffset>
51422 <bitWidth>1</bitWidth>
51423 </field>
51424 <field>
51425 <name>EPTYP</name>
51426 <description>Endpoint type</description>
51427 <bitOffset>18</bitOffset>
51428 <bitWidth>2</bitWidth>
51429 </field>
51430 <field>
51431 <name>MCNT</name>
51432 <description>Multicount</description>
51433 <bitOffset>20</bitOffset>
51434 <bitWidth>2</bitWidth>
51435 </field>
51436 <field>
51437 <name>DAD</name>
51438 <description>Device address</description>
51439 <bitOffset>22</bitOffset>
51440 <bitWidth>7</bitWidth>
51441 </field>
51442 <field>
51443 <name>ODDFRM</name>
51444 <description>Odd frame</description>
51445 <bitOffset>29</bitOffset>
51446 <bitWidth>1</bitWidth>
51447 </field>
51448 <field>
51449 <name>CHDIS</name>
51450 <description>Channel disable</description>
51451 <bitOffset>30</bitOffset>
51452 <bitWidth>1</bitWidth>
51453 </field>
51454 <field>
51455 <name>CHENA</name>
51456 <description>Channel enable</description>
51457 <bitOffset>31</bitOffset>
51458 <bitWidth>1</bitWidth>
51459 </field>
51460 </fields>
51461 </register>
51462 <register>
51463 <name>OTG_FS_HCCHAR2</name>
51464 <displayName>OTG_FS_HCCHAR2</displayName>
51465 <description>OTG_FS host channel-2 characteristics
51466 register (OTG_FS_HCCHAR2)</description>
51467 <addressOffset>0x140</addressOffset>
51468 <size>0x20</size>
51469 <access>read-write</access>
51470 <resetValue>0x00000000</resetValue>
51471 <fields>
51472 <field>
51473 <name>MPSIZ</name>
51474 <description>Maximum packet size</description>
51475 <bitOffset>0</bitOffset>
51476 <bitWidth>11</bitWidth>
51477 </field>
51478 <field>
51479 <name>EPNUM</name>
51480 <description>Endpoint number</description>
51481 <bitOffset>11</bitOffset>
51482 <bitWidth>4</bitWidth>
51483 </field>
51484 <field>
51485 <name>EPDIR</name>
51486 <description>Endpoint direction</description>
51487 <bitOffset>15</bitOffset>
51488 <bitWidth>1</bitWidth>
51489 </field>
51490 <field>
51491 <name>LSDEV</name>
51492 <description>Low-speed device</description>
51493 <bitOffset>17</bitOffset>
51494 <bitWidth>1</bitWidth>
51495 </field>
51496 <field>
51497 <name>EPTYP</name>
51498 <description>Endpoint type</description>
51499 <bitOffset>18</bitOffset>
51500 <bitWidth>2</bitWidth>
51501 </field>
51502 <field>
51503 <name>MCNT</name>
51504 <description>Multicount</description>
51505 <bitOffset>20</bitOffset>
51506 <bitWidth>2</bitWidth>
51507 </field>
51508 <field>
51509 <name>DAD</name>
51510 <description>Device address</description>
51511 <bitOffset>22</bitOffset>
51512 <bitWidth>7</bitWidth>
51513 </field>
51514 <field>
51515 <name>ODDFRM</name>
51516 <description>Odd frame</description>
51517 <bitOffset>29</bitOffset>
51518 <bitWidth>1</bitWidth>
51519 </field>
51520 <field>
51521 <name>CHDIS</name>
51522 <description>Channel disable</description>
51523 <bitOffset>30</bitOffset>
51524 <bitWidth>1</bitWidth>
51525 </field>
51526 <field>
51527 <name>CHENA</name>
51528 <description>Channel enable</description>
51529 <bitOffset>31</bitOffset>
51530 <bitWidth>1</bitWidth>
51531 </field>
51532 </fields>
51533 </register>
51534 <register>
51535 <name>OTG_FS_HCCHAR3</name>
51536 <displayName>OTG_FS_HCCHAR3</displayName>
51537 <description>OTG_FS host channel-3 characteristics
51538 register (OTG_FS_HCCHAR3)</description>
51539 <addressOffset>0x160</addressOffset>
51540 <size>0x20</size>
51541 <access>read-write</access>
51542 <resetValue>0x00000000</resetValue>
51543 <fields>
51544 <field>
51545 <name>MPSIZ</name>
51546 <description>Maximum packet size</description>
51547 <bitOffset>0</bitOffset>
51548 <bitWidth>11</bitWidth>
51549 </field>
51550 <field>
51551 <name>EPNUM</name>
51552 <description>Endpoint number</description>
51553 <bitOffset>11</bitOffset>
51554 <bitWidth>4</bitWidth>
51555 </field>
51556 <field>
51557 <name>EPDIR</name>
51558 <description>Endpoint direction</description>
51559 <bitOffset>15</bitOffset>
51560 <bitWidth>1</bitWidth>
51561 </field>
51562 <field>
51563 <name>LSDEV</name>
51564 <description>Low-speed device</description>
51565 <bitOffset>17</bitOffset>
51566 <bitWidth>1</bitWidth>
51567 </field>
51568 <field>
51569 <name>EPTYP</name>
51570 <description>Endpoint type</description>
51571 <bitOffset>18</bitOffset>
51572 <bitWidth>2</bitWidth>
51573 </field>
51574 <field>
51575 <name>MCNT</name>
51576 <description>Multicount</description>
51577 <bitOffset>20</bitOffset>
51578 <bitWidth>2</bitWidth>
51579 </field>
51580 <field>
51581 <name>DAD</name>
51582 <description>Device address</description>
51583 <bitOffset>22</bitOffset>
51584 <bitWidth>7</bitWidth>
51585 </field>
51586 <field>
51587 <name>ODDFRM</name>
51588 <description>Odd frame</description>
51589 <bitOffset>29</bitOffset>
51590 <bitWidth>1</bitWidth>
51591 </field>
51592 <field>
51593 <name>CHDIS</name>
51594 <description>Channel disable</description>
51595 <bitOffset>30</bitOffset>
51596 <bitWidth>1</bitWidth>
51597 </field>
51598 <field>
51599 <name>CHENA</name>
51600 <description>Channel enable</description>
51601 <bitOffset>31</bitOffset>
51602 <bitWidth>1</bitWidth>
51603 </field>
51604 </fields>
51605 </register>
51606 <register>
51607 <name>OTG_FS_HCCHAR4</name>
51608 <displayName>OTG_FS_HCCHAR4</displayName>
51609 <description>OTG_FS host channel-4 characteristics
51610 register (OTG_FS_HCCHAR4)</description>
51611 <addressOffset>0x180</addressOffset>
51612 <size>0x20</size>
51613 <access>read-write</access>
51614 <resetValue>0x00000000</resetValue>
51615 <fields>
51616 <field>
51617 <name>MPSIZ</name>
51618 <description>Maximum packet size</description>
51619 <bitOffset>0</bitOffset>
51620 <bitWidth>11</bitWidth>
51621 </field>
51622 <field>
51623 <name>EPNUM</name>
51624 <description>Endpoint number</description>
51625 <bitOffset>11</bitOffset>
51626 <bitWidth>4</bitWidth>
51627 </field>
51628 <field>
51629 <name>EPDIR</name>
51630 <description>Endpoint direction</description>
51631 <bitOffset>15</bitOffset>
51632 <bitWidth>1</bitWidth>
51633 </field>
51634 <field>
51635 <name>LSDEV</name>
51636 <description>Low-speed device</description>
51637 <bitOffset>17</bitOffset>
51638 <bitWidth>1</bitWidth>
51639 </field>
51640 <field>
51641 <name>EPTYP</name>
51642 <description>Endpoint type</description>
51643 <bitOffset>18</bitOffset>
51644 <bitWidth>2</bitWidth>
51645 </field>
51646 <field>
51647 <name>MCNT</name>
51648 <description>Multicount</description>
51649 <bitOffset>20</bitOffset>
51650 <bitWidth>2</bitWidth>
51651 </field>
51652 <field>
51653 <name>DAD</name>
51654 <description>Device address</description>
51655 <bitOffset>22</bitOffset>
51656 <bitWidth>7</bitWidth>
51657 </field>
51658 <field>
51659 <name>ODDFRM</name>
51660 <description>Odd frame</description>
51661 <bitOffset>29</bitOffset>
51662 <bitWidth>1</bitWidth>
51663 </field>
51664 <field>
51665 <name>CHDIS</name>
51666 <description>Channel disable</description>
51667 <bitOffset>30</bitOffset>
51668 <bitWidth>1</bitWidth>
51669 </field>
51670 <field>
51671 <name>CHENA</name>
51672 <description>Channel enable</description>
51673 <bitOffset>31</bitOffset>
51674 <bitWidth>1</bitWidth>
51675 </field>
51676 </fields>
51677 </register>
51678 <register>
51679 <name>OTG_FS_HCCHAR5</name>
51680 <displayName>OTG_FS_HCCHAR5</displayName>
51681 <description>OTG_FS host channel-5 characteristics
51682 register (OTG_FS_HCCHAR5)</description>
51683 <addressOffset>0x1A0</addressOffset>
51684 <size>0x20</size>
51685 <access>read-write</access>
51686 <resetValue>0x00000000</resetValue>
51687 <fields>
51688 <field>
51689 <name>MPSIZ</name>
51690 <description>Maximum packet size</description>
51691 <bitOffset>0</bitOffset>
51692 <bitWidth>11</bitWidth>
51693 </field>
51694 <field>
51695 <name>EPNUM</name>
51696 <description>Endpoint number</description>
51697 <bitOffset>11</bitOffset>
51698 <bitWidth>4</bitWidth>
51699 </field>
51700 <field>
51701 <name>EPDIR</name>
51702 <description>Endpoint direction</description>
51703 <bitOffset>15</bitOffset>
51704 <bitWidth>1</bitWidth>
51705 </field>
51706 <field>
51707 <name>LSDEV</name>
51708 <description>Low-speed device</description>
51709 <bitOffset>17</bitOffset>
51710 <bitWidth>1</bitWidth>
51711 </field>
51712 <field>
51713 <name>EPTYP</name>
51714 <description>Endpoint type</description>
51715 <bitOffset>18</bitOffset>
51716 <bitWidth>2</bitWidth>
51717 </field>
51718 <field>
51719 <name>MCNT</name>
51720 <description>Multicount</description>
51721 <bitOffset>20</bitOffset>
51722 <bitWidth>2</bitWidth>
51723 </field>
51724 <field>
51725 <name>DAD</name>
51726 <description>Device address</description>
51727 <bitOffset>22</bitOffset>
51728 <bitWidth>7</bitWidth>
51729 </field>
51730 <field>
51731 <name>ODDFRM</name>
51732 <description>Odd frame</description>
51733 <bitOffset>29</bitOffset>
51734 <bitWidth>1</bitWidth>
51735 </field>
51736 <field>
51737 <name>CHDIS</name>
51738 <description>Channel disable</description>
51739 <bitOffset>30</bitOffset>
51740 <bitWidth>1</bitWidth>
51741 </field>
51742 <field>
51743 <name>CHENA</name>
51744 <description>Channel enable</description>
51745 <bitOffset>31</bitOffset>
51746 <bitWidth>1</bitWidth>
51747 </field>
51748 </fields>
51749 </register>
51750 <register>
51751 <name>OTG_FS_HCCHAR6</name>
51752 <displayName>OTG_FS_HCCHAR6</displayName>
51753 <description>OTG_FS host channel-6 characteristics
51754 register (OTG_FS_HCCHAR6)</description>
51755 <addressOffset>0x1C0</addressOffset>
51756 <size>0x20</size>
51757 <access>read-write</access>
51758 <resetValue>0x00000000</resetValue>
51759 <fields>
51760 <field>
51761 <name>MPSIZ</name>
51762 <description>Maximum packet size</description>
51763 <bitOffset>0</bitOffset>
51764 <bitWidth>11</bitWidth>
51765 </field>
51766 <field>
51767 <name>EPNUM</name>
51768 <description>Endpoint number</description>
51769 <bitOffset>11</bitOffset>
51770 <bitWidth>4</bitWidth>
51771 </field>
51772 <field>
51773 <name>EPDIR</name>
51774 <description>Endpoint direction</description>
51775 <bitOffset>15</bitOffset>
51776 <bitWidth>1</bitWidth>
51777 </field>
51778 <field>
51779 <name>LSDEV</name>
51780 <description>Low-speed device</description>
51781 <bitOffset>17</bitOffset>
51782 <bitWidth>1</bitWidth>
51783 </field>
51784 <field>
51785 <name>EPTYP</name>
51786 <description>Endpoint type</description>
51787 <bitOffset>18</bitOffset>
51788 <bitWidth>2</bitWidth>
51789 </field>
51790 <field>
51791 <name>MCNT</name>
51792 <description>Multicount</description>
51793 <bitOffset>20</bitOffset>
51794 <bitWidth>2</bitWidth>
51795 </field>
51796 <field>
51797 <name>DAD</name>
51798 <description>Device address</description>
51799 <bitOffset>22</bitOffset>
51800 <bitWidth>7</bitWidth>
51801 </field>
51802 <field>
51803 <name>ODDFRM</name>
51804 <description>Odd frame</description>
51805 <bitOffset>29</bitOffset>
51806 <bitWidth>1</bitWidth>
51807 </field>
51808 <field>
51809 <name>CHDIS</name>
51810 <description>Channel disable</description>
51811 <bitOffset>30</bitOffset>
51812 <bitWidth>1</bitWidth>
51813 </field>
51814 <field>
51815 <name>CHENA</name>
51816 <description>Channel enable</description>
51817 <bitOffset>31</bitOffset>
51818 <bitWidth>1</bitWidth>
51819 </field>
51820 </fields>
51821 </register>
51822 <register>
51823 <name>OTG_FS_HCCHAR7</name>
51824 <displayName>OTG_FS_HCCHAR7</displayName>
51825 <description>OTG_FS host channel-7 characteristics
51826 register (OTG_FS_HCCHAR7)</description>
51827 <addressOffset>0x1E0</addressOffset>
51828 <size>0x20</size>
51829 <access>read-write</access>
51830 <resetValue>0x00000000</resetValue>
51831 <fields>
51832 <field>
51833 <name>MPSIZ</name>
51834 <description>Maximum packet size</description>
51835 <bitOffset>0</bitOffset>
51836 <bitWidth>11</bitWidth>
51837 </field>
51838 <field>
51839 <name>EPNUM</name>
51840 <description>Endpoint number</description>
51841 <bitOffset>11</bitOffset>
51842 <bitWidth>4</bitWidth>
51843 </field>
51844 <field>
51845 <name>EPDIR</name>
51846 <description>Endpoint direction</description>
51847 <bitOffset>15</bitOffset>
51848 <bitWidth>1</bitWidth>
51849 </field>
51850 <field>
51851 <name>LSDEV</name>
51852 <description>Low-speed device</description>
51853 <bitOffset>17</bitOffset>
51854 <bitWidth>1</bitWidth>
51855 </field>
51856 <field>
51857 <name>EPTYP</name>
51858 <description>Endpoint type</description>
51859 <bitOffset>18</bitOffset>
51860 <bitWidth>2</bitWidth>
51861 </field>
51862 <field>
51863 <name>MCNT</name>
51864 <description>Multicount</description>
51865 <bitOffset>20</bitOffset>
51866 <bitWidth>2</bitWidth>
51867 </field>
51868 <field>
51869 <name>DAD</name>
51870 <description>Device address</description>
51871 <bitOffset>22</bitOffset>
51872 <bitWidth>7</bitWidth>
51873 </field>
51874 <field>
51875 <name>ODDFRM</name>
51876 <description>Odd frame</description>
51877 <bitOffset>29</bitOffset>
51878 <bitWidth>1</bitWidth>
51879 </field>
51880 <field>
51881 <name>CHDIS</name>
51882 <description>Channel disable</description>
51883 <bitOffset>30</bitOffset>
51884 <bitWidth>1</bitWidth>
51885 </field>
51886 <field>
51887 <name>CHENA</name>
51888 <description>Channel enable</description>
51889 <bitOffset>31</bitOffset>
51890 <bitWidth>1</bitWidth>
51891 </field>
51892 </fields>
51893 </register>
51894 <register>
51895 <name>OTG_FS_HCINT0</name>
51896 <displayName>OTG_FS_HCINT0</displayName>
51897 <description>OTG_FS host channel-0 interrupt register
51898 (OTG_FS_HCINT0)</description>
51899 <addressOffset>0x108</addressOffset>
51900 <size>0x20</size>
51901 <access>read-write</access>
51902 <resetValue>0x00000000</resetValue>
51903 <fields>
51904 <field>
51905 <name>XFRC</name>
51906 <description>Transfer completed</description>
51907 <bitOffset>0</bitOffset>
51908 <bitWidth>1</bitWidth>
51909 </field>
51910 <field>
51911 <name>CHH</name>
51912 <description>Channel halted</description>
51913 <bitOffset>1</bitOffset>
51914 <bitWidth>1</bitWidth>
51915 </field>
51916 <field>
51917 <name>STALL</name>
51918 <description>STALL response received
51919 interrupt</description>
51920 <bitOffset>3</bitOffset>
51921 <bitWidth>1</bitWidth>
51922 </field>
51923 <field>
51924 <name>NAK</name>
51925 <description>NAK response received
51926 interrupt</description>
51927 <bitOffset>4</bitOffset>
51928 <bitWidth>1</bitWidth>
51929 </field>
51930 <field>
51931 <name>ACK</name>
51932 <description>ACK response received/transmitted
51933 interrupt</description>
51934 <bitOffset>5</bitOffset>
51935 <bitWidth>1</bitWidth>
51936 </field>
51937 <field>
51938 <name>TXERR</name>
51939 <description>Transaction error</description>
51940 <bitOffset>7</bitOffset>
51941 <bitWidth>1</bitWidth>
51942 </field>
51943 <field>
51944 <name>BBERR</name>
51945 <description>Babble error</description>
51946 <bitOffset>8</bitOffset>
51947 <bitWidth>1</bitWidth>
51948 </field>
51949 <field>
51950 <name>FRMOR</name>
51951 <description>Frame overrun</description>
51952 <bitOffset>9</bitOffset>
51953 <bitWidth>1</bitWidth>
51954 </field>
51955 <field>
51956 <name>DTERR</name>
51957 <description>Data toggle error</description>
51958 <bitOffset>10</bitOffset>
51959 <bitWidth>1</bitWidth>
51960 </field>
51961 </fields>
51962 </register>
51963 <register>
51964 <name>OTG_FS_HCINT1</name>
51965 <displayName>OTG_FS_HCINT1</displayName>
51966 <description>OTG_FS host channel-1 interrupt register
51967 (OTG_FS_HCINT1)</description>
51968 <addressOffset>0x128</addressOffset>
51969 <size>0x20</size>
51970 <access>read-write</access>
51971 <resetValue>0x00000000</resetValue>
51972 <fields>
51973 <field>
51974 <name>XFRC</name>
51975 <description>Transfer completed</description>
51976 <bitOffset>0</bitOffset>
51977 <bitWidth>1</bitWidth>
51978 </field>
51979 <field>
51980 <name>CHH</name>
51981 <description>Channel halted</description>
51982 <bitOffset>1</bitOffset>
51983 <bitWidth>1</bitWidth>
51984 </field>
51985 <field>
51986 <name>STALL</name>
51987 <description>STALL response received
51988 interrupt</description>
51989 <bitOffset>3</bitOffset>
51990 <bitWidth>1</bitWidth>
51991 </field>
51992 <field>
51993 <name>NAK</name>
51994 <description>NAK response received
51995 interrupt</description>
51996 <bitOffset>4</bitOffset>
51997 <bitWidth>1</bitWidth>
51998 </field>
51999 <field>
52000 <name>ACK</name>
52001 <description>ACK response received/transmitted
52002 interrupt</description>
52003 <bitOffset>5</bitOffset>
52004 <bitWidth>1</bitWidth>
52005 </field>
52006 <field>
52007 <name>TXERR</name>
52008 <description>Transaction error</description>
52009 <bitOffset>7</bitOffset>
52010 <bitWidth>1</bitWidth>
52011 </field>
52012 <field>
52013 <name>BBERR</name>
52014 <description>Babble error</description>
52015 <bitOffset>8</bitOffset>
52016 <bitWidth>1</bitWidth>
52017 </field>
52018 <field>
52019 <name>FRMOR</name>
52020 <description>Frame overrun</description>
52021 <bitOffset>9</bitOffset>
52022 <bitWidth>1</bitWidth>
52023 </field>
52024 <field>
52025 <name>DTERR</name>
52026 <description>Data toggle error</description>
52027 <bitOffset>10</bitOffset>
52028 <bitWidth>1</bitWidth>
52029 </field>
52030 </fields>
52031 </register>
52032 <register>
52033 <name>OTG_FS_HCINT2</name>
52034 <displayName>OTG_FS_HCINT2</displayName>
52035 <description>OTG_FS host channel-2 interrupt register
52036 (OTG_FS_HCINT2)</description>
52037 <addressOffset>0x148</addressOffset>
52038 <size>0x20</size>
52039 <access>read-write</access>
52040 <resetValue>0x00000000</resetValue>
52041 <fields>
52042 <field>
52043 <name>XFRC</name>
52044 <description>Transfer completed</description>
52045 <bitOffset>0</bitOffset>
52046 <bitWidth>1</bitWidth>
52047 </field>
52048 <field>
52049 <name>CHH</name>
52050 <description>Channel halted</description>
52051 <bitOffset>1</bitOffset>
52052 <bitWidth>1</bitWidth>
52053 </field>
52054 <field>
52055 <name>STALL</name>
52056 <description>STALL response received
52057 interrupt</description>
52058 <bitOffset>3</bitOffset>
52059 <bitWidth>1</bitWidth>
52060 </field>
52061 <field>
52062 <name>NAK</name>
52063 <description>NAK response received
52064 interrupt</description>
52065 <bitOffset>4</bitOffset>
52066 <bitWidth>1</bitWidth>
52067 </field>
52068 <field>
52069 <name>ACK</name>
52070 <description>ACK response received/transmitted
52071 interrupt</description>
52072 <bitOffset>5</bitOffset>
52073 <bitWidth>1</bitWidth>
52074 </field>
52075 <field>
52076 <name>TXERR</name>
52077 <description>Transaction error</description>
52078 <bitOffset>7</bitOffset>
52079 <bitWidth>1</bitWidth>
52080 </field>
52081 <field>
52082 <name>BBERR</name>
52083 <description>Babble error</description>
52084 <bitOffset>8</bitOffset>
52085 <bitWidth>1</bitWidth>
52086 </field>
52087 <field>
52088 <name>FRMOR</name>
52089 <description>Frame overrun</description>
52090 <bitOffset>9</bitOffset>
52091 <bitWidth>1</bitWidth>
52092 </field>
52093 <field>
52094 <name>DTERR</name>
52095 <description>Data toggle error</description>
52096 <bitOffset>10</bitOffset>
52097 <bitWidth>1</bitWidth>
52098 </field>
52099 </fields>
52100 </register>
52101 <register>
52102 <name>OTG_FS_HCINT3</name>
52103 <displayName>OTG_FS_HCINT3</displayName>
52104 <description>OTG_FS host channel-3 interrupt register
52105 (OTG_FS_HCINT3)</description>
52106 <addressOffset>0x168</addressOffset>
52107 <size>0x20</size>
52108 <access>read-write</access>
52109 <resetValue>0x00000000</resetValue>
52110 <fields>
52111 <field>
52112 <name>XFRC</name>
52113 <description>Transfer completed</description>
52114 <bitOffset>0</bitOffset>
52115 <bitWidth>1</bitWidth>
52116 </field>
52117 <field>
52118 <name>CHH</name>
52119 <description>Channel halted</description>
52120 <bitOffset>1</bitOffset>
52121 <bitWidth>1</bitWidth>
52122 </field>
52123 <field>
52124 <name>STALL</name>
52125 <description>STALL response received
52126 interrupt</description>
52127 <bitOffset>3</bitOffset>
52128 <bitWidth>1</bitWidth>
52129 </field>
52130 <field>
52131 <name>NAK</name>
52132 <description>NAK response received
52133 interrupt</description>
52134 <bitOffset>4</bitOffset>
52135 <bitWidth>1</bitWidth>
52136 </field>
52137 <field>
52138 <name>ACK</name>
52139 <description>ACK response received/transmitted
52140 interrupt</description>
52141 <bitOffset>5</bitOffset>
52142 <bitWidth>1</bitWidth>
52143 </field>
52144 <field>
52145 <name>TXERR</name>
52146 <description>Transaction error</description>
52147 <bitOffset>7</bitOffset>
52148 <bitWidth>1</bitWidth>
52149 </field>
52150 <field>
52151 <name>BBERR</name>
52152 <description>Babble error</description>
52153 <bitOffset>8</bitOffset>
52154 <bitWidth>1</bitWidth>
52155 </field>
52156 <field>
52157 <name>FRMOR</name>
52158 <description>Frame overrun</description>
52159 <bitOffset>9</bitOffset>
52160 <bitWidth>1</bitWidth>
52161 </field>
52162 <field>
52163 <name>DTERR</name>
52164 <description>Data toggle error</description>
52165 <bitOffset>10</bitOffset>
52166 <bitWidth>1</bitWidth>
52167 </field>
52168 </fields>
52169 </register>
52170 <register>
52171 <name>OTG_FS_HCINT4</name>
52172 <displayName>OTG_FS_HCINT4</displayName>
52173 <description>OTG_FS host channel-4 interrupt register
52174 (OTG_FS_HCINT4)</description>
52175 <addressOffset>0x188</addressOffset>
52176 <size>0x20</size>
52177 <access>read-write</access>
52178 <resetValue>0x00000000</resetValue>
52179 <fields>
52180 <field>
52181 <name>XFRC</name>
52182 <description>Transfer completed</description>
52183 <bitOffset>0</bitOffset>
52184 <bitWidth>1</bitWidth>
52185 </field>
52186 <field>
52187 <name>CHH</name>
52188 <description>Channel halted</description>
52189 <bitOffset>1</bitOffset>
52190 <bitWidth>1</bitWidth>
52191 </field>
52192 <field>
52193 <name>STALL</name>
52194 <description>STALL response received
52195 interrupt</description>
52196 <bitOffset>3</bitOffset>
52197 <bitWidth>1</bitWidth>
52198 </field>
52199 <field>
52200 <name>NAK</name>
52201 <description>NAK response received
52202 interrupt</description>
52203 <bitOffset>4</bitOffset>
52204 <bitWidth>1</bitWidth>
52205 </field>
52206 <field>
52207 <name>ACK</name>
52208 <description>ACK response received/transmitted
52209 interrupt</description>
52210 <bitOffset>5</bitOffset>
52211 <bitWidth>1</bitWidth>
52212 </field>
52213 <field>
52214 <name>TXERR</name>
52215 <description>Transaction error</description>
52216 <bitOffset>7</bitOffset>
52217 <bitWidth>1</bitWidth>
52218 </field>
52219 <field>
52220 <name>BBERR</name>
52221 <description>Babble error</description>
52222 <bitOffset>8</bitOffset>
52223 <bitWidth>1</bitWidth>
52224 </field>
52225 <field>
52226 <name>FRMOR</name>
52227 <description>Frame overrun</description>
52228 <bitOffset>9</bitOffset>
52229 <bitWidth>1</bitWidth>
52230 </field>
52231 <field>
52232 <name>DTERR</name>
52233 <description>Data toggle error</description>
52234 <bitOffset>10</bitOffset>
52235 <bitWidth>1</bitWidth>
52236 </field>
52237 </fields>
52238 </register>
52239 <register>
52240 <name>OTG_FS_HCINT5</name>
52241 <displayName>OTG_FS_HCINT5</displayName>
52242 <description>OTG_FS host channel-5 interrupt register
52243 (OTG_FS_HCINT5)</description>
52244 <addressOffset>0x1A8</addressOffset>
52245 <size>0x20</size>
52246 <access>read-write</access>
52247 <resetValue>0x00000000</resetValue>
52248 <fields>
52249 <field>
52250 <name>XFRC</name>
52251 <description>Transfer completed</description>
52252 <bitOffset>0</bitOffset>
52253 <bitWidth>1</bitWidth>
52254 </field>
52255 <field>
52256 <name>CHH</name>
52257 <description>Channel halted</description>
52258 <bitOffset>1</bitOffset>
52259 <bitWidth>1</bitWidth>
52260 </field>
52261 <field>
52262 <name>STALL</name>
52263 <description>STALL response received
52264 interrupt</description>
52265 <bitOffset>3</bitOffset>
52266 <bitWidth>1</bitWidth>
52267 </field>
52268 <field>
52269 <name>NAK</name>
52270 <description>NAK response received
52271 interrupt</description>
52272 <bitOffset>4</bitOffset>
52273 <bitWidth>1</bitWidth>
52274 </field>
52275 <field>
52276 <name>ACK</name>
52277 <description>ACK response received/transmitted
52278 interrupt</description>
52279 <bitOffset>5</bitOffset>
52280 <bitWidth>1</bitWidth>
52281 </field>
52282 <field>
52283 <name>TXERR</name>
52284 <description>Transaction error</description>
52285 <bitOffset>7</bitOffset>
52286 <bitWidth>1</bitWidth>
52287 </field>
52288 <field>
52289 <name>BBERR</name>
52290 <description>Babble error</description>
52291 <bitOffset>8</bitOffset>
52292 <bitWidth>1</bitWidth>
52293 </field>
52294 <field>
52295 <name>FRMOR</name>
52296 <description>Frame overrun</description>
52297 <bitOffset>9</bitOffset>
52298 <bitWidth>1</bitWidth>
52299 </field>
52300 <field>
52301 <name>DTERR</name>
52302 <description>Data toggle error</description>
52303 <bitOffset>10</bitOffset>
52304 <bitWidth>1</bitWidth>
52305 </field>
52306 </fields>
52307 </register>
52308 <register>
52309 <name>OTG_FS_HCINT6</name>
52310 <displayName>OTG_FS_HCINT6</displayName>
52311 <description>OTG_FS host channel-6 interrupt register
52312 (OTG_FS_HCINT6)</description>
52313 <addressOffset>0x1C8</addressOffset>
52314 <size>0x20</size>
52315 <access>read-write</access>
52316 <resetValue>0x00000000</resetValue>
52317 <fields>
52318 <field>
52319 <name>XFRC</name>
52320 <description>Transfer completed</description>
52321 <bitOffset>0</bitOffset>
52322 <bitWidth>1</bitWidth>
52323 </field>
52324 <field>
52325 <name>CHH</name>
52326 <description>Channel halted</description>
52327 <bitOffset>1</bitOffset>
52328 <bitWidth>1</bitWidth>
52329 </field>
52330 <field>
52331 <name>STALL</name>
52332 <description>STALL response received
52333 interrupt</description>
52334 <bitOffset>3</bitOffset>
52335 <bitWidth>1</bitWidth>
52336 </field>
52337 <field>
52338 <name>NAK</name>
52339 <description>NAK response received
52340 interrupt</description>
52341 <bitOffset>4</bitOffset>
52342 <bitWidth>1</bitWidth>
52343 </field>
52344 <field>
52345 <name>ACK</name>
52346 <description>ACK response received/transmitted
52347 interrupt</description>
52348 <bitOffset>5</bitOffset>
52349 <bitWidth>1</bitWidth>
52350 </field>
52351 <field>
52352 <name>TXERR</name>
52353 <description>Transaction error</description>
52354 <bitOffset>7</bitOffset>
52355 <bitWidth>1</bitWidth>
52356 </field>
52357 <field>
52358 <name>BBERR</name>
52359 <description>Babble error</description>
52360 <bitOffset>8</bitOffset>
52361 <bitWidth>1</bitWidth>
52362 </field>
52363 <field>
52364 <name>FRMOR</name>
52365 <description>Frame overrun</description>
52366 <bitOffset>9</bitOffset>
52367 <bitWidth>1</bitWidth>
52368 </field>
52369 <field>
52370 <name>DTERR</name>
52371 <description>Data toggle error</description>
52372 <bitOffset>10</bitOffset>
52373 <bitWidth>1</bitWidth>
52374 </field>
52375 </fields>
52376 </register>
52377 <register>
52378 <name>OTG_FS_HCINT7</name>
52379 <displayName>OTG_FS_HCINT7</displayName>
52380 <description>OTG_FS host channel-7 interrupt register
52381 (OTG_FS_HCINT7)</description>
52382 <addressOffset>0x1E8</addressOffset>
52383 <size>0x20</size>
52384 <access>read-write</access>
52385 <resetValue>0x00000000</resetValue>
52386 <fields>
52387 <field>
52388 <name>XFRC</name>
52389 <description>Transfer completed</description>
52390 <bitOffset>0</bitOffset>
52391 <bitWidth>1</bitWidth>
52392 </field>
52393 <field>
52394 <name>CHH</name>
52395 <description>Channel halted</description>
52396 <bitOffset>1</bitOffset>
52397 <bitWidth>1</bitWidth>
52398 </field>
52399 <field>
52400 <name>STALL</name>
52401 <description>STALL response received
52402 interrupt</description>
52403 <bitOffset>3</bitOffset>
52404 <bitWidth>1</bitWidth>
52405 </field>
52406 <field>
52407 <name>NAK</name>
52408 <description>NAK response received
52409 interrupt</description>
52410 <bitOffset>4</bitOffset>
52411 <bitWidth>1</bitWidth>
52412 </field>
52413 <field>
52414 <name>ACK</name>
52415 <description>ACK response received/transmitted
52416 interrupt</description>
52417 <bitOffset>5</bitOffset>
52418 <bitWidth>1</bitWidth>
52419 </field>
52420 <field>
52421 <name>TXERR</name>
52422 <description>Transaction error</description>
52423 <bitOffset>7</bitOffset>
52424 <bitWidth>1</bitWidth>
52425 </field>
52426 <field>
52427 <name>BBERR</name>
52428 <description>Babble error</description>
52429 <bitOffset>8</bitOffset>
52430 <bitWidth>1</bitWidth>
52431 </field>
52432 <field>
52433 <name>FRMOR</name>
52434 <description>Frame overrun</description>
52435 <bitOffset>9</bitOffset>
52436 <bitWidth>1</bitWidth>
52437 </field>
52438 <field>
52439 <name>DTERR</name>
52440 <description>Data toggle error</description>
52441 <bitOffset>10</bitOffset>
52442 <bitWidth>1</bitWidth>
52443 </field>
52444 </fields>
52445 </register>
52446 <register>
52447 <name>OTG_FS_HCINTMSK0</name>
52448 <displayName>OTG_FS_HCINTMSK0</displayName>
52449 <description>OTG_FS host channel-0 mask register
52450 (OTG_FS_HCINTMSK0)</description>
52451 <addressOffset>0x10C</addressOffset>
52452 <size>0x20</size>
52453 <access>read-write</access>
52454 <resetValue>0x00000000</resetValue>
52455 <fields>
52456 <field>
52457 <name>XFRCM</name>
52458 <description>Transfer completed mask</description>
52459 <bitOffset>0</bitOffset>
52460 <bitWidth>1</bitWidth>
52461 </field>
52462 <field>
52463 <name>CHHM</name>
52464 <description>Channel halted mask</description>
52465 <bitOffset>1</bitOffset>
52466 <bitWidth>1</bitWidth>
52467 </field>
52468 <field>
52469 <name>STALLM</name>
52470 <description>STALL response received interrupt
52471 mask</description>
52472 <bitOffset>3</bitOffset>
52473 <bitWidth>1</bitWidth>
52474 </field>
52475 <field>
52476 <name>NAKM</name>
52477 <description>NAK response received interrupt
52478 mask</description>
52479 <bitOffset>4</bitOffset>
52480 <bitWidth>1</bitWidth>
52481 </field>
52482 <field>
52483 <name>ACKM</name>
52484 <description>ACK response received/transmitted
52485 interrupt mask</description>
52486 <bitOffset>5</bitOffset>
52487 <bitWidth>1</bitWidth>
52488 </field>
52489 <field>
52490 <name>NYET</name>
52491 <description>response received interrupt
52492 mask</description>
52493 <bitOffset>6</bitOffset>
52494 <bitWidth>1</bitWidth>
52495 </field>
52496 <field>
52497 <name>TXERRM</name>
52498 <description>Transaction error mask</description>
52499 <bitOffset>7</bitOffset>
52500 <bitWidth>1</bitWidth>
52501 </field>
52502 <field>
52503 <name>BBERRM</name>
52504 <description>Babble error mask</description>
52505 <bitOffset>8</bitOffset>
52506 <bitWidth>1</bitWidth>
52507 </field>
52508 <field>
52509 <name>FRMORM</name>
52510 <description>Frame overrun mask</description>
52511 <bitOffset>9</bitOffset>
52512 <bitWidth>1</bitWidth>
52513 </field>
52514 <field>
52515 <name>DTERRM</name>
52516 <description>Data toggle error mask</description>
52517 <bitOffset>10</bitOffset>
52518 <bitWidth>1</bitWidth>
52519 </field>
52520 </fields>
52521 </register>
52522 <register>
52523 <name>OTG_FS_HCINTMSK1</name>
52524 <displayName>OTG_FS_HCINTMSK1</displayName>
52525 <description>OTG_FS host channel-1 mask register
52526 (OTG_FS_HCINTMSK1)</description>
52527 <addressOffset>0x12C</addressOffset>
52528 <size>0x20</size>
52529 <access>read-write</access>
52530 <resetValue>0x00000000</resetValue>
52531 <fields>
52532 <field>
52533 <name>XFRCM</name>
52534 <description>Transfer completed mask</description>
52535 <bitOffset>0</bitOffset>
52536 <bitWidth>1</bitWidth>
52537 </field>
52538 <field>
52539 <name>CHHM</name>
52540 <description>Channel halted mask</description>
52541 <bitOffset>1</bitOffset>
52542 <bitWidth>1</bitWidth>
52543 </field>
52544 <field>
52545 <name>STALLM</name>
52546 <description>STALL response received interrupt
52547 mask</description>
52548 <bitOffset>3</bitOffset>
52549 <bitWidth>1</bitWidth>
52550 </field>
52551 <field>
52552 <name>NAKM</name>
52553 <description>NAK response received interrupt
52554 mask</description>
52555 <bitOffset>4</bitOffset>
52556 <bitWidth>1</bitWidth>
52557 </field>
52558 <field>
52559 <name>ACKM</name>
52560 <description>ACK response received/transmitted
52561 interrupt mask</description>
52562 <bitOffset>5</bitOffset>
52563 <bitWidth>1</bitWidth>
52564 </field>
52565 <field>
52566 <name>NYET</name>
52567 <description>response received interrupt
52568 mask</description>
52569 <bitOffset>6</bitOffset>
52570 <bitWidth>1</bitWidth>
52571 </field>
52572 <field>
52573 <name>TXERRM</name>
52574 <description>Transaction error mask</description>
52575 <bitOffset>7</bitOffset>
52576 <bitWidth>1</bitWidth>
52577 </field>
52578 <field>
52579 <name>BBERRM</name>
52580 <description>Babble error mask</description>
52581 <bitOffset>8</bitOffset>
52582 <bitWidth>1</bitWidth>
52583 </field>
52584 <field>
52585 <name>FRMORM</name>
52586 <description>Frame overrun mask</description>
52587 <bitOffset>9</bitOffset>
52588 <bitWidth>1</bitWidth>
52589 </field>
52590 <field>
52591 <name>DTERRM</name>
52592 <description>Data toggle error mask</description>
52593 <bitOffset>10</bitOffset>
52594 <bitWidth>1</bitWidth>
52595 </field>
52596 </fields>
52597 </register>
52598 <register>
52599 <name>OTG_FS_HCINTMSK2</name>
52600 <displayName>OTG_FS_HCINTMSK2</displayName>
52601 <description>OTG_FS host channel-2 mask register
52602 (OTG_FS_HCINTMSK2)</description>
52603 <addressOffset>0x14C</addressOffset>
52604 <size>0x20</size>
52605 <access>read-write</access>
52606 <resetValue>0x00000000</resetValue>
52607 <fields>
52608 <field>
52609 <name>XFRCM</name>
52610 <description>Transfer completed mask</description>
52611 <bitOffset>0</bitOffset>
52612 <bitWidth>1</bitWidth>
52613 </field>
52614 <field>
52615 <name>CHHM</name>
52616 <description>Channel halted mask</description>
52617 <bitOffset>1</bitOffset>
52618 <bitWidth>1</bitWidth>
52619 </field>
52620 <field>
52621 <name>STALLM</name>
52622 <description>STALL response received interrupt
52623 mask</description>
52624 <bitOffset>3</bitOffset>
52625 <bitWidth>1</bitWidth>
52626 </field>
52627 <field>
52628 <name>NAKM</name>
52629 <description>NAK response received interrupt
52630 mask</description>
52631 <bitOffset>4</bitOffset>
52632 <bitWidth>1</bitWidth>
52633 </field>
52634 <field>
52635 <name>ACKM</name>
52636 <description>ACK response received/transmitted
52637 interrupt mask</description>
52638 <bitOffset>5</bitOffset>
52639 <bitWidth>1</bitWidth>
52640 </field>
52641 <field>
52642 <name>NYET</name>
52643 <description>response received interrupt
52644 mask</description>
52645 <bitOffset>6</bitOffset>
52646 <bitWidth>1</bitWidth>
52647 </field>
52648 <field>
52649 <name>TXERRM</name>
52650 <description>Transaction error mask</description>
52651 <bitOffset>7</bitOffset>
52652 <bitWidth>1</bitWidth>
52653 </field>
52654 <field>
52655 <name>BBERRM</name>
52656 <description>Babble error mask</description>
52657 <bitOffset>8</bitOffset>
52658 <bitWidth>1</bitWidth>
52659 </field>
52660 <field>
52661 <name>FRMORM</name>
52662 <description>Frame overrun mask</description>
52663 <bitOffset>9</bitOffset>
52664 <bitWidth>1</bitWidth>
52665 </field>
52666 <field>
52667 <name>DTERRM</name>
52668 <description>Data toggle error mask</description>
52669 <bitOffset>10</bitOffset>
52670 <bitWidth>1</bitWidth>
52671 </field>
52672 </fields>
52673 </register>
52674 <register>
52675 <name>OTG_FS_HCINTMSK3</name>
52676 <displayName>OTG_FS_HCINTMSK3</displayName>
52677 <description>OTG_FS host channel-3 mask register
52678 (OTG_FS_HCINTMSK3)</description>
52679 <addressOffset>0x16C</addressOffset>
52680 <size>0x20</size>
52681 <access>read-write</access>
52682 <resetValue>0x00000000</resetValue>
52683 <fields>
52684 <field>
52685 <name>XFRCM</name>
52686 <description>Transfer completed mask</description>
52687 <bitOffset>0</bitOffset>
52688 <bitWidth>1</bitWidth>
52689 </field>
52690 <field>
52691 <name>CHHM</name>
52692 <description>Channel halted mask</description>
52693 <bitOffset>1</bitOffset>
52694 <bitWidth>1</bitWidth>
52695 </field>
52696 <field>
52697 <name>STALLM</name>
52698 <description>STALL response received interrupt
52699 mask</description>
52700 <bitOffset>3</bitOffset>
52701 <bitWidth>1</bitWidth>
52702 </field>
52703 <field>
52704 <name>NAKM</name>
52705 <description>NAK response received interrupt
52706 mask</description>
52707 <bitOffset>4</bitOffset>
52708 <bitWidth>1</bitWidth>
52709 </field>
52710 <field>
52711 <name>ACKM</name>
52712 <description>ACK response received/transmitted
52713 interrupt mask</description>
52714 <bitOffset>5</bitOffset>
52715 <bitWidth>1</bitWidth>
52716 </field>
52717 <field>
52718 <name>NYET</name>
52719 <description>response received interrupt
52720 mask</description>
52721 <bitOffset>6</bitOffset>
52722 <bitWidth>1</bitWidth>
52723 </field>
52724 <field>
52725 <name>TXERRM</name>
52726 <description>Transaction error mask</description>
52727 <bitOffset>7</bitOffset>
52728 <bitWidth>1</bitWidth>
52729 </field>
52730 <field>
52731 <name>BBERRM</name>
52732 <description>Babble error mask</description>
52733 <bitOffset>8</bitOffset>
52734 <bitWidth>1</bitWidth>
52735 </field>
52736 <field>
52737 <name>FRMORM</name>
52738 <description>Frame overrun mask</description>
52739 <bitOffset>9</bitOffset>
52740 <bitWidth>1</bitWidth>
52741 </field>
52742 <field>
52743 <name>DTERRM</name>
52744 <description>Data toggle error mask</description>
52745 <bitOffset>10</bitOffset>
52746 <bitWidth>1</bitWidth>
52747 </field>
52748 </fields>
52749 </register>
52750 <register>
52751 <name>OTG_FS_HCINTMSK4</name>
52752 <displayName>OTG_FS_HCINTMSK4</displayName>
52753 <description>OTG_FS host channel-4 mask register
52754 (OTG_FS_HCINTMSK4)</description>
52755 <addressOffset>0x18C</addressOffset>
52756 <size>0x20</size>
52757 <access>read-write</access>
52758 <resetValue>0x00000000</resetValue>
52759 <fields>
52760 <field>
52761 <name>XFRCM</name>
52762 <description>Transfer completed mask</description>
52763 <bitOffset>0</bitOffset>
52764 <bitWidth>1</bitWidth>
52765 </field>
52766 <field>
52767 <name>CHHM</name>
52768 <description>Channel halted mask</description>
52769 <bitOffset>1</bitOffset>
52770 <bitWidth>1</bitWidth>
52771 </field>
52772 <field>
52773 <name>STALLM</name>
52774 <description>STALL response received interrupt
52775 mask</description>
52776 <bitOffset>3</bitOffset>
52777 <bitWidth>1</bitWidth>
52778 </field>
52779 <field>
52780 <name>NAKM</name>
52781 <description>NAK response received interrupt
52782 mask</description>
52783 <bitOffset>4</bitOffset>
52784 <bitWidth>1</bitWidth>
52785 </field>
52786 <field>
52787 <name>ACKM</name>
52788 <description>ACK response received/transmitted
52789 interrupt mask</description>
52790 <bitOffset>5</bitOffset>
52791 <bitWidth>1</bitWidth>
52792 </field>
52793 <field>
52794 <name>NYET</name>
52795 <description>response received interrupt
52796 mask</description>
52797 <bitOffset>6</bitOffset>
52798 <bitWidth>1</bitWidth>
52799 </field>
52800 <field>
52801 <name>TXERRM</name>
52802 <description>Transaction error mask</description>
52803 <bitOffset>7</bitOffset>
52804 <bitWidth>1</bitWidth>
52805 </field>
52806 <field>
52807 <name>BBERRM</name>
52808 <description>Babble error mask</description>
52809 <bitOffset>8</bitOffset>
52810 <bitWidth>1</bitWidth>
52811 </field>
52812 <field>
52813 <name>FRMORM</name>
52814 <description>Frame overrun mask</description>
52815 <bitOffset>9</bitOffset>
52816 <bitWidth>1</bitWidth>
52817 </field>
52818 <field>
52819 <name>DTERRM</name>
52820 <description>Data toggle error mask</description>
52821 <bitOffset>10</bitOffset>
52822 <bitWidth>1</bitWidth>
52823 </field>
52824 </fields>
52825 </register>
52826 <register>
52827 <name>OTG_FS_HCINTMSK5</name>
52828 <displayName>OTG_FS_HCINTMSK5</displayName>
52829 <description>OTG_FS host channel-5 mask register
52830 (OTG_FS_HCINTMSK5)</description>
52831 <addressOffset>0x1AC</addressOffset>
52832 <size>0x20</size>
52833 <access>read-write</access>
52834 <resetValue>0x00000000</resetValue>
52835 <fields>
52836 <field>
52837 <name>XFRCM</name>
52838 <description>Transfer completed mask</description>
52839 <bitOffset>0</bitOffset>
52840 <bitWidth>1</bitWidth>
52841 </field>
52842 <field>
52843 <name>CHHM</name>
52844 <description>Channel halted mask</description>
52845 <bitOffset>1</bitOffset>
52846 <bitWidth>1</bitWidth>
52847 </field>
52848 <field>
52849 <name>STALLM</name>
52850 <description>STALL response received interrupt
52851 mask</description>
52852 <bitOffset>3</bitOffset>
52853 <bitWidth>1</bitWidth>
52854 </field>
52855 <field>
52856 <name>NAKM</name>
52857 <description>NAK response received interrupt
52858 mask</description>
52859 <bitOffset>4</bitOffset>
52860 <bitWidth>1</bitWidth>
52861 </field>
52862 <field>
52863 <name>ACKM</name>
52864 <description>ACK response received/transmitted
52865 interrupt mask</description>
52866 <bitOffset>5</bitOffset>
52867 <bitWidth>1</bitWidth>
52868 </field>
52869 <field>
52870 <name>NYET</name>
52871 <description>response received interrupt
52872 mask</description>
52873 <bitOffset>6</bitOffset>
52874 <bitWidth>1</bitWidth>
52875 </field>
52876 <field>
52877 <name>TXERRM</name>
52878 <description>Transaction error mask</description>
52879 <bitOffset>7</bitOffset>
52880 <bitWidth>1</bitWidth>
52881 </field>
52882 <field>
52883 <name>BBERRM</name>
52884 <description>Babble error mask</description>
52885 <bitOffset>8</bitOffset>
52886 <bitWidth>1</bitWidth>
52887 </field>
52888 <field>
52889 <name>FRMORM</name>
52890 <description>Frame overrun mask</description>
52891 <bitOffset>9</bitOffset>
52892 <bitWidth>1</bitWidth>
52893 </field>
52894 <field>
52895 <name>DTERRM</name>
52896 <description>Data toggle error mask</description>
52897 <bitOffset>10</bitOffset>
52898 <bitWidth>1</bitWidth>
52899 </field>
52900 </fields>
52901 </register>
52902 <register>
52903 <name>OTG_FS_HCINTMSK6</name>
52904 <displayName>OTG_FS_HCINTMSK6</displayName>
52905 <description>OTG_FS host channel-6 mask register
52906 (OTG_FS_HCINTMSK6)</description>
52907 <addressOffset>0x1CC</addressOffset>
52908 <size>0x20</size>
52909 <access>read-write</access>
52910 <resetValue>0x00000000</resetValue>
52911 <fields>
52912 <field>
52913 <name>XFRCM</name>
52914 <description>Transfer completed mask</description>
52915 <bitOffset>0</bitOffset>
52916 <bitWidth>1</bitWidth>
52917 </field>
52918 <field>
52919 <name>CHHM</name>
52920 <description>Channel halted mask</description>
52921 <bitOffset>1</bitOffset>
52922 <bitWidth>1</bitWidth>
52923 </field>
52924 <field>
52925 <name>STALLM</name>
52926 <description>STALL response received interrupt
52927 mask</description>
52928 <bitOffset>3</bitOffset>
52929 <bitWidth>1</bitWidth>
52930 </field>
52931 <field>
52932 <name>NAKM</name>
52933 <description>NAK response received interrupt
52934 mask</description>
52935 <bitOffset>4</bitOffset>
52936 <bitWidth>1</bitWidth>
52937 </field>
52938 <field>
52939 <name>ACKM</name>
52940 <description>ACK response received/transmitted
52941 interrupt mask</description>
52942 <bitOffset>5</bitOffset>
52943 <bitWidth>1</bitWidth>
52944 </field>
52945 <field>
52946 <name>NYET</name>
52947 <description>response received interrupt
52948 mask</description>
52949 <bitOffset>6</bitOffset>
52950 <bitWidth>1</bitWidth>
52951 </field>
52952 <field>
52953 <name>TXERRM</name>
52954 <description>Transaction error mask</description>
52955 <bitOffset>7</bitOffset>
52956 <bitWidth>1</bitWidth>
52957 </field>
52958 <field>
52959 <name>BBERRM</name>
52960 <description>Babble error mask</description>
52961 <bitOffset>8</bitOffset>
52962 <bitWidth>1</bitWidth>
52963 </field>
52964 <field>
52965 <name>FRMORM</name>
52966 <description>Frame overrun mask</description>
52967 <bitOffset>9</bitOffset>
52968 <bitWidth>1</bitWidth>
52969 </field>
52970 <field>
52971 <name>DTERRM</name>
52972 <description>Data toggle error mask</description>
52973 <bitOffset>10</bitOffset>
52974 <bitWidth>1</bitWidth>
52975 </field>
52976 </fields>
52977 </register>
52978 <register>
52979 <name>OTG_FS_HCINTMSK7</name>
52980 <displayName>OTG_FS_HCINTMSK7</displayName>
52981 <description>OTG_FS host channel-7 mask register
52982 (OTG_FS_HCINTMSK7)</description>
52983 <addressOffset>0x1EC</addressOffset>
52984 <size>0x20</size>
52985 <access>read-write</access>
52986 <resetValue>0x00000000</resetValue>
52987 <fields>
52988 <field>
52989 <name>XFRCM</name>
52990 <description>Transfer completed mask</description>
52991 <bitOffset>0</bitOffset>
52992 <bitWidth>1</bitWidth>
52993 </field>
52994 <field>
52995 <name>CHHM</name>
52996 <description>Channel halted mask</description>
52997 <bitOffset>1</bitOffset>
52998 <bitWidth>1</bitWidth>
52999 </field>
53000 <field>
53001 <name>STALLM</name>
53002 <description>STALL response received interrupt
53003 mask</description>
53004 <bitOffset>3</bitOffset>
53005 <bitWidth>1</bitWidth>
53006 </field>
53007 <field>
53008 <name>NAKM</name>
53009 <description>NAK response received interrupt
53010 mask</description>
53011 <bitOffset>4</bitOffset>
53012 <bitWidth>1</bitWidth>
53013 </field>
53014 <field>
53015 <name>ACKM</name>
53016 <description>ACK response received/transmitted
53017 interrupt mask</description>
53018 <bitOffset>5</bitOffset>
53019 <bitWidth>1</bitWidth>
53020 </field>
53021 <field>
53022 <name>NYET</name>
53023 <description>response received interrupt
53024 mask</description>
53025 <bitOffset>6</bitOffset>
53026 <bitWidth>1</bitWidth>
53027 </field>
53028 <field>
53029 <name>TXERRM</name>
53030 <description>Transaction error mask</description>
53031 <bitOffset>7</bitOffset>
53032 <bitWidth>1</bitWidth>
53033 </field>
53034 <field>
53035 <name>BBERRM</name>
53036 <description>Babble error mask</description>
53037 <bitOffset>8</bitOffset>
53038 <bitWidth>1</bitWidth>
53039 </field>
53040 <field>
53041 <name>FRMORM</name>
53042 <description>Frame overrun mask</description>
53043 <bitOffset>9</bitOffset>
53044 <bitWidth>1</bitWidth>
53045 </field>
53046 <field>
53047 <name>DTERRM</name>
53048 <description>Data toggle error mask</description>
53049 <bitOffset>10</bitOffset>
53050 <bitWidth>1</bitWidth>
53051 </field>
53052 </fields>
53053 </register>
53054 <register>
53055 <name>OTG_FS_HCTSIZ0</name>
53056 <displayName>OTG_FS_HCTSIZ0</displayName>
53057 <description>OTG_FS host channel-0 transfer size
53058 register</description>
53059 <addressOffset>0x110</addressOffset>
53060 <size>0x20</size>
53061 <access>read-write</access>
53062 <resetValue>0x00000000</resetValue>
53063 <fields>
53064 <field>
53065 <name>XFRSIZ</name>
53066 <description>Transfer size</description>
53067 <bitOffset>0</bitOffset>
53068 <bitWidth>19</bitWidth>
53069 </field>
53070 <field>
53071 <name>PKTCNT</name>
53072 <description>Packet count</description>
53073 <bitOffset>19</bitOffset>
53074 <bitWidth>10</bitWidth>
53075 </field>
53076 <field>
53077 <name>DPID</name>
53078 <description>Data PID</description>
53079 <bitOffset>29</bitOffset>
53080 <bitWidth>2</bitWidth>
53081 </field>
53082 </fields>
53083 </register>
53084 <register>
53085 <name>OTG_FS_HCTSIZ1</name>
53086 <displayName>OTG_FS_HCTSIZ1</displayName>
53087 <description>OTG_FS host channel-1 transfer size
53088 register</description>
53089 <addressOffset>0x130</addressOffset>
53090 <size>0x20</size>
53091 <access>read-write</access>
53092 <resetValue>0x00000000</resetValue>
53093 <fields>
53094 <field>
53095 <name>XFRSIZ</name>
53096 <description>Transfer size</description>
53097 <bitOffset>0</bitOffset>
53098 <bitWidth>19</bitWidth>
53099 </field>
53100 <field>
53101 <name>PKTCNT</name>
53102 <description>Packet count</description>
53103 <bitOffset>19</bitOffset>
53104 <bitWidth>10</bitWidth>
53105 </field>
53106 <field>
53107 <name>DPID</name>
53108 <description>Data PID</description>
53109 <bitOffset>29</bitOffset>
53110 <bitWidth>2</bitWidth>
53111 </field>
53112 </fields>
53113 </register>
53114 <register>
53115 <name>OTG_FS_HCTSIZ2</name>
53116 <displayName>OTG_FS_HCTSIZ2</displayName>
53117 <description>OTG_FS host channel-2 transfer size
53118 register</description>
53119 <addressOffset>0x150</addressOffset>
53120 <size>0x20</size>
53121 <access>read-write</access>
53122 <resetValue>0x00000000</resetValue>
53123 <fields>
53124 <field>
53125 <name>XFRSIZ</name>
53126 <description>Transfer size</description>
53127 <bitOffset>0</bitOffset>
53128 <bitWidth>19</bitWidth>
53129 </field>
53130 <field>
53131 <name>PKTCNT</name>
53132 <description>Packet count</description>
53133 <bitOffset>19</bitOffset>
53134 <bitWidth>10</bitWidth>
53135 </field>
53136 <field>
53137 <name>DPID</name>
53138 <description>Data PID</description>
53139 <bitOffset>29</bitOffset>
53140 <bitWidth>2</bitWidth>
53141 </field>
53142 </fields>
53143 </register>
53144 <register>
53145 <name>OTG_FS_HCTSIZ3</name>
53146 <displayName>OTG_FS_HCTSIZ3</displayName>
53147 <description>OTG_FS host channel-3 transfer size
53148 register</description>
53149 <addressOffset>0x170</addressOffset>
53150 <size>0x20</size>
53151 <access>read-write</access>
53152 <resetValue>0x00000000</resetValue>
53153 <fields>
53154 <field>
53155 <name>XFRSIZ</name>
53156 <description>Transfer size</description>
53157 <bitOffset>0</bitOffset>
53158 <bitWidth>19</bitWidth>
53159 </field>
53160 <field>
53161 <name>PKTCNT</name>
53162 <description>Packet count</description>
53163 <bitOffset>19</bitOffset>
53164 <bitWidth>10</bitWidth>
53165 </field>
53166 <field>
53167 <name>DPID</name>
53168 <description>Data PID</description>
53169 <bitOffset>29</bitOffset>
53170 <bitWidth>2</bitWidth>
53171 </field>
53172 </fields>
53173 </register>
53174 <register>
53175 <name>OTG_FS_HCTSIZ4</name>
53176 <displayName>OTG_FS_HCTSIZ4</displayName>
53177 <description>OTG_FS host channel-x transfer size
53178 register</description>
53179 <addressOffset>0x190</addressOffset>
53180 <size>0x20</size>
53181 <access>read-write</access>
53182 <resetValue>0x00000000</resetValue>
53183 <fields>
53184 <field>
53185 <name>XFRSIZ</name>
53186 <description>Transfer size</description>
53187 <bitOffset>0</bitOffset>
53188 <bitWidth>19</bitWidth>
53189 </field>
53190 <field>
53191 <name>PKTCNT</name>
53192 <description>Packet count</description>
53193 <bitOffset>19</bitOffset>
53194 <bitWidth>10</bitWidth>
53195 </field>
53196 <field>
53197 <name>DPID</name>
53198 <description>Data PID</description>
53199 <bitOffset>29</bitOffset>
53200 <bitWidth>2</bitWidth>
53201 </field>
53202 </fields>
53203 </register>
53204 <register>
53205 <name>OTG_FS_HCTSIZ5</name>
53206 <displayName>OTG_FS_HCTSIZ5</displayName>
53207 <description>OTG_FS host channel-5 transfer size
53208 register</description>
53209 <addressOffset>0x1B0</addressOffset>
53210 <size>0x20</size>
53211 <access>read-write</access>
53212 <resetValue>0x00000000</resetValue>
53213 <fields>
53214 <field>
53215 <name>XFRSIZ</name>
53216 <description>Transfer size</description>
53217 <bitOffset>0</bitOffset>
53218 <bitWidth>19</bitWidth>
53219 </field>
53220 <field>
53221 <name>PKTCNT</name>
53222 <description>Packet count</description>
53223 <bitOffset>19</bitOffset>
53224 <bitWidth>10</bitWidth>
53225 </field>
53226 <field>
53227 <name>DPID</name>
53228 <description>Data PID</description>
53229 <bitOffset>29</bitOffset>
53230 <bitWidth>2</bitWidth>
53231 </field>
53232 </fields>
53233 </register>
53234 <register>
53235 <name>OTG_FS_HCTSIZ6</name>
53236 <displayName>OTG_FS_HCTSIZ6</displayName>
53237 <description>OTG_FS host channel-6 transfer size
53238 register</description>
53239 <addressOffset>0x1D0</addressOffset>
53240 <size>0x20</size>
53241 <access>read-write</access>
53242 <resetValue>0x00000000</resetValue>
53243 <fields>
53244 <field>
53245 <name>XFRSIZ</name>
53246 <description>Transfer size</description>
53247 <bitOffset>0</bitOffset>
53248 <bitWidth>19</bitWidth>
53249 </field>
53250 <field>
53251 <name>PKTCNT</name>
53252 <description>Packet count</description>
53253 <bitOffset>19</bitOffset>
53254 <bitWidth>10</bitWidth>
53255 </field>
53256 <field>
53257 <name>DPID</name>
53258 <description>Data PID</description>
53259 <bitOffset>29</bitOffset>
53260 <bitWidth>2</bitWidth>
53261 </field>
53262 </fields>
53263 </register>
53264 <register>
53265 <name>OTG_FS_HCTSIZ7</name>
53266 <displayName>OTG_FS_HCTSIZ7</displayName>
53267 <description>OTG_FS host channel-7 transfer size
53268 register</description>
53269 <addressOffset>0x1F0</addressOffset>
53270 <size>0x20</size>
53271 <access>read-write</access>
53272 <resetValue>0x00000000</resetValue>
53273 <fields>
53274 <field>
53275 <name>XFRSIZ</name>
53276 <description>Transfer size</description>
53277 <bitOffset>0</bitOffset>
53278 <bitWidth>19</bitWidth>
53279 </field>
53280 <field>
53281 <name>PKTCNT</name>
53282 <description>Packet count</description>
53283 <bitOffset>19</bitOffset>
53284 <bitWidth>10</bitWidth>
53285 </field>
53286 <field>
53287 <name>DPID</name>
53288 <description>Data PID</description>
53289 <bitOffset>29</bitOffset>
53290 <bitWidth>2</bitWidth>
53291 </field>
53292 </fields>
53293 </register>
53294 <register>
53295 <name>OTG_FS_HCCHAR8</name>
53296 <displayName>OTG_FS_HCCHAR8</displayName>
53297 <description>OTG_FS host channel-8 characteristics
53298 register</description>
53299 <addressOffset>0x1F4</addressOffset>
53300 <size>0x20</size>
53301 <access>read-write</access>
53302 <resetValue>0x00000000</resetValue>
53303 <fields>
53304 <field>
53305 <name>MPSIZ</name>
53306 <description>Maximum packet size</description>
53307 <bitOffset>0</bitOffset>
53308 <bitWidth>11</bitWidth>
53309 </field>
53310 <field>
53311 <name>EPNUM</name>
53312 <description>Endpoint number</description>
53313 <bitOffset>11</bitOffset>
53314 <bitWidth>4</bitWidth>
53315 </field>
53316 <field>
53317 <name>EPDIR</name>
53318 <description>Endpoint direction</description>
53319 <bitOffset>15</bitOffset>
53320 <bitWidth>1</bitWidth>
53321 </field>
53322 <field>
53323 <name>LSDEV</name>
53324 <description>Low-speed device</description>
53325 <bitOffset>17</bitOffset>
53326 <bitWidth>1</bitWidth>
53327 </field>
53328 <field>
53329 <name>EPTYP</name>
53330 <description>Endpoint type</description>
53331 <bitOffset>18</bitOffset>
53332 <bitWidth>2</bitWidth>
53333 </field>
53334 <field>
53335 <name>MCNT</name>
53336 <description>Multicount</description>
53337 <bitOffset>20</bitOffset>
53338 <bitWidth>2</bitWidth>
53339 </field>
53340 <field>
53341 <name>DAD</name>
53342 <description>Device address</description>
53343 <bitOffset>22</bitOffset>
53344 <bitWidth>7</bitWidth>
53345 </field>
53346 <field>
53347 <name>ODDFRM</name>
53348 <description>Odd frame</description>
53349 <bitOffset>29</bitOffset>
53350 <bitWidth>1</bitWidth>
53351 </field>
53352 <field>
53353 <name>CHDIS</name>
53354 <description>Channel disable</description>
53355 <bitOffset>30</bitOffset>
53356 <bitWidth>1</bitWidth>
53357 </field>
53358 <field>
53359 <name>CHENA</name>
53360 <description>Channel enable</description>
53361 <bitOffset>31</bitOffset>
53362 <bitWidth>1</bitWidth>
53363 </field>
53364 </fields>
53365 </register>
53366 <register>
53367 <name>OTG_FS_HCINT8</name>
53368 <displayName>OTG_FS_HCINT8</displayName>
53369 <description>OTG_FS host channel-8 interrupt
53370 register</description>
53371 <addressOffset>0x1F8</addressOffset>
53372 <size>0x20</size>
53373 <access>read-write</access>
53374 <resetValue>0x00000000</resetValue>
53375 <fields>
53376 <field>
53377 <name>XFRC</name>
53378 <description>Transfer completed</description>
53379 <bitOffset>0</bitOffset>
53380 <bitWidth>1</bitWidth>
53381 </field>
53382 <field>
53383 <name>CHH</name>
53384 <description>Channel halted</description>
53385 <bitOffset>1</bitOffset>
53386 <bitWidth>1</bitWidth>
53387 </field>
53388 <field>
53389 <name>STALL</name>
53390 <description>STALL response received
53391 interrupt</description>
53392 <bitOffset>3</bitOffset>
53393 <bitWidth>1</bitWidth>
53394 </field>
53395 <field>
53396 <name>NAK</name>
53397 <description>NAK response received
53398 interrupt</description>
53399 <bitOffset>4</bitOffset>
53400 <bitWidth>1</bitWidth>
53401 </field>
53402 <field>
53403 <name>ACK</name>
53404 <description>ACK response received/transmitted
53405 interrupt</description>
53406 <bitOffset>5</bitOffset>
53407 <bitWidth>1</bitWidth>
53408 </field>
53409 <field>
53410 <name>TXERR</name>
53411 <description>Transaction error</description>
53412 <bitOffset>7</bitOffset>
53413 <bitWidth>1</bitWidth>
53414 </field>
53415 <field>
53416 <name>BBERR</name>
53417 <description>Babble error</description>
53418 <bitOffset>8</bitOffset>
53419 <bitWidth>1</bitWidth>
53420 </field>
53421 <field>
53422 <name>FRMOR</name>
53423 <description>Frame overrun</description>
53424 <bitOffset>9</bitOffset>
53425 <bitWidth>1</bitWidth>
53426 </field>
53427 <field>
53428 <name>DTERR</name>
53429 <description>Data toggle error</description>
53430 <bitOffset>10</bitOffset>
53431 <bitWidth>1</bitWidth>
53432 </field>
53433 </fields>
53434 </register>
53435 <register>
53436 <name>OTG_FS_HCINTMSK8</name>
53437 <displayName>OTG_FS_HCINTMSK8</displayName>
53438 <description>OTG_FS host channel-8 mask
53439 register</description>
53440 <addressOffset>0x1FC</addressOffset>
53441 <size>0x20</size>
53442 <access>read-write</access>
53443 <resetValue>0x00000000</resetValue>
53444 <fields>
53445 <field>
53446 <name>XFRCM</name>
53447 <description>Transfer completed mask</description>
53448 <bitOffset>0</bitOffset>
53449 <bitWidth>1</bitWidth>
53450 </field>
53451 <field>
53452 <name>CHHM</name>
53453 <description>Channel halted mask</description>
53454 <bitOffset>1</bitOffset>
53455 <bitWidth>1</bitWidth>
53456 </field>
53457 <field>
53458 <name>STALLM</name>
53459 <description>STALL response received interrupt
53460 mask</description>
53461 <bitOffset>3</bitOffset>
53462 <bitWidth>1</bitWidth>
53463 </field>
53464 <field>
53465 <name>NAKM</name>
53466 <description>NAK response received interrupt
53467 mask</description>
53468 <bitOffset>4</bitOffset>
53469 <bitWidth>1</bitWidth>
53470 </field>
53471 <field>
53472 <name>ACKM</name>
53473 <description>ACK response received/transmitted
53474 interrupt mask</description>
53475 <bitOffset>5</bitOffset>
53476 <bitWidth>1</bitWidth>
53477 </field>
53478 <field>
53479 <name>NYET</name>
53480 <description>response received interrupt
53481 mask</description>
53482 <bitOffset>6</bitOffset>
53483 <bitWidth>1</bitWidth>
53484 </field>
53485 <field>
53486 <name>TXERRM</name>
53487 <description>Transaction error</description>
53488 <bitOffset>7</bitOffset>
53489 <bitWidth>1</bitWidth>
53490 </field>
53491 <field>
53492 <name>BBERRM</name>
53493 <description>Babble error mask</description>
53494 <bitOffset>8</bitOffset>
53495 <bitWidth>1</bitWidth>
53496 </field>
53497 <field>
53498 <name>FRMORM</name>
53499 <description>Frame overrun mask</description>
53500 <bitOffset>9</bitOffset>
53501 <bitWidth>1</bitWidth>
53502 </field>
53503 <field>
53504 <name>DTERRM</name>
53505 <description>Data toggle error mask</description>
53506 <bitOffset>10</bitOffset>
53507 <bitWidth>1</bitWidth>
53508 </field>
53509 </fields>
53510 </register>
53511 <register>
53512 <name>OTG_FS_HCTSIZ8</name>
53513 <displayName>OTG_FS_HCTSIZ8</displayName>
53514 <description>OTG_FS host channel-8 transfer size
53515 register</description>
53516 <addressOffset>0x200</addressOffset>
53517 <size>0x20</size>
53518 <access>read-write</access>
53519 <resetValue>0x00000000</resetValue>
53520 <fields>
53521 <field>
53522 <name>XFRSIZ</name>
53523 <description>Transfer size</description>
53524 <bitOffset>0</bitOffset>
53525 <bitWidth>19</bitWidth>
53526 </field>
53527 <field>
53528 <name>PKTCNT</name>
53529 <description>Packet count</description>
53530 <bitOffset>19</bitOffset>
53531 <bitWidth>10</bitWidth>
53532 </field>
53533 <field>
53534 <name>DPID</name>
53535 <description>Data PID</description>
53536 <bitOffset>29</bitOffset>
53537 <bitWidth>2</bitWidth>
53538 </field>
53539 </fields>
53540 </register>
53541 <register>
53542 <name>OTG_FS_HCCHAR9</name>
53543 <displayName>OTG_FS_HCCHAR9</displayName>
53544 <description>OTG_FS host channel-9 characteristics
53545 register</description>
53546 <addressOffset>0x204</addressOffset>
53547 <size>0x20</size>
53548 <access>read-write</access>
53549 <resetValue>0x00000000</resetValue>
53550 <fields>
53551 <field>
53552 <name>MPSIZ</name>
53553 <description>Maximum packet size</description>
53554 <bitOffset>0</bitOffset>
53555 <bitWidth>11</bitWidth>
53556 </field>
53557 <field>
53558 <name>EPNUM</name>
53559 <description>Endpoint number</description>
53560 <bitOffset>11</bitOffset>
53561 <bitWidth>4</bitWidth>
53562 </field>
53563 <field>
53564 <name>EPDIR</name>
53565 <description>Endpoint direction</description>
53566 <bitOffset>15</bitOffset>
53567 <bitWidth>1</bitWidth>
53568 </field>
53569 <field>
53570 <name>LSDEV</name>
53571 <description>Low-speed device</description>
53572 <bitOffset>17</bitOffset>
53573 <bitWidth>1</bitWidth>
53574 </field>
53575 <field>
53576 <name>EPTYP</name>
53577 <description>Endpoint type</description>
53578 <bitOffset>18</bitOffset>
53579 <bitWidth>2</bitWidth>
53580 </field>
53581 <field>
53582 <name>MCNT</name>
53583 <description>Multicount</description>
53584 <bitOffset>20</bitOffset>
53585 <bitWidth>2</bitWidth>
53586 </field>
53587 <field>
53588 <name>DAD</name>
53589 <description>Device address</description>
53590 <bitOffset>22</bitOffset>
53591 <bitWidth>7</bitWidth>
53592 </field>
53593 <field>
53594 <name>ODDFRM</name>
53595 <description>Odd frame</description>
53596 <bitOffset>29</bitOffset>
53597 <bitWidth>1</bitWidth>
53598 </field>
53599 <field>
53600 <name>CHDIS</name>
53601 <description>Channel disable</description>
53602 <bitOffset>30</bitOffset>
53603 <bitWidth>1</bitWidth>
53604 </field>
53605 <field>
53606 <name>CHENA</name>
53607 <description>Channel enable</description>
53608 <bitOffset>31</bitOffset>
53609 <bitWidth>1</bitWidth>
53610 </field>
53611 </fields>
53612 </register>
53613 <register>
53614 <name>OTG_FS_HCINT9</name>
53615 <displayName>OTG_FS_HCINT9</displayName>
53616 <description>OTG_FS host channel-9 interrupt
53617 register</description>
53618 <addressOffset>0x208</addressOffset>
53619 <size>0x20</size>
53620 <access>read-write</access>
53621 <resetValue>0x00000000</resetValue>
53622 <fields>
53623 <field>
53624 <name>XFRC</name>
53625 <description>Transfer completed</description>
53626 <bitOffset>0</bitOffset>
53627 <bitWidth>1</bitWidth>
53628 </field>
53629 <field>
53630 <name>CHH</name>
53631 <description>Channel halted</description>
53632 <bitOffset>1</bitOffset>
53633 <bitWidth>1</bitWidth>
53634 </field>
53635 <field>
53636 <name>STALL</name>
53637 <description>STALL response received
53638 interrupt</description>
53639 <bitOffset>3</bitOffset>
53640 <bitWidth>1</bitWidth>
53641 </field>
53642 <field>
53643 <name>NAK</name>
53644 <description>NAK response received
53645 interrupt</description>
53646 <bitOffset>4</bitOffset>
53647 <bitWidth>1</bitWidth>
53648 </field>
53649 <field>
53650 <name>ACK</name>
53651 <description>ACK response received/transmitted
53652 interrupt</description>
53653 <bitOffset>5</bitOffset>
53654 <bitWidth>1</bitWidth>
53655 </field>
53656 <field>
53657 <name>TXERR</name>
53658 <description>Transaction error</description>
53659 <bitOffset>7</bitOffset>
53660 <bitWidth>1</bitWidth>
53661 </field>
53662 <field>
53663 <name>BBERR</name>
53664 <description>Babble error</description>
53665 <bitOffset>8</bitOffset>
53666 <bitWidth>1</bitWidth>
53667 </field>
53668 <field>
53669 <name>FRMOR</name>
53670 <description>Frame overrun</description>
53671 <bitOffset>9</bitOffset>
53672 <bitWidth>1</bitWidth>
53673 </field>
53674 <field>
53675 <name>DTERR</name>
53676 <description>Data toggle error</description>
53677 <bitOffset>10</bitOffset>
53678 <bitWidth>1</bitWidth>
53679 </field>
53680 </fields>
53681 </register>
53682 <register>
53683 <name>OTG_FS_HCINTMSK9</name>
53684 <displayName>OTG_FS_HCINTMSK9</displayName>
53685 <description>OTG_FS host channel-9 mask
53686 register</description>
53687 <addressOffset>0x20C</addressOffset>
53688 <size>0x20</size>
53689 <access>read-write</access>
53690 <resetValue>0x00000000</resetValue>
53691 <fields>
53692 <field>
53693 <name>XFRCM</name>
53694 <description>Transfer completed mask</description>
53695 <bitOffset>0</bitOffset>
53696 <bitWidth>1</bitWidth>
53697 </field>
53698 <field>
53699 <name>CHHM</name>
53700 <description>Channel halted mask</description>
53701 <bitOffset>1</bitOffset>
53702 <bitWidth>1</bitWidth>
53703 </field>
53704 <field>
53705 <name>STALLM</name>
53706 <description>STALL response received interrupt
53707 mask</description>
53708 <bitOffset>3</bitOffset>
53709 <bitWidth>1</bitWidth>
53710 </field>
53711 <field>
53712 <name>NAKM</name>
53713 <description>NAK response received interrupt
53714 mask</description>
53715 <bitOffset>4</bitOffset>
53716 <bitWidth>1</bitWidth>
53717 </field>
53718 <field>
53719 <name>ACKM</name>
53720 <description>ACK response received/transmitted
53721 interrupt mask</description>
53722 <bitOffset>5</bitOffset>
53723 <bitWidth>1</bitWidth>
53724 </field>
53725 <field>
53726 <name>NYET</name>
53727 <description>response received interrupt
53728 mask</description>
53729 <bitOffset>6</bitOffset>
53730 <bitWidth>1</bitWidth>
53731 </field>
53732 <field>
53733 <name>TXERRM</name>
53734 <description>Transaction error mask</description>
53735 <bitOffset>7</bitOffset>
53736 <bitWidth>1</bitWidth>
53737 </field>
53738 <field>
53739 <name>BBERRM</name>
53740 <description>Babble error mask</description>
53741 <bitOffset>8</bitOffset>
53742 <bitWidth>1</bitWidth>
53743 </field>
53744 <field>
53745 <name>FRMORM</name>
53746 <description>Frame overrun mask</description>
53747 <bitOffset>9</bitOffset>
53748 <bitWidth>1</bitWidth>
53749 </field>
53750 <field>
53751 <name>DTERRM</name>
53752 <description>Data toggle error mask</description>
53753 <bitOffset>10</bitOffset>
53754 <bitWidth>1</bitWidth>
53755 </field>
53756 </fields>
53757 </register>
53758 <register>
53759 <name>OTG_FS_HCTSIZ9</name>
53760 <displayName>OTG_FS_HCTSIZ9</displayName>
53761 <description>OTG_FS host channel-9 transfer size
53762 register</description>
53763 <addressOffset>0x210</addressOffset>
53764 <size>0x20</size>
53765 <access>read-write</access>
53766 <resetValue>0x00000000</resetValue>
53767 <fields>
53768 <field>
53769 <name>XFRSIZ</name>
53770 <description>Transfer size</description>
53771 <bitOffset>0</bitOffset>
53772 <bitWidth>19</bitWidth>
53773 </field>
53774 <field>
53775 <name>PKTCNT</name>
53776 <description>Packet count</description>
53777 <bitOffset>19</bitOffset>
53778 <bitWidth>10</bitWidth>
53779 </field>
53780 <field>
53781 <name>DPID</name>
53782 <description>Data PID</description>
53783 <bitOffset>29</bitOffset>
53784 <bitWidth>2</bitWidth>
53785 </field>
53786 </fields>
53787 </register>
53788 <register>
53789 <name>OTG_FS_HCCHAR10</name>
53790 <displayName>OTG_FS_HCCHAR10</displayName>
53791 <description>OTG_FS host channel-10 characteristics
53792 register</description>
53793 <addressOffset>0x214</addressOffset>
53794 <size>0x20</size>
53795 <access>read-write</access>
53796 <resetValue>0x00000000</resetValue>
53797 <fields>
53798 <field>
53799 <name>MPSIZ</name>
53800 <description>Maximum packet size</description>
53801 <bitOffset>0</bitOffset>
53802 <bitWidth>11</bitWidth>
53803 </field>
53804 <field>
53805 <name>EPNUM</name>
53806 <description>Endpoint number</description>
53807 <bitOffset>11</bitOffset>
53808 <bitWidth>4</bitWidth>
53809 </field>
53810 <field>
53811 <name>EPDIR</name>
53812 <description>Endpoint direction</description>
53813 <bitOffset>15</bitOffset>
53814 <bitWidth>1</bitWidth>
53815 </field>
53816 <field>
53817 <name>LSDEV</name>
53818 <description>Low-speed device</description>
53819 <bitOffset>17</bitOffset>
53820 <bitWidth>1</bitWidth>
53821 </field>
53822 <field>
53823 <name>EPTYP</name>
53824 <description>Endpoint type</description>
53825 <bitOffset>18</bitOffset>
53826 <bitWidth>2</bitWidth>
53827 </field>
53828 <field>
53829 <name>MCNT</name>
53830 <description>Multicount</description>
53831 <bitOffset>20</bitOffset>
53832 <bitWidth>2</bitWidth>
53833 </field>
53834 <field>
53835 <name>DAD</name>
53836 <description>Device address</description>
53837 <bitOffset>22</bitOffset>
53838 <bitWidth>7</bitWidth>
53839 </field>
53840 <field>
53841 <name>ODDFRM</name>
53842 <description>Odd frame</description>
53843 <bitOffset>29</bitOffset>
53844 <bitWidth>1</bitWidth>
53845 </field>
53846 <field>
53847 <name>CHDIS</name>
53848 <description>Channel disable</description>
53849 <bitOffset>30</bitOffset>
53850 <bitWidth>1</bitWidth>
53851 </field>
53852 <field>
53853 <name>CHENA</name>
53854 <description>Channel enable</description>
53855 <bitOffset>31</bitOffset>
53856 <bitWidth>1</bitWidth>
53857 </field>
53858 </fields>
53859 </register>
53860 <register>
53861 <name>OTG_FS_HCINT10</name>
53862 <displayName>OTG_FS_HCINT10</displayName>
53863 <description>OTG_FS host channel-10 interrupt
53864 register</description>
53865 <addressOffset>0x218</addressOffset>
53866 <size>0x20</size>
53867 <access>read-write</access>
53868 <resetValue>0x00000000</resetValue>
53869 <fields>
53870 <field>
53871 <name>XFRC</name>
53872 <description>Transfer completed</description>
53873 <bitOffset>0</bitOffset>
53874 <bitWidth>1</bitWidth>
53875 </field>
53876 <field>
53877 <name>CHH</name>
53878 <description>Channel halted</description>
53879 <bitOffset>1</bitOffset>
53880 <bitWidth>1</bitWidth>
53881 </field>
53882 <field>
53883 <name>STALL</name>
53884 <description>STALL response received
53885 interrupt</description>
53886 <bitOffset>3</bitOffset>
53887 <bitWidth>1</bitWidth>
53888 </field>
53889 <field>
53890 <name>NAK</name>
53891 <description>NAK response received
53892 interrupt</description>
53893 <bitOffset>4</bitOffset>
53894 <bitWidth>1</bitWidth>
53895 </field>
53896 <field>
53897 <name>ACK</name>
53898 <description>ACK response received/transmitted
53899 interrupt</description>
53900 <bitOffset>5</bitOffset>
53901 <bitWidth>1</bitWidth>
53902 </field>
53903 <field>
53904 <name>TXERR</name>
53905 <description>Transaction error</description>
53906 <bitOffset>7</bitOffset>
53907 <bitWidth>1</bitWidth>
53908 </field>
53909 <field>
53910 <name>BBERR</name>
53911 <description>Babble error</description>
53912 <bitOffset>8</bitOffset>
53913 <bitWidth>1</bitWidth>
53914 </field>
53915 <field>
53916 <name>FRMOR</name>
53917 <description>Frame overrun</description>
53918 <bitOffset>9</bitOffset>
53919 <bitWidth>1</bitWidth>
53920 </field>
53921 <field>
53922 <name>DTERR</name>
53923 <description>Data toggle error</description>
53924 <bitOffset>10</bitOffset>
53925 <bitWidth>1</bitWidth>
53926 </field>
53927 </fields>
53928 </register>
53929 <register>
53930 <name>OTG_FS_HCINTMSK10</name>
53931 <displayName>OTG_FS_HCINTMSK10</displayName>
53932 <description>OTG_FS host channel-10 mask
53933 register</description>
53934 <addressOffset>0x21C</addressOffset>
53935 <size>0x20</size>
53936 <access>read-write</access>
53937 <resetValue>0x00000000</resetValue>
53938 <fields>
53939 <field>
53940 <name>XFRCM</name>
53941 <description>Transfer completed mask</description>
53942 <bitOffset>0</bitOffset>
53943 <bitWidth>1</bitWidth>
53944 </field>
53945 <field>
53946 <name>CHHM</name>
53947 <description>Channel halted mask</description>
53948 <bitOffset>1</bitOffset>
53949 <bitWidth>1</bitWidth>
53950 </field>
53951 <field>
53952 <name>STALLM</name>
53953 <description>STALL response received interrupt
53954 mask</description>
53955 <bitOffset>3</bitOffset>
53956 <bitWidth>1</bitWidth>
53957 </field>
53958 <field>
53959 <name>NAKM</name>
53960 <description>NAK response received interrupt
53961 mask</description>
53962 <bitOffset>4</bitOffset>
53963 <bitWidth>1</bitWidth>
53964 </field>
53965 <field>
53966 <name>ACKM</name>
53967 <description>ACK response received/transmitted
53968 interrupt mask</description>
53969 <bitOffset>5</bitOffset>
53970 <bitWidth>1</bitWidth>
53971 </field>
53972 <field>
53973 <name>NYET</name>
53974 <description>response received interrupt
53975 mask</description>
53976 <bitOffset>6</bitOffset>
53977 <bitWidth>1</bitWidth>
53978 </field>
53979 <field>
53980 <name>TXERRM</name>
53981 <description>Transaction error mask</description>
53982 <bitOffset>7</bitOffset>
53983 <bitWidth>1</bitWidth>
53984 </field>
53985 <field>
53986 <name>BBERRM</name>
53987 <description>Babble error mask</description>
53988 <bitOffset>8</bitOffset>
53989 <bitWidth>1</bitWidth>
53990 </field>
53991 <field>
53992 <name>FRMORM</name>
53993 <description>Frame overrun mask</description>
53994 <bitOffset>9</bitOffset>
53995 <bitWidth>1</bitWidth>
53996 </field>
53997 <field>
53998 <name>DTERRM</name>
53999 <description>Data toggle error mask</description>
54000 <bitOffset>10</bitOffset>
54001 <bitWidth>1</bitWidth>
54002 </field>
54003 </fields>
54004 </register>
54005 <register>
54006 <name>OTG_FS_HCTSIZ10</name>
54007 <displayName>OTG_FS_HCTSIZ10</displayName>
54008 <description>OTG_FS host channel-10 transfer size
54009 register</description>
54010 <addressOffset>0x220</addressOffset>
54011 <size>0x20</size>
54012 <access>read-write</access>
54013 <resetValue>0x00000000</resetValue>
54014 <fields>
54015 <field>
54016 <name>XFRSIZ</name>
54017 <description>Transfer size</description>
54018 <bitOffset>0</bitOffset>
54019 <bitWidth>19</bitWidth>
54020 </field>
54021 <field>
54022 <name>PKTCNT</name>
54023 <description>Packet count</description>
54024 <bitOffset>19</bitOffset>
54025 <bitWidth>10</bitWidth>
54026 </field>
54027 <field>
54028 <name>DPID</name>
54029 <description>Data PID</description>
54030 <bitOffset>29</bitOffset>
54031 <bitWidth>2</bitWidth>
54032 </field>
54033 </fields>
54034 </register>
54035 <register>
54036 <name>OTG_FS_HCCHAR11</name>
54037 <displayName>OTG_FS_HCCHAR11</displayName>
54038 <description>OTG_FS host channel-11 characteristics
54039 register</description>
54040 <addressOffset>0x224</addressOffset>
54041 <size>0x20</size>
54042 <access>read-write</access>
54043 <resetValue>0x00000000</resetValue>
54044 <fields>
54045 <field>
54046 <name>MPSIZ</name>
54047 <description>Maximum packet size</description>
54048 <bitOffset>0</bitOffset>
54049 <bitWidth>11</bitWidth>
54050 </field>
54051 <field>
54052 <name>EPNUM</name>
54053 <description>Endpoint number</description>
54054 <bitOffset>11</bitOffset>
54055 <bitWidth>4</bitWidth>
54056 </field>
54057 <field>
54058 <name>EPDIR</name>
54059 <description>Endpoint direction</description>
54060 <bitOffset>15</bitOffset>
54061 <bitWidth>1</bitWidth>
54062 </field>
54063 <field>
54064 <name>LSDEV</name>
54065 <description>Low-speed device</description>
54066 <bitOffset>17</bitOffset>
54067 <bitWidth>1</bitWidth>
54068 </field>
54069 <field>
54070 <name>EPTYP</name>
54071 <description>Endpoint type</description>
54072 <bitOffset>18</bitOffset>
54073 <bitWidth>2</bitWidth>
54074 </field>
54075 <field>
54076 <name>MCNT</name>
54077 <description>Multicount</description>
54078 <bitOffset>20</bitOffset>
54079 <bitWidth>2</bitWidth>
54080 </field>
54081 <field>
54082 <name>DAD</name>
54083 <description>Device address</description>
54084 <bitOffset>22</bitOffset>
54085 <bitWidth>7</bitWidth>
54086 </field>
54087 <field>
54088 <name>ODDFRM</name>
54089 <description>Odd frame</description>
54090 <bitOffset>29</bitOffset>
54091 <bitWidth>1</bitWidth>
54092 </field>
54093 <field>
54094 <name>CHDIS</name>
54095 <description>Channel disable</description>
54096 <bitOffset>30</bitOffset>
54097 <bitWidth>1</bitWidth>
54098 </field>
54099 <field>
54100 <name>CHENA</name>
54101 <description>Channel enable</description>
54102 <bitOffset>31</bitOffset>
54103 <bitWidth>1</bitWidth>
54104 </field>
54105 </fields>
54106 </register>
54107 <register>
54108 <name>OTG_FS_HCINT11</name>
54109 <displayName>OTG_FS_HCINT11</displayName>
54110 <description>OTG_FS host channel-11 interrupt
54111 register</description>
54112 <addressOffset>0x228</addressOffset>
54113 <size>0x20</size>
54114 <access>read-write</access>
54115 <resetValue>0x00000000</resetValue>
54116 <fields>
54117 <field>
54118 <name>XFRC</name>
54119 <description>Transfer completed</description>
54120 <bitOffset>0</bitOffset>
54121 <bitWidth>1</bitWidth>
54122 </field>
54123 <field>
54124 <name>CHH</name>
54125 <description>Channel halted</description>
54126 <bitOffset>1</bitOffset>
54127 <bitWidth>1</bitWidth>
54128 </field>
54129 <field>
54130 <name>STALL</name>
54131 <description>STALL response received
54132 interrupt</description>
54133 <bitOffset>3</bitOffset>
54134 <bitWidth>1</bitWidth>
54135 </field>
54136 <field>
54137 <name>NAK</name>
54138 <description>NAK response received
54139 interrupt</description>
54140 <bitOffset>4</bitOffset>
54141 <bitWidth>1</bitWidth>
54142 </field>
54143 <field>
54144 <name>ACK</name>
54145 <description>ACK response received/transmitted
54146 interrupt</description>
54147 <bitOffset>5</bitOffset>
54148 <bitWidth>1</bitWidth>
54149 </field>
54150 <field>
54151 <name>TXERR</name>
54152 <description>Transaction error</description>
54153 <bitOffset>7</bitOffset>
54154 <bitWidth>1</bitWidth>
54155 </field>
54156 <field>
54157 <name>BBERR</name>
54158 <description>Babble error</description>
54159 <bitOffset>8</bitOffset>
54160 <bitWidth>1</bitWidth>
54161 </field>
54162 <field>
54163 <name>FRMOR</name>
54164 <description>Frame overrun</description>
54165 <bitOffset>9</bitOffset>
54166 <bitWidth>1</bitWidth>
54167 </field>
54168 <field>
54169 <name>DTERR</name>
54170 <description>Data toggle error</description>
54171 <bitOffset>10</bitOffset>
54172 <bitWidth>1</bitWidth>
54173 </field>
54174 </fields>
54175 </register>
54176 <register>
54177 <name>OTG_FS_HCINTMSK11</name>
54178 <displayName>OTG_FS_HCINTMSK11</displayName>
54179 <description>OTG_FS host channel-11 mask
54180 register</description>
54181 <addressOffset>0x22C</addressOffset>
54182 <size>0x20</size>
54183 <access>read-write</access>
54184 <resetValue>0x00000000</resetValue>
54185 <fields>
54186 <field>
54187 <name>XFRCM</name>
54188 <description>Transfer completed mask</description>
54189 <bitOffset>0</bitOffset>
54190 <bitWidth>1</bitWidth>
54191 </field>
54192 <field>
54193 <name>CHHM</name>
54194 <description>Channel halted mask</description>
54195 <bitOffset>1</bitOffset>
54196 <bitWidth>1</bitWidth>
54197 </field>
54198 <field>
54199 <name>STALLM</name>
54200 <description>STALL response received interrupt
54201 mask</description>
54202 <bitOffset>3</bitOffset>
54203 <bitWidth>1</bitWidth>
54204 </field>
54205 <field>
54206 <name>NAKM</name>
54207 <description>NAK response received interrupt
54208 mask</description>
54209 <bitOffset>4</bitOffset>
54210 <bitWidth>1</bitWidth>
54211 </field>
54212 <field>
54213 <name>ACKM</name>
54214 <description>ACK response received/transmitted
54215 interrupt mask</description>
54216 <bitOffset>5</bitOffset>
54217 <bitWidth>1</bitWidth>
54218 </field>
54219 <field>
54220 <name>NYET</name>
54221 <description>response received interrupt
54222 mask</description>
54223 <bitOffset>6</bitOffset>
54224 <bitWidth>1</bitWidth>
54225 </field>
54226 <field>
54227 <name>TXERRM</name>
54228 <description>Transaction error mask</description>
54229 <bitOffset>7</bitOffset>
54230 <bitWidth>1</bitWidth>
54231 </field>
54232 <field>
54233 <name>BBERRM</name>
54234 <description>Babble error mask</description>
54235 <bitOffset>8</bitOffset>
54236 <bitWidth>1</bitWidth>
54237 </field>
54238 <field>
54239 <name>FRMORM</name>
54240 <description>Frame overrun mask</description>
54241 <bitOffset>9</bitOffset>
54242 <bitWidth>1</bitWidth>
54243 </field>
54244 <field>
54245 <name>DTERRM</name>
54246 <description>Data toggle error mask</description>
54247 <bitOffset>10</bitOffset>
54248 <bitWidth>1</bitWidth>
54249 </field>
54250 </fields>
54251 </register>
54252 <register>
54253 <name>OTG_FS_HCTSIZ11</name>
54254 <displayName>OTG_FS_HCTSIZ11</displayName>
54255 <description>OTG_FS host channel-11 transfer size
54256 register</description>
54257 <addressOffset>0x230</addressOffset>
54258 <size>0x20</size>
54259 <access>read-write</access>
54260 <resetValue>0x00000000</resetValue>
54261 <fields>
54262 <field>
54263 <name>XFRSIZ</name>
54264 <description>Transfer size</description>
54265 <bitOffset>0</bitOffset>
54266 <bitWidth>19</bitWidth>
54267 </field>
54268 <field>
54269 <name>PKTCNT</name>
54270 <description>Packet count</description>
54271 <bitOffset>19</bitOffset>
54272 <bitWidth>10</bitWidth>
54273 </field>
54274 <field>
54275 <name>DPID</name>
54276 <description>Data PID</description>
54277 <bitOffset>29</bitOffset>
54278 <bitWidth>2</bitWidth>
54279 </field>
54280 </fields>
54281 </register>
54282 </registers>
54283 </peripheral>
54284 <peripheral>
54285 <name>OTG_FS_DEVICE</name>
54286 <description>USB on the go full speed</description>
54287 <groupName>USB_OTG_FS</groupName>
54288 <baseAddress>0x50000800</baseAddress>
54289 <addressBlock>
54290 <offset>0x0</offset>
54291 <size>0x400</size>
54292 <usage>registers</usage>
54293 </addressBlock>
54294 <registers>
54295 <register>
54296 <name>OTG_FS_DCFG</name>
54297 <displayName>OTG_FS_DCFG</displayName>
54298 <description>OTG_FS device configuration register
54299 (OTG_FS_DCFG)</description>
54300 <addressOffset>0x0</addressOffset>
54301 <size>0x20</size>
54302 <access>read-write</access>
54303 <resetValue>0x02200000</resetValue>
54304 <fields>
54305 <field>
54306 <name>DSPD</name>
54307 <description>Device speed</description>
54308 <bitOffset>0</bitOffset>
54309 <bitWidth>2</bitWidth>
54310 </field>
54311 <field>
54312 <name>NZLSOHSK</name>
54313 <description>Non-zero-length status OUT
54314 handshake</description>
54315 <bitOffset>2</bitOffset>
54316 <bitWidth>1</bitWidth>
54317 </field>
54318 <field>
54319 <name>DAD</name>
54320 <description>Device address</description>
54321 <bitOffset>4</bitOffset>
54322 <bitWidth>7</bitWidth>
54323 </field>
54324 <field>
54325 <name>PFIVL</name>
54326 <description>Periodic frame interval</description>
54327 <bitOffset>11</bitOffset>
54328 <bitWidth>2</bitWidth>
54329 </field>
54330 </fields>
54331 </register>
54332 <register>
54333 <name>OTG_FS_DCTL</name>
54334 <displayName>OTG_FS_DCTL</displayName>
54335 <description>OTG_FS device control register
54336 (OTG_FS_DCTL)</description>
54337 <addressOffset>0x4</addressOffset>
54338 <size>0x20</size>
54339 <resetValue>0x00000000</resetValue>
54340 <fields>
54341 <field>
54342 <name>RWUSIG</name>
54343 <description>Remote wakeup signaling</description>
54344 <bitOffset>0</bitOffset>
54345 <bitWidth>1</bitWidth>
54346 <access>read-write</access>
54347 </field>
54348 <field>
54349 <name>SDIS</name>
54350 <description>Soft disconnect</description>
54351 <bitOffset>1</bitOffset>
54352 <bitWidth>1</bitWidth>
54353 <access>read-write</access>
54354 </field>
54355 <field>
54356 <name>GINSTS</name>
54357 <description>Global IN NAK status</description>
54358 <bitOffset>2</bitOffset>
54359 <bitWidth>1</bitWidth>
54360 <access>read-only</access>
54361 </field>
54362 <field>
54363 <name>GONSTS</name>
54364 <description>Global OUT NAK status</description>
54365 <bitOffset>3</bitOffset>
54366 <bitWidth>1</bitWidth>
54367 <access>read-only</access>
54368 </field>
54369 <field>
54370 <name>TCTL</name>
54371 <description>Test control</description>
54372 <bitOffset>4</bitOffset>
54373 <bitWidth>3</bitWidth>
54374 <access>read-write</access>
54375 </field>
54376 <field>
54377 <name>SGINAK</name>
54378 <description>Set global IN NAK</description>
54379 <bitOffset>7</bitOffset>
54380 <bitWidth>1</bitWidth>
54381 <access>read-write</access>
54382 </field>
54383 <field>
54384 <name>CGINAK</name>
54385 <description>Clear global IN NAK</description>
54386 <bitOffset>8</bitOffset>
54387 <bitWidth>1</bitWidth>
54388 <access>read-write</access>
54389 </field>
54390 <field>
54391 <name>SGONAK</name>
54392 <description>Set global OUT NAK</description>
54393 <bitOffset>9</bitOffset>
54394 <bitWidth>1</bitWidth>
54395 <access>read-write</access>
54396 </field>
54397 <field>
54398 <name>CGONAK</name>
54399 <description>Clear global OUT NAK</description>
54400 <bitOffset>10</bitOffset>
54401 <bitWidth>1</bitWidth>
54402 <access>read-write</access>
54403 </field>
54404 <field>
54405 <name>POPRGDNE</name>
54406 <description>Power-on programming done</description>
54407 <bitOffset>11</bitOffset>
54408 <bitWidth>1</bitWidth>
54409 <access>read-write</access>
54410 </field>
54411 </fields>
54412 </register>
54413 <register>
54414 <name>OTG_FS_DSTS</name>
54415 <displayName>OTG_FS_DSTS</displayName>
54416 <description>OTG_FS device status register
54417 (OTG_FS_DSTS)</description>
54418 <addressOffset>0x8</addressOffset>
54419 <size>0x20</size>
54420 <access>read-only</access>
54421 <resetValue>0x00000010</resetValue>
54422 <fields>
54423 <field>
54424 <name>SUSPSTS</name>
54425 <description>Suspend status</description>
54426 <bitOffset>0</bitOffset>
54427 <bitWidth>1</bitWidth>
54428 </field>
54429 <field>
54430 <name>ENUMSPD</name>
54431 <description>Enumerated speed</description>
54432 <bitOffset>1</bitOffset>
54433 <bitWidth>2</bitWidth>
54434 </field>
54435 <field>
54436 <name>EERR</name>
54437 <description>Erratic error</description>
54438 <bitOffset>3</bitOffset>
54439 <bitWidth>1</bitWidth>
54440 </field>
54441 <field>
54442 <name>FNSOF</name>
54443 <description>Frame number of the received
54444 SOF</description>
54445 <bitOffset>8</bitOffset>
54446 <bitWidth>14</bitWidth>
54447 </field>
54448 </fields>
54449 </register>
54450 <register>
54451 <name>OTG_FS_DIEPMSK</name>
54452 <displayName>OTG_FS_DIEPMSK</displayName>
54453 <description>OTG_FS device IN endpoint common interrupt
54454 mask register (OTG_FS_DIEPMSK)</description>
54455 <addressOffset>0x10</addressOffset>
54456 <size>0x20</size>
54457 <access>read-write</access>
54458 <resetValue>0x00000000</resetValue>
54459 <fields>
54460 <field>
54461 <name>XFRCM</name>
54462 <description>Transfer completed interrupt
54463 mask</description>
54464 <bitOffset>0</bitOffset>
54465 <bitWidth>1</bitWidth>
54466 </field>
54467 <field>
54468 <name>EPDM</name>
54469 <description>Endpoint disabled interrupt
54470 mask</description>
54471 <bitOffset>1</bitOffset>
54472 <bitWidth>1</bitWidth>
54473 </field>
54474 <field>
54475 <name>TOM</name>
54476 <description>Timeout condition mask (Non-isochronous
54477 endpoints)</description>
54478 <bitOffset>3</bitOffset>
54479 <bitWidth>1</bitWidth>
54480 </field>
54481 <field>
54482 <name>ITTXFEMSK</name>
54483 <description>IN token received when TxFIFO empty
54484 mask</description>
54485 <bitOffset>4</bitOffset>
54486 <bitWidth>1</bitWidth>
54487 </field>
54488 <field>
54489 <name>INEPNMM</name>
54490 <description>IN token received with EP mismatch
54491 mask</description>
54492 <bitOffset>5</bitOffset>
54493 <bitWidth>1</bitWidth>
54494 </field>
54495 <field>
54496 <name>INEPNEM</name>
54497 <description>IN endpoint NAK effective
54498 mask</description>
54499 <bitOffset>6</bitOffset>
54500 <bitWidth>1</bitWidth>
54501 </field>
54502 </fields>
54503 </register>
54504 <register>
54505 <name>OTG_FS_DOEPMSK</name>
54506 <displayName>OTG_FS_DOEPMSK</displayName>
54507 <description>OTG_FS device OUT endpoint common interrupt
54508 mask register (OTG_FS_DOEPMSK)</description>
54509 <addressOffset>0x14</addressOffset>
54510 <size>0x20</size>
54511 <access>read-write</access>
54512 <resetValue>0x00000000</resetValue>
54513 <fields>
54514 <field>
54515 <name>XFRCM</name>
54516 <description>Transfer completed interrupt
54517 mask</description>
54518 <bitOffset>0</bitOffset>
54519 <bitWidth>1</bitWidth>
54520 </field>
54521 <field>
54522 <name>EPDM</name>
54523 <description>Endpoint disabled interrupt
54524 mask</description>
54525 <bitOffset>1</bitOffset>
54526 <bitWidth>1</bitWidth>
54527 </field>
54528 <field>
54529 <name>STUPM</name>
54530 <description>SETUP phase done mask</description>
54531 <bitOffset>3</bitOffset>
54532 <bitWidth>1</bitWidth>
54533 </field>
54534 <field>
54535 <name>OTEPDM</name>
54536 <description>OUT token received when endpoint
54537 disabled mask</description>
54538 <bitOffset>4</bitOffset>
54539 <bitWidth>1</bitWidth>
54540 </field>
54541 </fields>
54542 </register>
54543 <register>
54544 <name>OTG_FS_DAINT</name>
54545 <displayName>OTG_FS_DAINT</displayName>
54546 <description>OTG_FS device all endpoints interrupt
54547 register (OTG_FS_DAINT)</description>
54548 <addressOffset>0x18</addressOffset>
54549 <size>0x20</size>
54550 <access>read-only</access>
54551 <resetValue>0x00000000</resetValue>
54552 <fields>
54553 <field>
54554 <name>IEPINT</name>
54555 <description>IN endpoint interrupt bits</description>
54556 <bitOffset>0</bitOffset>
54557 <bitWidth>16</bitWidth>
54558 </field>
54559 <field>
54560 <name>OEPINT</name>
54561 <description>OUT endpoint interrupt
54562 bits</description>
54563 <bitOffset>16</bitOffset>
54564 <bitWidth>16</bitWidth>
54565 </field>
54566 </fields>
54567 </register>
54568 <register>
54569 <name>OTG_FS_DAINTMSK</name>
54570 <displayName>OTG_FS_DAINTMSK</displayName>
54571 <description>OTG_FS all endpoints interrupt mask register
54572 (OTG_FS_DAINTMSK)</description>
54573 <addressOffset>0x1C</addressOffset>
54574 <size>0x20</size>
54575 <access>read-write</access>
54576 <resetValue>0x00000000</resetValue>
54577 <fields>
54578 <field>
54579 <name>IEPM</name>
54580 <description>IN EP interrupt mask bits</description>
54581 <bitOffset>0</bitOffset>
54582 <bitWidth>16</bitWidth>
54583 </field>
54584 <field>
54585 <name>OEPINT</name>
54586 <description>OUT endpoint interrupt
54587 bits</description>
54588 <bitOffset>16</bitOffset>
54589 <bitWidth>16</bitWidth>
54590 </field>
54591 </fields>
54592 </register>
54593 <register>
54594 <name>OTG_FS_DVBUSDIS</name>
54595 <displayName>OTG_FS_DVBUSDIS</displayName>
54596 <description>OTG_FS device VBUS discharge time
54597 register</description>
54598 <addressOffset>0x28</addressOffset>
54599 <size>0x20</size>
54600 <access>read-write</access>
54601 <resetValue>0x000017D7</resetValue>
54602 <fields>
54603 <field>
54604 <name>VBUSDT</name>
54605 <description>Device VBUS discharge time</description>
54606 <bitOffset>0</bitOffset>
54607 <bitWidth>16</bitWidth>
54608 </field>
54609 </fields>
54610 </register>
54611 <register>
54612 <name>OTG_FS_DVBUSPULSE</name>
54613 <displayName>OTG_FS_DVBUSPULSE</displayName>
54614 <description>OTG_FS device VBUS pulsing time
54615 register</description>
54616 <addressOffset>0x2C</addressOffset>
54617 <size>0x20</size>
54618 <access>read-write</access>
54619 <resetValue>0x000005B8</resetValue>
54620 <fields>
54621 <field>
54622 <name>DVBUSP</name>
54623 <description>Device VBUS pulsing time</description>
54624 <bitOffset>0</bitOffset>
54625 <bitWidth>12</bitWidth>
54626 </field>
54627 </fields>
54628 </register>
54629 <register>
54630 <name>OTG_FS_DIEPEMPMSK</name>
54631 <displayName>OTG_FS_DIEPEMPMSK</displayName>
54632 <description>OTG_FS device IN endpoint FIFO empty
54633 interrupt mask register</description>
54634 <addressOffset>0x34</addressOffset>
54635 <size>0x20</size>
54636 <access>read-write</access>
54637 <resetValue>0x00000000</resetValue>
54638 <fields>
54639 <field>
54640 <name>INEPTXFEM</name>
54641 <description>IN EP Tx FIFO empty interrupt mask
54642 bits</description>
54643 <bitOffset>0</bitOffset>
54644 <bitWidth>16</bitWidth>
54645 </field>
54646 </fields>
54647 </register>
54648 <register>
54649 <name>OTG_FS_DIEPCTL0</name>
54650 <displayName>OTG_FS_DIEPCTL0</displayName>
54651 <description>OTG_FS device control IN endpoint 0 control
54652 register (OTG_FS_DIEPCTL0)</description>
54653 <addressOffset>0x100</addressOffset>
54654 <size>0x20</size>
54655 <resetValue>0x00000000</resetValue>
54656 <fields>
54657 <field>
54658 <name>MPSIZ</name>
54659 <description>Maximum packet size</description>
54660 <bitOffset>0</bitOffset>
54661 <bitWidth>2</bitWidth>
54662 <access>read-write</access>
54663 </field>
54664 <field>
54665 <name>USBAEP</name>
54666 <description>USB active endpoint</description>
54667 <bitOffset>15</bitOffset>
54668 <bitWidth>1</bitWidth>
54669 <access>read-only</access>
54670 </field>
54671 <field>
54672 <name>NAKSTS</name>
54673 <description>NAK status</description>
54674 <bitOffset>17</bitOffset>
54675 <bitWidth>1</bitWidth>
54676 <access>read-only</access>
54677 </field>
54678 <field>
54679 <name>EPTYP</name>
54680 <description>Endpoint type</description>
54681 <bitOffset>18</bitOffset>
54682 <bitWidth>2</bitWidth>
54683 <access>read-only</access>
54684 </field>
54685 <field>
54686 <name>STALL</name>
54687 <description>STALL handshake</description>
54688 <bitOffset>21</bitOffset>
54689 <bitWidth>1</bitWidth>
54690 <access>read-write</access>
54691 </field>
54692 <field>
54693 <name>TXFNUM</name>
54694 <description>TxFIFO number</description>
54695 <bitOffset>22</bitOffset>
54696 <bitWidth>4</bitWidth>
54697 <access>read-write</access>
54698 </field>
54699 <field>
54700 <name>CNAK</name>
54701 <description>Clear NAK</description>
54702 <bitOffset>26</bitOffset>
54703 <bitWidth>1</bitWidth>
54704 <access>write-only</access>
54705 </field>
54706 <field>
54707 <name>SNAK</name>
54708 <description>Set NAK</description>
54709 <bitOffset>27</bitOffset>
54710 <bitWidth>1</bitWidth>
54711 <access>write-only</access>
54712 </field>
54713 <field>
54714 <name>EPDIS</name>
54715 <description>Endpoint disable</description>
54716 <bitOffset>30</bitOffset>
54717 <bitWidth>1</bitWidth>
54718 <access>read-only</access>
54719 </field>
54720 <field>
54721 <name>EPENA</name>
54722 <description>Endpoint enable</description>
54723 <bitOffset>31</bitOffset>
54724 <bitWidth>1</bitWidth>
54725 <access>read-only</access>
54726 </field>
54727 </fields>
54728 </register>
54729 <register>
54730 <name>OTG_FS_DIEPCTL1</name>
54731 <displayName>OTG_FS_DIEPCTL1</displayName>
54732 <description>OTG device endpoint-1 control
54733 register</description>
54734 <addressOffset>0x120</addressOffset>
54735 <size>0x20</size>
54736 <resetValue>0x00000000</resetValue>
54737 <fields>
54738 <field>
54739 <name>EPENA</name>
54740 <description>EPENA</description>
54741 <bitOffset>31</bitOffset>
54742 <bitWidth>1</bitWidth>
54743 <access>read-write</access>
54744 </field>
54745 <field>
54746 <name>EPDIS</name>
54747 <description>EPDIS</description>
54748 <bitOffset>30</bitOffset>
54749 <bitWidth>1</bitWidth>
54750 <access>read-write</access>
54751 </field>
54752 <field>
54753 <name>SODDFRM_SD1PID</name>
54754 <description>SODDFRM/SD1PID</description>
54755 <bitOffset>29</bitOffset>
54756 <bitWidth>1</bitWidth>
54757 <access>write-only</access>
54758 </field>
54759 <field>
54760 <name>SD0PID_SEVNFRM</name>
54761 <description>SD0PID/SEVNFRM</description>
54762 <bitOffset>28</bitOffset>
54763 <bitWidth>1</bitWidth>
54764 <access>write-only</access>
54765 </field>
54766 <field>
54767 <name>SNAK</name>
54768 <description>SNAK</description>
54769 <bitOffset>27</bitOffset>
54770 <bitWidth>1</bitWidth>
54771 <access>write-only</access>
54772 </field>
54773 <field>
54774 <name>CNAK</name>
54775 <description>CNAK</description>
54776 <bitOffset>26</bitOffset>
54777 <bitWidth>1</bitWidth>
54778 <access>write-only</access>
54779 </field>
54780 <field>
54781 <name>TXFNUM</name>
54782 <description>TXFNUM</description>
54783 <bitOffset>22</bitOffset>
54784 <bitWidth>4</bitWidth>
54785 <access>read-write</access>
54786 </field>
54787 <field>
54788 <name>Stall</name>
54789 <description>Stall</description>
54790 <bitOffset>21</bitOffset>
54791 <bitWidth>1</bitWidth>
54792 <access>read-write</access>
54793 </field>
54794 <field>
54795 <name>EPTYP</name>
54796 <description>EPTYP</description>
54797 <bitOffset>18</bitOffset>
54798 <bitWidth>2</bitWidth>
54799 <access>read-write</access>
54800 </field>
54801 <field>
54802 <name>NAKSTS</name>
54803 <description>NAKSTS</description>
54804 <bitOffset>17</bitOffset>
54805 <bitWidth>1</bitWidth>
54806 <access>read-only</access>
54807 </field>
54808 <field>
54809 <name>EONUM_DPID</name>
54810 <description>EONUM/DPID</description>
54811 <bitOffset>16</bitOffset>
54812 <bitWidth>1</bitWidth>
54813 <access>read-only</access>
54814 </field>
54815 <field>
54816 <name>USBAEP</name>
54817 <description>USBAEP</description>
54818 <bitOffset>15</bitOffset>
54819 <bitWidth>1</bitWidth>
54820 <access>read-write</access>
54821 </field>
54822 <field>
54823 <name>MPSIZ</name>
54824 <description>MPSIZ</description>
54825 <bitOffset>0</bitOffset>
54826 <bitWidth>11</bitWidth>
54827 <access>read-write</access>
54828 </field>
54829 </fields>
54830 </register>
54831 <register>
54832 <name>OTG_FS_DIEPCTL2</name>
54833 <displayName>OTG_FS_DIEPCTL2</displayName>
54834 <description>OTG device endpoint-2 control
54835 register</description>
54836 <addressOffset>0x140</addressOffset>
54837 <size>0x20</size>
54838 <resetValue>0x00000000</resetValue>
54839 <fields>
54840 <field>
54841 <name>EPENA</name>
54842 <description>EPENA</description>
54843 <bitOffset>31</bitOffset>
54844 <bitWidth>1</bitWidth>
54845 <access>read-write</access>
54846 </field>
54847 <field>
54848 <name>EPDIS</name>
54849 <description>EPDIS</description>
54850 <bitOffset>30</bitOffset>
54851 <bitWidth>1</bitWidth>
54852 <access>read-write</access>
54853 </field>
54854 <field>
54855 <name>SODDFRM</name>
54856 <description>SODDFRM</description>
54857 <bitOffset>29</bitOffset>
54858 <bitWidth>1</bitWidth>
54859 <access>write-only</access>
54860 </field>
54861 <field>
54862 <name>SD0PID_SEVNFRM</name>
54863 <description>SD0PID/SEVNFRM</description>
54864 <bitOffset>28</bitOffset>
54865 <bitWidth>1</bitWidth>
54866 <access>write-only</access>
54867 </field>
54868 <field>
54869 <name>SNAK</name>
54870 <description>SNAK</description>
54871 <bitOffset>27</bitOffset>
54872 <bitWidth>1</bitWidth>
54873 <access>write-only</access>
54874 </field>
54875 <field>
54876 <name>CNAK</name>
54877 <description>CNAK</description>
54878 <bitOffset>26</bitOffset>
54879 <bitWidth>1</bitWidth>
54880 <access>write-only</access>
54881 </field>
54882 <field>
54883 <name>TXFNUM</name>
54884 <description>TXFNUM</description>
54885 <bitOffset>22</bitOffset>
54886 <bitWidth>4</bitWidth>
54887 <access>read-write</access>
54888 </field>
54889 <field>
54890 <name>Stall</name>
54891 <description>Stall</description>
54892 <bitOffset>21</bitOffset>
54893 <bitWidth>1</bitWidth>
54894 <access>read-write</access>
54895 </field>
54896 <field>
54897 <name>EPTYP</name>
54898 <description>EPTYP</description>
54899 <bitOffset>18</bitOffset>
54900 <bitWidth>2</bitWidth>
54901 <access>read-write</access>
54902 </field>
54903 <field>
54904 <name>NAKSTS</name>
54905 <description>NAKSTS</description>
54906 <bitOffset>17</bitOffset>
54907 <bitWidth>1</bitWidth>
54908 <access>read-only</access>
54909 </field>
54910 <field>
54911 <name>EONUM_DPID</name>
54912 <description>EONUM/DPID</description>
54913 <bitOffset>16</bitOffset>
54914 <bitWidth>1</bitWidth>
54915 <access>read-only</access>
54916 </field>
54917 <field>
54918 <name>USBAEP</name>
54919 <description>USBAEP</description>
54920 <bitOffset>15</bitOffset>
54921 <bitWidth>1</bitWidth>
54922 <access>read-write</access>
54923 </field>
54924 <field>
54925 <name>MPSIZ</name>
54926 <description>MPSIZ</description>
54927 <bitOffset>0</bitOffset>
54928 <bitWidth>11</bitWidth>
54929 <access>read-write</access>
54930 </field>
54931 </fields>
54932 </register>
54933 <register>
54934 <name>OTG_FS_DIEPCTL3</name>
54935 <displayName>OTG_FS_DIEPCTL3</displayName>
54936 <description>OTG device endpoint-3 control
54937 register</description>
54938 <addressOffset>0x160</addressOffset>
54939 <size>0x20</size>
54940 <resetValue>0x00000000</resetValue>
54941 <fields>
54942 <field>
54943 <name>EPENA</name>
54944 <description>EPENA</description>
54945 <bitOffset>31</bitOffset>
54946 <bitWidth>1</bitWidth>
54947 <access>read-write</access>
54948 </field>
54949 <field>
54950 <name>EPDIS</name>
54951 <description>EPDIS</description>
54952 <bitOffset>30</bitOffset>
54953 <bitWidth>1</bitWidth>
54954 <access>read-write</access>
54955 </field>
54956 <field>
54957 <name>SODDFRM</name>
54958 <description>SODDFRM</description>
54959 <bitOffset>29</bitOffset>
54960 <bitWidth>1</bitWidth>
54961 <access>write-only</access>
54962 </field>
54963 <field>
54964 <name>SD0PID_SEVNFRM</name>
54965 <description>SD0PID/SEVNFRM</description>
54966 <bitOffset>28</bitOffset>
54967 <bitWidth>1</bitWidth>
54968 <access>write-only</access>
54969 </field>
54970 <field>
54971 <name>SNAK</name>
54972 <description>SNAK</description>
54973 <bitOffset>27</bitOffset>
54974 <bitWidth>1</bitWidth>
54975 <access>write-only</access>
54976 </field>
54977 <field>
54978 <name>CNAK</name>
54979 <description>CNAK</description>
54980 <bitOffset>26</bitOffset>
54981 <bitWidth>1</bitWidth>
54982 <access>write-only</access>
54983 </field>
54984 <field>
54985 <name>TXFNUM</name>
54986 <description>TXFNUM</description>
54987 <bitOffset>22</bitOffset>
54988 <bitWidth>4</bitWidth>
54989 <access>read-write</access>
54990 </field>
54991 <field>
54992 <name>Stall</name>
54993 <description>Stall</description>
54994 <bitOffset>21</bitOffset>
54995 <bitWidth>1</bitWidth>
54996 <access>read-write</access>
54997 </field>
54998 <field>
54999 <name>EPTYP</name>
55000 <description>EPTYP</description>
55001 <bitOffset>18</bitOffset>
55002 <bitWidth>2</bitWidth>
55003 <access>read-write</access>
55004 </field>
55005 <field>
55006 <name>NAKSTS</name>
55007 <description>NAKSTS</description>
55008 <bitOffset>17</bitOffset>
55009 <bitWidth>1</bitWidth>
55010 <access>read-only</access>
55011 </field>
55012 <field>
55013 <name>EONUM_DPID</name>
55014 <description>EONUM/DPID</description>
55015 <bitOffset>16</bitOffset>
55016 <bitWidth>1</bitWidth>
55017 <access>read-only</access>
55018 </field>
55019 <field>
55020 <name>USBAEP</name>
55021 <description>USBAEP</description>
55022 <bitOffset>15</bitOffset>
55023 <bitWidth>1</bitWidth>
55024 <access>read-write</access>
55025 </field>
55026 <field>
55027 <name>MPSIZ</name>
55028 <description>MPSIZ</description>
55029 <bitOffset>0</bitOffset>
55030 <bitWidth>11</bitWidth>
55031 <access>read-write</access>
55032 </field>
55033 </fields>
55034 </register>
55035 <register>
55036 <name>OTG_FS_DOEPCTL0</name>
55037 <displayName>OTG_FS_DOEPCTL0</displayName>
55038 <description>device endpoint-0 control
55039 register</description>
55040 <addressOffset>0x300</addressOffset>
55041 <size>0x20</size>
55042 <resetValue>0x00008000</resetValue>
55043 <fields>
55044 <field>
55045 <name>EPENA</name>
55046 <description>EPENA</description>
55047 <bitOffset>31</bitOffset>
55048 <bitWidth>1</bitWidth>
55049 <access>write-only</access>
55050 </field>
55051 <field>
55052 <name>EPDIS</name>
55053 <description>EPDIS</description>
55054 <bitOffset>30</bitOffset>
55055 <bitWidth>1</bitWidth>
55056 <access>read-only</access>
55057 </field>
55058 <field>
55059 <name>SNAK</name>
55060 <description>SNAK</description>
55061 <bitOffset>27</bitOffset>
55062 <bitWidth>1</bitWidth>
55063 <access>write-only</access>
55064 </field>
55065 <field>
55066 <name>CNAK</name>
55067 <description>CNAK</description>
55068 <bitOffset>26</bitOffset>
55069 <bitWidth>1</bitWidth>
55070 <access>write-only</access>
55071 </field>
55072 <field>
55073 <name>Stall</name>
55074 <description>Stall</description>
55075 <bitOffset>21</bitOffset>
55076 <bitWidth>1</bitWidth>
55077 <access>read-write</access>
55078 </field>
55079 <field>
55080 <name>SNPM</name>
55081 <description>SNPM</description>
55082 <bitOffset>20</bitOffset>
55083 <bitWidth>1</bitWidth>
55084 <access>read-write</access>
55085 </field>
55086 <field>
55087 <name>EPTYP</name>
55088 <description>EPTYP</description>
55089 <bitOffset>18</bitOffset>
55090 <bitWidth>2</bitWidth>
55091 <access>read-only</access>
55092 </field>
55093 <field>
55094 <name>NAKSTS</name>
55095 <description>NAKSTS</description>
55096 <bitOffset>17</bitOffset>
55097 <bitWidth>1</bitWidth>
55098 <access>read-only</access>
55099 </field>
55100 <field>
55101 <name>USBAEP</name>
55102 <description>USBAEP</description>
55103 <bitOffset>15</bitOffset>
55104 <bitWidth>1</bitWidth>
55105 <access>read-only</access>
55106 </field>
55107 <field>
55108 <name>MPSIZ</name>
55109 <description>MPSIZ</description>
55110 <bitOffset>0</bitOffset>
55111 <bitWidth>2</bitWidth>
55112 <access>read-only</access>
55113 </field>
55114 </fields>
55115 </register>
55116 <register>
55117 <name>OTG_FS_DOEPCTL1</name>
55118 <displayName>OTG_FS_DOEPCTL1</displayName>
55119 <description>device endpoint-1 control
55120 register</description>
55121 <addressOffset>0x320</addressOffset>
55122 <size>0x20</size>
55123 <resetValue>0x00000000</resetValue>
55124 <fields>
55125 <field>
55126 <name>EPENA</name>
55127 <description>EPENA</description>
55128 <bitOffset>31</bitOffset>
55129 <bitWidth>1</bitWidth>
55130 <access>read-write</access>
55131 </field>
55132 <field>
55133 <name>EPDIS</name>
55134 <description>EPDIS</description>
55135 <bitOffset>30</bitOffset>
55136 <bitWidth>1</bitWidth>
55137 <access>read-write</access>
55138 </field>
55139 <field>
55140 <name>SODDFRM</name>
55141 <description>SODDFRM</description>
55142 <bitOffset>29</bitOffset>
55143 <bitWidth>1</bitWidth>
55144 <access>write-only</access>
55145 </field>
55146 <field>
55147 <name>SD0PID_SEVNFRM</name>
55148 <description>SD0PID/SEVNFRM</description>
55149 <bitOffset>28</bitOffset>
55150 <bitWidth>1</bitWidth>
55151 <access>write-only</access>
55152 </field>
55153 <field>
55154 <name>SNAK</name>
55155 <description>SNAK</description>
55156 <bitOffset>27</bitOffset>
55157 <bitWidth>1</bitWidth>
55158 <access>write-only</access>
55159 </field>
55160 <field>
55161 <name>CNAK</name>
55162 <description>CNAK</description>
55163 <bitOffset>26</bitOffset>
55164 <bitWidth>1</bitWidth>
55165 <access>write-only</access>
55166 </field>
55167 <field>
55168 <name>Stall</name>
55169 <description>Stall</description>
55170 <bitOffset>21</bitOffset>
55171 <bitWidth>1</bitWidth>
55172 <access>read-write</access>
55173 </field>
55174 <field>
55175 <name>SNPM</name>
55176 <description>SNPM</description>
55177 <bitOffset>20</bitOffset>
55178 <bitWidth>1</bitWidth>
55179 <access>read-write</access>
55180 </field>
55181 <field>
55182 <name>EPTYP</name>
55183 <description>EPTYP</description>
55184 <bitOffset>18</bitOffset>
55185 <bitWidth>2</bitWidth>
55186 <access>read-write</access>
55187 </field>
55188 <field>
55189 <name>NAKSTS</name>
55190 <description>NAKSTS</description>
55191 <bitOffset>17</bitOffset>
55192 <bitWidth>1</bitWidth>
55193 <access>read-only</access>
55194 </field>
55195 <field>
55196 <name>EONUM_DPID</name>
55197 <description>EONUM/DPID</description>
55198 <bitOffset>16</bitOffset>
55199 <bitWidth>1</bitWidth>
55200 <access>read-only</access>
55201 </field>
55202 <field>
55203 <name>USBAEP</name>
55204 <description>USBAEP</description>
55205 <bitOffset>15</bitOffset>
55206 <bitWidth>1</bitWidth>
55207 <access>read-write</access>
55208 </field>
55209 <field>
55210 <name>MPSIZ</name>
55211 <description>MPSIZ</description>
55212 <bitOffset>0</bitOffset>
55213 <bitWidth>11</bitWidth>
55214 <access>read-write</access>
55215 </field>
55216 </fields>
55217 </register>
55218 <register>
55219 <name>OTG_FS_DOEPCTL2</name>
55220 <displayName>OTG_FS_DOEPCTL2</displayName>
55221 <description>device endpoint-2 control
55222 register</description>
55223 <addressOffset>0x340</addressOffset>
55224 <size>0x20</size>
55225 <resetValue>0x00000000</resetValue>
55226 <fields>
55227 <field>
55228 <name>EPENA</name>
55229 <description>EPENA</description>
55230 <bitOffset>31</bitOffset>
55231 <bitWidth>1</bitWidth>
55232 <access>read-write</access>
55233 </field>
55234 <field>
55235 <name>EPDIS</name>
55236 <description>EPDIS</description>
55237 <bitOffset>30</bitOffset>
55238 <bitWidth>1</bitWidth>
55239 <access>read-write</access>
55240 </field>
55241 <field>
55242 <name>SODDFRM</name>
55243 <description>SODDFRM</description>
55244 <bitOffset>29</bitOffset>
55245 <bitWidth>1</bitWidth>
55246 <access>write-only</access>
55247 </field>
55248 <field>
55249 <name>SD0PID_SEVNFRM</name>
55250 <description>SD0PID/SEVNFRM</description>
55251 <bitOffset>28</bitOffset>
55252 <bitWidth>1</bitWidth>
55253 <access>write-only</access>
55254 </field>
55255 <field>
55256 <name>SNAK</name>
55257 <description>SNAK</description>
55258 <bitOffset>27</bitOffset>
55259 <bitWidth>1</bitWidth>
55260 <access>write-only</access>
55261 </field>
55262 <field>
55263 <name>CNAK</name>
55264 <description>CNAK</description>
55265 <bitOffset>26</bitOffset>
55266 <bitWidth>1</bitWidth>
55267 <access>write-only</access>
55268 </field>
55269 <field>
55270 <name>Stall</name>
55271 <description>Stall</description>
55272 <bitOffset>21</bitOffset>
55273 <bitWidth>1</bitWidth>
55274 <access>read-write</access>
55275 </field>
55276 <field>
55277 <name>SNPM</name>
55278 <description>SNPM</description>
55279 <bitOffset>20</bitOffset>
55280 <bitWidth>1</bitWidth>
55281 <access>read-write</access>
55282 </field>
55283 <field>
55284 <name>EPTYP</name>
55285 <description>EPTYP</description>
55286 <bitOffset>18</bitOffset>
55287 <bitWidth>2</bitWidth>
55288 <access>read-write</access>
55289 </field>
55290 <field>
55291 <name>NAKSTS</name>
55292 <description>NAKSTS</description>
55293 <bitOffset>17</bitOffset>
55294 <bitWidth>1</bitWidth>
55295 <access>read-only</access>
55296 </field>
55297 <field>
55298 <name>EONUM_DPID</name>
55299 <description>EONUM/DPID</description>
55300 <bitOffset>16</bitOffset>
55301 <bitWidth>1</bitWidth>
55302 <access>read-only</access>
55303 </field>
55304 <field>
55305 <name>USBAEP</name>
55306 <description>USBAEP</description>
55307 <bitOffset>15</bitOffset>
55308 <bitWidth>1</bitWidth>
55309 <access>read-write</access>
55310 </field>
55311 <field>
55312 <name>MPSIZ</name>
55313 <description>MPSIZ</description>
55314 <bitOffset>0</bitOffset>
55315 <bitWidth>11</bitWidth>
55316 <access>read-write</access>
55317 </field>
55318 </fields>
55319 </register>
55320 <register>
55321 <name>OTG_FS_DOEPCTL3</name>
55322 <displayName>OTG_FS_DOEPCTL3</displayName>
55323 <description>device endpoint-3 control
55324 register</description>
55325 <addressOffset>0x360</addressOffset>
55326 <size>0x20</size>
55327 <resetValue>0x00000000</resetValue>
55328 <fields>
55329 <field>
55330 <name>EPENA</name>
55331 <description>EPENA</description>
55332 <bitOffset>31</bitOffset>
55333 <bitWidth>1</bitWidth>
55334 <access>read-write</access>
55335 </field>
55336 <field>
55337 <name>EPDIS</name>
55338 <description>EPDIS</description>
55339 <bitOffset>30</bitOffset>
55340 <bitWidth>1</bitWidth>
55341 <access>read-write</access>
55342 </field>
55343 <field>
55344 <name>SODDFRM</name>
55345 <description>SODDFRM</description>
55346 <bitOffset>29</bitOffset>
55347 <bitWidth>1</bitWidth>
55348 <access>write-only</access>
55349 </field>
55350 <field>
55351 <name>SD0PID_SEVNFRM</name>
55352 <description>SD0PID/SEVNFRM</description>
55353 <bitOffset>28</bitOffset>
55354 <bitWidth>1</bitWidth>
55355 <access>write-only</access>
55356 </field>
55357 <field>
55358 <name>SNAK</name>
55359 <description>SNAK</description>
55360 <bitOffset>27</bitOffset>
55361 <bitWidth>1</bitWidth>
55362 <access>write-only</access>
55363 </field>
55364 <field>
55365 <name>CNAK</name>
55366 <description>CNAK</description>
55367 <bitOffset>26</bitOffset>
55368 <bitWidth>1</bitWidth>
55369 <access>write-only</access>
55370 </field>
55371 <field>
55372 <name>Stall</name>
55373 <description>Stall</description>
55374 <bitOffset>21</bitOffset>
55375 <bitWidth>1</bitWidth>
55376 <access>read-write</access>
55377 </field>
55378 <field>
55379 <name>SNPM</name>
55380 <description>SNPM</description>
55381 <bitOffset>20</bitOffset>
55382 <bitWidth>1</bitWidth>
55383 <access>read-write</access>
55384 </field>
55385 <field>
55386 <name>EPTYP</name>
55387 <description>EPTYP</description>
55388 <bitOffset>18</bitOffset>
55389 <bitWidth>2</bitWidth>
55390 <access>read-write</access>
55391 </field>
55392 <field>
55393 <name>NAKSTS</name>
55394 <description>NAKSTS</description>
55395 <bitOffset>17</bitOffset>
55396 <bitWidth>1</bitWidth>
55397 <access>read-only</access>
55398 </field>
55399 <field>
55400 <name>EONUM_DPID</name>
55401 <description>EONUM/DPID</description>
55402 <bitOffset>16</bitOffset>
55403 <bitWidth>1</bitWidth>
55404 <access>read-only</access>
55405 </field>
55406 <field>
55407 <name>USBAEP</name>
55408 <description>USBAEP</description>
55409 <bitOffset>15</bitOffset>
55410 <bitWidth>1</bitWidth>
55411 <access>read-write</access>
55412 </field>
55413 <field>
55414 <name>MPSIZ</name>
55415 <description>MPSIZ</description>
55416 <bitOffset>0</bitOffset>
55417 <bitWidth>11</bitWidth>
55418 <access>read-write</access>
55419 </field>
55420 </fields>
55421 </register>
55422 <register>
55423 <name>OTG_FS_DIEPINT0</name>
55424 <displayName>OTG_FS_DIEPINT0</displayName>
55425 <description>device endpoint-x interrupt
55426 register</description>
55427 <addressOffset>0x108</addressOffset>
55428 <size>0x20</size>
55429 <resetValue>0x00000080</resetValue>
55430 <fields>
55431 <field>
55432 <name>TXFE</name>
55433 <description>TXFE</description>
55434 <bitOffset>7</bitOffset>
55435 <bitWidth>1</bitWidth>
55436 <access>read-only</access>
55437 </field>
55438 <field>
55439 <name>INEPNE</name>
55440 <description>INEPNE</description>
55441 <bitOffset>6</bitOffset>
55442 <bitWidth>1</bitWidth>
55443 <access>read-write</access>
55444 </field>
55445 <field>
55446 <name>ITTXFE</name>
55447 <description>ITTXFE</description>
55448 <bitOffset>4</bitOffset>
55449 <bitWidth>1</bitWidth>
55450 <access>read-write</access>
55451 </field>
55452 <field>
55453 <name>TOC</name>
55454 <description>TOC</description>
55455 <bitOffset>3</bitOffset>
55456 <bitWidth>1</bitWidth>
55457 <access>read-write</access>
55458 </field>
55459 <field>
55460 <name>EPDISD</name>
55461 <description>EPDISD</description>
55462 <bitOffset>1</bitOffset>
55463 <bitWidth>1</bitWidth>
55464 <access>read-write</access>
55465 </field>
55466 <field>
55467 <name>XFRC</name>
55468 <description>XFRC</description>
55469 <bitOffset>0</bitOffset>
55470 <bitWidth>1</bitWidth>
55471 <access>read-write</access>
55472 </field>
55473 </fields>
55474 </register>
55475 <register>
55476 <name>OTG_FS_DIEPINT1</name>
55477 <displayName>OTG_FS_DIEPINT1</displayName>
55478 <description>device endpoint-1 interrupt
55479 register</description>
55480 <addressOffset>0x128</addressOffset>
55481 <size>0x20</size>
55482 <resetValue>0x00000080</resetValue>
55483 <fields>
55484 <field>
55485 <name>TXFE</name>
55486 <description>TXFE</description>
55487 <bitOffset>7</bitOffset>
55488 <bitWidth>1</bitWidth>
55489 <access>read-only</access>
55490 </field>
55491 <field>
55492 <name>INEPNE</name>
55493 <description>INEPNE</description>
55494 <bitOffset>6</bitOffset>
55495 <bitWidth>1</bitWidth>
55496 <access>read-write</access>
55497 </field>
55498 <field>
55499 <name>ITTXFE</name>
55500 <description>ITTXFE</description>
55501 <bitOffset>4</bitOffset>
55502 <bitWidth>1</bitWidth>
55503 <access>read-write</access>
55504 </field>
55505 <field>
55506 <name>TOC</name>
55507 <description>TOC</description>
55508 <bitOffset>3</bitOffset>
55509 <bitWidth>1</bitWidth>
55510 <access>read-write</access>
55511 </field>
55512 <field>
55513 <name>EPDISD</name>
55514 <description>EPDISD</description>
55515 <bitOffset>1</bitOffset>
55516 <bitWidth>1</bitWidth>
55517 <access>read-write</access>
55518 </field>
55519 <field>
55520 <name>XFRC</name>
55521 <description>XFRC</description>
55522 <bitOffset>0</bitOffset>
55523 <bitWidth>1</bitWidth>
55524 <access>read-write</access>
55525 </field>
55526 </fields>
55527 </register>
55528 <register>
55529 <name>OTG_FS_DIEPINT2</name>
55530 <displayName>OTG_FS_DIEPINT2</displayName>
55531 <description>device endpoint-2 interrupt
55532 register</description>
55533 <addressOffset>0x148</addressOffset>
55534 <size>0x20</size>
55535 <resetValue>0x00000080</resetValue>
55536 <fields>
55537 <field>
55538 <name>TXFE</name>
55539 <description>TXFE</description>
55540 <bitOffset>7</bitOffset>
55541 <bitWidth>1</bitWidth>
55542 <access>read-only</access>
55543 </field>
55544 <field>
55545 <name>INEPNE</name>
55546 <description>INEPNE</description>
55547 <bitOffset>6</bitOffset>
55548 <bitWidth>1</bitWidth>
55549 <access>read-write</access>
55550 </field>
55551 <field>
55552 <name>ITTXFE</name>
55553 <description>ITTXFE</description>
55554 <bitOffset>4</bitOffset>
55555 <bitWidth>1</bitWidth>
55556 <access>read-write</access>
55557 </field>
55558 <field>
55559 <name>TOC</name>
55560 <description>TOC</description>
55561 <bitOffset>3</bitOffset>
55562 <bitWidth>1</bitWidth>
55563 <access>read-write</access>
55564 </field>
55565 <field>
55566 <name>EPDISD</name>
55567 <description>EPDISD</description>
55568 <bitOffset>1</bitOffset>
55569 <bitWidth>1</bitWidth>
55570 <access>read-write</access>
55571 </field>
55572 <field>
55573 <name>XFRC</name>
55574 <description>XFRC</description>
55575 <bitOffset>0</bitOffset>
55576 <bitWidth>1</bitWidth>
55577 <access>read-write</access>
55578 </field>
55579 </fields>
55580 </register>
55581 <register>
55582 <name>OTG_FS_DIEPINT3</name>
55583 <displayName>OTG_FS_DIEPINT3</displayName>
55584 <description>device endpoint-3 interrupt
55585 register</description>
55586 <addressOffset>0x168</addressOffset>
55587 <size>0x20</size>
55588 <resetValue>0x00000080</resetValue>
55589 <fields>
55590 <field>
55591 <name>TXFE</name>
55592 <description>TXFE</description>
55593 <bitOffset>7</bitOffset>
55594 <bitWidth>1</bitWidth>
55595 <access>read-only</access>
55596 </field>
55597 <field>
55598 <name>INEPNE</name>
55599 <description>INEPNE</description>
55600 <bitOffset>6</bitOffset>
55601 <bitWidth>1</bitWidth>
55602 <access>read-write</access>
55603 </field>
55604 <field>
55605 <name>ITTXFE</name>
55606 <description>ITTXFE</description>
55607 <bitOffset>4</bitOffset>
55608 <bitWidth>1</bitWidth>
55609 <access>read-write</access>
55610 </field>
55611 <field>
55612 <name>TOC</name>
55613 <description>TOC</description>
55614 <bitOffset>3</bitOffset>
55615 <bitWidth>1</bitWidth>
55616 <access>read-write</access>
55617 </field>
55618 <field>
55619 <name>EPDISD</name>
55620 <description>EPDISD</description>
55621 <bitOffset>1</bitOffset>
55622 <bitWidth>1</bitWidth>
55623 <access>read-write</access>
55624 </field>
55625 <field>
55626 <name>XFRC</name>
55627 <description>XFRC</description>
55628 <bitOffset>0</bitOffset>
55629 <bitWidth>1</bitWidth>
55630 <access>read-write</access>
55631 </field>
55632 </fields>
55633 </register>
55634 <register>
55635 <name>OTG_FS_DOEPINT0</name>
55636 <displayName>OTG_FS_DOEPINT0</displayName>
55637 <description>device endpoint-0 interrupt
55638 register</description>
55639 <addressOffset>0x308</addressOffset>
55640 <size>0x20</size>
55641 <access>read-write</access>
55642 <resetValue>0x00000080</resetValue>
55643 <fields>
55644 <field>
55645 <name>B2BSTUP</name>
55646 <description>B2BSTUP</description>
55647 <bitOffset>6</bitOffset>
55648 <bitWidth>1</bitWidth>
55649 </field>
55650 <field>
55651 <name>OTEPDIS</name>
55652 <description>OTEPDIS</description>
55653 <bitOffset>4</bitOffset>
55654 <bitWidth>1</bitWidth>
55655 </field>
55656 <field>
55657 <name>STUP</name>
55658 <description>STUP</description>
55659 <bitOffset>3</bitOffset>
55660 <bitWidth>1</bitWidth>
55661 </field>
55662 <field>
55663 <name>EPDISD</name>
55664 <description>EPDISD</description>
55665 <bitOffset>1</bitOffset>
55666 <bitWidth>1</bitWidth>
55667 </field>
55668 <field>
55669 <name>XFRC</name>
55670 <description>XFRC</description>
55671 <bitOffset>0</bitOffset>
55672 <bitWidth>1</bitWidth>
55673 </field>
55674 </fields>
55675 </register>
55676 <register>
55677 <name>OTG_FS_DOEPINT1</name>
55678 <displayName>OTG_FS_DOEPINT1</displayName>
55679 <description>device endpoint-1 interrupt
55680 register</description>
55681 <addressOffset>0x328</addressOffset>
55682 <size>0x20</size>
55683 <access>read-write</access>
55684 <resetValue>0x00000080</resetValue>
55685 <fields>
55686 <field>
55687 <name>B2BSTUP</name>
55688 <description>B2BSTUP</description>
55689 <bitOffset>6</bitOffset>
55690 <bitWidth>1</bitWidth>
55691 </field>
55692 <field>
55693 <name>OTEPDIS</name>
55694 <description>OTEPDIS</description>
55695 <bitOffset>4</bitOffset>
55696 <bitWidth>1</bitWidth>
55697 </field>
55698 <field>
55699 <name>STUP</name>
55700 <description>STUP</description>
55701 <bitOffset>3</bitOffset>
55702 <bitWidth>1</bitWidth>
55703 </field>
55704 <field>
55705 <name>EPDISD</name>
55706 <description>EPDISD</description>
55707 <bitOffset>1</bitOffset>
55708 <bitWidth>1</bitWidth>
55709 </field>
55710 <field>
55711 <name>XFRC</name>
55712 <description>XFRC</description>
55713 <bitOffset>0</bitOffset>
55714 <bitWidth>1</bitWidth>
55715 </field>
55716 </fields>
55717 </register>
55718 <register>
55719 <name>OTG_FS_DOEPINT2</name>
55720 <displayName>OTG_FS_DOEPINT2</displayName>
55721 <description>device endpoint-2 interrupt
55722 register</description>
55723 <addressOffset>0x348</addressOffset>
55724 <size>0x20</size>
55725 <access>read-write</access>
55726 <resetValue>0x00000080</resetValue>
55727 <fields>
55728 <field>
55729 <name>B2BSTUP</name>
55730 <description>B2BSTUP</description>
55731 <bitOffset>6</bitOffset>
55732 <bitWidth>1</bitWidth>
55733 </field>
55734 <field>
55735 <name>OTEPDIS</name>
55736 <description>OTEPDIS</description>
55737 <bitOffset>4</bitOffset>
55738 <bitWidth>1</bitWidth>
55739 </field>
55740 <field>
55741 <name>STUP</name>
55742 <description>STUP</description>
55743 <bitOffset>3</bitOffset>
55744 <bitWidth>1</bitWidth>
55745 </field>
55746 <field>
55747 <name>EPDISD</name>
55748 <description>EPDISD</description>
55749 <bitOffset>1</bitOffset>
55750 <bitWidth>1</bitWidth>
55751 </field>
55752 <field>
55753 <name>XFRC</name>
55754 <description>XFRC</description>
55755 <bitOffset>0</bitOffset>
55756 <bitWidth>1</bitWidth>
55757 </field>
55758 </fields>
55759 </register>
55760 <register>
55761 <name>OTG_FS_DOEPINT3</name>
55762 <displayName>OTG_FS_DOEPINT3</displayName>
55763 <description>device endpoint-3 interrupt
55764 register</description>
55765 <addressOffset>0x368</addressOffset>
55766 <size>0x20</size>
55767 <access>read-write</access>
55768 <resetValue>0x00000080</resetValue>
55769 <fields>
55770 <field>
55771 <name>B2BSTUP</name>
55772 <description>B2BSTUP</description>
55773 <bitOffset>6</bitOffset>
55774 <bitWidth>1</bitWidth>
55775 </field>
55776 <field>
55777 <name>OTEPDIS</name>
55778 <description>OTEPDIS</description>
55779 <bitOffset>4</bitOffset>
55780 <bitWidth>1</bitWidth>
55781 </field>
55782 <field>
55783 <name>STUP</name>
55784 <description>STUP</description>
55785 <bitOffset>3</bitOffset>
55786 <bitWidth>1</bitWidth>
55787 </field>
55788 <field>
55789 <name>EPDISD</name>
55790 <description>EPDISD</description>
55791 <bitOffset>1</bitOffset>
55792 <bitWidth>1</bitWidth>
55793 </field>
55794 <field>
55795 <name>XFRC</name>
55796 <description>XFRC</description>
55797 <bitOffset>0</bitOffset>
55798 <bitWidth>1</bitWidth>
55799 </field>
55800 </fields>
55801 </register>
55802 <register>
55803 <name>OTG_FS_DIEPTSIZ0</name>
55804 <displayName>OTG_FS_DIEPTSIZ0</displayName>
55805 <description>device endpoint-0 transfer size
55806 register</description>
55807 <addressOffset>0x110</addressOffset>
55808 <size>0x20</size>
55809 <access>read-write</access>
55810 <resetValue>0x00000000</resetValue>
55811 <fields>
55812 <field>
55813 <name>PKTCNT</name>
55814 <description>Packet count</description>
55815 <bitOffset>19</bitOffset>
55816 <bitWidth>2</bitWidth>
55817 </field>
55818 <field>
55819 <name>XFRSIZ</name>
55820 <description>Transfer size</description>
55821 <bitOffset>0</bitOffset>
55822 <bitWidth>7</bitWidth>
55823 </field>
55824 </fields>
55825 </register>
55826 <register>
55827 <name>OTG_FS_DOEPTSIZ0</name>
55828 <displayName>OTG_FS_DOEPTSIZ0</displayName>
55829 <description>device OUT endpoint-0 transfer size
55830 register</description>
55831 <addressOffset>0x310</addressOffset>
55832 <size>0x20</size>
55833 <access>read-write</access>
55834 <resetValue>0x00000000</resetValue>
55835 <fields>
55836 <field>
55837 <name>STUPCNT</name>
55838 <description>SETUP packet count</description>
55839 <bitOffset>29</bitOffset>
55840 <bitWidth>2</bitWidth>
55841 </field>
55842 <field>
55843 <name>PKTCNT</name>
55844 <description>Packet count</description>
55845 <bitOffset>19</bitOffset>
55846 <bitWidth>1</bitWidth>
55847 </field>
55848 <field>
55849 <name>XFRSIZ</name>
55850 <description>Transfer size</description>
55851 <bitOffset>0</bitOffset>
55852 <bitWidth>7</bitWidth>
55853 </field>
55854 </fields>
55855 </register>
55856 <register>
55857 <name>OTG_FS_DIEPTSIZ1</name>
55858 <displayName>OTG_FS_DIEPTSIZ1</displayName>
55859 <description>device endpoint-1 transfer size
55860 register</description>
55861 <addressOffset>0x130</addressOffset>
55862 <size>0x20</size>
55863 <access>read-write</access>
55864 <resetValue>0x00000000</resetValue>
55865 <fields>
55866 <field>
55867 <name>MCNT</name>
55868 <description>Multi count</description>
55869 <bitOffset>29</bitOffset>
55870 <bitWidth>2</bitWidth>
55871 </field>
55872 <field>
55873 <name>PKTCNT</name>
55874 <description>Packet count</description>
55875 <bitOffset>19</bitOffset>
55876 <bitWidth>10</bitWidth>
55877 </field>
55878 <field>
55879 <name>XFRSIZ</name>
55880 <description>Transfer size</description>
55881 <bitOffset>0</bitOffset>
55882 <bitWidth>19</bitWidth>
55883 </field>
55884 </fields>
55885 </register>
55886 <register>
55887 <name>OTG_FS_DIEPTSIZ2</name>
55888 <displayName>OTG_FS_DIEPTSIZ2</displayName>
55889 <description>device endpoint-2 transfer size
55890 register</description>
55891 <addressOffset>0x150</addressOffset>
55892 <size>0x20</size>
55893 <access>read-write</access>
55894 <resetValue>0x00000000</resetValue>
55895 <fields>
55896 <field>
55897 <name>MCNT</name>
55898 <description>Multi count</description>
55899 <bitOffset>29</bitOffset>
55900 <bitWidth>2</bitWidth>
55901 </field>
55902 <field>
55903 <name>PKTCNT</name>
55904 <description>Packet count</description>
55905 <bitOffset>19</bitOffset>
55906 <bitWidth>10</bitWidth>
55907 </field>
55908 <field>
55909 <name>XFRSIZ</name>
55910 <description>Transfer size</description>
55911 <bitOffset>0</bitOffset>
55912 <bitWidth>19</bitWidth>
55913 </field>
55914 </fields>
55915 </register>
55916 <register>
55917 <name>OTG_FS_DIEPTSIZ3</name>
55918 <displayName>OTG_FS_DIEPTSIZ3</displayName>
55919 <description>device endpoint-3 transfer size
55920 register</description>
55921 <addressOffset>0x170</addressOffset>
55922 <size>0x20</size>
55923 <access>read-write</access>
55924 <resetValue>0x00000000</resetValue>
55925 <fields>
55926 <field>
55927 <name>MCNT</name>
55928 <description>Multi count</description>
55929 <bitOffset>29</bitOffset>
55930 <bitWidth>2</bitWidth>
55931 </field>
55932 <field>
55933 <name>PKTCNT</name>
55934 <description>Packet count</description>
55935 <bitOffset>19</bitOffset>
55936 <bitWidth>10</bitWidth>
55937 </field>
55938 <field>
55939 <name>XFRSIZ</name>
55940 <description>Transfer size</description>
55941 <bitOffset>0</bitOffset>
55942 <bitWidth>19</bitWidth>
55943 </field>
55944 </fields>
55945 </register>
55946 <register>
55947 <name>OTG_FS_DTXFSTS0</name>
55948 <displayName>OTG_FS_DTXFSTS0</displayName>
55949 <description>OTG_FS device IN endpoint transmit FIFO
55950 status register</description>
55951 <addressOffset>0x118</addressOffset>
55952 <size>0x20</size>
55953 <access>read-only</access>
55954 <resetValue>0x00000000</resetValue>
55955 <fields>
55956 <field>
55957 <name>INEPTFSAV</name>
55958 <description>IN endpoint TxFIFO space
55959 available</description>
55960 <bitOffset>0</bitOffset>
55961 <bitWidth>16</bitWidth>
55962 </field>
55963 </fields>
55964 </register>
55965 <register>
55966 <name>OTG_FS_DTXFSTS1</name>
55967 <displayName>OTG_FS_DTXFSTS1</displayName>
55968 <description>OTG_FS device IN endpoint transmit FIFO
55969 status register</description>
55970 <addressOffset>0x138</addressOffset>
55971 <size>0x20</size>
55972 <access>read-only</access>
55973 <resetValue>0x00000000</resetValue>
55974 <fields>
55975 <field>
55976 <name>INEPTFSAV</name>
55977 <description>IN endpoint TxFIFO space
55978 available</description>
55979 <bitOffset>0</bitOffset>
55980 <bitWidth>16</bitWidth>
55981 </field>
55982 </fields>
55983 </register>
55984 <register>
55985 <name>OTG_FS_DTXFSTS2</name>
55986 <displayName>OTG_FS_DTXFSTS2</displayName>
55987 <description>OTG_FS device IN endpoint transmit FIFO
55988 status register</description>
55989 <addressOffset>0x158</addressOffset>
55990 <size>0x20</size>
55991 <access>read-only</access>
55992 <resetValue>0x00000000</resetValue>
55993 <fields>
55994 <field>
55995 <name>INEPTFSAV</name>
55996 <description>IN endpoint TxFIFO space
55997 available</description>
55998 <bitOffset>0</bitOffset>
55999 <bitWidth>16</bitWidth>
56000 </field>
56001 </fields>
56002 </register>
56003 <register>
56004 <name>OTG_FS_DTXFSTS3</name>
56005 <displayName>OTG_FS_DTXFSTS3</displayName>
56006 <description>OTG_FS device IN endpoint transmit FIFO
56007 status register</description>
56008 <addressOffset>0x178</addressOffset>
56009 <size>0x20</size>
56010 <access>read-only</access>
56011 <resetValue>0x00000000</resetValue>
56012 <fields>
56013 <field>
56014 <name>INEPTFSAV</name>
56015 <description>IN endpoint TxFIFO space
56016 available</description>
56017 <bitOffset>0</bitOffset>
56018 <bitWidth>16</bitWidth>
56019 </field>
56020 </fields>
56021 </register>
56022 <register>
56023 <name>OTG_FS_DOEPTSIZ1</name>
56024 <displayName>OTG_FS_DOEPTSIZ1</displayName>
56025 <description>device OUT endpoint-1 transfer size
56026 register</description>
56027 <addressOffset>0x330</addressOffset>
56028 <size>0x20</size>
56029 <access>read-write</access>
56030 <resetValue>0x00000000</resetValue>
56031 <fields>
56032 <field>
56033 <name>RXDPID_STUPCNT</name>
56034 <description>Received data PID/SETUP packet
56035 count</description>
56036 <bitOffset>29</bitOffset>
56037 <bitWidth>2</bitWidth>
56038 </field>
56039 <field>
56040 <name>PKTCNT</name>
56041 <description>Packet count</description>
56042 <bitOffset>19</bitOffset>
56043 <bitWidth>10</bitWidth>
56044 </field>
56045 <field>
56046 <name>XFRSIZ</name>
56047 <description>Transfer size</description>
56048 <bitOffset>0</bitOffset>
56049 <bitWidth>19</bitWidth>
56050 </field>
56051 </fields>
56052 </register>
56053 <register>
56054 <name>OTG_FS_DOEPTSIZ2</name>
56055 <displayName>OTG_FS_DOEPTSIZ2</displayName>
56056 <description>device OUT endpoint-2 transfer size
56057 register</description>
56058 <addressOffset>0x350</addressOffset>
56059 <size>0x20</size>
56060 <access>read-write</access>
56061 <resetValue>0x00000000</resetValue>
56062 <fields>
56063 <field>
56064 <name>RXDPID_STUPCNT</name>
56065 <description>Received data PID/SETUP packet
56066 count</description>
56067 <bitOffset>29</bitOffset>
56068 <bitWidth>2</bitWidth>
56069 </field>
56070 <field>
56071 <name>PKTCNT</name>
56072 <description>Packet count</description>
56073 <bitOffset>19</bitOffset>
56074 <bitWidth>10</bitWidth>
56075 </field>
56076 <field>
56077 <name>XFRSIZ</name>
56078 <description>Transfer size</description>
56079 <bitOffset>0</bitOffset>
56080 <bitWidth>19</bitWidth>
56081 </field>
56082 </fields>
56083 </register>
56084 <register>
56085 <name>OTG_FS_DOEPTSIZ3</name>
56086 <displayName>OTG_FS_DOEPTSIZ3</displayName>
56087 <description>device OUT endpoint-3 transfer size
56088 register</description>
56089 <addressOffset>0x370</addressOffset>
56090 <size>0x20</size>
56091 <access>read-write</access>
56092 <resetValue>0x00000000</resetValue>
56093 <fields>
56094 <field>
56095 <name>RXDPID_STUPCNT</name>
56096 <description>Received data PID/SETUP packet
56097 count</description>
56098 <bitOffset>29</bitOffset>
56099 <bitWidth>2</bitWidth>
56100 </field>
56101 <field>
56102 <name>PKTCNT</name>
56103 <description>Packet count</description>
56104 <bitOffset>19</bitOffset>
56105 <bitWidth>10</bitWidth>
56106 </field>
56107 <field>
56108 <name>XFRSIZ</name>
56109 <description>Transfer size</description>
56110 <bitOffset>0</bitOffset>
56111 <bitWidth>19</bitWidth>
56112 </field>
56113 </fields>
56114 </register>
56115 <register>
56116 <name>OTG_FS_DIEPCTL4</name>
56117 <displayName>OTG_FS_DIEPCTL4</displayName>
56118 <description>OTG device endpoint-4 control
56119 register</description>
56120 <addressOffset>0x180</addressOffset>
56121 <size>0x20</size>
56122 <resetValue>0x00000000</resetValue>
56123 <fields>
56124 <field>
56125 <name>EPENA</name>
56126 <description>EPENA</description>
56127 <bitOffset>31</bitOffset>
56128 <bitWidth>1</bitWidth>
56129 <access>read-write</access>
56130 </field>
56131 <field>
56132 <name>EPDIS</name>
56133 <description>EPDIS</description>
56134 <bitOffset>30</bitOffset>
56135 <bitWidth>1</bitWidth>
56136 <access>read-write</access>
56137 </field>
56138 <field>
56139 <name>SODDFRM</name>
56140 <description>SODDFRM</description>
56141 <bitOffset>29</bitOffset>
56142 <bitWidth>1</bitWidth>
56143 <access>write-only</access>
56144 </field>
56145 <field>
56146 <name>SD0PID_SEVNFRM</name>
56147 <description>SD0PID/SEVNFRM</description>
56148 <bitOffset>28</bitOffset>
56149 <bitWidth>1</bitWidth>
56150 <access>write-only</access>
56151 </field>
56152 <field>
56153 <name>SNAK</name>
56154 <description>SNAK</description>
56155 <bitOffset>27</bitOffset>
56156 <bitWidth>1</bitWidth>
56157 <access>write-only</access>
56158 </field>
56159 <field>
56160 <name>CNAK</name>
56161 <description>CNAK</description>
56162 <bitOffset>26</bitOffset>
56163 <bitWidth>1</bitWidth>
56164 <access>write-only</access>
56165 </field>
56166 <field>
56167 <name>TXFNUM</name>
56168 <description>TXFNUM</description>
56169 <bitOffset>22</bitOffset>
56170 <bitWidth>4</bitWidth>
56171 <access>read-write</access>
56172 </field>
56173 <field>
56174 <name>Stall</name>
56175 <description>Stall</description>
56176 <bitOffset>21</bitOffset>
56177 <bitWidth>1</bitWidth>
56178 <access>read-write</access>
56179 </field>
56180 <field>
56181 <name>EPTYP</name>
56182 <description>EPTYP</description>
56183 <bitOffset>18</bitOffset>
56184 <bitWidth>2</bitWidth>
56185 <access>read-write</access>
56186 </field>
56187 <field>
56188 <name>NAKSTS</name>
56189 <description>NAKSTS</description>
56190 <bitOffset>17</bitOffset>
56191 <bitWidth>1</bitWidth>
56192 <access>read-only</access>
56193 </field>
56194 <field>
56195 <name>EONUM_DPID</name>
56196 <description>EONUM/DPID</description>
56197 <bitOffset>16</bitOffset>
56198 <bitWidth>1</bitWidth>
56199 <access>read-only</access>
56200 </field>
56201 <field>
56202 <name>USBAEP</name>
56203 <description>USBAEP</description>
56204 <bitOffset>15</bitOffset>
56205 <bitWidth>1</bitWidth>
56206 <access>read-write</access>
56207 </field>
56208 <field>
56209 <name>MPSIZ</name>
56210 <description>MPSIZ</description>
56211 <bitOffset>0</bitOffset>
56212 <bitWidth>11</bitWidth>
56213 <access>read-write</access>
56214 </field>
56215 </fields>
56216 </register>
56217 <register>
56218 <name>OTG_FS_DIEPINT4</name>
56219 <displayName>OTG_FS_DIEPINT4</displayName>
56220 <description>device endpoint-4 interrupt
56221 register</description>
56222 <addressOffset>0x188</addressOffset>
56223 <size>0x20</size>
56224 <resetValue>0x00000000</resetValue>
56225 <fields>
56226 <field>
56227 <name>TXFE</name>
56228 <description>TXFE</description>
56229 <bitOffset>7</bitOffset>
56230 <bitWidth>1</bitWidth>
56231 <access>read-only</access>
56232 </field>
56233 <field>
56234 <name>INEPNE</name>
56235 <description>INEPNE</description>
56236 <bitOffset>6</bitOffset>
56237 <bitWidth>1</bitWidth>
56238 <access>read-write</access>
56239 </field>
56240 <field>
56241 <name>ITTXFE</name>
56242 <description>ITTXFE</description>
56243 <bitOffset>4</bitOffset>
56244 <bitWidth>1</bitWidth>
56245 <access>read-write</access>
56246 </field>
56247 <field>
56248 <name>TOC</name>
56249 <description>TOC</description>
56250 <bitOffset>3</bitOffset>
56251 <bitWidth>1</bitWidth>
56252 <access>read-write</access>
56253 </field>
56254 <field>
56255 <name>EPDISD</name>
56256 <description>EPDISD</description>
56257 <bitOffset>1</bitOffset>
56258 <bitWidth>1</bitWidth>
56259 <access>read-write</access>
56260 </field>
56261 <field>
56262 <name>XFRC</name>
56263 <description>XFRC</description>
56264 <bitOffset>0</bitOffset>
56265 <bitWidth>1</bitWidth>
56266 <access>read-write</access>
56267 </field>
56268 </fields>
56269 </register>
56270 <register>
56271 <name>OTG_FS_DIEPTSIZ4</name>
56272 <displayName>OTG_FS_DIEPTSIZ4</displayName>
56273 <description>device endpoint-4 transfer size
56274 register</description>
56275 <addressOffset>0x194</addressOffset>
56276 <size>0x20</size>
56277 <access>read-write</access>
56278 <resetValue>0x00000000</resetValue>
56279 <fields>
56280 <field>
56281 <name>MCNT</name>
56282 <description>Multi count</description>
56283 <bitOffset>29</bitOffset>
56284 <bitWidth>2</bitWidth>
56285 </field>
56286 <field>
56287 <name>PKTCNT</name>
56288 <description>Packet count</description>
56289 <bitOffset>19</bitOffset>
56290 <bitWidth>10</bitWidth>
56291 </field>
56292 <field>
56293 <name>XFRSIZ</name>
56294 <description>Transfer size</description>
56295 <bitOffset>0</bitOffset>
56296 <bitWidth>19</bitWidth>
56297 </field>
56298 </fields>
56299 </register>
56300 <register>
56301 <name>OTG_FS_DTXFSTS4</name>
56302 <displayName>OTG_FS_DTXFSTS4</displayName>
56303 <description>OTG_FS device IN endpoint transmit FIFO
56304 status register</description>
56305 <addressOffset>0x19C</addressOffset>
56306 <size>0x20</size>
56307 <access>read-write</access>
56308 <resetValue>0x00000000</resetValue>
56309 <fields>
56310 <field>
56311 <name>INEPTFSAV</name>
56312 <description>IN endpoint TxFIFO space
56313 available</description>
56314 <bitOffset>0</bitOffset>
56315 <bitWidth>16</bitWidth>
56316 </field>
56317 </fields>
56318 </register>
56319 <register>
56320 <name>OTG_FS_DIEPCTL5</name>
56321 <displayName>OTG_FS_DIEPCTL5</displayName>
56322 <description>OTG device endpoint-5 control
56323 register</description>
56324 <addressOffset>0x1A0</addressOffset>
56325 <size>0x20</size>
56326 <resetValue>0x00000000</resetValue>
56327 <fields>
56328 <field>
56329 <name>EPENA</name>
56330 <description>EPENA</description>
56331 <bitOffset>31</bitOffset>
56332 <bitWidth>1</bitWidth>
56333 <access>read-write</access>
56334 </field>
56335 <field>
56336 <name>EPDIS</name>
56337 <description>EPDIS</description>
56338 <bitOffset>30</bitOffset>
56339 <bitWidth>1</bitWidth>
56340 <access>read-write</access>
56341 </field>
56342 <field>
56343 <name>SODDFRM</name>
56344 <description>SODDFRM</description>
56345 <bitOffset>29</bitOffset>
56346 <bitWidth>1</bitWidth>
56347 <access>write-only</access>
56348 </field>
56349 <field>
56350 <name>SD0PID_SEVNFRM</name>
56351 <description>SD0PID/SEVNFRM</description>
56352 <bitOffset>28</bitOffset>
56353 <bitWidth>1</bitWidth>
56354 <access>write-only</access>
56355 </field>
56356 <field>
56357 <name>SNAK</name>
56358 <description>SNAK</description>
56359 <bitOffset>27</bitOffset>
56360 <bitWidth>1</bitWidth>
56361 <access>write-only</access>
56362 </field>
56363 <field>
56364 <name>CNAK</name>
56365 <description>CNAK</description>
56366 <bitOffset>26</bitOffset>
56367 <bitWidth>1</bitWidth>
56368 <access>write-only</access>
56369 </field>
56370 <field>
56371 <name>TXFNUM</name>
56372 <description>TXFNUM</description>
56373 <bitOffset>22</bitOffset>
56374 <bitWidth>4</bitWidth>
56375 <access>read-write</access>
56376 </field>
56377 <field>
56378 <name>Stall</name>
56379 <description>Stall</description>
56380 <bitOffset>21</bitOffset>
56381 <bitWidth>1</bitWidth>
56382 <access>read-write</access>
56383 </field>
56384 <field>
56385 <name>EPTYP</name>
56386 <description>EPTYP</description>
56387 <bitOffset>18</bitOffset>
56388 <bitWidth>2</bitWidth>
56389 <access>read-write</access>
56390 </field>
56391 <field>
56392 <name>NAKSTS</name>
56393 <description>NAKSTS</description>
56394 <bitOffset>17</bitOffset>
56395 <bitWidth>1</bitWidth>
56396 <access>read-only</access>
56397 </field>
56398 <field>
56399 <name>EONUM_DPID</name>
56400 <description>EONUM/DPID</description>
56401 <bitOffset>16</bitOffset>
56402 <bitWidth>1</bitWidth>
56403 <access>read-only</access>
56404 </field>
56405 <field>
56406 <name>USBAEP</name>
56407 <description>USBAEP</description>
56408 <bitOffset>15</bitOffset>
56409 <bitWidth>1</bitWidth>
56410 <access>read-write</access>
56411 </field>
56412 <field>
56413 <name>MPSIZ</name>
56414 <description>MPSIZ</description>
56415 <bitOffset>0</bitOffset>
56416 <bitWidth>11</bitWidth>
56417 <access>read-write</access>
56418 </field>
56419 </fields>
56420 </register>
56421 <register>
56422 <name>OTG_FS_DIEPINT5</name>
56423 <displayName>OTG_FS_DIEPINT5</displayName>
56424 <description>device endpoint-5 interrupt
56425 register</description>
56426 <addressOffset>0x1A8</addressOffset>
56427 <size>0x20</size>
56428 <resetValue>0x00000000</resetValue>
56429 <fields>
56430 <field>
56431 <name>TXFE</name>
56432 <description>TXFE</description>
56433 <bitOffset>7</bitOffset>
56434 <bitWidth>1</bitWidth>
56435 <access>read-only</access>
56436 </field>
56437 <field>
56438 <name>INEPNE</name>
56439 <description>INEPNE</description>
56440 <bitOffset>6</bitOffset>
56441 <bitWidth>1</bitWidth>
56442 <access>read-write</access>
56443 </field>
56444 <field>
56445 <name>ITTXFE</name>
56446 <description>ITTXFE</description>
56447 <bitOffset>4</bitOffset>
56448 <bitWidth>1</bitWidth>
56449 <access>read-write</access>
56450 </field>
56451 <field>
56452 <name>TOC</name>
56453 <description>TOC</description>
56454 <bitOffset>3</bitOffset>
56455 <bitWidth>1</bitWidth>
56456 <access>read-write</access>
56457 </field>
56458 <field>
56459 <name>EPDISD</name>
56460 <description>EPDISD</description>
56461 <bitOffset>1</bitOffset>
56462 <bitWidth>1</bitWidth>
56463 <access>read-write</access>
56464 </field>
56465 <field>
56466 <name>XFRC</name>
56467 <description>XFRC</description>
56468 <bitOffset>0</bitOffset>
56469 <bitWidth>1</bitWidth>
56470 <access>read-write</access>
56471 </field>
56472 </fields>
56473 </register>
56474 <register>
56475 <name>OTG_FS_DIEPTSIZ55</name>
56476 <displayName>OTG_FS_DIEPTSIZ55</displayName>
56477 <description>device endpoint-5 transfer size
56478 register</description>
56479 <addressOffset>0x1B0</addressOffset>
56480 <size>0x20</size>
56481 <access>read-write</access>
56482 <resetValue>0x00000000</resetValue>
56483 <fields>
56484 <field>
56485 <name>MCNT</name>
56486 <description>Multi count</description>
56487 <bitOffset>29</bitOffset>
56488 <bitWidth>2</bitWidth>
56489 </field>
56490 <field>
56491 <name>PKTCNT</name>
56492 <description>Packet count</description>
56493 <bitOffset>19</bitOffset>
56494 <bitWidth>10</bitWidth>
56495 </field>
56496 <field>
56497 <name>XFRSIZ</name>
56498 <description>Transfer size</description>
56499 <bitOffset>0</bitOffset>
56500 <bitWidth>19</bitWidth>
56501 </field>
56502 </fields>
56503 </register>
56504 <register>
56505 <name>OTG_FS_DTXFSTS55</name>
56506 <displayName>OTG_FS_DTXFSTS55</displayName>
56507 <description>OTG_FS device IN endpoint transmit FIFO
56508 status register</description>
56509 <addressOffset>0x1B8</addressOffset>
56510 <size>0x20</size>
56511 <access>read-write</access>
56512 <resetValue>0x00000000</resetValue>
56513 <fields>
56514 <field>
56515 <name>INEPTFSAV</name>
56516 <description>IN endpoint TxFIFO space
56517 available</description>
56518 <bitOffset>0</bitOffset>
56519 <bitWidth>16</bitWidth>
56520 </field>
56521 </fields>
56522 </register>
56523 <register>
56524 <name>OTG_FS_DOEPCTL4</name>
56525 <displayName>OTG_FS_DOEPCTL4</displayName>
56526 <description>device endpoint-4 control
56527 register</description>
56528 <addressOffset>0x378</addressOffset>
56529 <size>0x20</size>
56530 <resetValue>0x00000000</resetValue>
56531 <fields>
56532 <field>
56533 <name>EPENA</name>
56534 <description>EPENA</description>
56535 <bitOffset>31</bitOffset>
56536 <bitWidth>1</bitWidth>
56537 <access>read-write</access>
56538 </field>
56539 <field>
56540 <name>EPDIS</name>
56541 <description>EPDIS</description>
56542 <bitOffset>30</bitOffset>
56543 <bitWidth>1</bitWidth>
56544 <access>read-write</access>
56545 </field>
56546 <field>
56547 <name>SODDFRM</name>
56548 <description>SODDFRM</description>
56549 <bitOffset>29</bitOffset>
56550 <bitWidth>1</bitWidth>
56551 <access>write-only</access>
56552 </field>
56553 <field>
56554 <name>SD0PID_SEVNFRM</name>
56555 <description>SD0PID/SEVNFRM</description>
56556 <bitOffset>28</bitOffset>
56557 <bitWidth>1</bitWidth>
56558 <access>write-only</access>
56559 </field>
56560 <field>
56561 <name>SNAK</name>
56562 <description>SNAK</description>
56563 <bitOffset>27</bitOffset>
56564 <bitWidth>1</bitWidth>
56565 <access>write-only</access>
56566 </field>
56567 <field>
56568 <name>CNAK</name>
56569 <description>CNAK</description>
56570 <bitOffset>26</bitOffset>
56571 <bitWidth>1</bitWidth>
56572 <access>write-only</access>
56573 </field>
56574 <field>
56575 <name>Stall</name>
56576 <description>Stall</description>
56577 <bitOffset>21</bitOffset>
56578 <bitWidth>1</bitWidth>
56579 <access>read-write</access>
56580 </field>
56581 <field>
56582 <name>SNPM</name>
56583 <description>SNPM</description>
56584 <bitOffset>20</bitOffset>
56585 <bitWidth>1</bitWidth>
56586 <access>read-write</access>
56587 </field>
56588 <field>
56589 <name>EPTYP</name>
56590 <description>EPTYP</description>
56591 <bitOffset>18</bitOffset>
56592 <bitWidth>2</bitWidth>
56593 <access>read-write</access>
56594 </field>
56595 <field>
56596 <name>NAKSTS</name>
56597 <description>NAKSTS</description>
56598 <bitOffset>17</bitOffset>
56599 <bitWidth>1</bitWidth>
56600 <access>read-only</access>
56601 </field>
56602 <field>
56603 <name>EONUM_DPID</name>
56604 <description>EONUM/DPID</description>
56605 <bitOffset>16</bitOffset>
56606 <bitWidth>1</bitWidth>
56607 <access>read-only</access>
56608 </field>
56609 <field>
56610 <name>USBAEP</name>
56611 <description>USBAEP</description>
56612 <bitOffset>15</bitOffset>
56613 <bitWidth>1</bitWidth>
56614 <access>read-write</access>
56615 </field>
56616 <field>
56617 <name>MPSIZ</name>
56618 <description>MPSIZ</description>
56619 <bitOffset>0</bitOffset>
56620 <bitWidth>11</bitWidth>
56621 <access>read-write</access>
56622 </field>
56623 </fields>
56624 </register>
56625 <register>
56626 <name>OTG_FS_DOEPINT4</name>
56627 <displayName>OTG_FS_DOEPINT4</displayName>
56628 <description>device endpoint-4 interrupt
56629 register</description>
56630 <addressOffset>0x380</addressOffset>
56631 <size>0x20</size>
56632 <access>read-write</access>
56633 <resetValue>0x00000000</resetValue>
56634 <fields>
56635 <field>
56636 <name>B2BSTUP</name>
56637 <description>B2BSTUP</description>
56638 <bitOffset>6</bitOffset>
56639 <bitWidth>1</bitWidth>
56640 </field>
56641 <field>
56642 <name>OTEPDIS</name>
56643 <description>OTEPDIS</description>
56644 <bitOffset>4</bitOffset>
56645 <bitWidth>1</bitWidth>
56646 </field>
56647 <field>
56648 <name>STUP</name>
56649 <description>STUP</description>
56650 <bitOffset>3</bitOffset>
56651 <bitWidth>1</bitWidth>
56652 </field>
56653 <field>
56654 <name>EPDISD</name>
56655 <description>EPDISD</description>
56656 <bitOffset>1</bitOffset>
56657 <bitWidth>1</bitWidth>
56658 </field>
56659 <field>
56660 <name>XFRC</name>
56661 <description>XFRC</description>
56662 <bitOffset>0</bitOffset>
56663 <bitWidth>1</bitWidth>
56664 </field>
56665 </fields>
56666 </register>
56667 <register>
56668 <name>OTG_FS_DOEPTSIZ4</name>
56669 <displayName>OTG_FS_DOEPTSIZ4</displayName>
56670 <description>device OUT endpoint-4 transfer size
56671 register</description>
56672 <addressOffset>0x388</addressOffset>
56673 <size>0x20</size>
56674 <access>read-write</access>
56675 <resetValue>0x00000000</resetValue>
56676 <fields>
56677 <field>
56678 <name>RXDPID_STUPCNT</name>
56679 <description>Received data PID/SETUP packet
56680 count</description>
56681 <bitOffset>29</bitOffset>
56682 <bitWidth>2</bitWidth>
56683 </field>
56684 <field>
56685 <name>PKTCNT</name>
56686 <description>Packet count</description>
56687 <bitOffset>19</bitOffset>
56688 <bitWidth>10</bitWidth>
56689 </field>
56690 <field>
56691 <name>XFRSIZ</name>
56692 <description>Transfer size</description>
56693 <bitOffset>0</bitOffset>
56694 <bitWidth>19</bitWidth>
56695 </field>
56696 </fields>
56697 </register>
56698 <register>
56699 <name>OTG_FS_DOEPCTL5</name>
56700 <displayName>OTG_FS_DOEPCTL5</displayName>
56701 <description>device endpoint-5 control
56702 register</description>
56703 <addressOffset>0x390</addressOffset>
56704 <size>0x20</size>
56705 <resetValue>0x00000000</resetValue>
56706 <fields>
56707 <field>
56708 <name>EPENA</name>
56709 <description>EPENA</description>
56710 <bitOffset>31</bitOffset>
56711 <bitWidth>1</bitWidth>
56712 <access>read-write</access>
56713 </field>
56714 <field>
56715 <name>EPDIS</name>
56716 <description>EPDIS</description>
56717 <bitOffset>30</bitOffset>
56718 <bitWidth>1</bitWidth>
56719 <access>read-write</access>
56720 </field>
56721 <field>
56722 <name>SODDFRM</name>
56723 <description>SODDFRM</description>
56724 <bitOffset>29</bitOffset>
56725 <bitWidth>1</bitWidth>
56726 <access>write-only</access>
56727 </field>
56728 <field>
56729 <name>SD0PID_SEVNFRM</name>
56730 <description>SD0PID/SEVNFRM</description>
56731 <bitOffset>28</bitOffset>
56732 <bitWidth>1</bitWidth>
56733 <access>write-only</access>
56734 </field>
56735 <field>
56736 <name>SNAK</name>
56737 <description>SNAK</description>
56738 <bitOffset>27</bitOffset>
56739 <bitWidth>1</bitWidth>
56740 <access>write-only</access>
56741 </field>
56742 <field>
56743 <name>CNAK</name>
56744 <description>CNAK</description>
56745 <bitOffset>26</bitOffset>
56746 <bitWidth>1</bitWidth>
56747 <access>write-only</access>
56748 </field>
56749 <field>
56750 <name>Stall</name>
56751 <description>Stall</description>
56752 <bitOffset>21</bitOffset>
56753 <bitWidth>1</bitWidth>
56754 <access>read-write</access>
56755 </field>
56756 <field>
56757 <name>SNPM</name>
56758 <description>SNPM</description>
56759 <bitOffset>20</bitOffset>
56760 <bitWidth>1</bitWidth>
56761 <access>read-write</access>
56762 </field>
56763 <field>
56764 <name>EPTYP</name>
56765 <description>EPTYP</description>
56766 <bitOffset>18</bitOffset>
56767 <bitWidth>2</bitWidth>
56768 <access>read-write</access>
56769 </field>
56770 <field>
56771 <name>NAKSTS</name>
56772 <description>NAKSTS</description>
56773 <bitOffset>17</bitOffset>
56774 <bitWidth>1</bitWidth>
56775 <access>read-only</access>
56776 </field>
56777 <field>
56778 <name>EONUM_DPID</name>
56779 <description>EONUM/DPID</description>
56780 <bitOffset>16</bitOffset>
56781 <bitWidth>1</bitWidth>
56782 <access>read-only</access>
56783 </field>
56784 <field>
56785 <name>USBAEP</name>
56786 <description>USBAEP</description>
56787 <bitOffset>15</bitOffset>
56788 <bitWidth>1</bitWidth>
56789 <access>read-write</access>
56790 </field>
56791 <field>
56792 <name>MPSIZ</name>
56793 <description>MPSIZ</description>
56794 <bitOffset>0</bitOffset>
56795 <bitWidth>11</bitWidth>
56796 <access>read-write</access>
56797 </field>
56798 </fields>
56799 </register>
56800 <register>
56801 <name>OTG_FS_DOEPINT5</name>
56802 <displayName>OTG_FS_DOEPINT5</displayName>
56803 <description>device endpoint-5 interrupt
56804 register</description>
56805 <addressOffset>0x398</addressOffset>
56806 <size>0x20</size>
56807 <access>read-write</access>
56808 <resetValue>0x00000000</resetValue>
56809 <fields>
56810 <field>
56811 <name>B2BSTUP</name>
56812 <description>B2BSTUP</description>
56813 <bitOffset>6</bitOffset>
56814 <bitWidth>1</bitWidth>
56815 </field>
56816 <field>
56817 <name>OTEPDIS</name>
56818 <description>OTEPDIS</description>
56819 <bitOffset>4</bitOffset>
56820 <bitWidth>1</bitWidth>
56821 </field>
56822 <field>
56823 <name>STUP</name>
56824 <description>STUP</description>
56825 <bitOffset>3</bitOffset>
56826 <bitWidth>1</bitWidth>
56827 </field>
56828 <field>
56829 <name>EPDISD</name>
56830 <description>EPDISD</description>
56831 <bitOffset>1</bitOffset>
56832 <bitWidth>1</bitWidth>
56833 </field>
56834 <field>
56835 <name>XFRC</name>
56836 <description>XFRC</description>
56837 <bitOffset>0</bitOffset>
56838 <bitWidth>1</bitWidth>
56839 </field>
56840 </fields>
56841 </register>
56842 <register>
56843 <name>OTG_FS_DOEPTSIZ5</name>
56844 <displayName>OTG_FS_DOEPTSIZ5</displayName>
56845 <description>device OUT endpoint-5 transfer size
56846 register</description>
56847 <addressOffset>0x3A0</addressOffset>
56848 <size>0x20</size>
56849 <access>read-write</access>
56850 <resetValue>0x00000000</resetValue>
56851 <fields>
56852 <field>
56853 <name>RXDPID_STUPCNT</name>
56854 <description>Received data PID/SETUP packet
56855 count</description>
56856 <bitOffset>29</bitOffset>
56857 <bitWidth>2</bitWidth>
56858 </field>
56859 <field>
56860 <name>PKTCNT</name>
56861 <description>Packet count</description>
56862 <bitOffset>19</bitOffset>
56863 <bitWidth>10</bitWidth>
56864 </field>
56865 <field>
56866 <name>XFRSIZ</name>
56867 <description>Transfer size</description>
56868 <bitOffset>0</bitOffset>
56869 <bitWidth>19</bitWidth>
56870 </field>
56871 </fields>
56872 </register>
56873 </registers>
56874 </peripheral>
56875 <peripheral>
56876 <name>OTG_FS_PWRCLK</name>
56877 <description>USB on the go full speed</description>
56878 <groupName>USB_OTG_FS</groupName>
56879 <baseAddress>0x50000E00</baseAddress>
56880 <addressBlock>
56881 <offset>0x0</offset>
56882 <size>0x400</size>
56883 <usage>registers</usage>
56884 </addressBlock>
56885 <interrupt>
56886 <name>OTG_FS_WKUP</name>
56887 <description>USB On-The-Go FS Wakeup through EXTI line
56888 interrupt</description>
56889 <value>42</value>
56890 </interrupt>
56891 <interrupt>
56892 <name>OTG_FS</name>
56893 <description>USB On The Go FS global
56894 interrupt</description>
56895 <value>67</value>
56896 </interrupt>
56897 <registers>
56898 <register>
56899 <name>OTG_FS_PCGCCTL</name>
56900 <displayName>OTG_FS_PCGCCTL</displayName>
56901 <description>OTG_FS power and clock gating control
56902 register (OTG_FS_PCGCCTL)</description>
56903 <addressOffset>0x0</addressOffset>
56904 <size>0x20</size>
56905 <access>read-write</access>
56906 <resetValue>0x00000000</resetValue>
56907 <fields>
56908 <field>
56909 <name>STPPCLK</name>
56910 <description>Stop PHY clock</description>
56911 <bitOffset>0</bitOffset>
56912 <bitWidth>1</bitWidth>
56913 </field>
56914 <field>
56915 <name>GATEHCLK</name>
56916 <description>Gate HCLK</description>
56917 <bitOffset>1</bitOffset>
56918 <bitWidth>1</bitWidth>
56919 </field>
56920 <field>
56921 <name>PHYSUSP</name>
56922 <description>PHY Suspended</description>
56923 <bitOffset>4</bitOffset>
56924 <bitWidth>1</bitWidth>
56925 </field>
56926 </fields>
56927 </register>
56928 </registers>
56929 </peripheral>
56930 <peripheral>
56931 <name>OTG_HS_GLOBAL</name>
56932 <description>USB on the go high speed</description>
56933 <groupName>USB_OTG_HS</groupName>
56934 <baseAddress>0x40040000</baseAddress>
56935 <addressBlock>
56936 <offset>0x0</offset>
56937 <size>0x400</size>
56938 <usage>registers</usage>
56939 </addressBlock>
56940 <registers>
56941 <register>
56942 <name>OTG_HS_GOTGCTL</name>
56943 <displayName>OTG_HS_GOTGCTL</displayName>
56944 <description>OTG_HS control and status
56945 register</description>
56946 <addressOffset>0x0</addressOffset>
56947 <size>32</size>
56948 <resetValue>0x00000800</resetValue>
56949 <fields>
56950 <field>
56951 <name>SRQSCS</name>
56952 <description>Session request success</description>
56953 <bitOffset>0</bitOffset>
56954 <bitWidth>1</bitWidth>
56955 <access>read-only</access>
56956 </field>
56957 <field>
56958 <name>SRQ</name>
56959 <description>Session request</description>
56960 <bitOffset>1</bitOffset>
56961 <bitWidth>1</bitWidth>
56962 <access>read-write</access>
56963 </field>
56964 <field>
56965 <name>HNGSCS</name>
56966 <description>Host negotiation success</description>
56967 <bitOffset>8</bitOffset>
56968 <bitWidth>1</bitWidth>
56969 <access>read-only</access>
56970 </field>
56971 <field>
56972 <name>HNPRQ</name>
56973 <description>HNP request</description>
56974 <bitOffset>9</bitOffset>
56975 <bitWidth>1</bitWidth>
56976 <access>read-write</access>
56977 </field>
56978 <field>
56979 <name>HSHNPEN</name>
56980 <description>Host set HNP enable</description>
56981 <bitOffset>10</bitOffset>
56982 <bitWidth>1</bitWidth>
56983 <access>read-write</access>
56984 </field>
56985 <field>
56986 <name>DHNPEN</name>
56987 <description>Device HNP enabled</description>
56988 <bitOffset>11</bitOffset>
56989 <bitWidth>1</bitWidth>
56990 <access>read-write</access>
56991 </field>
56992 <field>
56993 <name>CIDSTS</name>
56994 <description>Connector ID status</description>
56995 <bitOffset>16</bitOffset>
56996 <bitWidth>1</bitWidth>
56997 <access>read-only</access>
56998 </field>
56999 <field>
57000 <name>DBCT</name>
57001 <description>Long/short debounce time</description>
57002 <bitOffset>17</bitOffset>
57003 <bitWidth>1</bitWidth>
57004 <access>read-only</access>
57005 </field>
57006 <field>
57007 <name>ASVLD</name>
57008 <description>A-session valid</description>
57009 <bitOffset>18</bitOffset>
57010 <bitWidth>1</bitWidth>
57011 <access>read-only</access>
57012 </field>
57013 <field>
57014 <name>BSVLD</name>
57015 <description>B-session valid</description>
57016 <bitOffset>19</bitOffset>
57017 <bitWidth>1</bitWidth>
57018 <access>read-only</access>
57019 </field>
57020 <field>
57021 <name>EHEN</name>
57022 <description>Embedded host enable</description>
57023 <bitOffset>12</bitOffset>
57024 <bitWidth>1</bitWidth>
57025 <access>read-write</access>
57026 </field>
57027 </fields>
57028 </register>
57029 <register>
57030 <name>OTG_HS_GOTGINT</name>
57031 <displayName>OTG_HS_GOTGINT</displayName>
57032 <description>OTG_HS interrupt register</description>
57033 <addressOffset>0x4</addressOffset>
57034 <size>32</size>
57035 <access>read-write</access>
57036 <resetValue>0x0</resetValue>
57037 <fields>
57038 <field>
57039 <name>SEDET</name>
57040 <description>Session end detected</description>
57041 <bitOffset>2</bitOffset>
57042 <bitWidth>1</bitWidth>
57043 </field>
57044 <field>
57045 <name>SRSSCHG</name>
57046 <description>Session request success status
57047 change</description>
57048 <bitOffset>8</bitOffset>
57049 <bitWidth>1</bitWidth>
57050 </field>
57051 <field>
57052 <name>HNSSCHG</name>
57053 <description>Host negotiation success status
57054 change</description>
57055 <bitOffset>9</bitOffset>
57056 <bitWidth>1</bitWidth>
57057 </field>
57058 <field>
57059 <name>HNGDET</name>
57060 <description>Host negotiation detected</description>
57061 <bitOffset>17</bitOffset>
57062 <bitWidth>1</bitWidth>
57063 </field>
57064 <field>
57065 <name>ADTOCHG</name>
57066 <description>A-device timeout change</description>
57067 <bitOffset>18</bitOffset>
57068 <bitWidth>1</bitWidth>
57069 </field>
57070 <field>
57071 <name>DBCDNE</name>
57072 <description>Debounce done</description>
57073 <bitOffset>19</bitOffset>
57074 <bitWidth>1</bitWidth>
57075 </field>
57076 <field>
57077 <name>IDCHNG</name>
57078 <description>ID input pin changed</description>
57079 <bitOffset>20</bitOffset>
57080 <bitWidth>1</bitWidth>
57081 </field>
57082 </fields>
57083 </register>
57084 <register>
57085 <name>OTG_HS_GAHBCFG</name>
57086 <displayName>OTG_HS_GAHBCFG</displayName>
57087 <description>OTG_HS AHB configuration
57088 register</description>
57089 <addressOffset>0x8</addressOffset>
57090 <size>32</size>
57091 <access>read-write</access>
57092 <resetValue>0x0</resetValue>
57093 <fields>
57094 <field>
57095 <name>GINT</name>
57096 <description>Global interrupt mask</description>
57097 <bitOffset>0</bitOffset>
57098 <bitWidth>1</bitWidth>
57099 </field>
57100 <field>
57101 <name>HBSTLEN</name>
57102 <description>Burst length/type</description>
57103 <bitOffset>1</bitOffset>
57104 <bitWidth>4</bitWidth>
57105 </field>
57106 <field>
57107 <name>DMAEN</name>
57108 <description>DMA enable</description>
57109 <bitOffset>5</bitOffset>
57110 <bitWidth>1</bitWidth>
57111 </field>
57112 <field>
57113 <name>TXFELVL</name>
57114 <description>TxFIFO empty level</description>
57115 <bitOffset>7</bitOffset>
57116 <bitWidth>1</bitWidth>
57117 </field>
57118 <field>
57119 <name>PTXFELVL</name>
57120 <description>Periodic TxFIFO empty
57121 level</description>
57122 <bitOffset>8</bitOffset>
57123 <bitWidth>1</bitWidth>
57124 </field>
57125 </fields>
57126 </register>
57127 <register>
57128 <name>OTG_HS_GUSBCFG</name>
57129 <displayName>OTG_HS_GUSBCFG</displayName>
57130 <description>OTG_HS USB configuration
57131 register</description>
57132 <addressOffset>0xC</addressOffset>
57133 <size>32</size>
57134 <resetValue>0x00000A00</resetValue>
57135 <fields>
57136 <field>
57137 <name>TOCAL</name>
57138 <description>FS timeout calibration</description>
57139 <bitOffset>0</bitOffset>
57140 <bitWidth>3</bitWidth>
57141 <access>read-write</access>
57142 </field>
57143 <field>
57144 <name>PHYSEL</name>
57145 <description>USB 2.0 high-speed ULPI PHY or USB 1.1
57146 full-speed serial transceiver select</description>
57147 <bitOffset>6</bitOffset>
57148 <bitWidth>1</bitWidth>
57149 <access>write-only</access>
57150 </field>
57151 <field>
57152 <name>SRPCAP</name>
57153 <description>SRP-capable</description>
57154 <bitOffset>8</bitOffset>
57155 <bitWidth>1</bitWidth>
57156 <access>read-write</access>
57157 </field>
57158 <field>
57159 <name>HNPCAP</name>
57160 <description>HNP-capable</description>
57161 <bitOffset>9</bitOffset>
57162 <bitWidth>1</bitWidth>
57163 <access>read-write</access>
57164 </field>
57165 <field>
57166 <name>TRDT</name>
57167 <description>USB turnaround time</description>
57168 <bitOffset>10</bitOffset>
57169 <bitWidth>4</bitWidth>
57170 <access>read-write</access>
57171 </field>
57172 <field>
57173 <name>PHYLPCS</name>
57174 <description>PHY Low-power clock select</description>
57175 <bitOffset>15</bitOffset>
57176 <bitWidth>1</bitWidth>
57177 <access>read-write</access>
57178 </field>
57179 <field>
57180 <name>ULPIFSLS</name>
57181 <description>ULPI FS/LS select</description>
57182 <bitOffset>17</bitOffset>
57183 <bitWidth>1</bitWidth>
57184 <access>read-write</access>
57185 </field>
57186 <field>
57187 <name>ULPIAR</name>
57188 <description>ULPI Auto-resume</description>
57189 <bitOffset>18</bitOffset>
57190 <bitWidth>1</bitWidth>
57191 <access>read-write</access>
57192 </field>
57193 <field>
57194 <name>ULPICSM</name>
57195 <description>ULPI Clock SuspendM</description>
57196 <bitOffset>19</bitOffset>
57197 <bitWidth>1</bitWidth>
57198 <access>read-write</access>
57199 </field>
57200 <field>
57201 <name>ULPIEVBUSD</name>
57202 <description>ULPI External VBUS Drive</description>
57203 <bitOffset>20</bitOffset>
57204 <bitWidth>1</bitWidth>
57205 <access>read-write</access>
57206 </field>
57207 <field>
57208 <name>ULPIEVBUSI</name>
57209 <description>ULPI external VBUS
57210 indicator</description>
57211 <bitOffset>21</bitOffset>
57212 <bitWidth>1</bitWidth>
57213 <access>read-write</access>
57214 </field>
57215 <field>
57216 <name>TSDPS</name>
57217 <description>TermSel DLine pulsing
57218 selection</description>
57219 <bitOffset>22</bitOffset>
57220 <bitWidth>1</bitWidth>
57221 <access>read-write</access>
57222 </field>
57223 <field>
57224 <name>PCCI</name>
57225 <description>Indicator complement</description>
57226 <bitOffset>23</bitOffset>
57227 <bitWidth>1</bitWidth>
57228 <access>read-write</access>
57229 </field>
57230 <field>
57231 <name>PTCI</name>
57232 <description>Indicator pass through</description>
57233 <bitOffset>24</bitOffset>
57234 <bitWidth>1</bitWidth>
57235 <access>read-write</access>
57236 </field>
57237 <field>
57238 <name>ULPIIPD</name>
57239 <description>ULPI interface protect
57240 disable</description>
57241 <bitOffset>25</bitOffset>
57242 <bitWidth>1</bitWidth>
57243 <access>read-write</access>
57244 </field>
57245 <field>
57246 <name>FHMOD</name>
57247 <description>Forced host mode</description>
57248 <bitOffset>29</bitOffset>
57249 <bitWidth>1</bitWidth>
57250 <access>read-write</access>
57251 </field>
57252 <field>
57253 <name>FDMOD</name>
57254 <description>Forced peripheral mode</description>
57255 <bitOffset>30</bitOffset>
57256 <bitWidth>1</bitWidth>
57257 <access>read-write</access>
57258 </field>
57259 </fields>
57260 </register>
57261 <register>
57262 <name>OTG_HS_GRSTCTL</name>
57263 <displayName>OTG_HS_GRSTCTL</displayName>
57264 <description>OTG_HS reset register</description>
57265 <addressOffset>0x10</addressOffset>
57266 <size>32</size>
57267 <resetValue>0x20000000</resetValue>
57268 <fields>
57269 <field>
57270 <name>CSRST</name>
57271 <description>Core soft reset</description>
57272 <bitOffset>0</bitOffset>
57273 <bitWidth>1</bitWidth>
57274 <access>read-write</access>
57275 </field>
57276 <field>
57277 <name>HSRST</name>
57278 <description>HCLK soft reset</description>
57279 <bitOffset>1</bitOffset>
57280 <bitWidth>1</bitWidth>
57281 <access>read-write</access>
57282 </field>
57283 <field>
57284 <name>FCRST</name>
57285 <description>Host frame counter reset</description>
57286 <bitOffset>2</bitOffset>
57287 <bitWidth>1</bitWidth>
57288 <access>read-write</access>
57289 </field>
57290 <field>
57291 <name>RXFFLSH</name>
57292 <description>RxFIFO flush</description>
57293 <bitOffset>4</bitOffset>
57294 <bitWidth>1</bitWidth>
57295 <access>read-write</access>
57296 </field>
57297 <field>
57298 <name>TXFFLSH</name>
57299 <description>TxFIFO flush</description>
57300 <bitOffset>5</bitOffset>
57301 <bitWidth>1</bitWidth>
57302 <access>read-write</access>
57303 </field>
57304 <field>
57305 <name>TXFNUM</name>
57306 <description>TxFIFO number</description>
57307 <bitOffset>6</bitOffset>
57308 <bitWidth>5</bitWidth>
57309 <access>read-write</access>
57310 </field>
57311 <field>
57312 <name>AHBIDL</name>
57313 <description>AHB master idle</description>
57314 <bitOffset>31</bitOffset>
57315 <bitWidth>1</bitWidth>
57316 <access>read-only</access>
57317 </field>
57318 <field>
57319 <name>DMAREQ</name>
57320 <description>DMA request signal enabled for USB OTG
57321 HS</description>
57322 <bitOffset>30</bitOffset>
57323 <bitWidth>1</bitWidth>
57324 <access>read-only</access>
57325 </field>
57326 </fields>
57327 </register>
57328 <register>
57329 <name>OTG_HS_GINTSTS</name>
57330 <displayName>OTG_HS_GINTSTS</displayName>
57331 <description>OTG_HS core interrupt register</description>
57332 <addressOffset>0x14</addressOffset>
57333 <size>32</size>
57334 <resetValue>0x04000020</resetValue>
57335 <fields>
57336 <field>
57337 <name>CMOD</name>
57338 <description>Current mode of operation</description>
57339 <bitOffset>0</bitOffset>
57340 <bitWidth>1</bitWidth>
57341 <access>read-only</access>
57342 </field>
57343 <field>
57344 <name>MMIS</name>
57345 <description>Mode mismatch interrupt</description>
57346 <bitOffset>1</bitOffset>
57347 <bitWidth>1</bitWidth>
57348 <access>read-write</access>
57349 </field>
57350 <field>
57351 <name>OTGINT</name>
57352 <description>OTG interrupt</description>
57353 <bitOffset>2</bitOffset>
57354 <bitWidth>1</bitWidth>
57355 <access>read-only</access>
57356 </field>
57357 <field>
57358 <name>SOF</name>
57359 <description>Start of frame</description>
57360 <bitOffset>3</bitOffset>
57361 <bitWidth>1</bitWidth>
57362 <access>read-write</access>
57363 </field>
57364 <field>
57365 <name>RXFLVL</name>
57366 <description>RxFIFO nonempty</description>
57367 <bitOffset>4</bitOffset>
57368 <bitWidth>1</bitWidth>
57369 <access>read-only</access>
57370 </field>
57371 <field>
57372 <name>NPTXFE</name>
57373 <description>Nonperiodic TxFIFO empty</description>
57374 <bitOffset>5</bitOffset>
57375 <bitWidth>1</bitWidth>
57376 <access>read-only</access>
57377 </field>
57378 <field>
57379 <name>GINAKEFF</name>
57380 <description>Global IN nonperiodic NAK
57381 effective</description>
57382 <bitOffset>6</bitOffset>
57383 <bitWidth>1</bitWidth>
57384 <access>read-only</access>
57385 </field>
57386 <field>
57387 <name>BOUTNAKEFF</name>
57388 <description>Global OUT NAK effective</description>
57389 <bitOffset>7</bitOffset>
57390 <bitWidth>1</bitWidth>
57391 <access>read-only</access>
57392 </field>
57393 <field>
57394 <name>ESUSP</name>
57395 <description>Early suspend</description>
57396 <bitOffset>10</bitOffset>
57397 <bitWidth>1</bitWidth>
57398 <access>read-write</access>
57399 </field>
57400 <field>
57401 <name>USBSUSP</name>
57402 <description>USB suspend</description>
57403 <bitOffset>11</bitOffset>
57404 <bitWidth>1</bitWidth>
57405 <access>read-write</access>
57406 </field>
57407 <field>
57408 <name>USBRST</name>
57409 <description>USB reset</description>
57410 <bitOffset>12</bitOffset>
57411 <bitWidth>1</bitWidth>
57412 <access>read-write</access>
57413 </field>
57414 <field>
57415 <name>ENUMDNE</name>
57416 <description>Enumeration done</description>
57417 <bitOffset>13</bitOffset>
57418 <bitWidth>1</bitWidth>
57419 <access>read-write</access>
57420 </field>
57421 <field>
57422 <name>ISOODRP</name>
57423 <description>Isochronous OUT packet dropped
57424 interrupt</description>
57425 <bitOffset>14</bitOffset>
57426 <bitWidth>1</bitWidth>
57427 <access>read-write</access>
57428 </field>
57429 <field>
57430 <name>EOPF</name>
57431 <description>End of periodic frame
57432 interrupt</description>
57433 <bitOffset>15</bitOffset>
57434 <bitWidth>1</bitWidth>
57435 <access>read-write</access>
57436 </field>
57437 <field>
57438 <name>IEPINT</name>
57439 <description>IN endpoint interrupt</description>
57440 <bitOffset>18</bitOffset>
57441 <bitWidth>1</bitWidth>
57442 <access>read-only</access>
57443 </field>
57444 <field>
57445 <name>OEPINT</name>
57446 <description>OUT endpoint interrupt</description>
57447 <bitOffset>19</bitOffset>
57448 <bitWidth>1</bitWidth>
57449 <access>read-only</access>
57450 </field>
57451 <field>
57452 <name>IISOIXFR</name>
57453 <description>Incomplete isochronous IN
57454 transfer</description>
57455 <bitOffset>20</bitOffset>
57456 <bitWidth>1</bitWidth>
57457 <access>read-write</access>
57458 </field>
57459 <field>
57460 <name>PXFR_INCOMPISOOUT</name>
57461 <description>Incomplete periodic
57462 transfer</description>
57463 <bitOffset>21</bitOffset>
57464 <bitWidth>1</bitWidth>
57465 <access>read-write</access>
57466 </field>
57467 <field>
57468 <name>DATAFSUSP</name>
57469 <description>Data fetch suspended</description>
57470 <bitOffset>22</bitOffset>
57471 <bitWidth>1</bitWidth>
57472 <access>read-write</access>
57473 </field>
57474 <field>
57475 <name>HPRTINT</name>
57476 <description>Host port interrupt</description>
57477 <bitOffset>24</bitOffset>
57478 <bitWidth>1</bitWidth>
57479 <access>read-only</access>
57480 </field>
57481 <field>
57482 <name>HCINT</name>
57483 <description>Host channels interrupt</description>
57484 <bitOffset>25</bitOffset>
57485 <bitWidth>1</bitWidth>
57486 <access>read-only</access>
57487 </field>
57488 <field>
57489 <name>PTXFE</name>
57490 <description>Periodic TxFIFO empty</description>
57491 <bitOffset>26</bitOffset>
57492 <bitWidth>1</bitWidth>
57493 <access>read-only</access>
57494 </field>
57495 <field>
57496 <name>CIDSCHG</name>
57497 <description>Connector ID status change</description>
57498 <bitOffset>28</bitOffset>
57499 <bitWidth>1</bitWidth>
57500 <access>read-write</access>
57501 </field>
57502 <field>
57503 <name>DISCINT</name>
57504 <description>Disconnect detected
57505 interrupt</description>
57506 <bitOffset>29</bitOffset>
57507 <bitWidth>1</bitWidth>
57508 <access>read-write</access>
57509 </field>
57510 <field>
57511 <name>SRQINT</name>
57512 <description>Session request/new session detected
57513 interrupt</description>
57514 <bitOffset>30</bitOffset>
57515 <bitWidth>1</bitWidth>
57516 <access>read-write</access>
57517 </field>
57518 <field>
57519 <name>WKUINT</name>
57520 <description>Resume/remote wakeup detected
57521 interrupt</description>
57522 <bitOffset>31</bitOffset>
57523 <bitWidth>1</bitWidth>
57524 <access>read-write</access>
57525 </field>
57526 </fields>
57527 </register>
57528 <register>
57529 <name>OTG_HS_GINTMSK</name>
57530 <displayName>OTG_HS_GINTMSK</displayName>
57531 <description>OTG_HS interrupt mask register</description>
57532 <addressOffset>0x18</addressOffset>
57533 <size>32</size>
57534 <resetValue>0x0</resetValue>
57535 <fields>
57536 <field>
57537 <name>MMISM</name>
57538 <description>Mode mismatch interrupt
57539 mask</description>
57540 <bitOffset>1</bitOffset>
57541 <bitWidth>1</bitWidth>
57542 <access>read-write</access>
57543 </field>
57544 <field>
57545 <name>OTGINT</name>
57546 <description>OTG interrupt mask</description>
57547 <bitOffset>2</bitOffset>
57548 <bitWidth>1</bitWidth>
57549 <access>read-write</access>
57550 </field>
57551 <field>
57552 <name>SOFM</name>
57553 <description>Start of frame mask</description>
57554 <bitOffset>3</bitOffset>
57555 <bitWidth>1</bitWidth>
57556 <access>read-write</access>
57557 </field>
57558 <field>
57559 <name>RXFLVLM</name>
57560 <description>Receive FIFO nonempty mask</description>
57561 <bitOffset>4</bitOffset>
57562 <bitWidth>1</bitWidth>
57563 <access>read-write</access>
57564 </field>
57565 <field>
57566 <name>NPTXFEM</name>
57567 <description>Nonperiodic TxFIFO empty
57568 mask</description>
57569 <bitOffset>5</bitOffset>
57570 <bitWidth>1</bitWidth>
57571 <access>read-write</access>
57572 </field>
57573 <field>
57574 <name>GINAKEFFM</name>
57575 <description>Global nonperiodic IN NAK effective
57576 mask</description>
57577 <bitOffset>6</bitOffset>
57578 <bitWidth>1</bitWidth>
57579 <access>read-write</access>
57580 </field>
57581 <field>
57582 <name>GONAKEFFM</name>
57583 <description>Global OUT NAK effective
57584 mask</description>
57585 <bitOffset>7</bitOffset>
57586 <bitWidth>1</bitWidth>
57587 <access>read-write</access>
57588 </field>
57589 <field>
57590 <name>ESUSPM</name>
57591 <description>Early suspend mask</description>
57592 <bitOffset>10</bitOffset>
57593 <bitWidth>1</bitWidth>
57594 <access>read-write</access>
57595 </field>
57596 <field>
57597 <name>USBSUSPM</name>
57598 <description>USB suspend mask</description>
57599 <bitOffset>11</bitOffset>
57600 <bitWidth>1</bitWidth>
57601 <access>read-write</access>
57602 </field>
57603 <field>
57604 <name>USBRST</name>
57605 <description>USB reset mask</description>
57606 <bitOffset>12</bitOffset>
57607 <bitWidth>1</bitWidth>
57608 <access>read-write</access>
57609 </field>
57610 <field>
57611 <name>ENUMDNEM</name>
57612 <description>Enumeration done mask</description>
57613 <bitOffset>13</bitOffset>
57614 <bitWidth>1</bitWidth>
57615 <access>read-write</access>
57616 </field>
57617 <field>
57618 <name>ISOODRPM</name>
57619 <description>Isochronous OUT packet dropped interrupt
57620 mask</description>
57621 <bitOffset>14</bitOffset>
57622 <bitWidth>1</bitWidth>
57623 <access>read-write</access>
57624 </field>
57625 <field>
57626 <name>EOPFM</name>
57627 <description>End of periodic frame interrupt
57628 mask</description>
57629 <bitOffset>15</bitOffset>
57630 <bitWidth>1</bitWidth>
57631 <access>read-write</access>
57632 </field>
57633 <field>
57634 <name>IEPINT</name>
57635 <description>IN endpoints interrupt
57636 mask</description>
57637 <bitOffset>18</bitOffset>
57638 <bitWidth>1</bitWidth>
57639 <access>read-write</access>
57640 </field>
57641 <field>
57642 <name>OEPINT</name>
57643 <description>OUT endpoints interrupt
57644 mask</description>
57645 <bitOffset>19</bitOffset>
57646 <bitWidth>1</bitWidth>
57647 <access>read-write</access>
57648 </field>
57649 <field>
57650 <name>IISOIXFRM</name>
57651 <description>Incomplete isochronous IN transfer
57652 mask</description>
57653 <bitOffset>20</bitOffset>
57654 <bitWidth>1</bitWidth>
57655 <access>read-write</access>
57656 </field>
57657 <field>
57658 <name>PXFRM_IISOOXFRM</name>
57659 <description>Incomplete periodic transfer
57660 mask</description>
57661 <bitOffset>21</bitOffset>
57662 <bitWidth>1</bitWidth>
57663 <access>read-write</access>
57664 </field>
57665 <field>
57666 <name>FSUSPM</name>
57667 <description>Data fetch suspended mask</description>
57668 <bitOffset>22</bitOffset>
57669 <bitWidth>1</bitWidth>
57670 <access>read-write</access>
57671 </field>
57672 <field>
57673 <name>PRTIM</name>
57674 <description>Host port interrupt mask</description>
57675 <bitOffset>24</bitOffset>
57676 <bitWidth>1</bitWidth>
57677 <access>read-only</access>
57678 </field>
57679 <field>
57680 <name>HCIM</name>
57681 <description>Host channels interrupt
57682 mask</description>
57683 <bitOffset>25</bitOffset>
57684 <bitWidth>1</bitWidth>
57685 <access>read-write</access>
57686 </field>
57687 <field>
57688 <name>PTXFEM</name>
57689 <description>Periodic TxFIFO empty mask</description>
57690 <bitOffset>26</bitOffset>
57691 <bitWidth>1</bitWidth>
57692 <access>read-write</access>
57693 </field>
57694 <field>
57695 <name>CIDSCHGM</name>
57696 <description>Connector ID status change
57697 mask</description>
57698 <bitOffset>28</bitOffset>
57699 <bitWidth>1</bitWidth>
57700 <access>read-write</access>
57701 </field>
57702 <field>
57703 <name>DISCINT</name>
57704 <description>Disconnect detected interrupt
57705 mask</description>
57706 <bitOffset>29</bitOffset>
57707 <bitWidth>1</bitWidth>
57708 <access>read-write</access>
57709 </field>
57710 <field>
57711 <name>SRQIM</name>
57712 <description>Session request/new session detected
57713 interrupt mask</description>
57714 <bitOffset>30</bitOffset>
57715 <bitWidth>1</bitWidth>
57716 <access>read-write</access>
57717 </field>
57718 <field>
57719 <name>WUIM</name>
57720 <description>Resume/remote wakeup detected interrupt
57721 mask</description>
57722 <bitOffset>31</bitOffset>
57723 <bitWidth>1</bitWidth>
57724 <access>read-write</access>
57725 </field>
57726 <field>
57727 <name>RSTDE</name>
57728 <description>Reset detected interrupt
57729 mask</description>
57730 <bitOffset>23</bitOffset>
57731 <bitWidth>1</bitWidth>
57732 <access>read-write</access>
57733 </field>
57734 <field>
57735 <name>LPMINTM</name>
57736 <description>LPM interrupt mask</description>
57737 <bitOffset>27</bitOffset>
57738 <bitWidth>1</bitWidth>
57739 <access>read-write</access>
57740 </field>
57741 </fields>
57742 </register>
57743 <register>
57744 <name>OTG_HS_GRXSTSR_Host</name>
57745 <displayName>OTG_HS_GRXSTSR_Host</displayName>
57746 <description>OTG_HS Receive status debug read register
57747 (host mode)</description>
57748 <addressOffset>0x1C</addressOffset>
57749 <size>32</size>
57750 <access>read-only</access>
57751 <resetValue>0x0</resetValue>
57752 <fields>
57753 <field>
57754 <name>CHNUM</name>
57755 <description>Channel number</description>
57756 <bitOffset>0</bitOffset>
57757 <bitWidth>4</bitWidth>
57758 </field>
57759 <field>
57760 <name>BCNT</name>
57761 <description>Byte count</description>
57762 <bitOffset>4</bitOffset>
57763 <bitWidth>11</bitWidth>
57764 </field>
57765 <field>
57766 <name>DPID</name>
57767 <description>Data PID</description>
57768 <bitOffset>15</bitOffset>
57769 <bitWidth>2</bitWidth>
57770 </field>
57771 <field>
57772 <name>PKTSTS</name>
57773 <description>Packet status</description>
57774 <bitOffset>17</bitOffset>
57775 <bitWidth>4</bitWidth>
57776 </field>
57777 </fields>
57778 </register>
57779 <register>
57780 <name>OTG_HS_GRXSTSP_Host</name>
57781 <displayName>OTG_HS_GRXSTSP_Host</displayName>
57782 <description>OTG_HS status read and pop register (host
57783 mode)</description>
57784 <addressOffset>0x20</addressOffset>
57785 <size>32</size>
57786 <access>read-only</access>
57787 <resetValue>0x0</resetValue>
57788 <fields>
57789 <field>
57790 <name>CHNUM</name>
57791 <description>Channel number</description>
57792 <bitOffset>0</bitOffset>
57793 <bitWidth>4</bitWidth>
57794 </field>
57795 <field>
57796 <name>BCNT</name>
57797 <description>Byte count</description>
57798 <bitOffset>4</bitOffset>
57799 <bitWidth>11</bitWidth>
57800 </field>
57801 <field>
57802 <name>DPID</name>
57803 <description>Data PID</description>
57804 <bitOffset>15</bitOffset>
57805 <bitWidth>2</bitWidth>
57806 </field>
57807 <field>
57808 <name>PKTSTS</name>
57809 <description>Packet status</description>
57810 <bitOffset>17</bitOffset>
57811 <bitWidth>4</bitWidth>
57812 </field>
57813 </fields>
57814 </register>
57815 <register>
57816 <name>OTG_HS_GRXFSIZ</name>
57817 <displayName>OTG_HS_GRXFSIZ</displayName>
57818 <description>OTG_HS Receive FIFO size
57819 register</description>
57820 <addressOffset>0x24</addressOffset>
57821 <size>32</size>
57822 <access>read-write</access>
57823 <resetValue>0x00000200</resetValue>
57824 <fields>
57825 <field>
57826 <name>RXFD</name>
57827 <description>RxFIFO depth</description>
57828 <bitOffset>0</bitOffset>
57829 <bitWidth>16</bitWidth>
57830 </field>
57831 </fields>
57832 </register>
57833 <register>
57834 <name>OTG_HS_HNPTXFSIZ_Host</name>
57835 <displayName>OTG_HS_HNPTXFSIZ_Host</displayName>
57836 <description>OTG_HS nonperiodic transmit FIFO size
57837 register (host mode)</description>
57838 <addressOffset>0x28</addressOffset>
57839 <size>32</size>
57840 <access>read-write</access>
57841 <resetValue>0x00000200</resetValue>
57842 <fields>
57843 <field>
57844 <name>NPTXFSA</name>
57845 <description>Nonperiodic transmit RAM start
57846 address</description>
57847 <bitOffset>0</bitOffset>
57848 <bitWidth>16</bitWidth>
57849 </field>
57850 <field>
57851 <name>NPTXFD</name>
57852 <description>Nonperiodic TxFIFO depth</description>
57853 <bitOffset>16</bitOffset>
57854 <bitWidth>16</bitWidth>
57855 </field>
57856 </fields>
57857 </register>
57858 <register>
57859 <name>OTG_HS_DIEPTXF0_Device</name>
57860 <displayName>OTG_HS_DIEPTXF0_Device</displayName>
57861 <description>Endpoint 0 transmit FIFO size (peripheral
57862 mode)</description>
57863 <alternateRegister>OTG_HS_HNPTXFSIZ_Host</alternateRegister>
57864 <addressOffset>0x28</addressOffset>
57865 <size>32</size>
57866 <access>read-write</access>
57867 <resetValue>0x00000200</resetValue>
57868 <fields>
57869 <field>
57870 <name>TX0FSA</name>
57871 <description>Endpoint 0 transmit RAM start
57872 address</description>
57873 <bitOffset>0</bitOffset>
57874 <bitWidth>16</bitWidth>
57875 </field>
57876 <field>
57877 <name>TX0FD</name>
57878 <description>Endpoint 0 TxFIFO depth</description>
57879 <bitOffset>16</bitOffset>
57880 <bitWidth>16</bitWidth>
57881 </field>
57882 </fields>
57883 </register>
57884 <register>
57885 <name>OTG_HS_GNPTXSTS</name>
57886 <displayName>OTG_HS_GNPTXSTS</displayName>
57887 <description>OTG_HS nonperiodic transmit FIFO/queue
57888 status register</description>
57889 <addressOffset>0x2C</addressOffset>
57890 <size>32</size>
57891 <access>read-only</access>
57892 <resetValue>0x00080200</resetValue>
57893 <fields>
57894 <field>
57895 <name>NPTXFSAV</name>
57896 <description>Nonperiodic TxFIFO space
57897 available</description>
57898 <bitOffset>0</bitOffset>
57899 <bitWidth>16</bitWidth>
57900 </field>
57901 <field>
57902 <name>NPTQXSAV</name>
57903 <description>Nonperiodic transmit request queue space
57904 available</description>
57905 <bitOffset>16</bitOffset>
57906 <bitWidth>8</bitWidth>
57907 </field>
57908 <field>
57909 <name>NPTXQTOP</name>
57910 <description>Top of the nonperiodic transmit request
57911 queue</description>
57912 <bitOffset>24</bitOffset>
57913 <bitWidth>7</bitWidth>
57914 </field>
57915 </fields>
57916 </register>
57917 <register>
57918 <name>OTG_HS_GCCFG</name>
57919 <displayName>OTG_HS_GCCFG</displayName>
57920 <description>OTG_HS general core configuration
57921 register</description>
57922 <addressOffset>0x38</addressOffset>
57923 <size>32</size>
57924 <access>read-write</access>
57925 <resetValue>0x0</resetValue>
57926 <fields>
57927 <field>
57928 <name>PWRDWN</name>
57929 <description>Power down</description>
57930 <bitOffset>16</bitOffset>
57931 <bitWidth>1</bitWidth>
57932 </field>
57933 <field>
57934 <name>BCDEN</name>
57935 <description>Battery charging detector (BCD)
57936 enable</description>
57937 <bitOffset>17</bitOffset>
57938 <bitWidth>1</bitWidth>
57939 </field>
57940 <field>
57941 <name>DCDEN</name>
57942 <description>Data contact detection (DCD) mode
57943 enable</description>
57944 <bitOffset>18</bitOffset>
57945 <bitWidth>1</bitWidth>
57946 </field>
57947 <field>
57948 <name>PDEN</name>
57949 <description>Primary detection (PD) mode
57950 enable</description>
57951 <bitOffset>19</bitOffset>
57952 <bitWidth>1</bitWidth>
57953 </field>
57954 <field>
57955 <name>SDEN</name>
57956 <description>Secondary detection (SD) mode
57957 enable</description>
57958 <bitOffset>20</bitOffset>
57959 <bitWidth>1</bitWidth>
57960 </field>
57961 <field>
57962 <name>VBDEN</name>
57963 <description>USB VBUS detection enable</description>
57964 <bitOffset>21</bitOffset>
57965 <bitWidth>1</bitWidth>
57966 </field>
57967 <field>
57968 <name>DCDET</name>
57969 <description>Data contact detection (DCD)
57970 status</description>
57971 <bitOffset>0</bitOffset>
57972 <bitWidth>1</bitWidth>
57973 </field>
57974 <field>
57975 <name>PDET</name>
57976 <description>Primary detection (PD)
57977 status</description>
57978 <bitOffset>1</bitOffset>
57979 <bitWidth>1</bitWidth>
57980 </field>
57981 <field>
57982 <name>SDET</name>
57983 <description>Secondary detection (SD)
57984 status</description>
57985 <bitOffset>2</bitOffset>
57986 <bitWidth>1</bitWidth>
57987 </field>
57988 <field>
57989 <name>PS2DET</name>
57990 <description>DM pull-up detection
57991 status</description>
57992 <bitOffset>3</bitOffset>
57993 <bitWidth>1</bitWidth>
57994 </field>
57995 </fields>
57996 </register>
57997 <register>
57998 <name>OTG_HS_CID</name>
57999 <displayName>OTG_HS_CID</displayName>
58000 <description>OTG_HS core ID register</description>
58001 <addressOffset>0x3C</addressOffset>
58002 <size>32</size>
58003 <access>read-write</access>
58004 <resetValue>0x00001200</resetValue>
58005 <fields>
58006 <field>
58007 <name>PRODUCT_ID</name>
58008 <description>Product ID field</description>
58009 <bitOffset>0</bitOffset>
58010 <bitWidth>32</bitWidth>
58011 </field>
58012 </fields>
58013 </register>
58014 <register>
58015 <name>OTG_HS_HPTXFSIZ</name>
58016 <displayName>OTG_HS_HPTXFSIZ</displayName>
58017 <description>OTG_HS Host periodic transmit FIFO size
58018 register</description>
58019 <addressOffset>0x100</addressOffset>
58020 <size>32</size>
58021 <access>read-write</access>
58022 <resetValue>0x02000600</resetValue>
58023 <fields>
58024 <field>
58025 <name>PTXSA</name>
58026 <description>Host periodic TxFIFO start
58027 address</description>
58028 <bitOffset>0</bitOffset>
58029 <bitWidth>16</bitWidth>
58030 </field>
58031 <field>
58032 <name>PTXFD</name>
58033 <description>Host periodic TxFIFO depth</description>
58034 <bitOffset>16</bitOffset>
58035 <bitWidth>16</bitWidth>
58036 </field>
58037 </fields>
58038 </register>
58039 <register>
58040 <name>OTG_HS_DIEPTXF1</name>
58041 <displayName>OTG_HS_DIEPTXF1</displayName>
58042 <description>OTG_HS device IN endpoint transmit FIFO size
58043 register</description>
58044 <addressOffset>0x104</addressOffset>
58045 <size>32</size>
58046 <access>read-write</access>
58047 <resetValue>0x02000400</resetValue>
58048 <fields>
58049 <field>
58050 <name>INEPTXSA</name>
58051 <description>IN endpoint FIFOx transmit RAM start
58052 address</description>
58053 <bitOffset>0</bitOffset>
58054 <bitWidth>16</bitWidth>
58055 </field>
58056 <field>
58057 <name>INEPTXFD</name>
58058 <description>IN endpoint TxFIFO depth</description>
58059 <bitOffset>16</bitOffset>
58060 <bitWidth>16</bitWidth>
58061 </field>
58062 </fields>
58063 </register>
58064 <register>
58065 <name>OTG_HS_DIEPTXF2</name>
58066 <displayName>OTG_HS_DIEPTXF2</displayName>
58067 <description>OTG_HS device IN endpoint transmit FIFO size
58068 register</description>
58069 <addressOffset>0x108</addressOffset>
58070 <size>32</size>
58071 <access>read-write</access>
58072 <resetValue>0x02000400</resetValue>
58073 <fields>
58074 <field>
58075 <name>INEPTXSA</name>
58076 <description>IN endpoint FIFOx transmit RAM start
58077 address</description>
58078 <bitOffset>0</bitOffset>
58079 <bitWidth>16</bitWidth>
58080 </field>
58081 <field>
58082 <name>INEPTXFD</name>
58083 <description>IN endpoint TxFIFO depth</description>
58084 <bitOffset>16</bitOffset>
58085 <bitWidth>16</bitWidth>
58086 </field>
58087 </fields>
58088 </register>
58089 <register>
58090 <name>OTG_HS_DIEPTXF3</name>
58091 <displayName>OTG_HS_DIEPTXF3</displayName>
58092 <description>OTG_HS device IN endpoint transmit FIFO size
58093 register</description>
58094 <addressOffset>0x11C</addressOffset>
58095 <size>32</size>
58096 <access>read-write</access>
58097 <resetValue>0x02000400</resetValue>
58098 <fields>
58099 <field>
58100 <name>INEPTXSA</name>
58101 <description>IN endpoint FIFOx transmit RAM start
58102 address</description>
58103 <bitOffset>0</bitOffset>
58104 <bitWidth>16</bitWidth>
58105 </field>
58106 <field>
58107 <name>INEPTXFD</name>
58108 <description>IN endpoint TxFIFO depth</description>
58109 <bitOffset>16</bitOffset>
58110 <bitWidth>16</bitWidth>
58111 </field>
58112 </fields>
58113 </register>
58114 <register>
58115 <name>OTG_HS_DIEPTXF4</name>
58116 <displayName>OTG_HS_DIEPTXF4</displayName>
58117 <description>OTG_HS device IN endpoint transmit FIFO size
58118 register</description>
58119 <addressOffset>0x120</addressOffset>
58120 <size>32</size>
58121 <access>read-write</access>
58122 <resetValue>0x02000400</resetValue>
58123 <fields>
58124 <field>
58125 <name>INEPTXSA</name>
58126 <description>IN endpoint FIFOx transmit RAM start
58127 address</description>
58128 <bitOffset>0</bitOffset>
58129 <bitWidth>16</bitWidth>
58130 </field>
58131 <field>
58132 <name>INEPTXFD</name>
58133 <description>IN endpoint TxFIFO depth</description>
58134 <bitOffset>16</bitOffset>
58135 <bitWidth>16</bitWidth>
58136 </field>
58137 </fields>
58138 </register>
58139 <register>
58140 <name>OTG_HS_DIEPTXF5</name>
58141 <displayName>OTG_HS_DIEPTXF5</displayName>
58142 <description>OTG_HS device IN endpoint transmit FIFO size
58143 register</description>
58144 <addressOffset>0x124</addressOffset>
58145 <size>32</size>
58146 <access>read-write</access>
58147 <resetValue>0x02000400</resetValue>
58148 <fields>
58149 <field>
58150 <name>INEPTXSA</name>
58151 <description>IN endpoint FIFOx transmit RAM start
58152 address</description>
58153 <bitOffset>0</bitOffset>
58154 <bitWidth>16</bitWidth>
58155 </field>
58156 <field>
58157 <name>INEPTXFD</name>
58158 <description>IN endpoint TxFIFO depth</description>
58159 <bitOffset>16</bitOffset>
58160 <bitWidth>16</bitWidth>
58161 </field>
58162 </fields>
58163 </register>
58164 <register>
58165 <name>OTG_HS_DIEPTXF6</name>
58166 <displayName>OTG_HS_DIEPTXF6</displayName>
58167 <description>OTG_HS device IN endpoint transmit FIFO size
58168 register</description>
58169 <addressOffset>0x128</addressOffset>
58170 <size>32</size>
58171 <access>read-write</access>
58172 <resetValue>0x02000400</resetValue>
58173 <fields>
58174 <field>
58175 <name>INEPTXSA</name>
58176 <description>IN endpoint FIFOx transmit RAM start
58177 address</description>
58178 <bitOffset>0</bitOffset>
58179 <bitWidth>16</bitWidth>
58180 </field>
58181 <field>
58182 <name>INEPTXFD</name>
58183 <description>IN endpoint TxFIFO depth</description>
58184 <bitOffset>16</bitOffset>
58185 <bitWidth>16</bitWidth>
58186 </field>
58187 </fields>
58188 </register>
58189 <register>
58190 <name>OTG_HS_DIEPTXF7</name>
58191 <displayName>OTG_HS_DIEPTXF7</displayName>
58192 <description>OTG_HS device IN endpoint transmit FIFO size
58193 register</description>
58194 <addressOffset>0x12C</addressOffset>
58195 <size>32</size>
58196 <access>read-write</access>
58197 <resetValue>0x02000400</resetValue>
58198 <fields>
58199 <field>
58200 <name>INEPTXSA</name>
58201 <description>IN endpoint FIFOx transmit RAM start
58202 address</description>
58203 <bitOffset>0</bitOffset>
58204 <bitWidth>16</bitWidth>
58205 </field>
58206 <field>
58207 <name>INEPTXFD</name>
58208 <description>IN endpoint TxFIFO depth</description>
58209 <bitOffset>16</bitOffset>
58210 <bitWidth>16</bitWidth>
58211 </field>
58212 </fields>
58213 </register>
58214 <register>
58215 <name>OTG_HS_GRXSTSR_Device</name>
58216 <displayName>OTG_HS_GRXSTSR_Device</displayName>
58217 <description>OTG_HS Receive status debug read register
58218 (peripheral mode mode)</description>
58219 <alternateRegister>OTG_HS_GRXSTSR_Host</alternateRegister>
58220 <addressOffset>0x1C</addressOffset>
58221 <size>32</size>
58222 <access>read-only</access>
58223 <resetValue>0x0</resetValue>
58224 <fields>
58225 <field>
58226 <name>EPNUM</name>
58227 <description>Endpoint number</description>
58228 <bitOffset>0</bitOffset>
58229 <bitWidth>4</bitWidth>
58230 </field>
58231 <field>
58232 <name>BCNT</name>
58233 <description>Byte count</description>
58234 <bitOffset>4</bitOffset>
58235 <bitWidth>11</bitWidth>
58236 </field>
58237 <field>
58238 <name>DPID</name>
58239 <description>Data PID</description>
58240 <bitOffset>15</bitOffset>
58241 <bitWidth>2</bitWidth>
58242 </field>
58243 <field>
58244 <name>PKTSTS</name>
58245 <description>Packet status</description>
58246 <bitOffset>17</bitOffset>
58247 <bitWidth>4</bitWidth>
58248 </field>
58249 <field>
58250 <name>FRMNUM</name>
58251 <description>Frame number</description>
58252 <bitOffset>21</bitOffset>
58253 <bitWidth>4</bitWidth>
58254 </field>
58255 </fields>
58256 </register>
58257 <register>
58258 <name>OTG_HS_GRXSTSP_Device</name>
58259 <displayName>OTG_HS_GRXSTSP_Device</displayName>
58260 <description>OTG_HS status read and pop register
58261 (peripheral mode)</description>
58262 <alternateRegister>OTG_HS_GRXSTSP_Host</alternateRegister>
58263 <addressOffset>0x20</addressOffset>
58264 <size>32</size>
58265 <access>read-only</access>
58266 <resetValue>0x0</resetValue>
58267 <fields>
58268 <field>
58269 <name>EPNUM</name>
58270 <description>Endpoint number</description>
58271 <bitOffset>0</bitOffset>
58272 <bitWidth>4</bitWidth>
58273 </field>
58274 <field>
58275 <name>BCNT</name>
58276 <description>Byte count</description>
58277 <bitOffset>4</bitOffset>
58278 <bitWidth>11</bitWidth>
58279 </field>
58280 <field>
58281 <name>DPID</name>
58282 <description>Data PID</description>
58283 <bitOffset>15</bitOffset>
58284 <bitWidth>2</bitWidth>
58285 </field>
58286 <field>
58287 <name>PKTSTS</name>
58288 <description>Packet status</description>
58289 <bitOffset>17</bitOffset>
58290 <bitWidth>4</bitWidth>
58291 </field>
58292 <field>
58293 <name>FRMNUM</name>
58294 <description>Frame number</description>
58295 <bitOffset>21</bitOffset>
58296 <bitWidth>4</bitWidth>
58297 </field>
58298 </fields>
58299 </register>
58300 <register>
58301 <name>OTG_HS_GLPMCFG</name>
58302 <displayName>OTG_HS_GLPMCFG</displayName>
58303 <description>OTG core LPM configuration
58304 register</description>
58305 <addressOffset>0x54</addressOffset>
58306 <size>32</size>
58307 <resetValue>0x0</resetValue>
58308 <fields>
58309 <field>
58310 <name>LPMEN</name>
58311 <description>LPM support enable</description>
58312 <bitOffset>0</bitOffset>
58313 <bitWidth>1</bitWidth>
58314 <access>read-write</access>
58315 </field>
58316 <field>
58317 <name>LPMACK</name>
58318 <description>LPM token acknowledge
58319 enable</description>
58320 <bitOffset>1</bitOffset>
58321 <bitWidth>1</bitWidth>
58322 <access>read-write</access>
58323 </field>
58324 <field>
58325 <name>BESL</name>
58326 <description>Best effort service
58327 latency</description>
58328 <bitOffset>2</bitOffset>
58329 <bitWidth>4</bitWidth>
58330 <access>read-only</access>
58331 </field>
58332 <field>
58333 <name>REMWAKE</name>
58334 <description>bRemoteWake value</description>
58335 <bitOffset>6</bitOffset>
58336 <bitWidth>1</bitWidth>
58337 <access>read-only</access>
58338 </field>
58339 <field>
58340 <name>L1SSEN</name>
58341 <description>L1 Shallow Sleep enable</description>
58342 <bitOffset>7</bitOffset>
58343 <bitWidth>1</bitWidth>
58344 <access>read-write</access>
58345 </field>
58346 <field>
58347 <name>BESLTHRS</name>
58348 <description>BESL threshold</description>
58349 <bitOffset>8</bitOffset>
58350 <bitWidth>4</bitWidth>
58351 <access>read-write</access>
58352 </field>
58353 <field>
58354 <name>L1DSEN</name>
58355 <description>L1 deep sleep enable</description>
58356 <bitOffset>12</bitOffset>
58357 <bitWidth>1</bitWidth>
58358 <access>read-write</access>
58359 </field>
58360 <field>
58361 <name>LPMRST</name>
58362 <description>LPM response</description>
58363 <bitOffset>13</bitOffset>
58364 <bitWidth>2</bitWidth>
58365 <access>read-only</access>
58366 </field>
58367 <field>
58368 <name>SLPSTS</name>
58369 <description>Port sleep status</description>
58370 <bitOffset>15</bitOffset>
58371 <bitWidth>1</bitWidth>
58372 <access>read-only</access>
58373 </field>
58374 <field>
58375 <name>L1RSMOK</name>
58376 <description>Sleep State Resume OK</description>
58377 <bitOffset>16</bitOffset>
58378 <bitWidth>1</bitWidth>
58379 <access>read-only</access>
58380 </field>
58381 <field>
58382 <name>LPMCHIDX</name>
58383 <description>LPM Channel Index</description>
58384 <bitOffset>17</bitOffset>
58385 <bitWidth>4</bitWidth>
58386 <access>read-write</access>
58387 </field>
58388 <field>
58389 <name>LPMRCNT</name>
58390 <description>LPM retry count</description>
58391 <bitOffset>21</bitOffset>
58392 <bitWidth>3</bitWidth>
58393 <access>read-write</access>
58394 </field>
58395 <field>
58396 <name>SNDLPM</name>
58397 <description>Send LPM transaction</description>
58398 <bitOffset>24</bitOffset>
58399 <bitWidth>1</bitWidth>
58400 <access>read-write</access>
58401 </field>
58402 <field>
58403 <name>LPMRCNTSTS</name>
58404 <description>LPM retry count status</description>
58405 <bitOffset>25</bitOffset>
58406 <bitWidth>3</bitWidth>
58407 <access>read-only</access>
58408 </field>
58409 <field>
58410 <name>ENBESL</name>
58411 <description>Enable best effort service
58412 latency</description>
58413 <bitOffset>28</bitOffset>
58414 <bitWidth>1</bitWidth>
58415 <access>read-write</access>
58416 </field>
58417 </fields>
58418 </register>
58419 </registers>
58420 </peripheral>
58421 <peripheral>
58422 <name>OTG_HS_HOST</name>
58423 <description>USB on the go high speed</description>
58424 <groupName>USB_OTG_HS</groupName>
58425 <baseAddress>0x40040400</baseAddress>
58426 <addressBlock>
58427 <offset>0x0</offset>
58428 <size>0x400</size>
58429 <usage>registers</usage>
58430 </addressBlock>
58431 <registers>
58432 <register>
58433 <name>OTG_HS_HCFG</name>
58434 <displayName>OTG_HS_HCFG</displayName>
58435 <description>OTG_HS host configuration
58436 register</description>
58437 <addressOffset>0x0</addressOffset>
58438 <size>32</size>
58439 <resetValue>0x0</resetValue>
58440 <fields>
58441 <field>
58442 <name>FSLSPCS</name>
58443 <description>FS/LS PHY clock select</description>
58444 <bitOffset>0</bitOffset>
58445 <bitWidth>2</bitWidth>
58446 <access>read-write</access>
58447 </field>
58448 <field>
58449 <name>FSLSS</name>
58450 <description>FS- and LS-only support</description>
58451 <bitOffset>2</bitOffset>
58452 <bitWidth>1</bitWidth>
58453 <access>read-only</access>
58454 </field>
58455 </fields>
58456 </register>
58457 <register>
58458 <name>OTG_HS_HFIR</name>
58459 <displayName>OTG_HS_HFIR</displayName>
58460 <description>OTG_HS Host frame interval
58461 register</description>
58462 <addressOffset>0x4</addressOffset>
58463 <size>32</size>
58464 <access>read-write</access>
58465 <resetValue>0x0000EA60</resetValue>
58466 <fields>
58467 <field>
58468 <name>FRIVL</name>
58469 <description>Frame interval</description>
58470 <bitOffset>0</bitOffset>
58471 <bitWidth>16</bitWidth>
58472 </field>
58473 </fields>
58474 </register>
58475 <register>
58476 <name>OTG_HS_HFNUM</name>
58477 <displayName>OTG_HS_HFNUM</displayName>
58478 <description>OTG_HS host frame number/frame time
58479 remaining register</description>
58480 <addressOffset>0x8</addressOffset>
58481 <size>32</size>
58482 <access>read-only</access>
58483 <resetValue>0x00003FFF</resetValue>
58484 <fields>
58485 <field>
58486 <name>FRNUM</name>
58487 <description>Frame number</description>
58488 <bitOffset>0</bitOffset>
58489 <bitWidth>16</bitWidth>
58490 </field>
58491 <field>
58492 <name>FTREM</name>
58493 <description>Frame time remaining</description>
58494 <bitOffset>16</bitOffset>
58495 <bitWidth>16</bitWidth>
58496 </field>
58497 </fields>
58498 </register>
58499 <register>
58500 <name>OTG_HS_HPTXSTS</name>
58501 <displayName>OTG_HS_HPTXSTS</displayName>
58502 <description>OTG_HS_Host periodic transmit FIFO/queue
58503 status register</description>
58504 <addressOffset>0x10</addressOffset>
58505 <size>32</size>
58506 <resetValue>0x00080100</resetValue>
58507 <fields>
58508 <field>
58509 <name>PTXFSAVL</name>
58510 <description>Periodic transmit data FIFO space
58511 available</description>
58512 <bitOffset>0</bitOffset>
58513 <bitWidth>16</bitWidth>
58514 <access>read-write</access>
58515 </field>
58516 <field>
58517 <name>PTXQSAV</name>
58518 <description>Periodic transmit request queue space
58519 available</description>
58520 <bitOffset>16</bitOffset>
58521 <bitWidth>8</bitWidth>
58522 <access>read-only</access>
58523 </field>
58524 <field>
58525 <name>PTXQTOP</name>
58526 <description>Top of the periodic transmit request
58527 queue</description>
58528 <bitOffset>24</bitOffset>
58529 <bitWidth>8</bitWidth>
58530 <access>read-only</access>
58531 </field>
58532 </fields>
58533 </register>
58534 <register>
58535 <name>OTG_HS_HAINT</name>
58536 <displayName>OTG_HS_HAINT</displayName>
58537 <description>OTG_HS Host all channels interrupt
58538 register</description>
58539 <addressOffset>0x14</addressOffset>
58540 <size>32</size>
58541 <access>read-only</access>
58542 <resetValue>0x0</resetValue>
58543 <fields>
58544 <field>
58545 <name>HAINT</name>
58546 <description>Channel interrupts</description>
58547 <bitOffset>0</bitOffset>
58548 <bitWidth>16</bitWidth>
58549 </field>
58550 </fields>
58551 </register>
58552 <register>
58553 <name>OTG_HS_HAINTMSK</name>
58554 <displayName>OTG_HS_HAINTMSK</displayName>
58555 <description>OTG_HS host all channels interrupt mask
58556 register</description>
58557 <addressOffset>0x18</addressOffset>
58558 <size>32</size>
58559 <access>read-write</access>
58560 <resetValue>0x0</resetValue>
58561 <fields>
58562 <field>
58563 <name>HAINTM</name>
58564 <description>Channel interrupt mask</description>
58565 <bitOffset>0</bitOffset>
58566 <bitWidth>16</bitWidth>
58567 </field>
58568 </fields>
58569 </register>
58570 <register>
58571 <name>OTG_HS_HPRT</name>
58572 <displayName>OTG_HS_HPRT</displayName>
58573 <description>OTG_HS host port control and status
58574 register</description>
58575 <addressOffset>0x40</addressOffset>
58576 <size>32</size>
58577 <resetValue>0x0</resetValue>
58578 <fields>
58579 <field>
58580 <name>PCSTS</name>
58581 <description>Port connect status</description>
58582 <bitOffset>0</bitOffset>
58583 <bitWidth>1</bitWidth>
58584 <access>read-only</access>
58585 </field>
58586 <field>
58587 <name>PCDET</name>
58588 <description>Port connect detected</description>
58589 <bitOffset>1</bitOffset>
58590 <bitWidth>1</bitWidth>
58591 <access>read-write</access>
58592 </field>
58593 <field>
58594 <name>PENA</name>
58595 <description>Port enable</description>
58596 <bitOffset>2</bitOffset>
58597 <bitWidth>1</bitWidth>
58598 <access>read-write</access>
58599 </field>
58600 <field>
58601 <name>PENCHNG</name>
58602 <description>Port enable/disable change</description>
58603 <bitOffset>3</bitOffset>
58604 <bitWidth>1</bitWidth>
58605 <access>read-write</access>
58606 </field>
58607 <field>
58608 <name>POCA</name>
58609 <description>Port overcurrent active</description>
58610 <bitOffset>4</bitOffset>
58611 <bitWidth>1</bitWidth>
58612 <access>read-only</access>
58613 </field>
58614 <field>
58615 <name>POCCHNG</name>
58616 <description>Port overcurrent change</description>
58617 <bitOffset>5</bitOffset>
58618 <bitWidth>1</bitWidth>
58619 <access>read-write</access>
58620 </field>
58621 <field>
58622 <name>PRES</name>
58623 <description>Port resume</description>
58624 <bitOffset>6</bitOffset>
58625 <bitWidth>1</bitWidth>
58626 <access>read-write</access>
58627 </field>
58628 <field>
58629 <name>PSUSP</name>
58630 <description>Port suspend</description>
58631 <bitOffset>7</bitOffset>
58632 <bitWidth>1</bitWidth>
58633 <access>read-write</access>
58634 </field>
58635 <field>
58636 <name>PRST</name>
58637 <description>Port reset</description>
58638 <bitOffset>8</bitOffset>
58639 <bitWidth>1</bitWidth>
58640 <access>read-write</access>
58641 </field>
58642 <field>
58643 <name>PLSTS</name>
58644 <description>Port line status</description>
58645 <bitOffset>10</bitOffset>
58646 <bitWidth>2</bitWidth>
58647 <access>read-only</access>
58648 </field>
58649 <field>
58650 <name>PPWR</name>
58651 <description>Port power</description>
58652 <bitOffset>12</bitOffset>
58653 <bitWidth>1</bitWidth>
58654 <access>read-write</access>
58655 </field>
58656 <field>
58657 <name>PTCTL</name>
58658 <description>Port test control</description>
58659 <bitOffset>13</bitOffset>
58660 <bitWidth>4</bitWidth>
58661 <access>read-write</access>
58662 </field>
58663 <field>
58664 <name>PSPD</name>
58665 <description>Port speed</description>
58666 <bitOffset>17</bitOffset>
58667 <bitWidth>2</bitWidth>
58668 <access>read-only</access>
58669 </field>
58670 </fields>
58671 </register>
58672 <register>
58673 <name>OTG_HS_HCCHAR0</name>
58674 <displayName>OTG_HS_HCCHAR0</displayName>
58675 <description>OTG_HS host channel-0 characteristics
58676 register</description>
58677 <addressOffset>0x100</addressOffset>
58678 <size>32</size>
58679 <access>read-write</access>
58680 <resetValue>0x0</resetValue>
58681 <fields>
58682 <field>
58683 <name>MPSIZ</name>
58684 <description>Maximum packet size</description>
58685 <bitOffset>0</bitOffset>
58686 <bitWidth>11</bitWidth>
58687 </field>
58688 <field>
58689 <name>EPNUM</name>
58690 <description>Endpoint number</description>
58691 <bitOffset>11</bitOffset>
58692 <bitWidth>4</bitWidth>
58693 </field>
58694 <field>
58695 <name>EPDIR</name>
58696 <description>Endpoint direction</description>
58697 <bitOffset>15</bitOffset>
58698 <bitWidth>1</bitWidth>
58699 </field>
58700 <field>
58701 <name>LSDEV</name>
58702 <description>Low-speed device</description>
58703 <bitOffset>17</bitOffset>
58704 <bitWidth>1</bitWidth>
58705 </field>
58706 <field>
58707 <name>EPTYP</name>
58708 <description>Endpoint type</description>
58709 <bitOffset>18</bitOffset>
58710 <bitWidth>2</bitWidth>
58711 </field>
58712 <field>
58713 <name>MC</name>
58714 <description>Multi Count (MC) / Error Count
58715 (EC)</description>
58716 <bitOffset>20</bitOffset>
58717 <bitWidth>2</bitWidth>
58718 </field>
58719 <field>
58720 <name>DAD</name>
58721 <description>Device address</description>
58722 <bitOffset>22</bitOffset>
58723 <bitWidth>7</bitWidth>
58724 </field>
58725 <field>
58726 <name>ODDFRM</name>
58727 <description>Odd frame</description>
58728 <bitOffset>29</bitOffset>
58729 <bitWidth>1</bitWidth>
58730 </field>
58731 <field>
58732 <name>CHDIS</name>
58733 <description>Channel disable</description>
58734 <bitOffset>30</bitOffset>
58735 <bitWidth>1</bitWidth>
58736 </field>
58737 <field>
58738 <name>CHENA</name>
58739 <description>Channel enable</description>
58740 <bitOffset>31</bitOffset>
58741 <bitWidth>1</bitWidth>
58742 </field>
58743 </fields>
58744 </register>
58745 <register>
58746 <name>OTG_HS_HCCHAR1</name>
58747 <displayName>OTG_HS_HCCHAR1</displayName>
58748 <description>OTG_HS host channel-1 characteristics
58749 register</description>
58750 <addressOffset>0x120</addressOffset>
58751 <size>32</size>
58752 <access>read-write</access>
58753 <resetValue>0x0</resetValue>
58754 <fields>
58755 <field>
58756 <name>MPSIZ</name>
58757 <description>Maximum packet size</description>
58758 <bitOffset>0</bitOffset>
58759 <bitWidth>11</bitWidth>
58760 </field>
58761 <field>
58762 <name>EPNUM</name>
58763 <description>Endpoint number</description>
58764 <bitOffset>11</bitOffset>
58765 <bitWidth>4</bitWidth>
58766 </field>
58767 <field>
58768 <name>EPDIR</name>
58769 <description>Endpoint direction</description>
58770 <bitOffset>15</bitOffset>
58771 <bitWidth>1</bitWidth>
58772 </field>
58773 <field>
58774 <name>LSDEV</name>
58775 <description>Low-speed device</description>
58776 <bitOffset>17</bitOffset>
58777 <bitWidth>1</bitWidth>
58778 </field>
58779 <field>
58780 <name>EPTYP</name>
58781 <description>Endpoint type</description>
58782 <bitOffset>18</bitOffset>
58783 <bitWidth>2</bitWidth>
58784 </field>
58785 <field>
58786 <name>MC</name>
58787 <description>Multi Count (MC) / Error Count
58788 (EC)</description>
58789 <bitOffset>20</bitOffset>
58790 <bitWidth>2</bitWidth>
58791 </field>
58792 <field>
58793 <name>DAD</name>
58794 <description>Device address</description>
58795 <bitOffset>22</bitOffset>
58796 <bitWidth>7</bitWidth>
58797 </field>
58798 <field>
58799 <name>ODDFRM</name>
58800 <description>Odd frame</description>
58801 <bitOffset>29</bitOffset>
58802 <bitWidth>1</bitWidth>
58803 </field>
58804 <field>
58805 <name>CHDIS</name>
58806 <description>Channel disable</description>
58807 <bitOffset>30</bitOffset>
58808 <bitWidth>1</bitWidth>
58809 </field>
58810 <field>
58811 <name>CHENA</name>
58812 <description>Channel enable</description>
58813 <bitOffset>31</bitOffset>
58814 <bitWidth>1</bitWidth>
58815 </field>
58816 </fields>
58817 </register>
58818 <register>
58819 <name>OTG_HS_HCCHAR2</name>
58820 <displayName>OTG_HS_HCCHAR2</displayName>
58821 <description>OTG_HS host channel-2 characteristics
58822 register</description>
58823 <addressOffset>0x140</addressOffset>
58824 <size>32</size>
58825 <access>read-write</access>
58826 <resetValue>0x0</resetValue>
58827 <fields>
58828 <field>
58829 <name>MPSIZ</name>
58830 <description>Maximum packet size</description>
58831 <bitOffset>0</bitOffset>
58832 <bitWidth>11</bitWidth>
58833 </field>
58834 <field>
58835 <name>EPNUM</name>
58836 <description>Endpoint number</description>
58837 <bitOffset>11</bitOffset>
58838 <bitWidth>4</bitWidth>
58839 </field>
58840 <field>
58841 <name>EPDIR</name>
58842 <description>Endpoint direction</description>
58843 <bitOffset>15</bitOffset>
58844 <bitWidth>1</bitWidth>
58845 </field>
58846 <field>
58847 <name>LSDEV</name>
58848 <description>Low-speed device</description>
58849 <bitOffset>17</bitOffset>
58850 <bitWidth>1</bitWidth>
58851 </field>
58852 <field>
58853 <name>EPTYP</name>
58854 <description>Endpoint type</description>
58855 <bitOffset>18</bitOffset>
58856 <bitWidth>2</bitWidth>
58857 </field>
58858 <field>
58859 <name>MC</name>
58860 <description>Multi Count (MC) / Error Count
58861 (EC)</description>
58862 <bitOffset>20</bitOffset>
58863 <bitWidth>2</bitWidth>
58864 </field>
58865 <field>
58866 <name>DAD</name>
58867 <description>Device address</description>
58868 <bitOffset>22</bitOffset>
58869 <bitWidth>7</bitWidth>
58870 </field>
58871 <field>
58872 <name>ODDFRM</name>
58873 <description>Odd frame</description>
58874 <bitOffset>29</bitOffset>
58875 <bitWidth>1</bitWidth>
58876 </field>
58877 <field>
58878 <name>CHDIS</name>
58879 <description>Channel disable</description>
58880 <bitOffset>30</bitOffset>
58881 <bitWidth>1</bitWidth>
58882 </field>
58883 <field>
58884 <name>CHENA</name>
58885 <description>Channel enable</description>
58886 <bitOffset>31</bitOffset>
58887 <bitWidth>1</bitWidth>
58888 </field>
58889 </fields>
58890 </register>
58891 <register>
58892 <name>OTG_HS_HCCHAR3</name>
58893 <displayName>OTG_HS_HCCHAR3</displayName>
58894 <description>OTG_HS host channel-3 characteristics
58895 register</description>
58896 <addressOffset>0x160</addressOffset>
58897 <size>32</size>
58898 <access>read-write</access>
58899 <resetValue>0x0</resetValue>
58900 <fields>
58901 <field>
58902 <name>MPSIZ</name>
58903 <description>Maximum packet size</description>
58904 <bitOffset>0</bitOffset>
58905 <bitWidth>11</bitWidth>
58906 </field>
58907 <field>
58908 <name>EPNUM</name>
58909 <description>Endpoint number</description>
58910 <bitOffset>11</bitOffset>
58911 <bitWidth>4</bitWidth>
58912 </field>
58913 <field>
58914 <name>EPDIR</name>
58915 <description>Endpoint direction</description>
58916 <bitOffset>15</bitOffset>
58917 <bitWidth>1</bitWidth>
58918 </field>
58919 <field>
58920 <name>LSDEV</name>
58921 <description>Low-speed device</description>
58922 <bitOffset>17</bitOffset>
58923 <bitWidth>1</bitWidth>
58924 </field>
58925 <field>
58926 <name>EPTYP</name>
58927 <description>Endpoint type</description>
58928 <bitOffset>18</bitOffset>
58929 <bitWidth>2</bitWidth>
58930 </field>
58931 <field>
58932 <name>MC</name>
58933 <description>Multi Count (MC) / Error Count
58934 (EC)</description>
58935 <bitOffset>20</bitOffset>
58936 <bitWidth>2</bitWidth>
58937 </field>
58938 <field>
58939 <name>DAD</name>
58940 <description>Device address</description>
58941 <bitOffset>22</bitOffset>
58942 <bitWidth>7</bitWidth>
58943 </field>
58944 <field>
58945 <name>ODDFRM</name>
58946 <description>Odd frame</description>
58947 <bitOffset>29</bitOffset>
58948 <bitWidth>1</bitWidth>
58949 </field>
58950 <field>
58951 <name>CHDIS</name>
58952 <description>Channel disable</description>
58953 <bitOffset>30</bitOffset>
58954 <bitWidth>1</bitWidth>
58955 </field>
58956 <field>
58957 <name>CHENA</name>
58958 <description>Channel enable</description>
58959 <bitOffset>31</bitOffset>
58960 <bitWidth>1</bitWidth>
58961 </field>
58962 </fields>
58963 </register>
58964 <register>
58965 <name>OTG_HS_HCCHAR4</name>
58966 <displayName>OTG_HS_HCCHAR4</displayName>
58967 <description>OTG_HS host channel-4 characteristics
58968 register</description>
58969 <addressOffset>0x180</addressOffset>
58970 <size>32</size>
58971 <access>read-write</access>
58972 <resetValue>0x0</resetValue>
58973 <fields>
58974 <field>
58975 <name>MPSIZ</name>
58976 <description>Maximum packet size</description>
58977 <bitOffset>0</bitOffset>
58978 <bitWidth>11</bitWidth>
58979 </field>
58980 <field>
58981 <name>EPNUM</name>
58982 <description>Endpoint number</description>
58983 <bitOffset>11</bitOffset>
58984 <bitWidth>4</bitWidth>
58985 </field>
58986 <field>
58987 <name>EPDIR</name>
58988 <description>Endpoint direction</description>
58989 <bitOffset>15</bitOffset>
58990 <bitWidth>1</bitWidth>
58991 </field>
58992 <field>
58993 <name>LSDEV</name>
58994 <description>Low-speed device</description>
58995 <bitOffset>17</bitOffset>
58996 <bitWidth>1</bitWidth>
58997 </field>
58998 <field>
58999 <name>EPTYP</name>
59000 <description>Endpoint type</description>
59001 <bitOffset>18</bitOffset>
59002 <bitWidth>2</bitWidth>
59003 </field>
59004 <field>
59005 <name>MC</name>
59006 <description>Multi Count (MC) / Error Count
59007 (EC)</description>
59008 <bitOffset>20</bitOffset>
59009 <bitWidth>2</bitWidth>
59010 </field>
59011 <field>
59012 <name>DAD</name>
59013 <description>Device address</description>
59014 <bitOffset>22</bitOffset>
59015 <bitWidth>7</bitWidth>
59016 </field>
59017 <field>
59018 <name>ODDFRM</name>
59019 <description>Odd frame</description>
59020 <bitOffset>29</bitOffset>
59021 <bitWidth>1</bitWidth>
59022 </field>
59023 <field>
59024 <name>CHDIS</name>
59025 <description>Channel disable</description>
59026 <bitOffset>30</bitOffset>
59027 <bitWidth>1</bitWidth>
59028 </field>
59029 <field>
59030 <name>CHENA</name>
59031 <description>Channel enable</description>
59032 <bitOffset>31</bitOffset>
59033 <bitWidth>1</bitWidth>
59034 </field>
59035 </fields>
59036 </register>
59037 <register>
59038 <name>OTG_HS_HCCHAR5</name>
59039 <displayName>OTG_HS_HCCHAR5</displayName>
59040 <description>OTG_HS host channel-5 characteristics
59041 register</description>
59042 <addressOffset>0x1A0</addressOffset>
59043 <size>32</size>
59044 <access>read-write</access>
59045 <resetValue>0x0</resetValue>
59046 <fields>
59047 <field>
59048 <name>MPSIZ</name>
59049 <description>Maximum packet size</description>
59050 <bitOffset>0</bitOffset>
59051 <bitWidth>11</bitWidth>
59052 </field>
59053 <field>
59054 <name>EPNUM</name>
59055 <description>Endpoint number</description>
59056 <bitOffset>11</bitOffset>
59057 <bitWidth>4</bitWidth>
59058 </field>
59059 <field>
59060 <name>EPDIR</name>
59061 <description>Endpoint direction</description>
59062 <bitOffset>15</bitOffset>
59063 <bitWidth>1</bitWidth>
59064 </field>
59065 <field>
59066 <name>LSDEV</name>
59067 <description>Low-speed device</description>
59068 <bitOffset>17</bitOffset>
59069 <bitWidth>1</bitWidth>
59070 </field>
59071 <field>
59072 <name>EPTYP</name>
59073 <description>Endpoint type</description>
59074 <bitOffset>18</bitOffset>
59075 <bitWidth>2</bitWidth>
59076 </field>
59077 <field>
59078 <name>MC</name>
59079 <description>Multi Count (MC) / Error Count
59080 (EC)</description>
59081 <bitOffset>20</bitOffset>
59082 <bitWidth>2</bitWidth>
59083 </field>
59084 <field>
59085 <name>DAD</name>
59086 <description>Device address</description>
59087 <bitOffset>22</bitOffset>
59088 <bitWidth>7</bitWidth>
59089 </field>
59090 <field>
59091 <name>ODDFRM</name>
59092 <description>Odd frame</description>
59093 <bitOffset>29</bitOffset>
59094 <bitWidth>1</bitWidth>
59095 </field>
59096 <field>
59097 <name>CHDIS</name>
59098 <description>Channel disable</description>
59099 <bitOffset>30</bitOffset>
59100 <bitWidth>1</bitWidth>
59101 </field>
59102 <field>
59103 <name>CHENA</name>
59104 <description>Channel enable</description>
59105 <bitOffset>31</bitOffset>
59106 <bitWidth>1</bitWidth>
59107 </field>
59108 </fields>
59109 </register>
59110 <register>
59111 <name>OTG_HS_HCCHAR6</name>
59112 <displayName>OTG_HS_HCCHAR6</displayName>
59113 <description>OTG_HS host channel-6 characteristics
59114 register</description>
59115 <addressOffset>0x1C0</addressOffset>
59116 <size>32</size>
59117 <access>read-write</access>
59118 <resetValue>0x0</resetValue>
59119 <fields>
59120 <field>
59121 <name>MPSIZ</name>
59122 <description>Maximum packet size</description>
59123 <bitOffset>0</bitOffset>
59124 <bitWidth>11</bitWidth>
59125 </field>
59126 <field>
59127 <name>EPNUM</name>
59128 <description>Endpoint number</description>
59129 <bitOffset>11</bitOffset>
59130 <bitWidth>4</bitWidth>
59131 </field>
59132 <field>
59133 <name>EPDIR</name>
59134 <description>Endpoint direction</description>
59135 <bitOffset>15</bitOffset>
59136 <bitWidth>1</bitWidth>
59137 </field>
59138 <field>
59139 <name>LSDEV</name>
59140 <description>Low-speed device</description>
59141 <bitOffset>17</bitOffset>
59142 <bitWidth>1</bitWidth>
59143 </field>
59144 <field>
59145 <name>EPTYP</name>
59146 <description>Endpoint type</description>
59147 <bitOffset>18</bitOffset>
59148 <bitWidth>2</bitWidth>
59149 </field>
59150 <field>
59151 <name>MC</name>
59152 <description>Multi Count (MC) / Error Count
59153 (EC)</description>
59154 <bitOffset>20</bitOffset>
59155 <bitWidth>2</bitWidth>
59156 </field>
59157 <field>
59158 <name>DAD</name>
59159 <description>Device address</description>
59160 <bitOffset>22</bitOffset>
59161 <bitWidth>7</bitWidth>
59162 </field>
59163 <field>
59164 <name>ODDFRM</name>
59165 <description>Odd frame</description>
59166 <bitOffset>29</bitOffset>
59167 <bitWidth>1</bitWidth>
59168 </field>
59169 <field>
59170 <name>CHDIS</name>
59171 <description>Channel disable</description>
59172 <bitOffset>30</bitOffset>
59173 <bitWidth>1</bitWidth>
59174 </field>
59175 <field>
59176 <name>CHENA</name>
59177 <description>Channel enable</description>
59178 <bitOffset>31</bitOffset>
59179 <bitWidth>1</bitWidth>
59180 </field>
59181 </fields>
59182 </register>
59183 <register>
59184 <name>OTG_HS_HCCHAR7</name>
59185 <displayName>OTG_HS_HCCHAR7</displayName>
59186 <description>OTG_HS host channel-7 characteristics
59187 register</description>
59188 <addressOffset>0x1E0</addressOffset>
59189 <size>32</size>
59190 <access>read-write</access>
59191 <resetValue>0x0</resetValue>
59192 <fields>
59193 <field>
59194 <name>MPSIZ</name>
59195 <description>Maximum packet size</description>
59196 <bitOffset>0</bitOffset>
59197 <bitWidth>11</bitWidth>
59198 </field>
59199 <field>
59200 <name>EPNUM</name>
59201 <description>Endpoint number</description>
59202 <bitOffset>11</bitOffset>
59203 <bitWidth>4</bitWidth>
59204 </field>
59205 <field>
59206 <name>EPDIR</name>
59207 <description>Endpoint direction</description>
59208 <bitOffset>15</bitOffset>
59209 <bitWidth>1</bitWidth>
59210 </field>
59211 <field>
59212 <name>LSDEV</name>
59213 <description>Low-speed device</description>
59214 <bitOffset>17</bitOffset>
59215 <bitWidth>1</bitWidth>
59216 </field>
59217 <field>
59218 <name>EPTYP</name>
59219 <description>Endpoint type</description>
59220 <bitOffset>18</bitOffset>
59221 <bitWidth>2</bitWidth>
59222 </field>
59223 <field>
59224 <name>MC</name>
59225 <description>Multi Count (MC) / Error Count
59226 (EC)</description>
59227 <bitOffset>20</bitOffset>
59228 <bitWidth>2</bitWidth>
59229 </field>
59230 <field>
59231 <name>DAD</name>
59232 <description>Device address</description>
59233 <bitOffset>22</bitOffset>
59234 <bitWidth>7</bitWidth>
59235 </field>
59236 <field>
59237 <name>ODDFRM</name>
59238 <description>Odd frame</description>
59239 <bitOffset>29</bitOffset>
59240 <bitWidth>1</bitWidth>
59241 </field>
59242 <field>
59243 <name>CHDIS</name>
59244 <description>Channel disable</description>
59245 <bitOffset>30</bitOffset>
59246 <bitWidth>1</bitWidth>
59247 </field>
59248 <field>
59249 <name>CHENA</name>
59250 <description>Channel enable</description>
59251 <bitOffset>31</bitOffset>
59252 <bitWidth>1</bitWidth>
59253 </field>
59254 </fields>
59255 </register>
59256 <register>
59257 <name>OTG_HS_HCCHAR8</name>
59258 <displayName>OTG_HS_HCCHAR8</displayName>
59259 <description>OTG_HS host channel-8 characteristics
59260 register</description>
59261 <addressOffset>0x200</addressOffset>
59262 <size>32</size>
59263 <access>read-write</access>
59264 <resetValue>0x0</resetValue>
59265 <fields>
59266 <field>
59267 <name>MPSIZ</name>
59268 <description>Maximum packet size</description>
59269 <bitOffset>0</bitOffset>
59270 <bitWidth>11</bitWidth>
59271 </field>
59272 <field>
59273 <name>EPNUM</name>
59274 <description>Endpoint number</description>
59275 <bitOffset>11</bitOffset>
59276 <bitWidth>4</bitWidth>
59277 </field>
59278 <field>
59279 <name>EPDIR</name>
59280 <description>Endpoint direction</description>
59281 <bitOffset>15</bitOffset>
59282 <bitWidth>1</bitWidth>
59283 </field>
59284 <field>
59285 <name>LSDEV</name>
59286 <description>Low-speed device</description>
59287 <bitOffset>17</bitOffset>
59288 <bitWidth>1</bitWidth>
59289 </field>
59290 <field>
59291 <name>EPTYP</name>
59292 <description>Endpoint type</description>
59293 <bitOffset>18</bitOffset>
59294 <bitWidth>2</bitWidth>
59295 </field>
59296 <field>
59297 <name>MC</name>
59298 <description>Multi Count (MC) / Error Count
59299 (EC)</description>
59300 <bitOffset>20</bitOffset>
59301 <bitWidth>2</bitWidth>
59302 </field>
59303 <field>
59304 <name>DAD</name>
59305 <description>Device address</description>
59306 <bitOffset>22</bitOffset>
59307 <bitWidth>7</bitWidth>
59308 </field>
59309 <field>
59310 <name>ODDFRM</name>
59311 <description>Odd frame</description>
59312 <bitOffset>29</bitOffset>
59313 <bitWidth>1</bitWidth>
59314 </field>
59315 <field>
59316 <name>CHDIS</name>
59317 <description>Channel disable</description>
59318 <bitOffset>30</bitOffset>
59319 <bitWidth>1</bitWidth>
59320 </field>
59321 <field>
59322 <name>CHENA</name>
59323 <description>Channel enable</description>
59324 <bitOffset>31</bitOffset>
59325 <bitWidth>1</bitWidth>
59326 </field>
59327 </fields>
59328 </register>
59329 <register>
59330 <name>OTG_HS_HCCHAR9</name>
59331 <displayName>OTG_HS_HCCHAR9</displayName>
59332 <description>OTG_HS host channel-9 characteristics
59333 register</description>
59334 <addressOffset>0x220</addressOffset>
59335 <size>32</size>
59336 <access>read-write</access>
59337 <resetValue>0x0</resetValue>
59338 <fields>
59339 <field>
59340 <name>MPSIZ</name>
59341 <description>Maximum packet size</description>
59342 <bitOffset>0</bitOffset>
59343 <bitWidth>11</bitWidth>
59344 </field>
59345 <field>
59346 <name>EPNUM</name>
59347 <description>Endpoint number</description>
59348 <bitOffset>11</bitOffset>
59349 <bitWidth>4</bitWidth>
59350 </field>
59351 <field>
59352 <name>EPDIR</name>
59353 <description>Endpoint direction</description>
59354 <bitOffset>15</bitOffset>
59355 <bitWidth>1</bitWidth>
59356 </field>
59357 <field>
59358 <name>LSDEV</name>
59359 <description>Low-speed device</description>
59360 <bitOffset>17</bitOffset>
59361 <bitWidth>1</bitWidth>
59362 </field>
59363 <field>
59364 <name>EPTYP</name>
59365 <description>Endpoint type</description>
59366 <bitOffset>18</bitOffset>
59367 <bitWidth>2</bitWidth>
59368 </field>
59369 <field>
59370 <name>MC</name>
59371 <description>Multi Count (MC) / Error Count
59372 (EC)</description>
59373 <bitOffset>20</bitOffset>
59374 <bitWidth>2</bitWidth>
59375 </field>
59376 <field>
59377 <name>DAD</name>
59378 <description>Device address</description>
59379 <bitOffset>22</bitOffset>
59380 <bitWidth>7</bitWidth>
59381 </field>
59382 <field>
59383 <name>ODDFRM</name>
59384 <description>Odd frame</description>
59385 <bitOffset>29</bitOffset>
59386 <bitWidth>1</bitWidth>
59387 </field>
59388 <field>
59389 <name>CHDIS</name>
59390 <description>Channel disable</description>
59391 <bitOffset>30</bitOffset>
59392 <bitWidth>1</bitWidth>
59393 </field>
59394 <field>
59395 <name>CHENA</name>
59396 <description>Channel enable</description>
59397 <bitOffset>31</bitOffset>
59398 <bitWidth>1</bitWidth>
59399 </field>
59400 </fields>
59401 </register>
59402 <register>
59403 <name>OTG_HS_HCCHAR10</name>
59404 <displayName>OTG_HS_HCCHAR10</displayName>
59405 <description>OTG_HS host channel-10 characteristics
59406 register</description>
59407 <addressOffset>0x240</addressOffset>
59408 <size>32</size>
59409 <access>read-write</access>
59410 <resetValue>0x0</resetValue>
59411 <fields>
59412 <field>
59413 <name>MPSIZ</name>
59414 <description>Maximum packet size</description>
59415 <bitOffset>0</bitOffset>
59416 <bitWidth>11</bitWidth>
59417 </field>
59418 <field>
59419 <name>EPNUM</name>
59420 <description>Endpoint number</description>
59421 <bitOffset>11</bitOffset>
59422 <bitWidth>4</bitWidth>
59423 </field>
59424 <field>
59425 <name>EPDIR</name>
59426 <description>Endpoint direction</description>
59427 <bitOffset>15</bitOffset>
59428 <bitWidth>1</bitWidth>
59429 </field>
59430 <field>
59431 <name>LSDEV</name>
59432 <description>Low-speed device</description>
59433 <bitOffset>17</bitOffset>
59434 <bitWidth>1</bitWidth>
59435 </field>
59436 <field>
59437 <name>EPTYP</name>
59438 <description>Endpoint type</description>
59439 <bitOffset>18</bitOffset>
59440 <bitWidth>2</bitWidth>
59441 </field>
59442 <field>
59443 <name>MC</name>
59444 <description>Multi Count (MC) / Error Count
59445 (EC)</description>
59446 <bitOffset>20</bitOffset>
59447 <bitWidth>2</bitWidth>
59448 </field>
59449 <field>
59450 <name>DAD</name>
59451 <description>Device address</description>
59452 <bitOffset>22</bitOffset>
59453 <bitWidth>7</bitWidth>
59454 </field>
59455 <field>
59456 <name>ODDFRM</name>
59457 <description>Odd frame</description>
59458 <bitOffset>29</bitOffset>
59459 <bitWidth>1</bitWidth>
59460 </field>
59461 <field>
59462 <name>CHDIS</name>
59463 <description>Channel disable</description>
59464 <bitOffset>30</bitOffset>
59465 <bitWidth>1</bitWidth>
59466 </field>
59467 <field>
59468 <name>CHENA</name>
59469 <description>Channel enable</description>
59470 <bitOffset>31</bitOffset>
59471 <bitWidth>1</bitWidth>
59472 </field>
59473 </fields>
59474 </register>
59475 <register>
59476 <name>OTG_HS_HCCHAR11</name>
59477 <displayName>OTG_HS_HCCHAR11</displayName>
59478 <description>OTG_HS host channel-11 characteristics
59479 register</description>
59480 <addressOffset>0x260</addressOffset>
59481 <size>32</size>
59482 <access>read-write</access>
59483 <resetValue>0x0</resetValue>
59484 <fields>
59485 <field>
59486 <name>MPSIZ</name>
59487 <description>Maximum packet size</description>
59488 <bitOffset>0</bitOffset>
59489 <bitWidth>11</bitWidth>
59490 </field>
59491 <field>
59492 <name>EPNUM</name>
59493 <description>Endpoint number</description>
59494 <bitOffset>11</bitOffset>
59495 <bitWidth>4</bitWidth>
59496 </field>
59497 <field>
59498 <name>EPDIR</name>
59499 <description>Endpoint direction</description>
59500 <bitOffset>15</bitOffset>
59501 <bitWidth>1</bitWidth>
59502 </field>
59503 <field>
59504 <name>LSDEV</name>
59505 <description>Low-speed device</description>
59506 <bitOffset>17</bitOffset>
59507 <bitWidth>1</bitWidth>
59508 </field>
59509 <field>
59510 <name>EPTYP</name>
59511 <description>Endpoint type</description>
59512 <bitOffset>18</bitOffset>
59513 <bitWidth>2</bitWidth>
59514 </field>
59515 <field>
59516 <name>MC</name>
59517 <description>Multi Count (MC) / Error Count
59518 (EC)</description>
59519 <bitOffset>20</bitOffset>
59520 <bitWidth>2</bitWidth>
59521 </field>
59522 <field>
59523 <name>DAD</name>
59524 <description>Device address</description>
59525 <bitOffset>22</bitOffset>
59526 <bitWidth>7</bitWidth>
59527 </field>
59528 <field>
59529 <name>ODDFRM</name>
59530 <description>Odd frame</description>
59531 <bitOffset>29</bitOffset>
59532 <bitWidth>1</bitWidth>
59533 </field>
59534 <field>
59535 <name>CHDIS</name>
59536 <description>Channel disable</description>
59537 <bitOffset>30</bitOffset>
59538 <bitWidth>1</bitWidth>
59539 </field>
59540 <field>
59541 <name>CHENA</name>
59542 <description>Channel enable</description>
59543 <bitOffset>31</bitOffset>
59544 <bitWidth>1</bitWidth>
59545 </field>
59546 </fields>
59547 </register>
59548 <register>
59549 <name>OTG_HS_HCSPLT0</name>
59550 <displayName>OTG_HS_HCSPLT0</displayName>
59551 <description>OTG_HS host channel-0 split control
59552 register</description>
59553 <addressOffset>0x104</addressOffset>
59554 <size>32</size>
59555 <access>read-write</access>
59556 <resetValue>0x0</resetValue>
59557 <fields>
59558 <field>
59559 <name>PRTADDR</name>
59560 <description>Port address</description>
59561 <bitOffset>0</bitOffset>
59562 <bitWidth>7</bitWidth>
59563 </field>
59564 <field>
59565 <name>HUBADDR</name>
59566 <description>Hub address</description>
59567 <bitOffset>7</bitOffset>
59568 <bitWidth>7</bitWidth>
59569 </field>
59570 <field>
59571 <name>XACTPOS</name>
59572 <description>XACTPOS</description>
59573 <bitOffset>14</bitOffset>
59574 <bitWidth>2</bitWidth>
59575 </field>
59576 <field>
59577 <name>COMPLSPLT</name>
59578 <description>Do complete split</description>
59579 <bitOffset>16</bitOffset>
59580 <bitWidth>1</bitWidth>
59581 </field>
59582 <field>
59583 <name>SPLITEN</name>
59584 <description>Split enable</description>
59585 <bitOffset>31</bitOffset>
59586 <bitWidth>1</bitWidth>
59587 </field>
59588 </fields>
59589 </register>
59590 <register>
59591 <name>OTG_HS_HCSPLT1</name>
59592 <displayName>OTG_HS_HCSPLT1</displayName>
59593 <description>OTG_HS host channel-1 split control
59594 register</description>
59595 <addressOffset>0x124</addressOffset>
59596 <size>32</size>
59597 <access>read-write</access>
59598 <resetValue>0x0</resetValue>
59599 <fields>
59600 <field>
59601 <name>PRTADDR</name>
59602 <description>Port address</description>
59603 <bitOffset>0</bitOffset>
59604 <bitWidth>7</bitWidth>
59605 </field>
59606 <field>
59607 <name>HUBADDR</name>
59608 <description>Hub address</description>
59609 <bitOffset>7</bitOffset>
59610 <bitWidth>7</bitWidth>
59611 </field>
59612 <field>
59613 <name>XACTPOS</name>
59614 <description>XACTPOS</description>
59615 <bitOffset>14</bitOffset>
59616 <bitWidth>2</bitWidth>
59617 </field>
59618 <field>
59619 <name>COMPLSPLT</name>
59620 <description>Do complete split</description>
59621 <bitOffset>16</bitOffset>
59622 <bitWidth>1</bitWidth>
59623 </field>
59624 <field>
59625 <name>SPLITEN</name>
59626 <description>Split enable</description>
59627 <bitOffset>31</bitOffset>
59628 <bitWidth>1</bitWidth>
59629 </field>
59630 </fields>
59631 </register>
59632 <register>
59633 <name>OTG_HS_HCSPLT2</name>
59634 <displayName>OTG_HS_HCSPLT2</displayName>
59635 <description>OTG_HS host channel-2 split control
59636 register</description>
59637 <addressOffset>0x144</addressOffset>
59638 <size>32</size>
59639 <access>read-write</access>
59640 <resetValue>0x0</resetValue>
59641 <fields>
59642 <field>
59643 <name>PRTADDR</name>
59644 <description>Port address</description>
59645 <bitOffset>0</bitOffset>
59646 <bitWidth>7</bitWidth>
59647 </field>
59648 <field>
59649 <name>HUBADDR</name>
59650 <description>Hub address</description>
59651 <bitOffset>7</bitOffset>
59652 <bitWidth>7</bitWidth>
59653 </field>
59654 <field>
59655 <name>XACTPOS</name>
59656 <description>XACTPOS</description>
59657 <bitOffset>14</bitOffset>
59658 <bitWidth>2</bitWidth>
59659 </field>
59660 <field>
59661 <name>COMPLSPLT</name>
59662 <description>Do complete split</description>
59663 <bitOffset>16</bitOffset>
59664 <bitWidth>1</bitWidth>
59665 </field>
59666 <field>
59667 <name>SPLITEN</name>
59668 <description>Split enable</description>
59669 <bitOffset>31</bitOffset>
59670 <bitWidth>1</bitWidth>
59671 </field>
59672 </fields>
59673 </register>
59674 <register>
59675 <name>OTG_HS_HCSPLT3</name>
59676 <displayName>OTG_HS_HCSPLT3</displayName>
59677 <description>OTG_HS host channel-3 split control
59678 register</description>
59679 <addressOffset>0x164</addressOffset>
59680 <size>32</size>
59681 <access>read-write</access>
59682 <resetValue>0x0</resetValue>
59683 <fields>
59684 <field>
59685 <name>PRTADDR</name>
59686 <description>Port address</description>
59687 <bitOffset>0</bitOffset>
59688 <bitWidth>7</bitWidth>
59689 </field>
59690 <field>
59691 <name>HUBADDR</name>
59692 <description>Hub address</description>
59693 <bitOffset>7</bitOffset>
59694 <bitWidth>7</bitWidth>
59695 </field>
59696 <field>
59697 <name>XACTPOS</name>
59698 <description>XACTPOS</description>
59699 <bitOffset>14</bitOffset>
59700 <bitWidth>2</bitWidth>
59701 </field>
59702 <field>
59703 <name>COMPLSPLT</name>
59704 <description>Do complete split</description>
59705 <bitOffset>16</bitOffset>
59706 <bitWidth>1</bitWidth>
59707 </field>
59708 <field>
59709 <name>SPLITEN</name>
59710 <description>Split enable</description>
59711 <bitOffset>31</bitOffset>
59712 <bitWidth>1</bitWidth>
59713 </field>
59714 </fields>
59715 </register>
59716 <register>
59717 <name>OTG_HS_HCSPLT4</name>
59718 <displayName>OTG_HS_HCSPLT4</displayName>
59719 <description>OTG_HS host channel-4 split control
59720 register</description>
59721 <addressOffset>0x184</addressOffset>
59722 <size>32</size>
59723 <access>read-write</access>
59724 <resetValue>0x0</resetValue>
59725 <fields>
59726 <field>
59727 <name>PRTADDR</name>
59728 <description>Port address</description>
59729 <bitOffset>0</bitOffset>
59730 <bitWidth>7</bitWidth>
59731 </field>
59732 <field>
59733 <name>HUBADDR</name>
59734 <description>Hub address</description>
59735 <bitOffset>7</bitOffset>
59736 <bitWidth>7</bitWidth>
59737 </field>
59738 <field>
59739 <name>XACTPOS</name>
59740 <description>XACTPOS</description>
59741 <bitOffset>14</bitOffset>
59742 <bitWidth>2</bitWidth>
59743 </field>
59744 <field>
59745 <name>COMPLSPLT</name>
59746 <description>Do complete split</description>
59747 <bitOffset>16</bitOffset>
59748 <bitWidth>1</bitWidth>
59749 </field>
59750 <field>
59751 <name>SPLITEN</name>
59752 <description>Split enable</description>
59753 <bitOffset>31</bitOffset>
59754 <bitWidth>1</bitWidth>
59755 </field>
59756 </fields>
59757 </register>
59758 <register>
59759 <name>OTG_HS_HCSPLT5</name>
59760 <displayName>OTG_HS_HCSPLT5</displayName>
59761 <description>OTG_HS host channel-5 split control
59762 register</description>
59763 <addressOffset>0x1A4</addressOffset>
59764 <size>32</size>
59765 <access>read-write</access>
59766 <resetValue>0x0</resetValue>
59767 <fields>
59768 <field>
59769 <name>PRTADDR</name>
59770 <description>Port address</description>
59771 <bitOffset>0</bitOffset>
59772 <bitWidth>7</bitWidth>
59773 </field>
59774 <field>
59775 <name>HUBADDR</name>
59776 <description>Hub address</description>
59777 <bitOffset>7</bitOffset>
59778 <bitWidth>7</bitWidth>
59779 </field>
59780 <field>
59781 <name>XACTPOS</name>
59782 <description>XACTPOS</description>
59783 <bitOffset>14</bitOffset>
59784 <bitWidth>2</bitWidth>
59785 </field>
59786 <field>
59787 <name>COMPLSPLT</name>
59788 <description>Do complete split</description>
59789 <bitOffset>16</bitOffset>
59790 <bitWidth>1</bitWidth>
59791 </field>
59792 <field>
59793 <name>SPLITEN</name>
59794 <description>Split enable</description>
59795 <bitOffset>31</bitOffset>
59796 <bitWidth>1</bitWidth>
59797 </field>
59798 </fields>
59799 </register>
59800 <register>
59801 <name>OTG_HS_HCSPLT6</name>
59802 <displayName>OTG_HS_HCSPLT6</displayName>
59803 <description>OTG_HS host channel-6 split control
59804 register</description>
59805 <addressOffset>0x1C4</addressOffset>
59806 <size>32</size>
59807 <access>read-write</access>
59808 <resetValue>0x0</resetValue>
59809 <fields>
59810 <field>
59811 <name>PRTADDR</name>
59812 <description>Port address</description>
59813 <bitOffset>0</bitOffset>
59814 <bitWidth>7</bitWidth>
59815 </field>
59816 <field>
59817 <name>HUBADDR</name>
59818 <description>Hub address</description>
59819 <bitOffset>7</bitOffset>
59820 <bitWidth>7</bitWidth>
59821 </field>
59822 <field>
59823 <name>XACTPOS</name>
59824 <description>XACTPOS</description>
59825 <bitOffset>14</bitOffset>
59826 <bitWidth>2</bitWidth>
59827 </field>
59828 <field>
59829 <name>COMPLSPLT</name>
59830 <description>Do complete split</description>
59831 <bitOffset>16</bitOffset>
59832 <bitWidth>1</bitWidth>
59833 </field>
59834 <field>
59835 <name>SPLITEN</name>
59836 <description>Split enable</description>
59837 <bitOffset>31</bitOffset>
59838 <bitWidth>1</bitWidth>
59839 </field>
59840 </fields>
59841 </register>
59842 <register>
59843 <name>OTG_HS_HCSPLT7</name>
59844 <displayName>OTG_HS_HCSPLT7</displayName>
59845 <description>OTG_HS host channel-7 split control
59846 register</description>
59847 <addressOffset>0x1E4</addressOffset>
59848 <size>32</size>
59849 <access>read-write</access>
59850 <resetValue>0x0</resetValue>
59851 <fields>
59852 <field>
59853 <name>PRTADDR</name>
59854 <description>Port address</description>
59855 <bitOffset>0</bitOffset>
59856 <bitWidth>7</bitWidth>
59857 </field>
59858 <field>
59859 <name>HUBADDR</name>
59860 <description>Hub address</description>
59861 <bitOffset>7</bitOffset>
59862 <bitWidth>7</bitWidth>
59863 </field>
59864 <field>
59865 <name>XACTPOS</name>
59866 <description>XACTPOS</description>
59867 <bitOffset>14</bitOffset>
59868 <bitWidth>2</bitWidth>
59869 </field>
59870 <field>
59871 <name>COMPLSPLT</name>
59872 <description>Do complete split</description>
59873 <bitOffset>16</bitOffset>
59874 <bitWidth>1</bitWidth>
59875 </field>
59876 <field>
59877 <name>SPLITEN</name>
59878 <description>Split enable</description>
59879 <bitOffset>31</bitOffset>
59880 <bitWidth>1</bitWidth>
59881 </field>
59882 </fields>
59883 </register>
59884 <register>
59885 <name>OTG_HS_HCSPLT8</name>
59886 <displayName>OTG_HS_HCSPLT8</displayName>
59887 <description>OTG_HS host channel-8 split control
59888 register</description>
59889 <addressOffset>0x204</addressOffset>
59890 <size>32</size>
59891 <access>read-write</access>
59892 <resetValue>0x0</resetValue>
59893 <fields>
59894 <field>
59895 <name>PRTADDR</name>
59896 <description>Port address</description>
59897 <bitOffset>0</bitOffset>
59898 <bitWidth>7</bitWidth>
59899 </field>
59900 <field>
59901 <name>HUBADDR</name>
59902 <description>Hub address</description>
59903 <bitOffset>7</bitOffset>
59904 <bitWidth>7</bitWidth>
59905 </field>
59906 <field>
59907 <name>XACTPOS</name>
59908 <description>XACTPOS</description>
59909 <bitOffset>14</bitOffset>
59910 <bitWidth>2</bitWidth>
59911 </field>
59912 <field>
59913 <name>COMPLSPLT</name>
59914 <description>Do complete split</description>
59915 <bitOffset>16</bitOffset>
59916 <bitWidth>1</bitWidth>
59917 </field>
59918 <field>
59919 <name>SPLITEN</name>
59920 <description>Split enable</description>
59921 <bitOffset>31</bitOffset>
59922 <bitWidth>1</bitWidth>
59923 </field>
59924 </fields>
59925 </register>
59926 <register>
59927 <name>OTG_HS_HCSPLT9</name>
59928 <displayName>OTG_HS_HCSPLT9</displayName>
59929 <description>OTG_HS host channel-9 split control
59930 register</description>
59931 <addressOffset>0x224</addressOffset>
59932 <size>32</size>
59933 <access>read-write</access>
59934 <resetValue>0x0</resetValue>
59935 <fields>
59936 <field>
59937 <name>PRTADDR</name>
59938 <description>Port address</description>
59939 <bitOffset>0</bitOffset>
59940 <bitWidth>7</bitWidth>
59941 </field>
59942 <field>
59943 <name>HUBADDR</name>
59944 <description>Hub address</description>
59945 <bitOffset>7</bitOffset>
59946 <bitWidth>7</bitWidth>
59947 </field>
59948 <field>
59949 <name>XACTPOS</name>
59950 <description>XACTPOS</description>
59951 <bitOffset>14</bitOffset>
59952 <bitWidth>2</bitWidth>
59953 </field>
59954 <field>
59955 <name>COMPLSPLT</name>
59956 <description>Do complete split</description>
59957 <bitOffset>16</bitOffset>
59958 <bitWidth>1</bitWidth>
59959 </field>
59960 <field>
59961 <name>SPLITEN</name>
59962 <description>Split enable</description>
59963 <bitOffset>31</bitOffset>
59964 <bitWidth>1</bitWidth>
59965 </field>
59966 </fields>
59967 </register>
59968 <register>
59969 <name>OTG_HS_HCSPLT10</name>
59970 <displayName>OTG_HS_HCSPLT10</displayName>
59971 <description>OTG_HS host channel-10 split control
59972 register</description>
59973 <addressOffset>0x244</addressOffset>
59974 <size>32</size>
59975 <access>read-write</access>
59976 <resetValue>0x0</resetValue>
59977 <fields>
59978 <field>
59979 <name>PRTADDR</name>
59980 <description>Port address</description>
59981 <bitOffset>0</bitOffset>
59982 <bitWidth>7</bitWidth>
59983 </field>
59984 <field>
59985 <name>HUBADDR</name>
59986 <description>Hub address</description>
59987 <bitOffset>7</bitOffset>
59988 <bitWidth>7</bitWidth>
59989 </field>
59990 <field>
59991 <name>XACTPOS</name>
59992 <description>XACTPOS</description>
59993 <bitOffset>14</bitOffset>
59994 <bitWidth>2</bitWidth>
59995 </field>
59996 <field>
59997 <name>COMPLSPLT</name>
59998 <description>Do complete split</description>
59999 <bitOffset>16</bitOffset>
60000 <bitWidth>1</bitWidth>
60001 </field>
60002 <field>
60003 <name>SPLITEN</name>
60004 <description>Split enable</description>
60005 <bitOffset>31</bitOffset>
60006 <bitWidth>1</bitWidth>
60007 </field>
60008 </fields>
60009 </register>
60010 <register>
60011 <name>OTG_HS_HCSPLT11</name>
60012 <displayName>OTG_HS_HCSPLT11</displayName>
60013 <description>OTG_HS host channel-11 split control
60014 register</description>
60015 <addressOffset>0x264</addressOffset>
60016 <size>32</size>
60017 <access>read-write</access>
60018 <resetValue>0x0</resetValue>
60019 <fields>
60020 <field>
60021 <name>PRTADDR</name>
60022 <description>Port address</description>
60023 <bitOffset>0</bitOffset>
60024 <bitWidth>7</bitWidth>
60025 </field>
60026 <field>
60027 <name>HUBADDR</name>
60028 <description>Hub address</description>
60029 <bitOffset>7</bitOffset>
60030 <bitWidth>7</bitWidth>
60031 </field>
60032 <field>
60033 <name>XACTPOS</name>
60034 <description>XACTPOS</description>
60035 <bitOffset>14</bitOffset>
60036 <bitWidth>2</bitWidth>
60037 </field>
60038 <field>
60039 <name>COMPLSPLT</name>
60040 <description>Do complete split</description>
60041 <bitOffset>16</bitOffset>
60042 <bitWidth>1</bitWidth>
60043 </field>
60044 <field>
60045 <name>SPLITEN</name>
60046 <description>Split enable</description>
60047 <bitOffset>31</bitOffset>
60048 <bitWidth>1</bitWidth>
60049 </field>
60050 </fields>
60051 </register>
60052 <register>
60053 <name>OTG_HS_HCINT0</name>
60054 <displayName>OTG_HS_HCINT0</displayName>
60055 <description>OTG_HS host channel-11 interrupt
60056 register</description>
60057 <addressOffset>0x108</addressOffset>
60058 <size>32</size>
60059 <access>read-write</access>
60060 <resetValue>0x0</resetValue>
60061 <fields>
60062 <field>
60063 <name>XFRC</name>
60064 <description>Transfer completed</description>
60065 <bitOffset>0</bitOffset>
60066 <bitWidth>1</bitWidth>
60067 </field>
60068 <field>
60069 <name>CHH</name>
60070 <description>Channel halted</description>
60071 <bitOffset>1</bitOffset>
60072 <bitWidth>1</bitWidth>
60073 </field>
60074 <field>
60075 <name>AHBERR</name>
60076 <description>AHB error</description>
60077 <bitOffset>2</bitOffset>
60078 <bitWidth>1</bitWidth>
60079 </field>
60080 <field>
60081 <name>STALL</name>
60082 <description>STALL response received
60083 interrupt</description>
60084 <bitOffset>3</bitOffset>
60085 <bitWidth>1</bitWidth>
60086 </field>
60087 <field>
60088 <name>NAK</name>
60089 <description>NAK response received
60090 interrupt</description>
60091 <bitOffset>4</bitOffset>
60092 <bitWidth>1</bitWidth>
60093 </field>
60094 <field>
60095 <name>ACK</name>
60096 <description>ACK response received/transmitted
60097 interrupt</description>
60098 <bitOffset>5</bitOffset>
60099 <bitWidth>1</bitWidth>
60100 </field>
60101 <field>
60102 <name>NYET</name>
60103 <description>Response received
60104 interrupt</description>
60105 <bitOffset>6</bitOffset>
60106 <bitWidth>1</bitWidth>
60107 </field>
60108 <field>
60109 <name>TXERR</name>
60110 <description>Transaction error</description>
60111 <bitOffset>7</bitOffset>
60112 <bitWidth>1</bitWidth>
60113 </field>
60114 <field>
60115 <name>BBERR</name>
60116 <description>Babble error</description>
60117 <bitOffset>8</bitOffset>
60118 <bitWidth>1</bitWidth>
60119 </field>
60120 <field>
60121 <name>FRMOR</name>
60122 <description>Frame overrun</description>
60123 <bitOffset>9</bitOffset>
60124 <bitWidth>1</bitWidth>
60125 </field>
60126 <field>
60127 <name>DTERR</name>
60128 <description>Data toggle error</description>
60129 <bitOffset>10</bitOffset>
60130 <bitWidth>1</bitWidth>
60131 </field>
60132 </fields>
60133 </register>
60134 <register>
60135 <name>OTG_HS_HCINT1</name>
60136 <displayName>OTG_HS_HCINT1</displayName>
60137 <description>OTG_HS host channel-1 interrupt
60138 register</description>
60139 <addressOffset>0x128</addressOffset>
60140 <size>32</size>
60141 <access>read-write</access>
60142 <resetValue>0x0</resetValue>
60143 <fields>
60144 <field>
60145 <name>XFRC</name>
60146 <description>Transfer completed</description>
60147 <bitOffset>0</bitOffset>
60148 <bitWidth>1</bitWidth>
60149 </field>
60150 <field>
60151 <name>CHH</name>
60152 <description>Channel halted</description>
60153 <bitOffset>1</bitOffset>
60154 <bitWidth>1</bitWidth>
60155 </field>
60156 <field>
60157 <name>AHBERR</name>
60158 <description>AHB error</description>
60159 <bitOffset>2</bitOffset>
60160 <bitWidth>1</bitWidth>
60161 </field>
60162 <field>
60163 <name>STALL</name>
60164 <description>STALL response received
60165 interrupt</description>
60166 <bitOffset>3</bitOffset>
60167 <bitWidth>1</bitWidth>
60168 </field>
60169 <field>
60170 <name>NAK</name>
60171 <description>NAK response received
60172 interrupt</description>
60173 <bitOffset>4</bitOffset>
60174 <bitWidth>1</bitWidth>
60175 </field>
60176 <field>
60177 <name>ACK</name>
60178 <description>ACK response received/transmitted
60179 interrupt</description>
60180 <bitOffset>5</bitOffset>
60181 <bitWidth>1</bitWidth>
60182 </field>
60183 <field>
60184 <name>NYET</name>
60185 <description>Response received
60186 interrupt</description>
60187 <bitOffset>6</bitOffset>
60188 <bitWidth>1</bitWidth>
60189 </field>
60190 <field>
60191 <name>TXERR</name>
60192 <description>Transaction error</description>
60193 <bitOffset>7</bitOffset>
60194 <bitWidth>1</bitWidth>
60195 </field>
60196 <field>
60197 <name>BBERR</name>
60198 <description>Babble error</description>
60199 <bitOffset>8</bitOffset>
60200 <bitWidth>1</bitWidth>
60201 </field>
60202 <field>
60203 <name>FRMOR</name>
60204 <description>Frame overrun</description>
60205 <bitOffset>9</bitOffset>
60206 <bitWidth>1</bitWidth>
60207 </field>
60208 <field>
60209 <name>DTERR</name>
60210 <description>Data toggle error</description>
60211 <bitOffset>10</bitOffset>
60212 <bitWidth>1</bitWidth>
60213 </field>
60214 </fields>
60215 </register>
60216 <register>
60217 <name>OTG_HS_HCINT2</name>
60218 <displayName>OTG_HS_HCINT2</displayName>
60219 <description>OTG_HS host channel-2 interrupt
60220 register</description>
60221 <addressOffset>0x148</addressOffset>
60222 <size>32</size>
60223 <access>read-write</access>
60224 <resetValue>0x0</resetValue>
60225 <fields>
60226 <field>
60227 <name>XFRC</name>
60228 <description>Transfer completed</description>
60229 <bitOffset>0</bitOffset>
60230 <bitWidth>1</bitWidth>
60231 </field>
60232 <field>
60233 <name>CHH</name>
60234 <description>Channel halted</description>
60235 <bitOffset>1</bitOffset>
60236 <bitWidth>1</bitWidth>
60237 </field>
60238 <field>
60239 <name>AHBERR</name>
60240 <description>AHB error</description>
60241 <bitOffset>2</bitOffset>
60242 <bitWidth>1</bitWidth>
60243 </field>
60244 <field>
60245 <name>STALL</name>
60246 <description>STALL response received
60247 interrupt</description>
60248 <bitOffset>3</bitOffset>
60249 <bitWidth>1</bitWidth>
60250 </field>
60251 <field>
60252 <name>NAK</name>
60253 <description>NAK response received
60254 interrupt</description>
60255 <bitOffset>4</bitOffset>
60256 <bitWidth>1</bitWidth>
60257 </field>
60258 <field>
60259 <name>ACK</name>
60260 <description>ACK response received/transmitted
60261 interrupt</description>
60262 <bitOffset>5</bitOffset>
60263 <bitWidth>1</bitWidth>
60264 </field>
60265 <field>
60266 <name>NYET</name>
60267 <description>Response received
60268 interrupt</description>
60269 <bitOffset>6</bitOffset>
60270 <bitWidth>1</bitWidth>
60271 </field>
60272 <field>
60273 <name>TXERR</name>
60274 <description>Transaction error</description>
60275 <bitOffset>7</bitOffset>
60276 <bitWidth>1</bitWidth>
60277 </field>
60278 <field>
60279 <name>BBERR</name>
60280 <description>Babble error</description>
60281 <bitOffset>8</bitOffset>
60282 <bitWidth>1</bitWidth>
60283 </field>
60284 <field>
60285 <name>FRMOR</name>
60286 <description>Frame overrun</description>
60287 <bitOffset>9</bitOffset>
60288 <bitWidth>1</bitWidth>
60289 </field>
60290 <field>
60291 <name>DTERR</name>
60292 <description>Data toggle error</description>
60293 <bitOffset>10</bitOffset>
60294 <bitWidth>1</bitWidth>
60295 </field>
60296 </fields>
60297 </register>
60298 <register>
60299 <name>OTG_HS_HCINT3</name>
60300 <displayName>OTG_HS_HCINT3</displayName>
60301 <description>OTG_HS host channel-3 interrupt
60302 register</description>
60303 <addressOffset>0x168</addressOffset>
60304 <size>32</size>
60305 <access>read-write</access>
60306 <resetValue>0x0</resetValue>
60307 <fields>
60308 <field>
60309 <name>XFRC</name>
60310 <description>Transfer completed</description>
60311 <bitOffset>0</bitOffset>
60312 <bitWidth>1</bitWidth>
60313 </field>
60314 <field>
60315 <name>CHH</name>
60316 <description>Channel halted</description>
60317 <bitOffset>1</bitOffset>
60318 <bitWidth>1</bitWidth>
60319 </field>
60320 <field>
60321 <name>AHBERR</name>
60322 <description>AHB error</description>
60323 <bitOffset>2</bitOffset>
60324 <bitWidth>1</bitWidth>
60325 </field>
60326 <field>
60327 <name>STALL</name>
60328 <description>STALL response received
60329 interrupt</description>
60330 <bitOffset>3</bitOffset>
60331 <bitWidth>1</bitWidth>
60332 </field>
60333 <field>
60334 <name>NAK</name>
60335 <description>NAK response received
60336 interrupt</description>
60337 <bitOffset>4</bitOffset>
60338 <bitWidth>1</bitWidth>
60339 </field>
60340 <field>
60341 <name>ACK</name>
60342 <description>ACK response received/transmitted
60343 interrupt</description>
60344 <bitOffset>5</bitOffset>
60345 <bitWidth>1</bitWidth>
60346 </field>
60347 <field>
60348 <name>NYET</name>
60349 <description>Response received
60350 interrupt</description>
60351 <bitOffset>6</bitOffset>
60352 <bitWidth>1</bitWidth>
60353 </field>
60354 <field>
60355 <name>TXERR</name>
60356 <description>Transaction error</description>
60357 <bitOffset>7</bitOffset>
60358 <bitWidth>1</bitWidth>
60359 </field>
60360 <field>
60361 <name>BBERR</name>
60362 <description>Babble error</description>
60363 <bitOffset>8</bitOffset>
60364 <bitWidth>1</bitWidth>
60365 </field>
60366 <field>
60367 <name>FRMOR</name>
60368 <description>Frame overrun</description>
60369 <bitOffset>9</bitOffset>
60370 <bitWidth>1</bitWidth>
60371 </field>
60372 <field>
60373 <name>DTERR</name>
60374 <description>Data toggle error</description>
60375 <bitOffset>10</bitOffset>
60376 <bitWidth>1</bitWidth>
60377 </field>
60378 </fields>
60379 </register>
60380 <register>
60381 <name>OTG_HS_HCINT4</name>
60382 <displayName>OTG_HS_HCINT4</displayName>
60383 <description>OTG_HS host channel-4 interrupt
60384 register</description>
60385 <addressOffset>0x188</addressOffset>
60386 <size>32</size>
60387 <access>read-write</access>
60388 <resetValue>0x0</resetValue>
60389 <fields>
60390 <field>
60391 <name>XFRC</name>
60392 <description>Transfer completed</description>
60393 <bitOffset>0</bitOffset>
60394 <bitWidth>1</bitWidth>
60395 </field>
60396 <field>
60397 <name>CHH</name>
60398 <description>Channel halted</description>
60399 <bitOffset>1</bitOffset>
60400 <bitWidth>1</bitWidth>
60401 </field>
60402 <field>
60403 <name>AHBERR</name>
60404 <description>AHB error</description>
60405 <bitOffset>2</bitOffset>
60406 <bitWidth>1</bitWidth>
60407 </field>
60408 <field>
60409 <name>STALL</name>
60410 <description>STALL response received
60411 interrupt</description>
60412 <bitOffset>3</bitOffset>
60413 <bitWidth>1</bitWidth>
60414 </field>
60415 <field>
60416 <name>NAK</name>
60417 <description>NAK response received
60418 interrupt</description>
60419 <bitOffset>4</bitOffset>
60420 <bitWidth>1</bitWidth>
60421 </field>
60422 <field>
60423 <name>ACK</name>
60424 <description>ACK response received/transmitted
60425 interrupt</description>
60426 <bitOffset>5</bitOffset>
60427 <bitWidth>1</bitWidth>
60428 </field>
60429 <field>
60430 <name>NYET</name>
60431 <description>Response received
60432 interrupt</description>
60433 <bitOffset>6</bitOffset>
60434 <bitWidth>1</bitWidth>
60435 </field>
60436 <field>
60437 <name>TXERR</name>
60438 <description>Transaction error</description>
60439 <bitOffset>7</bitOffset>
60440 <bitWidth>1</bitWidth>
60441 </field>
60442 <field>
60443 <name>BBERR</name>
60444 <description>Babble error</description>
60445 <bitOffset>8</bitOffset>
60446 <bitWidth>1</bitWidth>
60447 </field>
60448 <field>
60449 <name>FRMOR</name>
60450 <description>Frame overrun</description>
60451 <bitOffset>9</bitOffset>
60452 <bitWidth>1</bitWidth>
60453 </field>
60454 <field>
60455 <name>DTERR</name>
60456 <description>Data toggle error</description>
60457 <bitOffset>10</bitOffset>
60458 <bitWidth>1</bitWidth>
60459 </field>
60460 </fields>
60461 </register>
60462 <register>
60463 <name>OTG_HS_HCINT5</name>
60464 <displayName>OTG_HS_HCINT5</displayName>
60465 <description>OTG_HS host channel-5 interrupt
60466 register</description>
60467 <addressOffset>0x1A8</addressOffset>
60468 <size>32</size>
60469 <access>read-write</access>
60470 <resetValue>0x0</resetValue>
60471 <fields>
60472 <field>
60473 <name>XFRC</name>
60474 <description>Transfer completed</description>
60475 <bitOffset>0</bitOffset>
60476 <bitWidth>1</bitWidth>
60477 </field>
60478 <field>
60479 <name>CHH</name>
60480 <description>Channel halted</description>
60481 <bitOffset>1</bitOffset>
60482 <bitWidth>1</bitWidth>
60483 </field>
60484 <field>
60485 <name>AHBERR</name>
60486 <description>AHB error</description>
60487 <bitOffset>2</bitOffset>
60488 <bitWidth>1</bitWidth>
60489 </field>
60490 <field>
60491 <name>STALL</name>
60492 <description>STALL response received
60493 interrupt</description>
60494 <bitOffset>3</bitOffset>
60495 <bitWidth>1</bitWidth>
60496 </field>
60497 <field>
60498 <name>NAK</name>
60499 <description>NAK response received
60500 interrupt</description>
60501 <bitOffset>4</bitOffset>
60502 <bitWidth>1</bitWidth>
60503 </field>
60504 <field>
60505 <name>ACK</name>
60506 <description>ACK response received/transmitted
60507 interrupt</description>
60508 <bitOffset>5</bitOffset>
60509 <bitWidth>1</bitWidth>
60510 </field>
60511 <field>
60512 <name>NYET</name>
60513 <description>Response received
60514 interrupt</description>
60515 <bitOffset>6</bitOffset>
60516 <bitWidth>1</bitWidth>
60517 </field>
60518 <field>
60519 <name>TXERR</name>
60520 <description>Transaction error</description>
60521 <bitOffset>7</bitOffset>
60522 <bitWidth>1</bitWidth>
60523 </field>
60524 <field>
60525 <name>BBERR</name>
60526 <description>Babble error</description>
60527 <bitOffset>8</bitOffset>
60528 <bitWidth>1</bitWidth>
60529 </field>
60530 <field>
60531 <name>FRMOR</name>
60532 <description>Frame overrun</description>
60533 <bitOffset>9</bitOffset>
60534 <bitWidth>1</bitWidth>
60535 </field>
60536 <field>
60537 <name>DTERR</name>
60538 <description>Data toggle error</description>
60539 <bitOffset>10</bitOffset>
60540 <bitWidth>1</bitWidth>
60541 </field>
60542 </fields>
60543 </register>
60544 <register>
60545 <name>OTG_HS_HCINT6</name>
60546 <displayName>OTG_HS_HCINT6</displayName>
60547 <description>OTG_HS host channel-6 interrupt
60548 register</description>
60549 <addressOffset>0x1C8</addressOffset>
60550 <size>32</size>
60551 <access>read-write</access>
60552 <resetValue>0x0</resetValue>
60553 <fields>
60554 <field>
60555 <name>XFRC</name>
60556 <description>Transfer completed</description>
60557 <bitOffset>0</bitOffset>
60558 <bitWidth>1</bitWidth>
60559 </field>
60560 <field>
60561 <name>CHH</name>
60562 <description>Channel halted</description>
60563 <bitOffset>1</bitOffset>
60564 <bitWidth>1</bitWidth>
60565 </field>
60566 <field>
60567 <name>AHBERR</name>
60568 <description>AHB error</description>
60569 <bitOffset>2</bitOffset>
60570 <bitWidth>1</bitWidth>
60571 </field>
60572 <field>
60573 <name>STALL</name>
60574 <description>STALL response received
60575 interrupt</description>
60576 <bitOffset>3</bitOffset>
60577 <bitWidth>1</bitWidth>
60578 </field>
60579 <field>
60580 <name>NAK</name>
60581 <description>NAK response received
60582 interrupt</description>
60583 <bitOffset>4</bitOffset>
60584 <bitWidth>1</bitWidth>
60585 </field>
60586 <field>
60587 <name>ACK</name>
60588 <description>ACK response received/transmitted
60589 interrupt</description>
60590 <bitOffset>5</bitOffset>
60591 <bitWidth>1</bitWidth>
60592 </field>
60593 <field>
60594 <name>NYET</name>
60595 <description>Response received
60596 interrupt</description>
60597 <bitOffset>6</bitOffset>
60598 <bitWidth>1</bitWidth>
60599 </field>
60600 <field>
60601 <name>TXERR</name>
60602 <description>Transaction error</description>
60603 <bitOffset>7</bitOffset>
60604 <bitWidth>1</bitWidth>
60605 </field>
60606 <field>
60607 <name>BBERR</name>
60608 <description>Babble error</description>
60609 <bitOffset>8</bitOffset>
60610 <bitWidth>1</bitWidth>
60611 </field>
60612 <field>
60613 <name>FRMOR</name>
60614 <description>Frame overrun</description>
60615 <bitOffset>9</bitOffset>
60616 <bitWidth>1</bitWidth>
60617 </field>
60618 <field>
60619 <name>DTERR</name>
60620 <description>Data toggle error</description>
60621 <bitOffset>10</bitOffset>
60622 <bitWidth>1</bitWidth>
60623 </field>
60624 </fields>
60625 </register>
60626 <register>
60627 <name>OTG_HS_HCINT7</name>
60628 <displayName>OTG_HS_HCINT7</displayName>
60629 <description>OTG_HS host channel-7 interrupt
60630 register</description>
60631 <addressOffset>0x1E8</addressOffset>
60632 <size>32</size>
60633 <access>read-write</access>
60634 <resetValue>0x0</resetValue>
60635 <fields>
60636 <field>
60637 <name>XFRC</name>
60638 <description>Transfer completed</description>
60639 <bitOffset>0</bitOffset>
60640 <bitWidth>1</bitWidth>
60641 </field>
60642 <field>
60643 <name>CHH</name>
60644 <description>Channel halted</description>
60645 <bitOffset>1</bitOffset>
60646 <bitWidth>1</bitWidth>
60647 </field>
60648 <field>
60649 <name>AHBERR</name>
60650 <description>AHB error</description>
60651 <bitOffset>2</bitOffset>
60652 <bitWidth>1</bitWidth>
60653 </field>
60654 <field>
60655 <name>STALL</name>
60656 <description>STALL response received
60657 interrupt</description>
60658 <bitOffset>3</bitOffset>
60659 <bitWidth>1</bitWidth>
60660 </field>
60661 <field>
60662 <name>NAK</name>
60663 <description>NAK response received
60664 interrupt</description>
60665 <bitOffset>4</bitOffset>
60666 <bitWidth>1</bitWidth>
60667 </field>
60668 <field>
60669 <name>ACK</name>
60670 <description>ACK response received/transmitted
60671 interrupt</description>
60672 <bitOffset>5</bitOffset>
60673 <bitWidth>1</bitWidth>
60674 </field>
60675 <field>
60676 <name>NYET</name>
60677 <description>Response received
60678 interrupt</description>
60679 <bitOffset>6</bitOffset>
60680 <bitWidth>1</bitWidth>
60681 </field>
60682 <field>
60683 <name>TXERR</name>
60684 <description>Transaction error</description>
60685 <bitOffset>7</bitOffset>
60686 <bitWidth>1</bitWidth>
60687 </field>
60688 <field>
60689 <name>BBERR</name>
60690 <description>Babble error</description>
60691 <bitOffset>8</bitOffset>
60692 <bitWidth>1</bitWidth>
60693 </field>
60694 <field>
60695 <name>FRMOR</name>
60696 <description>Frame overrun</description>
60697 <bitOffset>9</bitOffset>
60698 <bitWidth>1</bitWidth>
60699 </field>
60700 <field>
60701 <name>DTERR</name>
60702 <description>Data toggle error</description>
60703 <bitOffset>10</bitOffset>
60704 <bitWidth>1</bitWidth>
60705 </field>
60706 </fields>
60707 </register>
60708 <register>
60709 <name>OTG_HS_HCINT8</name>
60710 <displayName>OTG_HS_HCINT8</displayName>
60711 <description>OTG_HS host channel-8 interrupt
60712 register</description>
60713 <addressOffset>0x208</addressOffset>
60714 <size>32</size>
60715 <access>read-write</access>
60716 <resetValue>0x0</resetValue>
60717 <fields>
60718 <field>
60719 <name>XFRC</name>
60720 <description>Transfer completed</description>
60721 <bitOffset>0</bitOffset>
60722 <bitWidth>1</bitWidth>
60723 </field>
60724 <field>
60725 <name>CHH</name>
60726 <description>Channel halted</description>
60727 <bitOffset>1</bitOffset>
60728 <bitWidth>1</bitWidth>
60729 </field>
60730 <field>
60731 <name>AHBERR</name>
60732 <description>AHB error</description>
60733 <bitOffset>2</bitOffset>
60734 <bitWidth>1</bitWidth>
60735 </field>
60736 <field>
60737 <name>STALL</name>
60738 <description>STALL response received
60739 interrupt</description>
60740 <bitOffset>3</bitOffset>
60741 <bitWidth>1</bitWidth>
60742 </field>
60743 <field>
60744 <name>NAK</name>
60745 <description>NAK response received
60746 interrupt</description>
60747 <bitOffset>4</bitOffset>
60748 <bitWidth>1</bitWidth>
60749 </field>
60750 <field>
60751 <name>ACK</name>
60752 <description>ACK response received/transmitted
60753 interrupt</description>
60754 <bitOffset>5</bitOffset>
60755 <bitWidth>1</bitWidth>
60756 </field>
60757 <field>
60758 <name>NYET</name>
60759 <description>Response received
60760 interrupt</description>
60761 <bitOffset>6</bitOffset>
60762 <bitWidth>1</bitWidth>
60763 </field>
60764 <field>
60765 <name>TXERR</name>
60766 <description>Transaction error</description>
60767 <bitOffset>7</bitOffset>
60768 <bitWidth>1</bitWidth>
60769 </field>
60770 <field>
60771 <name>BBERR</name>
60772 <description>Babble error</description>
60773 <bitOffset>8</bitOffset>
60774 <bitWidth>1</bitWidth>
60775 </field>
60776 <field>
60777 <name>FRMOR</name>
60778 <description>Frame overrun</description>
60779 <bitOffset>9</bitOffset>
60780 <bitWidth>1</bitWidth>
60781 </field>
60782 <field>
60783 <name>DTERR</name>
60784 <description>Data toggle error</description>
60785 <bitOffset>10</bitOffset>
60786 <bitWidth>1</bitWidth>
60787 </field>
60788 </fields>
60789 </register>
60790 <register>
60791 <name>OTG_HS_HCINT9</name>
60792 <displayName>OTG_HS_HCINT9</displayName>
60793 <description>OTG_HS host channel-9 interrupt
60794 register</description>
60795 <addressOffset>0x228</addressOffset>
60796 <size>32</size>
60797 <access>read-write</access>
60798 <resetValue>0x0</resetValue>
60799 <fields>
60800 <field>
60801 <name>XFRC</name>
60802 <description>Transfer completed</description>
60803 <bitOffset>0</bitOffset>
60804 <bitWidth>1</bitWidth>
60805 </field>
60806 <field>
60807 <name>CHH</name>
60808 <description>Channel halted</description>
60809 <bitOffset>1</bitOffset>
60810 <bitWidth>1</bitWidth>
60811 </field>
60812 <field>
60813 <name>AHBERR</name>
60814 <description>AHB error</description>
60815 <bitOffset>2</bitOffset>
60816 <bitWidth>1</bitWidth>
60817 </field>
60818 <field>
60819 <name>STALL</name>
60820 <description>STALL response received
60821 interrupt</description>
60822 <bitOffset>3</bitOffset>
60823 <bitWidth>1</bitWidth>
60824 </field>
60825 <field>
60826 <name>NAK</name>
60827 <description>NAK response received
60828 interrupt</description>
60829 <bitOffset>4</bitOffset>
60830 <bitWidth>1</bitWidth>
60831 </field>
60832 <field>
60833 <name>ACK</name>
60834 <description>ACK response received/transmitted
60835 interrupt</description>
60836 <bitOffset>5</bitOffset>
60837 <bitWidth>1</bitWidth>
60838 </field>
60839 <field>
60840 <name>NYET</name>
60841 <description>Response received
60842 interrupt</description>
60843 <bitOffset>6</bitOffset>
60844 <bitWidth>1</bitWidth>
60845 </field>
60846 <field>
60847 <name>TXERR</name>
60848 <description>Transaction error</description>
60849 <bitOffset>7</bitOffset>
60850 <bitWidth>1</bitWidth>
60851 </field>
60852 <field>
60853 <name>BBERR</name>
60854 <description>Babble error</description>
60855 <bitOffset>8</bitOffset>
60856 <bitWidth>1</bitWidth>
60857 </field>
60858 <field>
60859 <name>FRMOR</name>
60860 <description>Frame overrun</description>
60861 <bitOffset>9</bitOffset>
60862 <bitWidth>1</bitWidth>
60863 </field>
60864 <field>
60865 <name>DTERR</name>
60866 <description>Data toggle error</description>
60867 <bitOffset>10</bitOffset>
60868 <bitWidth>1</bitWidth>
60869 </field>
60870 </fields>
60871 </register>
60872 <register>
60873 <name>OTG_HS_HCINT10</name>
60874 <displayName>OTG_HS_HCINT10</displayName>
60875 <description>OTG_HS host channel-10 interrupt
60876 register</description>
60877 <addressOffset>0x248</addressOffset>
60878 <size>32</size>
60879 <access>read-write</access>
60880 <resetValue>0x0</resetValue>
60881 <fields>
60882 <field>
60883 <name>XFRC</name>
60884 <description>Transfer completed</description>
60885 <bitOffset>0</bitOffset>
60886 <bitWidth>1</bitWidth>
60887 </field>
60888 <field>
60889 <name>CHH</name>
60890 <description>Channel halted</description>
60891 <bitOffset>1</bitOffset>
60892 <bitWidth>1</bitWidth>
60893 </field>
60894 <field>
60895 <name>AHBERR</name>
60896 <description>AHB error</description>
60897 <bitOffset>2</bitOffset>
60898 <bitWidth>1</bitWidth>
60899 </field>
60900 <field>
60901 <name>STALL</name>
60902 <description>STALL response received
60903 interrupt</description>
60904 <bitOffset>3</bitOffset>
60905 <bitWidth>1</bitWidth>
60906 </field>
60907 <field>
60908 <name>NAK</name>
60909 <description>NAK response received
60910 interrupt</description>
60911 <bitOffset>4</bitOffset>
60912 <bitWidth>1</bitWidth>
60913 </field>
60914 <field>
60915 <name>ACK</name>
60916 <description>ACK response received/transmitted
60917 interrupt</description>
60918 <bitOffset>5</bitOffset>
60919 <bitWidth>1</bitWidth>
60920 </field>
60921 <field>
60922 <name>NYET</name>
60923 <description>Response received
60924 interrupt</description>
60925 <bitOffset>6</bitOffset>
60926 <bitWidth>1</bitWidth>
60927 </field>
60928 <field>
60929 <name>TXERR</name>
60930 <description>Transaction error</description>
60931 <bitOffset>7</bitOffset>
60932 <bitWidth>1</bitWidth>
60933 </field>
60934 <field>
60935 <name>BBERR</name>
60936 <description>Babble error</description>
60937 <bitOffset>8</bitOffset>
60938 <bitWidth>1</bitWidth>
60939 </field>
60940 <field>
60941 <name>FRMOR</name>
60942 <description>Frame overrun</description>
60943 <bitOffset>9</bitOffset>
60944 <bitWidth>1</bitWidth>
60945 </field>
60946 <field>
60947 <name>DTERR</name>
60948 <description>Data toggle error</description>
60949 <bitOffset>10</bitOffset>
60950 <bitWidth>1</bitWidth>
60951 </field>
60952 </fields>
60953 </register>
60954 <register>
60955 <name>OTG_HS_HCINT11</name>
60956 <displayName>OTG_HS_HCINT11</displayName>
60957 <description>OTG_HS host channel-11 interrupt
60958 register</description>
60959 <addressOffset>0x268</addressOffset>
60960 <size>32</size>
60961 <access>read-write</access>
60962 <resetValue>0x0</resetValue>
60963 <fields>
60964 <field>
60965 <name>XFRC</name>
60966 <description>Transfer completed</description>
60967 <bitOffset>0</bitOffset>
60968 <bitWidth>1</bitWidth>
60969 </field>
60970 <field>
60971 <name>CHH</name>
60972 <description>Channel halted</description>
60973 <bitOffset>1</bitOffset>
60974 <bitWidth>1</bitWidth>
60975 </field>
60976 <field>
60977 <name>AHBERR</name>
60978 <description>AHB error</description>
60979 <bitOffset>2</bitOffset>
60980 <bitWidth>1</bitWidth>
60981 </field>
60982 <field>
60983 <name>STALL</name>
60984 <description>STALL response received
60985 interrupt</description>
60986 <bitOffset>3</bitOffset>
60987 <bitWidth>1</bitWidth>
60988 </field>
60989 <field>
60990 <name>NAK</name>
60991 <description>NAK response received
60992 interrupt</description>
60993 <bitOffset>4</bitOffset>
60994 <bitWidth>1</bitWidth>
60995 </field>
60996 <field>
60997 <name>ACK</name>
60998 <description>ACK response received/transmitted
60999 interrupt</description>
61000 <bitOffset>5</bitOffset>
61001 <bitWidth>1</bitWidth>
61002 </field>
61003 <field>
61004 <name>NYET</name>
61005 <description>Response received
61006 interrupt</description>
61007 <bitOffset>6</bitOffset>
61008 <bitWidth>1</bitWidth>
61009 </field>
61010 <field>
61011 <name>TXERR</name>
61012 <description>Transaction error</description>
61013 <bitOffset>7</bitOffset>
61014 <bitWidth>1</bitWidth>
61015 </field>
61016 <field>
61017 <name>BBERR</name>
61018 <description>Babble error</description>
61019 <bitOffset>8</bitOffset>
61020 <bitWidth>1</bitWidth>
61021 </field>
61022 <field>
61023 <name>FRMOR</name>
61024 <description>Frame overrun</description>
61025 <bitOffset>9</bitOffset>
61026 <bitWidth>1</bitWidth>
61027 </field>
61028 <field>
61029 <name>DTERR</name>
61030 <description>Data toggle error</description>
61031 <bitOffset>10</bitOffset>
61032 <bitWidth>1</bitWidth>
61033 </field>
61034 </fields>
61035 </register>
61036 <register>
61037 <name>OTG_HS_HCINTMSK0</name>
61038 <displayName>OTG_HS_HCINTMSK0</displayName>
61039 <description>OTG_HS host channel-11 interrupt mask
61040 register</description>
61041 <addressOffset>0x10C</addressOffset>
61042 <size>32</size>
61043 <access>read-write</access>
61044 <resetValue>0x0</resetValue>
61045 <fields>
61046 <field>
61047 <name>XFRCM</name>
61048 <description>Transfer completed mask</description>
61049 <bitOffset>0</bitOffset>
61050 <bitWidth>1</bitWidth>
61051 </field>
61052 <field>
61053 <name>CHHM</name>
61054 <description>Channel halted mask</description>
61055 <bitOffset>1</bitOffset>
61056 <bitWidth>1</bitWidth>
61057 </field>
61058 <field>
61059 <name>AHBERR</name>
61060 <description>AHB error</description>
61061 <bitOffset>2</bitOffset>
61062 <bitWidth>1</bitWidth>
61063 </field>
61064 <field>
61065 <name>STALLM</name>
61066 <description>STALL response received interrupt
61067 mask</description>
61068 <bitOffset>3</bitOffset>
61069 <bitWidth>1</bitWidth>
61070 </field>
61071 <field>
61072 <name>NAKM</name>
61073 <description>NAK response received interrupt
61074 mask</description>
61075 <bitOffset>4</bitOffset>
61076 <bitWidth>1</bitWidth>
61077 </field>
61078 <field>
61079 <name>ACKM</name>
61080 <description>ACK response received/transmitted
61081 interrupt mask</description>
61082 <bitOffset>5</bitOffset>
61083 <bitWidth>1</bitWidth>
61084 </field>
61085 <field>
61086 <name>NYET</name>
61087 <description>response received interrupt
61088 mask</description>
61089 <bitOffset>6</bitOffset>
61090 <bitWidth>1</bitWidth>
61091 </field>
61092 <field>
61093 <name>TXERRM</name>
61094 <description>Transaction error mask</description>
61095 <bitOffset>7</bitOffset>
61096 <bitWidth>1</bitWidth>
61097 </field>
61098 <field>
61099 <name>BBERRM</name>
61100 <description>Babble error mask</description>
61101 <bitOffset>8</bitOffset>
61102 <bitWidth>1</bitWidth>
61103 </field>
61104 <field>
61105 <name>FRMORM</name>
61106 <description>Frame overrun mask</description>
61107 <bitOffset>9</bitOffset>
61108 <bitWidth>1</bitWidth>
61109 </field>
61110 <field>
61111 <name>DTERRM</name>
61112 <description>Data toggle error mask</description>
61113 <bitOffset>10</bitOffset>
61114 <bitWidth>1</bitWidth>
61115 </field>
61116 </fields>
61117 </register>
61118 <register>
61119 <name>OTG_HS_HCINTMSK1</name>
61120 <displayName>OTG_HS_HCINTMSK1</displayName>
61121 <description>OTG_HS host channel-1 interrupt mask
61122 register</description>
61123 <addressOffset>0x12C</addressOffset>
61124 <size>32</size>
61125 <access>read-write</access>
61126 <resetValue>0x0</resetValue>
61127 <fields>
61128 <field>
61129 <name>XFRCM</name>
61130 <description>Transfer completed mask</description>
61131 <bitOffset>0</bitOffset>
61132 <bitWidth>1</bitWidth>
61133 </field>
61134 <field>
61135 <name>CHHM</name>
61136 <description>Channel halted mask</description>
61137 <bitOffset>1</bitOffset>
61138 <bitWidth>1</bitWidth>
61139 </field>
61140 <field>
61141 <name>AHBERR</name>
61142 <description>AHB error</description>
61143 <bitOffset>2</bitOffset>
61144 <bitWidth>1</bitWidth>
61145 </field>
61146 <field>
61147 <name>STALLM</name>
61148 <description>STALL response received interrupt
61149 mask</description>
61150 <bitOffset>3</bitOffset>
61151 <bitWidth>1</bitWidth>
61152 </field>
61153 <field>
61154 <name>NAKM</name>
61155 <description>NAK response received interrupt
61156 mask</description>
61157 <bitOffset>4</bitOffset>
61158 <bitWidth>1</bitWidth>
61159 </field>
61160 <field>
61161 <name>ACKM</name>
61162 <description>ACK response received/transmitted
61163 interrupt mask</description>
61164 <bitOffset>5</bitOffset>
61165 <bitWidth>1</bitWidth>
61166 </field>
61167 <field>
61168 <name>NYET</name>
61169 <description>response received interrupt
61170 mask</description>
61171 <bitOffset>6</bitOffset>
61172 <bitWidth>1</bitWidth>
61173 </field>
61174 <field>
61175 <name>TXERRM</name>
61176 <description>Transaction error mask</description>
61177 <bitOffset>7</bitOffset>
61178 <bitWidth>1</bitWidth>
61179 </field>
61180 <field>
61181 <name>BBERRM</name>
61182 <description>Babble error mask</description>
61183 <bitOffset>8</bitOffset>
61184 <bitWidth>1</bitWidth>
61185 </field>
61186 <field>
61187 <name>FRMORM</name>
61188 <description>Frame overrun mask</description>
61189 <bitOffset>9</bitOffset>
61190 <bitWidth>1</bitWidth>
61191 </field>
61192 <field>
61193 <name>DTERRM</name>
61194 <description>Data toggle error mask</description>
61195 <bitOffset>10</bitOffset>
61196 <bitWidth>1</bitWidth>
61197 </field>
61198 </fields>
61199 </register>
61200 <register>
61201 <name>OTG_HS_HCINTMSK2</name>
61202 <displayName>OTG_HS_HCINTMSK2</displayName>
61203 <description>OTG_HS host channel-2 interrupt mask
61204 register</description>
61205 <addressOffset>0x14C</addressOffset>
61206 <size>32</size>
61207 <access>read-write</access>
61208 <resetValue>0x0</resetValue>
61209 <fields>
61210 <field>
61211 <name>XFRCM</name>
61212 <description>Transfer completed mask</description>
61213 <bitOffset>0</bitOffset>
61214 <bitWidth>1</bitWidth>
61215 </field>
61216 <field>
61217 <name>CHHM</name>
61218 <description>Channel halted mask</description>
61219 <bitOffset>1</bitOffset>
61220 <bitWidth>1</bitWidth>
61221 </field>
61222 <field>
61223 <name>AHBERR</name>
61224 <description>AHB error</description>
61225 <bitOffset>2</bitOffset>
61226 <bitWidth>1</bitWidth>
61227 </field>
61228 <field>
61229 <name>STALLM</name>
61230 <description>STALL response received interrupt
61231 mask</description>
61232 <bitOffset>3</bitOffset>
61233 <bitWidth>1</bitWidth>
61234 </field>
61235 <field>
61236 <name>NAKM</name>
61237 <description>NAK response received interrupt
61238 mask</description>
61239 <bitOffset>4</bitOffset>
61240 <bitWidth>1</bitWidth>
61241 </field>
61242 <field>
61243 <name>ACKM</name>
61244 <description>ACK response received/transmitted
61245 interrupt mask</description>
61246 <bitOffset>5</bitOffset>
61247 <bitWidth>1</bitWidth>
61248 </field>
61249 <field>
61250 <name>NYET</name>
61251 <description>response received interrupt
61252 mask</description>
61253 <bitOffset>6</bitOffset>
61254 <bitWidth>1</bitWidth>
61255 </field>
61256 <field>
61257 <name>TXERRM</name>
61258 <description>Transaction error mask</description>
61259 <bitOffset>7</bitOffset>
61260 <bitWidth>1</bitWidth>
61261 </field>
61262 <field>
61263 <name>BBERRM</name>
61264 <description>Babble error mask</description>
61265 <bitOffset>8</bitOffset>
61266 <bitWidth>1</bitWidth>
61267 </field>
61268 <field>
61269 <name>FRMORM</name>
61270 <description>Frame overrun mask</description>
61271 <bitOffset>9</bitOffset>
61272 <bitWidth>1</bitWidth>
61273 </field>
61274 <field>
61275 <name>DTERRM</name>
61276 <description>Data toggle error mask</description>
61277 <bitOffset>10</bitOffset>
61278 <bitWidth>1</bitWidth>
61279 </field>
61280 </fields>
61281 </register>
61282 <register>
61283 <name>OTG_HS_HCINTMSK3</name>
61284 <displayName>OTG_HS_HCINTMSK3</displayName>
61285 <description>OTG_HS host channel-3 interrupt mask
61286 register</description>
61287 <addressOffset>0x16C</addressOffset>
61288 <size>32</size>
61289 <access>read-write</access>
61290 <resetValue>0x0</resetValue>
61291 <fields>
61292 <field>
61293 <name>XFRCM</name>
61294 <description>Transfer completed mask</description>
61295 <bitOffset>0</bitOffset>
61296 <bitWidth>1</bitWidth>
61297 </field>
61298 <field>
61299 <name>CHHM</name>
61300 <description>Channel halted mask</description>
61301 <bitOffset>1</bitOffset>
61302 <bitWidth>1</bitWidth>
61303 </field>
61304 <field>
61305 <name>AHBERR</name>
61306 <description>AHB error</description>
61307 <bitOffset>2</bitOffset>
61308 <bitWidth>1</bitWidth>
61309 </field>
61310 <field>
61311 <name>STALLM</name>
61312 <description>STALL response received interrupt
61313 mask</description>
61314 <bitOffset>3</bitOffset>
61315 <bitWidth>1</bitWidth>
61316 </field>
61317 <field>
61318 <name>NAKM</name>
61319 <description>NAK response received interrupt
61320 mask</description>
61321 <bitOffset>4</bitOffset>
61322 <bitWidth>1</bitWidth>
61323 </field>
61324 <field>
61325 <name>ACKM</name>
61326 <description>ACK response received/transmitted
61327 interrupt mask</description>
61328 <bitOffset>5</bitOffset>
61329 <bitWidth>1</bitWidth>
61330 </field>
61331 <field>
61332 <name>NYET</name>
61333 <description>response received interrupt
61334 mask</description>
61335 <bitOffset>6</bitOffset>
61336 <bitWidth>1</bitWidth>
61337 </field>
61338 <field>
61339 <name>TXERRM</name>
61340 <description>Transaction error mask</description>
61341 <bitOffset>7</bitOffset>
61342 <bitWidth>1</bitWidth>
61343 </field>
61344 <field>
61345 <name>BBERRM</name>
61346 <description>Babble error mask</description>
61347 <bitOffset>8</bitOffset>
61348 <bitWidth>1</bitWidth>
61349 </field>
61350 <field>
61351 <name>FRMORM</name>
61352 <description>Frame overrun mask</description>
61353 <bitOffset>9</bitOffset>
61354 <bitWidth>1</bitWidth>
61355 </field>
61356 <field>
61357 <name>DTERRM</name>
61358 <description>Data toggle error mask</description>
61359 <bitOffset>10</bitOffset>
61360 <bitWidth>1</bitWidth>
61361 </field>
61362 </fields>
61363 </register>
61364 <register>
61365 <name>OTG_HS_HCINTMSK4</name>
61366 <displayName>OTG_HS_HCINTMSK4</displayName>
61367 <description>OTG_HS host channel-4 interrupt mask
61368 register</description>
61369 <addressOffset>0x18C</addressOffset>
61370 <size>32</size>
61371 <access>read-write</access>
61372 <resetValue>0x0</resetValue>
61373 <fields>
61374 <field>
61375 <name>XFRCM</name>
61376 <description>Transfer completed mask</description>
61377 <bitOffset>0</bitOffset>
61378 <bitWidth>1</bitWidth>
61379 </field>
61380 <field>
61381 <name>CHHM</name>
61382 <description>Channel halted mask</description>
61383 <bitOffset>1</bitOffset>
61384 <bitWidth>1</bitWidth>
61385 </field>
61386 <field>
61387 <name>AHBERR</name>
61388 <description>AHB error</description>
61389 <bitOffset>2</bitOffset>
61390 <bitWidth>1</bitWidth>
61391 </field>
61392 <field>
61393 <name>STALLM</name>
61394 <description>STALL response received interrupt
61395 mask</description>
61396 <bitOffset>3</bitOffset>
61397 <bitWidth>1</bitWidth>
61398 </field>
61399 <field>
61400 <name>NAKM</name>
61401 <description>NAK response received interrupt
61402 mask</description>
61403 <bitOffset>4</bitOffset>
61404 <bitWidth>1</bitWidth>
61405 </field>
61406 <field>
61407 <name>ACKM</name>
61408 <description>ACK response received/transmitted
61409 interrupt mask</description>
61410 <bitOffset>5</bitOffset>
61411 <bitWidth>1</bitWidth>
61412 </field>
61413 <field>
61414 <name>NYET</name>
61415 <description>response received interrupt
61416 mask</description>
61417 <bitOffset>6</bitOffset>
61418 <bitWidth>1</bitWidth>
61419 </field>
61420 <field>
61421 <name>TXERRM</name>
61422 <description>Transaction error mask</description>
61423 <bitOffset>7</bitOffset>
61424 <bitWidth>1</bitWidth>
61425 </field>
61426 <field>
61427 <name>BBERRM</name>
61428 <description>Babble error mask</description>
61429 <bitOffset>8</bitOffset>
61430 <bitWidth>1</bitWidth>
61431 </field>
61432 <field>
61433 <name>FRMORM</name>
61434 <description>Frame overrun mask</description>
61435 <bitOffset>9</bitOffset>
61436 <bitWidth>1</bitWidth>
61437 </field>
61438 <field>
61439 <name>DTERRM</name>
61440 <description>Data toggle error mask</description>
61441 <bitOffset>10</bitOffset>
61442 <bitWidth>1</bitWidth>
61443 </field>
61444 </fields>
61445 </register>
61446 <register>
61447 <name>OTG_HS_HCINTMSK5</name>
61448 <displayName>OTG_HS_HCINTMSK5</displayName>
61449 <description>OTG_HS host channel-5 interrupt mask
61450 register</description>
61451 <addressOffset>0x1AC</addressOffset>
61452 <size>32</size>
61453 <access>read-write</access>
61454 <resetValue>0x0</resetValue>
61455 <fields>
61456 <field>
61457 <name>XFRCM</name>
61458 <description>Transfer completed mask</description>
61459 <bitOffset>0</bitOffset>
61460 <bitWidth>1</bitWidth>
61461 </field>
61462 <field>
61463 <name>CHHM</name>
61464 <description>Channel halted mask</description>
61465 <bitOffset>1</bitOffset>
61466 <bitWidth>1</bitWidth>
61467 </field>
61468 <field>
61469 <name>AHBERR</name>
61470 <description>AHB error</description>
61471 <bitOffset>2</bitOffset>
61472 <bitWidth>1</bitWidth>
61473 </field>
61474 <field>
61475 <name>STALLM</name>
61476 <description>STALL response received interrupt
61477 mask</description>
61478 <bitOffset>3</bitOffset>
61479 <bitWidth>1</bitWidth>
61480 </field>
61481 <field>
61482 <name>NAKM</name>
61483 <description>NAK response received interrupt
61484 mask</description>
61485 <bitOffset>4</bitOffset>
61486 <bitWidth>1</bitWidth>
61487 </field>
61488 <field>
61489 <name>ACKM</name>
61490 <description>ACK response received/transmitted
61491 interrupt mask</description>
61492 <bitOffset>5</bitOffset>
61493 <bitWidth>1</bitWidth>
61494 </field>
61495 <field>
61496 <name>NYET</name>
61497 <description>response received interrupt
61498 mask</description>
61499 <bitOffset>6</bitOffset>
61500 <bitWidth>1</bitWidth>
61501 </field>
61502 <field>
61503 <name>TXERRM</name>
61504 <description>Transaction error mask</description>
61505 <bitOffset>7</bitOffset>
61506 <bitWidth>1</bitWidth>
61507 </field>
61508 <field>
61509 <name>BBERRM</name>
61510 <description>Babble error mask</description>
61511 <bitOffset>8</bitOffset>
61512 <bitWidth>1</bitWidth>
61513 </field>
61514 <field>
61515 <name>FRMORM</name>
61516 <description>Frame overrun mask</description>
61517 <bitOffset>9</bitOffset>
61518 <bitWidth>1</bitWidth>
61519 </field>
61520 <field>
61521 <name>DTERRM</name>
61522 <description>Data toggle error mask</description>
61523 <bitOffset>10</bitOffset>
61524 <bitWidth>1</bitWidth>
61525 </field>
61526 </fields>
61527 </register>
61528 <register>
61529 <name>OTG_HS_HCINTMSK6</name>
61530 <displayName>OTG_HS_HCINTMSK6</displayName>
61531 <description>OTG_HS host channel-6 interrupt mask
61532 register</description>
61533 <addressOffset>0x1CC</addressOffset>
61534 <size>32</size>
61535 <access>read-write</access>
61536 <resetValue>0x0</resetValue>
61537 <fields>
61538 <field>
61539 <name>XFRCM</name>
61540 <description>Transfer completed mask</description>
61541 <bitOffset>0</bitOffset>
61542 <bitWidth>1</bitWidth>
61543 </field>
61544 <field>
61545 <name>CHHM</name>
61546 <description>Channel halted mask</description>
61547 <bitOffset>1</bitOffset>
61548 <bitWidth>1</bitWidth>
61549 </field>
61550 <field>
61551 <name>AHBERR</name>
61552 <description>AHB error</description>
61553 <bitOffset>2</bitOffset>
61554 <bitWidth>1</bitWidth>
61555 </field>
61556 <field>
61557 <name>STALLM</name>
61558 <description>STALL response received interrupt
61559 mask</description>
61560 <bitOffset>3</bitOffset>
61561 <bitWidth>1</bitWidth>
61562 </field>
61563 <field>
61564 <name>NAKM</name>
61565 <description>NAK response received interrupt
61566 mask</description>
61567 <bitOffset>4</bitOffset>
61568 <bitWidth>1</bitWidth>
61569 </field>
61570 <field>
61571 <name>ACKM</name>
61572 <description>ACK response received/transmitted
61573 interrupt mask</description>
61574 <bitOffset>5</bitOffset>
61575 <bitWidth>1</bitWidth>
61576 </field>
61577 <field>
61578 <name>NYET</name>
61579 <description>response received interrupt
61580 mask</description>
61581 <bitOffset>6</bitOffset>
61582 <bitWidth>1</bitWidth>
61583 </field>
61584 <field>
61585 <name>TXERRM</name>
61586 <description>Transaction error mask</description>
61587 <bitOffset>7</bitOffset>
61588 <bitWidth>1</bitWidth>
61589 </field>
61590 <field>
61591 <name>BBERRM</name>
61592 <description>Babble error mask</description>
61593 <bitOffset>8</bitOffset>
61594 <bitWidth>1</bitWidth>
61595 </field>
61596 <field>
61597 <name>FRMORM</name>
61598 <description>Frame overrun mask</description>
61599 <bitOffset>9</bitOffset>
61600 <bitWidth>1</bitWidth>
61601 </field>
61602 <field>
61603 <name>DTERRM</name>
61604 <description>Data toggle error mask</description>
61605 <bitOffset>10</bitOffset>
61606 <bitWidth>1</bitWidth>
61607 </field>
61608 </fields>
61609 </register>
61610 <register>
61611 <name>OTG_HS_HCINTMSK7</name>
61612 <displayName>OTG_HS_HCINTMSK7</displayName>
61613 <description>OTG_HS host channel-7 interrupt mask
61614 register</description>
61615 <addressOffset>0x1EC</addressOffset>
61616 <size>32</size>
61617 <access>read-write</access>
61618 <resetValue>0x0</resetValue>
61619 <fields>
61620 <field>
61621 <name>XFRCM</name>
61622 <description>Transfer completed mask</description>
61623 <bitOffset>0</bitOffset>
61624 <bitWidth>1</bitWidth>
61625 </field>
61626 <field>
61627 <name>CHHM</name>
61628 <description>Channel halted mask</description>
61629 <bitOffset>1</bitOffset>
61630 <bitWidth>1</bitWidth>
61631 </field>
61632 <field>
61633 <name>AHBERR</name>
61634 <description>AHB error</description>
61635 <bitOffset>2</bitOffset>
61636 <bitWidth>1</bitWidth>
61637 </field>
61638 <field>
61639 <name>STALLM</name>
61640 <description>STALL response received interrupt
61641 mask</description>
61642 <bitOffset>3</bitOffset>
61643 <bitWidth>1</bitWidth>
61644 </field>
61645 <field>
61646 <name>NAKM</name>
61647 <description>NAK response received interrupt
61648 mask</description>
61649 <bitOffset>4</bitOffset>
61650 <bitWidth>1</bitWidth>
61651 </field>
61652 <field>
61653 <name>ACKM</name>
61654 <description>ACK response received/transmitted
61655 interrupt mask</description>
61656 <bitOffset>5</bitOffset>
61657 <bitWidth>1</bitWidth>
61658 </field>
61659 <field>
61660 <name>NYET</name>
61661 <description>response received interrupt
61662 mask</description>
61663 <bitOffset>6</bitOffset>
61664 <bitWidth>1</bitWidth>
61665 </field>
61666 <field>
61667 <name>TXERRM</name>
61668 <description>Transaction error mask</description>
61669 <bitOffset>7</bitOffset>
61670 <bitWidth>1</bitWidth>
61671 </field>
61672 <field>
61673 <name>BBERRM</name>
61674 <description>Babble error mask</description>
61675 <bitOffset>8</bitOffset>
61676 <bitWidth>1</bitWidth>
61677 </field>
61678 <field>
61679 <name>FRMORM</name>
61680 <description>Frame overrun mask</description>
61681 <bitOffset>9</bitOffset>
61682 <bitWidth>1</bitWidth>
61683 </field>
61684 <field>
61685 <name>DTERRM</name>
61686 <description>Data toggle error mask</description>
61687 <bitOffset>10</bitOffset>
61688 <bitWidth>1</bitWidth>
61689 </field>
61690 </fields>
61691 </register>
61692 <register>
61693 <name>OTG_HS_HCINTMSK8</name>
61694 <displayName>OTG_HS_HCINTMSK8</displayName>
61695 <description>OTG_HS host channel-8 interrupt mask
61696 register</description>
61697 <addressOffset>0x20C</addressOffset>
61698 <size>32</size>
61699 <access>read-write</access>
61700 <resetValue>0x0</resetValue>
61701 <fields>
61702 <field>
61703 <name>XFRCM</name>
61704 <description>Transfer completed mask</description>
61705 <bitOffset>0</bitOffset>
61706 <bitWidth>1</bitWidth>
61707 </field>
61708 <field>
61709 <name>CHHM</name>
61710 <description>Channel halted mask</description>
61711 <bitOffset>1</bitOffset>
61712 <bitWidth>1</bitWidth>
61713 </field>
61714 <field>
61715 <name>AHBERR</name>
61716 <description>AHB error</description>
61717 <bitOffset>2</bitOffset>
61718 <bitWidth>1</bitWidth>
61719 </field>
61720 <field>
61721 <name>STALLM</name>
61722 <description>STALL response received interrupt
61723 mask</description>
61724 <bitOffset>3</bitOffset>
61725 <bitWidth>1</bitWidth>
61726 </field>
61727 <field>
61728 <name>NAKM</name>
61729 <description>NAK response received interrupt
61730 mask</description>
61731 <bitOffset>4</bitOffset>
61732 <bitWidth>1</bitWidth>
61733 </field>
61734 <field>
61735 <name>ACKM</name>
61736 <description>ACK response received/transmitted
61737 interrupt mask</description>
61738 <bitOffset>5</bitOffset>
61739 <bitWidth>1</bitWidth>
61740 </field>
61741 <field>
61742 <name>NYET</name>
61743 <description>response received interrupt
61744 mask</description>
61745 <bitOffset>6</bitOffset>
61746 <bitWidth>1</bitWidth>
61747 </field>
61748 <field>
61749 <name>TXERRM</name>
61750 <description>Transaction error mask</description>
61751 <bitOffset>7</bitOffset>
61752 <bitWidth>1</bitWidth>
61753 </field>
61754 <field>
61755 <name>BBERRM</name>
61756 <description>Babble error mask</description>
61757 <bitOffset>8</bitOffset>
61758 <bitWidth>1</bitWidth>
61759 </field>
61760 <field>
61761 <name>FRMORM</name>
61762 <description>Frame overrun mask</description>
61763 <bitOffset>9</bitOffset>
61764 <bitWidth>1</bitWidth>
61765 </field>
61766 <field>
61767 <name>DTERRM</name>
61768 <description>Data toggle error mask</description>
61769 <bitOffset>10</bitOffset>
61770 <bitWidth>1</bitWidth>
61771 </field>
61772 </fields>
61773 </register>
61774 <register>
61775 <name>OTG_HS_HCINTMSK9</name>
61776 <displayName>OTG_HS_HCINTMSK9</displayName>
61777 <description>OTG_HS host channel-9 interrupt mask
61778 register</description>
61779 <addressOffset>0x22C</addressOffset>
61780 <size>32</size>
61781 <access>read-write</access>
61782 <resetValue>0x0</resetValue>
61783 <fields>
61784 <field>
61785 <name>XFRCM</name>
61786 <description>Transfer completed mask</description>
61787 <bitOffset>0</bitOffset>
61788 <bitWidth>1</bitWidth>
61789 </field>
61790 <field>
61791 <name>CHHM</name>
61792 <description>Channel halted mask</description>
61793 <bitOffset>1</bitOffset>
61794 <bitWidth>1</bitWidth>
61795 </field>
61796 <field>
61797 <name>AHBERR</name>
61798 <description>AHB error</description>
61799 <bitOffset>2</bitOffset>
61800 <bitWidth>1</bitWidth>
61801 </field>
61802 <field>
61803 <name>STALLM</name>
61804 <description>STALL response received interrupt
61805 mask</description>
61806 <bitOffset>3</bitOffset>
61807 <bitWidth>1</bitWidth>
61808 </field>
61809 <field>
61810 <name>NAKM</name>
61811 <description>NAK response received interrupt
61812 mask</description>
61813 <bitOffset>4</bitOffset>
61814 <bitWidth>1</bitWidth>
61815 </field>
61816 <field>
61817 <name>ACKM</name>
61818 <description>ACK response received/transmitted
61819 interrupt mask</description>
61820 <bitOffset>5</bitOffset>
61821 <bitWidth>1</bitWidth>
61822 </field>
61823 <field>
61824 <name>NYET</name>
61825 <description>response received interrupt
61826 mask</description>
61827 <bitOffset>6</bitOffset>
61828 <bitWidth>1</bitWidth>
61829 </field>
61830 <field>
61831 <name>TXERRM</name>
61832 <description>Transaction error mask</description>
61833 <bitOffset>7</bitOffset>
61834 <bitWidth>1</bitWidth>
61835 </field>
61836 <field>
61837 <name>BBERRM</name>
61838 <description>Babble error mask</description>
61839 <bitOffset>8</bitOffset>
61840 <bitWidth>1</bitWidth>
61841 </field>
61842 <field>
61843 <name>FRMORM</name>
61844 <description>Frame overrun mask</description>
61845 <bitOffset>9</bitOffset>
61846 <bitWidth>1</bitWidth>
61847 </field>
61848 <field>
61849 <name>DTERRM</name>
61850 <description>Data toggle error mask</description>
61851 <bitOffset>10</bitOffset>
61852 <bitWidth>1</bitWidth>
61853 </field>
61854 </fields>
61855 </register>
61856 <register>
61857 <name>OTG_HS_HCINTMSK10</name>
61858 <displayName>OTG_HS_HCINTMSK10</displayName>
61859 <description>OTG_HS host channel-10 interrupt mask
61860 register</description>
61861 <addressOffset>0x24C</addressOffset>
61862 <size>32</size>
61863 <access>read-write</access>
61864 <resetValue>0x0</resetValue>
61865 <fields>
61866 <field>
61867 <name>XFRCM</name>
61868 <description>Transfer completed mask</description>
61869 <bitOffset>0</bitOffset>
61870 <bitWidth>1</bitWidth>
61871 </field>
61872 <field>
61873 <name>CHHM</name>
61874 <description>Channel halted mask</description>
61875 <bitOffset>1</bitOffset>
61876 <bitWidth>1</bitWidth>
61877 </field>
61878 <field>
61879 <name>AHBERR</name>
61880 <description>AHB error</description>
61881 <bitOffset>2</bitOffset>
61882 <bitWidth>1</bitWidth>
61883 </field>
61884 <field>
61885 <name>STALLM</name>
61886 <description>STALL response received interrupt
61887 mask</description>
61888 <bitOffset>3</bitOffset>
61889 <bitWidth>1</bitWidth>
61890 </field>
61891 <field>
61892 <name>NAKM</name>
61893 <description>NAK response received interrupt
61894 mask</description>
61895 <bitOffset>4</bitOffset>
61896 <bitWidth>1</bitWidth>
61897 </field>
61898 <field>
61899 <name>ACKM</name>
61900 <description>ACK response received/transmitted
61901 interrupt mask</description>
61902 <bitOffset>5</bitOffset>
61903 <bitWidth>1</bitWidth>
61904 </field>
61905 <field>
61906 <name>NYET</name>
61907 <description>response received interrupt
61908 mask</description>
61909 <bitOffset>6</bitOffset>
61910 <bitWidth>1</bitWidth>
61911 </field>
61912 <field>
61913 <name>TXERRM</name>
61914 <description>Transaction error mask</description>
61915 <bitOffset>7</bitOffset>
61916 <bitWidth>1</bitWidth>
61917 </field>
61918 <field>
61919 <name>BBERRM</name>
61920 <description>Babble error mask</description>
61921 <bitOffset>8</bitOffset>
61922 <bitWidth>1</bitWidth>
61923 </field>
61924 <field>
61925 <name>FRMORM</name>
61926 <description>Frame overrun mask</description>
61927 <bitOffset>9</bitOffset>
61928 <bitWidth>1</bitWidth>
61929 </field>
61930 <field>
61931 <name>DTERRM</name>
61932 <description>Data toggle error mask</description>
61933 <bitOffset>10</bitOffset>
61934 <bitWidth>1</bitWidth>
61935 </field>
61936 </fields>
61937 </register>
61938 <register>
61939 <name>OTG_HS_HCINTMSK11</name>
61940 <displayName>OTG_HS_HCINTMSK11</displayName>
61941 <description>OTG_HS host channel-11 interrupt mask
61942 register</description>
61943 <addressOffset>0x26C</addressOffset>
61944 <size>32</size>
61945 <access>read-write</access>
61946 <resetValue>0x0</resetValue>
61947 <fields>
61948 <field>
61949 <name>XFRCM</name>
61950 <description>Transfer completed mask</description>
61951 <bitOffset>0</bitOffset>
61952 <bitWidth>1</bitWidth>
61953 </field>
61954 <field>
61955 <name>CHHM</name>
61956 <description>Channel halted mask</description>
61957 <bitOffset>1</bitOffset>
61958 <bitWidth>1</bitWidth>
61959 </field>
61960 <field>
61961 <name>AHBERR</name>
61962 <description>AHB error</description>
61963 <bitOffset>2</bitOffset>
61964 <bitWidth>1</bitWidth>
61965 </field>
61966 <field>
61967 <name>STALLM</name>
61968 <description>STALL response received interrupt
61969 mask</description>
61970 <bitOffset>3</bitOffset>
61971 <bitWidth>1</bitWidth>
61972 </field>
61973 <field>
61974 <name>NAKM</name>
61975 <description>NAK response received interrupt
61976 mask</description>
61977 <bitOffset>4</bitOffset>
61978 <bitWidth>1</bitWidth>
61979 </field>
61980 <field>
61981 <name>ACKM</name>
61982 <description>ACK response received/transmitted
61983 interrupt mask</description>
61984 <bitOffset>5</bitOffset>
61985 <bitWidth>1</bitWidth>
61986 </field>
61987 <field>
61988 <name>NYET</name>
61989 <description>response received interrupt
61990 mask</description>
61991 <bitOffset>6</bitOffset>
61992 <bitWidth>1</bitWidth>
61993 </field>
61994 <field>
61995 <name>TXERRM</name>
61996 <description>Transaction error mask</description>
61997 <bitOffset>7</bitOffset>
61998 <bitWidth>1</bitWidth>
61999 </field>
62000 <field>
62001 <name>BBERRM</name>
62002 <description>Babble error mask</description>
62003 <bitOffset>8</bitOffset>
62004 <bitWidth>1</bitWidth>
62005 </field>
62006 <field>
62007 <name>FRMORM</name>
62008 <description>Frame overrun mask</description>
62009 <bitOffset>9</bitOffset>
62010 <bitWidth>1</bitWidth>
62011 </field>
62012 <field>
62013 <name>DTERRM</name>
62014 <description>Data toggle error mask</description>
62015 <bitOffset>10</bitOffset>
62016 <bitWidth>1</bitWidth>
62017 </field>
62018 </fields>
62019 </register>
62020 <register>
62021 <name>OTG_HS_HCTSIZ0</name>
62022 <displayName>OTG_HS_HCTSIZ0</displayName>
62023 <description>OTG_HS host channel-11 transfer size
62024 register</description>
62025 <addressOffset>0x110</addressOffset>
62026 <size>32</size>
62027 <access>read-write</access>
62028 <resetValue>0x0</resetValue>
62029 <fields>
62030 <field>
62031 <name>XFRSIZ</name>
62032 <description>Transfer size</description>
62033 <bitOffset>0</bitOffset>
62034 <bitWidth>19</bitWidth>
62035 </field>
62036 <field>
62037 <name>PKTCNT</name>
62038 <description>Packet count</description>
62039 <bitOffset>19</bitOffset>
62040 <bitWidth>10</bitWidth>
62041 </field>
62042 <field>
62043 <name>DPID</name>
62044 <description>Data PID</description>
62045 <bitOffset>29</bitOffset>
62046 <bitWidth>2</bitWidth>
62047 </field>
62048 </fields>
62049 </register>
62050 <register>
62051 <name>OTG_HS_HCTSIZ1</name>
62052 <displayName>OTG_HS_HCTSIZ1</displayName>
62053 <description>OTG_HS host channel-1 transfer size
62054 register</description>
62055 <addressOffset>0x130</addressOffset>
62056 <size>32</size>
62057 <access>read-write</access>
62058 <resetValue>0x0</resetValue>
62059 <fields>
62060 <field>
62061 <name>XFRSIZ</name>
62062 <description>Transfer size</description>
62063 <bitOffset>0</bitOffset>
62064 <bitWidth>19</bitWidth>
62065 </field>
62066 <field>
62067 <name>PKTCNT</name>
62068 <description>Packet count</description>
62069 <bitOffset>19</bitOffset>
62070 <bitWidth>10</bitWidth>
62071 </field>
62072 <field>
62073 <name>DPID</name>
62074 <description>Data PID</description>
62075 <bitOffset>29</bitOffset>
62076 <bitWidth>2</bitWidth>
62077 </field>
62078 </fields>
62079 </register>
62080 <register>
62081 <name>OTG_HS_HCTSIZ2</name>
62082 <displayName>OTG_HS_HCTSIZ2</displayName>
62083 <description>OTG_HS host channel-2 transfer size
62084 register</description>
62085 <addressOffset>0x150</addressOffset>
62086 <size>32</size>
62087 <access>read-write</access>
62088 <resetValue>0x0</resetValue>
62089 <fields>
62090 <field>
62091 <name>XFRSIZ</name>
62092 <description>Transfer size</description>
62093 <bitOffset>0</bitOffset>
62094 <bitWidth>19</bitWidth>
62095 </field>
62096 <field>
62097 <name>PKTCNT</name>
62098 <description>Packet count</description>
62099 <bitOffset>19</bitOffset>
62100 <bitWidth>10</bitWidth>
62101 </field>
62102 <field>
62103 <name>DPID</name>
62104 <description>Data PID</description>
62105 <bitOffset>29</bitOffset>
62106 <bitWidth>2</bitWidth>
62107 </field>
62108 </fields>
62109 </register>
62110 <register>
62111 <name>OTG_HS_HCTSIZ3</name>
62112 <displayName>OTG_HS_HCTSIZ3</displayName>
62113 <description>OTG_HS host channel-3 transfer size
62114 register</description>
62115 <addressOffset>0x170</addressOffset>
62116 <size>32</size>
62117 <access>read-write</access>
62118 <resetValue>0x0</resetValue>
62119 <fields>
62120 <field>
62121 <name>XFRSIZ</name>
62122 <description>Transfer size</description>
62123 <bitOffset>0</bitOffset>
62124 <bitWidth>19</bitWidth>
62125 </field>
62126 <field>
62127 <name>PKTCNT</name>
62128 <description>Packet count</description>
62129 <bitOffset>19</bitOffset>
62130 <bitWidth>10</bitWidth>
62131 </field>
62132 <field>
62133 <name>DPID</name>
62134 <description>Data PID</description>
62135 <bitOffset>29</bitOffset>
62136 <bitWidth>2</bitWidth>
62137 </field>
62138 </fields>
62139 </register>
62140 <register>
62141 <name>OTG_HS_HCTSIZ4</name>
62142 <displayName>OTG_HS_HCTSIZ4</displayName>
62143 <description>OTG_HS host channel-4 transfer size
62144 register</description>
62145 <addressOffset>0x190</addressOffset>
62146 <size>32</size>
62147 <access>read-write</access>
62148 <resetValue>0x0</resetValue>
62149 <fields>
62150 <field>
62151 <name>XFRSIZ</name>
62152 <description>Transfer size</description>
62153 <bitOffset>0</bitOffset>
62154 <bitWidth>19</bitWidth>
62155 </field>
62156 <field>
62157 <name>PKTCNT</name>
62158 <description>Packet count</description>
62159 <bitOffset>19</bitOffset>
62160 <bitWidth>10</bitWidth>
62161 </field>
62162 <field>
62163 <name>DPID</name>
62164 <description>Data PID</description>
62165 <bitOffset>29</bitOffset>
62166 <bitWidth>2</bitWidth>
62167 </field>
62168 </fields>
62169 </register>
62170 <register>
62171 <name>OTG_HS_HCTSIZ5</name>
62172 <displayName>OTG_HS_HCTSIZ5</displayName>
62173 <description>OTG_HS host channel-5 transfer size
62174 register</description>
62175 <addressOffset>0x1B0</addressOffset>
62176 <size>32</size>
62177 <access>read-write</access>
62178 <resetValue>0x0</resetValue>
62179 <fields>
62180 <field>
62181 <name>XFRSIZ</name>
62182 <description>Transfer size</description>
62183 <bitOffset>0</bitOffset>
62184 <bitWidth>19</bitWidth>
62185 </field>
62186 <field>
62187 <name>PKTCNT</name>
62188 <description>Packet count</description>
62189 <bitOffset>19</bitOffset>
62190 <bitWidth>10</bitWidth>
62191 </field>
62192 <field>
62193 <name>DPID</name>
62194 <description>Data PID</description>
62195 <bitOffset>29</bitOffset>
62196 <bitWidth>2</bitWidth>
62197 </field>
62198 </fields>
62199 </register>
62200 <register>
62201 <name>OTG_HS_HCTSIZ6</name>
62202 <displayName>OTG_HS_HCTSIZ6</displayName>
62203 <description>OTG_HS host channel-6 transfer size
62204 register</description>
62205 <addressOffset>0x1D0</addressOffset>
62206 <size>32</size>
62207 <access>read-write</access>
62208 <resetValue>0x0</resetValue>
62209 <fields>
62210 <field>
62211 <name>XFRSIZ</name>
62212 <description>Transfer size</description>
62213 <bitOffset>0</bitOffset>
62214 <bitWidth>19</bitWidth>
62215 </field>
62216 <field>
62217 <name>PKTCNT</name>
62218 <description>Packet count</description>
62219 <bitOffset>19</bitOffset>
62220 <bitWidth>10</bitWidth>
62221 </field>
62222 <field>
62223 <name>DPID</name>
62224 <description>Data PID</description>
62225 <bitOffset>29</bitOffset>
62226 <bitWidth>2</bitWidth>
62227 </field>
62228 </fields>
62229 </register>
62230 <register>
62231 <name>OTG_HS_HCTSIZ7</name>
62232 <displayName>OTG_HS_HCTSIZ7</displayName>
62233 <description>OTG_HS host channel-7 transfer size
62234 register</description>
62235 <addressOffset>0x1F0</addressOffset>
62236 <size>32</size>
62237 <access>read-write</access>
62238 <resetValue>0x0</resetValue>
62239 <fields>
62240 <field>
62241 <name>XFRSIZ</name>
62242 <description>Transfer size</description>
62243 <bitOffset>0</bitOffset>
62244 <bitWidth>19</bitWidth>
62245 </field>
62246 <field>
62247 <name>PKTCNT</name>
62248 <description>Packet count</description>
62249 <bitOffset>19</bitOffset>
62250 <bitWidth>10</bitWidth>
62251 </field>
62252 <field>
62253 <name>DPID</name>
62254 <description>Data PID</description>
62255 <bitOffset>29</bitOffset>
62256 <bitWidth>2</bitWidth>
62257 </field>
62258 </fields>
62259 </register>
62260 <register>
62261 <name>OTG_HS_HCTSIZ8</name>
62262 <displayName>OTG_HS_HCTSIZ8</displayName>
62263 <description>OTG_HS host channel-8 transfer size
62264 register</description>
62265 <addressOffset>0x210</addressOffset>
62266 <size>32</size>
62267 <access>read-write</access>
62268 <resetValue>0x0</resetValue>
62269 <fields>
62270 <field>
62271 <name>XFRSIZ</name>
62272 <description>Transfer size</description>
62273 <bitOffset>0</bitOffset>
62274 <bitWidth>19</bitWidth>
62275 </field>
62276 <field>
62277 <name>PKTCNT</name>
62278 <description>Packet count</description>
62279 <bitOffset>19</bitOffset>
62280 <bitWidth>10</bitWidth>
62281 </field>
62282 <field>
62283 <name>DPID</name>
62284 <description>Data PID</description>
62285 <bitOffset>29</bitOffset>
62286 <bitWidth>2</bitWidth>
62287 </field>
62288 </fields>
62289 </register>
62290 <register>
62291 <name>OTG_HS_HCTSIZ9</name>
62292 <displayName>OTG_HS_HCTSIZ9</displayName>
62293 <description>OTG_HS host channel-9 transfer size
62294 register</description>
62295 <addressOffset>0x230</addressOffset>
62296 <size>32</size>
62297 <access>read-write</access>
62298 <resetValue>0x0</resetValue>
62299 <fields>
62300 <field>
62301 <name>XFRSIZ</name>
62302 <description>Transfer size</description>
62303 <bitOffset>0</bitOffset>
62304 <bitWidth>19</bitWidth>
62305 </field>
62306 <field>
62307 <name>PKTCNT</name>
62308 <description>Packet count</description>
62309 <bitOffset>19</bitOffset>
62310 <bitWidth>10</bitWidth>
62311 </field>
62312 <field>
62313 <name>DPID</name>
62314 <description>Data PID</description>
62315 <bitOffset>29</bitOffset>
62316 <bitWidth>2</bitWidth>
62317 </field>
62318 </fields>
62319 </register>
62320 <register>
62321 <name>OTG_HS_HCTSIZ10</name>
62322 <displayName>OTG_HS_HCTSIZ10</displayName>
62323 <description>OTG_HS host channel-10 transfer size
62324 register</description>
62325 <addressOffset>0x250</addressOffset>
62326 <size>32</size>
62327 <access>read-write</access>
62328 <resetValue>0x0</resetValue>
62329 <fields>
62330 <field>
62331 <name>XFRSIZ</name>
62332 <description>Transfer size</description>
62333 <bitOffset>0</bitOffset>
62334 <bitWidth>19</bitWidth>
62335 </field>
62336 <field>
62337 <name>PKTCNT</name>
62338 <description>Packet count</description>
62339 <bitOffset>19</bitOffset>
62340 <bitWidth>10</bitWidth>
62341 </field>
62342 <field>
62343 <name>DPID</name>
62344 <description>Data PID</description>
62345 <bitOffset>29</bitOffset>
62346 <bitWidth>2</bitWidth>
62347 </field>
62348 </fields>
62349 </register>
62350 <register>
62351 <name>OTG_HS_HCTSIZ11</name>
62352 <displayName>OTG_HS_HCTSIZ11</displayName>
62353 <description>OTG_HS host channel-11 transfer size
62354 register</description>
62355 <addressOffset>0x270</addressOffset>
62356 <size>32</size>
62357 <access>read-write</access>
62358 <resetValue>0x0</resetValue>
62359 <fields>
62360 <field>
62361 <name>XFRSIZ</name>
62362 <description>Transfer size</description>
62363 <bitOffset>0</bitOffset>
62364 <bitWidth>19</bitWidth>
62365 </field>
62366 <field>
62367 <name>PKTCNT</name>
62368 <description>Packet count</description>
62369 <bitOffset>19</bitOffset>
62370 <bitWidth>10</bitWidth>
62371 </field>
62372 <field>
62373 <name>DPID</name>
62374 <description>Data PID</description>
62375 <bitOffset>29</bitOffset>
62376 <bitWidth>2</bitWidth>
62377 </field>
62378 </fields>
62379 </register>
62380 <register>
62381 <name>OTG_HS_HCDMA0</name>
62382 <displayName>OTG_HS_HCDMA0</displayName>
62383 <description>OTG_HS host channel-0 DMA address
62384 register</description>
62385 <addressOffset>0x114</addressOffset>
62386 <size>32</size>
62387 <access>read-write</access>
62388 <resetValue>0x0</resetValue>
62389 <fields>
62390 <field>
62391 <name>DMAADDR</name>
62392 <description>DMA address</description>
62393 <bitOffset>0</bitOffset>
62394 <bitWidth>32</bitWidth>
62395 </field>
62396 </fields>
62397 </register>
62398 <register>
62399 <name>OTG_HS_HCDMA1</name>
62400 <displayName>OTG_HS_HCDMA1</displayName>
62401 <description>OTG_HS host channel-1 DMA address
62402 register</description>
62403 <addressOffset>0x134</addressOffset>
62404 <size>32</size>
62405 <access>read-write</access>
62406 <resetValue>0x0</resetValue>
62407 <fields>
62408 <field>
62409 <name>DMAADDR</name>
62410 <description>DMA address</description>
62411 <bitOffset>0</bitOffset>
62412 <bitWidth>32</bitWidth>
62413 </field>
62414 </fields>
62415 </register>
62416 <register>
62417 <name>OTG_HS_HCDMA2</name>
62418 <displayName>OTG_HS_HCDMA2</displayName>
62419 <description>OTG_HS host channel-2 DMA address
62420 register</description>
62421 <addressOffset>0x154</addressOffset>
62422 <size>32</size>
62423 <access>read-write</access>
62424 <resetValue>0x0</resetValue>
62425 <fields>
62426 <field>
62427 <name>DMAADDR</name>
62428 <description>DMA address</description>
62429 <bitOffset>0</bitOffset>
62430 <bitWidth>32</bitWidth>
62431 </field>
62432 </fields>
62433 </register>
62434 <register>
62435 <name>OTG_HS_HCDMA3</name>
62436 <displayName>OTG_HS_HCDMA3</displayName>
62437 <description>OTG_HS host channel-3 DMA address
62438 register</description>
62439 <addressOffset>0x174</addressOffset>
62440 <size>32</size>
62441 <access>read-write</access>
62442 <resetValue>0x0</resetValue>
62443 <fields>
62444 <field>
62445 <name>DMAADDR</name>
62446 <description>DMA address</description>
62447 <bitOffset>0</bitOffset>
62448 <bitWidth>32</bitWidth>
62449 </field>
62450 </fields>
62451 </register>
62452 <register>
62453 <name>OTG_HS_HCDMA4</name>
62454 <displayName>OTG_HS_HCDMA4</displayName>
62455 <description>OTG_HS host channel-4 DMA address
62456 register</description>
62457 <addressOffset>0x194</addressOffset>
62458 <size>32</size>
62459 <access>read-write</access>
62460 <resetValue>0x0</resetValue>
62461 <fields>
62462 <field>
62463 <name>DMAADDR</name>
62464 <description>DMA address</description>
62465 <bitOffset>0</bitOffset>
62466 <bitWidth>32</bitWidth>
62467 </field>
62468 </fields>
62469 </register>
62470 <register>
62471 <name>OTG_HS_HCDMA5</name>
62472 <displayName>OTG_HS_HCDMA5</displayName>
62473 <description>OTG_HS host channel-5 DMA address
62474 register</description>
62475 <addressOffset>0x1B4</addressOffset>
62476 <size>32</size>
62477 <access>read-write</access>
62478 <resetValue>0x0</resetValue>
62479 <fields>
62480 <field>
62481 <name>DMAADDR</name>
62482 <description>DMA address</description>
62483 <bitOffset>0</bitOffset>
62484 <bitWidth>32</bitWidth>
62485 </field>
62486 </fields>
62487 </register>
62488 <register>
62489 <name>OTG_HS_HCDMA6</name>
62490 <displayName>OTG_HS_HCDMA6</displayName>
62491 <description>OTG_HS host channel-6 DMA address
62492 register</description>
62493 <addressOffset>0x1D4</addressOffset>
62494 <size>32</size>
62495 <access>read-write</access>
62496 <resetValue>0x0</resetValue>
62497 <fields>
62498 <field>
62499 <name>DMAADDR</name>
62500 <description>DMA address</description>
62501 <bitOffset>0</bitOffset>
62502 <bitWidth>32</bitWidth>
62503 </field>
62504 </fields>
62505 </register>
62506 <register>
62507 <name>OTG_HS_HCDMA7</name>
62508 <displayName>OTG_HS_HCDMA7</displayName>
62509 <description>OTG_HS host channel-7 DMA address
62510 register</description>
62511 <addressOffset>0x1F4</addressOffset>
62512 <size>32</size>
62513 <access>read-write</access>
62514 <resetValue>0x0</resetValue>
62515 <fields>
62516 <field>
62517 <name>DMAADDR</name>
62518 <description>DMA address</description>
62519 <bitOffset>0</bitOffset>
62520 <bitWidth>32</bitWidth>
62521 </field>
62522 </fields>
62523 </register>
62524 <register>
62525 <name>OTG_HS_HCDMA8</name>
62526 <displayName>OTG_HS_HCDMA8</displayName>
62527 <description>OTG_HS host channel-8 DMA address
62528 register</description>
62529 <addressOffset>0x214</addressOffset>
62530 <size>32</size>
62531 <access>read-write</access>
62532 <resetValue>0x0</resetValue>
62533 <fields>
62534 <field>
62535 <name>DMAADDR</name>
62536 <description>DMA address</description>
62537 <bitOffset>0</bitOffset>
62538 <bitWidth>32</bitWidth>
62539 </field>
62540 </fields>
62541 </register>
62542 <register>
62543 <name>OTG_HS_HCDMA9</name>
62544 <displayName>OTG_HS_HCDMA9</displayName>
62545 <description>OTG_HS host channel-9 DMA address
62546 register</description>
62547 <addressOffset>0x234</addressOffset>
62548 <size>32</size>
62549 <access>read-write</access>
62550 <resetValue>0x0</resetValue>
62551 <fields>
62552 <field>
62553 <name>DMAADDR</name>
62554 <description>DMA address</description>
62555 <bitOffset>0</bitOffset>
62556 <bitWidth>32</bitWidth>
62557 </field>
62558 </fields>
62559 </register>
62560 <register>
62561 <name>OTG_HS_HCDMA10</name>
62562 <displayName>OTG_HS_HCDMA10</displayName>
62563 <description>OTG_HS host channel-10 DMA address
62564 register</description>
62565 <addressOffset>0x254</addressOffset>
62566 <size>32</size>
62567 <access>read-write</access>
62568 <resetValue>0x0</resetValue>
62569 <fields>
62570 <field>
62571 <name>DMAADDR</name>
62572 <description>DMA address</description>
62573 <bitOffset>0</bitOffset>
62574 <bitWidth>32</bitWidth>
62575 </field>
62576 </fields>
62577 </register>
62578 <register>
62579 <name>OTG_HS_HCDMA11</name>
62580 <displayName>OTG_HS_HCDMA11</displayName>
62581 <description>OTG_HS host channel-11 DMA address
62582 register</description>
62583 <addressOffset>0x274</addressOffset>
62584 <size>32</size>
62585 <access>read-write</access>
62586 <resetValue>0x0</resetValue>
62587 <fields>
62588 <field>
62589 <name>DMAADDR</name>
62590 <description>DMA address</description>
62591 <bitOffset>0</bitOffset>
62592 <bitWidth>32</bitWidth>
62593 </field>
62594 </fields>
62595 </register>
62596 <register>
62597 <name>OTG_HS_HCCHAR12</name>
62598 <displayName>OTG_HS_HCCHAR12</displayName>
62599 <description>OTG_HS host channel-12 characteristics
62600 register</description>
62601 <addressOffset>0x278</addressOffset>
62602 <size>32</size>
62603 <access>read-write</access>
62604 <resetValue>0x0</resetValue>
62605 <fields>
62606 <field>
62607 <name>MPSIZ</name>
62608 <description>Maximum packet size</description>
62609 <bitOffset>0</bitOffset>
62610 <bitWidth>11</bitWidth>
62611 </field>
62612 <field>
62613 <name>EPNUM</name>
62614 <description>Endpoint number</description>
62615 <bitOffset>11</bitOffset>
62616 <bitWidth>4</bitWidth>
62617 </field>
62618 <field>
62619 <name>EPDIR</name>
62620 <description>Endpoint direction</description>
62621 <bitOffset>15</bitOffset>
62622 <bitWidth>1</bitWidth>
62623 </field>
62624 <field>
62625 <name>LSDEV</name>
62626 <description>Low-speed device</description>
62627 <bitOffset>17</bitOffset>
62628 <bitWidth>1</bitWidth>
62629 </field>
62630 <field>
62631 <name>EPTYP</name>
62632 <description>Endpoint type</description>
62633 <bitOffset>18</bitOffset>
62634 <bitWidth>2</bitWidth>
62635 </field>
62636 <field>
62637 <name>MC</name>
62638 <description>Multi Count (MC) / Error Count
62639 (EC)</description>
62640 <bitOffset>20</bitOffset>
62641 <bitWidth>2</bitWidth>
62642 </field>
62643 <field>
62644 <name>DAD</name>
62645 <description>Device address</description>
62646 <bitOffset>22</bitOffset>
62647 <bitWidth>7</bitWidth>
62648 </field>
62649 <field>
62650 <name>ODDFRM</name>
62651 <description>Odd frame</description>
62652 <bitOffset>29</bitOffset>
62653 <bitWidth>1</bitWidth>
62654 </field>
62655 <field>
62656 <name>CHDIS</name>
62657 <description>Channel disable</description>
62658 <bitOffset>30</bitOffset>
62659 <bitWidth>1</bitWidth>
62660 </field>
62661 <field>
62662 <name>CHENA</name>
62663 <description>Channel enable</description>
62664 <bitOffset>31</bitOffset>
62665 <bitWidth>1</bitWidth>
62666 </field>
62667 </fields>
62668 </register>
62669 <register>
62670 <name>OTG_HS_HCSPLT12</name>
62671 <displayName>OTG_HS_HCSPLT12</displayName>
62672 <description>OTG_HS host channel-12 split control
62673 register</description>
62674 <addressOffset>0x27C</addressOffset>
62675 <size>32</size>
62676 <access>read-write</access>
62677 <resetValue>0x0</resetValue>
62678 <fields>
62679 <field>
62680 <name>PRTADDR</name>
62681 <description>Port address</description>
62682 <bitOffset>0</bitOffset>
62683 <bitWidth>7</bitWidth>
62684 </field>
62685 <field>
62686 <name>HUBADDR</name>
62687 <description>Hub address</description>
62688 <bitOffset>7</bitOffset>
62689 <bitWidth>7</bitWidth>
62690 </field>
62691 <field>
62692 <name>XACTPOS</name>
62693 <description>XACTPOS</description>
62694 <bitOffset>14</bitOffset>
62695 <bitWidth>2</bitWidth>
62696 </field>
62697 <field>
62698 <name>COMPLSPLT</name>
62699 <description>Do complete split</description>
62700 <bitOffset>16</bitOffset>
62701 <bitWidth>1</bitWidth>
62702 </field>
62703 <field>
62704 <name>SPLITEN</name>
62705 <description>Split enable</description>
62706 <bitOffset>31</bitOffset>
62707 <bitWidth>1</bitWidth>
62708 </field>
62709 </fields>
62710 </register>
62711 <register>
62712 <name>OTG_HS_HCINT12</name>
62713 <displayName>OTG_HS_HCINT12</displayName>
62714 <description>OTG_HS host channel-12 interrupt
62715 register</description>
62716 <addressOffset>0x280</addressOffset>
62717 <size>32</size>
62718 <access>read-write</access>
62719 <resetValue>0x0</resetValue>
62720 <fields>
62721 <field>
62722 <name>XFRC</name>
62723 <description>Transfer completed</description>
62724 <bitOffset>0</bitOffset>
62725 <bitWidth>1</bitWidth>
62726 </field>
62727 <field>
62728 <name>CHH</name>
62729 <description>Channel halted</description>
62730 <bitOffset>1</bitOffset>
62731 <bitWidth>1</bitWidth>
62732 </field>
62733 <field>
62734 <name>AHBERR</name>
62735 <description>AHB error</description>
62736 <bitOffset>2</bitOffset>
62737 <bitWidth>1</bitWidth>
62738 </field>
62739 <field>
62740 <name>STALL</name>
62741 <description>STALL response received
62742 interrupt</description>
62743 <bitOffset>3</bitOffset>
62744 <bitWidth>1</bitWidth>
62745 </field>
62746 <field>
62747 <name>NAK</name>
62748 <description>NAK response received
62749 interrupt</description>
62750 <bitOffset>4</bitOffset>
62751 <bitWidth>1</bitWidth>
62752 </field>
62753 <field>
62754 <name>ACK</name>
62755 <description>ACK response received/transmitted
62756 interrupt</description>
62757 <bitOffset>5</bitOffset>
62758 <bitWidth>1</bitWidth>
62759 </field>
62760 <field>
62761 <name>NYET</name>
62762 <description>Response received
62763 interrupt</description>
62764 <bitOffset>6</bitOffset>
62765 <bitWidth>1</bitWidth>
62766 </field>
62767 <field>
62768 <name>TXERR</name>
62769 <description>Transaction error</description>
62770 <bitOffset>7</bitOffset>
62771 <bitWidth>1</bitWidth>
62772 </field>
62773 <field>
62774 <name>BBERR</name>
62775 <description>Babble error</description>
62776 <bitOffset>8</bitOffset>
62777 <bitWidth>1</bitWidth>
62778 </field>
62779 <field>
62780 <name>FRMOR</name>
62781 <description>Frame overrun</description>
62782 <bitOffset>9</bitOffset>
62783 <bitWidth>1</bitWidth>
62784 </field>
62785 <field>
62786 <name>DTERR</name>
62787 <description>Data toggle error</description>
62788 <bitOffset>10</bitOffset>
62789 <bitWidth>1</bitWidth>
62790 </field>
62791 </fields>
62792 </register>
62793 <register>
62794 <name>OTG_HS_HCINTMSK12</name>
62795 <displayName>OTG_HS_HCINTMSK12</displayName>
62796 <description>OTG_HS host channel-12 interrupt mask
62797 register</description>
62798 <addressOffset>0x284</addressOffset>
62799 <size>32</size>
62800 <access>read-write</access>
62801 <resetValue>0x0</resetValue>
62802 <fields>
62803 <field>
62804 <name>XFRCM</name>
62805 <description>Transfer completed mask</description>
62806 <bitOffset>0</bitOffset>
62807 <bitWidth>1</bitWidth>
62808 </field>
62809 <field>
62810 <name>CHHM</name>
62811 <description>Channel halted mask</description>
62812 <bitOffset>1</bitOffset>
62813 <bitWidth>1</bitWidth>
62814 </field>
62815 <field>
62816 <name>AHBERR</name>
62817 <description>AHB error</description>
62818 <bitOffset>2</bitOffset>
62819 <bitWidth>1</bitWidth>
62820 </field>
62821 <field>
62822 <name>STALLM</name>
62823 <description>STALL response received interrupt
62824 mask</description>
62825 <bitOffset>3</bitOffset>
62826 <bitWidth>1</bitWidth>
62827 </field>
62828 <field>
62829 <name>NAKM</name>
62830 <description>NAK response received interrupt
62831 mask</description>
62832 <bitOffset>4</bitOffset>
62833 <bitWidth>1</bitWidth>
62834 </field>
62835 <field>
62836 <name>ACKM</name>
62837 <description>ACK response received/transmitted
62838 interrupt mask</description>
62839 <bitOffset>5</bitOffset>
62840 <bitWidth>1</bitWidth>
62841 </field>
62842 <field>
62843 <name>NYET</name>
62844 <description>Response received
62845 interrupt</description>
62846 <bitOffset>6</bitOffset>
62847 <bitWidth>1</bitWidth>
62848 </field>
62849 <field>
62850 <name>TXERRM</name>
62851 <description>Transaction error</description>
62852 <bitOffset>7</bitOffset>
62853 <bitWidth>1</bitWidth>
62854 </field>
62855 <field>
62856 <name>BBERRM</name>
62857 <description>Babble error</description>
62858 <bitOffset>8</bitOffset>
62859 <bitWidth>1</bitWidth>
62860 </field>
62861 <field>
62862 <name>FRMORM</name>
62863 <description>Frame overrun mask</description>
62864 <bitOffset>9</bitOffset>
62865 <bitWidth>1</bitWidth>
62866 </field>
62867 <field>
62868 <name>DTERRM</name>
62869 <description>Data toggle error mask</description>
62870 <bitOffset>10</bitOffset>
62871 <bitWidth>1</bitWidth>
62872 </field>
62873 </fields>
62874 </register>
62875 <register>
62876 <name>OTG_HS_HCTSIZ12</name>
62877 <displayName>OTG_HS_HCTSIZ12</displayName>
62878 <description>OTG_HS host channel-12 transfer size
62879 register</description>
62880 <addressOffset>0x288</addressOffset>
62881 <size>32</size>
62882 <access>read-write</access>
62883 <resetValue>0x0</resetValue>
62884 <fields>
62885 <field>
62886 <name>XFRSIZ</name>
62887 <description>Transfer size</description>
62888 <bitOffset>0</bitOffset>
62889 <bitWidth>19</bitWidth>
62890 </field>
62891 <field>
62892 <name>PKTCNT</name>
62893 <description>Packet count</description>
62894 <bitOffset>19</bitOffset>
62895 <bitWidth>10</bitWidth>
62896 </field>
62897 <field>
62898 <name>DPID</name>
62899 <description>Data PID</description>
62900 <bitOffset>29</bitOffset>
62901 <bitWidth>2</bitWidth>
62902 </field>
62903 </fields>
62904 </register>
62905 <register>
62906 <name>OTG_HS_HCDMA12</name>
62907 <displayName>OTG_HS_HCDMA12</displayName>
62908 <description>OTG_HS host channel-12 DMA address
62909 register</description>
62910 <addressOffset>0x28C</addressOffset>
62911 <size>32</size>
62912 <access>read-write</access>
62913 <resetValue>0x0</resetValue>
62914 <fields>
62915 <field>
62916 <name>DMAADDR</name>
62917 <description>DMA address</description>
62918 <bitOffset>0</bitOffset>
62919 <bitWidth>32</bitWidth>
62920 </field>
62921 </fields>
62922 </register>
62923 <register>
62924 <name>OTG_HS_HCCHAR13</name>
62925 <displayName>OTG_HS_HCCHAR13</displayName>
62926 <description>OTG_HS host channel-13 characteristics
62927 register</description>
62928 <addressOffset>0x290</addressOffset>
62929 <size>32</size>
62930 <access>read-write</access>
62931 <resetValue>0x0</resetValue>
62932 <fields>
62933 <field>
62934 <name>MPSIZ</name>
62935 <description>Maximum packet size</description>
62936 <bitOffset>0</bitOffset>
62937 <bitWidth>11</bitWidth>
62938 </field>
62939 <field>
62940 <name>EPNUM</name>
62941 <description>Endpoint number</description>
62942 <bitOffset>11</bitOffset>
62943 <bitWidth>4</bitWidth>
62944 </field>
62945 <field>
62946 <name>EPDIR</name>
62947 <description>Endpoint direction</description>
62948 <bitOffset>15</bitOffset>
62949 <bitWidth>1</bitWidth>
62950 </field>
62951 <field>
62952 <name>LSDEV</name>
62953 <description>Low-speed device</description>
62954 <bitOffset>17</bitOffset>
62955 <bitWidth>1</bitWidth>
62956 </field>
62957 <field>
62958 <name>EPTYP</name>
62959 <description>Endpoint type</description>
62960 <bitOffset>18</bitOffset>
62961 <bitWidth>2</bitWidth>
62962 </field>
62963 <field>
62964 <name>MC</name>
62965 <description>Multi Count (MC) / Error Count
62966 (EC)</description>
62967 <bitOffset>20</bitOffset>
62968 <bitWidth>2</bitWidth>
62969 </field>
62970 <field>
62971 <name>DAD</name>
62972 <description>Device address</description>
62973 <bitOffset>22</bitOffset>
62974 <bitWidth>7</bitWidth>
62975 </field>
62976 <field>
62977 <name>ODDFRM</name>
62978 <description>Odd frame</description>
62979 <bitOffset>29</bitOffset>
62980 <bitWidth>1</bitWidth>
62981 </field>
62982 <field>
62983 <name>CHDIS</name>
62984 <description>Channel disable</description>
62985 <bitOffset>30</bitOffset>
62986 <bitWidth>1</bitWidth>
62987 </field>
62988 <field>
62989 <name>CHENA</name>
62990 <description>Channel enable</description>
62991 <bitOffset>31</bitOffset>
62992 <bitWidth>1</bitWidth>
62993 </field>
62994 </fields>
62995 </register>
62996 <register>
62997 <name>OTG_HS_HCSPLT13</name>
62998 <displayName>OTG_HS_HCSPLT13</displayName>
62999 <description>OTG_HS host channel-13 split control
63000 register</description>
63001 <addressOffset>0x294</addressOffset>
63002 <size>32</size>
63003 <access>read-write</access>
63004 <resetValue>0x0</resetValue>
63005 <fields>
63006 <field>
63007 <name>PRTADDR</name>
63008 <description>Port address</description>
63009 <bitOffset>0</bitOffset>
63010 <bitWidth>7</bitWidth>
63011 </field>
63012 <field>
63013 <name>HUBADDR</name>
63014 <description>Hub address</description>
63015 <bitOffset>7</bitOffset>
63016 <bitWidth>7</bitWidth>
63017 </field>
63018 <field>
63019 <name>XACTPOS</name>
63020 <description>XACTPOS</description>
63021 <bitOffset>14</bitOffset>
63022 <bitWidth>2</bitWidth>
63023 </field>
63024 <field>
63025 <name>COMPLSPLT</name>
63026 <description>Do complete split</description>
63027 <bitOffset>16</bitOffset>
63028 <bitWidth>1</bitWidth>
63029 </field>
63030 <field>
63031 <name>SPLITEN</name>
63032 <description>Split enable</description>
63033 <bitOffset>31</bitOffset>
63034 <bitWidth>1</bitWidth>
63035 </field>
63036 </fields>
63037 </register>
63038 <register>
63039 <name>OTG_HS_HCINT13</name>
63040 <displayName>OTG_HS_HCINT13</displayName>
63041 <description>OTG_HS host channel-13 interrupt
63042 register</description>
63043 <addressOffset>0x298</addressOffset>
63044 <size>32</size>
63045 <access>read-write</access>
63046 <resetValue>0x0</resetValue>
63047 <fields>
63048 <field>
63049 <name>XFRC</name>
63050 <description>Transfer completed</description>
63051 <bitOffset>0</bitOffset>
63052 <bitWidth>1</bitWidth>
63053 </field>
63054 <field>
63055 <name>CHH</name>
63056 <description>Channel halted</description>
63057 <bitOffset>1</bitOffset>
63058 <bitWidth>1</bitWidth>
63059 </field>
63060 <field>
63061 <name>AHBERR</name>
63062 <description>AHB error</description>
63063 <bitOffset>2</bitOffset>
63064 <bitWidth>1</bitWidth>
63065 </field>
63066 <field>
63067 <name>STALL</name>
63068 <description>STALL response received
63069 interrupt</description>
63070 <bitOffset>3</bitOffset>
63071 <bitWidth>1</bitWidth>
63072 </field>
63073 <field>
63074 <name>NAK</name>
63075 <description>NAK response received
63076 interrupt</description>
63077 <bitOffset>4</bitOffset>
63078 <bitWidth>1</bitWidth>
63079 </field>
63080 <field>
63081 <name>ACK</name>
63082 <description>ACK response received/transmitted
63083 interrupt</description>
63084 <bitOffset>5</bitOffset>
63085 <bitWidth>1</bitWidth>
63086 </field>
63087 <field>
63088 <name>NYET</name>
63089 <description>Response received
63090 interrupt</description>
63091 <bitOffset>6</bitOffset>
63092 <bitWidth>1</bitWidth>
63093 </field>
63094 <field>
63095 <name>TXERR</name>
63096 <description>Transaction error</description>
63097 <bitOffset>7</bitOffset>
63098 <bitWidth>1</bitWidth>
63099 </field>
63100 <field>
63101 <name>BBERR</name>
63102 <description>Babble error</description>
63103 <bitOffset>8</bitOffset>
63104 <bitWidth>1</bitWidth>
63105 </field>
63106 <field>
63107 <name>FRMOR</name>
63108 <description>Frame overrun</description>
63109 <bitOffset>9</bitOffset>
63110 <bitWidth>1</bitWidth>
63111 </field>
63112 <field>
63113 <name>DTERR</name>
63114 <description>Data toggle error</description>
63115 <bitOffset>10</bitOffset>
63116 <bitWidth>1</bitWidth>
63117 </field>
63118 </fields>
63119 </register>
63120 <register>
63121 <name>OTG_HS_HCINTMSK13</name>
63122 <displayName>OTG_HS_HCINTMSK13</displayName>
63123 <description>OTG_HS host channel-13 interrupt mask
63124 register</description>
63125 <addressOffset>0x29C</addressOffset>
63126 <size>32</size>
63127 <access>read-write</access>
63128 <resetValue>0x0</resetValue>
63129 <fields>
63130 <field>
63131 <name>XFRCM</name>
63132 <description>Transfer completed mask</description>
63133 <bitOffset>0</bitOffset>
63134 <bitWidth>1</bitWidth>
63135 </field>
63136 <field>
63137 <name>CHHM</name>
63138 <description>Channel halted mask</description>
63139 <bitOffset>1</bitOffset>
63140 <bitWidth>1</bitWidth>
63141 </field>
63142 <field>
63143 <name>AHBERR</name>
63144 <description>AHB error</description>
63145 <bitOffset>2</bitOffset>
63146 <bitWidth>1</bitWidth>
63147 </field>
63148 <field>
63149 <name>STALLM</name>
63150 <description>STALLM response received interrupt
63151 mask</description>
63152 <bitOffset>3</bitOffset>
63153 <bitWidth>1</bitWidth>
63154 </field>
63155 <field>
63156 <name>NAKM</name>
63157 <description>NAK response received interrupt
63158 mask</description>
63159 <bitOffset>4</bitOffset>
63160 <bitWidth>1</bitWidth>
63161 </field>
63162 <field>
63163 <name>ACKM</name>
63164 <description>ACK response received/transmitted
63165 interrupt mask</description>
63166 <bitOffset>5</bitOffset>
63167 <bitWidth>1</bitWidth>
63168 </field>
63169 <field>
63170 <name>NYET</name>
63171 <description>Response received
63172 interrupt</description>
63173 <bitOffset>6</bitOffset>
63174 <bitWidth>1</bitWidth>
63175 </field>
63176 <field>
63177 <name>TXERRM</name>
63178 <description>Transaction error</description>
63179 <bitOffset>7</bitOffset>
63180 <bitWidth>1</bitWidth>
63181 </field>
63182 <field>
63183 <name>BBERRM</name>
63184 <description>Babble error</description>
63185 <bitOffset>8</bitOffset>
63186 <bitWidth>1</bitWidth>
63187 </field>
63188 <field>
63189 <name>FRMORM</name>
63190 <description>Frame overrun mask</description>
63191 <bitOffset>9</bitOffset>
63192 <bitWidth>1</bitWidth>
63193 </field>
63194 <field>
63195 <name>DTERRM</name>
63196 <description>Data toggle error mask</description>
63197 <bitOffset>10</bitOffset>
63198 <bitWidth>1</bitWidth>
63199 </field>
63200 </fields>
63201 </register>
63202 <register>
63203 <name>OTG_HS_HCTSIZ13</name>
63204 <displayName>OTG_HS_HCTSIZ13</displayName>
63205 <description>OTG_HS host channel-13 transfer size
63206 register</description>
63207 <addressOffset>0x2A0</addressOffset>
63208 <size>32</size>
63209 <access>read-write</access>
63210 <resetValue>0x0</resetValue>
63211 <fields>
63212 <field>
63213 <name>XFRSIZ</name>
63214 <description>Transfer size</description>
63215 <bitOffset>0</bitOffset>
63216 <bitWidth>19</bitWidth>
63217 </field>
63218 <field>
63219 <name>PKTCNT</name>
63220 <description>Packet count</description>
63221 <bitOffset>19</bitOffset>
63222 <bitWidth>10</bitWidth>
63223 </field>
63224 <field>
63225 <name>DPID</name>
63226 <description>Data PID</description>
63227 <bitOffset>29</bitOffset>
63228 <bitWidth>2</bitWidth>
63229 </field>
63230 </fields>
63231 </register>
63232 <register>
63233 <name>OTG_HS_HCDMA13</name>
63234 <displayName>OTG_HS_HCDMA13</displayName>
63235 <description>OTG_HS host channel-13 DMA address
63236 register</description>
63237 <addressOffset>0x2A4</addressOffset>
63238 <size>32</size>
63239 <access>read-write</access>
63240 <resetValue>0x0</resetValue>
63241 <fields>
63242 <field>
63243 <name>DMAADDR</name>
63244 <description>DMA address</description>
63245 <bitOffset>0</bitOffset>
63246 <bitWidth>32</bitWidth>
63247 </field>
63248 </fields>
63249 </register>
63250 <register>
63251 <name>OTG_HS_HCCHAR14</name>
63252 <displayName>OTG_HS_HCCHAR14</displayName>
63253 <description>OTG_HS host channel-14 characteristics
63254 register</description>
63255 <addressOffset>0x2A8</addressOffset>
63256 <size>32</size>
63257 <access>read-write</access>
63258 <resetValue>0x0</resetValue>
63259 <fields>
63260 <field>
63261 <name>MPSIZ</name>
63262 <description>Maximum packet size</description>
63263 <bitOffset>0</bitOffset>
63264 <bitWidth>11</bitWidth>
63265 </field>
63266 <field>
63267 <name>EPNUM</name>
63268 <description>Endpoint number</description>
63269 <bitOffset>11</bitOffset>
63270 <bitWidth>4</bitWidth>
63271 </field>
63272 <field>
63273 <name>EPDIR</name>
63274 <description>Endpoint direction</description>
63275 <bitOffset>15</bitOffset>
63276 <bitWidth>1</bitWidth>
63277 </field>
63278 <field>
63279 <name>LSDEV</name>
63280 <description>Low-speed device</description>
63281 <bitOffset>17</bitOffset>
63282 <bitWidth>1</bitWidth>
63283 </field>
63284 <field>
63285 <name>EPTYP</name>
63286 <description>Endpoint type</description>
63287 <bitOffset>18</bitOffset>
63288 <bitWidth>2</bitWidth>
63289 </field>
63290 <field>
63291 <name>MC</name>
63292 <description>Multi Count (MC) / Error Count
63293 (EC)</description>
63294 <bitOffset>20</bitOffset>
63295 <bitWidth>2</bitWidth>
63296 </field>
63297 <field>
63298 <name>DAD</name>
63299 <description>Device address</description>
63300 <bitOffset>22</bitOffset>
63301 <bitWidth>7</bitWidth>
63302 </field>
63303 <field>
63304 <name>ODDFRM</name>
63305 <description>Odd frame</description>
63306 <bitOffset>29</bitOffset>
63307 <bitWidth>1</bitWidth>
63308 </field>
63309 <field>
63310 <name>CHDIS</name>
63311 <description>Channel disable</description>
63312 <bitOffset>30</bitOffset>
63313 <bitWidth>1</bitWidth>
63314 </field>
63315 <field>
63316 <name>CHENA</name>
63317 <description>Channel enable</description>
63318 <bitOffset>31</bitOffset>
63319 <bitWidth>1</bitWidth>
63320 </field>
63321 </fields>
63322 </register>
63323 <register>
63324 <name>OTG_HS_HCSPLT14</name>
63325 <displayName>OTG_HS_HCSPLT14</displayName>
63326 <description>OTG_HS host channel-14 split control
63327 register</description>
63328 <addressOffset>0x2AC</addressOffset>
63329 <size>32</size>
63330 <access>read-write</access>
63331 <resetValue>0x0</resetValue>
63332 <fields>
63333 <field>
63334 <name>PRTADDR</name>
63335 <description>Port address</description>
63336 <bitOffset>0</bitOffset>
63337 <bitWidth>7</bitWidth>
63338 </field>
63339 <field>
63340 <name>HUBADDR</name>
63341 <description>Hub address</description>
63342 <bitOffset>7</bitOffset>
63343 <bitWidth>7</bitWidth>
63344 </field>
63345 <field>
63346 <name>XACTPOS</name>
63347 <description>XACTPOS</description>
63348 <bitOffset>14</bitOffset>
63349 <bitWidth>2</bitWidth>
63350 </field>
63351 <field>
63352 <name>COMPLSPLT</name>
63353 <description>Do complete split</description>
63354 <bitOffset>16</bitOffset>
63355 <bitWidth>1</bitWidth>
63356 </field>
63357 <field>
63358 <name>SPLITEN</name>
63359 <description>Split enable</description>
63360 <bitOffset>31</bitOffset>
63361 <bitWidth>1</bitWidth>
63362 </field>
63363 </fields>
63364 </register>
63365 <register>
63366 <name>OTG_HS_HCINT14</name>
63367 <displayName>OTG_HS_HCINT14</displayName>
63368 <description>OTG_HS host channel-14 interrupt
63369 register</description>
63370 <addressOffset>0x2B0</addressOffset>
63371 <size>32</size>
63372 <access>read-write</access>
63373 <resetValue>0x0</resetValue>
63374 <fields>
63375 <field>
63376 <name>XFRC</name>
63377 <description>Transfer completed</description>
63378 <bitOffset>0</bitOffset>
63379 <bitWidth>1</bitWidth>
63380 </field>
63381 <field>
63382 <name>CHH</name>
63383 <description>Channel halted</description>
63384 <bitOffset>1</bitOffset>
63385 <bitWidth>1</bitWidth>
63386 </field>
63387 <field>
63388 <name>AHBERR</name>
63389 <description>AHB error</description>
63390 <bitOffset>2</bitOffset>
63391 <bitWidth>1</bitWidth>
63392 </field>
63393 <field>
63394 <name>STALL</name>
63395 <description>STALL response received
63396 interrupt</description>
63397 <bitOffset>3</bitOffset>
63398 <bitWidth>1</bitWidth>
63399 </field>
63400 <field>
63401 <name>NAK</name>
63402 <description>NAK response received
63403 interrupt</description>
63404 <bitOffset>4</bitOffset>
63405 <bitWidth>1</bitWidth>
63406 </field>
63407 <field>
63408 <name>ACK</name>
63409 <description>ACK response received/transmitted
63410 interrupt</description>
63411 <bitOffset>5</bitOffset>
63412 <bitWidth>1</bitWidth>
63413 </field>
63414 <field>
63415 <name>NYET</name>
63416 <description>Response received
63417 interrupt</description>
63418 <bitOffset>6</bitOffset>
63419 <bitWidth>1</bitWidth>
63420 </field>
63421 <field>
63422 <name>TXERR</name>
63423 <description>Transaction error</description>
63424 <bitOffset>7</bitOffset>
63425 <bitWidth>1</bitWidth>
63426 </field>
63427 <field>
63428 <name>BBERR</name>
63429 <description>Babble error</description>
63430 <bitOffset>8</bitOffset>
63431 <bitWidth>1</bitWidth>
63432 </field>
63433 <field>
63434 <name>FRMOR</name>
63435 <description>Frame overrun</description>
63436 <bitOffset>9</bitOffset>
63437 <bitWidth>1</bitWidth>
63438 </field>
63439 <field>
63440 <name>DTERR</name>
63441 <description>Data toggle error</description>
63442 <bitOffset>10</bitOffset>
63443 <bitWidth>1</bitWidth>
63444 </field>
63445 </fields>
63446 </register>
63447 <register>
63448 <name>OTG_HS_HCINTMSK14</name>
63449 <displayName>OTG_HS_HCINTMSK14</displayName>
63450 <description>OTG_HS host channel-14 interrupt mask
63451 register</description>
63452 <addressOffset>0x2B4</addressOffset>
63453 <size>32</size>
63454 <access>read-write</access>
63455 <resetValue>0x0</resetValue>
63456 <fields>
63457 <field>
63458 <name>XFRCM</name>
63459 <description>Transfer completed mask</description>
63460 <bitOffset>0</bitOffset>
63461 <bitWidth>1</bitWidth>
63462 </field>
63463 <field>
63464 <name>CHHM</name>
63465 <description>Channel halted mask</description>
63466 <bitOffset>1</bitOffset>
63467 <bitWidth>1</bitWidth>
63468 </field>
63469 <field>
63470 <name>AHBERR</name>
63471 <description>AHB error</description>
63472 <bitOffset>2</bitOffset>
63473 <bitWidth>1</bitWidth>
63474 </field>
63475 <field>
63476 <name>STALLM</name>
63477 <description>STALL response received interrupt
63478 mask</description>
63479 <bitOffset>3</bitOffset>
63480 <bitWidth>1</bitWidth>
63481 </field>
63482 <field>
63483 <name>NAKM</name>
63484 <description>NAKM response received interrupt
63485 mask</description>
63486 <bitOffset>4</bitOffset>
63487 <bitWidth>1</bitWidth>
63488 </field>
63489 <field>
63490 <name>ACKM</name>
63491 <description>ACKM response received/transmitted
63492 interrupt mask</description>
63493 <bitOffset>5</bitOffset>
63494 <bitWidth>1</bitWidth>
63495 </field>
63496 <field>
63497 <name>NYET</name>
63498 <description>Response received
63499 interrupt</description>
63500 <bitOffset>6</bitOffset>
63501 <bitWidth>1</bitWidth>
63502 </field>
63503 <field>
63504 <name>TXERRM</name>
63505 <description>Transaction error</description>
63506 <bitOffset>7</bitOffset>
63507 <bitWidth>1</bitWidth>
63508 </field>
63509 <field>
63510 <name>BBERRM</name>
63511 <description>Babble error</description>
63512 <bitOffset>8</bitOffset>
63513 <bitWidth>1</bitWidth>
63514 </field>
63515 <field>
63516 <name>FRMORM</name>
63517 <description>Frame overrun mask</description>
63518 <bitOffset>9</bitOffset>
63519 <bitWidth>1</bitWidth>
63520 </field>
63521 <field>
63522 <name>DTERRM</name>
63523 <description>Data toggle error mask</description>
63524 <bitOffset>10</bitOffset>
63525 <bitWidth>1</bitWidth>
63526 </field>
63527 </fields>
63528 </register>
63529 <register>
63530 <name>OTG_HS_HCTSIZ14</name>
63531 <displayName>OTG_HS_HCTSIZ14</displayName>
63532 <description>OTG_HS host channel-14 transfer size
63533 register</description>
63534 <addressOffset>0x2B8</addressOffset>
63535 <size>32</size>
63536 <access>read-write</access>
63537 <resetValue>0x0</resetValue>
63538 <fields>
63539 <field>
63540 <name>XFRSIZ</name>
63541 <description>Transfer size</description>
63542 <bitOffset>0</bitOffset>
63543 <bitWidth>19</bitWidth>
63544 </field>
63545 <field>
63546 <name>PKTCNT</name>
63547 <description>Packet count</description>
63548 <bitOffset>19</bitOffset>
63549 <bitWidth>10</bitWidth>
63550 </field>
63551 <field>
63552 <name>DPID</name>
63553 <description>Data PID</description>
63554 <bitOffset>29</bitOffset>
63555 <bitWidth>2</bitWidth>
63556 </field>
63557 </fields>
63558 </register>
63559 <register>
63560 <name>OTG_HS_HCDMA14</name>
63561 <displayName>OTG_HS_HCDMA14</displayName>
63562 <description>OTG_HS host channel-14 DMA address
63563 register</description>
63564 <addressOffset>0x2BC</addressOffset>
63565 <size>32</size>
63566 <access>read-write</access>
63567 <resetValue>0x0</resetValue>
63568 <fields>
63569 <field>
63570 <name>DMAADDR</name>
63571 <description>DMA address</description>
63572 <bitOffset>0</bitOffset>
63573 <bitWidth>32</bitWidth>
63574 </field>
63575 </fields>
63576 </register>
63577 <register>
63578 <name>OTG_HS_HCCHAR15</name>
63579 <displayName>OTG_HS_HCCHAR15</displayName>
63580 <description>OTG_HS host channel-15 characteristics
63581 register</description>
63582 <addressOffset>0x2C0</addressOffset>
63583 <size>32</size>
63584 <access>read-write</access>
63585 <resetValue>0x0</resetValue>
63586 <fields>
63587 <field>
63588 <name>MPSIZ</name>
63589 <description>Maximum packet size</description>
63590 <bitOffset>0</bitOffset>
63591 <bitWidth>11</bitWidth>
63592 </field>
63593 <field>
63594 <name>EPNUM</name>
63595 <description>Endpoint number</description>
63596 <bitOffset>11</bitOffset>
63597 <bitWidth>4</bitWidth>
63598 </field>
63599 <field>
63600 <name>EPDIR</name>
63601 <description>Endpoint direction</description>
63602 <bitOffset>15</bitOffset>
63603 <bitWidth>1</bitWidth>
63604 </field>
63605 <field>
63606 <name>LSDEV</name>
63607 <description>Low-speed device</description>
63608 <bitOffset>17</bitOffset>
63609 <bitWidth>1</bitWidth>
63610 </field>
63611 <field>
63612 <name>EPTYP</name>
63613 <description>Endpoint type</description>
63614 <bitOffset>18</bitOffset>
63615 <bitWidth>2</bitWidth>
63616 </field>
63617 <field>
63618 <name>MC</name>
63619 <description>Multi Count (MC) / Error Count
63620 (EC)</description>
63621 <bitOffset>20</bitOffset>
63622 <bitWidth>2</bitWidth>
63623 </field>
63624 <field>
63625 <name>DAD</name>
63626 <description>Device address</description>
63627 <bitOffset>22</bitOffset>
63628 <bitWidth>7</bitWidth>
63629 </field>
63630 <field>
63631 <name>ODDFRM</name>
63632 <description>Odd frame</description>
63633 <bitOffset>29</bitOffset>
63634 <bitWidth>1</bitWidth>
63635 </field>
63636 <field>
63637 <name>CHDIS</name>
63638 <description>Channel disable</description>
63639 <bitOffset>30</bitOffset>
63640 <bitWidth>1</bitWidth>
63641 </field>
63642 <field>
63643 <name>CHENA</name>
63644 <description>Channel enable</description>
63645 <bitOffset>31</bitOffset>
63646 <bitWidth>1</bitWidth>
63647 </field>
63648 </fields>
63649 </register>
63650 <register>
63651 <name>OTG_HS_HCSPLT15</name>
63652 <displayName>OTG_HS_HCSPLT15</displayName>
63653 <description>OTG_HS host channel-15 split control
63654 register</description>
63655 <addressOffset>0x2C4</addressOffset>
63656 <size>32</size>
63657 <access>read-write</access>
63658 <resetValue>0x0</resetValue>
63659 <fields>
63660 <field>
63661 <name>PRTADDR</name>
63662 <description>Port address</description>
63663 <bitOffset>0</bitOffset>
63664 <bitWidth>7</bitWidth>
63665 </field>
63666 <field>
63667 <name>HUBADDR</name>
63668 <description>Hub address</description>
63669 <bitOffset>7</bitOffset>
63670 <bitWidth>7</bitWidth>
63671 </field>
63672 <field>
63673 <name>XACTPOS</name>
63674 <description>XACTPOS</description>
63675 <bitOffset>14</bitOffset>
63676 <bitWidth>2</bitWidth>
63677 </field>
63678 <field>
63679 <name>COMPLSPLT</name>
63680 <description>Do complete split</description>
63681 <bitOffset>16</bitOffset>
63682 <bitWidth>1</bitWidth>
63683 </field>
63684 <field>
63685 <name>SPLITEN</name>
63686 <description>Split enable</description>
63687 <bitOffset>31</bitOffset>
63688 <bitWidth>1</bitWidth>
63689 </field>
63690 </fields>
63691 </register>
63692 <register>
63693 <name>OTG_HS_HCINT15</name>
63694 <displayName>OTG_HS_HCINT15</displayName>
63695 <description>OTG_HS host channel-15 interrupt
63696 register</description>
63697 <addressOffset>0x2C8</addressOffset>
63698 <size>32</size>
63699 <access>read-write</access>
63700 <resetValue>0x0</resetValue>
63701 <fields>
63702 <field>
63703 <name>XFRC</name>
63704 <description>Transfer completed</description>
63705 <bitOffset>0</bitOffset>
63706 <bitWidth>1</bitWidth>
63707 </field>
63708 <field>
63709 <name>CHH</name>
63710 <description>Channel halted</description>
63711 <bitOffset>1</bitOffset>
63712 <bitWidth>1</bitWidth>
63713 </field>
63714 <field>
63715 <name>AHBERR</name>
63716 <description>AHB error</description>
63717 <bitOffset>2</bitOffset>
63718 <bitWidth>1</bitWidth>
63719 </field>
63720 <field>
63721 <name>STALL</name>
63722 <description>STALL response received
63723 interrupt</description>
63724 <bitOffset>3</bitOffset>
63725 <bitWidth>1</bitWidth>
63726 </field>
63727 <field>
63728 <name>NAK</name>
63729 <description>NAK response received
63730 interrupt</description>
63731 <bitOffset>4</bitOffset>
63732 <bitWidth>1</bitWidth>
63733 </field>
63734 <field>
63735 <name>ACK</name>
63736 <description>ACK response received/transmitted
63737 interrupt</description>
63738 <bitOffset>5</bitOffset>
63739 <bitWidth>1</bitWidth>
63740 </field>
63741 <field>
63742 <name>NYET</name>
63743 <description>Response received
63744 interrupt</description>
63745 <bitOffset>6</bitOffset>
63746 <bitWidth>1</bitWidth>
63747 </field>
63748 <field>
63749 <name>TXERR</name>
63750 <description>Transaction error</description>
63751 <bitOffset>7</bitOffset>
63752 <bitWidth>1</bitWidth>
63753 </field>
63754 <field>
63755 <name>BBERR</name>
63756 <description>Babble error</description>
63757 <bitOffset>8</bitOffset>
63758 <bitWidth>1</bitWidth>
63759 </field>
63760 <field>
63761 <name>FRMOR</name>
63762 <description>Frame overrun</description>
63763 <bitOffset>9</bitOffset>
63764 <bitWidth>1</bitWidth>
63765 </field>
63766 <field>
63767 <name>DTERR</name>
63768 <description>Data toggle error</description>
63769 <bitOffset>10</bitOffset>
63770 <bitWidth>1</bitWidth>
63771 </field>
63772 </fields>
63773 </register>
63774 <register>
63775 <name>OTG_HS_HCINTMSK15</name>
63776 <displayName>OTG_HS_HCINTMSK15</displayName>
63777 <description>OTG_HS host channel-15 interrupt mask
63778 register</description>
63779 <addressOffset>0x2CC</addressOffset>
63780 <size>32</size>
63781 <access>read-write</access>
63782 <resetValue>0x0</resetValue>
63783 <fields>
63784 <field>
63785 <name>XFRCM</name>
63786 <description>Transfer completed mask</description>
63787 <bitOffset>0</bitOffset>
63788 <bitWidth>1</bitWidth>
63789 </field>
63790 <field>
63791 <name>CHHM</name>
63792 <description>Channel halted mask</description>
63793 <bitOffset>1</bitOffset>
63794 <bitWidth>1</bitWidth>
63795 </field>
63796 <field>
63797 <name>AHBERR</name>
63798 <description>AHB error</description>
63799 <bitOffset>2</bitOffset>
63800 <bitWidth>1</bitWidth>
63801 </field>
63802 <field>
63803 <name>STALL</name>
63804 <description>STALL response received interrupt
63805 mask</description>
63806 <bitOffset>3</bitOffset>
63807 <bitWidth>1</bitWidth>
63808 </field>
63809 <field>
63810 <name>NAKM</name>
63811 <description>NAK response received interrupt
63812 mask</description>
63813 <bitOffset>4</bitOffset>
63814 <bitWidth>1</bitWidth>
63815 </field>
63816 <field>
63817 <name>ACKM</name>
63818 <description>ACK response received/transmitted
63819 interrupt mask</description>
63820 <bitOffset>5</bitOffset>
63821 <bitWidth>1</bitWidth>
63822 </field>
63823 <field>
63824 <name>NYET</name>
63825 <description>Response received
63826 interrupt</description>
63827 <bitOffset>6</bitOffset>
63828 <bitWidth>1</bitWidth>
63829 </field>
63830 <field>
63831 <name>TXERRM</name>
63832 <description>Transaction error</description>
63833 <bitOffset>7</bitOffset>
63834 <bitWidth>1</bitWidth>
63835 </field>
63836 <field>
63837 <name>BBERRM</name>
63838 <description>Babble error</description>
63839 <bitOffset>8</bitOffset>
63840 <bitWidth>1</bitWidth>
63841 </field>
63842 <field>
63843 <name>FRMORM</name>
63844 <description>Frame overrun mask</description>
63845 <bitOffset>9</bitOffset>
63846 <bitWidth>1</bitWidth>
63847 </field>
63848 <field>
63849 <name>DTERRM</name>
63850 <description>Data toggle error mask</description>
63851 <bitOffset>10</bitOffset>
63852 <bitWidth>1</bitWidth>
63853 </field>
63854 </fields>
63855 </register>
63856 <register>
63857 <name>OTG_HS_HCTSIZ15</name>
63858 <displayName>OTG_HS_HCTSIZ15</displayName>
63859 <description>OTG_HS host channel-15 transfer size
63860 register</description>
63861 <addressOffset>0x2D0</addressOffset>
63862 <size>32</size>
63863 <access>read-write</access>
63864 <resetValue>0x0</resetValue>
63865 <fields>
63866 <field>
63867 <name>XFRSIZ</name>
63868 <description>Transfer size</description>
63869 <bitOffset>0</bitOffset>
63870 <bitWidth>19</bitWidth>
63871 </field>
63872 <field>
63873 <name>PKTCNT</name>
63874 <description>Packet count</description>
63875 <bitOffset>19</bitOffset>
63876 <bitWidth>10</bitWidth>
63877 </field>
63878 <field>
63879 <name>DPID</name>
63880 <description>Data PID</description>
63881 <bitOffset>29</bitOffset>
63882 <bitWidth>2</bitWidth>
63883 </field>
63884 </fields>
63885 </register>
63886 <register>
63887 <name>OTG_HS_HCDMA15</name>
63888 <displayName>OTG_HS_HCDMA15</displayName>
63889 <description>OTG_HS host channel-15 DMA address
63890 register</description>
63891 <addressOffset>0x2D4</addressOffset>
63892 <size>32</size>
63893 <access>read-write</access>
63894 <resetValue>0x0</resetValue>
63895 <fields>
63896 <field>
63897 <name>DMAADDR</name>
63898 <description>DMA address</description>
63899 <bitOffset>0</bitOffset>
63900 <bitWidth>32</bitWidth>
63901 </field>
63902 </fields>
63903 </register>
63904 </registers>
63905 </peripheral>
63906 <peripheral>
63907 <name>OTG_HS_DEVICE</name>
63908 <description>USB on the go high speed</description>
63909 <groupName>USB_OTG_HS</groupName>
63910 <baseAddress>0x40040800</baseAddress>
63911 <addressBlock>
63912 <offset>0x0</offset>
63913 <size>0x400</size>
63914 <usage>registers</usage>
63915 </addressBlock>
63916 <registers>
63917 <register>
63918 <name>OTG_HS_DCFG</name>
63919 <displayName>OTG_HS_DCFG</displayName>
63920 <description>OTG_HS device configuration
63921 register</description>
63922 <addressOffset>0x0</addressOffset>
63923 <size>32</size>
63924 <access>read-write</access>
63925 <resetValue>0x02200000</resetValue>
63926 <fields>
63927 <field>
63928 <name>DSPD</name>
63929 <description>Device speed</description>
63930 <bitOffset>0</bitOffset>
63931 <bitWidth>2</bitWidth>
63932 </field>
63933 <field>
63934 <name>NZLSOHSK</name>
63935 <description>Nonzero-length status OUT
63936 handshake</description>
63937 <bitOffset>2</bitOffset>
63938 <bitWidth>1</bitWidth>
63939 </field>
63940 <field>
63941 <name>DAD</name>
63942 <description>Device address</description>
63943 <bitOffset>4</bitOffset>
63944 <bitWidth>7</bitWidth>
63945 </field>
63946 <field>
63947 <name>PFIVL</name>
63948 <description>Periodic (micro)frame
63949 interval</description>
63950 <bitOffset>11</bitOffset>
63951 <bitWidth>2</bitWidth>
63952 </field>
63953 <field>
63954 <name>PERSCHIVL</name>
63955 <description>Periodic scheduling
63956 interval</description>
63957 <bitOffset>24</bitOffset>
63958 <bitWidth>2</bitWidth>
63959 </field>
63960 </fields>
63961 </register>
63962 <register>
63963 <name>OTG_HS_DCTL</name>
63964 <displayName>OTG_HS_DCTL</displayName>
63965 <description>OTG_HS device control register</description>
63966 <addressOffset>0x4</addressOffset>
63967 <size>32</size>
63968 <resetValue>0x0</resetValue>
63969 <fields>
63970 <field>
63971 <name>RWUSIG</name>
63972 <description>Remote wakeup signaling</description>
63973 <bitOffset>0</bitOffset>
63974 <bitWidth>1</bitWidth>
63975 <access>read-write</access>
63976 </field>
63977 <field>
63978 <name>SDIS</name>
63979 <description>Soft disconnect</description>
63980 <bitOffset>1</bitOffset>
63981 <bitWidth>1</bitWidth>
63982 <access>read-write</access>
63983 </field>
63984 <field>
63985 <name>GINSTS</name>
63986 <description>Global IN NAK status</description>
63987 <bitOffset>2</bitOffset>
63988 <bitWidth>1</bitWidth>
63989 <access>read-only</access>
63990 </field>
63991 <field>
63992 <name>GONSTS</name>
63993 <description>Global OUT NAK status</description>
63994 <bitOffset>3</bitOffset>
63995 <bitWidth>1</bitWidth>
63996 <access>read-only</access>
63997 </field>
63998 <field>
63999 <name>TCTL</name>
64000 <description>Test control</description>
64001 <bitOffset>4</bitOffset>
64002 <bitWidth>3</bitWidth>
64003 <access>read-write</access>
64004 </field>
64005 <field>
64006 <name>SGINAK</name>
64007 <description>Set global IN NAK</description>
64008 <bitOffset>7</bitOffset>
64009 <bitWidth>1</bitWidth>
64010 <access>write-only</access>
64011 </field>
64012 <field>
64013 <name>CGINAK</name>
64014 <description>Clear global IN NAK</description>
64015 <bitOffset>8</bitOffset>
64016 <bitWidth>1</bitWidth>
64017 <access>write-only</access>
64018 </field>
64019 <field>
64020 <name>SGONAK</name>
64021 <description>Set global OUT NAK</description>
64022 <bitOffset>9</bitOffset>
64023 <bitWidth>1</bitWidth>
64024 <access>write-only</access>
64025 </field>
64026 <field>
64027 <name>CGONAK</name>
64028 <description>Clear global OUT NAK</description>
64029 <bitOffset>10</bitOffset>
64030 <bitWidth>1</bitWidth>
64031 <access>write-only</access>
64032 </field>
64033 <field>
64034 <name>POPRGDNE</name>
64035 <description>Power-on programming done</description>
64036 <bitOffset>11</bitOffset>
64037 <bitWidth>1</bitWidth>
64038 <access>read-write</access>
64039 </field>
64040 </fields>
64041 </register>
64042 <register>
64043 <name>OTG_HS_DSTS</name>
64044 <displayName>OTG_HS_DSTS</displayName>
64045 <description>OTG_HS device status register</description>
64046 <addressOffset>0x8</addressOffset>
64047 <size>32</size>
64048 <access>read-only</access>
64049 <resetValue>0x00000010</resetValue>
64050 <fields>
64051 <field>
64052 <name>SUSPSTS</name>
64053 <description>Suspend status</description>
64054 <bitOffset>0</bitOffset>
64055 <bitWidth>1</bitWidth>
64056 </field>
64057 <field>
64058 <name>ENUMSPD</name>
64059 <description>Enumerated speed</description>
64060 <bitOffset>1</bitOffset>
64061 <bitWidth>2</bitWidth>
64062 </field>
64063 <field>
64064 <name>EERR</name>
64065 <description>Erratic error</description>
64066 <bitOffset>3</bitOffset>
64067 <bitWidth>1</bitWidth>
64068 </field>
64069 <field>
64070 <name>FNSOF</name>
64071 <description>Frame number of the received
64072 SOF</description>
64073 <bitOffset>8</bitOffset>
64074 <bitWidth>14</bitWidth>
64075 </field>
64076 </fields>
64077 </register>
64078 <register>
64079 <name>OTG_HS_DIEPMSK</name>
64080 <displayName>OTG_HS_DIEPMSK</displayName>
64081 <description>OTG_HS device IN endpoint common interrupt
64082 mask register</description>
64083 <addressOffset>0x10</addressOffset>
64084 <size>32</size>
64085 <access>read-write</access>
64086 <resetValue>0x0</resetValue>
64087 <fields>
64088 <field>
64089 <name>XFRCM</name>
64090 <description>Transfer completed interrupt
64091 mask</description>
64092 <bitOffset>0</bitOffset>
64093 <bitWidth>1</bitWidth>
64094 </field>
64095 <field>
64096 <name>EPDM</name>
64097 <description>Endpoint disabled interrupt
64098 mask</description>
64099 <bitOffset>1</bitOffset>
64100 <bitWidth>1</bitWidth>
64101 </field>
64102 <field>
64103 <name>TOM</name>
64104 <description>Timeout condition mask (nonisochronous
64105 endpoints)</description>
64106 <bitOffset>3</bitOffset>
64107 <bitWidth>1</bitWidth>
64108 </field>
64109 <field>
64110 <name>ITTXFEMSK</name>
64111 <description>IN token received when TxFIFO empty
64112 mask</description>
64113 <bitOffset>4</bitOffset>
64114 <bitWidth>1</bitWidth>
64115 </field>
64116 <field>
64117 <name>INEPNMM</name>
64118 <description>IN token received with EP mismatch
64119 mask</description>
64120 <bitOffset>5</bitOffset>
64121 <bitWidth>1</bitWidth>
64122 </field>
64123 <field>
64124 <name>INEPNEM</name>
64125 <description>IN endpoint NAK effective
64126 mask</description>
64127 <bitOffset>6</bitOffset>
64128 <bitWidth>1</bitWidth>
64129 </field>
64130 <field>
64131 <name>TXFURM</name>
64132 <description>FIFO underrun mask</description>
64133 <bitOffset>8</bitOffset>
64134 <bitWidth>1</bitWidth>
64135 </field>
64136 <field>
64137 <name>BIM</name>
64138 <description>BNA interrupt mask</description>
64139 <bitOffset>9</bitOffset>
64140 <bitWidth>1</bitWidth>
64141 </field>
64142 </fields>
64143 </register>
64144 <register>
64145 <name>OTG_HS_DOEPMSK</name>
64146 <displayName>OTG_HS_DOEPMSK</displayName>
64147 <description>OTG_HS device OUT endpoint common interrupt
64148 mask register</description>
64149 <addressOffset>0x14</addressOffset>
64150 <size>32</size>
64151 <access>read-write</access>
64152 <resetValue>0x0</resetValue>
64153 <fields>
64154 <field>
64155 <name>XFRCM</name>
64156 <description>Transfer completed interrupt
64157 mask</description>
64158 <bitOffset>0</bitOffset>
64159 <bitWidth>1</bitWidth>
64160 </field>
64161 <field>
64162 <name>EPDM</name>
64163 <description>Endpoint disabled interrupt
64164 mask</description>
64165 <bitOffset>1</bitOffset>
64166 <bitWidth>1</bitWidth>
64167 </field>
64168 <field>
64169 <name>STUPM</name>
64170 <description>SETUP phase done mask</description>
64171 <bitOffset>3</bitOffset>
64172 <bitWidth>1</bitWidth>
64173 </field>
64174 <field>
64175 <name>OTEPDM</name>
64176 <description>OUT token received when endpoint
64177 disabled mask</description>
64178 <bitOffset>4</bitOffset>
64179 <bitWidth>1</bitWidth>
64180 </field>
64181 <field>
64182 <name>B2BSTUP</name>
64183 <description>Back-to-back SETUP packets received
64184 mask</description>
64185 <bitOffset>6</bitOffset>
64186 <bitWidth>1</bitWidth>
64187 </field>
64188 <field>
64189 <name>OPEM</name>
64190 <description>OUT packet error mask</description>
64191 <bitOffset>8</bitOffset>
64192 <bitWidth>1</bitWidth>
64193 </field>
64194 <field>
64195 <name>BOIM</name>
64196 <description>BNA interrupt mask</description>
64197 <bitOffset>9</bitOffset>
64198 <bitWidth>1</bitWidth>
64199 </field>
64200 </fields>
64201 </register>
64202 <register>
64203 <name>OTG_HS_DAINT</name>
64204 <displayName>OTG_HS_DAINT</displayName>
64205 <description>OTG_HS device all endpoints interrupt
64206 register</description>
64207 <addressOffset>0x18</addressOffset>
64208 <size>32</size>
64209 <access>read-only</access>
64210 <resetValue>0x0</resetValue>
64211 <fields>
64212 <field>
64213 <name>IEPINT</name>
64214 <description>IN endpoint interrupt bits</description>
64215 <bitOffset>0</bitOffset>
64216 <bitWidth>16</bitWidth>
64217 </field>
64218 <field>
64219 <name>OEPINT</name>
64220 <description>OUT endpoint interrupt
64221 bits</description>
64222 <bitOffset>16</bitOffset>
64223 <bitWidth>16</bitWidth>
64224 </field>
64225 </fields>
64226 </register>
64227 <register>
64228 <name>OTG_HS_DAINTMSK</name>
64229 <displayName>OTG_HS_DAINTMSK</displayName>
64230 <description>OTG_HS all endpoints interrupt mask
64231 register</description>
64232 <addressOffset>0x1C</addressOffset>
64233 <size>32</size>
64234 <access>read-write</access>
64235 <resetValue>0x0</resetValue>
64236 <fields>
64237 <field>
64238 <name>IEPM</name>
64239 <description>IN EP interrupt mask bits</description>
64240 <bitOffset>0</bitOffset>
64241 <bitWidth>16</bitWidth>
64242 </field>
64243 <field>
64244 <name>OEPM</name>
64245 <description>OUT EP interrupt mask bits</description>
64246 <bitOffset>16</bitOffset>
64247 <bitWidth>16</bitWidth>
64248 </field>
64249 </fields>
64250 </register>
64251 <register>
64252 <name>OTG_HS_DVBUSDIS</name>
64253 <displayName>OTG_HS_DVBUSDIS</displayName>
64254 <description>OTG_HS device VBUS discharge time
64255 register</description>
64256 <addressOffset>0x28</addressOffset>
64257 <size>32</size>
64258 <access>read-write</access>
64259 <resetValue>0x000017D7</resetValue>
64260 <fields>
64261 <field>
64262 <name>VBUSDT</name>
64263 <description>Device VBUS discharge time</description>
64264 <bitOffset>0</bitOffset>
64265 <bitWidth>16</bitWidth>
64266 </field>
64267 </fields>
64268 </register>
64269 <register>
64270 <name>OTG_HS_DVBUSPULSE</name>
64271 <displayName>OTG_HS_DVBUSPULSE</displayName>
64272 <description>OTG_HS device VBUS pulsing time
64273 register</description>
64274 <addressOffset>0x2C</addressOffset>
64275 <size>32</size>
64276 <access>read-write</access>
64277 <resetValue>0x000005B8</resetValue>
64278 <fields>
64279 <field>
64280 <name>DVBUSP</name>
64281 <description>Device VBUS pulsing time</description>
64282 <bitOffset>0</bitOffset>
64283 <bitWidth>12</bitWidth>
64284 </field>
64285 </fields>
64286 </register>
64287 <register>
64288 <name>OTG_HS_DTHRCTL</name>
64289 <displayName>OTG_HS_DTHRCTL</displayName>
64290 <description>OTG_HS Device threshold control
64291 register</description>
64292 <addressOffset>0x30</addressOffset>
64293 <size>32</size>
64294 <access>read-write</access>
64295 <resetValue>0x0</resetValue>
64296 <fields>
64297 <field>
64298 <name>NONISOTHREN</name>
64299 <description>Nonisochronous IN endpoints threshold
64300 enable</description>
64301 <bitOffset>0</bitOffset>
64302 <bitWidth>1</bitWidth>
64303 </field>
64304 <field>
64305 <name>ISOTHREN</name>
64306 <description>ISO IN endpoint threshold
64307 enable</description>
64308 <bitOffset>1</bitOffset>
64309 <bitWidth>1</bitWidth>
64310 </field>
64311 <field>
64312 <name>TXTHRLEN</name>
64313 <description>Transmit threshold length</description>
64314 <bitOffset>2</bitOffset>
64315 <bitWidth>9</bitWidth>
64316 </field>
64317 <field>
64318 <name>RXTHREN</name>
64319 <description>Receive threshold enable</description>
64320 <bitOffset>16</bitOffset>
64321 <bitWidth>1</bitWidth>
64322 </field>
64323 <field>
64324 <name>RXTHRLEN</name>
64325 <description>Receive threshold length</description>
64326 <bitOffset>17</bitOffset>
64327 <bitWidth>9</bitWidth>
64328 </field>
64329 <field>
64330 <name>ARPEN</name>
64331 <description>Arbiter parking enable</description>
64332 <bitOffset>27</bitOffset>
64333 <bitWidth>1</bitWidth>
64334 </field>
64335 </fields>
64336 </register>
64337 <register>
64338 <name>OTG_HS_DIEPEMPMSK</name>
64339 <displayName>OTG_HS_DIEPEMPMSK</displayName>
64340 <description>OTG_HS device IN endpoint FIFO empty
64341 interrupt mask register</description>
64342 <addressOffset>0x34</addressOffset>
64343 <size>32</size>
64344 <access>read-write</access>
64345 <resetValue>0x0</resetValue>
64346 <fields>
64347 <field>
64348 <name>INEPTXFEM</name>
64349 <description>IN EP Tx FIFO empty interrupt mask
64350 bits</description>
64351 <bitOffset>0</bitOffset>
64352 <bitWidth>16</bitWidth>
64353 </field>
64354 </fields>
64355 </register>
64356 <register>
64357 <name>OTG_HS_DEACHINT</name>
64358 <displayName>OTG_HS_DEACHINT</displayName>
64359 <description>OTG_HS device each endpoint interrupt
64360 register</description>
64361 <addressOffset>0x38</addressOffset>
64362 <size>32</size>
64363 <access>read-write</access>
64364 <resetValue>0x0</resetValue>
64365 <fields>
64366 <field>
64367 <name>IEP1INT</name>
64368 <description>IN endpoint 1interrupt bit</description>
64369 <bitOffset>1</bitOffset>
64370 <bitWidth>1</bitWidth>
64371 </field>
64372 <field>
64373 <name>OEP1INT</name>
64374 <description>OUT endpoint 1 interrupt
64375 bit</description>
64376 <bitOffset>17</bitOffset>
64377 <bitWidth>1</bitWidth>
64378 </field>
64379 </fields>
64380 </register>
64381 <register>
64382 <name>OTG_HS_DEACHINTMSK</name>
64383 <displayName>OTG_HS_DEACHINTMSK</displayName>
64384 <description>OTG_HS device each endpoint interrupt
64385 register mask</description>
64386 <addressOffset>0x3C</addressOffset>
64387 <size>32</size>
64388 <access>read-write</access>
64389 <resetValue>0x0</resetValue>
64390 <fields>
64391 <field>
64392 <name>IEP1INTM</name>
64393 <description>IN Endpoint 1 interrupt mask
64394 bit</description>
64395 <bitOffset>1</bitOffset>
64396 <bitWidth>1</bitWidth>
64397 </field>
64398 <field>
64399 <name>OEP1INTM</name>
64400 <description>OUT Endpoint 1 interrupt mask
64401 bit</description>
64402 <bitOffset>17</bitOffset>
64403 <bitWidth>1</bitWidth>
64404 </field>
64405 </fields>
64406 </register>
64407 <register>
64408 <name>OTG_HS_DIEPCTL0</name>
64409 <displayName>OTG_HS_DIEPCTL0</displayName>
64410 <description>OTG device endpoint-0 control
64411 register</description>
64412 <addressOffset>0x100</addressOffset>
64413 <size>32</size>
64414 <resetValue>0x0</resetValue>
64415 <fields>
64416 <field>
64417 <name>MPSIZ</name>
64418 <description>Maximum packet size</description>
64419 <bitOffset>0</bitOffset>
64420 <bitWidth>11</bitWidth>
64421 <access>read-write</access>
64422 </field>
64423 <field>
64424 <name>USBAEP</name>
64425 <description>USB active endpoint</description>
64426 <bitOffset>15</bitOffset>
64427 <bitWidth>1</bitWidth>
64428 <access>read-write</access>
64429 </field>
64430 <field>
64431 <name>EONUM_DPID</name>
64432 <description>Even/odd frame</description>
64433 <bitOffset>16</bitOffset>
64434 <bitWidth>1</bitWidth>
64435 <access>read-only</access>
64436 </field>
64437 <field>
64438 <name>NAKSTS</name>
64439 <description>NAK status</description>
64440 <bitOffset>17</bitOffset>
64441 <bitWidth>1</bitWidth>
64442 <access>read-only</access>
64443 </field>
64444 <field>
64445 <name>EPTYP</name>
64446 <description>Endpoint type</description>
64447 <bitOffset>18</bitOffset>
64448 <bitWidth>2</bitWidth>
64449 <access>read-write</access>
64450 </field>
64451 <field>
64452 <name>Stall</name>
64453 <description>STALL handshake</description>
64454 <bitOffset>21</bitOffset>
64455 <bitWidth>1</bitWidth>
64456 <access>read-write</access>
64457 </field>
64458 <field>
64459 <name>TXFNUM</name>
64460 <description>TxFIFO number</description>
64461 <bitOffset>22</bitOffset>
64462 <bitWidth>4</bitWidth>
64463 <access>read-write</access>
64464 </field>
64465 <field>
64466 <name>CNAK</name>
64467 <description>Clear NAK</description>
64468 <bitOffset>26</bitOffset>
64469 <bitWidth>1</bitWidth>
64470 <access>write-only</access>
64471 </field>
64472 <field>
64473 <name>SNAK</name>
64474 <description>Set NAK</description>
64475 <bitOffset>27</bitOffset>
64476 <bitWidth>1</bitWidth>
64477 <access>write-only</access>
64478 </field>
64479 <field>
64480 <name>SD0PID_SEVNFRM</name>
64481 <description>Set DATA0 PID</description>
64482 <bitOffset>28</bitOffset>
64483 <bitWidth>1</bitWidth>
64484 <access>write-only</access>
64485 </field>
64486 <field>
64487 <name>SODDFRM</name>
64488 <description>Set odd frame</description>
64489 <bitOffset>29</bitOffset>
64490 <bitWidth>1</bitWidth>
64491 <access>write-only</access>
64492 </field>
64493 <field>
64494 <name>EPDIS</name>
64495 <description>Endpoint disable</description>
64496 <bitOffset>30</bitOffset>
64497 <bitWidth>1</bitWidth>
64498 <access>read-write</access>
64499 </field>
64500 <field>
64501 <name>EPENA</name>
64502 <description>Endpoint enable</description>
64503 <bitOffset>31</bitOffset>
64504 <bitWidth>1</bitWidth>
64505 <access>read-write</access>
64506 </field>
64507 </fields>
64508 </register>
64509 <register>
64510 <name>OTG_HS_DIEPCTL1</name>
64511 <displayName>OTG_HS_DIEPCTL1</displayName>
64512 <description>OTG device endpoint-1 control
64513 register</description>
64514 <addressOffset>0x120</addressOffset>
64515 <size>32</size>
64516 <resetValue>0x0</resetValue>
64517 <fields>
64518 <field>
64519 <name>MPSIZ</name>
64520 <description>Maximum packet size</description>
64521 <bitOffset>0</bitOffset>
64522 <bitWidth>11</bitWidth>
64523 <access>read-write</access>
64524 </field>
64525 <field>
64526 <name>USBAEP</name>
64527 <description>USB active endpoint</description>
64528 <bitOffset>15</bitOffset>
64529 <bitWidth>1</bitWidth>
64530 <access>read-write</access>
64531 </field>
64532 <field>
64533 <name>EONUM_DPID</name>
64534 <description>Even/odd frame</description>
64535 <bitOffset>16</bitOffset>
64536 <bitWidth>1</bitWidth>
64537 <access>read-only</access>
64538 </field>
64539 <field>
64540 <name>NAKSTS</name>
64541 <description>NAK status</description>
64542 <bitOffset>17</bitOffset>
64543 <bitWidth>1</bitWidth>
64544 <access>read-only</access>
64545 </field>
64546 <field>
64547 <name>EPTYP</name>
64548 <description>Endpoint type</description>
64549 <bitOffset>18</bitOffset>
64550 <bitWidth>2</bitWidth>
64551 <access>read-write</access>
64552 </field>
64553 <field>
64554 <name>Stall</name>
64555 <description>STALL handshake</description>
64556 <bitOffset>21</bitOffset>
64557 <bitWidth>1</bitWidth>
64558 <access>read-write</access>
64559 </field>
64560 <field>
64561 <name>TXFNUM</name>
64562 <description>TxFIFO number</description>
64563 <bitOffset>22</bitOffset>
64564 <bitWidth>4</bitWidth>
64565 <access>read-write</access>
64566 </field>
64567 <field>
64568 <name>CNAK</name>
64569 <description>Clear NAK</description>
64570 <bitOffset>26</bitOffset>
64571 <bitWidth>1</bitWidth>
64572 <access>write-only</access>
64573 </field>
64574 <field>
64575 <name>SNAK</name>
64576 <description>Set NAK</description>
64577 <bitOffset>27</bitOffset>
64578 <bitWidth>1</bitWidth>
64579 <access>write-only</access>
64580 </field>
64581 <field>
64582 <name>SD0PID_SEVNFRM</name>
64583 <description>Set DATA0 PID</description>
64584 <bitOffset>28</bitOffset>
64585 <bitWidth>1</bitWidth>
64586 <access>write-only</access>
64587 </field>
64588 <field>
64589 <name>SODDFRM</name>
64590 <description>Set odd frame</description>
64591 <bitOffset>29</bitOffset>
64592 <bitWidth>1</bitWidth>
64593 <access>write-only</access>
64594 </field>
64595 <field>
64596 <name>EPDIS</name>
64597 <description>Endpoint disable</description>
64598 <bitOffset>30</bitOffset>
64599 <bitWidth>1</bitWidth>
64600 <access>read-write</access>
64601 </field>
64602 <field>
64603 <name>EPENA</name>
64604 <description>Endpoint enable</description>
64605 <bitOffset>31</bitOffset>
64606 <bitWidth>1</bitWidth>
64607 <access>read-write</access>
64608 </field>
64609 </fields>
64610 </register>
64611 <register>
64612 <name>OTG_HS_DIEPCTL2</name>
64613 <displayName>OTG_HS_DIEPCTL2</displayName>
64614 <description>OTG device endpoint-2 control
64615 register</description>
64616 <addressOffset>0x140</addressOffset>
64617 <size>32</size>
64618 <resetValue>0x0</resetValue>
64619 <fields>
64620 <field>
64621 <name>MPSIZ</name>
64622 <description>Maximum packet size</description>
64623 <bitOffset>0</bitOffset>
64624 <bitWidth>11</bitWidth>
64625 <access>read-write</access>
64626 </field>
64627 <field>
64628 <name>USBAEP</name>
64629 <description>USB active endpoint</description>
64630 <bitOffset>15</bitOffset>
64631 <bitWidth>1</bitWidth>
64632 <access>read-write</access>
64633 </field>
64634 <field>
64635 <name>EONUM_DPID</name>
64636 <description>Even/odd frame</description>
64637 <bitOffset>16</bitOffset>
64638 <bitWidth>1</bitWidth>
64639 <access>read-only</access>
64640 </field>
64641 <field>
64642 <name>NAKSTS</name>
64643 <description>NAK status</description>
64644 <bitOffset>17</bitOffset>
64645 <bitWidth>1</bitWidth>
64646 <access>read-only</access>
64647 </field>
64648 <field>
64649 <name>EPTYP</name>
64650 <description>Endpoint type</description>
64651 <bitOffset>18</bitOffset>
64652 <bitWidth>2</bitWidth>
64653 <access>read-write</access>
64654 </field>
64655 <field>
64656 <name>Stall</name>
64657 <description>STALL handshake</description>
64658 <bitOffset>21</bitOffset>
64659 <bitWidth>1</bitWidth>
64660 <access>read-write</access>
64661 </field>
64662 <field>
64663 <name>TXFNUM</name>
64664 <description>TxFIFO number</description>
64665 <bitOffset>22</bitOffset>
64666 <bitWidth>4</bitWidth>
64667 <access>read-write</access>
64668 </field>
64669 <field>
64670 <name>CNAK</name>
64671 <description>Clear NAK</description>
64672 <bitOffset>26</bitOffset>
64673 <bitWidth>1</bitWidth>
64674 <access>write-only</access>
64675 </field>
64676 <field>
64677 <name>SNAK</name>
64678 <description>Set NAK</description>
64679 <bitOffset>27</bitOffset>
64680 <bitWidth>1</bitWidth>
64681 <access>write-only</access>
64682 </field>
64683 <field>
64684 <name>SD0PID_SEVNFRM</name>
64685 <description>Set DATA0 PID</description>
64686 <bitOffset>28</bitOffset>
64687 <bitWidth>1</bitWidth>
64688 <access>write-only</access>
64689 </field>
64690 <field>
64691 <name>SODDFRM</name>
64692 <description>Set odd frame</description>
64693 <bitOffset>29</bitOffset>
64694 <bitWidth>1</bitWidth>
64695 <access>write-only</access>
64696 </field>
64697 <field>
64698 <name>EPDIS</name>
64699 <description>Endpoint disable</description>
64700 <bitOffset>30</bitOffset>
64701 <bitWidth>1</bitWidth>
64702 <access>read-write</access>
64703 </field>
64704 <field>
64705 <name>EPENA</name>
64706 <description>Endpoint enable</description>
64707 <bitOffset>31</bitOffset>
64708 <bitWidth>1</bitWidth>
64709 <access>read-write</access>
64710 </field>
64711 </fields>
64712 </register>
64713 <register>
64714 <name>OTG_HS_DIEPCTL3</name>
64715 <displayName>OTG_HS_DIEPCTL3</displayName>
64716 <description>OTG device endpoint-3 control
64717 register</description>
64718 <addressOffset>0x160</addressOffset>
64719 <size>32</size>
64720 <resetValue>0x0</resetValue>
64721 <fields>
64722 <field>
64723 <name>MPSIZ</name>
64724 <description>Maximum packet size</description>
64725 <bitOffset>0</bitOffset>
64726 <bitWidth>11</bitWidth>
64727 <access>read-write</access>
64728 </field>
64729 <field>
64730 <name>USBAEP</name>
64731 <description>USB active endpoint</description>
64732 <bitOffset>15</bitOffset>
64733 <bitWidth>1</bitWidth>
64734 <access>read-write</access>
64735 </field>
64736 <field>
64737 <name>EONUM_DPID</name>
64738 <description>Even/odd frame</description>
64739 <bitOffset>16</bitOffset>
64740 <bitWidth>1</bitWidth>
64741 <access>read-only</access>
64742 </field>
64743 <field>
64744 <name>NAKSTS</name>
64745 <description>NAK status</description>
64746 <bitOffset>17</bitOffset>
64747 <bitWidth>1</bitWidth>
64748 <access>read-only</access>
64749 </field>
64750 <field>
64751 <name>EPTYP</name>
64752 <description>Endpoint type</description>
64753 <bitOffset>18</bitOffset>
64754 <bitWidth>2</bitWidth>
64755 <access>read-write</access>
64756 </field>
64757 <field>
64758 <name>Stall</name>
64759 <description>STALL handshake</description>
64760 <bitOffset>21</bitOffset>
64761 <bitWidth>1</bitWidth>
64762 <access>read-write</access>
64763 </field>
64764 <field>
64765 <name>TXFNUM</name>
64766 <description>TxFIFO number</description>
64767 <bitOffset>22</bitOffset>
64768 <bitWidth>4</bitWidth>
64769 <access>read-write</access>
64770 </field>
64771 <field>
64772 <name>CNAK</name>
64773 <description>Clear NAK</description>
64774 <bitOffset>26</bitOffset>
64775 <bitWidth>1</bitWidth>
64776 <access>write-only</access>
64777 </field>
64778 <field>
64779 <name>SNAK</name>
64780 <description>Set NAK</description>
64781 <bitOffset>27</bitOffset>
64782 <bitWidth>1</bitWidth>
64783 <access>write-only</access>
64784 </field>
64785 <field>
64786 <name>SD0PID_SEVNFRM</name>
64787 <description>Set DATA0 PID</description>
64788 <bitOffset>28</bitOffset>
64789 <bitWidth>1</bitWidth>
64790 <access>write-only</access>
64791 </field>
64792 <field>
64793 <name>SODDFRM</name>
64794 <description>Set odd frame</description>
64795 <bitOffset>29</bitOffset>
64796 <bitWidth>1</bitWidth>
64797 <access>write-only</access>
64798 </field>
64799 <field>
64800 <name>EPDIS</name>
64801 <description>Endpoint disable</description>
64802 <bitOffset>30</bitOffset>
64803 <bitWidth>1</bitWidth>
64804 <access>read-write</access>
64805 </field>
64806 <field>
64807 <name>EPENA</name>
64808 <description>Endpoint enable</description>
64809 <bitOffset>31</bitOffset>
64810 <bitWidth>1</bitWidth>
64811 <access>read-write</access>
64812 </field>
64813 </fields>
64814 </register>
64815 <register>
64816 <name>OTG_HS_DIEPCTL4</name>
64817 <displayName>OTG_HS_DIEPCTL4</displayName>
64818 <description>OTG device endpoint-4 control
64819 register</description>
64820 <addressOffset>0x180</addressOffset>
64821 <size>32</size>
64822 <resetValue>0x0</resetValue>
64823 <fields>
64824 <field>
64825 <name>MPSIZ</name>
64826 <description>Maximum packet size</description>
64827 <bitOffset>0</bitOffset>
64828 <bitWidth>11</bitWidth>
64829 <access>read-write</access>
64830 </field>
64831 <field>
64832 <name>USBAEP</name>
64833 <description>USB active endpoint</description>
64834 <bitOffset>15</bitOffset>
64835 <bitWidth>1</bitWidth>
64836 <access>read-write</access>
64837 </field>
64838 <field>
64839 <name>EONUM_DPID</name>
64840 <description>Even/odd frame</description>
64841 <bitOffset>16</bitOffset>
64842 <bitWidth>1</bitWidth>
64843 <access>read-only</access>
64844 </field>
64845 <field>
64846 <name>NAKSTS</name>
64847 <description>NAK status</description>
64848 <bitOffset>17</bitOffset>
64849 <bitWidth>1</bitWidth>
64850 <access>read-only</access>
64851 </field>
64852 <field>
64853 <name>EPTYP</name>
64854 <description>Endpoint type</description>
64855 <bitOffset>18</bitOffset>
64856 <bitWidth>2</bitWidth>
64857 <access>read-write</access>
64858 </field>
64859 <field>
64860 <name>Stall</name>
64861 <description>STALL handshake</description>
64862 <bitOffset>21</bitOffset>
64863 <bitWidth>1</bitWidth>
64864 <access>read-write</access>
64865 </field>
64866 <field>
64867 <name>TXFNUM</name>
64868 <description>TxFIFO number</description>
64869 <bitOffset>22</bitOffset>
64870 <bitWidth>4</bitWidth>
64871 <access>read-write</access>
64872 </field>
64873 <field>
64874 <name>CNAK</name>
64875 <description>Clear NAK</description>
64876 <bitOffset>26</bitOffset>
64877 <bitWidth>1</bitWidth>
64878 <access>write-only</access>
64879 </field>
64880 <field>
64881 <name>SNAK</name>
64882 <description>Set NAK</description>
64883 <bitOffset>27</bitOffset>
64884 <bitWidth>1</bitWidth>
64885 <access>write-only</access>
64886 </field>
64887 <field>
64888 <name>SD0PID_SEVNFRM</name>
64889 <description>Set DATA0 PID</description>
64890 <bitOffset>28</bitOffset>
64891 <bitWidth>1</bitWidth>
64892 <access>write-only</access>
64893 </field>
64894 <field>
64895 <name>SODDFRM</name>
64896 <description>Set odd frame</description>
64897 <bitOffset>29</bitOffset>
64898 <bitWidth>1</bitWidth>
64899 <access>write-only</access>
64900 </field>
64901 <field>
64902 <name>EPDIS</name>
64903 <description>Endpoint disable</description>
64904 <bitOffset>30</bitOffset>
64905 <bitWidth>1</bitWidth>
64906 <access>read-write</access>
64907 </field>
64908 <field>
64909 <name>EPENA</name>
64910 <description>Endpoint enable</description>
64911 <bitOffset>31</bitOffset>
64912 <bitWidth>1</bitWidth>
64913 <access>read-write</access>
64914 </field>
64915 </fields>
64916 </register>
64917 <register>
64918 <name>OTG_HS_DIEPCTL5</name>
64919 <displayName>OTG_HS_DIEPCTL5</displayName>
64920 <description>OTG device endpoint-5 control
64921 register</description>
64922 <addressOffset>0x1A0</addressOffset>
64923 <size>32</size>
64924 <resetValue>0x0</resetValue>
64925 <fields>
64926 <field>
64927 <name>MPSIZ</name>
64928 <description>Maximum packet size</description>
64929 <bitOffset>0</bitOffset>
64930 <bitWidth>11</bitWidth>
64931 <access>read-write</access>
64932 </field>
64933 <field>
64934 <name>USBAEP</name>
64935 <description>USB active endpoint</description>
64936 <bitOffset>15</bitOffset>
64937 <bitWidth>1</bitWidth>
64938 <access>read-write</access>
64939 </field>
64940 <field>
64941 <name>EONUM_DPID</name>
64942 <description>Even/odd frame</description>
64943 <bitOffset>16</bitOffset>
64944 <bitWidth>1</bitWidth>
64945 <access>read-only</access>
64946 </field>
64947 <field>
64948 <name>NAKSTS</name>
64949 <description>NAK status</description>
64950 <bitOffset>17</bitOffset>
64951 <bitWidth>1</bitWidth>
64952 <access>read-only</access>
64953 </field>
64954 <field>
64955 <name>EPTYP</name>
64956 <description>Endpoint type</description>
64957 <bitOffset>18</bitOffset>
64958 <bitWidth>2</bitWidth>
64959 <access>read-write</access>
64960 </field>
64961 <field>
64962 <name>Stall</name>
64963 <description>STALL handshake</description>
64964 <bitOffset>21</bitOffset>
64965 <bitWidth>1</bitWidth>
64966 <access>read-write</access>
64967 </field>
64968 <field>
64969 <name>TXFNUM</name>
64970 <description>TxFIFO number</description>
64971 <bitOffset>22</bitOffset>
64972 <bitWidth>4</bitWidth>
64973 <access>read-write</access>
64974 </field>
64975 <field>
64976 <name>CNAK</name>
64977 <description>Clear NAK</description>
64978 <bitOffset>26</bitOffset>
64979 <bitWidth>1</bitWidth>
64980 <access>write-only</access>
64981 </field>
64982 <field>
64983 <name>SNAK</name>
64984 <description>Set NAK</description>
64985 <bitOffset>27</bitOffset>
64986 <bitWidth>1</bitWidth>
64987 <access>write-only</access>
64988 </field>
64989 <field>
64990 <name>SD0PID_SEVNFRM</name>
64991 <description>Set DATA0 PID</description>
64992 <bitOffset>28</bitOffset>
64993 <bitWidth>1</bitWidth>
64994 <access>write-only</access>
64995 </field>
64996 <field>
64997 <name>SODDFRM</name>
64998 <description>Set odd frame</description>
64999 <bitOffset>29</bitOffset>
65000 <bitWidth>1</bitWidth>
65001 <access>write-only</access>
65002 </field>
65003 <field>
65004 <name>EPDIS</name>
65005 <description>Endpoint disable</description>
65006 <bitOffset>30</bitOffset>
65007 <bitWidth>1</bitWidth>
65008 <access>read-write</access>
65009 </field>
65010 <field>
65011 <name>EPENA</name>
65012 <description>Endpoint enable</description>
65013 <bitOffset>31</bitOffset>
65014 <bitWidth>1</bitWidth>
65015 <access>read-write</access>
65016 </field>
65017 </fields>
65018 </register>
65019 <register>
65020 <name>OTG_HS_DIEPCTL6</name>
65021 <displayName>OTG_HS_DIEPCTL6</displayName>
65022 <description>OTG device endpoint-6 control
65023 register</description>
65024 <addressOffset>0x1C0</addressOffset>
65025 <size>32</size>
65026 <resetValue>0x0</resetValue>
65027 <fields>
65028 <field>
65029 <name>MPSIZ</name>
65030 <description>Maximum packet size</description>
65031 <bitOffset>0</bitOffset>
65032 <bitWidth>11</bitWidth>
65033 <access>read-write</access>
65034 </field>
65035 <field>
65036 <name>USBAEP</name>
65037 <description>USB active endpoint</description>
65038 <bitOffset>15</bitOffset>
65039 <bitWidth>1</bitWidth>
65040 <access>read-write</access>
65041 </field>
65042 <field>
65043 <name>EONUM_DPID</name>
65044 <description>Even/odd frame</description>
65045 <bitOffset>16</bitOffset>
65046 <bitWidth>1</bitWidth>
65047 <access>read-only</access>
65048 </field>
65049 <field>
65050 <name>NAKSTS</name>
65051 <description>NAK status</description>
65052 <bitOffset>17</bitOffset>
65053 <bitWidth>1</bitWidth>
65054 <access>read-only</access>
65055 </field>
65056 <field>
65057 <name>EPTYP</name>
65058 <description>Endpoint type</description>
65059 <bitOffset>18</bitOffset>
65060 <bitWidth>2</bitWidth>
65061 <access>read-write</access>
65062 </field>
65063 <field>
65064 <name>Stall</name>
65065 <description>STALL handshake</description>
65066 <bitOffset>21</bitOffset>
65067 <bitWidth>1</bitWidth>
65068 <access>read-write</access>
65069 </field>
65070 <field>
65071 <name>TXFNUM</name>
65072 <description>TxFIFO number</description>
65073 <bitOffset>22</bitOffset>
65074 <bitWidth>4</bitWidth>
65075 <access>read-write</access>
65076 </field>
65077 <field>
65078 <name>CNAK</name>
65079 <description>Clear NAK</description>
65080 <bitOffset>26</bitOffset>
65081 <bitWidth>1</bitWidth>
65082 <access>write-only</access>
65083 </field>
65084 <field>
65085 <name>SNAK</name>
65086 <description>Set NAK</description>
65087 <bitOffset>27</bitOffset>
65088 <bitWidth>1</bitWidth>
65089 <access>write-only</access>
65090 </field>
65091 <field>
65092 <name>SD0PID_SEVNFRM</name>
65093 <description>Set DATA0 PID</description>
65094 <bitOffset>28</bitOffset>
65095 <bitWidth>1</bitWidth>
65096 <access>write-only</access>
65097 </field>
65098 <field>
65099 <name>SODDFRM</name>
65100 <description>Set odd frame</description>
65101 <bitOffset>29</bitOffset>
65102 <bitWidth>1</bitWidth>
65103 <access>write-only</access>
65104 </field>
65105 <field>
65106 <name>EPDIS</name>
65107 <description>Endpoint disable</description>
65108 <bitOffset>30</bitOffset>
65109 <bitWidth>1</bitWidth>
65110 <access>read-write</access>
65111 </field>
65112 <field>
65113 <name>EPENA</name>
65114 <description>Endpoint enable</description>
65115 <bitOffset>31</bitOffset>
65116 <bitWidth>1</bitWidth>
65117 <access>read-write</access>
65118 </field>
65119 </fields>
65120 </register>
65121 <register>
65122 <name>OTG_HS_DIEPCTL7</name>
65123 <displayName>OTG_HS_DIEPCTL7</displayName>
65124 <description>OTG device endpoint-7 control
65125 register</description>
65126 <addressOffset>0x1E0</addressOffset>
65127 <size>32</size>
65128 <resetValue>0x0</resetValue>
65129 <fields>
65130 <field>
65131 <name>MPSIZ</name>
65132 <description>Maximum packet size</description>
65133 <bitOffset>0</bitOffset>
65134 <bitWidth>11</bitWidth>
65135 <access>read-write</access>
65136 </field>
65137 <field>
65138 <name>USBAEP</name>
65139 <description>USB active endpoint</description>
65140 <bitOffset>15</bitOffset>
65141 <bitWidth>1</bitWidth>
65142 <access>read-write</access>
65143 </field>
65144 <field>
65145 <name>EONUM_DPID</name>
65146 <description>Even/odd frame</description>
65147 <bitOffset>16</bitOffset>
65148 <bitWidth>1</bitWidth>
65149 <access>read-only</access>
65150 </field>
65151 <field>
65152 <name>NAKSTS</name>
65153 <description>NAK status</description>
65154 <bitOffset>17</bitOffset>
65155 <bitWidth>1</bitWidth>
65156 <access>read-only</access>
65157 </field>
65158 <field>
65159 <name>EPTYP</name>
65160 <description>Endpoint type</description>
65161 <bitOffset>18</bitOffset>
65162 <bitWidth>2</bitWidth>
65163 <access>read-write</access>
65164 </field>
65165 <field>
65166 <name>Stall</name>
65167 <description>STALL handshake</description>
65168 <bitOffset>21</bitOffset>
65169 <bitWidth>1</bitWidth>
65170 <access>read-write</access>
65171 </field>
65172 <field>
65173 <name>TXFNUM</name>
65174 <description>TxFIFO number</description>
65175 <bitOffset>22</bitOffset>
65176 <bitWidth>4</bitWidth>
65177 <access>read-write</access>
65178 </field>
65179 <field>
65180 <name>CNAK</name>
65181 <description>Clear NAK</description>
65182 <bitOffset>26</bitOffset>
65183 <bitWidth>1</bitWidth>
65184 <access>write-only</access>
65185 </field>
65186 <field>
65187 <name>SNAK</name>
65188 <description>Set NAK</description>
65189 <bitOffset>27</bitOffset>
65190 <bitWidth>1</bitWidth>
65191 <access>write-only</access>
65192 </field>
65193 <field>
65194 <name>SD0PID_SEVNFRM</name>
65195 <description>Set DATA0 PID</description>
65196 <bitOffset>28</bitOffset>
65197 <bitWidth>1</bitWidth>
65198 <access>write-only</access>
65199 </field>
65200 <field>
65201 <name>SODDFRM</name>
65202 <description>Set odd frame</description>
65203 <bitOffset>29</bitOffset>
65204 <bitWidth>1</bitWidth>
65205 <access>write-only</access>
65206 </field>
65207 <field>
65208 <name>EPDIS</name>
65209 <description>Endpoint disable</description>
65210 <bitOffset>30</bitOffset>
65211 <bitWidth>1</bitWidth>
65212 <access>read-write</access>
65213 </field>
65214 <field>
65215 <name>EPENA</name>
65216 <description>Endpoint enable</description>
65217 <bitOffset>31</bitOffset>
65218 <bitWidth>1</bitWidth>
65219 <access>read-write</access>
65220 </field>
65221 </fields>
65222 </register>
65223 <register>
65224 <name>OTG_HS_DIEPINT0</name>
65225 <displayName>OTG_HS_DIEPINT0</displayName>
65226 <description>OTG device endpoint-0 interrupt
65227 register</description>
65228 <addressOffset>0x108</addressOffset>
65229 <size>32</size>
65230 <resetValue>0x00000080</resetValue>
65231 <fields>
65232 <field>
65233 <name>XFRC</name>
65234 <description>Transfer completed
65235 interrupt</description>
65236 <bitOffset>0</bitOffset>
65237 <bitWidth>1</bitWidth>
65238 <access>read-write</access>
65239 </field>
65240 <field>
65241 <name>EPDISD</name>
65242 <description>Endpoint disabled
65243 interrupt</description>
65244 <bitOffset>1</bitOffset>
65245 <bitWidth>1</bitWidth>
65246 <access>read-write</access>
65247 </field>
65248 <field>
65249 <name>TOC</name>
65250 <description>Timeout condition</description>
65251 <bitOffset>3</bitOffset>
65252 <bitWidth>1</bitWidth>
65253 <access>read-write</access>
65254 </field>
65255 <field>
65256 <name>ITTXFE</name>
65257 <description>IN token received when TxFIFO is
65258 empty</description>
65259 <bitOffset>4</bitOffset>
65260 <bitWidth>1</bitWidth>
65261 <access>read-write</access>
65262 </field>
65263 <field>
65264 <name>INEPNE</name>
65265 <description>IN endpoint NAK effective</description>
65266 <bitOffset>6</bitOffset>
65267 <bitWidth>1</bitWidth>
65268 <access>read-write</access>
65269 </field>
65270 <field>
65271 <name>TXFE</name>
65272 <description>Transmit FIFO empty</description>
65273 <bitOffset>7</bitOffset>
65274 <bitWidth>1</bitWidth>
65275 <access>read-only</access>
65276 </field>
65277 <field>
65278 <name>TXFIFOUDRN</name>
65279 <description>Transmit Fifo Underrun</description>
65280 <bitOffset>8</bitOffset>
65281 <bitWidth>1</bitWidth>
65282 <access>read-write</access>
65283 </field>
65284 <field>
65285 <name>BNA</name>
65286 <description>Buffer not available
65287 interrupt</description>
65288 <bitOffset>9</bitOffset>
65289 <bitWidth>1</bitWidth>
65290 <access>read-write</access>
65291 </field>
65292 <field>
65293 <name>PKTDRPSTS</name>
65294 <description>Packet dropped status</description>
65295 <bitOffset>11</bitOffset>
65296 <bitWidth>1</bitWidth>
65297 <access>read-write</access>
65298 </field>
65299 <field>
65300 <name>BERR</name>
65301 <description>Babble error interrupt</description>
65302 <bitOffset>12</bitOffset>
65303 <bitWidth>1</bitWidth>
65304 <access>read-write</access>
65305 </field>
65306 <field>
65307 <name>NAK</name>
65308 <description>NAK interrupt</description>
65309 <bitOffset>13</bitOffset>
65310 <bitWidth>1</bitWidth>
65311 <access>read-write</access>
65312 </field>
65313 </fields>
65314 </register>
65315 <register>
65316 <name>OTG_HS_DIEPINT1</name>
65317 <displayName>OTG_HS_DIEPINT1</displayName>
65318 <description>OTG device endpoint-1 interrupt
65319 register</description>
65320 <addressOffset>0x128</addressOffset>
65321 <size>32</size>
65322 <resetValue>0x0</resetValue>
65323 <fields>
65324 <field>
65325 <name>XFRC</name>
65326 <description>Transfer completed
65327 interrupt</description>
65328 <bitOffset>0</bitOffset>
65329 <bitWidth>1</bitWidth>
65330 <access>read-write</access>
65331 </field>
65332 <field>
65333 <name>EPDISD</name>
65334 <description>Endpoint disabled
65335 interrupt</description>
65336 <bitOffset>1</bitOffset>
65337 <bitWidth>1</bitWidth>
65338 <access>read-write</access>
65339 </field>
65340 <field>
65341 <name>TOC</name>
65342 <description>Timeout condition</description>
65343 <bitOffset>3</bitOffset>
65344 <bitWidth>1</bitWidth>
65345 <access>read-write</access>
65346 </field>
65347 <field>
65348 <name>ITTXFE</name>
65349 <description>IN token received when TxFIFO is
65350 empty</description>
65351 <bitOffset>4</bitOffset>
65352 <bitWidth>1</bitWidth>
65353 <access>read-write</access>
65354 </field>
65355 <field>
65356 <name>INEPNE</name>
65357 <description>IN endpoint NAK effective</description>
65358 <bitOffset>6</bitOffset>
65359 <bitWidth>1</bitWidth>
65360 <access>read-write</access>
65361 </field>
65362 <field>
65363 <name>TXFE</name>
65364 <description>Transmit FIFO empty</description>
65365 <bitOffset>7</bitOffset>
65366 <bitWidth>1</bitWidth>
65367 <access>read-only</access>
65368 </field>
65369 <field>
65370 <name>TXFIFOUDRN</name>
65371 <description>Transmit Fifo Underrun</description>
65372 <bitOffset>8</bitOffset>
65373 <bitWidth>1</bitWidth>
65374 <access>read-write</access>
65375 </field>
65376 <field>
65377 <name>BNA</name>
65378 <description>Buffer not available
65379 interrupt</description>
65380 <bitOffset>9</bitOffset>
65381 <bitWidth>1</bitWidth>
65382 <access>read-write</access>
65383 </field>
65384 <field>
65385 <name>PKTDRPSTS</name>
65386 <description>Packet dropped status</description>
65387 <bitOffset>11</bitOffset>
65388 <bitWidth>1</bitWidth>
65389 <access>read-write</access>
65390 </field>
65391 <field>
65392 <name>BERR</name>
65393 <description>Babble error interrupt</description>
65394 <bitOffset>12</bitOffset>
65395 <bitWidth>1</bitWidth>
65396 <access>read-write</access>
65397 </field>
65398 <field>
65399 <name>NAK</name>
65400 <description>NAK interrupt</description>
65401 <bitOffset>13</bitOffset>
65402 <bitWidth>1</bitWidth>
65403 <access>read-write</access>
65404 </field>
65405 </fields>
65406 </register>
65407 <register>
65408 <name>OTG_HS_DIEPINT2</name>
65409 <displayName>OTG_HS_DIEPINT2</displayName>
65410 <description>OTG device endpoint-2 interrupt
65411 register</description>
65412 <addressOffset>0x148</addressOffset>
65413 <size>32</size>
65414 <resetValue>0x0</resetValue>
65415 <fields>
65416 <field>
65417 <name>XFRC</name>
65418 <description>Transfer completed
65419 interrupt</description>
65420 <bitOffset>0</bitOffset>
65421 <bitWidth>1</bitWidth>
65422 <access>read-write</access>
65423 </field>
65424 <field>
65425 <name>EPDISD</name>
65426 <description>Endpoint disabled
65427 interrupt</description>
65428 <bitOffset>1</bitOffset>
65429 <bitWidth>1</bitWidth>
65430 <access>read-write</access>
65431 </field>
65432 <field>
65433 <name>TOC</name>
65434 <description>Timeout condition</description>
65435 <bitOffset>3</bitOffset>
65436 <bitWidth>1</bitWidth>
65437 <access>read-write</access>
65438 </field>
65439 <field>
65440 <name>ITTXFE</name>
65441 <description>IN token received when TxFIFO is
65442 empty</description>
65443 <bitOffset>4</bitOffset>
65444 <bitWidth>1</bitWidth>
65445 <access>read-write</access>
65446 </field>
65447 <field>
65448 <name>INEPNE</name>
65449 <description>IN endpoint NAK effective</description>
65450 <bitOffset>6</bitOffset>
65451 <bitWidth>1</bitWidth>
65452 <access>read-write</access>
65453 </field>
65454 <field>
65455 <name>TXFE</name>
65456 <description>Transmit FIFO empty</description>
65457 <bitOffset>7</bitOffset>
65458 <bitWidth>1</bitWidth>
65459 <access>read-only</access>
65460 </field>
65461 <field>
65462 <name>TXFIFOUDRN</name>
65463 <description>Transmit Fifo Underrun</description>
65464 <bitOffset>8</bitOffset>
65465 <bitWidth>1</bitWidth>
65466 <access>read-write</access>
65467 </field>
65468 <field>
65469 <name>BNA</name>
65470 <description>Buffer not available
65471 interrupt</description>
65472 <bitOffset>9</bitOffset>
65473 <bitWidth>1</bitWidth>
65474 <access>read-write</access>
65475 </field>
65476 <field>
65477 <name>PKTDRPSTS</name>
65478 <description>Packet dropped status</description>
65479 <bitOffset>11</bitOffset>
65480 <bitWidth>1</bitWidth>
65481 <access>read-write</access>
65482 </field>
65483 <field>
65484 <name>BERR</name>
65485 <description>Babble error interrupt</description>
65486 <bitOffset>12</bitOffset>
65487 <bitWidth>1</bitWidth>
65488 <access>read-write</access>
65489 </field>
65490 <field>
65491 <name>NAK</name>
65492 <description>NAK interrupt</description>
65493 <bitOffset>13</bitOffset>
65494 <bitWidth>1</bitWidth>
65495 <access>read-write</access>
65496 </field>
65497 </fields>
65498 </register>
65499 <register>
65500 <name>OTG_HS_DIEPINT3</name>
65501 <displayName>OTG_HS_DIEPINT3</displayName>
65502 <description>OTG device endpoint-3 interrupt
65503 register</description>
65504 <addressOffset>0x168</addressOffset>
65505 <size>32</size>
65506 <resetValue>0x0</resetValue>
65507 <fields>
65508 <field>
65509 <name>XFRC</name>
65510 <description>Transfer completed
65511 interrupt</description>
65512 <bitOffset>0</bitOffset>
65513 <bitWidth>1</bitWidth>
65514 <access>read-write</access>
65515 </field>
65516 <field>
65517 <name>EPDISD</name>
65518 <description>Endpoint disabled
65519 interrupt</description>
65520 <bitOffset>1</bitOffset>
65521 <bitWidth>1</bitWidth>
65522 <access>read-write</access>
65523 </field>
65524 <field>
65525 <name>TOC</name>
65526 <description>Timeout condition</description>
65527 <bitOffset>3</bitOffset>
65528 <bitWidth>1</bitWidth>
65529 <access>read-write</access>
65530 </field>
65531 <field>
65532 <name>ITTXFE</name>
65533 <description>IN token received when TxFIFO is
65534 empty</description>
65535 <bitOffset>4</bitOffset>
65536 <bitWidth>1</bitWidth>
65537 <access>read-write</access>
65538 </field>
65539 <field>
65540 <name>INEPNE</name>
65541 <description>IN endpoint NAK effective</description>
65542 <bitOffset>6</bitOffset>
65543 <bitWidth>1</bitWidth>
65544 <access>read-write</access>
65545 </field>
65546 <field>
65547 <name>TXFE</name>
65548 <description>Transmit FIFO empty</description>
65549 <bitOffset>7</bitOffset>
65550 <bitWidth>1</bitWidth>
65551 <access>read-only</access>
65552 </field>
65553 <field>
65554 <name>TXFIFOUDRN</name>
65555 <description>Transmit Fifo Underrun</description>
65556 <bitOffset>8</bitOffset>
65557 <bitWidth>1</bitWidth>
65558 <access>read-write</access>
65559 </field>
65560 <field>
65561 <name>BNA</name>
65562 <description>Buffer not available
65563 interrupt</description>
65564 <bitOffset>9</bitOffset>
65565 <bitWidth>1</bitWidth>
65566 <access>read-write</access>
65567 </field>
65568 <field>
65569 <name>PKTDRPSTS</name>
65570 <description>Packet dropped status</description>
65571 <bitOffset>11</bitOffset>
65572 <bitWidth>1</bitWidth>
65573 <access>read-write</access>
65574 </field>
65575 <field>
65576 <name>BERR</name>
65577 <description>Babble error interrupt</description>
65578 <bitOffset>12</bitOffset>
65579 <bitWidth>1</bitWidth>
65580 <access>read-write</access>
65581 </field>
65582 <field>
65583 <name>NAK</name>
65584 <description>NAK interrupt</description>
65585 <bitOffset>13</bitOffset>
65586 <bitWidth>1</bitWidth>
65587 <access>read-write</access>
65588 </field>
65589 </fields>
65590 </register>
65591 <register>
65592 <name>OTG_HS_DIEPINT4</name>
65593 <displayName>OTG_HS_DIEPINT4</displayName>
65594 <description>OTG device endpoint-4 interrupt
65595 register</description>
65596 <addressOffset>0x188</addressOffset>
65597 <size>32</size>
65598 <resetValue>0x0</resetValue>
65599 <fields>
65600 <field>
65601 <name>XFRC</name>
65602 <description>Transfer completed
65603 interrupt</description>
65604 <bitOffset>0</bitOffset>
65605 <bitWidth>1</bitWidth>
65606 <access>read-write</access>
65607 </field>
65608 <field>
65609 <name>EPDISD</name>
65610 <description>Endpoint disabled
65611 interrupt</description>
65612 <bitOffset>1</bitOffset>
65613 <bitWidth>1</bitWidth>
65614 <access>read-write</access>
65615 </field>
65616 <field>
65617 <name>TOC</name>
65618 <description>Timeout condition</description>
65619 <bitOffset>3</bitOffset>
65620 <bitWidth>1</bitWidth>
65621 <access>read-write</access>
65622 </field>
65623 <field>
65624 <name>ITTXFE</name>
65625 <description>IN token received when TxFIFO is
65626 empty</description>
65627 <bitOffset>4</bitOffset>
65628 <bitWidth>1</bitWidth>
65629 <access>read-write</access>
65630 </field>
65631 <field>
65632 <name>INEPNE</name>
65633 <description>IN endpoint NAK effective</description>
65634 <bitOffset>6</bitOffset>
65635 <bitWidth>1</bitWidth>
65636 <access>read-write</access>
65637 </field>
65638 <field>
65639 <name>TXFE</name>
65640 <description>Transmit FIFO empty</description>
65641 <bitOffset>7</bitOffset>
65642 <bitWidth>1</bitWidth>
65643 <access>read-only</access>
65644 </field>
65645 <field>
65646 <name>TXFIFOUDRN</name>
65647 <description>Transmit Fifo Underrun</description>
65648 <bitOffset>8</bitOffset>
65649 <bitWidth>1</bitWidth>
65650 <access>read-write</access>
65651 </field>
65652 <field>
65653 <name>BNA</name>
65654 <description>Buffer not available
65655 interrupt</description>
65656 <bitOffset>9</bitOffset>
65657 <bitWidth>1</bitWidth>
65658 <access>read-write</access>
65659 </field>
65660 <field>
65661 <name>PKTDRPSTS</name>
65662 <description>Packet dropped status</description>
65663 <bitOffset>11</bitOffset>
65664 <bitWidth>1</bitWidth>
65665 <access>read-write</access>
65666 </field>
65667 <field>
65668 <name>BERR</name>
65669 <description>Babble error interrupt</description>
65670 <bitOffset>12</bitOffset>
65671 <bitWidth>1</bitWidth>
65672 <access>read-write</access>
65673 </field>
65674 <field>
65675 <name>NAK</name>
65676 <description>NAK interrupt</description>
65677 <bitOffset>13</bitOffset>
65678 <bitWidth>1</bitWidth>
65679 <access>read-write</access>
65680 </field>
65681 </fields>
65682 </register>
65683 <register>
65684 <name>OTG_HS_DIEPINT5</name>
65685 <displayName>OTG_HS_DIEPINT5</displayName>
65686 <description>OTG device endpoint-5 interrupt
65687 register</description>
65688 <addressOffset>0x1A8</addressOffset>
65689 <size>32</size>
65690 <resetValue>0x0</resetValue>
65691 <fields>
65692 <field>
65693 <name>XFRC</name>
65694 <description>Transfer completed
65695 interrupt</description>
65696 <bitOffset>0</bitOffset>
65697 <bitWidth>1</bitWidth>
65698 <access>read-write</access>
65699 </field>
65700 <field>
65701 <name>EPDISD</name>
65702 <description>Endpoint disabled
65703 interrupt</description>
65704 <bitOffset>1</bitOffset>
65705 <bitWidth>1</bitWidth>
65706 <access>read-write</access>
65707 </field>
65708 <field>
65709 <name>TOC</name>
65710 <description>Timeout condition</description>
65711 <bitOffset>3</bitOffset>
65712 <bitWidth>1</bitWidth>
65713 <access>read-write</access>
65714 </field>
65715 <field>
65716 <name>ITTXFE</name>
65717 <description>IN token received when TxFIFO is
65718 empty</description>
65719 <bitOffset>4</bitOffset>
65720 <bitWidth>1</bitWidth>
65721 <access>read-write</access>
65722 </field>
65723 <field>
65724 <name>INEPNE</name>
65725 <description>IN endpoint NAK effective</description>
65726 <bitOffset>6</bitOffset>
65727 <bitWidth>1</bitWidth>
65728 <access>read-write</access>
65729 </field>
65730 <field>
65731 <name>TXFE</name>
65732 <description>Transmit FIFO empty</description>
65733 <bitOffset>7</bitOffset>
65734 <bitWidth>1</bitWidth>
65735 <access>read-only</access>
65736 </field>
65737 <field>
65738 <name>TXFIFOUDRN</name>
65739 <description>Transmit Fifo Underrun</description>
65740 <bitOffset>8</bitOffset>
65741 <bitWidth>1</bitWidth>
65742 <access>read-write</access>
65743 </field>
65744 <field>
65745 <name>BNA</name>
65746 <description>Buffer not available
65747 interrupt</description>
65748 <bitOffset>9</bitOffset>
65749 <bitWidth>1</bitWidth>
65750 <access>read-write</access>
65751 </field>
65752 <field>
65753 <name>PKTDRPSTS</name>
65754 <description>Packet dropped status</description>
65755 <bitOffset>11</bitOffset>
65756 <bitWidth>1</bitWidth>
65757 <access>read-write</access>
65758 </field>
65759 <field>
65760 <name>BERR</name>
65761 <description>Babble error interrupt</description>
65762 <bitOffset>12</bitOffset>
65763 <bitWidth>1</bitWidth>
65764 <access>read-write</access>
65765 </field>
65766 <field>
65767 <name>NAK</name>
65768 <description>NAK interrupt</description>
65769 <bitOffset>13</bitOffset>
65770 <bitWidth>1</bitWidth>
65771 <access>read-write</access>
65772 </field>
65773 </fields>
65774 </register>
65775 <register>
65776 <name>OTG_HS_DIEPINT6</name>
65777 <displayName>OTG_HS_DIEPINT6</displayName>
65778 <description>OTG device endpoint-6 interrupt
65779 register</description>
65780 <addressOffset>0x1C8</addressOffset>
65781 <size>32</size>
65782 <resetValue>0x0</resetValue>
65783 <fields>
65784 <field>
65785 <name>XFRC</name>
65786 <description>Transfer completed
65787 interrupt</description>
65788 <bitOffset>0</bitOffset>
65789 <bitWidth>1</bitWidth>
65790 <access>read-write</access>
65791 </field>
65792 <field>
65793 <name>EPDISD</name>
65794 <description>Endpoint disabled
65795 interrupt</description>
65796 <bitOffset>1</bitOffset>
65797 <bitWidth>1</bitWidth>
65798 <access>read-write</access>
65799 </field>
65800 <field>
65801 <name>TOC</name>
65802 <description>Timeout condition</description>
65803 <bitOffset>3</bitOffset>
65804 <bitWidth>1</bitWidth>
65805 <access>read-write</access>
65806 </field>
65807 <field>
65808 <name>ITTXFE</name>
65809 <description>IN token received when TxFIFO is
65810 empty</description>
65811 <bitOffset>4</bitOffset>
65812 <bitWidth>1</bitWidth>
65813 <access>read-write</access>
65814 </field>
65815 <field>
65816 <name>INEPNE</name>
65817 <description>IN endpoint NAK effective</description>
65818 <bitOffset>6</bitOffset>
65819 <bitWidth>1</bitWidth>
65820 <access>read-write</access>
65821 </field>
65822 <field>
65823 <name>TXFE</name>
65824 <description>Transmit FIFO empty</description>
65825 <bitOffset>7</bitOffset>
65826 <bitWidth>1</bitWidth>
65827 <access>read-only</access>
65828 </field>
65829 <field>
65830 <name>TXFIFOUDRN</name>
65831 <description>Transmit Fifo Underrun</description>
65832 <bitOffset>8</bitOffset>
65833 <bitWidth>1</bitWidth>
65834 <access>read-write</access>
65835 </field>
65836 <field>
65837 <name>BNA</name>
65838 <description>Buffer not available
65839 interrupt</description>
65840 <bitOffset>9</bitOffset>
65841 <bitWidth>1</bitWidth>
65842 <access>read-write</access>
65843 </field>
65844 <field>
65845 <name>PKTDRPSTS</name>
65846 <description>Packet dropped status</description>
65847 <bitOffset>11</bitOffset>
65848 <bitWidth>1</bitWidth>
65849 <access>read-write</access>
65850 </field>
65851 <field>
65852 <name>BERR</name>
65853 <description>Babble error interrupt</description>
65854 <bitOffset>12</bitOffset>
65855 <bitWidth>1</bitWidth>
65856 <access>read-write</access>
65857 </field>
65858 <field>
65859 <name>NAK</name>
65860 <description>NAK interrupt</description>
65861 <bitOffset>13</bitOffset>
65862 <bitWidth>1</bitWidth>
65863 <access>read-write</access>
65864 </field>
65865 </fields>
65866 </register>
65867 <register>
65868 <name>OTG_HS_DIEPINT7</name>
65869 <displayName>OTG_HS_DIEPINT7</displayName>
65870 <description>OTG device endpoint-7 interrupt
65871 register</description>
65872 <addressOffset>0x1E8</addressOffset>
65873 <size>32</size>
65874 <resetValue>0x0</resetValue>
65875 <fields>
65876 <field>
65877 <name>XFRC</name>
65878 <description>Transfer completed
65879 interrupt</description>
65880 <bitOffset>0</bitOffset>
65881 <bitWidth>1</bitWidth>
65882 <access>read-write</access>
65883 </field>
65884 <field>
65885 <name>EPDISD</name>
65886 <description>Endpoint disabled
65887 interrupt</description>
65888 <bitOffset>1</bitOffset>
65889 <bitWidth>1</bitWidth>
65890 <access>read-write</access>
65891 </field>
65892 <field>
65893 <name>TOC</name>
65894 <description>Timeout condition</description>
65895 <bitOffset>3</bitOffset>
65896 <bitWidth>1</bitWidth>
65897 <access>read-write</access>
65898 </field>
65899 <field>
65900 <name>ITTXFE</name>
65901 <description>IN token received when TxFIFO is
65902 empty</description>
65903 <bitOffset>4</bitOffset>
65904 <bitWidth>1</bitWidth>
65905 <access>read-write</access>
65906 </field>
65907 <field>
65908 <name>INEPNE</name>
65909 <description>IN endpoint NAK effective</description>
65910 <bitOffset>6</bitOffset>
65911 <bitWidth>1</bitWidth>
65912 <access>read-write</access>
65913 </field>
65914 <field>
65915 <name>TXFE</name>
65916 <description>Transmit FIFO empty</description>
65917 <bitOffset>7</bitOffset>
65918 <bitWidth>1</bitWidth>
65919 <access>read-only</access>
65920 </field>
65921 <field>
65922 <name>TXFIFOUDRN</name>
65923 <description>Transmit Fifo Underrun</description>
65924 <bitOffset>8</bitOffset>
65925 <bitWidth>1</bitWidth>
65926 <access>read-write</access>
65927 </field>
65928 <field>
65929 <name>BNA</name>
65930 <description>Buffer not available
65931 interrupt</description>
65932 <bitOffset>9</bitOffset>
65933 <bitWidth>1</bitWidth>
65934 <access>read-write</access>
65935 </field>
65936 <field>
65937 <name>PKTDRPSTS</name>
65938 <description>Packet dropped status</description>
65939 <bitOffset>11</bitOffset>
65940 <bitWidth>1</bitWidth>
65941 <access>read-write</access>
65942 </field>
65943 <field>
65944 <name>BERR</name>
65945 <description>Babble error interrupt</description>
65946 <bitOffset>12</bitOffset>
65947 <bitWidth>1</bitWidth>
65948 <access>read-write</access>
65949 </field>
65950 <field>
65951 <name>NAK</name>
65952 <description>NAK interrupt</description>
65953 <bitOffset>13</bitOffset>
65954 <bitWidth>1</bitWidth>
65955 <access>read-write</access>
65956 </field>
65957 </fields>
65958 </register>
65959 <register>
65960 <name>OTG_HS_DIEPTSIZ0</name>
65961 <displayName>OTG_HS_DIEPTSIZ0</displayName>
65962 <description>OTG_HS device IN endpoint 0 transfer size
65963 register</description>
65964 <addressOffset>0x110</addressOffset>
65965 <size>32</size>
65966 <access>read-write</access>
65967 <resetValue>0x0</resetValue>
65968 <fields>
65969 <field>
65970 <name>XFRSIZ</name>
65971 <description>Transfer size</description>
65972 <bitOffset>0</bitOffset>
65973 <bitWidth>7</bitWidth>
65974 </field>
65975 <field>
65976 <name>PKTCNT</name>
65977 <description>Packet count</description>
65978 <bitOffset>19</bitOffset>
65979 <bitWidth>2</bitWidth>
65980 </field>
65981 </fields>
65982 </register>
65983 <register>
65984 <name>OTG_HS_DIEPDMA1</name>
65985 <displayName>OTG_HS_DIEPDMA1</displayName>
65986 <description>OTG_HS device endpoint-1 DMA address
65987 register</description>
65988 <addressOffset>0x114</addressOffset>
65989 <size>32</size>
65990 <access>read-write</access>
65991 <resetValue>0x0</resetValue>
65992 <fields>
65993 <field>
65994 <name>DMAADDR</name>
65995 <description>DMA address</description>
65996 <bitOffset>0</bitOffset>
65997 <bitWidth>32</bitWidth>
65998 </field>
65999 </fields>
66000 </register>
66001 <register>
66002 <name>OTG_HS_DIEPDMA2</name>
66003 <displayName>OTG_HS_DIEPDMA2</displayName>
66004 <description>OTG_HS device endpoint-2 DMA address
66005 register</description>
66006 <addressOffset>0x134</addressOffset>
66007 <size>32</size>
66008 <access>read-write</access>
66009 <resetValue>0x0</resetValue>
66010 <fields>
66011 <field>
66012 <name>DMAADDR</name>
66013 <description>DMA address</description>
66014 <bitOffset>0</bitOffset>
66015 <bitWidth>32</bitWidth>
66016 </field>
66017 </fields>
66018 </register>
66019 <register>
66020 <name>OTG_HS_DIEPDMA3</name>
66021 <displayName>OTG_HS_DIEPDMA3</displayName>
66022 <description>OTG_HS device endpoint-3 DMA address
66023 register</description>
66024 <addressOffset>0x154</addressOffset>
66025 <size>32</size>
66026 <access>read-write</access>
66027 <resetValue>0x0</resetValue>
66028 <fields>
66029 <field>
66030 <name>DMAADDR</name>
66031 <description>DMA address</description>
66032 <bitOffset>0</bitOffset>
66033 <bitWidth>32</bitWidth>
66034 </field>
66035 </fields>
66036 </register>
66037 <register>
66038 <name>OTG_HS_DIEPDMA4</name>
66039 <displayName>OTG_HS_DIEPDMA4</displayName>
66040 <description>OTG_HS device endpoint-4 DMA address
66041 register</description>
66042 <addressOffset>0x174</addressOffset>
66043 <size>32</size>
66044 <access>read-write</access>
66045 <resetValue>0x0</resetValue>
66046 <fields>
66047 <field>
66048 <name>DMAADDR</name>
66049 <description>DMA address</description>
66050 <bitOffset>0</bitOffset>
66051 <bitWidth>32</bitWidth>
66052 </field>
66053 </fields>
66054 </register>
66055 <register>
66056 <name>OTG_HS_DIEPDMA5</name>
66057 <displayName>OTG_HS_DIEPDMA5</displayName>
66058 <description>OTG_HS device endpoint-5 DMA address
66059 register</description>
66060 <addressOffset>0x194</addressOffset>
66061 <size>32</size>
66062 <access>read-write</access>
66063 <resetValue>0x0</resetValue>
66064 <fields>
66065 <field>
66066 <name>DMAADDR</name>
66067 <description>DMA address</description>
66068 <bitOffset>0</bitOffset>
66069 <bitWidth>32</bitWidth>
66070 </field>
66071 </fields>
66072 </register>
66073 <register>
66074 <name>OTG_HS_DTXFSTS0</name>
66075 <displayName>OTG_HS_DTXFSTS0</displayName>
66076 <description>OTG_HS device IN endpoint transmit FIFO
66077 status register</description>
66078 <addressOffset>0x118</addressOffset>
66079 <size>32</size>
66080 <access>read-only</access>
66081 <resetValue>0x0</resetValue>
66082 <fields>
66083 <field>
66084 <name>INEPTFSAV</name>
66085 <description>IN endpoint TxFIFO space
66086 avail</description>
66087 <bitOffset>0</bitOffset>
66088 <bitWidth>16</bitWidth>
66089 </field>
66090 </fields>
66091 </register>
66092 <register>
66093 <name>OTG_HS_DTXFSTS1</name>
66094 <displayName>OTG_HS_DTXFSTS1</displayName>
66095 <description>OTG_HS device IN endpoint transmit FIFO
66096 status register</description>
66097 <addressOffset>0x138</addressOffset>
66098 <size>32</size>
66099 <access>read-only</access>
66100 <resetValue>0x0</resetValue>
66101 <fields>
66102 <field>
66103 <name>INEPTFSAV</name>
66104 <description>IN endpoint TxFIFO space
66105 avail</description>
66106 <bitOffset>0</bitOffset>
66107 <bitWidth>16</bitWidth>
66108 </field>
66109 </fields>
66110 </register>
66111 <register>
66112 <name>OTG_HS_DTXFSTS2</name>
66113 <displayName>OTG_HS_DTXFSTS2</displayName>
66114 <description>OTG_HS device IN endpoint transmit FIFO
66115 status register</description>
66116 <addressOffset>0x158</addressOffset>
66117 <size>32</size>
66118 <access>read-only</access>
66119 <resetValue>0x0</resetValue>
66120 <fields>
66121 <field>
66122 <name>INEPTFSAV</name>
66123 <description>IN endpoint TxFIFO space
66124 avail</description>
66125 <bitOffset>0</bitOffset>
66126 <bitWidth>16</bitWidth>
66127 </field>
66128 </fields>
66129 </register>
66130 <register>
66131 <name>OTG_HS_DTXFSTS3</name>
66132 <displayName>OTG_HS_DTXFSTS3</displayName>
66133 <description>OTG_HS device IN endpoint transmit FIFO
66134 status register</description>
66135 <addressOffset>0x178</addressOffset>
66136 <size>32</size>
66137 <access>read-only</access>
66138 <resetValue>0x0</resetValue>
66139 <fields>
66140 <field>
66141 <name>INEPTFSAV</name>
66142 <description>IN endpoint TxFIFO space
66143 avail</description>
66144 <bitOffset>0</bitOffset>
66145 <bitWidth>16</bitWidth>
66146 </field>
66147 </fields>
66148 </register>
66149 <register>
66150 <name>OTG_HS_DTXFSTS4</name>
66151 <displayName>OTG_HS_DTXFSTS4</displayName>
66152 <description>OTG_HS device IN endpoint transmit FIFO
66153 status register</description>
66154 <addressOffset>0x198</addressOffset>
66155 <size>32</size>
66156 <access>read-only</access>
66157 <resetValue>0x0</resetValue>
66158 <fields>
66159 <field>
66160 <name>INEPTFSAV</name>
66161 <description>IN endpoint TxFIFO space
66162 avail</description>
66163 <bitOffset>0</bitOffset>
66164 <bitWidth>16</bitWidth>
66165 </field>
66166 </fields>
66167 </register>
66168 <register>
66169 <name>OTG_HS_DTXFSTS5</name>
66170 <displayName>OTG_HS_DTXFSTS5</displayName>
66171 <description>OTG_HS device IN endpoint transmit FIFO
66172 status register</description>
66173 <addressOffset>0x1B8</addressOffset>
66174 <size>32</size>
66175 <access>read-only</access>
66176 <resetValue>0x0</resetValue>
66177 <fields>
66178 <field>
66179 <name>INEPTFSAV</name>
66180 <description>IN endpoint TxFIFO space
66181 avail</description>
66182 <bitOffset>0</bitOffset>
66183 <bitWidth>16</bitWidth>
66184 </field>
66185 </fields>
66186 </register>
66187 <register>
66188 <name>OTG_HS_DIEPTSIZ1</name>
66189 <displayName>OTG_HS_DIEPTSIZ1</displayName>
66190 <description>OTG_HS device endpoint transfer size
66191 register</description>
66192 <addressOffset>0x130</addressOffset>
66193 <size>32</size>
66194 <access>read-write</access>
66195 <resetValue>0x0</resetValue>
66196 <fields>
66197 <field>
66198 <name>XFRSIZ</name>
66199 <description>Transfer size</description>
66200 <bitOffset>0</bitOffset>
66201 <bitWidth>19</bitWidth>
66202 </field>
66203 <field>
66204 <name>PKTCNT</name>
66205 <description>Packet count</description>
66206 <bitOffset>19</bitOffset>
66207 <bitWidth>10</bitWidth>
66208 </field>
66209 <field>
66210 <name>MCNT</name>
66211 <description>Multi count</description>
66212 <bitOffset>29</bitOffset>
66213 <bitWidth>2</bitWidth>
66214 </field>
66215 </fields>
66216 </register>
66217 <register>
66218 <name>OTG_HS_DIEPTSIZ2</name>
66219 <displayName>OTG_HS_DIEPTSIZ2</displayName>
66220 <description>OTG_HS device endpoint transfer size
66221 register</description>
66222 <addressOffset>0x150</addressOffset>
66223 <size>32</size>
66224 <access>read-write</access>
66225 <resetValue>0x0</resetValue>
66226 <fields>
66227 <field>
66228 <name>XFRSIZ</name>
66229 <description>Transfer size</description>
66230 <bitOffset>0</bitOffset>
66231 <bitWidth>19</bitWidth>
66232 </field>
66233 <field>
66234 <name>PKTCNT</name>
66235 <description>Packet count</description>
66236 <bitOffset>19</bitOffset>
66237 <bitWidth>10</bitWidth>
66238 </field>
66239 <field>
66240 <name>MCNT</name>
66241 <description>Multi count</description>
66242 <bitOffset>29</bitOffset>
66243 <bitWidth>2</bitWidth>
66244 </field>
66245 </fields>
66246 </register>
66247 <register>
66248 <name>OTG_HS_DIEPTSIZ3</name>
66249 <displayName>OTG_HS_DIEPTSIZ3</displayName>
66250 <description>OTG_HS device endpoint transfer size
66251 register</description>
66252 <addressOffset>0x170</addressOffset>
66253 <size>32</size>
66254 <access>read-write</access>
66255 <resetValue>0x0</resetValue>
66256 <fields>
66257 <field>
66258 <name>XFRSIZ</name>
66259 <description>Transfer size</description>
66260 <bitOffset>0</bitOffset>
66261 <bitWidth>19</bitWidth>
66262 </field>
66263 <field>
66264 <name>PKTCNT</name>
66265 <description>Packet count</description>
66266 <bitOffset>19</bitOffset>
66267 <bitWidth>10</bitWidth>
66268 </field>
66269 <field>
66270 <name>MCNT</name>
66271 <description>Multi count</description>
66272 <bitOffset>29</bitOffset>
66273 <bitWidth>2</bitWidth>
66274 </field>
66275 </fields>
66276 </register>
66277 <register>
66278 <name>OTG_HS_DIEPTSIZ4</name>
66279 <displayName>OTG_HS_DIEPTSIZ4</displayName>
66280 <description>OTG_HS device endpoint transfer size
66281 register</description>
66282 <addressOffset>0x190</addressOffset>
66283 <size>32</size>
66284 <access>read-write</access>
66285 <resetValue>0x0</resetValue>
66286 <fields>
66287 <field>
66288 <name>XFRSIZ</name>
66289 <description>Transfer size</description>
66290 <bitOffset>0</bitOffset>
66291 <bitWidth>19</bitWidth>
66292 </field>
66293 <field>
66294 <name>PKTCNT</name>
66295 <description>Packet count</description>
66296 <bitOffset>19</bitOffset>
66297 <bitWidth>10</bitWidth>
66298 </field>
66299 <field>
66300 <name>MCNT</name>
66301 <description>Multi count</description>
66302 <bitOffset>29</bitOffset>
66303 <bitWidth>2</bitWidth>
66304 </field>
66305 </fields>
66306 </register>
66307 <register>
66308 <name>OTG_HS_DIEPTSIZ5</name>
66309 <displayName>OTG_HS_DIEPTSIZ5</displayName>
66310 <description>OTG_HS device endpoint transfer size
66311 register</description>
66312 <addressOffset>0x1B0</addressOffset>
66313 <size>32</size>
66314 <access>read-write</access>
66315 <resetValue>0x0</resetValue>
66316 <fields>
66317 <field>
66318 <name>XFRSIZ</name>
66319 <description>Transfer size</description>
66320 <bitOffset>0</bitOffset>
66321 <bitWidth>19</bitWidth>
66322 </field>
66323 <field>
66324 <name>PKTCNT</name>
66325 <description>Packet count</description>
66326 <bitOffset>19</bitOffset>
66327 <bitWidth>10</bitWidth>
66328 </field>
66329 <field>
66330 <name>MCNT</name>
66331 <description>Multi count</description>
66332 <bitOffset>29</bitOffset>
66333 <bitWidth>2</bitWidth>
66334 </field>
66335 </fields>
66336 </register>
66337 <register>
66338 <name>OTG_HS_DOEPCTL0</name>
66339 <displayName>OTG_HS_DOEPCTL0</displayName>
66340 <description>OTG_HS device control OUT endpoint 0 control
66341 register</description>
66342 <addressOffset>0x300</addressOffset>
66343 <size>32</size>
66344 <resetValue>0x00008000</resetValue>
66345 <fields>
66346 <field>
66347 <name>MPSIZ</name>
66348 <description>Maximum packet size</description>
66349 <bitOffset>0</bitOffset>
66350 <bitWidth>2</bitWidth>
66351 <access>read-only</access>
66352 </field>
66353 <field>
66354 <name>USBAEP</name>
66355 <description>USB active endpoint</description>
66356 <bitOffset>15</bitOffset>
66357 <bitWidth>1</bitWidth>
66358 <access>read-only</access>
66359 </field>
66360 <field>
66361 <name>NAKSTS</name>
66362 <description>NAK status</description>
66363 <bitOffset>17</bitOffset>
66364 <bitWidth>1</bitWidth>
66365 <access>read-only</access>
66366 </field>
66367 <field>
66368 <name>EPTYP</name>
66369 <description>Endpoint type</description>
66370 <bitOffset>18</bitOffset>
66371 <bitWidth>2</bitWidth>
66372 <access>read-only</access>
66373 </field>
66374 <field>
66375 <name>SNPM</name>
66376 <description>Snoop mode</description>
66377 <bitOffset>20</bitOffset>
66378 <bitWidth>1</bitWidth>
66379 <access>read-write</access>
66380 </field>
66381 <field>
66382 <name>Stall</name>
66383 <description>STALL handshake</description>
66384 <bitOffset>21</bitOffset>
66385 <bitWidth>1</bitWidth>
66386 <access>read-write</access>
66387 </field>
66388 <field>
66389 <name>CNAK</name>
66390 <description>Clear NAK</description>
66391 <bitOffset>26</bitOffset>
66392 <bitWidth>1</bitWidth>
66393 <access>write-only</access>
66394 </field>
66395 <field>
66396 <name>SNAK</name>
66397 <description>Set NAK</description>
66398 <bitOffset>27</bitOffset>
66399 <bitWidth>1</bitWidth>
66400 <access>write-only</access>
66401 </field>
66402 <field>
66403 <name>EPDIS</name>
66404 <description>Endpoint disable</description>
66405 <bitOffset>30</bitOffset>
66406 <bitWidth>1</bitWidth>
66407 <access>read-only</access>
66408 </field>
66409 <field>
66410 <name>EPENA</name>
66411 <description>Endpoint enable</description>
66412 <bitOffset>31</bitOffset>
66413 <bitWidth>1</bitWidth>
66414 <access>write-only</access>
66415 </field>
66416 </fields>
66417 </register>
66418 <register>
66419 <name>OTG_HS_DOEPCTL1</name>
66420 <displayName>OTG_HS_DOEPCTL1</displayName>
66421 <description>OTG device endpoint-1 control
66422 register</description>
66423 <addressOffset>0x320</addressOffset>
66424 <size>32</size>
66425 <resetValue>0x0</resetValue>
66426 <fields>
66427 <field>
66428 <name>MPSIZ</name>
66429 <description>Maximum packet size</description>
66430 <bitOffset>0</bitOffset>
66431 <bitWidth>11</bitWidth>
66432 <access>read-write</access>
66433 </field>
66434 <field>
66435 <name>USBAEP</name>
66436 <description>USB active endpoint</description>
66437 <bitOffset>15</bitOffset>
66438 <bitWidth>1</bitWidth>
66439 <access>read-write</access>
66440 </field>
66441 <field>
66442 <name>EONUM_DPID</name>
66443 <description>Even odd frame/Endpoint data
66444 PID</description>
66445 <bitOffset>16</bitOffset>
66446 <bitWidth>1</bitWidth>
66447 <access>read-only</access>
66448 </field>
66449 <field>
66450 <name>NAKSTS</name>
66451 <description>NAK status</description>
66452 <bitOffset>17</bitOffset>
66453 <bitWidth>1</bitWidth>
66454 <access>read-only</access>
66455 </field>
66456 <field>
66457 <name>EPTYP</name>
66458 <description>Endpoint type</description>
66459 <bitOffset>18</bitOffset>
66460 <bitWidth>2</bitWidth>
66461 <access>read-write</access>
66462 </field>
66463 <field>
66464 <name>SNPM</name>
66465 <description>Snoop mode</description>
66466 <bitOffset>20</bitOffset>
66467 <bitWidth>1</bitWidth>
66468 <access>read-write</access>
66469 </field>
66470 <field>
66471 <name>Stall</name>
66472 <description>STALL handshake</description>
66473 <bitOffset>21</bitOffset>
66474 <bitWidth>1</bitWidth>
66475 <access>read-write</access>
66476 </field>
66477 <field>
66478 <name>CNAK</name>
66479 <description>Clear NAK</description>
66480 <bitOffset>26</bitOffset>
66481 <bitWidth>1</bitWidth>
66482 <access>write-only</access>
66483 </field>
66484 <field>
66485 <name>SNAK</name>
66486 <description>Set NAK</description>
66487 <bitOffset>27</bitOffset>
66488 <bitWidth>1</bitWidth>
66489 <access>write-only</access>
66490 </field>
66491 <field>
66492 <name>SD0PID_SEVNFRM</name>
66493 <description>Set DATA0 PID/Set even
66494 frame</description>
66495 <bitOffset>28</bitOffset>
66496 <bitWidth>1</bitWidth>
66497 <access>write-only</access>
66498 </field>
66499 <field>
66500 <name>SODDFRM</name>
66501 <description>Set odd frame</description>
66502 <bitOffset>29</bitOffset>
66503 <bitWidth>1</bitWidth>
66504 <access>write-only</access>
66505 </field>
66506 <field>
66507 <name>EPDIS</name>
66508 <description>Endpoint disable</description>
66509 <bitOffset>30</bitOffset>
66510 <bitWidth>1</bitWidth>
66511 <access>read-write</access>
66512 </field>
66513 <field>
66514 <name>EPENA</name>
66515 <description>Endpoint enable</description>
66516 <bitOffset>31</bitOffset>
66517 <bitWidth>1</bitWidth>
66518 <access>read-write</access>
66519 </field>
66520 </fields>
66521 </register>
66522 <register>
66523 <name>OTG_HS_DOEPCTL2</name>
66524 <displayName>OTG_HS_DOEPCTL2</displayName>
66525 <description>OTG device endpoint-2 control
66526 register</description>
66527 <addressOffset>0x340</addressOffset>
66528 <size>32</size>
66529 <resetValue>0x0</resetValue>
66530 <fields>
66531 <field>
66532 <name>MPSIZ</name>
66533 <description>Maximum packet size</description>
66534 <bitOffset>0</bitOffset>
66535 <bitWidth>11</bitWidth>
66536 <access>read-write</access>
66537 </field>
66538 <field>
66539 <name>USBAEP</name>
66540 <description>USB active endpoint</description>
66541 <bitOffset>15</bitOffset>
66542 <bitWidth>1</bitWidth>
66543 <access>read-write</access>
66544 </field>
66545 <field>
66546 <name>EONUM_DPID</name>
66547 <description>Even odd frame/Endpoint data
66548 PID</description>
66549 <bitOffset>16</bitOffset>
66550 <bitWidth>1</bitWidth>
66551 <access>read-only</access>
66552 </field>
66553 <field>
66554 <name>NAKSTS</name>
66555 <description>NAK status</description>
66556 <bitOffset>17</bitOffset>
66557 <bitWidth>1</bitWidth>
66558 <access>read-only</access>
66559 </field>
66560 <field>
66561 <name>EPTYP</name>
66562 <description>Endpoint type</description>
66563 <bitOffset>18</bitOffset>
66564 <bitWidth>2</bitWidth>
66565 <access>read-write</access>
66566 </field>
66567 <field>
66568 <name>SNPM</name>
66569 <description>Snoop mode</description>
66570 <bitOffset>20</bitOffset>
66571 <bitWidth>1</bitWidth>
66572 <access>read-write</access>
66573 </field>
66574 <field>
66575 <name>Stall</name>
66576 <description>STALL handshake</description>
66577 <bitOffset>21</bitOffset>
66578 <bitWidth>1</bitWidth>
66579 <access>read-write</access>
66580 </field>
66581 <field>
66582 <name>CNAK</name>
66583 <description>Clear NAK</description>
66584 <bitOffset>26</bitOffset>
66585 <bitWidth>1</bitWidth>
66586 <access>write-only</access>
66587 </field>
66588 <field>
66589 <name>SNAK</name>
66590 <description>Set NAK</description>
66591 <bitOffset>27</bitOffset>
66592 <bitWidth>1</bitWidth>
66593 <access>write-only</access>
66594 </field>
66595 <field>
66596 <name>SD0PID_SEVNFRM</name>
66597 <description>Set DATA0 PID/Set even
66598 frame</description>
66599 <bitOffset>28</bitOffset>
66600 <bitWidth>1</bitWidth>
66601 <access>write-only</access>
66602 </field>
66603 <field>
66604 <name>SODDFRM</name>
66605 <description>Set odd frame</description>
66606 <bitOffset>29</bitOffset>
66607 <bitWidth>1</bitWidth>
66608 <access>write-only</access>
66609 </field>
66610 <field>
66611 <name>EPDIS</name>
66612 <description>Endpoint disable</description>
66613 <bitOffset>30</bitOffset>
66614 <bitWidth>1</bitWidth>
66615 <access>read-write</access>
66616 </field>
66617 <field>
66618 <name>EPENA</name>
66619 <description>Endpoint enable</description>
66620 <bitOffset>31</bitOffset>
66621 <bitWidth>1</bitWidth>
66622 <access>read-write</access>
66623 </field>
66624 </fields>
66625 </register>
66626 <register>
66627 <name>OTG_HS_DOEPCTL3</name>
66628 <displayName>OTG_HS_DOEPCTL3</displayName>
66629 <description>OTG device endpoint-3 control
66630 register</description>
66631 <addressOffset>0x360</addressOffset>
66632 <size>32</size>
66633 <resetValue>0x0</resetValue>
66634 <fields>
66635 <field>
66636 <name>MPSIZ</name>
66637 <description>Maximum packet size</description>
66638 <bitOffset>0</bitOffset>
66639 <bitWidth>11</bitWidth>
66640 <access>read-write</access>
66641 </field>
66642 <field>
66643 <name>USBAEP</name>
66644 <description>USB active endpoint</description>
66645 <bitOffset>15</bitOffset>
66646 <bitWidth>1</bitWidth>
66647 <access>read-write</access>
66648 </field>
66649 <field>
66650 <name>EONUM_DPID</name>
66651 <description>Even odd frame/Endpoint data
66652 PID</description>
66653 <bitOffset>16</bitOffset>
66654 <bitWidth>1</bitWidth>
66655 <access>read-only</access>
66656 </field>
66657 <field>
66658 <name>NAKSTS</name>
66659 <description>NAK status</description>
66660 <bitOffset>17</bitOffset>
66661 <bitWidth>1</bitWidth>
66662 <access>read-only</access>
66663 </field>
66664 <field>
66665 <name>EPTYP</name>
66666 <description>Endpoint type</description>
66667 <bitOffset>18</bitOffset>
66668 <bitWidth>2</bitWidth>
66669 <access>read-write</access>
66670 </field>
66671 <field>
66672 <name>SNPM</name>
66673 <description>Snoop mode</description>
66674 <bitOffset>20</bitOffset>
66675 <bitWidth>1</bitWidth>
66676 <access>read-write</access>
66677 </field>
66678 <field>
66679 <name>Stall</name>
66680 <description>STALL handshake</description>
66681 <bitOffset>21</bitOffset>
66682 <bitWidth>1</bitWidth>
66683 <access>read-write</access>
66684 </field>
66685 <field>
66686 <name>CNAK</name>
66687 <description>Clear NAK</description>
66688 <bitOffset>26</bitOffset>
66689 <bitWidth>1</bitWidth>
66690 <access>write-only</access>
66691 </field>
66692 <field>
66693 <name>SNAK</name>
66694 <description>Set NAK</description>
66695 <bitOffset>27</bitOffset>
66696 <bitWidth>1</bitWidth>
66697 <access>write-only</access>
66698 </field>
66699 <field>
66700 <name>SD0PID_SEVNFRM</name>
66701 <description>Set DATA0 PID/Set even
66702 frame</description>
66703 <bitOffset>28</bitOffset>
66704 <bitWidth>1</bitWidth>
66705 <access>write-only</access>
66706 </field>
66707 <field>
66708 <name>SODDFRM</name>
66709 <description>Set odd frame</description>
66710 <bitOffset>29</bitOffset>
66711 <bitWidth>1</bitWidth>
66712 <access>write-only</access>
66713 </field>
66714 <field>
66715 <name>EPDIS</name>
66716 <description>Endpoint disable</description>
66717 <bitOffset>30</bitOffset>
66718 <bitWidth>1</bitWidth>
66719 <access>read-write</access>
66720 </field>
66721 <field>
66722 <name>EPENA</name>
66723 <description>Endpoint enable</description>
66724 <bitOffset>31</bitOffset>
66725 <bitWidth>1</bitWidth>
66726 <access>read-write</access>
66727 </field>
66728 </fields>
66729 </register>
66730 <register>
66731 <name>OTG_HS_DOEPINT0</name>
66732 <displayName>OTG_HS_DOEPINT0</displayName>
66733 <description>OTG_HS device endpoint-0 interrupt
66734 register</description>
66735 <addressOffset>0x308</addressOffset>
66736 <size>32</size>
66737 <access>read-write</access>
66738 <resetValue>0x00000080</resetValue>
66739 <fields>
66740 <field>
66741 <name>XFRC</name>
66742 <description>Transfer completed
66743 interrupt</description>
66744 <bitOffset>0</bitOffset>
66745 <bitWidth>1</bitWidth>
66746 </field>
66747 <field>
66748 <name>EPDISD</name>
66749 <description>Endpoint disabled
66750 interrupt</description>
66751 <bitOffset>1</bitOffset>
66752 <bitWidth>1</bitWidth>
66753 </field>
66754 <field>
66755 <name>STUP</name>
66756 <description>SETUP phase done</description>
66757 <bitOffset>3</bitOffset>
66758 <bitWidth>1</bitWidth>
66759 </field>
66760 <field>
66761 <name>OTEPDIS</name>
66762 <description>OUT token received when endpoint
66763 disabled</description>
66764 <bitOffset>4</bitOffset>
66765 <bitWidth>1</bitWidth>
66766 </field>
66767 <field>
66768 <name>B2BSTUP</name>
66769 <description>Back-to-back SETUP packets
66770 received</description>
66771 <bitOffset>6</bitOffset>
66772 <bitWidth>1</bitWidth>
66773 </field>
66774 <field>
66775 <name>NYET</name>
66776 <description>NYET interrupt</description>
66777 <bitOffset>14</bitOffset>
66778 <bitWidth>1</bitWidth>
66779 </field>
66780 </fields>
66781 </register>
66782 <register>
66783 <name>OTG_HS_DOEPINT1</name>
66784 <displayName>OTG_HS_DOEPINT1</displayName>
66785 <description>OTG_HS device endpoint-1 interrupt
66786 register</description>
66787 <addressOffset>0x328</addressOffset>
66788 <size>32</size>
66789 <access>read-write</access>
66790 <resetValue>0x0</resetValue>
66791 <fields>
66792 <field>
66793 <name>XFRC</name>
66794 <description>Transfer completed
66795 interrupt</description>
66796 <bitOffset>0</bitOffset>
66797 <bitWidth>1</bitWidth>
66798 </field>
66799 <field>
66800 <name>EPDISD</name>
66801 <description>Endpoint disabled
66802 interrupt</description>
66803 <bitOffset>1</bitOffset>
66804 <bitWidth>1</bitWidth>
66805 </field>
66806 <field>
66807 <name>STUP</name>
66808 <description>SETUP phase done</description>
66809 <bitOffset>3</bitOffset>
66810 <bitWidth>1</bitWidth>
66811 </field>
66812 <field>
66813 <name>OTEPDIS</name>
66814 <description>OUT token received when endpoint
66815 disabled</description>
66816 <bitOffset>4</bitOffset>
66817 <bitWidth>1</bitWidth>
66818 </field>
66819 <field>
66820 <name>B2BSTUP</name>
66821 <description>Back-to-back SETUP packets
66822 received</description>
66823 <bitOffset>6</bitOffset>
66824 <bitWidth>1</bitWidth>
66825 </field>
66826 <field>
66827 <name>NYET</name>
66828 <description>NYET interrupt</description>
66829 <bitOffset>14</bitOffset>
66830 <bitWidth>1</bitWidth>
66831 </field>
66832 </fields>
66833 </register>
66834 <register>
66835 <name>OTG_HS_DOEPINT2</name>
66836 <displayName>OTG_HS_DOEPINT2</displayName>
66837 <description>OTG_HS device endpoint-2 interrupt
66838 register</description>
66839 <addressOffset>0x348</addressOffset>
66840 <size>32</size>
66841 <access>read-write</access>
66842 <resetValue>0x0</resetValue>
66843 <fields>
66844 <field>
66845 <name>XFRC</name>
66846 <description>Transfer completed
66847 interrupt</description>
66848 <bitOffset>0</bitOffset>
66849 <bitWidth>1</bitWidth>
66850 </field>
66851 <field>
66852 <name>EPDISD</name>
66853 <description>Endpoint disabled
66854 interrupt</description>
66855 <bitOffset>1</bitOffset>
66856 <bitWidth>1</bitWidth>
66857 </field>
66858 <field>
66859 <name>STUP</name>
66860 <description>SETUP phase done</description>
66861 <bitOffset>3</bitOffset>
66862 <bitWidth>1</bitWidth>
66863 </field>
66864 <field>
66865 <name>OTEPDIS</name>
66866 <description>OUT token received when endpoint
66867 disabled</description>
66868 <bitOffset>4</bitOffset>
66869 <bitWidth>1</bitWidth>
66870 </field>
66871 <field>
66872 <name>B2BSTUP</name>
66873 <description>Back-to-back SETUP packets
66874 received</description>
66875 <bitOffset>6</bitOffset>
66876 <bitWidth>1</bitWidth>
66877 </field>
66878 <field>
66879 <name>NYET</name>
66880 <description>NYET interrupt</description>
66881 <bitOffset>14</bitOffset>
66882 <bitWidth>1</bitWidth>
66883 </field>
66884 </fields>
66885 </register>
66886 <register>
66887 <name>OTG_HS_DOEPINT3</name>
66888 <displayName>OTG_HS_DOEPINT3</displayName>
66889 <description>OTG_HS device endpoint-3 interrupt
66890 register</description>
66891 <addressOffset>0x368</addressOffset>
66892 <size>32</size>
66893 <access>read-write</access>
66894 <resetValue>0x0</resetValue>
66895 <fields>
66896 <field>
66897 <name>XFRC</name>
66898 <description>Transfer completed
66899 interrupt</description>
66900 <bitOffset>0</bitOffset>
66901 <bitWidth>1</bitWidth>
66902 </field>
66903 <field>
66904 <name>EPDISD</name>
66905 <description>Endpoint disabled
66906 interrupt</description>
66907 <bitOffset>1</bitOffset>
66908 <bitWidth>1</bitWidth>
66909 </field>
66910 <field>
66911 <name>STUP</name>
66912 <description>SETUP phase done</description>
66913 <bitOffset>3</bitOffset>
66914 <bitWidth>1</bitWidth>
66915 </field>
66916 <field>
66917 <name>OTEPDIS</name>
66918 <description>OUT token received when endpoint
66919 disabled</description>
66920 <bitOffset>4</bitOffset>
66921 <bitWidth>1</bitWidth>
66922 </field>
66923 <field>
66924 <name>B2BSTUP</name>
66925 <description>Back-to-back SETUP packets
66926 received</description>
66927 <bitOffset>6</bitOffset>
66928 <bitWidth>1</bitWidth>
66929 </field>
66930 <field>
66931 <name>NYET</name>
66932 <description>NYET interrupt</description>
66933 <bitOffset>14</bitOffset>
66934 <bitWidth>1</bitWidth>
66935 </field>
66936 </fields>
66937 </register>
66938 <register>
66939 <name>OTG_HS_DOEPINT4</name>
66940 <displayName>OTG_HS_DOEPINT4</displayName>
66941 <description>OTG_HS device endpoint-4 interrupt
66942 register</description>
66943 <addressOffset>0x388</addressOffset>
66944 <size>32</size>
66945 <access>read-write</access>
66946 <resetValue>0x0</resetValue>
66947 <fields>
66948 <field>
66949 <name>XFRC</name>
66950 <description>Transfer completed
66951 interrupt</description>
66952 <bitOffset>0</bitOffset>
66953 <bitWidth>1</bitWidth>
66954 </field>
66955 <field>
66956 <name>EPDISD</name>
66957 <description>Endpoint disabled
66958 interrupt</description>
66959 <bitOffset>1</bitOffset>
66960 <bitWidth>1</bitWidth>
66961 </field>
66962 <field>
66963 <name>STUP</name>
66964 <description>SETUP phase done</description>
66965 <bitOffset>3</bitOffset>
66966 <bitWidth>1</bitWidth>
66967 </field>
66968 <field>
66969 <name>OTEPDIS</name>
66970 <description>OUT token received when endpoint
66971 disabled</description>
66972 <bitOffset>4</bitOffset>
66973 <bitWidth>1</bitWidth>
66974 </field>
66975 <field>
66976 <name>B2BSTUP</name>
66977 <description>Back-to-back SETUP packets
66978 received</description>
66979 <bitOffset>6</bitOffset>
66980 <bitWidth>1</bitWidth>
66981 </field>
66982 <field>
66983 <name>NYET</name>
66984 <description>NYET interrupt</description>
66985 <bitOffset>14</bitOffset>
66986 <bitWidth>1</bitWidth>
66987 </field>
66988 </fields>
66989 </register>
66990 <register>
66991 <name>OTG_HS_DOEPINT5</name>
66992 <displayName>OTG_HS_DOEPINT5</displayName>
66993 <description>OTG_HS device endpoint-5 interrupt
66994 register</description>
66995 <addressOffset>0x3A8</addressOffset>
66996 <size>32</size>
66997 <access>read-write</access>
66998 <resetValue>0x0</resetValue>
66999 <fields>
67000 <field>
67001 <name>XFRC</name>
67002 <description>Transfer completed
67003 interrupt</description>
67004 <bitOffset>0</bitOffset>
67005 <bitWidth>1</bitWidth>
67006 </field>
67007 <field>
67008 <name>EPDISD</name>
67009 <description>Endpoint disabled
67010 interrupt</description>
67011 <bitOffset>1</bitOffset>
67012 <bitWidth>1</bitWidth>
67013 </field>
67014 <field>
67015 <name>STUP</name>
67016 <description>SETUP phase done</description>
67017 <bitOffset>3</bitOffset>
67018 <bitWidth>1</bitWidth>
67019 </field>
67020 <field>
67021 <name>OTEPDIS</name>
67022 <description>OUT token received when endpoint
67023 disabled</description>
67024 <bitOffset>4</bitOffset>
67025 <bitWidth>1</bitWidth>
67026 </field>
67027 <field>
67028 <name>B2BSTUP</name>
67029 <description>Back-to-back SETUP packets
67030 received</description>
67031 <bitOffset>6</bitOffset>
67032 <bitWidth>1</bitWidth>
67033 </field>
67034 <field>
67035 <name>NYET</name>
67036 <description>NYET interrupt</description>
67037 <bitOffset>14</bitOffset>
67038 <bitWidth>1</bitWidth>
67039 </field>
67040 </fields>
67041 </register>
67042 <register>
67043 <name>OTG_HS_DOEPINT6</name>
67044 <displayName>OTG_HS_DOEPINT6</displayName>
67045 <description>OTG_HS device endpoint-6 interrupt
67046 register</description>
67047 <addressOffset>0x3C8</addressOffset>
67048 <size>32</size>
67049 <access>read-write</access>
67050 <resetValue>0x0</resetValue>
67051 <fields>
67052 <field>
67053 <name>XFRC</name>
67054 <description>Transfer completed
67055 interrupt</description>
67056 <bitOffset>0</bitOffset>
67057 <bitWidth>1</bitWidth>
67058 </field>
67059 <field>
67060 <name>EPDISD</name>
67061 <description>Endpoint disabled
67062 interrupt</description>
67063 <bitOffset>1</bitOffset>
67064 <bitWidth>1</bitWidth>
67065 </field>
67066 <field>
67067 <name>STUP</name>
67068 <description>SETUP phase done</description>
67069 <bitOffset>3</bitOffset>
67070 <bitWidth>1</bitWidth>
67071 </field>
67072 <field>
67073 <name>OTEPDIS</name>
67074 <description>OUT token received when endpoint
67075 disabled</description>
67076 <bitOffset>4</bitOffset>
67077 <bitWidth>1</bitWidth>
67078 </field>
67079 <field>
67080 <name>B2BSTUP</name>
67081 <description>Back-to-back SETUP packets
67082 received</description>
67083 <bitOffset>6</bitOffset>
67084 <bitWidth>1</bitWidth>
67085 </field>
67086 <field>
67087 <name>NYET</name>
67088 <description>NYET interrupt</description>
67089 <bitOffset>14</bitOffset>
67090 <bitWidth>1</bitWidth>
67091 </field>
67092 </fields>
67093 </register>
67094 <register>
67095 <name>OTG_HS_DOEPINT7</name>
67096 <displayName>OTG_HS_DOEPINT7</displayName>
67097 <description>OTG_HS device endpoint-7 interrupt
67098 register</description>
67099 <addressOffset>0x3E8</addressOffset>
67100 <size>32</size>
67101 <access>read-write</access>
67102 <resetValue>0x0</resetValue>
67103 <fields>
67104 <field>
67105 <name>XFRC</name>
67106 <description>Transfer completed
67107 interrupt</description>
67108 <bitOffset>0</bitOffset>
67109 <bitWidth>1</bitWidth>
67110 </field>
67111 <field>
67112 <name>EPDISD</name>
67113 <description>Endpoint disabled
67114 interrupt</description>
67115 <bitOffset>1</bitOffset>
67116 <bitWidth>1</bitWidth>
67117 </field>
67118 <field>
67119 <name>STUP</name>
67120 <description>SETUP phase done</description>
67121 <bitOffset>3</bitOffset>
67122 <bitWidth>1</bitWidth>
67123 </field>
67124 <field>
67125 <name>OTEPDIS</name>
67126 <description>OUT token received when endpoint
67127 disabled</description>
67128 <bitOffset>4</bitOffset>
67129 <bitWidth>1</bitWidth>
67130 </field>
67131 <field>
67132 <name>B2BSTUP</name>
67133 <description>Back-to-back SETUP packets
67134 received</description>
67135 <bitOffset>6</bitOffset>
67136 <bitWidth>1</bitWidth>
67137 </field>
67138 <field>
67139 <name>NYET</name>
67140 <description>NYET interrupt</description>
67141 <bitOffset>14</bitOffset>
67142 <bitWidth>1</bitWidth>
67143 </field>
67144 </fields>
67145 </register>
67146 <register>
67147 <name>OTG_HS_DOEPTSIZ0</name>
67148 <displayName>OTG_HS_DOEPTSIZ0</displayName>
67149 <description>OTG_HS device endpoint-0 transfer size
67150 register</description>
67151 <addressOffset>0x310</addressOffset>
67152 <size>32</size>
67153 <access>read-write</access>
67154 <resetValue>0x0</resetValue>
67155 <fields>
67156 <field>
67157 <name>XFRSIZ</name>
67158 <description>Transfer size</description>
67159 <bitOffset>0</bitOffset>
67160 <bitWidth>7</bitWidth>
67161 </field>
67162 <field>
67163 <name>PKTCNT</name>
67164 <description>Packet count</description>
67165 <bitOffset>19</bitOffset>
67166 <bitWidth>1</bitWidth>
67167 </field>
67168 <field>
67169 <name>STUPCNT</name>
67170 <description>SETUP packet count</description>
67171 <bitOffset>29</bitOffset>
67172 <bitWidth>2</bitWidth>
67173 </field>
67174 </fields>
67175 </register>
67176 <register>
67177 <name>OTG_HS_DOEPTSIZ1</name>
67178 <displayName>OTG_HS_DOEPTSIZ1</displayName>
67179 <description>OTG_HS device endpoint-1 transfer size
67180 register</description>
67181 <addressOffset>0x330</addressOffset>
67182 <size>32</size>
67183 <access>read-write</access>
67184 <resetValue>0x0</resetValue>
67185 <fields>
67186 <field>
67187 <name>XFRSIZ</name>
67188 <description>Transfer size</description>
67189 <bitOffset>0</bitOffset>
67190 <bitWidth>19</bitWidth>
67191 </field>
67192 <field>
67193 <name>PKTCNT</name>
67194 <description>Packet count</description>
67195 <bitOffset>19</bitOffset>
67196 <bitWidth>10</bitWidth>
67197 </field>
67198 <field>
67199 <name>RXDPID_STUPCNT</name>
67200 <description>Received data PID/SETUP packet
67201 count</description>
67202 <bitOffset>29</bitOffset>
67203 <bitWidth>2</bitWidth>
67204 </field>
67205 </fields>
67206 </register>
67207 <register>
67208 <name>OTG_HS_DOEPTSIZ2</name>
67209 <displayName>OTG_HS_DOEPTSIZ2</displayName>
67210 <description>OTG_HS device endpoint-2 transfer size
67211 register</description>
67212 <addressOffset>0x350</addressOffset>
67213 <size>32</size>
67214 <access>read-write</access>
67215 <resetValue>0x0</resetValue>
67216 <fields>
67217 <field>
67218 <name>XFRSIZ</name>
67219 <description>Transfer size</description>
67220 <bitOffset>0</bitOffset>
67221 <bitWidth>19</bitWidth>
67222 </field>
67223 <field>
67224 <name>PKTCNT</name>
67225 <description>Packet count</description>
67226 <bitOffset>19</bitOffset>
67227 <bitWidth>10</bitWidth>
67228 </field>
67229 <field>
67230 <name>RXDPID_STUPCNT</name>
67231 <description>Received data PID/SETUP packet
67232 count</description>
67233 <bitOffset>29</bitOffset>
67234 <bitWidth>2</bitWidth>
67235 </field>
67236 </fields>
67237 </register>
67238 <register>
67239 <name>OTG_HS_DOEPTSIZ3</name>
67240 <displayName>OTG_HS_DOEPTSIZ3</displayName>
67241 <description>OTG_HS device endpoint-3 transfer size
67242 register</description>
67243 <addressOffset>0x370</addressOffset>
67244 <size>32</size>
67245 <access>read-write</access>
67246 <resetValue>0x0</resetValue>
67247 <fields>
67248 <field>
67249 <name>XFRSIZ</name>
67250 <description>Transfer size</description>
67251 <bitOffset>0</bitOffset>
67252 <bitWidth>19</bitWidth>
67253 </field>
67254 <field>
67255 <name>PKTCNT</name>
67256 <description>Packet count</description>
67257 <bitOffset>19</bitOffset>
67258 <bitWidth>10</bitWidth>
67259 </field>
67260 <field>
67261 <name>RXDPID_STUPCNT</name>
67262 <description>Received data PID/SETUP packet
67263 count</description>
67264 <bitOffset>29</bitOffset>
67265 <bitWidth>2</bitWidth>
67266 </field>
67267 </fields>
67268 </register>
67269 <register>
67270 <name>OTG_HS_DOEPTSIZ4</name>
67271 <displayName>OTG_HS_DOEPTSIZ4</displayName>
67272 <description>OTG_HS device endpoint-4 transfer size
67273 register</description>
67274 <addressOffset>0x390</addressOffset>
67275 <size>32</size>
67276 <access>read-write</access>
67277 <resetValue>0x0</resetValue>
67278 <fields>
67279 <field>
67280 <name>XFRSIZ</name>
67281 <description>Transfer size</description>
67282 <bitOffset>0</bitOffset>
67283 <bitWidth>19</bitWidth>
67284 </field>
67285 <field>
67286 <name>PKTCNT</name>
67287 <description>Packet count</description>
67288 <bitOffset>19</bitOffset>
67289 <bitWidth>10</bitWidth>
67290 </field>
67291 <field>
67292 <name>RXDPID_STUPCNT</name>
67293 <description>Received data PID/SETUP packet
67294 count</description>
67295 <bitOffset>29</bitOffset>
67296 <bitWidth>2</bitWidth>
67297 </field>
67298 </fields>
67299 </register>
67300 <register>
67301 <name>OTG_HS_DIEPTSIZ6</name>
67302 <displayName>OTG_HS_DIEPTSIZ6</displayName>
67303 <description>OTG_HS device endpoint transfer size
67304 register</description>
67305 <alternateRegister>OTG_HS_DIEPCTL5</alternateRegister>
67306 <addressOffset>0x1A0</addressOffset>
67307 <size>32</size>
67308 <access>read-write</access>
67309 <resetValue>0x0</resetValue>
67310 <fields>
67311 <field>
67312 <name>XFRSIZ</name>
67313 <description>Transfer size</description>
67314 <bitOffset>0</bitOffset>
67315 <bitWidth>19</bitWidth>
67316 </field>
67317 <field>
67318 <name>PKTCNT</name>
67319 <description>Packet count</description>
67320 <bitOffset>19</bitOffset>
67321 <bitWidth>10</bitWidth>
67322 </field>
67323 <field>
67324 <name>MCNT</name>
67325 <description>Multi count</description>
67326 <bitOffset>29</bitOffset>
67327 <bitWidth>2</bitWidth>
67328 </field>
67329 </fields>
67330 </register>
67331 <register>
67332 <name>OTG_HS_DTXFSTS6</name>
67333 <displayName>OTG_HS_DTXFSTS6</displayName>
67334 <description>OTG_HS device IN endpoint transmit FIFO
67335 status register</description>
67336 <addressOffset>0x1A4</addressOffset>
67337 <size>32</size>
67338 <access>read-write</access>
67339 <resetValue>0x0</resetValue>
67340 <fields>
67341 <field>
67342 <name>INEPTFSAV</name>
67343 <description>IN endpoint TxFIFO space
67344 avail</description>
67345 <bitOffset>0</bitOffset>
67346 <bitWidth>16</bitWidth>
67347 </field>
67348 </fields>
67349 </register>
67350 <register>
67351 <name>OTG_HS_DIEPTSIZ7</name>
67352 <displayName>OTG_HS_DIEPTSIZ7</displayName>
67353 <description>OTG_HS device endpoint transfer size
67354 register</description>
67355 <alternateRegister>OTG_HS_DIEPINT5</alternateRegister>
67356 <addressOffset>0x1A8</addressOffset>
67357 <size>32</size>
67358 <access>read-write</access>
67359 <resetValue>0x0</resetValue>
67360 <fields>
67361 <field>
67362 <name>XFRSIZ</name>
67363 <description>Transfer size</description>
67364 <bitOffset>0</bitOffset>
67365 <bitWidth>19</bitWidth>
67366 </field>
67367 <field>
67368 <name>PKTCNT</name>
67369 <description>Packet count</description>
67370 <bitOffset>19</bitOffset>
67371 <bitWidth>10</bitWidth>
67372 </field>
67373 <field>
67374 <name>MCNT</name>
67375 <description>Multi count</description>
67376 <bitOffset>29</bitOffset>
67377 <bitWidth>2</bitWidth>
67378 </field>
67379 </fields>
67380 </register>
67381 <register>
67382 <name>OTG_HS_DTXFSTS7</name>
67383 <displayName>OTG_HS_DTXFSTS7</displayName>
67384 <description>OTG_HS device IN endpoint transmit FIFO
67385 status register</description>
67386 <addressOffset>0x1AC</addressOffset>
67387 <size>32</size>
67388 <access>read-write</access>
67389 <resetValue>0x0</resetValue>
67390 <fields>
67391 <field>
67392 <name>INEPTFSAV</name>
67393 <description>IN endpoint TxFIFO space
67394 avail</description>
67395 <bitOffset>0</bitOffset>
67396 <bitWidth>16</bitWidth>
67397 </field>
67398 </fields>
67399 </register>
67400 <register>
67401 <name>OTG_HS_DOEPCTL4</name>
67402 <displayName>OTG_HS_DOEPCTL4</displayName>
67403 <description>OTG device endpoint-4 control
67404 register</description>
67405 <addressOffset>0x380</addressOffset>
67406 <size>32</size>
67407 <resetValue>0x0</resetValue>
67408 <fields>
67409 <field>
67410 <name>MPSIZ</name>
67411 <description>Maximum packet size</description>
67412 <bitOffset>0</bitOffset>
67413 <bitWidth>11</bitWidth>
67414 <access>read-write</access>
67415 </field>
67416 <field>
67417 <name>USBAEP</name>
67418 <description>USB active endpoint</description>
67419 <bitOffset>15</bitOffset>
67420 <bitWidth>1</bitWidth>
67421 <access>read-write</access>
67422 </field>
67423 <field>
67424 <name>EONUM_DPID</name>
67425 <description>Even odd frame/Endpoint data
67426 PID</description>
67427 <bitOffset>16</bitOffset>
67428 <bitWidth>1</bitWidth>
67429 <access>read-only</access>
67430 </field>
67431 <field>
67432 <name>NAKSTS</name>
67433 <description>NAK status</description>
67434 <bitOffset>17</bitOffset>
67435 <bitWidth>1</bitWidth>
67436 <access>read-only</access>
67437 </field>
67438 <field>
67439 <name>EPTYP</name>
67440 <description>Endpoint type</description>
67441 <bitOffset>18</bitOffset>
67442 <bitWidth>2</bitWidth>
67443 <access>read-write</access>
67444 </field>
67445 <field>
67446 <name>SNPM</name>
67447 <description>Snoop mode</description>
67448 <bitOffset>20</bitOffset>
67449 <bitWidth>1</bitWidth>
67450 <access>read-write</access>
67451 </field>
67452 <field>
67453 <name>Stall</name>
67454 <description>STALL handshake</description>
67455 <bitOffset>21</bitOffset>
67456 <bitWidth>1</bitWidth>
67457 <access>read-write</access>
67458 </field>
67459 <field>
67460 <name>CNAK</name>
67461 <description>Clear NAK</description>
67462 <bitOffset>26</bitOffset>
67463 <bitWidth>1</bitWidth>
67464 <access>write-only</access>
67465 </field>
67466 <field>
67467 <name>SNAK</name>
67468 <description>Set NAK</description>
67469 <bitOffset>27</bitOffset>
67470 <bitWidth>1</bitWidth>
67471 <access>write-only</access>
67472 </field>
67473 <field>
67474 <name>SD0PID_SEVNFRM</name>
67475 <description>Set DATA0 PID/Set even
67476 frame</description>
67477 <bitOffset>28</bitOffset>
67478 <bitWidth>1</bitWidth>
67479 <access>write-only</access>
67480 </field>
67481 <field>
67482 <name>SODDFRM</name>
67483 <description>Set odd frame</description>
67484 <bitOffset>29</bitOffset>
67485 <bitWidth>1</bitWidth>
67486 <access>write-only</access>
67487 </field>
67488 <field>
67489 <name>EPDIS</name>
67490 <description>Endpoint disable</description>
67491 <bitOffset>30</bitOffset>
67492 <bitWidth>1</bitWidth>
67493 <access>read-write</access>
67494 </field>
67495 <field>
67496 <name>EPENA</name>
67497 <description>Endpoint enable</description>
67498 <bitOffset>31</bitOffset>
67499 <bitWidth>1</bitWidth>
67500 <access>read-write</access>
67501 </field>
67502 </fields>
67503 </register>
67504 <register>
67505 <name>OTG_HS_DOEPCTL5</name>
67506 <displayName>OTG_HS_DOEPCTL5</displayName>
67507 <description>OTG device endpoint-5 control
67508 register</description>
67509 <addressOffset>0x3A0</addressOffset>
67510 <size>32</size>
67511 <resetValue>0x0</resetValue>
67512 <fields>
67513 <field>
67514 <name>MPSIZ</name>
67515 <description>Maximum packet size</description>
67516 <bitOffset>0</bitOffset>
67517 <bitWidth>11</bitWidth>
67518 <access>read-write</access>
67519 </field>
67520 <field>
67521 <name>USBAEP</name>
67522 <description>USB active endpoint</description>
67523 <bitOffset>15</bitOffset>
67524 <bitWidth>1</bitWidth>
67525 <access>read-write</access>
67526 </field>
67527 <field>
67528 <name>EONUM_DPID</name>
67529 <description>Even odd frame/Endpoint data
67530 PID</description>
67531 <bitOffset>16</bitOffset>
67532 <bitWidth>1</bitWidth>
67533 <access>read-only</access>
67534 </field>
67535 <field>
67536 <name>NAKSTS</name>
67537 <description>NAK status</description>
67538 <bitOffset>17</bitOffset>
67539 <bitWidth>1</bitWidth>
67540 <access>read-only</access>
67541 </field>
67542 <field>
67543 <name>EPTYP</name>
67544 <description>Endpoint type</description>
67545 <bitOffset>18</bitOffset>
67546 <bitWidth>2</bitWidth>
67547 <access>read-write</access>
67548 </field>
67549 <field>
67550 <name>SNPM</name>
67551 <description>Snoop mode</description>
67552 <bitOffset>20</bitOffset>
67553 <bitWidth>1</bitWidth>
67554 <access>read-write</access>
67555 </field>
67556 <field>
67557 <name>Stall</name>
67558 <description>STALL handshake</description>
67559 <bitOffset>21</bitOffset>
67560 <bitWidth>1</bitWidth>
67561 <access>read-write</access>
67562 </field>
67563 <field>
67564 <name>CNAK</name>
67565 <description>Clear NAK</description>
67566 <bitOffset>26</bitOffset>
67567 <bitWidth>1</bitWidth>
67568 <access>write-only</access>
67569 </field>
67570 <field>
67571 <name>SNAK</name>
67572 <description>Set NAK</description>
67573 <bitOffset>27</bitOffset>
67574 <bitWidth>1</bitWidth>
67575 <access>write-only</access>
67576 </field>
67577 <field>
67578 <name>SD0PID_SEVNFRM</name>
67579 <description>Set DATA0 PID/Set even
67580 frame</description>
67581 <bitOffset>28</bitOffset>
67582 <bitWidth>1</bitWidth>
67583 <access>write-only</access>
67584 </field>
67585 <field>
67586 <name>SODDFRM</name>
67587 <description>Set odd frame</description>
67588 <bitOffset>29</bitOffset>
67589 <bitWidth>1</bitWidth>
67590 <access>write-only</access>
67591 </field>
67592 <field>
67593 <name>EPDIS</name>
67594 <description>Endpoint disable</description>
67595 <bitOffset>30</bitOffset>
67596 <bitWidth>1</bitWidth>
67597 <access>read-write</access>
67598 </field>
67599 <field>
67600 <name>EPENA</name>
67601 <description>Endpoint enable</description>
67602 <bitOffset>31</bitOffset>
67603 <bitWidth>1</bitWidth>
67604 <access>read-write</access>
67605 </field>
67606 </fields>
67607 </register>
67608 <register>
67609 <name>OTG_HS_DOEPCTL6</name>
67610 <displayName>OTG_HS_DOEPCTL6</displayName>
67611 <description>OTG device endpoint-6 control
67612 register</description>
67613 <addressOffset>0x3C0</addressOffset>
67614 <size>32</size>
67615 <resetValue>0x0</resetValue>
67616 <fields>
67617 <field>
67618 <name>MPSIZ</name>
67619 <description>Maximum packet size</description>
67620 <bitOffset>0</bitOffset>
67621 <bitWidth>11</bitWidth>
67622 <access>read-write</access>
67623 </field>
67624 <field>
67625 <name>USBAEP</name>
67626 <description>USB active endpoint</description>
67627 <bitOffset>15</bitOffset>
67628 <bitWidth>1</bitWidth>
67629 <access>read-write</access>
67630 </field>
67631 <field>
67632 <name>EONUM_DPID</name>
67633 <description>Even odd frame/Endpoint data
67634 PID</description>
67635 <bitOffset>16</bitOffset>
67636 <bitWidth>1</bitWidth>
67637 <access>read-only</access>
67638 </field>
67639 <field>
67640 <name>NAKSTS</name>
67641 <description>NAK status</description>
67642 <bitOffset>17</bitOffset>
67643 <bitWidth>1</bitWidth>
67644 <access>read-only</access>
67645 </field>
67646 <field>
67647 <name>EPTYP</name>
67648 <description>Endpoint type</description>
67649 <bitOffset>18</bitOffset>
67650 <bitWidth>2</bitWidth>
67651 <access>read-write</access>
67652 </field>
67653 <field>
67654 <name>SNPM</name>
67655 <description>Snoop mode</description>
67656 <bitOffset>20</bitOffset>
67657 <bitWidth>1</bitWidth>
67658 <access>read-write</access>
67659 </field>
67660 <field>
67661 <name>Stall</name>
67662 <description>STALL handshake</description>
67663 <bitOffset>21</bitOffset>
67664 <bitWidth>1</bitWidth>
67665 <access>read-write</access>
67666 </field>
67667 <field>
67668 <name>CNAK</name>
67669 <description>Clear NAK</description>
67670 <bitOffset>26</bitOffset>
67671 <bitWidth>1</bitWidth>
67672 <access>write-only</access>
67673 </field>
67674 <field>
67675 <name>SNAK</name>
67676 <description>Set NAK</description>
67677 <bitOffset>27</bitOffset>
67678 <bitWidth>1</bitWidth>
67679 <access>write-only</access>
67680 </field>
67681 <field>
67682 <name>SD0PID_SEVNFRM</name>
67683 <description>Set DATA0 PID/Set even
67684 frame</description>
67685 <bitOffset>28</bitOffset>
67686 <bitWidth>1</bitWidth>
67687 <access>write-only</access>
67688 </field>
67689 <field>
67690 <name>SODDFRM</name>
67691 <description>Set odd frame</description>
67692 <bitOffset>29</bitOffset>
67693 <bitWidth>1</bitWidth>
67694 <access>write-only</access>
67695 </field>
67696 <field>
67697 <name>EPDIS</name>
67698 <description>Endpoint disable</description>
67699 <bitOffset>30</bitOffset>
67700 <bitWidth>1</bitWidth>
67701 <access>read-write</access>
67702 </field>
67703 <field>
67704 <name>EPENA</name>
67705 <description>Endpoint enable</description>
67706 <bitOffset>31</bitOffset>
67707 <bitWidth>1</bitWidth>
67708 <access>read-write</access>
67709 </field>
67710 </fields>
67711 </register>
67712 <register>
67713 <name>OTG_HS_DOEPCTL7</name>
67714 <displayName>OTG_HS_DOEPCTL7</displayName>
67715 <description>OTG device endpoint-7 control
67716 register</description>
67717 <addressOffset>0x3E0</addressOffset>
67718 <size>32</size>
67719 <resetValue>0x0</resetValue>
67720 <fields>
67721 <field>
67722 <name>MPSIZ</name>
67723 <description>Maximum packet size</description>
67724 <bitOffset>0</bitOffset>
67725 <bitWidth>11</bitWidth>
67726 <access>read-write</access>
67727 </field>
67728 <field>
67729 <name>USBAEP</name>
67730 <description>USB active endpoint</description>
67731 <bitOffset>15</bitOffset>
67732 <bitWidth>1</bitWidth>
67733 <access>read-write</access>
67734 </field>
67735 <field>
67736 <name>EONUM_DPID</name>
67737 <description>Even odd frame/Endpoint data
67738 PID</description>
67739 <bitOffset>16</bitOffset>
67740 <bitWidth>1</bitWidth>
67741 <access>read-only</access>
67742 </field>
67743 <field>
67744 <name>NAKSTS</name>
67745 <description>NAK status</description>
67746 <bitOffset>17</bitOffset>
67747 <bitWidth>1</bitWidth>
67748 <access>read-only</access>
67749 </field>
67750 <field>
67751 <name>EPTYP</name>
67752 <description>Endpoint type</description>
67753 <bitOffset>18</bitOffset>
67754 <bitWidth>2</bitWidth>
67755 <access>read-write</access>
67756 </field>
67757 <field>
67758 <name>SNPM</name>
67759 <description>Snoop mode</description>
67760 <bitOffset>20</bitOffset>
67761 <bitWidth>1</bitWidth>
67762 <access>read-write</access>
67763 </field>
67764 <field>
67765 <name>Stall</name>
67766 <description>STALL handshake</description>
67767 <bitOffset>21</bitOffset>
67768 <bitWidth>1</bitWidth>
67769 <access>read-write</access>
67770 </field>
67771 <field>
67772 <name>CNAK</name>
67773 <description>Clear NAK</description>
67774 <bitOffset>26</bitOffset>
67775 <bitWidth>1</bitWidth>
67776 <access>write-only</access>
67777 </field>
67778 <field>
67779 <name>SNAK</name>
67780 <description>Set NAK</description>
67781 <bitOffset>27</bitOffset>
67782 <bitWidth>1</bitWidth>
67783 <access>write-only</access>
67784 </field>
67785 <field>
67786 <name>SD0PID_SEVNFRM</name>
67787 <description>Set DATA0 PID/Set even
67788 frame</description>
67789 <bitOffset>28</bitOffset>
67790 <bitWidth>1</bitWidth>
67791 <access>write-only</access>
67792 </field>
67793 <field>
67794 <name>SODDFRM</name>
67795 <description>Set odd frame</description>
67796 <bitOffset>29</bitOffset>
67797 <bitWidth>1</bitWidth>
67798 <access>write-only</access>
67799 </field>
67800 <field>
67801 <name>EPDIS</name>
67802 <description>Endpoint disable</description>
67803 <bitOffset>30</bitOffset>
67804 <bitWidth>1</bitWidth>
67805 <access>read-write</access>
67806 </field>
67807 <field>
67808 <name>EPENA</name>
67809 <description>Endpoint enable</description>
67810 <bitOffset>31</bitOffset>
67811 <bitWidth>1</bitWidth>
67812 <access>read-write</access>
67813 </field>
67814 </fields>
67815 </register>
67816 <register>
67817 <name>OTG_HS_DOEPTSIZ5</name>
67818 <displayName>OTG_HS_DOEPTSIZ5</displayName>
67819 <description>OTG_HS device endpoint-5 transfer size
67820 register</description>
67821 <addressOffset>0x3B0</addressOffset>
67822 <size>32</size>
67823 <access>read-write</access>
67824 <resetValue>0x0</resetValue>
67825 <fields>
67826 <field>
67827 <name>XFRSIZ</name>
67828 <description>Transfer size</description>
67829 <bitOffset>0</bitOffset>
67830 <bitWidth>19</bitWidth>
67831 </field>
67832 <field>
67833 <name>PKTCNT</name>
67834 <description>Packet count</description>
67835 <bitOffset>19</bitOffset>
67836 <bitWidth>10</bitWidth>
67837 </field>
67838 <field>
67839 <name>RXDPID_STUPCNT</name>
67840 <description>Received data PID/SETUP packet
67841 count</description>
67842 <bitOffset>29</bitOffset>
67843 <bitWidth>2</bitWidth>
67844 </field>
67845 </fields>
67846 </register>
67847 <register>
67848 <name>OTG_HS_DOEPTSIZ6</name>
67849 <displayName>OTG_HS_DOEPTSIZ6</displayName>
67850 <description>OTG_HS device endpoint-6 transfer size
67851 register</description>
67852 <addressOffset>0x3D0</addressOffset>
67853 <size>32</size>
67854 <access>read-write</access>
67855 <resetValue>0x0</resetValue>
67856 <fields>
67857 <field>
67858 <name>XFRSIZ</name>
67859 <description>Transfer size</description>
67860 <bitOffset>0</bitOffset>
67861 <bitWidth>19</bitWidth>
67862 </field>
67863 <field>
67864 <name>PKTCNT</name>
67865 <description>Packet count</description>
67866 <bitOffset>19</bitOffset>
67867 <bitWidth>10</bitWidth>
67868 </field>
67869 <field>
67870 <name>RXDPID_STUPCNT</name>
67871 <description>Received data PID/SETUP packet
67872 count</description>
67873 <bitOffset>29</bitOffset>
67874 <bitWidth>2</bitWidth>
67875 </field>
67876 </fields>
67877 </register>
67878 <register>
67879 <name>OTG_HS_DOEPTSIZ7</name>
67880 <displayName>OTG_HS_DOEPTSIZ7</displayName>
67881 <description>OTG_HS device endpoint-7 transfer size
67882 register</description>
67883 <addressOffset>0x3F0</addressOffset>
67884 <size>32</size>
67885 <access>read-write</access>
67886 <resetValue>0x0</resetValue>
67887 <fields>
67888 <field>
67889 <name>XFRSIZ</name>
67890 <description>Transfer size</description>
67891 <bitOffset>0</bitOffset>
67892 <bitWidth>19</bitWidth>
67893 </field>
67894 <field>
67895 <name>PKTCNT</name>
67896 <description>Packet count</description>
67897 <bitOffset>19</bitOffset>
67898 <bitWidth>10</bitWidth>
67899 </field>
67900 <field>
67901 <name>RXDPID_STUPCNT</name>
67902 <description>Received data PID/SETUP packet
67903 count</description>
67904 <bitOffset>29</bitOffset>
67905 <bitWidth>2</bitWidth>
67906 </field>
67907 </fields>
67908 </register>
67909 </registers>
67910 </peripheral>
67911 <peripheral>
67912 <name>OTG_HS_PWRCLK</name>
67913 <description>USB on the go high speed</description>
67914 <groupName>USB_OTG_HS</groupName>
67915 <baseAddress>0x40040E00</baseAddress>
67916 <addressBlock>
67917 <offset>0x0</offset>
67918 <size>0x3F200</size>
67919 <usage>registers</usage>
67920 </addressBlock>
67921 <interrupt>
67922 <name>OTG_HS_EP1_OUT</name>
67923 <description>USB On The Go HS End Point 1 Out global
67924 interrupt</description>
67925 <value>74</value>
67926 </interrupt>
67927 <interrupt>
67928 <name>OTG_HS_EP1_IN</name>
67929 <description>USB On The Go HS End Point 1 In global
67930 interrupt</description>
67931 <value>75</value>
67932 </interrupt>
67933 <interrupt>
67934 <name>OTG_HS_WKUP</name>
67935 <description>USB On The Go HS Wakeup through EXTI
67936 interrupt</description>
67937 <value>76</value>
67938 </interrupt>
67939 <interrupt>
67940 <name>OTG_HS</name>
67941 <description>USB On The Go HS global
67942 interrupt</description>
67943 <value>77</value>
67944 </interrupt>
67945 <registers>
67946 <register>
67947 <name>OTG_HS_PCGCR</name>
67948 <displayName>OTG_HS_PCGCR</displayName>
67949 <description>Power and clock gating control
67950 register</description>
67951 <addressOffset>0x0</addressOffset>
67952 <size>32</size>
67953 <access>read-write</access>
67954 <resetValue>0x0</resetValue>
67955 <fields>
67956 <field>
67957 <name>STPPCLK</name>
67958 <description>Stop PHY clock</description>
67959 <bitOffset>0</bitOffset>
67960 <bitWidth>1</bitWidth>
67961 </field>
67962 <field>
67963 <name>GATEHCLK</name>
67964 <description>Gate HCLK</description>
67965 <bitOffset>1</bitOffset>
67966 <bitWidth>1</bitWidth>
67967 </field>
67968 <field>
67969 <name>PHYSUSP</name>
67970 <description>PHY suspended</description>
67971 <bitOffset>4</bitOffset>
67972 <bitWidth>1</bitWidth>
67973 </field>
67974 </fields>
67975 </register>
67976 </registers>
67977 </peripheral>
67978 <peripheral>
67979 <name>NVIC</name>
67980 <description>Nested Vectored Interrupt
67981 Controller</description>
67982 <groupName>NVIC</groupName>
67983 <baseAddress>0xE000E100</baseAddress>
67984 <addressBlock>
67985 <offset>0x0</offset>
67986 <size>0x355</size>
67987 <usage>registers</usage>
67988 </addressBlock>
67989 <registers>
67990 <register>
67991 <name>ISER0</name>
67992 <displayName>ISER0</displayName>
67993 <description>Interrupt Set-Enable Register</description>
67994 <addressOffset>0x0</addressOffset>
67995 <size>0x20</size>
67996 <access>read-write</access>
67997 <resetValue>0x00000000</resetValue>
67998 <fields>
67999 <field>
68000 <name>SETENA</name>
68001 <description>SETENA</description>
68002 <bitOffset>0</bitOffset>
68003 <bitWidth>32</bitWidth>
68004 </field>
68005 </fields>
68006 </register>
68007 <register>
68008 <name>ISER1</name>
68009 <displayName>ISER1</displayName>
68010 <description>Interrupt Set-Enable Register</description>
68011 <addressOffset>0x4</addressOffset>
68012 <size>0x20</size>
68013 <access>read-write</access>
68014 <resetValue>0x00000000</resetValue>
68015 <fields>
68016 <field>
68017 <name>SETENA</name>
68018 <description>SETENA</description>
68019 <bitOffset>0</bitOffset>
68020 <bitWidth>32</bitWidth>
68021 </field>
68022 </fields>
68023 </register>
68024 <register>
68025 <name>ISER2</name>
68026 <displayName>ISER2</displayName>
68027 <description>Interrupt Set-Enable Register</description>
68028 <addressOffset>0x8</addressOffset>
68029 <size>0x20</size>
68030 <access>read-write</access>
68031 <resetValue>0x00000000</resetValue>
68032 <fields>
68033 <field>
68034 <name>SETENA</name>
68035 <description>SETENA</description>
68036 <bitOffset>0</bitOffset>
68037 <bitWidth>32</bitWidth>
68038 </field>
68039 </fields>
68040 </register>
68041 <register>
68042 <name>ICER0</name>
68043 <displayName>ICER0</displayName>
68044 <description>Interrupt Clear-Enable
68045 Register</description>
68046 <addressOffset>0x80</addressOffset>
68047 <size>0x20</size>
68048 <access>read-write</access>
68049 <resetValue>0x00000000</resetValue>
68050 <fields>
68051 <field>
68052 <name>CLRENA</name>
68053 <description>CLRENA</description>
68054 <bitOffset>0</bitOffset>
68055 <bitWidth>32</bitWidth>
68056 </field>
68057 </fields>
68058 </register>
68059 <register>
68060 <name>ICER1</name>
68061 <displayName>ICER1</displayName>
68062 <description>Interrupt Clear-Enable
68063 Register</description>
68064 <addressOffset>0x84</addressOffset>
68065 <size>0x20</size>
68066 <access>read-write</access>
68067 <resetValue>0x00000000</resetValue>
68068 <fields>
68069 <field>
68070 <name>CLRENA</name>
68071 <description>CLRENA</description>
68072 <bitOffset>0</bitOffset>
68073 <bitWidth>32</bitWidth>
68074 </field>
68075 </fields>
68076 </register>
68077 <register>
68078 <name>ICER2</name>
68079 <displayName>ICER2</displayName>
68080 <description>Interrupt Clear-Enable
68081 Register</description>
68082 <addressOffset>0x88</addressOffset>
68083 <size>0x20</size>
68084 <access>read-write</access>
68085 <resetValue>0x00000000</resetValue>
68086 <fields>
68087 <field>
68088 <name>CLRENA</name>
68089 <description>CLRENA</description>
68090 <bitOffset>0</bitOffset>
68091 <bitWidth>32</bitWidth>
68092 </field>
68093 </fields>
68094 </register>
68095 <register>
68096 <name>ISPR0</name>
68097 <displayName>ISPR0</displayName>
68098 <description>Interrupt Set-Pending Register</description>
68099 <addressOffset>0x100</addressOffset>
68100 <size>0x20</size>
68101 <access>read-write</access>
68102 <resetValue>0x00000000</resetValue>
68103 <fields>
68104 <field>
68105 <name>SETPEND</name>
68106 <description>SETPEND</description>
68107 <bitOffset>0</bitOffset>
68108 <bitWidth>32</bitWidth>
68109 </field>
68110 </fields>
68111 </register>
68112 <register>
68113 <name>ISPR1</name>
68114 <displayName>ISPR1</displayName>
68115 <description>Interrupt Set-Pending Register</description>
68116 <addressOffset>0x104</addressOffset>
68117 <size>0x20</size>
68118 <access>read-write</access>
68119 <resetValue>0x00000000</resetValue>
68120 <fields>
68121 <field>
68122 <name>SETPEND</name>
68123 <description>SETPEND</description>
68124 <bitOffset>0</bitOffset>
68125 <bitWidth>32</bitWidth>
68126 </field>
68127 </fields>
68128 </register>
68129 <register>
68130 <name>ISPR2</name>
68131 <displayName>ISPR2</displayName>
68132 <description>Interrupt Set-Pending Register</description>
68133 <addressOffset>0x108</addressOffset>
68134 <size>0x20</size>
68135 <access>read-write</access>
68136 <resetValue>0x00000000</resetValue>
68137 <fields>
68138 <field>
68139 <name>SETPEND</name>
68140 <description>SETPEND</description>
68141 <bitOffset>0</bitOffset>
68142 <bitWidth>32</bitWidth>
68143 </field>
68144 </fields>
68145 </register>
68146 <register>
68147 <name>ICPR0</name>
68148 <displayName>ICPR0</displayName>
68149 <description>Interrupt Clear-Pending
68150 Register</description>
68151 <addressOffset>0x180</addressOffset>
68152 <size>0x20</size>
68153 <access>read-write</access>
68154 <resetValue>0x00000000</resetValue>
68155 <fields>
68156 <field>
68157 <name>CLRPEND</name>
68158 <description>CLRPEND</description>
68159 <bitOffset>0</bitOffset>
68160 <bitWidth>32</bitWidth>
68161 </field>
68162 </fields>
68163 </register>
68164 <register>
68165 <name>ICPR1</name>
68166 <displayName>ICPR1</displayName>
68167 <description>Interrupt Clear-Pending
68168 Register</description>
68169 <addressOffset>0x184</addressOffset>
68170 <size>0x20</size>
68171 <access>read-write</access>
68172 <resetValue>0x00000000</resetValue>
68173 <fields>
68174 <field>
68175 <name>CLRPEND</name>
68176 <description>CLRPEND</description>
68177 <bitOffset>0</bitOffset>
68178 <bitWidth>32</bitWidth>
68179 </field>
68180 </fields>
68181 </register>
68182 <register>
68183 <name>ICPR2</name>
68184 <displayName>ICPR2</displayName>
68185 <description>Interrupt Clear-Pending
68186 Register</description>
68187 <addressOffset>0x188</addressOffset>
68188 <size>0x20</size>
68189 <access>read-write</access>
68190 <resetValue>0x00000000</resetValue>
68191 <fields>
68192 <field>
68193 <name>CLRPEND</name>
68194 <description>CLRPEND</description>
68195 <bitOffset>0</bitOffset>
68196 <bitWidth>32</bitWidth>
68197 </field>
68198 </fields>
68199 </register>
68200 <register>
68201 <name>IABR0</name>
68202 <displayName>IABR0</displayName>
68203 <description>Interrupt Active Bit Register</description>
68204 <addressOffset>0x200</addressOffset>
68205 <size>0x20</size>
68206 <access>read-only</access>
68207 <resetValue>0x00000000</resetValue>
68208 <fields>
68209 <field>
68210 <name>ACTIVE</name>
68211 <description>ACTIVE</description>
68212 <bitOffset>0</bitOffset>
68213 <bitWidth>32</bitWidth>
68214 </field>
68215 </fields>
68216 </register>
68217 <register>
68218 <name>IABR1</name>
68219 <displayName>IABR1</displayName>
68220 <description>Interrupt Active Bit Register</description>
68221 <addressOffset>0x204</addressOffset>
68222 <size>0x20</size>
68223 <access>read-only</access>
68224 <resetValue>0x00000000</resetValue>
68225 <fields>
68226 <field>
68227 <name>ACTIVE</name>
68228 <description>ACTIVE</description>
68229 <bitOffset>0</bitOffset>
68230 <bitWidth>32</bitWidth>
68231 </field>
68232 </fields>
68233 </register>
68234 <register>
68235 <name>IABR2</name>
68236 <displayName>IABR2</displayName>
68237 <description>Interrupt Active Bit Register</description>
68238 <addressOffset>0x208</addressOffset>
68239 <size>0x20</size>
68240 <access>read-only</access>
68241 <resetValue>0x00000000</resetValue>
68242 <fields>
68243 <field>
68244 <name>ACTIVE</name>
68245 <description>ACTIVE</description>
68246 <bitOffset>0</bitOffset>
68247 <bitWidth>32</bitWidth>
68248 </field>
68249 </fields>
68250 </register>
68251 <register>
68252 <name>IPR0</name>
68253 <displayName>IPR0</displayName>
68254 <description>Interrupt Priority Register</description>
68255 <addressOffset>0x300</addressOffset>
68256 <size>0x20</size>
68257 <access>read-write</access>
68258 <resetValue>0x00000000</resetValue>
68259 <fields>
68260 <field>
68261 <name>IPR_N0</name>
68262 <description>IPR_N0</description>
68263 <bitOffset>0</bitOffset>
68264 <bitWidth>8</bitWidth>
68265 </field>
68266 <field>
68267 <name>IPR_N1</name>
68268 <description>IPR_N1</description>
68269 <bitOffset>8</bitOffset>
68270 <bitWidth>8</bitWidth>
68271 </field>
68272 <field>
68273 <name>IPR_N2</name>
68274 <description>IPR_N2</description>
68275 <bitOffset>16</bitOffset>
68276 <bitWidth>8</bitWidth>
68277 </field>
68278 <field>
68279 <name>IPR_N3</name>
68280 <description>IPR_N3</description>
68281 <bitOffset>24</bitOffset>
68282 <bitWidth>8</bitWidth>
68283 </field>
68284 </fields>
68285 </register>
68286 <register>
68287 <name>IPR1</name>
68288 <displayName>IPR1</displayName>
68289 <description>Interrupt Priority Register</description>
68290 <addressOffset>0x304</addressOffset>
68291 <size>0x20</size>
68292 <access>read-write</access>
68293 <resetValue>0x00000000</resetValue>
68294 <fields>
68295 <field>
68296 <name>IPR_N0</name>
68297 <description>IPR_N0</description>
68298 <bitOffset>0</bitOffset>
68299 <bitWidth>8</bitWidth>
68300 </field>
68301 <field>
68302 <name>IPR_N1</name>
68303 <description>IPR_N1</description>
68304 <bitOffset>8</bitOffset>
68305 <bitWidth>8</bitWidth>
68306 </field>
68307 <field>
68308 <name>IPR_N2</name>
68309 <description>IPR_N2</description>
68310 <bitOffset>16</bitOffset>
68311 <bitWidth>8</bitWidth>
68312 </field>
68313 <field>
68314 <name>IPR_N3</name>
68315 <description>IPR_N3</description>
68316 <bitOffset>24</bitOffset>
68317 <bitWidth>8</bitWidth>
68318 </field>
68319 </fields>
68320 </register>
68321 <register>
68322 <name>IPR2</name>
68323 <displayName>IPR2</displayName>
68324 <description>Interrupt Priority Register</description>
68325 <addressOffset>0x308</addressOffset>
68326 <size>0x20</size>
68327 <access>read-write</access>
68328 <resetValue>0x00000000</resetValue>
68329 <fields>
68330 <field>
68331 <name>IPR_N0</name>
68332 <description>IPR_N0</description>
68333 <bitOffset>0</bitOffset>
68334 <bitWidth>8</bitWidth>
68335 </field>
68336 <field>
68337 <name>IPR_N1</name>
68338 <description>IPR_N1</description>
68339 <bitOffset>8</bitOffset>
68340 <bitWidth>8</bitWidth>
68341 </field>
68342 <field>
68343 <name>IPR_N2</name>
68344 <description>IPR_N2</description>
68345 <bitOffset>16</bitOffset>
68346 <bitWidth>8</bitWidth>
68347 </field>
68348 <field>
68349 <name>IPR_N3</name>
68350 <description>IPR_N3</description>
68351 <bitOffset>24</bitOffset>
68352 <bitWidth>8</bitWidth>
68353 </field>
68354 </fields>
68355 </register>
68356 <register>
68357 <name>IPR3</name>
68358 <displayName>IPR3</displayName>
68359 <description>Interrupt Priority Register</description>
68360 <addressOffset>0x30C</addressOffset>
68361 <size>0x20</size>
68362 <access>read-write</access>
68363 <resetValue>0x00000000</resetValue>
68364 <fields>
68365 <field>
68366 <name>IPR_N0</name>
68367 <description>IPR_N0</description>
68368 <bitOffset>0</bitOffset>
68369 <bitWidth>8</bitWidth>
68370 </field>
68371 <field>
68372 <name>IPR_N1</name>
68373 <description>IPR_N1</description>
68374 <bitOffset>8</bitOffset>
68375 <bitWidth>8</bitWidth>
68376 </field>
68377 <field>
68378 <name>IPR_N2</name>
68379 <description>IPR_N2</description>
68380 <bitOffset>16</bitOffset>
68381 <bitWidth>8</bitWidth>
68382 </field>
68383 <field>
68384 <name>IPR_N3</name>
68385 <description>IPR_N3</description>
68386 <bitOffset>24</bitOffset>
68387 <bitWidth>8</bitWidth>
68388 </field>
68389 </fields>
68390 </register>
68391 <register>
68392 <name>IPR4</name>
68393 <displayName>IPR4</displayName>
68394 <description>Interrupt Priority Register</description>
68395 <addressOffset>0x310</addressOffset>
68396 <size>0x20</size>
68397 <access>read-write</access>
68398 <resetValue>0x00000000</resetValue>
68399 <fields>
68400 <field>
68401 <name>IPR_N0</name>
68402 <description>IPR_N0</description>
68403 <bitOffset>0</bitOffset>
68404 <bitWidth>8</bitWidth>
68405 </field>
68406 <field>
68407 <name>IPR_N1</name>
68408 <description>IPR_N1</description>
68409 <bitOffset>8</bitOffset>
68410 <bitWidth>8</bitWidth>
68411 </field>
68412 <field>
68413 <name>IPR_N2</name>
68414 <description>IPR_N2</description>
68415 <bitOffset>16</bitOffset>
68416 <bitWidth>8</bitWidth>
68417 </field>
68418 <field>
68419 <name>IPR_N3</name>
68420 <description>IPR_N3</description>
68421 <bitOffset>24</bitOffset>
68422 <bitWidth>8</bitWidth>
68423 </field>
68424 </fields>
68425 </register>
68426 <register>
68427 <name>IPR5</name>
68428 <displayName>IPR5</displayName>
68429 <description>Interrupt Priority Register</description>
68430 <addressOffset>0x314</addressOffset>
68431 <size>0x20</size>
68432 <access>read-write</access>
68433 <resetValue>0x00000000</resetValue>
68434 <fields>
68435 <field>
68436 <name>IPR_N0</name>
68437 <description>IPR_N0</description>
68438 <bitOffset>0</bitOffset>
68439 <bitWidth>8</bitWidth>
68440 </field>
68441 <field>
68442 <name>IPR_N1</name>
68443 <description>IPR_N1</description>
68444 <bitOffset>8</bitOffset>
68445 <bitWidth>8</bitWidth>
68446 </field>
68447 <field>
68448 <name>IPR_N2</name>
68449 <description>IPR_N2</description>
68450 <bitOffset>16</bitOffset>
68451 <bitWidth>8</bitWidth>
68452 </field>
68453 <field>
68454 <name>IPR_N3</name>
68455 <description>IPR_N3</description>
68456 <bitOffset>24</bitOffset>
68457 <bitWidth>8</bitWidth>
68458 </field>
68459 </fields>
68460 </register>
68461 <register>
68462 <name>IPR6</name>
68463 <displayName>IPR6</displayName>
68464 <description>Interrupt Priority Register</description>
68465 <addressOffset>0x318</addressOffset>
68466 <size>0x20</size>
68467 <access>read-write</access>
68468 <resetValue>0x00000000</resetValue>
68469 <fields>
68470 <field>
68471 <name>IPR_N0</name>
68472 <description>IPR_N0</description>
68473 <bitOffset>0</bitOffset>
68474 <bitWidth>8</bitWidth>
68475 </field>
68476 <field>
68477 <name>IPR_N1</name>
68478 <description>IPR_N1</description>
68479 <bitOffset>8</bitOffset>
68480 <bitWidth>8</bitWidth>
68481 </field>
68482 <field>
68483 <name>IPR_N2</name>
68484 <description>IPR_N2</description>
68485 <bitOffset>16</bitOffset>
68486 <bitWidth>8</bitWidth>
68487 </field>
68488 <field>
68489 <name>IPR_N3</name>
68490 <description>IPR_N3</description>
68491 <bitOffset>24</bitOffset>
68492 <bitWidth>8</bitWidth>
68493 </field>
68494 </fields>
68495 </register>
68496 <register>
68497 <name>IPR7</name>
68498 <displayName>IPR7</displayName>
68499 <description>Interrupt Priority Register</description>
68500 <addressOffset>0x31C</addressOffset>
68501 <size>0x20</size>
68502 <access>read-write</access>
68503 <resetValue>0x00000000</resetValue>
68504 <fields>
68505 <field>
68506 <name>IPR_N0</name>
68507 <description>IPR_N0</description>
68508 <bitOffset>0</bitOffset>
68509 <bitWidth>8</bitWidth>
68510 </field>
68511 <field>
68512 <name>IPR_N1</name>
68513 <description>IPR_N1</description>
68514 <bitOffset>8</bitOffset>
68515 <bitWidth>8</bitWidth>
68516 </field>
68517 <field>
68518 <name>IPR_N2</name>
68519 <description>IPR_N2</description>
68520 <bitOffset>16</bitOffset>
68521 <bitWidth>8</bitWidth>
68522 </field>
68523 <field>
68524 <name>IPR_N3</name>
68525 <description>IPR_N3</description>
68526 <bitOffset>24</bitOffset>
68527 <bitWidth>8</bitWidth>
68528 </field>
68529 </fields>
68530 </register>
68531 <register>
68532 <name>IPR8</name>
68533 <displayName>IPR8</displayName>
68534 <description>Interrupt Priority Register</description>
68535 <addressOffset>0x320</addressOffset>
68536 <size>0x20</size>
68537 <access>read-write</access>
68538 <resetValue>0x00000000</resetValue>
68539 <fields>
68540 <field>
68541 <name>IPR_N0</name>
68542 <description>IPR_N0</description>
68543 <bitOffset>0</bitOffset>
68544 <bitWidth>8</bitWidth>
68545 </field>
68546 <field>
68547 <name>IPR_N1</name>
68548 <description>IPR_N1</description>
68549 <bitOffset>8</bitOffset>
68550 <bitWidth>8</bitWidth>
68551 </field>
68552 <field>
68553 <name>IPR_N2</name>
68554 <description>IPR_N2</description>
68555 <bitOffset>16</bitOffset>
68556 <bitWidth>8</bitWidth>
68557 </field>
68558 <field>
68559 <name>IPR_N3</name>
68560 <description>IPR_N3</description>
68561 <bitOffset>24</bitOffset>
68562 <bitWidth>8</bitWidth>
68563 </field>
68564 </fields>
68565 </register>
68566 <register>
68567 <name>IPR9</name>
68568 <displayName>IPR9</displayName>
68569 <description>Interrupt Priority Register</description>
68570 <addressOffset>0x324</addressOffset>
68571 <size>0x20</size>
68572 <access>read-write</access>
68573 <resetValue>0x00000000</resetValue>
68574 <fields>
68575 <field>
68576 <name>IPR_N0</name>
68577 <description>IPR_N0</description>
68578 <bitOffset>0</bitOffset>
68579 <bitWidth>8</bitWidth>
68580 </field>
68581 <field>
68582 <name>IPR_N1</name>
68583 <description>IPR_N1</description>
68584 <bitOffset>8</bitOffset>
68585 <bitWidth>8</bitWidth>
68586 </field>
68587 <field>
68588 <name>IPR_N2</name>
68589 <description>IPR_N2</description>
68590 <bitOffset>16</bitOffset>
68591 <bitWidth>8</bitWidth>
68592 </field>
68593 <field>
68594 <name>IPR_N3</name>
68595 <description>IPR_N3</description>
68596 <bitOffset>24</bitOffset>
68597 <bitWidth>8</bitWidth>
68598 </field>
68599 </fields>
68600 </register>
68601 <register>
68602 <name>IPR10</name>
68603 <displayName>IPR10</displayName>
68604 <description>Interrupt Priority Register</description>
68605 <addressOffset>0x328</addressOffset>
68606 <size>0x20</size>
68607 <access>read-write</access>
68608 <resetValue>0x00000000</resetValue>
68609 <fields>
68610 <field>
68611 <name>IPR_N0</name>
68612 <description>IPR_N0</description>
68613 <bitOffset>0</bitOffset>
68614 <bitWidth>8</bitWidth>
68615 </field>
68616 <field>
68617 <name>IPR_N1</name>
68618 <description>IPR_N1</description>
68619 <bitOffset>8</bitOffset>
68620 <bitWidth>8</bitWidth>
68621 </field>
68622 <field>
68623 <name>IPR_N2</name>
68624 <description>IPR_N2</description>
68625 <bitOffset>16</bitOffset>
68626 <bitWidth>8</bitWidth>
68627 </field>
68628 <field>
68629 <name>IPR_N3</name>
68630 <description>IPR_N3</description>
68631 <bitOffset>24</bitOffset>
68632 <bitWidth>8</bitWidth>
68633 </field>
68634 </fields>
68635 </register>
68636 <register>
68637 <name>IPR11</name>
68638 <displayName>IPR11</displayName>
68639 <description>Interrupt Priority Register</description>
68640 <addressOffset>0x32C</addressOffset>
68641 <size>0x20</size>
68642 <access>read-write</access>
68643 <resetValue>0x00000000</resetValue>
68644 <fields>
68645 <field>
68646 <name>IPR_N0</name>
68647 <description>IPR_N0</description>
68648 <bitOffset>0</bitOffset>
68649 <bitWidth>8</bitWidth>
68650 </field>
68651 <field>
68652 <name>IPR_N1</name>
68653 <description>IPR_N1</description>
68654 <bitOffset>8</bitOffset>
68655 <bitWidth>8</bitWidth>
68656 </field>
68657 <field>
68658 <name>IPR_N2</name>
68659 <description>IPR_N2</description>
68660 <bitOffset>16</bitOffset>
68661 <bitWidth>8</bitWidth>
68662 </field>
68663 <field>
68664 <name>IPR_N3</name>
68665 <description>IPR_N3</description>
68666 <bitOffset>24</bitOffset>
68667 <bitWidth>8</bitWidth>
68668 </field>
68669 </fields>
68670 </register>
68671 <register>
68672 <name>IPR12</name>
68673 <displayName>IPR12</displayName>
68674 <description>Interrupt Priority Register</description>
68675 <addressOffset>0x330</addressOffset>
68676 <size>0x20</size>
68677 <access>read-write</access>
68678 <resetValue>0x00000000</resetValue>
68679 <fields>
68680 <field>
68681 <name>IPR_N0</name>
68682 <description>IPR_N0</description>
68683 <bitOffset>0</bitOffset>
68684 <bitWidth>8</bitWidth>
68685 </field>
68686 <field>
68687 <name>IPR_N1</name>
68688 <description>IPR_N1</description>
68689 <bitOffset>8</bitOffset>
68690 <bitWidth>8</bitWidth>
68691 </field>
68692 <field>
68693 <name>IPR_N2</name>
68694 <description>IPR_N2</description>
68695 <bitOffset>16</bitOffset>
68696 <bitWidth>8</bitWidth>
68697 </field>
68698 <field>
68699 <name>IPR_N3</name>
68700 <description>IPR_N3</description>
68701 <bitOffset>24</bitOffset>
68702 <bitWidth>8</bitWidth>
68703 </field>
68704 </fields>
68705 </register>
68706 <register>
68707 <name>IPR13</name>
68708 <displayName>IPR13</displayName>
68709 <description>Interrupt Priority Register</description>
68710 <addressOffset>0x334</addressOffset>
68711 <size>0x20</size>
68712 <access>read-write</access>
68713 <resetValue>0x00000000</resetValue>
68714 <fields>
68715 <field>
68716 <name>IPR_N0</name>
68717 <description>IPR_N0</description>
68718 <bitOffset>0</bitOffset>
68719 <bitWidth>8</bitWidth>
68720 </field>
68721 <field>
68722 <name>IPR_N1</name>
68723 <description>IPR_N1</description>
68724 <bitOffset>8</bitOffset>
68725 <bitWidth>8</bitWidth>
68726 </field>
68727 <field>
68728 <name>IPR_N2</name>
68729 <description>IPR_N2</description>
68730 <bitOffset>16</bitOffset>
68731 <bitWidth>8</bitWidth>
68732 </field>
68733 <field>
68734 <name>IPR_N3</name>
68735 <description>IPR_N3</description>
68736 <bitOffset>24</bitOffset>
68737 <bitWidth>8</bitWidth>
68738 </field>
68739 </fields>
68740 </register>
68741 <register>
68742 <name>IPR14</name>
68743 <displayName>IPR14</displayName>
68744 <description>Interrupt Priority Register</description>
68745 <addressOffset>0x338</addressOffset>
68746 <size>0x20</size>
68747 <access>read-write</access>
68748 <resetValue>0x00000000</resetValue>
68749 <fields>
68750 <field>
68751 <name>IPR_N0</name>
68752 <description>IPR_N0</description>
68753 <bitOffset>0</bitOffset>
68754 <bitWidth>8</bitWidth>
68755 </field>
68756 <field>
68757 <name>IPR_N1</name>
68758 <description>IPR_N1</description>
68759 <bitOffset>8</bitOffset>
68760 <bitWidth>8</bitWidth>
68761 </field>
68762 <field>
68763 <name>IPR_N2</name>
68764 <description>IPR_N2</description>
68765 <bitOffset>16</bitOffset>
68766 <bitWidth>8</bitWidth>
68767 </field>
68768 <field>
68769 <name>IPR_N3</name>
68770 <description>IPR_N3</description>
68771 <bitOffset>24</bitOffset>
68772 <bitWidth>8</bitWidth>
68773 </field>
68774 </fields>
68775 </register>
68776 <register>
68777 <name>IPR15</name>
68778 <displayName>IPR15</displayName>
68779 <description>Interrupt Priority Register</description>
68780 <addressOffset>0x33C</addressOffset>
68781 <size>0x20</size>
68782 <access>read-write</access>
68783 <resetValue>0x00000000</resetValue>
68784 <fields>
68785 <field>
68786 <name>IPR_N0</name>
68787 <description>IPR_N0</description>
68788 <bitOffset>0</bitOffset>
68789 <bitWidth>8</bitWidth>
68790 </field>
68791 <field>
68792 <name>IPR_N1</name>
68793 <description>IPR_N1</description>
68794 <bitOffset>8</bitOffset>
68795 <bitWidth>8</bitWidth>
68796 </field>
68797 <field>
68798 <name>IPR_N2</name>
68799 <description>IPR_N2</description>
68800 <bitOffset>16</bitOffset>
68801 <bitWidth>8</bitWidth>
68802 </field>
68803 <field>
68804 <name>IPR_N3</name>
68805 <description>IPR_N3</description>
68806 <bitOffset>24</bitOffset>
68807 <bitWidth>8</bitWidth>
68808 </field>
68809 </fields>
68810 </register>
68811 <register>
68812 <name>IPR16</name>
68813 <displayName>IPR16</displayName>
68814 <description>Interrupt Priority Register</description>
68815 <addressOffset>0x340</addressOffset>
68816 <size>0x20</size>
68817 <access>read-write</access>
68818 <resetValue>0x00000000</resetValue>
68819 <fields>
68820 <field>
68821 <name>IPR_N0</name>
68822 <description>IPR_N0</description>
68823 <bitOffset>0</bitOffset>
68824 <bitWidth>8</bitWidth>
68825 </field>
68826 <field>
68827 <name>IPR_N1</name>
68828 <description>IPR_N1</description>
68829 <bitOffset>8</bitOffset>
68830 <bitWidth>8</bitWidth>
68831 </field>
68832 <field>
68833 <name>IPR_N2</name>
68834 <description>IPR_N2</description>
68835 <bitOffset>16</bitOffset>
68836 <bitWidth>8</bitWidth>
68837 </field>
68838 <field>
68839 <name>IPR_N3</name>
68840 <description>IPR_N3</description>
68841 <bitOffset>24</bitOffset>
68842 <bitWidth>8</bitWidth>
68843 </field>
68844 </fields>
68845 </register>
68846 <register>
68847 <name>IPR17</name>
68848 <displayName>IPR17</displayName>
68849 <description>Interrupt Priority Register</description>
68850 <addressOffset>0x344</addressOffset>
68851 <size>0x20</size>
68852 <access>read-write</access>
68853 <resetValue>0x00000000</resetValue>
68854 <fields>
68855 <field>
68856 <name>IPR_N0</name>
68857 <description>IPR_N0</description>
68858 <bitOffset>0</bitOffset>
68859 <bitWidth>8</bitWidth>
68860 </field>
68861 <field>
68862 <name>IPR_N1</name>
68863 <description>IPR_N1</description>
68864 <bitOffset>8</bitOffset>
68865 <bitWidth>8</bitWidth>
68866 </field>
68867 <field>
68868 <name>IPR_N2</name>
68869 <description>IPR_N2</description>
68870 <bitOffset>16</bitOffset>
68871 <bitWidth>8</bitWidth>
68872 </field>
68873 <field>
68874 <name>IPR_N3</name>
68875 <description>IPR_N3</description>
68876 <bitOffset>24</bitOffset>
68877 <bitWidth>8</bitWidth>
68878 </field>
68879 </fields>
68880 </register>
68881 <register>
68882 <name>IPR18</name>
68883 <displayName>IPR18</displayName>
68884 <description>Interrupt Priority Register</description>
68885 <addressOffset>0x348</addressOffset>
68886 <size>0x20</size>
68887 <access>read-write</access>
68888 <resetValue>0x00000000</resetValue>
68889 <fields>
68890 <field>
68891 <name>IPR_N0</name>
68892 <description>IPR_N0</description>
68893 <bitOffset>0</bitOffset>
68894 <bitWidth>8</bitWidth>
68895 </field>
68896 <field>
68897 <name>IPR_N1</name>
68898 <description>IPR_N1</description>
68899 <bitOffset>8</bitOffset>
68900 <bitWidth>8</bitWidth>
68901 </field>
68902 <field>
68903 <name>IPR_N2</name>
68904 <description>IPR_N2</description>
68905 <bitOffset>16</bitOffset>
68906 <bitWidth>8</bitWidth>
68907 </field>
68908 <field>
68909 <name>IPR_N3</name>
68910 <description>IPR_N3</description>
68911 <bitOffset>24</bitOffset>
68912 <bitWidth>8</bitWidth>
68913 </field>
68914 </fields>
68915 </register>
68916 <register>
68917 <name>IPR19</name>
68918 <displayName>IPR19</displayName>
68919 <description>Interrupt Priority Register</description>
68920 <addressOffset>0x34C</addressOffset>
68921 <size>0x20</size>
68922 <access>read-write</access>
68923 <resetValue>0x00000000</resetValue>
68924 <fields>
68925 <field>
68926 <name>IPR_N0</name>
68927 <description>IPR_N0</description>
68928 <bitOffset>0</bitOffset>
68929 <bitWidth>8</bitWidth>
68930 </field>
68931 <field>
68932 <name>IPR_N1</name>
68933 <description>IPR_N1</description>
68934 <bitOffset>8</bitOffset>
68935 <bitWidth>8</bitWidth>
68936 </field>
68937 <field>
68938 <name>IPR_N2</name>
68939 <description>IPR_N2</description>
68940 <bitOffset>16</bitOffset>
68941 <bitWidth>8</bitWidth>
68942 </field>
68943 <field>
68944 <name>IPR_N3</name>
68945 <description>IPR_N3</description>
68946 <bitOffset>24</bitOffset>
68947 <bitWidth>8</bitWidth>
68948 </field>
68949 </fields>
68950 </register>
68951 <register>
68952 <name>IPR20</name>
68953 <displayName>IPR20</displayName>
68954 <description>Interrupt Priority Register</description>
68955 <addressOffset>0x350</addressOffset>
68956 <size>0x20</size>
68957 <access>read-write</access>
68958 <resetValue>0x00000000</resetValue>
68959 <fields>
68960 <field>
68961 <name>IPR_N0</name>
68962 <description>IPR_N0</description>
68963 <bitOffset>0</bitOffset>
68964 <bitWidth>8</bitWidth>
68965 </field>
68966 <field>
68967 <name>IPR_N1</name>
68968 <description>IPR_N1</description>
68969 <bitOffset>8</bitOffset>
68970 <bitWidth>8</bitWidth>
68971 </field>
68972 <field>
68973 <name>IPR_N2</name>
68974 <description>IPR_N2</description>
68975 <bitOffset>16</bitOffset>
68976 <bitWidth>8</bitWidth>
68977 </field>
68978 <field>
68979 <name>IPR_N3</name>
68980 <description>IPR_N3</description>
68981 <bitOffset>24</bitOffset>
68982 <bitWidth>8</bitWidth>
68983 </field>
68984 </fields>
68985 </register>
68986 </registers>
68987 </peripheral>
68988 <peripheral>
68989 <name>MPU</name>
68990 <description>Memory protection unit</description>
68991 <groupName>MPU</groupName>
68992 <baseAddress>0xE000ED90</baseAddress>
68993 <addressBlock>
68994 <offset>0x0</offset>
68995 <size>0x15</size>
68996 <usage>registers</usage>
68997 </addressBlock>
68998 <registers>
68999 <register>
69000 <name>MPU_TYPER</name>
69001 <displayName>MPU_TYPER</displayName>
69002 <description>MPU type register</description>
69003 <addressOffset>0x0</addressOffset>
69004 <size>0x20</size>
69005 <access>read-only</access>
69006 <resetValue>0X00000800</resetValue>
69007 <fields>
69008 <field>
69009 <name>SEPARATE</name>
69010 <description>Separate flag</description>
69011 <bitOffset>0</bitOffset>
69012 <bitWidth>1</bitWidth>
69013 </field>
69014 <field>
69015 <name>DREGION</name>
69016 <description>Number of MPU data regions</description>
69017 <bitOffset>8</bitOffset>
69018 <bitWidth>8</bitWidth>
69019 </field>
69020 <field>
69021 <name>IREGION</name>
69022 <description>Number of MPU instruction
69023 regions</description>
69024 <bitOffset>16</bitOffset>
69025 <bitWidth>8</bitWidth>
69026 </field>
69027 </fields>
69028 </register>
69029 <register>
69030 <name>MPU_CTRL</name>
69031 <displayName>MPU_CTRL</displayName>
69032 <description>MPU control register</description>
69033 <addressOffset>0x4</addressOffset>
69034 <size>0x20</size>
69035 <access>read-only</access>
69036 <resetValue>0X00000000</resetValue>
69037 <fields>
69038 <field>
69039 <name>ENABLE</name>
69040 <description>Enables the MPU</description>
69041 <bitOffset>0</bitOffset>
69042 <bitWidth>1</bitWidth>
69043 </field>
69044 <field>
69045 <name>HFNMIENA</name>
69046 <description>Enables the operation of MPU during hard
69047 fault</description>
69048 <bitOffset>1</bitOffset>
69049 <bitWidth>1</bitWidth>
69050 </field>
69051 <field>
69052 <name>PRIVDEFENA</name>
69053 <description>Enable priviliged software access to
69054 default memory map</description>
69055 <bitOffset>2</bitOffset>
69056 <bitWidth>1</bitWidth>
69057 </field>
69058 </fields>
69059 </register>
69060 <register>
69061 <name>MPU_RNR</name>
69062 <displayName>MPU_RNR</displayName>
69063 <description>MPU region number register</description>
69064 <addressOffset>0x8</addressOffset>
69065 <size>0x20</size>
69066 <access>read-write</access>
69067 <resetValue>0X00000000</resetValue>
69068 <fields>
69069 <field>
69070 <name>REGION</name>
69071 <description>MPU region</description>
69072 <bitOffset>0</bitOffset>
69073 <bitWidth>8</bitWidth>
69074 </field>
69075 </fields>
69076 </register>
69077 <register>
69078 <name>MPU_RBAR</name>
69079 <displayName>MPU_RBAR</displayName>
69080 <description>MPU region base address
69081 register</description>
69082 <addressOffset>0xC</addressOffset>
69083 <size>0x20</size>
69084 <access>read-write</access>
69085 <resetValue>0X00000000</resetValue>
69086 <fields>
69087 <field>
69088 <name>REGION</name>
69089 <description>MPU region field</description>
69090 <bitOffset>0</bitOffset>
69091 <bitWidth>4</bitWidth>
69092 </field>
69093 <field>
69094 <name>VALID</name>
69095 <description>MPU region number valid</description>
69096 <bitOffset>4</bitOffset>
69097 <bitWidth>1</bitWidth>
69098 </field>
69099 <field>
69100 <name>ADDR</name>
69101 <description>Region base address field</description>
69102 <bitOffset>5</bitOffset>
69103 <bitWidth>27</bitWidth>
69104 </field>
69105 </fields>
69106 </register>
69107 <register>
69108 <name>MPU_RASR</name>
69109 <displayName>MPU_RASR</displayName>
69110 <description>MPU region attribute and size
69111 register</description>
69112 <addressOffset>0x10</addressOffset>
69113 <size>0x20</size>
69114 <access>read-write</access>
69115 <resetValue>0X00000000</resetValue>
69116 <fields>
69117 <field>
69118 <name>ENABLE</name>
69119 <description>Region enable bit.</description>
69120 <bitOffset>0</bitOffset>
69121 <bitWidth>1</bitWidth>
69122 </field>
69123 <field>
69124 <name>SIZE</name>
69125 <description>Size of the MPU protection
69126 region</description>
69127 <bitOffset>1</bitOffset>
69128 <bitWidth>5</bitWidth>
69129 </field>
69130 <field>
69131 <name>SRD</name>
69132 <description>Subregion disable bits</description>
69133 <bitOffset>8</bitOffset>
69134 <bitWidth>8</bitWidth>
69135 </field>
69136 <field>
69137 <name>B</name>
69138 <description>memory attribute</description>
69139 <bitOffset>16</bitOffset>
69140 <bitWidth>1</bitWidth>
69141 </field>
69142 <field>
69143 <name>C</name>
69144 <description>memory attribute</description>
69145 <bitOffset>17</bitOffset>
69146 <bitWidth>1</bitWidth>
69147 </field>
69148 <field>
69149 <name>S</name>
69150 <description>Shareable memory attribute</description>
69151 <bitOffset>18</bitOffset>
69152 <bitWidth>1</bitWidth>
69153 </field>
69154 <field>
69155 <name>TEX</name>
69156 <description>memory attribute</description>
69157 <bitOffset>19</bitOffset>
69158 <bitWidth>3</bitWidth>
69159 </field>
69160 <field>
69161 <name>AP</name>
69162 <description>Access permission</description>
69163 <bitOffset>24</bitOffset>
69164 <bitWidth>3</bitWidth>
69165 </field>
69166 <field>
69167 <name>XN</name>
69168 <description>Instruction access disable
69169 bit</description>
69170 <bitOffset>28</bitOffset>
69171 <bitWidth>1</bitWidth>
69172 </field>
69173 </fields>
69174 </register>
69175 </registers>
69176 </peripheral>
69177 <peripheral>
69178 <name>STK</name>
69179 <description>SysTick timer</description>
69180 <groupName>STK</groupName>
69181 <baseAddress>0xE000E010</baseAddress>
69182 <addressBlock>
69183 <offset>0x0</offset>
69184 <size>0x11</size>
69185 <usage>registers</usage>
69186 </addressBlock>
69187 <registers>
69188 <register>
69189 <name>CSR</name>
69190 <displayName>CSR</displayName>
69191 <description>SysTick control and status
69192 register</description>
69193 <addressOffset>0x0</addressOffset>
69194 <size>0x20</size>
69195 <access>read-write</access>
69196 <resetValue>0X00000000</resetValue>
69197 <fields>
69198 <field>
69199 <name>ENABLE</name>
69200 <description>Counter enable</description>
69201 <bitOffset>0</bitOffset>
69202 <bitWidth>1</bitWidth>
69203 </field>
69204 <field>
69205 <name>TICKINT</name>
69206 <description>SysTick exception request
69207 enable</description>
69208 <bitOffset>1</bitOffset>
69209 <bitWidth>1</bitWidth>
69210 </field>
69211 <field>
69212 <name>CLKSOURCE</name>
69213 <description>Clock source selection</description>
69214 <bitOffset>2</bitOffset>
69215 <bitWidth>1</bitWidth>
69216 </field>
69217 <field>
69218 <name>COUNTFLAG</name>
69219 <description>COUNTFLAG</description>
69220 <bitOffset>16</bitOffset>
69221 <bitWidth>1</bitWidth>
69222 </field>
69223 </fields>
69224 </register>
69225 <register>
69226 <name>RVR</name>
69227 <displayName>RVR</displayName>
69228 <description>SysTick reload value register</description>
69229 <addressOffset>0x4</addressOffset>
69230 <size>0x20</size>
69231 <access>read-write</access>
69232 <resetValue>0X00000000</resetValue>
69233 <fields>
69234 <field>
69235 <name>RELOAD</name>
69236 <description>RELOAD value</description>
69237 <bitOffset>0</bitOffset>
69238 <bitWidth>24</bitWidth>
69239 </field>
69240 </fields>
69241 </register>
69242 <register>
69243 <name>CVR</name>
69244 <displayName>CVR</displayName>
69245 <description>SysTick current value register</description>
69246 <addressOffset>0x8</addressOffset>
69247 <size>0x20</size>
69248 <access>read-write</access>
69249 <resetValue>0X00000000</resetValue>
69250 <fields>
69251 <field>
69252 <name>CURRENT</name>
69253 <description>Current counter value</description>
69254 <bitOffset>0</bitOffset>
69255 <bitWidth>24</bitWidth>
69256 </field>
69257 </fields>
69258 </register>
69259 <register>
69260 <name>CALIB</name>
69261 <displayName>CALIB</displayName>
69262 <description>SysTick calibration value
69263 register</description>
69264 <addressOffset>0xC</addressOffset>
69265 <size>0x20</size>
69266 <access>read-write</access>
69267 <resetValue>0X00000000</resetValue>
69268 <fields>
69269 <field>
69270 <name>TENMS</name>
69271 <description>Calibration value</description>
69272 <bitOffset>0</bitOffset>
69273 <bitWidth>24</bitWidth>
69274 </field>
69275 <field>
69276 <name>SKEW</name>
69277 <description>SKEW flag: Indicates whether the TENMS
69278 value is exact</description>
69279 <bitOffset>30</bitOffset>
69280 <bitWidth>1</bitWidth>
69281 </field>
69282 <field>
69283 <name>NOREF</name>
69284 <description>NOREF flag. Reads as zero</description>
69285 <bitOffset>31</bitOffset>
69286 <bitWidth>1</bitWidth>
69287 </field>
69288 </fields>
69289 </register>
69290 </registers>
69291 </peripheral>
69292 <peripheral>
69293 <name>NVIC_STIR</name>
69294 <description>Nested vectored interrupt
69295 controller</description>
69296 <groupName>NVIC</groupName>
69297 <baseAddress>0xE000EF00</baseAddress>
69298 <addressBlock>
69299 <offset>0x0</offset>
69300 <size>0x5</size>
69301 <usage>registers</usage>
69302 </addressBlock>
69303 <registers>
69304 <register>
69305 <name>STIR</name>
69306 <displayName>STIR</displayName>
69307 <description>Software trigger interrupt
69308 register</description>
69309 <addressOffset>0x0</addressOffset>
69310 <size>0x20</size>
69311 <access>read-write</access>
69312 <resetValue>0x00000000</resetValue>
69313 <fields>
69314 <field>
69315 <name>INTID</name>
69316 <description>Software generated interrupt
69317 ID</description>
69318 <bitOffset>0</bitOffset>
69319 <bitWidth>9</bitWidth>
69320 </field>
69321 </fields>
69322 </register>
69323 </registers>
69324 </peripheral>
69325 <peripheral>
69326 <name>FPU_CPACR</name>
69327 <description>Floating point unit CPACR</description>
69328 <groupName>FPU</groupName>
69329 <baseAddress>0xE000ED88</baseAddress>
69330 <addressBlock>
69331 <offset>0x0</offset>
69332 <size>0x5</size>
69333 <usage>registers</usage>
69334 </addressBlock>
69335 <registers>
69336 <register>
69337 <name>CPACR</name>
69338 <displayName>CPACR</displayName>
69339 <description>Coprocessor access control
69340 register</description>
69341 <addressOffset>0x0</addressOffset>
69342 <size>0x20</size>
69343 <access>read-write</access>
69344 <resetValue>0x0000000</resetValue>
69345 <fields>
69346 <field>
69347 <name>CP</name>
69348 <description>CP</description>
69349 <bitOffset>20</bitOffset>
69350 <bitWidth>4</bitWidth>
69351 </field>
69352 </fields>
69353 </register>
69354 </registers>
69355 </peripheral>
69356 <peripheral>
69357 <name>SCB_ACTRL</name>
69358 <description>System control block ACTLR</description>
69359 <groupName>SCB</groupName>
69360 <baseAddress>0xE000E008</baseAddress>
69361 <addressBlock>
69362 <offset>0x0</offset>
69363 <size>0x5</size>
69364 <usage>registers</usage>
69365 </addressBlock>
69366 <registers>
69367 <register>
69368 <name>ACTRL</name>
69369 <displayName>ACTRL</displayName>
69370 <description>Auxiliary control register</description>
69371 <addressOffset>0x0</addressOffset>
69372 <size>0x20</size>
69373 <access>read-write</access>
69374 <resetValue>0x00000000</resetValue>
69375 <fields>
69376 <field>
69377 <name>DISFOLD</name>
69378 <description>DISFOLD</description>
69379 <bitOffset>2</bitOffset>
69380 <bitWidth>1</bitWidth>
69381 </field>
69382 <field>
69383 <name>FPEXCODIS</name>
69384 <description>FPEXCODIS</description>
69385 <bitOffset>10</bitOffset>
69386 <bitWidth>1</bitWidth>
69387 </field>
69388 <field>
69389 <name>DISRAMODE</name>
69390 <description>DISRAMODE</description>
69391 <bitOffset>11</bitOffset>
69392 <bitWidth>1</bitWidth>
69393 </field>
69394 <field>
69395 <name>DISITMATBFLUSH</name>
69396 <description>DISITMATBFLUSH</description>
69397 <bitOffset>12</bitOffset>
69398 <bitWidth>1</bitWidth>
69399 </field>
69400 </fields>
69401 </register>
69402 </registers>
69403 </peripheral>
69404 <peripheral>
69405 <name>FPU</name>
69406 <description>Floting point unit</description>
69407 <groupName>FPU</groupName>
69408 <baseAddress>0xE000EF34</baseAddress>
69409 <addressBlock>
69410 <offset>0x0</offset>
69411 <size>0xD</size>
69412 <usage>registers</usage>
69413 </addressBlock>
69414 <interrupt>
69415 <name>FPU</name>
69416 <description>Floating point unit interrupt</description>
69417 <value>81</value>
69418 </interrupt>
69419 <registers>
69420 <register>
69421 <name>FPCCR</name>
69422 <displayName>FPCCR</displayName>
69423 <description>Floating-point context control
69424 register</description>
69425 <addressOffset>0x0</addressOffset>
69426 <size>0x20</size>
69427 <access>read-write</access>
69428 <resetValue>0x00000000</resetValue>
69429 <fields>
69430 <field>
69431 <name>LSPACT</name>
69432 <description>LSPACT</description>
69433 <bitOffset>0</bitOffset>
69434 <bitWidth>1</bitWidth>
69435 </field>
69436 <field>
69437 <name>USER</name>
69438 <description>USER</description>
69439 <bitOffset>1</bitOffset>
69440 <bitWidth>1</bitWidth>
69441 </field>
69442 <field>
69443 <name>THREAD</name>
69444 <description>THREAD</description>
69445 <bitOffset>3</bitOffset>
69446 <bitWidth>1</bitWidth>
69447 </field>
69448 <field>
69449 <name>HFRDY</name>
69450 <description>HFRDY</description>
69451 <bitOffset>4</bitOffset>
69452 <bitWidth>1</bitWidth>
69453 </field>
69454 <field>
69455 <name>MMRDY</name>
69456 <description>MMRDY</description>
69457 <bitOffset>5</bitOffset>
69458 <bitWidth>1</bitWidth>
69459 </field>
69460 <field>
69461 <name>BFRDY</name>
69462 <description>BFRDY</description>
69463 <bitOffset>6</bitOffset>
69464 <bitWidth>1</bitWidth>
69465 </field>
69466 <field>
69467 <name>MONRDY</name>
69468 <description>MONRDY</description>
69469 <bitOffset>8</bitOffset>
69470 <bitWidth>1</bitWidth>
69471 </field>
69472 <field>
69473 <name>LSPEN</name>
69474 <description>LSPEN</description>
69475 <bitOffset>30</bitOffset>
69476 <bitWidth>1</bitWidth>
69477 </field>
69478 <field>
69479 <name>ASPEN</name>
69480 <description>ASPEN</description>
69481 <bitOffset>31</bitOffset>
69482 <bitWidth>1</bitWidth>
69483 </field>
69484 </fields>
69485 </register>
69486 <register>
69487 <name>FPCAR</name>
69488 <displayName>FPCAR</displayName>
69489 <description>Floating-point context address
69490 register</description>
69491 <addressOffset>0x4</addressOffset>
69492 <size>0x20</size>
69493 <access>read-write</access>
69494 <resetValue>0x00000000</resetValue>
69495 <fields>
69496 <field>
69497 <name>ADDRESS</name>
69498 <description>Location of unpopulated
69499 floating-point</description>
69500 <bitOffset>3</bitOffset>
69501 <bitWidth>29</bitWidth>
69502 </field>
69503 </fields>
69504 </register>
69505 <register>
69506 <name>FPSCR</name>
69507 <displayName>FPSCR</displayName>
69508 <description>Floating-point status control
69509 register</description>
69510 <addressOffset>0x8</addressOffset>
69511 <size>0x20</size>
69512 <access>read-write</access>
69513 <resetValue>0x00000000</resetValue>
69514 <fields>
69515 <field>
69516 <name>IOC</name>
69517 <description>Invalid operation cumulative exception
69518 bit</description>
69519 <bitOffset>0</bitOffset>
69520 <bitWidth>1</bitWidth>
69521 </field>
69522 <field>
69523 <name>DZC</name>
69524 <description>Division by zero cumulative exception
69525 bit.</description>
69526 <bitOffset>1</bitOffset>
69527 <bitWidth>1</bitWidth>
69528 </field>
69529 <field>
69530 <name>OFC</name>
69531 <description>Overflow cumulative exception
69532 bit</description>
69533 <bitOffset>2</bitOffset>
69534 <bitWidth>1</bitWidth>
69535 </field>
69536 <field>
69537 <name>UFC</name>
69538 <description>Underflow cumulative exception
69539 bit</description>
69540 <bitOffset>3</bitOffset>
69541 <bitWidth>1</bitWidth>
69542 </field>
69543 <field>
69544 <name>IXC</name>
69545 <description>Inexact cumulative exception
69546 bit</description>
69547 <bitOffset>4</bitOffset>
69548 <bitWidth>1</bitWidth>
69549 </field>
69550 <field>
69551 <name>IDC</name>
69552 <description>Input denormal cumulative exception
69553 bit.</description>
69554 <bitOffset>7</bitOffset>
69555 <bitWidth>1</bitWidth>
69556 </field>
69557 <field>
69558 <name>RMode</name>
69559 <description>Rounding Mode control
69560 field</description>
69561 <bitOffset>22</bitOffset>
69562 <bitWidth>2</bitWidth>
69563 </field>
69564 <field>
69565 <name>FZ</name>
69566 <description>Flush-to-zero mode control
69567 bit:</description>
69568 <bitOffset>24</bitOffset>
69569 <bitWidth>1</bitWidth>
69570 </field>
69571 <field>
69572 <name>DN</name>
69573 <description>Default NaN mode control
69574 bit</description>
69575 <bitOffset>25</bitOffset>
69576 <bitWidth>1</bitWidth>
69577 </field>
69578 <field>
69579 <name>AHP</name>
69580 <description>Alternative half-precision control
69581 bit</description>
69582 <bitOffset>26</bitOffset>
69583 <bitWidth>1</bitWidth>
69584 </field>
69585 <field>
69586 <name>V</name>
69587 <description>Overflow condition code
69588 flag</description>
69589 <bitOffset>28</bitOffset>
69590 <bitWidth>1</bitWidth>
69591 </field>
69592 <field>
69593 <name>C</name>
69594 <description>Carry condition code flag</description>
69595 <bitOffset>29</bitOffset>
69596 <bitWidth>1</bitWidth>
69597 </field>
69598 <field>
69599 <name>Z</name>
69600 <description>Zero condition code flag</description>
69601 <bitOffset>30</bitOffset>
69602 <bitWidth>1</bitWidth>
69603 </field>
69604 <field>
69605 <name>N</name>
69606 <description>Negative condition code
69607 flag</description>
69608 <bitOffset>31</bitOffset>
69609 <bitWidth>1</bitWidth>
69610 </field>
69611 </fields>
69612 </register>
69613 </registers>
69614 </peripheral>
69615 <peripheral>
69616 <name>SCB</name>
69617 <description>System control block</description>
69618 <groupName>SCB</groupName>
69619 <baseAddress>0xE000ED00</baseAddress>
69620 <addressBlock>
69621 <offset>0x0</offset>
69622 <size>0x41</size>
69623 <usage>registers</usage>
69624 </addressBlock>
69625 <registers>
69626 <register>
69627 <name>CPUID</name>
69628 <displayName>CPUID</displayName>
69629 <description>CPUID base register</description>
69630 <addressOffset>0x0</addressOffset>
69631 <size>0x20</size>
69632 <access>read-only</access>
69633 <resetValue>0x410FC241</resetValue>
69634 <fields>
69635 <field>
69636 <name>Revision</name>
69637 <description>Revision number</description>
69638 <bitOffset>0</bitOffset>
69639 <bitWidth>4</bitWidth>
69640 </field>
69641 <field>
69642 <name>PartNo</name>
69643 <description>Part number of the
69644 processor</description>
69645 <bitOffset>4</bitOffset>
69646 <bitWidth>12</bitWidth>
69647 </field>
69648 <field>
69649 <name>Constant</name>
69650 <description>Reads as 0xF</description>
69651 <bitOffset>16</bitOffset>
69652 <bitWidth>4</bitWidth>
69653 </field>
69654 <field>
69655 <name>Variant</name>
69656 <description>Variant number</description>
69657 <bitOffset>20</bitOffset>
69658 <bitWidth>4</bitWidth>
69659 </field>
69660 <field>
69661 <name>Implementer</name>
69662 <description>Implementer code</description>
69663 <bitOffset>24</bitOffset>
69664 <bitWidth>8</bitWidth>
69665 </field>
69666 </fields>
69667 </register>
69668 <register>
69669 <name>ICSR</name>
69670 <displayName>ICSR</displayName>
69671 <description>Interrupt control and state
69672 register</description>
69673 <addressOffset>0x4</addressOffset>
69674 <size>0x20</size>
69675 <access>read-write</access>
69676 <resetValue>0x00000000</resetValue>
69677 <fields>
69678 <field>
69679 <name>VECTACTIVE</name>
69680 <description>Active vector</description>
69681 <bitOffset>0</bitOffset>
69682 <bitWidth>9</bitWidth>
69683 </field>
69684 <field>
69685 <name>RETTOBASE</name>
69686 <description>Return to base level</description>
69687 <bitOffset>11</bitOffset>
69688 <bitWidth>1</bitWidth>
69689 </field>
69690 <field>
69691 <name>VECTPENDING</name>
69692 <description>Pending vector</description>
69693 <bitOffset>12</bitOffset>
69694 <bitWidth>7</bitWidth>
69695 </field>
69696 <field>
69697 <name>ISRPENDING</name>
69698 <description>Interrupt pending flag</description>
69699 <bitOffset>22</bitOffset>
69700 <bitWidth>1</bitWidth>
69701 </field>
69702 <field>
69703 <name>PENDSTCLR</name>
69704 <description>SysTick exception clear-pending
69705 bit</description>
69706 <bitOffset>25</bitOffset>
69707 <bitWidth>1</bitWidth>
69708 </field>
69709 <field>
69710 <name>PENDSTSET</name>
69711 <description>SysTick exception set-pending
69712 bit</description>
69713 <bitOffset>26</bitOffset>
69714 <bitWidth>1</bitWidth>
69715 </field>
69716 <field>
69717 <name>PENDSVCLR</name>
69718 <description>PendSV clear-pending bit</description>
69719 <bitOffset>27</bitOffset>
69720 <bitWidth>1</bitWidth>
69721 </field>
69722 <field>
69723 <name>PENDSVSET</name>
69724 <description>PendSV set-pending bit</description>
69725 <bitOffset>28</bitOffset>
69726 <bitWidth>1</bitWidth>
69727 </field>
69728 <field>
69729 <name>NMIPENDSET</name>
69730 <description>NMI set-pending bit.</description>
69731 <bitOffset>31</bitOffset>
69732 <bitWidth>1</bitWidth>
69733 </field>
69734 </fields>
69735 </register>
69736 <register>
69737 <name>VTOR</name>
69738 <displayName>VTOR</displayName>
69739 <description>Vector table offset register</description>
69740 <addressOffset>0x8</addressOffset>
69741 <size>0x20</size>
69742 <access>read-write</access>
69743 <resetValue>0x00000000</resetValue>
69744 <fields>
69745 <field>
69746 <name>TBLOFF</name>
69747 <description>Vector table base offset
69748 field</description>
69749 <bitOffset>9</bitOffset>
69750 <bitWidth>21</bitWidth>
69751 </field>
69752 </fields>
69753 </register>
69754 <register>
69755 <name>AIRCR</name>
69756 <displayName>AIRCR</displayName>
69757 <description>Application interrupt and reset control
69758 register</description>
69759 <addressOffset>0xC</addressOffset>
69760 <size>0x20</size>
69761 <access>read-write</access>
69762 <resetValue>0x00000000</resetValue>
69763 <fields>
69764 <field>
69765 <name>VECTRESET</name>
69766 <description>VECTRESET</description>
69767 <bitOffset>0</bitOffset>
69768 <bitWidth>1</bitWidth>
69769 </field>
69770 <field>
69771 <name>VECTCLRACTIVE</name>
69772 <description>VECTCLRACTIVE</description>
69773 <bitOffset>1</bitOffset>
69774 <bitWidth>1</bitWidth>
69775 </field>
69776 <field>
69777 <name>SYSRESETREQ</name>
69778 <description>SYSRESETREQ</description>
69779 <bitOffset>2</bitOffset>
69780 <bitWidth>1</bitWidth>
69781 </field>
69782 <field>
69783 <name>PRIGROUP</name>
69784 <description>PRIGROUP</description>
69785 <bitOffset>8</bitOffset>
69786 <bitWidth>3</bitWidth>
69787 </field>
69788 <field>
69789 <name>ENDIANESS</name>
69790 <description>ENDIANESS</description>
69791 <bitOffset>15</bitOffset>
69792 <bitWidth>1</bitWidth>
69793 </field>
69794 <field>
69795 <name>VECTKEYSTAT</name>
69796 <description>Register key</description>
69797 <bitOffset>16</bitOffset>
69798 <bitWidth>16</bitWidth>
69799 </field>
69800 </fields>
69801 </register>
69802 <register>
69803 <name>SCR</name>
69804 <displayName>SCR</displayName>
69805 <description>System control register</description>
69806 <addressOffset>0x10</addressOffset>
69807 <size>0x20</size>
69808 <access>read-write</access>
69809 <resetValue>0x00000000</resetValue>
69810 <fields>
69811 <field>
69812 <name>SLEEPONEXIT</name>
69813 <description>SLEEPONEXIT</description>
69814 <bitOffset>1</bitOffset>
69815 <bitWidth>1</bitWidth>
69816 </field>
69817 <field>
69818 <name>SLEEPDEEP</name>
69819 <description>SLEEPDEEP</description>
69820 <bitOffset>2</bitOffset>
69821 <bitWidth>1</bitWidth>
69822 </field>
69823 <field>
69824 <name>SEVEONPEND</name>
69825 <description>Send Event on Pending bit</description>
69826 <bitOffset>4</bitOffset>
69827 <bitWidth>1</bitWidth>
69828 </field>
69829 </fields>
69830 </register>
69831 <register>
69832 <name>CCR</name>
69833 <displayName>CCR</displayName>
69834 <description>Configuration and control
69835 register</description>
69836 <addressOffset>0x14</addressOffset>
69837 <size>0x20</size>
69838 <access>read-write</access>
69839 <resetValue>0x00000000</resetValue>
69840 <fields>
69841 <field>
69842 <name>NONBASETHRDENA</name>
69843 <description>Configures how the processor enters
69844 Thread mode</description>
69845 <bitOffset>0</bitOffset>
69846 <bitWidth>1</bitWidth>
69847 </field>
69848 <field>
69849 <name>USERSETMPEND</name>
69850 <description>USERSETMPEND</description>
69851 <bitOffset>1</bitOffset>
69852 <bitWidth>1</bitWidth>
69853 </field>
69854 <field>
69855 <name>UNALIGN__TRP</name>
69856 <description>UNALIGN_ TRP</description>
69857 <bitOffset>3</bitOffset>
69858 <bitWidth>1</bitWidth>
69859 </field>
69860 <field>
69861 <name>DIV_0_TRP</name>
69862 <description>DIV_0_TRP</description>
69863 <bitOffset>4</bitOffset>
69864 <bitWidth>1</bitWidth>
69865 </field>
69866 <field>
69867 <name>BFHFNMIGN</name>
69868 <description>BFHFNMIGN</description>
69869 <bitOffset>8</bitOffset>
69870 <bitWidth>1</bitWidth>
69871 </field>
69872 <field>
69873 <name>STKALIGN</name>
69874 <description>STKALIGN</description>
69875 <bitOffset>9</bitOffset>
69876 <bitWidth>1</bitWidth>
69877 </field>
69878 <field>
69879 <name>DC</name>
69880 <description>DC</description>
69881 <bitOffset>16</bitOffset>
69882 <bitWidth>1</bitWidth>
69883 </field>
69884 <field>
69885 <name>IC</name>
69886 <description>IC</description>
69887 <bitOffset>17</bitOffset>
69888 <bitWidth>1</bitWidth>
69889 </field>
69890 <field>
69891 <name>BP</name>
69892 <description>BP</description>
69893 <bitOffset>18</bitOffset>
69894 <bitWidth>1</bitWidth>
69895 </field>
69896 </fields>
69897 </register>
69898 <register>
69899 <name>SHPR1</name>
69900 <displayName>SHPR1</displayName>
69901 <description>System handler priority
69902 registers</description>
69903 <addressOffset>0x18</addressOffset>
69904 <size>0x20</size>
69905 <access>read-write</access>
69906 <resetValue>0x00000000</resetValue>
69907 <fields>
69908 <field>
69909 <name>PRI_4</name>
69910 <description>Priority of system handler
69911 4</description>
69912 <bitOffset>0</bitOffset>
69913 <bitWidth>8</bitWidth>
69914 </field>
69915 <field>
69916 <name>PRI_5</name>
69917 <description>Priority of system handler
69918 5</description>
69919 <bitOffset>8</bitOffset>
69920 <bitWidth>8</bitWidth>
69921 </field>
69922 <field>
69923 <name>PRI_6</name>
69924 <description>Priority of system handler
69925 6</description>
69926 <bitOffset>16</bitOffset>
69927 <bitWidth>8</bitWidth>
69928 </field>
69929 </fields>
69930 </register>
69931 <register>
69932 <name>SHPR2</name>
69933 <displayName>SHPR2</displayName>
69934 <description>System handler priority
69935 registers</description>
69936 <addressOffset>0x1C</addressOffset>
69937 <size>0x20</size>
69938 <access>read-write</access>
69939 <resetValue>0x00000000</resetValue>
69940 <fields>
69941 <field>
69942 <name>PRI_11</name>
69943 <description>Priority of system handler
69944 11</description>
69945 <bitOffset>24</bitOffset>
69946 <bitWidth>8</bitWidth>
69947 </field>
69948 </fields>
69949 </register>
69950 <register>
69951 <name>SHPR3</name>
69952 <displayName>SHPR3</displayName>
69953 <description>System handler priority
69954 registers</description>
69955 <addressOffset>0x20</addressOffset>
69956 <size>0x20</size>
69957 <access>read-write</access>
69958 <resetValue>0x00000000</resetValue>
69959 <fields>
69960 <field>
69961 <name>PRI_14</name>
69962 <description>Priority of system handler
69963 14</description>
69964 <bitOffset>16</bitOffset>
69965 <bitWidth>8</bitWidth>
69966 </field>
69967 <field>
69968 <name>PRI_15</name>
69969 <description>Priority of system handler
69970 15</description>
69971 <bitOffset>24</bitOffset>
69972 <bitWidth>8</bitWidth>
69973 </field>
69974 </fields>
69975 </register>
69976 <register>
69977 <name>SHCRS</name>
69978 <displayName>SHCRS</displayName>
69979 <description>System handler control and state
69980 register</description>
69981 <addressOffset>0x24</addressOffset>
69982 <size>0x20</size>
69983 <access>read-write</access>
69984 <resetValue>0x00000000</resetValue>
69985 <fields>
69986 <field>
69987 <name>MEMFAULTACT</name>
69988 <description>Memory management fault exception active
69989 bit</description>
69990 <bitOffset>0</bitOffset>
69991 <bitWidth>1</bitWidth>
69992 </field>
69993 <field>
69994 <name>BUSFAULTACT</name>
69995 <description>Bus fault exception active
69996 bit</description>
69997 <bitOffset>1</bitOffset>
69998 <bitWidth>1</bitWidth>
69999 </field>
70000 <field>
70001 <name>USGFAULTACT</name>
70002 <description>Usage fault exception active
70003 bit</description>
70004 <bitOffset>3</bitOffset>
70005 <bitWidth>1</bitWidth>
70006 </field>
70007 <field>
70008 <name>SVCALLACT</name>
70009 <description>SVC call active bit</description>
70010 <bitOffset>7</bitOffset>
70011 <bitWidth>1</bitWidth>
70012 </field>
70013 <field>
70014 <name>MONITORACT</name>
70015 <description>Debug monitor active bit</description>
70016 <bitOffset>8</bitOffset>
70017 <bitWidth>1</bitWidth>
70018 </field>
70019 <field>
70020 <name>PENDSVACT</name>
70021 <description>PendSV exception active
70022 bit</description>
70023 <bitOffset>10</bitOffset>
70024 <bitWidth>1</bitWidth>
70025 </field>
70026 <field>
70027 <name>SYSTICKACT</name>
70028 <description>SysTick exception active
70029 bit</description>
70030 <bitOffset>11</bitOffset>
70031 <bitWidth>1</bitWidth>
70032 </field>
70033 <field>
70034 <name>USGFAULTPENDED</name>
70035 <description>Usage fault exception pending
70036 bit</description>
70037 <bitOffset>12</bitOffset>
70038 <bitWidth>1</bitWidth>
70039 </field>
70040 <field>
70041 <name>MEMFAULTPENDED</name>
70042 <description>Memory management fault exception
70043 pending bit</description>
70044 <bitOffset>13</bitOffset>
70045 <bitWidth>1</bitWidth>
70046 </field>
70047 <field>
70048 <name>BUSFAULTPENDED</name>
70049 <description>Bus fault exception pending
70050 bit</description>
70051 <bitOffset>14</bitOffset>
70052 <bitWidth>1</bitWidth>
70053 </field>
70054 <field>
70055 <name>SVCALLPENDED</name>
70056 <description>SVC call pending bit</description>
70057 <bitOffset>15</bitOffset>
70058 <bitWidth>1</bitWidth>
70059 </field>
70060 <field>
70061 <name>MEMFAULTENA</name>
70062 <description>Memory management fault enable
70063 bit</description>
70064 <bitOffset>16</bitOffset>
70065 <bitWidth>1</bitWidth>
70066 </field>
70067 <field>
70068 <name>BUSFAULTENA</name>
70069 <description>Bus fault enable bit</description>
70070 <bitOffset>17</bitOffset>
70071 <bitWidth>1</bitWidth>
70072 </field>
70073 <field>
70074 <name>USGFAULTENA</name>
70075 <description>Usage fault enable bit</description>
70076 <bitOffset>18</bitOffset>
70077 <bitWidth>1</bitWidth>
70078 </field>
70079 </fields>
70080 </register>
70081 <register>
70082 <name>CFSR_UFSR_BFSR_MMFSR</name>
70083 <displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
70084 <description>Configurable fault status
70085 register</description>
70086 <addressOffset>0x28</addressOffset>
70087 <size>0x20</size>
70088 <access>read-write</access>
70089 <resetValue>0x00000000</resetValue>
70090 <fields>
70091 <field>
70092 <name>IACCVIOL</name>
70093 <description>IACCVIOL</description>
70094 <bitOffset>0</bitOffset>
70095 <bitWidth>1</bitWidth>
70096 </field>
70097 <field>
70098 <name>DACCVIOL</name>
70099 <description>DACCVIOL</description>
70100 <bitOffset>1</bitOffset>
70101 <bitWidth>1</bitWidth>
70102 </field>
70103 <field>
70104 <name>MUNSTKERR</name>
70105 <description>MUNSTKERR</description>
70106 <bitOffset>3</bitOffset>
70107 <bitWidth>1</bitWidth>
70108 </field>
70109 <field>
70110 <name>MSTKERR</name>
70111 <description>MSTKERR</description>
70112 <bitOffset>4</bitOffset>
70113 <bitWidth>1</bitWidth>
70114 </field>
70115 <field>
70116 <name>MLSPERR</name>
70117 <description>MLSPERR</description>
70118 <bitOffset>5</bitOffset>
70119 <bitWidth>1</bitWidth>
70120 </field>
70121 <field>
70122 <name>MMARVALID</name>
70123 <description>MMARVALID</description>
70124 <bitOffset>7</bitOffset>
70125 <bitWidth>1</bitWidth>
70126 </field>
70127 <field>
70128 <name>IBUSERR</name>
70129 <description>Instruction bus error</description>
70130 <bitOffset>8</bitOffset>
70131 <bitWidth>1</bitWidth>
70132 </field>
70133 <field>
70134 <name>PRECISERR</name>
70135 <description>Precise data bus error</description>
70136 <bitOffset>9</bitOffset>
70137 <bitWidth>1</bitWidth>
70138 </field>
70139 <field>
70140 <name>IMPRECISERR</name>
70141 <description>Imprecise data bus error</description>
70142 <bitOffset>10</bitOffset>
70143 <bitWidth>1</bitWidth>
70144 </field>
70145 <field>
70146 <name>UNSTKERR</name>
70147 <description>Bus fault on unstacking for a return
70148 from exception</description>
70149 <bitOffset>11</bitOffset>
70150 <bitWidth>1</bitWidth>
70151 </field>
70152 <field>
70153 <name>STKERR</name>
70154 <description>Bus fault on stacking for exception
70155 entry</description>
70156 <bitOffset>12</bitOffset>
70157 <bitWidth>1</bitWidth>
70158 </field>
70159 <field>
70160 <name>LSPERR</name>
70161 <description>Bus fault on floating-point lazy state
70162 preservation</description>
70163 <bitOffset>13</bitOffset>
70164 <bitWidth>1</bitWidth>
70165 </field>
70166 <field>
70167 <name>BFARVALID</name>
70168 <description>Bus Fault Address Register (BFAR) valid
70169 flag</description>
70170 <bitOffset>15</bitOffset>
70171 <bitWidth>1</bitWidth>
70172 </field>
70173 <field>
70174 <name>UNDEFINSTR</name>
70175 <description>Undefined instruction usage
70176 fault</description>
70177 <bitOffset>16</bitOffset>
70178 <bitWidth>1</bitWidth>
70179 </field>
70180 <field>
70181 <name>INVSTATE</name>
70182 <description>Invalid state usage fault</description>
70183 <bitOffset>17</bitOffset>
70184 <bitWidth>1</bitWidth>
70185 </field>
70186 <field>
70187 <name>INVPC</name>
70188 <description>Invalid PC load usage
70189 fault</description>
70190 <bitOffset>18</bitOffset>
70191 <bitWidth>1</bitWidth>
70192 </field>
70193 <field>
70194 <name>NOCP</name>
70195 <description>No coprocessor usage
70196 fault.</description>
70197 <bitOffset>19</bitOffset>
70198 <bitWidth>1</bitWidth>
70199 </field>
70200 <field>
70201 <name>UNALIGNED</name>
70202 <description>Unaligned access usage
70203 fault</description>
70204 <bitOffset>24</bitOffset>
70205 <bitWidth>1</bitWidth>
70206 </field>
70207 <field>
70208 <name>DIVBYZERO</name>
70209 <description>Divide by zero usage fault</description>
70210 <bitOffset>25</bitOffset>
70211 <bitWidth>1</bitWidth>
70212 </field>
70213 </fields>
70214 </register>
70215 <register>
70216 <name>HFSR</name>
70217 <displayName>HFSR</displayName>
70218 <description>Hard fault status register</description>
70219 <addressOffset>0x2C</addressOffset>
70220 <size>0x20</size>
70221 <access>read-write</access>
70222 <resetValue>0x00000000</resetValue>
70223 <fields>
70224 <field>
70225 <name>VECTTBL</name>
70226 <description>Vector table hard fault</description>
70227 <bitOffset>1</bitOffset>
70228 <bitWidth>1</bitWidth>
70229 </field>
70230 <field>
70231 <name>FORCED</name>
70232 <description>Forced hard fault</description>
70233 <bitOffset>30</bitOffset>
70234 <bitWidth>1</bitWidth>
70235 </field>
70236 <field>
70237 <name>DEBUG_VT</name>
70238 <description>Reserved for Debug use</description>
70239 <bitOffset>31</bitOffset>
70240 <bitWidth>1</bitWidth>
70241 </field>
70242 </fields>
70243 </register>
70244 <register>
70245 <name>MMFAR</name>
70246 <displayName>MMFAR</displayName>
70247 <description>Memory management fault address
70248 register</description>
70249 <addressOffset>0x34</addressOffset>
70250 <size>0x20</size>
70251 <access>read-write</access>
70252 <resetValue>0x00000000</resetValue>
70253 <fields>
70254 <field>
70255 <name>ADDRESS</name>
70256 <description>Memory management fault
70257 address</description>
70258 <bitOffset>0</bitOffset>
70259 <bitWidth>32</bitWidth>
70260 </field>
70261 </fields>
70262 </register>
70263 <register>
70264 <name>BFAR</name>
70265 <displayName>BFAR</displayName>
70266 <description>Bus fault address register</description>
70267 <addressOffset>0x38</addressOffset>
70268 <size>0x20</size>
70269 <access>read-write</access>
70270 <resetValue>0x00000000</resetValue>
70271 <fields>
70272 <field>
70273 <name>ADDRESS</name>
70274 <description>Bus fault address</description>
70275 <bitOffset>0</bitOffset>
70276 <bitWidth>32</bitWidth>
70277 </field>
70278 </fields>
70279 </register>
70280 </registers>
70281 </peripheral>
70282 <peripheral>
70283 <name>PF</name>
70284 <description>Processor features</description>
70285 <groupName>PF</groupName>
70286 <baseAddress>0xE000ED78</baseAddress>
70287 <addressBlock>
70288 <offset>0x0</offset>
70289 <size>0xD</size>
70290 <usage>registers</usage>
70291 </addressBlock>
70292 <interrupt>
70293 <name>FPU</name>
70294 <description>Floating point unit interrupt</description>
70295 <value>81</value>
70296 </interrupt>
70297 <registers>
70298 <register>
70299 <name>CLIDR</name>
70300 <displayName>CLIDR</displayName>
70301 <description>Cache Level ID register</description>
70302 <addressOffset>0x0</addressOffset>
70303 <size>0x20</size>
70304 <access>read-only</access>
70305 <resetValue>0x09000003</resetValue>
70306 <fields>
70307 <field>
70308 <name>CL1</name>
70309 <description>CL1</description>
70310 <bitOffset>0</bitOffset>
70311 <bitWidth>3</bitWidth>
70312 </field>
70313 <field>
70314 <name>CL2</name>
70315 <description>CL2</description>
70316 <bitOffset>3</bitOffset>
70317 <bitWidth>3</bitWidth>
70318 </field>
70319 <field>
70320 <name>CL3</name>
70321 <description>CL3</description>
70322 <bitOffset>6</bitOffset>
70323 <bitWidth>3</bitWidth>
70324 </field>
70325 <field>
70326 <name>CL4</name>
70327 <description>CL4</description>
70328 <bitOffset>9</bitOffset>
70329 <bitWidth>3</bitWidth>
70330 </field>
70331 <field>
70332 <name>CL5</name>
70333 <description>CL5</description>
70334 <bitOffset>12</bitOffset>
70335 <bitWidth>3</bitWidth>
70336 </field>
70337 <field>
70338 <name>CL6</name>
70339 <description>CL6</description>
70340 <bitOffset>15</bitOffset>
70341 <bitWidth>3</bitWidth>
70342 </field>
70343 <field>
70344 <name>CL7</name>
70345 <description>CL7</description>
70346 <bitOffset>18</bitOffset>
70347 <bitWidth>3</bitWidth>
70348 </field>
70349 <field>
70350 <name>LoUIS</name>
70351 <description>LoUIS</description>
70352 <bitOffset>21</bitOffset>
70353 <bitWidth>3</bitWidth>
70354 </field>
70355 <field>
70356 <name>LoC</name>
70357 <description>LoC</description>
70358 <bitOffset>24</bitOffset>
70359 <bitWidth>3</bitWidth>
70360 </field>
70361 <field>
70362 <name>LoU</name>
70363 <description>LoU</description>
70364 <bitOffset>27</bitOffset>
70365 <bitWidth>3</bitWidth>
70366 </field>
70367 </fields>
70368 </register>
70369 <register>
70370 <name>CTR</name>
70371 <displayName>CTR</displayName>
70372 <description>Cache Type register</description>
70373 <addressOffset>0x4</addressOffset>
70374 <size>0x20</size>
70375 <access>read-only</access>
70376 <resetValue>0X8303C003</resetValue>
70377 <fields>
70378 <field>
70379 <name>_IminLine</name>
70380 <description>IminLine</description>
70381 <bitOffset>0</bitOffset>
70382 <bitWidth>4</bitWidth>
70383 </field>
70384 <field>
70385 <name>DMinLine</name>
70386 <description>DMinLine</description>
70387 <bitOffset>16</bitOffset>
70388 <bitWidth>4</bitWidth>
70389 </field>
70390 <field>
70391 <name>ERG</name>
70392 <description>ERG</description>
70393 <bitOffset>20</bitOffset>
70394 <bitWidth>4</bitWidth>
70395 </field>
70396 <field>
70397 <name>CWG</name>
70398 <description>CWG</description>
70399 <bitOffset>24</bitOffset>
70400 <bitWidth>4</bitWidth>
70401 </field>
70402 <field>
70403 <name>Format</name>
70404 <description>Format</description>
70405 <bitOffset>29</bitOffset>
70406 <bitWidth>3</bitWidth>
70407 </field>
70408 </fields>
70409 </register>
70410 <register>
70411 <name>CCSIDR</name>
70412 <displayName>CCSIDR</displayName>
70413 <description>Cache Size ID register</description>
70414 <addressOffset>0x8</addressOffset>
70415 <size>0x20</size>
70416 <access>read-only</access>
70417 <resetValue>0X00000000</resetValue>
70418 <fields>
70419 <field>
70420 <name>LineSize</name>
70421 <description>LineSize</description>
70422 <bitOffset>0</bitOffset>
70423 <bitWidth>3</bitWidth>
70424 </field>
70425 <field>
70426 <name>Associativity</name>
70427 <description>Associativity</description>
70428 <bitOffset>3</bitOffset>
70429 <bitWidth>10</bitWidth>
70430 </field>
70431 <field>
70432 <name>NumSets</name>
70433 <description>NumSets</description>
70434 <bitOffset>13</bitOffset>
70435 <bitWidth>15</bitWidth>
70436 </field>
70437 <field>
70438 <name>WA</name>
70439 <description>WA</description>
70440 <bitOffset>28</bitOffset>
70441 <bitWidth>1</bitWidth>
70442 </field>
70443 <field>
70444 <name>RA</name>
70445 <description>RA</description>
70446 <bitOffset>29</bitOffset>
70447 <bitWidth>1</bitWidth>
70448 </field>
70449 <field>
70450 <name>WB</name>
70451 <description>WB</description>
70452 <bitOffset>30</bitOffset>
70453 <bitWidth>1</bitWidth>
70454 </field>
70455 <field>
70456 <name>WT</name>
70457 <description>WT</description>
70458 <bitOffset>31</bitOffset>
70459 <bitWidth>1</bitWidth>
70460 </field>
70461 </fields>
70462 </register>
70463 </registers>
70464 </peripheral>
70465 <peripheral>
70466 <name>AC</name>
70467 <description>Access control</description>
70468 <groupName>AC</groupName>
70469 <baseAddress>0xE000EF90</baseAddress>
70470 <addressBlock>
70471 <offset>0x0</offset>
70472 <size>0x1D</size>
70473 <usage>registers</usage>
70474 </addressBlock>
70475 <registers>
70476 <register>
70477 <name>ITCMCR</name>
70478 <displayName>ITCMCR</displayName>
70479 <description>Instruction and Data Tightly-Coupled Memory
70480 Control Registers</description>
70481 <addressOffset>0x0</addressOffset>
70482 <size>0x20</size>
70483 <access>read-write</access>
70484 <resetValue>0X00000000</resetValue>
70485 <fields>
70486 <field>
70487 <name>EN</name>
70488 <description>EN</description>
70489 <bitOffset>0</bitOffset>
70490 <bitWidth>1</bitWidth>
70491 </field>
70492 <field>
70493 <name>RMW</name>
70494 <description>RMW</description>
70495 <bitOffset>1</bitOffset>
70496 <bitWidth>1</bitWidth>
70497 </field>
70498 <field>
70499 <name>RETEN</name>
70500 <description>RETEN</description>
70501 <bitOffset>2</bitOffset>
70502 <bitWidth>1</bitWidth>
70503 </field>
70504 <field>
70505 <name>SZ</name>
70506 <description>SZ</description>
70507 <bitOffset>3</bitOffset>
70508 <bitWidth>4</bitWidth>
70509 </field>
70510 </fields>
70511 </register>
70512 <register>
70513 <name>DTCMCR</name>
70514 <displayName>DTCMCR</displayName>
70515 <description>Instruction and Data Tightly-Coupled Memory
70516 Control Registers</description>
70517 <addressOffset>0x4</addressOffset>
70518 <size>0x20</size>
70519 <access>read-write</access>
70520 <resetValue>0X00000000</resetValue>
70521 <fields>
70522 <field>
70523 <name>EN</name>
70524 <description>EN</description>
70525 <bitOffset>0</bitOffset>
70526 <bitWidth>1</bitWidth>
70527 </field>
70528 <field>
70529 <name>RMW</name>
70530 <description>RMW</description>
70531 <bitOffset>1</bitOffset>
70532 <bitWidth>1</bitWidth>
70533 </field>
70534 <field>
70535 <name>RETEN</name>
70536 <description>RETEN</description>
70537 <bitOffset>2</bitOffset>
70538 <bitWidth>1</bitWidth>
70539 </field>
70540 <field>
70541 <name>SZ</name>
70542 <description>SZ</description>
70543 <bitOffset>3</bitOffset>
70544 <bitWidth>4</bitWidth>
70545 </field>
70546 </fields>
70547 </register>
70548 <register>
70549 <name>AHBPCR</name>
70550 <displayName>AHBPCR</displayName>
70551 <description>AHBP Control register</description>
70552 <addressOffset>0x8</addressOffset>
70553 <size>0x20</size>
70554 <access>read-write</access>
70555 <resetValue>0X00000000</resetValue>
70556 <fields>
70557 <field>
70558 <name>EN</name>
70559 <description>EN</description>
70560 <bitOffset>0</bitOffset>
70561 <bitWidth>1</bitWidth>
70562 </field>
70563 <field>
70564 <name>SZ</name>
70565 <description>SZ</description>
70566 <bitOffset>1</bitOffset>
70567 <bitWidth>3</bitWidth>
70568 </field>
70569 </fields>
70570 </register>
70571 <register>
70572 <name>CACR</name>
70573 <displayName>CACR</displayName>
70574 <description>Auxiliary Cache Control
70575 register</description>
70576 <addressOffset>0xC</addressOffset>
70577 <size>0x20</size>
70578 <access>read-write</access>
70579 <resetValue>0X00000000</resetValue>
70580 <fields>
70581 <field>
70582 <name>SIWT</name>
70583 <description>SIWT</description>
70584 <bitOffset>0</bitOffset>
70585 <bitWidth>1</bitWidth>
70586 </field>
70587 <field>
70588 <name>ECCEN</name>
70589 <description>ECCEN</description>
70590 <bitOffset>1</bitOffset>
70591 <bitWidth>1</bitWidth>
70592 </field>
70593 <field>
70594 <name>FORCEWT</name>
70595 <description>FORCEWT</description>
70596 <bitOffset>2</bitOffset>
70597 <bitWidth>1</bitWidth>
70598 </field>
70599 </fields>
70600 </register>
70601 <register>
70602 <name>AHBSCR</name>
70603 <displayName>AHBSCR</displayName>
70604 <description>AHB Slave Control register</description>
70605 <addressOffset>0x10</addressOffset>
70606 <size>0x20</size>
70607 <access>read-write</access>
70608 <resetValue>0X00000000</resetValue>
70609 <fields>
70610 <field>
70611 <name>CTL</name>
70612 <description>CTL</description>
70613 <bitOffset>0</bitOffset>
70614 <bitWidth>2</bitWidth>
70615 </field>
70616 <field>
70617 <name>TPRI</name>
70618 <description>TPRI</description>
70619 <bitOffset>2</bitOffset>
70620 <bitWidth>9</bitWidth>
70621 </field>
70622 <field>
70623 <name>INITCOUNT</name>
70624 <description>INITCOUNT</description>
70625 <bitOffset>11</bitOffset>
70626 <bitWidth>5</bitWidth>
70627 </field>
70628 </fields>
70629 </register>
70630 <register>
70631 <name>ABFSR</name>
70632 <displayName>ABFSR</displayName>
70633 <description>Auxiliary Bus Fault Status
70634 register</description>
70635 <addressOffset>0x18</addressOffset>
70636 <size>0x20</size>
70637 <access>read-write</access>
70638 <resetValue>0X00000000</resetValue>
70639 <fields>
70640 <field>
70641 <name>ITCM</name>
70642 <description>ITCM</description>
70643 <bitOffset>0</bitOffset>
70644 <bitWidth>1</bitWidth>
70645 </field>
70646 <field>
70647 <name>DTCM</name>
70648 <description>DTCM</description>
70649 <bitOffset>1</bitOffset>
70650 <bitWidth>1</bitWidth>
70651 </field>
70652 <field>
70653 <name>AHBP</name>
70654 <description>AHBP</description>
70655 <bitOffset>2</bitOffset>
70656 <bitWidth>1</bitWidth>
70657 </field>
70658 <field>
70659 <name>AXIM</name>
70660 <description>AXIM</description>
70661 <bitOffset>3</bitOffset>
70662 <bitWidth>1</bitWidth>
70663 </field>
70664 <field>
70665 <name>EPPB</name>
70666 <description>EPPB</description>
70667 <bitOffset>4</bitOffset>
70668 <bitWidth>1</bitWidth>
70669 </field>
70670 <field>
70671 <name>AXIMTYPE</name>
70672 <description>AXIMTYPE</description>
70673 <bitOffset>8</bitOffset>
70674 <bitWidth>2</bitWidth>
70675 </field>
70676 </fields>
70677 </register>
70678 </registers>
70679 </peripheral>
70680 </peripherals>
70681 </device>
INAV: Navigation-enabled flight control software