lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_adc.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_adc.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 adc header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* Define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_ADC_H
  29 #define __AT32F435_437_ADC_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* Includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39
  40 /** @addtogroup AT32F435_437_periph_driver
  41   * @{
  42   */
  43
  44 /** @addtogroup ADC
  45   * @{
  46   */
  47
  48 /** @defgroup ADC_interrupts_definition
  49   * @brief adc interrupt
  50   * @{
  51   */
  52
  53 #define ADC_OCCE_INT                     ((uint32_t)0x00000020) /*!< ordinary channels conversion end interrupt */
  54 #define ADC_VMOR_INT                     ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
  55 #define ADC_PCCE_INT                     ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
  56 #define ADC_OCCO_INT                     ((uint32_t)0x04000000) /*!< ordinary channel conversion overflow interrupt */
  57
  58 /**
  59   * @}
  60   */
  61
  62 /** @defgroup ADC_flags_definition
  63   * @brief adc flag
  64   * @{
  65   */
  66
  67 #define ADC_VMOR_FLAG                    ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
  68 #define ADC_OCCE_FLAG                    ((uint8_t)0x02) /*!< ordinary channels conversion end flag */
  69 #define ADC_PCCE_FLAG                    ((uint8_t)0x04) /*!< preempt channels conversion end flag */
  70 #define ADC_PCCS_FLAG                    ((uint8_t)0x08) /*!< preempt channel conversion start flag */
  71 #define ADC_OCCS_FLAG                    ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
  72 #define ADC_OCCO_FLAG                    ((uint8_t)0x20) /*!< ordinary channel conversion overflow flag */
  73 #define ADC_RDY_FLAG                     ((uint8_t)0x40) /*!< adc ready to conversion flag */
  74
  75 /**
  76   * @}
  77   */
  78
  79 /** @defgroup ADC_exported_types
  80   * @{
  81   */
  82
  83 /**
  84   * @brief adc division type
  85   */
  86 typedef enum
  87 {
  88   ADC_HCLK_DIV_2                         = 0x00, /*!< adcclk is hclk/2 */
  89   ADC_HCLK_DIV_3                         = 0x01, /*!< adcclk is hclk/3 */
  90   ADC_HCLK_DIV_4                         = 0x02, /*!< adcclk is hclk/4 */
  91   ADC_HCLK_DIV_5                         = 0x03, /*!< adcclk is hclk/5 */
  92   ADC_HCLK_DIV_6                         = 0x04, /*!< adcclk is hclk/6 */
  93   ADC_HCLK_DIV_7                         = 0x05, /*!< adcclk is hclk/7 */
  94   ADC_HCLK_DIV_8                         = 0x06, /*!< adcclk is hclk/8 */
  95   ADC_HCLK_DIV_9                         = 0x07, /*!< adcclk is hclk/9 */
  96   ADC_HCLK_DIV_10                        = 0x08, /*!< adcclk is hclk/10 */
  97   ADC_HCLK_DIV_11                        = 0x09, /*!< adcclk is hclk/11 */
  98   ADC_HCLK_DIV_12                        = 0x0A, /*!< adcclk is hclk/12 */
  99   ADC_HCLK_DIV_13                        = 0x0B, /*!< adcclk is hclk/13 */
 100   ADC_HCLK_DIV_14                        = 0x0C, /*!< adcclk is hclk/14 */
 101   ADC_HCLK_DIV_15                        = 0x0D, /*!< adcclk is hclk/15 */
 102   ADC_HCLK_DIV_16                        = 0x0E, /*!< adcclk is hclk/16 */
 103   ADC_HCLK_DIV_17                        = 0x0F  /*!< adcclk is hclk/17 */
 104 } adc_div_type;
 105
 106 /**
 107   * @brief adc combine mode type
 108   */
 109 typedef enum
 110 {
 111   ADC_INDEPENDENT_MODE                               = 0x00, /*!< independent mode */
 112   ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE       = 0x01, /*!< single slaver combined ordinary simultaneous + preempt simultaneous mode */
 113   ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02, /*!< single slaver combined ordinary simultaneous + preempt interleaved trigger mode */
 114   ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE                = 0x05, /*!< single slaver preempt simultaneous mode only */
 115   ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE               = 0x06, /*!< single slaver ordinary simultaneous mode only */
 116   ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE              = 0x07, /*!< single slaver ordinary shifting mode only */
 117   ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE          = 0x09, /*!< single slaver preempt interleaved trigger mode only */
 118   ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE       = 0x11, /*!< double slaver combined ordinary simultaneous + preempt simultaneous mode */
 119   ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12, /*!< double slaver combined ordinary simultaneous + preempt interleaved trigger mode */
 120   ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE                = 0x15, /*!< double slaver preempt simultaneous mode only */
 121   ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE               = 0x16, /*!< double slaver ordinary simultaneous mode only */
 122   ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE              = 0x17, /*!< double slaver ordinary shifting mode only */
 123   ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE          = 0x19  /*!< double slaver preempt interleaved trigger mode only */
 124 } adc_combine_mode_type;
 125
 126 /**
 127   * @brief adc common dma mode type
 128   */
 129 typedef enum
 130 {
 131   ADC_COMMON_DMAMODE_DISABLE             = 0x00, /*!< dma mode disabled */
 132   ADC_COMMON_DMAMODE_1                   = 0x01, /*!< dma mode1: each dma request trans a half-word data(reference manual account the rule of data package) */
 133   ADC_COMMON_DMAMODE_2                   = 0x02, /*!< dma mode2: each dma request trans two half-word data(reference manual account the rule of data package) */
 134   ADC_COMMON_DMAMODE_3                   = 0x03, /*!< dma mode3: each dma request trans two bytes data(reference manual account the rule of data package) */
 135   ADC_COMMON_DMAMODE_4                   = 0x04, /*!< dma mode4: each dma request trans three bytes data(reference manual account the rule of data package) */
 136   ADC_COMMON_DMAMODE_5                   = 0x05  /*!< dma mode5: odd dma request trans two half-word data,even dma request trans a half-word data(reference manual account the rule of data package) */
 137 } adc_common_dma_mode_type;
 138
 139 /**
 140   * @brief adc common sampling interval type
 141   */
 142 typedef enum
 143 {
 144   ADC_SAMPLING_INTERVAL_5CYCLES          = 0x00, /*!< ordinary shifting mode adjacent adc sampling interval 5 adcclk */
 145   ADC_SAMPLING_INTERVAL_6CYCLES          = 0x01, /*!< ordinary shifting mode adjacent adc sampling interval 6 adcclk */
 146   ADC_SAMPLING_INTERVAL_7CYCLES          = 0x02, /*!< ordinary shifting mode adjacent adc sampling interval 7 adcclk */
 147   ADC_SAMPLING_INTERVAL_8CYCLES          = 0x03, /*!< ordinary shifting mode adjacent adc sampling interval 8 adcclk */
 148   ADC_SAMPLING_INTERVAL_9CYCLES          = 0x04, /*!< ordinary shifting mode adjacent adc sampling interval 9 adcclk */
 149   ADC_SAMPLING_INTERVAL_10CYCLES         = 0x05, /*!< ordinary shifting mode adjacent adc sampling interval 10 adcclk */
 150   ADC_SAMPLING_INTERVAL_11CYCLES         = 0x06, /*!< ordinary shifting mode adjacent adc sampling interval 11 adcclk */
 151   ADC_SAMPLING_INTERVAL_12CYCLES         = 0x07, /*!< ordinary shifting mode adjacent adc sampling interval 12 adcclk */
 152   ADC_SAMPLING_INTERVAL_13CYCLES         = 0x08, /*!< ordinary shifting mode adjacent adc sampling interval 13 adcclk */
 153   ADC_SAMPLING_INTERVAL_14CYCLES         = 0x09, /*!< ordinary shifting mode adjacent adc sampling interval 14 adcclk */
 154   ADC_SAMPLING_INTERVAL_15CYCLES         = 0x0A, /*!< ordinary shifting mode adjacent adc sampling interval 15 adcclk */
 155   ADC_SAMPLING_INTERVAL_16CYCLES         = 0x0B, /*!< ordinary shifting mode adjacent adc sampling interval 16 adcclk */
 156   ADC_SAMPLING_INTERVAL_17CYCLES         = 0x0C, /*!< ordinary shifting mode adjacent adc sampling interval 17 adcclk */
 157   ADC_SAMPLING_INTERVAL_18CYCLES         = 0x0D, /*!< ordinary shifting mode adjacent adc sampling interval 18 adcclk */
 158   ADC_SAMPLING_INTERVAL_19CYCLES         = 0x0E, /*!< ordinary shifting mode adjacent adc sampling interval 19 adcclk */
 159   ADC_SAMPLING_INTERVAL_20CYCLES         = 0x0F  /*!< ordinary shifting mode adjacent adc sampling interval 20 adcclk */
 160 } adc_sampling_interval_type;
 161
 162 /**
 163   * @brief adc conversion resolution type
 164   */
 165 typedef enum
 166 {
 167   ADC_RESOLUTION_12B                     = 0x00, /*!< conversion resolution 12 bit */
 168   ADC_RESOLUTION_10B                     = 0x01, /*!< conversion resolution 10 bit */
 169   ADC_RESOLUTION_8B                      = 0x02, /*!< conversion resolution 8 bit */
 170   ADC_RESOLUTION_6B                      = 0x03  /*!< conversion resolution 6 bit */
 171 } adc_resolution_type;
 172
 173 /**
 174   * @brief adc data align type
 175   */
 176 typedef enum
 177 {
 178   ADC_RIGHT_ALIGNMENT                    = 0x00, /*!< data right alignment */
 179   ADC_LEFT_ALIGNMENT                     = 0x01  /*!< data left alignment */
 180 } adc_data_align_type;
 181
 182 /**
 183   * @brief adc channel select type
 184   */
 185 typedef enum
 186 {
 187   ADC_CHANNEL_0                          = 0x00, /*!< adc channel 0 */
 188   ADC_CHANNEL_1                          = 0x01, /*!< adc channel 1 */
 189   ADC_CHANNEL_2                          = 0x02, /*!< adc channel 2 */
 190   ADC_CHANNEL_3                          = 0x03, /*!< adc channel 3 */
 191   ADC_CHANNEL_4                          = 0x04, /*!< adc channel 4 */
 192   ADC_CHANNEL_5                          = 0x05, /*!< adc channel 5 */
 193   ADC_CHANNEL_6                          = 0x06, /*!< adc channel 6 */
 194   ADC_CHANNEL_7                          = 0x07, /*!< adc channel 7 */
 195   ADC_CHANNEL_8                          = 0x08, /*!< adc channel 8 */
 196   ADC_CHANNEL_9                          = 0x09, /*!< adc channel 9 */
 197   ADC_CHANNEL_10                         = 0x0A, /*!< adc channel 10 */
 198   ADC_CHANNEL_11                         = 0x0B, /*!< adc channel 11 */
 199   ADC_CHANNEL_12                         = 0x0C, /*!< adc channel 12 */
 200   ADC_CHANNEL_13                         = 0x0D, /*!< adc channel 13 */
 201   ADC_CHANNEL_14                         = 0x0E, /*!< adc channel 14 */
 202   ADC_CHANNEL_15                         = 0x0F, /*!< adc channel 15 */
 203   ADC_CHANNEL_16                         = 0x10, /*!< adc channel 16 */
 204   ADC_CHANNEL_17                         = 0x11, /*!< adc channel 17 */
 205   ADC_CHANNEL_18                         = 0x12  /*!< adc channel 18 */
 206 } adc_channel_select_type;
 207
 208 /**
 209   * @brief adc sampletime select type
 210   */
 211 typedef enum
 212 {
 213   ADC_SAMPLETIME_2_5                     = 0x00, /*!< adc sample time 2.5 cycle */
 214   ADC_SAMPLETIME_6_5                     = 0x01, /*!< adc sample time 6.5 cycle */
 215   ADC_SAMPLETIME_12_5                    = 0x02, /*!< adc sample time 12.5 cycle */
 216   ADC_SAMPLETIME_24_5                    = 0x03, /*!< adc sample time 24.5 cycle */
 217   ADC_SAMPLETIME_47_5                    = 0x04, /*!< adc sample time 47.5 cycle */
 218   ADC_SAMPLETIME_92_5                    = 0x05, /*!< adc sample time 92.5 cycle */
 219   ADC_SAMPLETIME_247_5                   = 0x06, /*!< adc sample time 247.5 cycle */
 220   ADC_SAMPLETIME_640_5                   = 0x07  /*!< adc sample time 640.5 cycle */
 221 } adc_sampletime_select_type;
 222
 223 /**
 224   * @brief adc ordinary group trigger event select type
 225   */
 226 typedef enum
 227 {
 228   ADC_ORDINARY_TRIG_TMR1CH1              = 0x00, /*!< timer1 ch1 event as trigger source of ordinary sequence */
 229   ADC_ORDINARY_TRIG_TMR1CH2              = 0x01, /*!< timer1 ch2 event as trigger source of ordinary sequence */
 230   ADC_ORDINARY_TRIG_TMR1CH3              = 0x02, /*!< timer1 ch3 event as trigger source of ordinary sequence */
 231   ADC_ORDINARY_TRIG_TMR2CH2              = 0x03, /*!< timer2 ch2 event as trigger source of ordinary sequence */
 232   ADC_ORDINARY_TRIG_TMR2CH3              = 0x04, /*!< timer2 ch3 event as trigger source of ordinary sequence */
 233   ADC_ORDINARY_TRIG_TMR2CH4              = 0x05, /*!< timer2 ch4 event as trigger source of ordinary sequence */
 234   ADC_ORDINARY_TRIG_TMR2TRGOUT           = 0x06, /*!< timer2 trgout event as trigger source of ordinary sequence */
 235   ADC_ORDINARY_TRIG_TMR3CH1              = 0x07, /*!< timer3 ch1 event as trigger source of ordinary sequence */
 236   ADC_ORDINARY_TRIG_TMR3TRGOUT           = 0x08, /*!< timer3 trgout event as trigger source of ordinary sequence */
 237   ADC_ORDINARY_TRIG_TMR4CH4              = 0x09, /*!< timer4 ch4 event as trigger source of ordinary sequence */
 238   ADC_ORDINARY_TRIG_TMR5CH1              = 0x0A, /*!< timer5 ch1 event as trigger source of ordinary sequence */
 239   ADC_ORDINARY_TRIG_TMR5CH2              = 0x0B, /*!< timer5 ch2 event as trigger source of ordinary sequence */
 240   ADC_ORDINARY_TRIG_TMR5CH3              = 0x0C, /*!< timer5 ch3 event as trigger source of ordinary sequence */
 241   ADC_ORDINARY_TRIG_TMR8CH1              = 0x0D, /*!< timer8 ch1 event as trigger source of ordinary sequence */
 242   ADC_ORDINARY_TRIG_TMR8TRGOUT           = 0x0E, /*!< timer8 trgout event as trigger source of ordinary sequence */
 243   ADC_ORDINARY_TRIG_EXINT11              = 0x0F, /*!< exint line11 event as trigger source of ordinary sequence */
 244   ADC_ORDINARY_TRIG_TMR20TRGOUT          = 0x10, /*!< timer20 trgout event as trigger source of ordinary sequence */
 245   ADC_ORDINARY_TRIG_TMR20TRGOUT2         = 0x11, /*!< timer20 trgout2 event as trigger source of ordinary sequence */
 246   ADC_ORDINARY_TRIG_TMR20CH1             = 0x12, /*!< timer20 ch1 event as trigger source of ordinary sequence */
 247   ADC_ORDINARY_TRIG_TMR20CH2             = 0x13, /*!< timer20 ch2 event as trigger source of ordinary sequence */
 248   ADC_ORDINARY_TRIG_TMR20CH3             = 0x14, /*!< timer20 ch3 event as trigger source of ordinary sequence */
 249   ADC_ORDINARY_TRIG_TMR8TRGOUT2          = 0x15, /*!< timer8 trgout2 event as trigger source of ordinary sequence */
 250   ADC_ORDINARY_TRIG_TMR1TRGOUT2          = 0x16, /*!< timer1 trgout2 event as trigger source of ordinary sequence */
 251   ADC_ORDINARY_TRIG_TMR4TRGOUT           = 0x17, /*!< timer4 trgout event as trigger source of ordinary sequence */
 252   ADC_ORDINARY_TRIG_TMR6TRGOUT           = 0x18, /*!< timer6 trgout event as trigger source of ordinary sequence */
 253   ADC_ORDINARY_TRIG_TMR3CH4              = 0x19, /*!< timer3 ch4 event as trigger source of ordinary sequence */
 254   ADC_ORDINARY_TRIG_TMR4CH1              = 0x1A, /*!< timer4 ch1 event as trigger source of ordinary sequence */
 255   ADC_ORDINARY_TRIG_TMR1TRGOUT           = 0x1B, /*!< timer1 trgout event as trigger source of ordinary sequence */
 256   ADC_ORDINARY_TRIG_TMR2CH1              = 0x1C, /*!< timer2 ch1 event as trigger source of ordinary sequence */
 257   ADC_ORDINARY_TRIG_TMR7TRGOUT           = 0x1E  /*!< timer7 trgout event as trigger source of ordinary sequence */
 258 } adc_ordinary_trig_select_type;
 259
 260 /**
 261   * @brief adc ordinary channel conversion's external_trigger_edge type
 262   */
 263 typedef enum
 264 {
 265   ADC_ORDINARY_TRIG_EDGE_NONE            = 0x00, /*!< ordinary channels trigger detection disabled */
 266   ADC_ORDINARY_TRIG_EDGE_RISING          = 0x01, /*!< ordinary channels trigger detection on the rising edge */
 267   ADC_ORDINARY_TRIG_EDGE_FALLING         = 0x02, /*!< ordinary channels trigger detection on the falling edge */
 268   ADC_ORDINARY_TRIG_EDGE_RISING_FALLING  = 0x03  /*!< ordinary channels trigger detection on both the rising and falling edges */
 269 } adc_ordinary_trig_edge_type;
 270
 271 /**
 272   * @brief adc preempt group external trigger event select type
 273   */
 274 typedef enum
 275 {
 276   ADC_PREEMPT_TRIG_TMR1CH4               = 0x00, /*!< timer1 ch4 event as trigger source of preempt sequence */
 277   ADC_PREEMPT_TRIG_TMR1TRGOUT            = 0x01, /*!< timer1 trgout event as trigger source of preempt sequence */
 278   ADC_PREEMPT_TRIG_TMR2CH1               = 0x02, /*!< timer2 ch1 event as trigger source of preempt sequence */
 279   ADC_PREEMPT_TRIG_TMR2TRGOUT            = 0x03, /*!< timer2 trgout event as trigger source of preempt sequence */
 280   ADC_PREEMPT_TRIG_TMR3CH2               = 0x04, /*!< timer3 ch2 event as trigger source of preempt sequence */
 281   ADC_PREEMPT_TRIG_TMR3CH4               = 0x05, /*!< timer3 ch4 event as trigger source of preempt sequence */
 282   ADC_PREEMPT_TRIG_TMR4CH1               = 0x06, /*!< timer4 ch1 event as trigger source of preempt sequence */
 283   ADC_PREEMPT_TRIG_TMR4CH2               = 0x07, /*!< timer4 ch2 event as trigger source of preempt sequence */
 284   ADC_PREEMPT_TRIG_TMR4CH3               = 0x08, /*!< timer4 ch3 event as trigger source of preempt sequence */
 285   ADC_PREEMPT_TRIG_TMR4TRGOUT            = 0x09, /*!< timer4 trgout event as trigger source of preempt sequence */
 286   ADC_PREEMPT_TRIG_TMR5CH4               = 0x0A, /*!< timer5 ch4 event as trigger source of preempt sequence */
 287   ADC_PREEMPT_TRIG_TMR5TRGOUT            = 0x0B, /*!< timer5 trgout event as trigger source of preempt sequence */
 288   ADC_PREEMPT_TRIG_TMR8CH2               = 0x0C, /*!< timer8 ch2 event as trigger source of preempt sequence */
 289   ADC_PREEMPT_TRIG_TMR8CH3               = 0x0D, /*!< timer8 ch3 event as trigger source of preempt sequence */
 290   ADC_PREEMPT_TRIG_TMR8CH4               = 0x0E, /*!< timer8 ch4 event as trigger source of preempt sequence */
 291   ADC_PREEMPT_TRIG_EXINT15               = 0x0F, /*!< exint line15 event as trigger source of preempt sequence */
 292   ADC_PREEMPT_TRIG_TMR20TRGOUT           = 0x10, /*!< timer20 trgout event as trigger source of preempt sequence */
 293   ADC_PREEMPT_TRIG_TMR20TRGOUT2          = 0x11, /*!< timer20 trgout2 event as trigger source of preempt sequence */
 294   ADC_PREEMPT_TRIG_TMR20CH4              = 0x12, /*!< timer20 ch4 event as trigger source of preempt sequence */
 295   ADC_PREEMPT_TRIG_TMR1TRGOUT2           = 0x13, /*!< timer1 trgout2 event as trigger source of preempt sequence */
 296   ADC_PREEMPT_TRIG_TMR8TRGOUT            = 0x14, /*!< timer8 trgout event as trigger source of preempt sequence */
 297   ADC_PREEMPT_TRIG_TMR8TRGOUT2           = 0x15, /*!< timer8 trgout2 event as trigger source of preempt sequence */
 298   ADC_PREEMPT_TRIG_TMR3CH3               = 0x16, /*!< timer3 ch3 event as trigger source of preempt sequence */
 299   ADC_PREEMPT_TRIG_TMR3TRGOUT            = 0x17, /*!< timer3 trgout event as trigger source of preempt sequence */
 300   ADC_PREEMPT_TRIG_TMR3CH1               = 0x18, /*!< timer3 ch1 event as trigger source of preempt sequence */
 301   ADC_PREEMPT_TRIG_TMR6TRGOUT            = 0x19, /*!< timer6 trgout event as trigger source of preempt sequence */
 302   ADC_PREEMPT_TRIG_TMR4CH4               = 0x1A, /*!< timer4 ch4 event as trigger source of preempt sequence */
 303   ADC_PREEMPT_TRIG_TMR1CH3               = 0x1B, /*!< timer1 ch3 event as trigger source of preempt sequence */
 304   ADC_PREEMPT_TRIG_TMR20CH2              = 0x1C, /*!< timer20 ch2 event as trigger source of preempt sequence */
 305   ADC_PREEMPT_TRIG_TMR7TRGOUT            = 0x1E  /*!< timer7 trgout event as trigger source of preempt sequence */
 306 } adc_preempt_trig_select_type;
 307
 308 /**
 309   * @brief adc preempt channel conversion's external_trigger_edge type
 310   */
 311 typedef enum
 312 {
 313   ADC_PREEMPT_TRIG_EDGE_NONE             = 0x00, /*!< preempt channels trigger detection disabled */
 314   ADC_PREEMPT_TRIG_EDGE_RISING           = 0x01, /*!< preempt channels trigger detection on the rising edge */
 315   ADC_PREEMPT_TRIG_EDGE_FALLING          = 0x02, /*!< preempt channels trigger detection on the falling edge */
 316   ADC_PREEMPT_TRIG_EDGE_RISING_FALLING   = 0x03  /*!< preempt channels trigger detection on both the rising and falling edges */
 317 } adc_preempt_trig_edge_type;
 318
 319 /**
 320   * @brief adc preempt channel type
 321   */
 322 typedef enum
 323 {
 324   ADC_PREEMPT_CHANNEL_1                  = 0x00, /*!< adc preempt channel 1 */
 325   ADC_PREEMPT_CHANNEL_2                  = 0x01, /*!< adc preempt channel 2 */
 326   ADC_PREEMPT_CHANNEL_3                  = 0x02, /*!< adc preempt channel 3 */
 327   ADC_PREEMPT_CHANNEL_4                  = 0x03  /*!< adc preempt channel 4 */
 328 } adc_preempt_channel_type;
 329
 330 /**
 331   * @brief adc voltage_monitoring type
 332   */
 333 typedef enum
 334 {
 335   ADC_VMONITOR_SINGLE_ORDINARY           = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
 336   ADC_VMONITOR_SINGLE_PREEMPT            = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
 337   ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT   = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
 338   ADC_VMONITOR_ALL_ORDINARY              = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
 339   ADC_VMONITOR_ALL_PREEMPT               = 0x00400000, /*!< voltage_monitoring on all preempt channel */
 340   ADC_VMONITOR_ALL_ORDINARY_PREEMPT      = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
 341   ADC_VMONITOR_NONE                      = 0x00000000  /*!< no channel guarded by the voltage_monitoring */
 342 } adc_voltage_monitoring_type;
 343
 344 /**
 345   * @brief adc oversample ratio type
 346   */
 347 typedef enum
 348 {
 349   ADC_OVERSAMPLE_RATIO_2                 = 0x00, /*!< adc oversample ratio 2 */
 350   ADC_OVERSAMPLE_RATIO_4                 = 0x01, /*!< adc oversample ratio 4 */
 351   ADC_OVERSAMPLE_RATIO_8                 = 0x02, /*!< adc oversample ratio 8 */
 352   ADC_OVERSAMPLE_RATIO_16                = 0x03, /*!< adc oversample ratio 16 */
 353   ADC_OVERSAMPLE_RATIO_32                = 0x04, /*!< adc oversample ratio 32 */
 354   ADC_OVERSAMPLE_RATIO_64                = 0x05, /*!< adc oversample ratio 64 */
 355   ADC_OVERSAMPLE_RATIO_128               = 0x06, /*!< adc oversample ratio 128 */
 356   ADC_OVERSAMPLE_RATIO_256               = 0x07  /*!< adc oversample ratio 256 */
 357 } adc_oversample_ratio_type;
 358
 359 /**
 360   * @brief adc oversample shift type
 361   */
 362 typedef enum
 363 {
 364   ADC_OVERSAMPLE_SHIFT_0                 = 0x00, /*!< adc oversample shift 0 */
 365   ADC_OVERSAMPLE_SHIFT_1                 = 0x01, /*!< adc oversample shift 1 */
 366   ADC_OVERSAMPLE_SHIFT_2                 = 0x02, /*!< adc oversample shift 2 */
 367   ADC_OVERSAMPLE_SHIFT_3                 = 0x03, /*!< adc oversample shift 3 */
 368   ADC_OVERSAMPLE_SHIFT_4                 = 0x04, /*!< adc oversample shift 4 */
 369   ADC_OVERSAMPLE_SHIFT_5                 = 0x05, /*!< adc oversample shift 5 */
 370   ADC_OVERSAMPLE_SHIFT_6                 = 0x06, /*!< adc oversample shift 6 */
 371   ADC_OVERSAMPLE_SHIFT_7                 = 0x07, /*!< adc oversample shift 7 */
 372   ADC_OVERSAMPLE_SHIFT_8                 = 0x08  /*!< adc oversample shift 8 */
 373 } adc_oversample_shift_type;
 374
 375 /**
 376   * @brief adc ordinary oversample recover type
 377   */
 378 typedef enum
 379 {
 380   ADC_OVERSAMPLE_CONTINUE                = 0x00, /*!< continue mode:when preempt triggered,oversampling is temporary stopped and continued after preempt sequence */
 381   ADC_OVERSAMPLE_RESTART                 = 0x01  /*!< restart mode:when preempt triggered,oversampling is aborted and resumed from start after preempt sequence */
 382 } adc_ordinary_oversample_restart_type;
 383
 384 /**
 385   * @brief adc common config type
 386   */
 387 typedef struct
 388 {
 389   adc_combine_mode_type                  combine_mode;                    /*!< adc combine mode select */
 390   adc_div_type                           div;                             /*!< adc division select */
 391   adc_common_dma_mode_type               common_dma_mode;                 /*!< adc common dma mode select */
 392   confirm_state                          common_dma_request_repeat_state; /*!< adc common dma repeat state */
 393   adc_sampling_interval_type             sampling_interval;               /*!< ordinary shifting mode adjacent adc sampling interval select */
 394   confirm_state                          tempervintrv_state;              /*!< adc temperature sensor and vintrv state */
 395   confirm_state                          vbat_state;                      /*!< adc voltage battery state */
 396 } adc_common_config_type;
 397
 398 /**
 399   * @brief adc base config type
 400   */
 401 typedef struct
 402 {
 403   confirm_state                          sequence_mode;           /*!< adc sequence mode */
 404   confirm_state                          repeat_mode;             /*!< adc repeat mode */
 405   adc_data_align_type                    data_align;              /*!< adc data alignment */
 406   uint8_t                                ordinary_channel_length; /*!< adc ordinary channel sequence length*/
 407 } adc_base_config_type;
 408
 409 /**
 410   * @brief type define adc register all
 411   */
 412 typedef struct
 413 {
 414
 415   /**
 416     * @brief adc sts register, offset:0x00
 417     */
 418   union
 419   {
 420     __IO uint32_t sts;
 421     struct
 422     {
 423       __IO uint32_t vmor                 : 1; /* [0] */
 424       __IO uint32_t occe                 : 1; /* [1] */
 425       __IO uint32_t pcce                 : 1; /* [2] */
 426       __IO uint32_t pccs                 : 1; /* [3] */
 427       __IO uint32_t occs                 : 1; /* [4] */
 428       __IO uint32_t occo                 : 1; /* [5] */
 429       __IO uint32_t rdy                  : 1; /* [6] */
 430       __IO uint32_t reserved1            : 25;/* [31:7] */
 431     } sts_bit;
 432   };
 433
 434   /**
 435     * @brief adc ctrl1 register, offset:0x04
 436     */
 437   union
 438   {
 439     __IO uint32_t ctrl1;
 440     struct
 441     {
 442       __IO uint32_t vmcsel               : 5; /* [4:0] */
 443       __IO uint32_t occeien              : 1; /* [5] */
 444       __IO uint32_t vmorien              : 1; /* [6] */
 445       __IO uint32_t pcceien              : 1; /* [7] */
 446       __IO uint32_t sqen                 : 1; /* [8] */
 447       __IO uint32_t vmsgen               : 1; /* [9] */
 448       __IO uint32_t pcautoen             : 1; /* [10] */
 449       __IO uint32_t ocpen                : 1; /* [11] */
 450       __IO uint32_t pcpen                : 1; /* [12] */
 451       __IO uint32_t ocpcnt               : 3; /* [15:13] */
 452       __IO uint32_t reserved1            : 6; /* [21:16] */
 453       __IO uint32_t pcvmen               : 1; /* [22] */
 454       __IO uint32_t ocvmen               : 1; /* [23] */
 455       __IO uint32_t crsel                : 2; /* [25:24] */
 456       __IO uint32_t occoien              : 1; /* [26] */
 457       __IO uint32_t reserved2            : 5; /* [31:27] */
 458     } ctrl1_bit;
 459   };
 460
 461    /**
 462     * @brief adc ctrl2 register, offset:0x08
 463     */
 464   union
 465   {
 466     __IO uint32_t ctrl2;
 467     struct
 468     {
 469       __IO uint32_t adcen                : 1; /* [0] */
 470       __IO uint32_t rpen                 : 1; /* [1] */
 471       __IO uint32_t adcal                : 1; /* [2] */
 472       __IO uint32_t adcalinit            : 1; /* [3] */
 473       __IO uint32_t adabrt               : 1; /* [4] */
 474       __IO uint32_t reserved1            : 3; /* [7:5] */
 475       __IO uint32_t ocdmaen              : 1; /* [8] */
 476       __IO uint32_t ocdrcen              : 1; /* [9] */
 477       __IO uint32_t eocsfen              : 1; /* [10] */
 478       __IO uint32_t dtalign              : 1; /* [11] */
 479       __IO uint32_t reserved2            : 4; /* [15:12] */
 480       __IO uint32_t pctesel_l            : 4; /* [19:16] */
 481       __IO uint32_t pcete                : 2; /* [21:20] */
 482       __IO uint32_t pcswtrg              : 1; /* [22] */
 483       __IO uint32_t pctesel_h            : 1; /* [23] */
 484       __IO uint32_t octesel_l            : 4; /* [27:24] */
 485       __IO uint32_t ocete                : 2; /* [29:28] */
 486       __IO uint32_t ocswtrg              : 1; /* [30] */
 487       __IO uint32_t octesel_h            : 1; /* [31] */
 488     } ctrl2_bit;
 489   };
 490
 491   /**
 492   * @brief adc spt1 register, offset:0x0C
 493   */
 494   union
 495   {
 496     __IO uint32_t spt1;
 497     struct
 498     {
 499       __IO uint32_t cspt10               : 3; /* [2:0] */
 500       __IO uint32_t cspt11               : 3; /* [5:3] */
 501       __IO uint32_t cspt12               : 3; /* [8:6] */
 502       __IO uint32_t cspt13               : 3; /* [11:9] */
 503       __IO uint32_t cspt14               : 3; /* [14:12] */
 504       __IO uint32_t cspt15               : 3; /* [17:15] */
 505       __IO uint32_t cspt16               : 3; /* [20:18] */
 506       __IO uint32_t cspt17               : 3; /* [23:21] */
 507       __IO uint32_t cspt18               : 3; /* [26:24] */
 508       __IO uint32_t reserved1            : 5;/* [31:27] */
 509     } spt1_bit;
 510   };
 511
 512   /**
 513   * @brief adc spt2 register, offset:0x10
 514   */
 515   union
 516   {
 517     __IO uint32_t spt2;
 518     struct
 519     {
 520       __IO uint32_t cspt0                : 3;/* [2:0] */
 521       __IO uint32_t cspt1                : 3;/* [5:3] */
 522       __IO uint32_t cspt2                : 3;/* [8:6] */
 523       __IO uint32_t cspt3                : 3;/* [11:9] */
 524       __IO uint32_t cspt4                : 3;/* [14:12] */
 525       __IO uint32_t cspt5                : 3;/* [17:15] */
 526       __IO uint32_t cspt6                : 3;/* [20:18] */
 527       __IO uint32_t cspt7                : 3;/* [23:21] */
 528       __IO uint32_t cspt8                : 3;/* [26:24] */
 529       __IO uint32_t cspt9                : 3;/* [29:27] */
 530       __IO uint32_t reserved1            : 2;/* [31:30] */
 531     } spt2_bit;
 532   };
 533
 534   /**
 535   * @brief adc pcdto1 register, offset:0x14
 536   */
 537   union
 538   {
 539     __IO uint32_t pcdto1;
 540     struct
 541     {
 542       __IO uint32_t pcdto1               : 12; /* [11:0] */
 543       __IO uint32_t reserved1            : 20; /* [31:12] */
 544     } pcdto1_bit;
 545   };
 546
 547   /**
 548   * @brief adc pcdto2 register, offset:0x18
 549   */
 550   union
 551   {
 552     __IO uint32_t pcdto2;
 553     struct
 554     {
 555       __IO uint32_t pcdto2               : 12; /* [11:0] */
 556       __IO uint32_t reserved1            : 20; /* [31:12] */
 557     } pcdto2_bit;
 558   };
 559
 560   /**
 561   * @brief adc pcdto3 register, offset:0x1C
 562   */
 563   union
 564   {
 565     __IO uint32_t pcdto3;
 566     struct
 567     {
 568       __IO uint32_t pcdto3               : 12; /* [11:0] */
 569       __IO uint32_t reserved1            : 20; /* [31:12] */
 570     } pcdto3_bit;
 571   };
 572
 573   /**
 574   * @brief adc pcdto4 register, offset:0x20
 575   */
 576   union
 577   {
 578     __IO uint32_t pcdto4;
 579     struct
 580     {
 581       __IO uint32_t pcdto4               : 12; /* [11:0] */
 582       __IO uint32_t reserved1            : 20; /* [31:12] */
 583     } pcdto4_bit;
 584   };
 585
 586   /**
 587   * @brief adc vmhb register, offset:0x24
 588   */
 589   union
 590   {
 591     __IO uint32_t vmhb;
 592     struct
 593     {
 594       __IO uint32_t vmhb                 : 12; /* [11:0] */
 595       __IO uint32_t reserved1            : 20; /* [31:12] */
 596     } vmhb_bit;
 597   };
 598
 599   /**
 600   * @brief adc vmlb register, offset:0x28
 601   */
 602   union
 603   {
 604     __IO uint32_t vmlb;
 605     struct
 606     {
 607       __IO uint32_t vmlb                 : 12; /* [11:0] */
 608       __IO uint32_t reserved1            : 20; /* [31:12] */
 609     } vmlb_bit;
 610   };
 611
 612   /**
 613   * @brief adc osq1 register, offset:0x2C
 614   */
 615   union
 616   {
 617     __IO uint32_t osq1;
 618     struct
 619     {
 620       __IO uint32_t osn13                : 5; /* [4:0] */
 621       __IO uint32_t osn14                : 5; /* [9:5] */
 622       __IO uint32_t osn15                : 5; /* [14:10] */
 623       __IO uint32_t osn16                : 5; /* [19:15] */
 624       __IO uint32_t oclen                : 4; /* [23:20] */
 625       __IO uint32_t reserved1            : 8; /* [31:24] */
 626     } osq1_bit;
 627   };
 628
 629   /**
 630   * @brief adc osq2 register, offset:0x30
 631   */
 632   union
 633   {
 634     __IO uint32_t osq2;
 635     struct
 636     {
 637       __IO uint32_t osn7                 : 5; /* [4:0] */
 638       __IO uint32_t osn8                 : 5; /* [9:5] */
 639       __IO uint32_t osn9                 : 5; /* [14:10] */
 640       __IO uint32_t osn10                : 5; /* [19:15] */
 641       __IO uint32_t osn11                : 5; /* [24:20] */
 642       __IO uint32_t osn12                : 5; /* [29:25] */
 643       __IO uint32_t reserved1            : 2; /* [31:30] */
 644     } osq2_bit;
 645   };
 646
 647   /**
 648   * @brief adc osq3 register, offset:0x34
 649   */
 650   union
 651   {
 652     __IO uint32_t osq3;
 653     struct
 654     {
 655       __IO uint32_t osn1                 : 5; /* [4:0] */
 656       __IO uint32_t osn2                 : 5; /* [9:5] */
 657       __IO uint32_t osn3                 : 5; /* [14:10] */
 658       __IO uint32_t osn4                 : 5; /* [19:15] */
 659       __IO uint32_t osn5                 : 5; /* [24:20] */
 660       __IO uint32_t osn6                 : 5; /* [29:25] */
 661       __IO uint32_t reserved1            : 2; /* [31:30] */
 662     } osq3_bit;
 663   };
 664
 665   /**
 666   * @brief adc psq register, offset:0x38
 667   */
 668   union
 669   {
 670     __IO uint32_t psq;
 671     struct
 672     {
 673       __IO uint32_t psn1                 : 5; /* [4:0] */
 674       __IO uint32_t psn2                 : 5; /* [9:5] */
 675       __IO uint32_t psn3                 : 5; /* [14:10] */
 676       __IO uint32_t psn4                 : 5; /* [19:15] */
 677       __IO uint32_t pclen                : 2; /* [21:20] */
 678       __IO uint32_t reserved1            : 10;/* [31:22] */
 679     } psq_bit;
 680   };
 681
 682   /**
 683   * @brief adc pdt1 register, offset:0x3C
 684   */
 685   union
 686   {
 687     __IO uint32_t pdt1;
 688     struct
 689     {
 690       __IO uint32_t pdt1                 : 16; /* [15:0] */
 691       __IO uint32_t reserved1            : 16; /* [31:16] */
 692     } pdt1_bit;
 693   };
 694
 695   /**
 696   * @brief adc pdt2 register, offset:0x40
 697   */
 698   union
 699   {
 700     __IO uint32_t pdt2;
 701     struct
 702     {
 703       __IO uint32_t pdt2                 : 16; /* [15:0] */
 704       __IO uint32_t reserved1            : 16; /* [31:16] */
 705     } pdt2_bit;
 706   };
 707
 708   /**
 709   * @brief adc pdt3 register, offset:0x44
 710   */
 711   union
 712   {
 713     __IO uint32_t pdt3;
 714     struct
 715     {
 716       __IO uint32_t pdt3                 : 16; /* [15:0] */
 717       __IO uint32_t reserved1            : 16; /* [31:16] */
 718     } pdt3_bit;
 719   };
 720
 721   /**
 722   * @brief adc pdt4 register, offset:0x48
 723   */
 724   union
 725   {
 726     __IO uint32_t pdt4;
 727     struct
 728     {
 729       __IO uint32_t pdt4                 : 16; /* [15:0] */
 730       __IO uint32_t reserved1            : 16; /* [31:16] */
 731     } pdt4_bit;
 732   };
 733
 734   /**
 735   * @brief adc odt register, offset:0x4C
 736   */
 737   union
 738   {
 739     __IO uint32_t odt;
 740     struct
 741     {
 742       __IO uint32_t odt                  : 16; /* [15:0] */
 743       __IO uint32_t reserved1            : 16; /* [31:16] */
 744     } odt_bit;
 745   };
 746
 747   __IO uint32_t reserved1[12];
 748
 749   /**
 750   * @brief adc ovsp register, offset:0x80
 751   */
 752   union
 753   {
 754     __IO uint32_t ovsp;
 755     struct
 756     {
 757       __IO uint32_t oosen                : 1; /* [0] */
 758       __IO uint32_t posen                : 1; /* [1] */
 759       __IO uint32_t osrsel               : 3; /* [4:2] */
 760       __IO uint32_t osssel               : 4; /* [8:5] */
 761       __IO uint32_t oostren              : 1; /* [9] */
 762       __IO uint32_t oosrsel              : 1; /* [10] */
 763       __IO uint32_t reserved1            : 21; /* [31:11] */
 764     } ovsp_bit;
 765   };
 766
 767   __IO uint32_t reserved2[12];
 768
 769   /**
 770   * @brief adc calval register, offset:0xB4
 771   */
 772   union
 773   {
 774     __IO uint32_t calval;
 775     struct
 776     {
 777       __IO uint32_t calval               : 7; /* [6:0] */
 778       __IO uint32_t reserved1            : 25; /* [31:7] */
 779     } calval_bit;
 780   };
 781 } adc_type;
 782
 783 /**
 784   * @brief type define adc register all
 785   */
 786 typedef struct
 787 {
 788
 789   /**
 790     * @brief adc csts register, offset:0x00
 791     */
 792   union
 793   {
 794     __IO uint32_t csts;
 795     struct
 796     {
 797       __IO uint32_t vmor1                : 1; /* [0] */
 798       __IO uint32_t occe1                : 1; /* [1] */
 799       __IO uint32_t pcce1                : 1; /* [2] */
 800       __IO uint32_t pccs1                : 1; /* [3] */
 801       __IO uint32_t occs1                : 1; /* [4] */
 802       __IO uint32_t occo1                : 1; /* [5] */
 803       __IO uint32_t rdy1                 : 1; /* [6] */
 804       __IO uint32_t reserved1            : 1; /* [7] */
 805       __IO uint32_t vmor2                : 1; /* [8] */
 806       __IO uint32_t occe2                : 1; /* [9] */
 807       __IO uint32_t pcce2                : 1; /* [10] */
 808       __IO uint32_t pccs2                : 1; /* [11] */
 809       __IO uint32_t occs2                : 1; /* [12] */
 810       __IO uint32_t occo2                : 1; /* [13] */
 811       __IO uint32_t rdy2                 : 1; /* [14] */
 812       __IO uint32_t reserved2            : 1; /* [15] */
 813       __IO uint32_t vmor3                : 1; /* [16] */
 814       __IO uint32_t occe3                : 1; /* [17] */
 815       __IO uint32_t pcce3                : 1; /* [18] */
 816       __IO uint32_t pccs3                : 1; /* [19] */
 817       __IO uint32_t occs3                : 1; /* [20] */
 818       __IO uint32_t occo3                : 1; /* [21] */
 819       __IO uint32_t rdy3                 : 1; /* [22] */
 820       __IO uint32_t reserved3            : 9; /* [31:23] */
 821     } csts_bit;
 822   };
 823
 824   /**
 825     * @brief adc cctrl register, offset:0x04
 826     */
 827   union
 828   {
 829     __IO uint32_t cctrl;
 830     struct
 831     {
 832       __IO uint32_t mssel                : 5; /* [4_0] */
 833       __IO uint32_t reserved1            : 3; /* [7:5] */
 834       __IO uint32_t asisel               : 4; /* [11:8] */
 835       __IO uint32_t reserved2            : 1; /* [12] */
 836       __IO uint32_t msdrcen              : 1; /* [13] */
 837       __IO uint32_t msdmasel_l           : 2; /* [15:14] */
 838       __IO uint32_t adcdiv               : 4; /* [19:16] */
 839       __IO uint32_t reserved3            : 2; /* [21:20] */
 840       __IO uint32_t vbaten               : 1; /* [22] */
 841       __IO uint32_t itsrven              : 1; /* [23] */
 842       __IO uint32_t reserved4            : 4; /* [27:24] */
 843       __IO uint32_t msdmasel_h           : 1; /* [28] */
 844       __IO uint32_t reserved5            : 3; /* [31:29] */
 845     } cctrl_bit;
 846   };
 847
 848   /**
 849   * @brief adc codt register, offset:0x08
 850   */
 851   union
 852   {
 853     __IO uint32_t codt;
 854     struct
 855     {
 856       __IO uint32_t codtl                : 16; /* [15:0] */
 857       __IO uint32_t codth                : 16; /* [31:16] */
 858     } codt_bit;
 859   };
 860 } adccom_type;
 861
 862 /**
 863   * @}
 864   */
 865
 866 #define ADC1                             ((adc_type *) ADC1_BASE)
 867 #define ADC2                             ((adc_type *) ADC2_BASE)
 868 #define ADC3                             ((adc_type *) ADC3_BASE)
 869 #define ADCCOM                           ((adccom_type *) ADCCOM_BASE)
 870
 871 /** @defgroup ADC_exported_functions
 872   * @{
 873   */
 874
 875 void adc_reset(void);
 876 void adc_enable(adc_type *adc_x, confirm_state new_state);
 877 void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
 878 void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
 879 void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
 880 void adc_common_config(adc_common_config_type *adc_common_struct);
 881 void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
 882 void adc_voltage_battery_enable(confirm_state new_state);
 883 void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
 884 void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
 885 void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
 886 void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
 887 void adc_calibration_init(adc_type *adc_x);
 888 flag_status adc_calibration_init_status_get(adc_type *adc_x);
 889 void adc_calibration_start(adc_type *adc_x);
 890 flag_status adc_calibration_status_get(adc_type *adc_x);
 891 void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
 892 void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
 893 void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
 894 void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
 895 void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
 896 void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
 897 void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
 898 void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
 899 void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
 900 void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
 901 void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
 902 void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
 903 void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
 904 void adc_conversion_stop(adc_type *adc_x);
 905 flag_status adc_conversion_stop_status_get(adc_type *adc_x);
 906 void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
 907 void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
 908 flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
 909 void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
 910 flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
 911 uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
 912 uint32_t adc_combine_ordinary_conversion_data_get(void);
 913 uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
 914 flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
 915 void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
 916 void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
 917 void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
 918 void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
 919 void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
 920 void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
 921
 922 /**
 923   * @}
 924   */
 925
 926 /**
 927   * @}
 928   */
 929
 930 /**
 931   * @}
 932   */
 933
 934 #ifdef __cplusplus
 935 }
 936 #endif
 937
 938 #endif